From f45f55c4bbf8a9f9c607e5f6013abac60427e3f7 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 10 Aug 2014 04:10:23 +1000 Subject: [PATCH] drm/nouveau: remove (most) hardcoded object handle usage The PFIFO<->EVO sync buffers will be fixed up later when inter-channel sync in general is improved. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_abi16.c | 2 +- drivers/gpu/drm/nouveau/nouveau_bo.c | 10 +++---- drivers/gpu/drm/nouveau/nouveau_chan.c | 4 +-- drivers/gpu/drm/nouveau/nouveau_dma.h | 16 +---------- drivers/gpu/drm/nouveau/nv04_fbcon.c | 36 ++++++++++++------------- drivers/gpu/drm/nouveau/nv17_fence.c | 5 ++-- drivers/gpu/drm/nouveau/nv50_display.c | 16 +++++------ drivers/gpu/drm/nouveau/nv50_fbcon.c | 10 +++---- drivers/gpu/drm/nouveau/nvc0_fbcon.c | 4 +-- 9 files changed, 45 insertions(+), 58 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c index ae794625a5b..dbba603d50c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -301,7 +301,7 @@ nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS) if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { init->subchan[0].handle = 0x00000000; init->subchan[0].grclass = 0x0000; - init->subchan[1].handle = NvSw; + init->subchan[1].handle = chan->chan->nvsw.handle; init->subchan[1].grclass = 0x506e; init->nr_subchan = 2; } diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index d222875a58d..23146ce5352 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -765,9 +765,9 @@ nv50_bo_move_init(struct nouveau_channel *chan, u32 handle) BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); OUT_RING (chan, handle); BEGIN_NV04(chan, NvSubCopy, 0x0180, 3); - OUT_RING (chan, NvNotify0); - OUT_RING (chan, NvDmaFB); - OUT_RING (chan, NvDmaFB); + OUT_RING (chan, chan->drm->ntfy.handle); + OUT_RING (chan, chan->vram.handle); + OUT_RING (chan, chan->vram.handle); } return ret; @@ -854,7 +854,7 @@ nv04_bo_move_init(struct nouveau_channel *chan, u32 handle) BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); OUT_RING (chan, handle); BEGIN_NV04(chan, NvSubCopy, 0x0180, 1); - OUT_RING (chan, NvNotify0); + OUT_RING (chan, chan->drm->ntfy.handle); } return ret; @@ -866,7 +866,7 @@ nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, { if (mem->mem_type == TTM_PL_TT) return NvDmaTT; - return NvDmaFB; + return chan->vram.handle; } static int diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index 2072518f93f..676b1b9a308 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -335,7 +335,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) /* allocate software object class (used for fences on <= nv05) */ if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { - ret = nvif_object_init(chan->object, NULL, NvSw, 0x006e, + ret = nvif_object_init(chan->object, NULL, 0x006e, 0x006e, NULL, 0, &chan->nvsw); if (ret) return ret; @@ -349,7 +349,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) return ret; BEGIN_NV04(chan, NvSubSw, 0x0000, 1); - OUT_RING (chan, NvSw); + OUT_RING (chan, chan->nvsw.handle); FIRE_RING (chan); } diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index 28757c3f943..8da0a272c45 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -58,28 +58,14 @@ enum { FermiSw = 5, /* DO NOT CHANGE (well.. 6/7 will work...) */ }; -/* Object handles. */ +/* Object handles - for stuff that's doesn't use handle == oclass. */ enum { - NvM2MF = 0x80000001, NvDmaFB = 0x80000002, NvDmaTT = 0x80000003, NvNotify0 = 0x80000006, - Nv2D = 0x80000007, - NvCtxSurf2D = 0x80000008, - NvRop = 0x80000009, - NvImagePatt = 0x8000000a, - NvClipRect = 0x8000000b, - NvGdiRect = 0x8000000c, - NvImageBlit = 0x8000000d, - NvSw = 0x8000000e, NvSema = 0x8000000f, NvEvoSema0 = 0x80000010, NvEvoSema1 = 0x80000011, - NvNotify1 = 0x80000012, - - /* G80+ display objects */ - NvEvoVRAM = 0x01000000, - NvEvoSync = 0xcafe0000 }; #define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039 diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c index b8ab117a846..3d6735cbddf 100644 --- a/drivers/gpu/drm/nouveau/nv04_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c @@ -173,33 +173,33 @@ nv04_fbcon_accel_init(struct fb_info *info) return -EINVAL; } - ret = nvif_object_init(chan->object, NULL, NvCtxSurf2D, + ret = nvif_object_init(chan->object, NULL, 0x0062, device->info.family >= NV_DEVICE_INFO_V0_CELSIUS ? 0x0062 : 0x0042, NULL, 0, &nfbdev->surf2d); if (ret) return ret; - ret = nvif_object_init(chan->object, NULL, NvClipRect, 0x0019, NULL, 0, + ret = nvif_object_init(chan->object, NULL, 0x0019, 0x0019, NULL, 0, &nfbdev->clip); if (ret) return ret; - ret = nvif_object_init(chan->object, NULL, NvRop, 0x0043, NULL, 0, + ret = nvif_object_init(chan->object, NULL, 0x0043, 0x0043, NULL, 0, &nfbdev->rop); if (ret) return ret; - ret = nvif_object_init(chan->object, NULL, NvImagePatt, 0x0044, NULL, 0, + ret = nvif_object_init(chan->object, NULL, 0x0044, 0x0044, NULL, 0, &nfbdev->patt); if (ret) return ret; - ret = nvif_object_init(chan->object, NULL, NvGdiRect, 0x004a, NULL, 0, + ret = nvif_object_init(chan->object, NULL, 0x004a, 0x004a, NULL, 0, &nfbdev->gdi); if (ret) return ret; - ret = nvif_object_init(chan->object, NULL, NvImageBlit, + ret = nvif_object_init(chan->object, NULL, 0x005f, device->info.chipset >= 0x11 ? 0x009f : 0x005f, NULL, 0, &nfbdev->blit); if (ret) @@ -211,10 +211,10 @@ nv04_fbcon_accel_init(struct fb_info *info) } BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); - OUT_RING(chan, NvCtxSurf2D); + OUT_RING(chan, nfbdev->surf2d.handle); BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0184, 2); - OUT_RING(chan, NvDmaFB); - OUT_RING(chan, NvDmaFB); + OUT_RING(chan, chan->vram.handle); + OUT_RING(chan, chan->vram.handle); BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 4); OUT_RING(chan, surface_fmt); OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16)); @@ -222,12 +222,12 @@ nv04_fbcon_accel_init(struct fb_info *info) OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); - OUT_RING(chan, NvRop); + OUT_RING(chan, nfbdev->rop.handle); BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 1); OUT_RING(chan, 0x55); BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); - OUT_RING(chan, NvImagePatt); + OUT_RING(chan, nfbdev->patt.handle); BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 8); OUT_RING(chan, pattern_fmt); #ifdef __BIG_ENDIAN @@ -243,15 +243,15 @@ nv04_fbcon_accel_init(struct fb_info *info) OUT_RING(chan, ~0); BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); - OUT_RING(chan, NvClipRect); + OUT_RING(chan, nfbdev->clip.handle); BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 2); OUT_RING(chan, 0); OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual); BEGIN_NV04(chan, NvSubImageBlit, 0x0000, 1); - OUT_RING(chan, NvImageBlit); + OUT_RING(chan, nfbdev->blit.handle); BEGIN_NV04(chan, NvSubImageBlit, 0x019c, 1); - OUT_RING(chan, NvCtxSurf2D); + OUT_RING(chan, nfbdev->surf2d.handle); BEGIN_NV04(chan, NvSubImageBlit, 0x02fc, 1); OUT_RING(chan, 3); if (device->info.chipset >= 0x11 /*XXX: oclass == 0x009f*/) { @@ -262,12 +262,12 @@ nv04_fbcon_accel_init(struct fb_info *info) } BEGIN_NV04(chan, NvSubGdiRect, 0x0000, 1); - OUT_RING(chan, NvGdiRect); + OUT_RING(chan, nfbdev->gdi.handle); BEGIN_NV04(chan, NvSubGdiRect, 0x0198, 1); - OUT_RING(chan, NvCtxSurf2D); + OUT_RING(chan, nfbdev->surf2d.handle); BEGIN_NV04(chan, NvSubGdiRect, 0x0188, 2); - OUT_RING(chan, NvImagePatt); - OUT_RING(chan, NvRop); + OUT_RING(chan, nfbdev->patt.handle); + OUT_RING(chan, nfbdev->rop.handle); BEGIN_NV04(chan, NvSubGdiRect, 0x0304, 1); OUT_RING(chan, 1); BEGIN_NV04(chan, NvSubGdiRect, 0x0300, 1); diff --git a/drivers/gpu/drm/nouveau/nv17_fence.c b/drivers/gpu/drm/nouveau/nv17_fence.c index 4dde5320db0..5056131731f 100644 --- a/drivers/gpu/drm/nouveau/nv17_fence.c +++ b/drivers/gpu/drm/nouveau/nv17_fence.c @@ -35,6 +35,7 @@ nv17_fence_sync(struct nouveau_fence *fence, { struct nouveau_cli *cli = (void *)nvif_client(&prev->device->base); struct nv10_fence_priv *priv = chan->drm->fence; + struct nv10_fence_chan *fctx = chan->fence; u32 value; int ret; @@ -49,7 +50,7 @@ nv17_fence_sync(struct nouveau_fence *fence, ret = RING_SPACE(prev, 5); if (!ret) { BEGIN_NV04(prev, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4); - OUT_RING (prev, NvSema); + OUT_RING (prev, fctx->sema.handle); OUT_RING (prev, 0); OUT_RING (prev, value + 0); OUT_RING (prev, value + 1); @@ -58,7 +59,7 @@ nv17_fence_sync(struct nouveau_fence *fence, if (!ret && !(ret = RING_SPACE(chan, 5))) { BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4); - OUT_RING (chan, NvSema); + OUT_RING (chan, fctx->sema.handle); OUT_RING (chan, 0); OUT_RING (chan, value + 1); OUT_RING (chan, value + 2); diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index ca8c1db0ccb..6ae03044c3d 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -175,7 +175,7 @@ nv50_dmac_create(struct nvif_object *disp, u32 bclass, u8 head, if (ret) return ret; - ret = nvif_object_init(&dmac->base.user, NULL, NvEvoSync, + ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000000, NV_DMA_IN_MEMORY_CLASS, &(struct nv_dma_class) { .flags = NV_DMA_TARGET_VRAM | @@ -187,7 +187,7 @@ nv50_dmac_create(struct nvif_object *disp, u32 bclass, u8 head, if (ret) return ret; - ret = nvif_object_init(&dmac->base.user, NULL, NvEvoVRAM, + ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000001, NV_DMA_IN_MEMORY_CLASS, &(struct nv_dma_class) { .flags = NV_DMA_TARGET_VRAM | @@ -482,7 +482,7 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, evo_data(push, sync->addr); evo_data(push, sync->data++); evo_data(push, sync->data); - evo_data(push, NvEvoSync); + evo_data(push, sync->base.sync.handle); evo_mthd(push, 0x00a0, 2); evo_data(push, 0x00000000); evo_data(push, 0x00000000); @@ -763,13 +763,13 @@ nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc) evo_data(push, 0x85000000); evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1); - evo_data(push, NvEvoVRAM); + evo_data(push, mast->base.vram.handle); } else { evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2); evo_data(push, 0x85000000); evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); - evo_data(push, NvEvoVRAM); + evo_data(push, mast->base.vram.handle); } evo_kick(push, mast); } @@ -887,7 +887,7 @@ nv50_crtc_commit(struct drm_crtc *crtc) evo_data(push, 0xc0000000); evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1); - evo_data(push, NvEvoVRAM); + evo_data(push, mast->base.vram.handle); } else { evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); evo_data(push, nv_crtc->fb.handle); @@ -897,7 +897,7 @@ nv50_crtc_commit(struct drm_crtc *crtc) evo_data(push, 0x00000000); evo_data(push, 0x00000000); evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); - evo_data(push, NvEvoVRAM); + evo_data(push, mast->base.vram.handle); evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1); evo_data(push, 0xffffff00); } @@ -2210,7 +2210,7 @@ nv50_display_init(struct drm_device *dev) } evo_mthd(push, 0x0088, 1); - evo_data(push, NvEvoSync); + evo_data(push, nv50_mast(dev)->base.sync.handle); evo_kick(push, nv50_mast(dev)); return 0; } diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c index a92008c9d20..394c89abcc9 100644 --- a/drivers/gpu/drm/nouveau/nv50_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c @@ -183,7 +183,7 @@ nv50_fbcon_accel_init(struct fb_info *info) return -EINVAL; } - ret = nvif_object_init(chan->object, NULL, Nv2D, 0x502d, NULL, 0, + ret = nvif_object_init(chan->object, NULL, 0x502d, 0x502d, NULL, 0, &nfbdev->twod); if (ret) return ret; @@ -195,11 +195,11 @@ nv50_fbcon_accel_init(struct fb_info *info) } BEGIN_NV04(chan, NvSub2D, 0x0000, 1); - OUT_RING(chan, Nv2D); + OUT_RING(chan, nfbdev->twod.handle); BEGIN_NV04(chan, NvSub2D, 0x0184, 3); - OUT_RING(chan, NvDmaFB); - OUT_RING(chan, NvDmaFB); - OUT_RING(chan, NvDmaFB); + OUT_RING(chan, chan->vram.handle); + OUT_RING(chan, chan->vram.handle); + OUT_RING(chan, chan->vram.handle); BEGIN_NV04(chan, NvSub2D, 0x0290, 1); OUT_RING(chan, 0); BEGIN_NV04(chan, NvSub2D, 0x0888, 1); diff --git a/drivers/gpu/drm/nouveau/nvc0_fbcon.c b/drivers/gpu/drm/nouveau/nvc0_fbcon.c index 93e7b697ee9..61246677e8d 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fbcon.c +++ b/drivers/gpu/drm/nouveau/nvc0_fbcon.c @@ -156,7 +156,7 @@ nvc0_fbcon_accel_init(struct fb_info *info) struct nouveau_channel *chan = drm->channel; int ret, format; - ret = nvif_object_init(chan->object, NULL, Nv2D, 0x902d, NULL, 0, + ret = nvif_object_init(chan->object, NULL, 0x902d, 0x902d, NULL, 0, &nfbdev->twod); if (ret) return ret; @@ -196,7 +196,7 @@ nvc0_fbcon_accel_init(struct fb_info *info) } BEGIN_NVC0(chan, NvSub2D, 0x0000, 1); - OUT_RING (chan, 0x0000902d); + OUT_RING (chan, nfbdev->twod.handle); BEGIN_NVC0(chan, NvSub2D, 0x0290, 1); OUT_RING (chan, 0); BEGIN_NVC0(chan, NvSub2D, 0x0888, 1); -- 2.41.0