From dd202c6dd612beecf87b8b85c2f09b23f77364a2 Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Thu, 9 Feb 2012 10:15:18 +0100 Subject: [PATCH] drm/i915: use gtfifodbg Add register definitions for GTFIFODBG, and clear it during init time to make sure state is correct. This register tells us if either a read, or a write occurred while the fifo was full. It seems like bit 2 is an OR of bit 0 and bit 1, so we check that as well, but the documents are not quite clear. Reviewed-by: Chris Wilson Reviewed-by (v1): Eugeni Dodonov Signed-off-by: Ben Widawsky Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ drivers/gpu/drm/i915/intel_display.c | 8 ++++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7b4477cb165..5c62b788c25 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3703,6 +3703,12 @@ #define ECOBUS 0xa180 #define FORCEWAKE_MT_ENABLE (1<<5) +#define GTFIFODBG 0x120000 +#define GT_FIFO_CPU_ERROR_MASK 7 +#define GT_FIFO_OVFERR (1<<2) +#define GT_FIFO_IAWRERR (1<<1) +#define GT_FIFO_IARDERR (1<<0) + #define GT_FIFO_FREE_ENTRIES 0x120008 #define GT_FIFO_NUM_RESERVED_ENTRIES 20 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7fae6917bea..db7ccbbb97c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8241,6 +8241,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); u32 pcu_mbox, rc6_mask = 0; + u32 gtfifodbg; int cur_freq, min_freq, max_freq; int i; @@ -8252,6 +8253,13 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) */ I915_WRITE(GEN6_RC_STATE, 0); mutex_lock(&dev_priv->dev->struct_mutex); + + /* Clear the DBG now so we don't confuse earlier errors */ + if ((gtfifodbg = I915_READ(GTFIFODBG))) { + DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); + I915_WRITE(GTFIFODBG, gtfifodbg); + } + gen6_gt_force_wake_get(dev_priv); /* disable the counters and set deterministic thresholds */ -- 2.41.0