From c68c29c04c4ff11e51d98b2225c1e3b37ed22996 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 24 Feb 2014 14:26:44 +1000 Subject: [PATCH] drm/gm107/disp: initial implementation Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/Makefile | 1 + .../gpu/drm/nouveau/core/engine/disp/gm107.c | 101 ++++++++++++++++++ .../gpu/drm/nouveau/core/engine/dmaobj/nvd0.c | 3 + .../gpu/drm/nouveau/core/include/core/class.h | 12 +++ .../drm/nouveau/core/include/engine/disp.h | 1 + 5 files changed, 118 insertions(+) create mode 100644 drivers/gpu/drm/nouveau/core/engine/disp/gm107.c diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile index 266551b2703..e3a224fecad 100644 --- a/drivers/gpu/drm/nouveau/Makefile +++ b/drivers/gpu/drm/nouveau/Makefile @@ -221,6 +221,7 @@ nouveau-y += core/engine/disp/nva3.o nouveau-y += core/engine/disp/nvd0.o nouveau-y += core/engine/disp/nve0.o nouveau-y += core/engine/disp/nvf0.o +nouveau-y += core/engine/disp/gm107.o nouveau-y += core/engine/disp/dacnv50.o nouveau-y += core/engine/disp/dport.o nouveau-y += core/engine/disp/hdanva3.o diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c b/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c new file mode 100644 index 00000000000..cf6f59677b7 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c @@ -0,0 +1,101 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include + +#include + +#include "nv50.h" + +/******************************************************************************* + * Base display object + ******************************************************************************/ + +static struct nouveau_oclass +gm107_disp_sclass[] = { + { GM107_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs }, + { GM107_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs }, + { GM107_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs }, + { GM107_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs }, + { GM107_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs }, + {} +}; + +static struct nouveau_oclass +gm107_disp_base_oclass[] = { + { GM107_DISP_CLASS, &nvd0_disp_base_ofuncs, nvd0_disp_base_omthds }, + {} +}; + +/******************************************************************************* + * Display engine implementation + ******************************************************************************/ + +static int +gm107_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv50_disp_priv *priv; + int heads = nv_rd32(parent, 0x022448); + int ret; + + ret = nouveau_disp_create(parent, engine, oclass, heads, + "PDISP", "display", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_engine(priv)->sclass = gm107_disp_base_oclass; + nv_engine(priv)->cclass = &nv50_disp_cclass; + nv_subdev(priv)->intr = nvd0_disp_intr; + INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor); + priv->sclass = gm107_disp_sclass; + priv->head.nr = heads; + priv->dac.nr = 3; + priv->sor.nr = 4; + priv->dac.power = nv50_dac_power; + priv->dac.sense = nv50_dac_sense; + priv->sor.power = nv50_sor_power; + priv->sor.hda_eld = nvd0_hda_eld; + priv->sor.hdmi = nvd0_hdmi_ctrl; + priv->sor.dp = &nvd0_sor_dp_func; + return 0; +} + +struct nouveau_oclass * +gm107_disp_oclass = &(struct nv50_disp_impl) { + .base.base.handle = NV_ENGINE(DISP, 0x07), + .base.base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = gm107_disp_ctor, + .dtor = _nouveau_disp_dtor, + .init = _nouveau_disp_init, + .fini = _nouveau_disp_fini, + }, + .mthd.core = &nve0_disp_mast_mthd_chan, + .mthd.base = &nvd0_disp_sync_mthd_chan, + .mthd.ovly = &nve0_disp_ovly_mthd_chan, + .mthd.prev = -0x020000, +}.base.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c index 944e73ac485..1cfb3bb9013 100644 --- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c +++ b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c @@ -53,6 +53,9 @@ nvd0_dmaobj_bind(struct nouveau_dmaeng *dmaeng, case NVF0_DISP_MAST_CLASS: case NVF0_DISP_SYNC_CLASS: case NVF0_DISP_OVLY_CLASS: + case GM107_DISP_MAST_CLASS: + case GM107_DISP_SYNC_CLASS: + case GM107_DISP_OVLY_CLASS: break; default: return -EINVAL; diff --git a/drivers/gpu/drm/nouveau/core/include/core/class.h b/drivers/gpu/drm/nouveau/core/include/core/class.h index e71a4325e67..9c0cd73462d 100644 --- a/drivers/gpu/drm/nouveau/core/include/core/class.h +++ b/drivers/gpu/drm/nouveau/core/include/core/class.h @@ -258,6 +258,7 @@ struct nv04_display_scanoutpos { * 9070: NVD0_DISP * 9170: NVE0_DISP * 9270: NVF0_DISP + * 9470: GM107_DISP */ #define NV50_DISP_CLASS 0x00005070 @@ -268,6 +269,7 @@ struct nv04_display_scanoutpos { #define NVD0_DISP_CLASS 0x00009070 #define NVE0_DISP_CLASS 0x00009170 #define NVF0_DISP_CLASS 0x00009270 +#define GM107_DISP_CLASS 0x00009470 #define NV50_DISP_MTHD 0x00000000 #define NV50_DISP_MTHD_HEAD 0x00000003 @@ -342,6 +344,7 @@ struct nv50_display_class { * 907a: NVD0_DISP_CURS * 917a: NVE0_DISP_CURS * 927a: NVF0_DISP_CURS + * 947a: GM107_DISP_CURS */ #define NV50_DISP_CURS_CLASS 0x0000507a @@ -352,6 +355,7 @@ struct nv50_display_class { #define NVD0_DISP_CURS_CLASS 0x0000907a #define NVE0_DISP_CURS_CLASS 0x0000917a #define NVF0_DISP_CURS_CLASS 0x0000927a +#define GM107_DISP_CURS_CLASS 0x0000947a struct nv50_display_curs_class { u32 head; @@ -365,6 +369,7 @@ struct nv50_display_curs_class { * 907b: NVD0_DISP_OIMM * 917b: NVE0_DISP_OIMM * 927b: NVE0_DISP_OIMM + * 947b: GM107_DISP_OIMM */ #define NV50_DISP_OIMM_CLASS 0x0000507b @@ -375,6 +380,7 @@ struct nv50_display_curs_class { #define NVD0_DISP_OIMM_CLASS 0x0000907b #define NVE0_DISP_OIMM_CLASS 0x0000917b #define NVF0_DISP_OIMM_CLASS 0x0000927b +#define GM107_DISP_OIMM_CLASS 0x0000947b struct nv50_display_oimm_class { u32 head; @@ -388,6 +394,7 @@ struct nv50_display_oimm_class { * 907c: NVD0_DISP_SYNC * 917c: NVE0_DISP_SYNC * 927c: NVF0_DISP_SYNC + * 947c: GM107_DISP_SYNC */ #define NV50_DISP_SYNC_CLASS 0x0000507c @@ -398,6 +405,7 @@ struct nv50_display_oimm_class { #define NVD0_DISP_SYNC_CLASS 0x0000907c #define NVE0_DISP_SYNC_CLASS 0x0000917c #define NVF0_DISP_SYNC_CLASS 0x0000927c +#define GM107_DISP_SYNC_CLASS 0x0000947c struct nv50_display_sync_class { u32 pushbuf; @@ -412,6 +420,7 @@ struct nv50_display_sync_class { * 907d: NVD0_DISP_MAST * 917d: NVE0_DISP_MAST * 927d: NVF0_DISP_MAST + * 947d: GM107_DISP_MAST */ #define NV50_DISP_MAST_CLASS 0x0000507d @@ -422,6 +431,7 @@ struct nv50_display_sync_class { #define NVD0_DISP_MAST_CLASS 0x0000907d #define NVE0_DISP_MAST_CLASS 0x0000917d #define NVF0_DISP_MAST_CLASS 0x0000927d +#define GM107_DISP_MAST_CLASS 0x0000947d struct nv50_display_mast_class { u32 pushbuf; @@ -435,6 +445,7 @@ struct nv50_display_mast_class { * 907e: NVD0_DISP_OVLY * 917e: NVE0_DISP_OVLY * 927e: NVF0_DISP_OVLY + * 947e: GM107_DISP_OVLY */ #define NV50_DISP_OVLY_CLASS 0x0000507e @@ -445,6 +456,7 @@ struct nv50_display_mast_class { #define NVD0_DISP_OVLY_CLASS 0x0000907e #define NVE0_DISP_OVLY_CLASS 0x0000917e #define NVF0_DISP_OVLY_CLASS 0x0000927e +#define GM107_DISP_OVLY_CLASS 0x0000947e struct nv50_display_ovly_class { u32 pushbuf; diff --git a/drivers/gpu/drm/nouveau/core/include/engine/disp.h b/drivers/gpu/drm/nouveau/core/include/engine/disp.h index 4bfa3d8a126..fd0c68804de 100644 --- a/drivers/gpu/drm/nouveau/core/include/engine/disp.h +++ b/drivers/gpu/drm/nouveau/core/include/engine/disp.h @@ -45,5 +45,6 @@ extern struct nouveau_oclass *nva3_disp_oclass; extern struct nouveau_oclass *nvd0_disp_oclass; extern struct nouveau_oclass *nve0_disp_oclass; extern struct nouveau_oclass *nvf0_disp_oclass; +extern struct nouveau_oclass *gm107_disp_oclass; #endif -- 2.41.0