From 931272604f69f5d7610d9d319560e6035906dbdf Mon Sep 17 00:00:00 2001 From: leonidk Date: Mon, 26 Jan 2009 10:37:32 +0000 Subject: [PATCH] [MLX4] Fixing WQE Prefetch bug for LSO less than 60 bytes (Cache line-DWORD) Signed-off-by: Alex Naslednikov git-svn-id: svn://openib.tc.cornell.edu/gen1@1883 ad392aa1-c5ef-ae45-8dd8-e69d62a5ef86 --- trunk/hw/mlx4/kernel/bus/ib/qp.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/trunk/hw/mlx4/kernel/bus/ib/qp.c b/trunk/hw/mlx4/kernel/bus/ib/qp.c index 16527d2a..d7528c43 100644 --- a/trunk/hw/mlx4/kernel/bus/ib/qp.c +++ b/trunk/hw/mlx4/kernel/bus/ib/qp.c @@ -1507,10 +1507,17 @@ int mlx4_ib_post_send(struct ib_qp *ibqp, ib_send_wr_t *wr, } #define I64_CACHE_LINE 64 #define OPCODE_INVALID_BIT 6 - // WQE bug treatment for LSO case, when LSO header is large enough - if (unlikely (seglen > I64_CACHE_LINE)) { + // WQE bug treatment for LSO case + // If LSO segment is large enough (exceeds one cache block in size) + // or if it small enough such that S/G element will be placed within the same cache block, + // OPCODE_INVALID_BIT should be on in order to reread this WQE + // More correct solution is + // (unlikely (seglen % I64_CACHE_LINE || seglen % (I64_CACHE_LINE-2) )) + // but it will not be used in order to reduce calculations within Datapath + // If LSO segment consists of 15 DWORDS, S/G elements block will nevertheless start from + // the next cache block + if (unlikely (seglen < I64_CACHE_LINE-4 || seglen > I64_CACHE_LINE )) ctrl->owner_opcode |= cpu_to_be32 ( 1 << OPCODE_INVALID_BIT); - } wqe += seglen; size += seglen / 16; j=1; -- 2.46.0