From: Vijay Kumar <vijaykumar@bravegnu.org>
Date: Mon, 21 Sep 2009 05:53:57 +0000 (+0530)
Subject: Staging: poch: Parameter to enable loopback
X-Git-Tag: v2.6.33-rc1~313^2~106
X-Git-Url: https://openfabrics.org/gitweb/?a=commitdiff_plain;h=dad1740133ffe49ae44044f97e4cbfcb42f037b1;p=~shefty%2Frdma-dev.git

Staging: poch: Parameter to enable loopback

Enable setting of loopback through module parameter.

Signed-off-by: Vijay Kumar <vijaykumar@bravegnu.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
---

diff --git a/drivers/staging/poch/poch.c b/drivers/staging/poch/poch.c
index 1637c281ea3..babd881809a 100644
--- a/drivers/staging/poch/poch.c
+++ b/drivers/staging/poch/poch.c
@@ -252,6 +252,11 @@ module_param(synth_rx, bool, 0600);
 MODULE_PARM_DESC(synth_rx,
 		"Synthesize received values using a counter. Default: No");
 
+static int loopback;
+module_param(loopback, bool, 0600);
+MODULE_PARM_DESC(loopback,
+		"Enable hardware loopback of trasnmitted data. Default: No");
+
 static dev_t poch_first_dev;
 static struct class *poch_cls;
 static DEFINE_IDR(poch_ids);
@@ -830,9 +835,14 @@ static int poch_open(struct inode *inode, struct file *filp)
 
 	if (channel->dir == CHANNEL_DIR_TX) {
 		/* Flush TX FIFO and output data from cardbus. */
-		iowrite32(FPGA_TX_CTL_FIFO_FLUSH
-			  | FPGA_TX_CTL_OUTPUT_CARDBUS,
-			  fpga + FPGA_TX_CTL_REG);
+		u32 ctl_val = 0;
+
+		ctl_val |= FPGA_TX_CTL_FIFO_FLUSH;
+		ctl_val |= FPGA_TX_CTL_OUTPUT_CARDBUS;
+		if (loopback)
+			ctl_val |= FPGA_TX_CTL_LOOPBACK;
+
+		iowrite32(ctl_val, fpga + FPGA_TX_CTL_REG);
 	} else {
 		/* Flush RX FIFO and output data to cardbus. */
 		u32 ctl_val = FPGA_RX_CTL_CONT_CAP | FPGA_RX_CTL_FIFO_FLUSH;