From: Ralf Baechle Date: Thu, 21 Feb 2013 11:51:33 +0000 (+0100) Subject: Merge branch 'mips-next-3.9' of git://git.linux-mips.org/pub/scm/john/linux-john... X-Git-Tag: v3.9-rc1~26^2~1 X-Git-Url: https://openfabrics.org/gitweb/?a=commitdiff_plain;h=8bfc245f9ad7bd4e461179e4e7852ef99b8b6144;p=~emulex%2Finfiniband.git Merge branch 'mips-next-3.9' of git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next --- 8bfc245f9ad7bd4e461179e4e7852ef99b8b6144 diff --cc arch/mips/Kbuild.platforms index 5c088494e04,9a73ce6f4c5..4b597d91a8d --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@@ -18,9 -18,11 +18,10 @@@ platforms += loongson platforms += mti-malta platforms += mti-sead3 platforms += netlogic -platforms += pmc-sierra +platforms += pmcs-msp71xx platforms += pnx833x -platforms += pnx8550 platforms += powertv + platforms += ralink platforms += rb532 platforms += sgi-ip22 platforms += sgi-ip27 diff --cc arch/mips/Kconfig index af4e04fde0b,79ad1d09c25..6fe9a188c49 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@@ -835,8 -863,9 +854,9 @@@ source "arch/mips/jazz/Kconfig source "arch/mips/jz4740/Kconfig" source "arch/mips/lantiq/Kconfig" source "arch/mips/lasat/Kconfig" -source "arch/mips/pmc-sierra/Kconfig" +source "arch/mips/pmcs-msp71xx/Kconfig" source "arch/mips/powertv/Kconfig" + source "arch/mips/ralink/Kconfig" source "arch/mips/sgi-ip27/Kconfig" source "arch/mips/sibyte/Kconfig" source "arch/mips/txx9/Kconfig" diff --cc arch/mips/bcm47xx/nvram.c index c37419c11c9,e63bd5abd9a..cc40b74940f --- a/arch/mips/bcm47xx/nvram.c +++ b/arch/mips/bcm47xx/nvram.c @@@ -3,10 -3,10 +3,10 @@@ * * Copyright (C) 2005 Broadcom Corporation * Copyright (C) 2006 Felix Fietkau - * Copyright (C) 2010-2011 Hauke Mehrtens + * Copyright (C) 2010-2012 Hauke Mehrtens * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ diff --cc arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 8dec938af11,4de18311291..b86a1253a5b --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@@ -312,9 -396,11 +396,11 @@@ #define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) #define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) #define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) -#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) #define AR934X_BOOTSTRAP_DDR1 BIT(0) + #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) + #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) @@@ -362,8 -481,10 +481,10 @@@ #define AR724X_REV_ID_REVISION_MASK 0x3 -#define AR934X_REV_ID_REVISION_MASK 0xf +#define AR934X_REV_ID_REVISION_MASK 0xf + #define QCA955X_REV_ID_REVISION_MASK 0xf + /* * SPI block */ diff --cc arch/mips/include/asm/mips-boards/generic.h index 1465b1193b1,fa188ff08e5..44a09a64160 --- a/arch/mips/include/asm/mips-boards/generic.h +++ b/arch/mips/include/asm/mips-boards/generic.h @@@ -27,16 -20,9 +20,9 @@@ /* * Display register base. */ -#define ASCII_DISPLAY_WORD_BASE 0x1f000410 -#define ASCII_DISPLAY_POS_BASE 0x1f000418 +#define ASCII_DISPLAY_WORD_BASE 0x1f000410 +#define ASCII_DISPLAY_POS_BASE 0x1f000418 - - /* - * Yamon Prom print address. - */ - #define YAMON_PROM_PRINT_ADDR 0x1fc00504 - - /* * Reset register. */ diff --cc arch/mips/include/asm/mipsregs.h index 2145162674b,5df4cda4991..12b70c25906 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@@ -1142,36 -1144,28 +1144,32 @@@ do { /* * Macros to access the floating point coprocessor control registers */ -#define read_32bit_cp1_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - /* gas fails to assemble cfc1 for some archs (octeon).*/ \ - ".set\tmips1\n\t" \ - "cfc1\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ - : "=r" (__res)); \ - __res;}) +#define read_32bit_cp1_register(source) \ +({ \ + int __res; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set reorder \n" \ + " # gas fails to assemble cfc1 for some archs, \n" \ + " # like Octeon. \n" \ + " .set mips1 \n" \ + " cfc1 %0,"STR(source)" \n" \ + " .set pop \n" \ + : "=r" (__res)); \ + __res; \ +}) + #ifdef HAVE_AS_DSP #define rddsp(mask) \ ({ \ - unsigned int __res; \ + unsigned int __dspctl; \ \ __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # rddsp $1, %x1 \n" \ - " .word 0x7c000cb8 | (%x1 << 16) \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__res) \ + " rddsp %0, %x1 \n" \ + : "=r" (__dspctl) \ : "i" (mask)); \ - __res; \ + __dspctl; \ }) #define wrdsp(val, mask) \ diff --cc arch/mips/pci/pci-xlp.c index ad55f2cfeec,dd2d3eb3ad3..653d2db9e0c --- a/arch/mips/pci/pci-xlp.c +++ b/arch/mips/pci/pci-xlp.c @@@ -149,35 -154,29 +154,29 @@@ static struct resource nlm_pci_io_resou }; struct pci_controller nlm_pci_controller = { - .index = 0, - .pci_ops = &nlm_pci_ops, - .mem_resource = &nlm_pci_mem_resource, - .mem_offset = 0x00000000UL, - .io_resource = &nlm_pci_io_resource, - .io_offset = 0x00000000UL, + .index = 0, + .pci_ops = &nlm_pci_ops, + .mem_resource = &nlm_pci_mem_resource, + .mem_offset = 0x00000000UL, + .io_resource = &nlm_pci_io_resource, + .io_offset = 0x00000000UL, }; - static int get_irq_vector(const struct pci_dev *dev) + static struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev) { - /* - * For XLP PCIe, there is an IRQ per Link, find out which - * link the device is on to assign interrupts - */ - if (dev->bus->self == NULL) - return 0; + struct pci_bus *bus, *p; - switch (dev->bus->self->devfn) { - case 0x8: - return PIC_PCIE_LINK_0_IRQ; - case 0x9: - return PIC_PCIE_LINK_1_IRQ; - case 0xa: - return PIC_PCIE_LINK_2_IRQ; - case 0xb: - return PIC_PCIE_LINK_3_IRQ; - } - WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn); - return 0; + /* Find the bridge on bus 0 */ + bus = dev->bus; + for (p = bus->parent; p && p->number != 0; p = p->parent) + bus = p; + + return p ? bus->self : NULL; + } + + static inline int nlm_pci_link_to_irq(int link) + { + return PIC_PCIE_LINK_0_IRQ + link; } int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) @@@ -232,10 -249,29 +249,29 @@@ static int __init pcibios_init(void pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20); /* Extend IO port for memory mapped io */ - ioport_resource.start = 0; + ioport_resource.start = 0; ioport_resource.end = ~0; - xlp_enable_pci_bswap(); + for (n = 0; n < NLM_NR_NODES; n++) { + nodep = nlm_get_node(n); + if (!nodep->coremask) + continue; /* node does not exist */ + + for (link = 0; link < 4; link++) { + pciebase = nlm_get_pcie_base(n, link); + if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff) + continue; + xlp_config_pci_bswap(n, link); + + /* put in intpin and irq - u-boot does not */ + reg = nlm_read_pci_reg(pciebase, 0xf); + reg &= ~0x1fu; + reg |= (1 << 8) | nlm_pci_link_to_irq(link); + nlm_write_pci_reg(pciebase, 0xf, reg); + pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link); + } + } + set_io_port_base(CKSEG1); nlm_pci_controller.io_map_base = CKSEG1;