From: Tushar Behera Date: Thu, 29 Dec 2011 07:48:08 +0000 (+0900) Subject: ARM: EXYNOS: Invert VCLK polarity for framebuffer on ORIGEN X-Git-Url: https://openfabrics.org/gitweb/?a=commitdiff_plain;h=815ed6fc0a4d82bb39ed43d230c4e516214987e7;p=~shefty%2Frdma-dev.git ARM: EXYNOS: Invert VCLK polarity for framebuffer on ORIGEN Framebuffer driver needs to fetch the video data during the rising edge of the VCLK. Otherwise, there are some glitches in the LCD display. Signed-off-by: Tushar Behera Signed-off-by: Kukjin Kim --- diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c index 2b11e046d39..0679b8ad2d1 100644 --- a/arch/arm/mach-exynos/mach-origen.c +++ b/arch/arm/mach-exynos/mach-origen.c @@ -597,7 +597,8 @@ static struct s3c_fb_pd_win origen_fb_win0 = { static struct s3c_fb_platdata origen_lcd_pdata __initdata = { .win[0] = &origen_fb_win0, .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | + VIDCON1_INV_VCLK, .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, };