From: Stephen Warren <swarren@nvidia.com>
Date: Mon, 10 Sep 2012 23:02:45 +0000 (-0600)
Subject: ARM: tegra: fix overflow in tegra20_pll_clk_round_rate()
X-Git-Url: https://openfabrics.org/gitweb/?a=commitdiff_plain;h=7a74a4436b20980f8e19138e857bc7e39db5ad4b;p=~shefty%2Frdma-dev.git

ARM: tegra: fix overflow in tegra20_pll_clk_round_rate()

32-bit math isn't enough when e.g. *prate=12000000, and sel->n=1000.
Use 64-bit math to prevent this.

Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---

diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
index b9124afcca1..d9ce0087f6a 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.c
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -789,7 +789,7 @@ static long tegra20_pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
 	struct clk_tegra *c = to_clk_tegra(hw);
 	const struct clk_pll_freq_table *sel;
 	unsigned long input_rate = *prate;
-	unsigned long output_rate = *prate;
+	u64 output_rate = *prate;
 	int mul;
 	int div;