From: Ben Skeggs Date: Wed, 26 Sep 2012 02:43:10 +0000 (+1000) Subject: drm/nvc0/ltcg: mask off intr 0x10 X-Git-Tag: v3.6~10^2~3^2 X-Git-Url: https://openfabrics.org/gitweb/?a=commitdiff_plain;h=79eee7aa0d4de5a42331c63d3c7c735248b53d0c;p=~emulex%2Finfiniband.git drm/nvc0/ltcg: mask off intr 0x10 NVIDIA do that at startup too on Fermi, so perhaps the heap of 0x10 intrs we receive are normal and we can ignore them. On Kepler NVIDIA *don't* do this, but the hardware appears to come up with the bit masked off by default - so that's probably why :) This should silence some interrupt spam seen on Fermi+ boards. Backported patch from reworked nouveau kernel tree. Signed-off-by: Ben Skeggs --- diff --git a/drivers/gpu/drm/nouveau/nvc0_fb.c b/drivers/gpu/drm/nouveau/nvc0_fb.c index f704e942372..f376c39310d 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fb.c +++ b/drivers/gpu/drm/nouveau/nvc0_fb.c @@ -124,6 +124,7 @@ nvc0_fb_init(struct drm_device *dev) priv = dev_priv->engine.fb.priv; nv_wr32(dev, 0x100c10, priv->r100c10 >> 8); + nv_mask(dev, 0x17e820, 0x00100000, 0x00000000); /* NV_PLTCG_INTR_EN */ return 0; }