From: Rodrigo Vivi Date: Mon, 6 May 2013 22:37:34 +0000 (-0300) Subject: drm/i915: IVB FBC WaFbcAsynchFlipDisableFbcQueue X-Git-Tag: v3.11-rc1~65^2~131^2~13 X-Git-Url: https://openfabrics.org/gitweb/?a=commitdiff_plain;h=30ca7c6f97e266d122b03261f75f530d5c83608b;p=~emulex%2Finfiniband.git drm/i915: IVB FBC WaFbcAsynchFlipDisableFbcQueue Display register 42000h bit 22 must be set to 1b for the entire time that Frame Buffer Compression is enabled. Reviewed-by: Ville Syrjälä Signed-off-by: Rodrigo Vivi Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e398963797a..48283167c19 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -268,6 +268,8 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval) IVB_DPFC_CTL_FENCE_EN | intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT); + /* WaFbcAsynchFlipDisableFbcQueue */ + I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS); I915_WRITE(SNB_DPFC_CTL_SA, SNB_CPU_FENCE_ENABLE | obj->fence_reg); I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);