From: Guennadi Liakhovetski Date: Wed, 12 Dec 2012 14:38:17 +0000 (+0100) Subject: mmc: sh_mmcif: fix I/O errors X-Git-Tag: v3.9-rc1~78^2~72 X-Git-Url: https://openfabrics.org/gitweb/?a=commitdiff_plain;h=276bc96b2abfa2a6bb219aa4eda13c4c331c53eb;p=~emulex%2Finfiniband.git mmc: sh_mmcif: fix I/O errors The INT_BUFWEN IRQ often arrives with other bits set too. If they are not cleared, an additional IRQ can be triggered, sometimes also after the MMC request has already been completed. This leads to block I/O errors. Earlier Teppei Kamijou also observed these additional interrupts and proposed to explicitly wait for them. This patch chooses an alternative approach of clearing all active bits immediately, when processing the main interrupt. Reported-by: Teppei Kamijou Signed-off-by: Guennadi Liakhovetski Signed-off-by: Chris Ball --- diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c index 1c37854c0f3..e6a6d2363a4 100644 --- a/drivers/mmc/host/sh_mmcif.c +++ b/drivers/mmc/host/sh_mmcif.c @@ -1238,7 +1238,9 @@ static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN); sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); } else if (state & INT_BUFWEN) { - sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN); + sh_mmcif_writel(host->addr, MMCIF_CE_INT, + ~(INT_BUFWEN | INT_DTRANE | INT_CMD12DRE | + INT_CMD12RBE | INT_CMD12CRE)); sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); } else if (state & INT_CMD12DRE) { sh_mmcif_writel(host->addr, MMCIF_CE_INT,