Revert "drm/i915: Disable SSC for outputs other than LVDS or DP"

This reverts commit 633f2ea26665d37bb3c8ae30799aa14988622653 and the
attempted fix dcbe6f2b3d136995915e2f9ecc7d4f3b28f47b6c.

There is a single clock source used for both SSC (some LVDS and DP) and
non-SSC (VGA, DVI) outputs. So we need to be careful to only enable SSC
as necessary. However, fiddling with DREFCLK was causing DP links to be
dropped and we do not have a fix ready, so revert.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 92f4d33216cd86c9966db00599c49b03ea4add93..0c91262d259b4f290d594baecf0c8974452a83f5 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -346,7 +346,6 @@ typedef struct drm_i915_private {
        unsigned int lvds_vbt:1;
        unsigned int int_crt_support:1;
        unsigned int lvds_use_ssc:1;
-       unsigned int display_clock_mode:1;
        int lvds_ssc_freq;
        struct {
                int rate;

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 48a0f03b60c31f6b4a0a6809dfa1fb992830a11a..fb5b4d426ae0793baa93836cffe2aaf93c6f9241 100644 (file)
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -285,7 +285,6 @@ parse_general_features(struct drm_i915_private *dev_priv,
                dev_priv->lvds_use_ssc = general->enable_ssc;
                dev_priv->lvds_ssc_freq =
                        intel_bios_ssc_frequency(dev, general->ssc_freq);
-               dev_priv->display_clock_mode = general->display_clock_mode;
        }
 }
 

diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index 02b1b62415df5759697d712c4135513707043207..5f8e4edcbbb901937a20a522f60057ea762a0a9d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -120,9 +120,7 @@ struct bdb_general_features {
        u8 ssc_freq:1;
        u8 enable_lfp_on_override:1;
        u8 disable_ssc_ddt:1;
-       u8 rsvd7:1;
-       u8 display_clock_mode:1;
-       u8 rsvd8:1; /* finish byte */
+       u8 rsvd8:3; /* finish byte */
 
         /* bits 3 */
        u8 disable_smooth_vision:1;

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5e478338dc0a37199b1f3828244e9f87c34ca496..6bda30dae400e50b3527d004b029d530cb9c2250 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4506,81 +4506,6 @@ static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
        return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
 }
 
-static void intel_update_dref(struct drm_i915_private *dev_priv)
-{
-       struct drm_device *dev = dev_priv->dev;
-       struct drm_mode_config *mode_config = &dev->mode_config;
-       struct intel_encoder *encoder;
-       struct drm_crtc *crtc;
-       u32 temp;
-       bool lvds_on = false, edp_on = false, pch_edp_on = false, other_on = false;
-
-       list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
-               crtc = encoder->base.crtc;
-
-               if (!crtc || !crtc->enabled)
-                       continue;
-
-               switch (encoder->type) {
-               case INTEL_OUTPUT_LVDS:
-                       lvds_on = true;
-                       break;
-               case INTEL_OUTPUT_EDP:
-                       edp_on = true;
-                       if (!pch_edp_on)
-                               pch_edp_on = intel_encoder_is_pch_edp(&encoder->base);
-                       break;
-               default:
-                       other_on = true;
-                       break;
-               }
-       }
-
-       /*XXX BIOS treats 16:31 as a mask for 0:15 */
-
-       temp = I915_READ(PCH_DREF_CONTROL);
-
-       /* First clear the current state for output switching */
-       temp &= ~DREF_SSC1_ENABLE;
-       temp &= ~DREF_SSC4_ENABLE;
-       temp &= ~DREF_SUPERSPREAD_SOURCE_MASK;
-       temp &= ~DREF_NONSPREAD_SOURCE_MASK;
-       temp &= ~DREF_SSC_SOURCE_MASK;
-       temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
-       I915_WRITE(PCH_DREF_CONTROL, temp);
-
-       POSTING_READ(PCH_DREF_CONTROL);
-       udelay(200);
-
-       if ((lvds_on || edp_on) && intel_panel_use_ssc(dev_priv)) {
-               temp |= DREF_SSC_SOURCE_ENABLE;
-               if (edp_on) {
-                       if (!pch_edp_on) {
-                               /* Enable CPU source on CPU attached eDP */
-                               temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
-                       } else {
-                               /* Enable SSC on PCH eDP if needed */
-                               temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
-                       }
-                       I915_WRITE(PCH_DREF_CONTROL, temp);
-               }
-               if (!dev_priv->display_clock_mode)
-                       temp |= DREF_SSC1_ENABLE;
-       }
-
-       if (other_on && dev_priv->display_clock_mode)
-               temp |= DREF_NONSPREAD_CK505_ENABLE;
-       else if (other_on) {
-               temp |= DREF_NONSPREAD_SOURCE_ENABLE;
-               if (edp_on && !pch_edp_on)
-                       temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
-       }
-
-       I915_WRITE(PCH_DREF_CONTROL, temp);
-       POSTING_READ(PCH_DREF_CONTROL);
-       udelay(200);
-}
-
 static int intel_crtc_mode_set(struct drm_crtc *crtc,
                               struct drm_display_mode *mode,
                               struct drm_display_mode *adjusted_mode,
@@ -4806,8 +4731,46 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
         * PCH B stepping, previous chipset stepping should be
         * ignoring this setting.
         */
-       if (HAS_PCH_SPLIT(dev))
-               intel_update_dref(dev_priv);
+       if (HAS_PCH_SPLIT(dev)) {
+               temp = I915_READ(PCH_DREF_CONTROL);
+               /* Always enable nonspread source */
+               temp &= ~DREF_NONSPREAD_SOURCE_MASK;
+               temp |= DREF_NONSPREAD_SOURCE_ENABLE;
+               temp &= ~DREF_SSC_SOURCE_MASK;
+               temp |= DREF_SSC_SOURCE_ENABLE;
+               I915_WRITE(PCH_DREF_CONTROL, temp);
+
+               POSTING_READ(PCH_DREF_CONTROL);
+               udelay(200);
+
+               if (has_edp_encoder) {
+                       if (intel_panel_use_ssc(dev_priv)) {
+                               temp |= DREF_SSC1_ENABLE;
+                               I915_WRITE(PCH_DREF_CONTROL, temp);
+
+                               POSTING_READ(PCH_DREF_CONTROL);
+                               udelay(200);
+                       }
+                       temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
+
+                       /* Enable CPU source on CPU attached eDP */
+                       if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
+                               if (intel_panel_use_ssc(dev_priv))
+                                       temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
+                               else
+                                       temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
+                       } else {
+                               /* Enable SSC on PCH eDP if needed */
+                               if (intel_panel_use_ssc(dev_priv)) {
+                                       DRM_ERROR("enabling SSC on PCH\n");
+                                       temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
+                               }
+                       }
+                       I915_WRITE(PCH_DREF_CONTROL, temp);
+                       POSTING_READ(PCH_DREF_CONTROL);
+                       udelay(200);
+               }
+       }
 
        if (IS_PINEVIEW(dev)) {
                fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;