\r
MLX4_ENTER( MLX4_DBG_PNP );\r
\r
+ ASSERT(KeGetCurrentIrql() == PASSIVE_LEVEL);\r
+\r
/* save Card Config Space including MSI-X capabilities */\r
pci_get_msi_info( pdev, p_cfg, &pdev->uplink_info );\r
\r
if (pdev->msix_info.valid) \r
pci_free_msix_info_resources(&pdev->msix_info);\r
MLX4_EXIT( MLX4_DBG_PNP );\r
+ ASSERT(KeGetCurrentIrql() == PASSIVE_LEVEL);\r
return status;\r
}\r
\r
struct ib_udata *udata, u32 sqpn, struct mlx4_ib_qp *qp)\r
{\r
int err;\r
+ BOOLEAN range_allocated = FALSE;\r
\r
mutex_init(&qp->mutex);\r
spin_lock_init(&qp->sq.lock);\r
}\r
}\r
\r
- if (!sqpn)\r
- err = mlx4_qp_reserve_range(dev->dev, 1, 1, &sqpn);\r
- if (err)\r
- goto err_wrid;\r
+ if (!sqpn) {\r
+ err = mlx4_qp_reserve_range(dev->dev, 1, 1, &sqpn);\r
+ if (err)\r
+ goto err_wrid;\r
+ range_allocated = TRUE;\r
+ \r
+ }\r
\r
err = mlx4_qp_alloc(dev->dev, sqpn, &qp->mqp);\r
if (err)\r
- goto err_wrid;\r
-\r
- if (err) {\r
- mlx4_qp_release_range(dev->dev, sqpn, 1);\r
- goto err_wrid;\r
- }\r
+ goto err_range;\r
\r
/*\r
* Hardware wants QPN written in big-endian order (after\r
\r
return 0;\r
\r
+err_range:\r
+ if (range_allocated)\r
+ mlx4_qp_release_range(dev->dev, sqpn, 1);\r
+\r
err_wrid:\r
if (pd->p_uctx) {\r
if (!init_attr->srq)\r