atl1c: fix issue of io access mode for AR8152 v2.1

When io access mode is enabled by BOOTROM or BIOS for AR8152 v2.1,
the register can't be read/write by memory access mode.
Clearing Bit 8  of Register 0x21c could fixed the issue.

Signed-off-by: Cloud Ren <cjren@qca.qualcomm.com>
Cc: stable <stable@vger.kernel.org>
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
index 17d935bdde0ad5a7043393b2bb9f9559351e36b3..21d8c4dbdbe12b6bd90676b49a08823de35a30f7 100644 (file)
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
@@ -74,6 +74,8 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
 #define PCI_DEVICE_ID_ATHEROS_L1D_2_0  0x1083 /* AR8151 v2.0 Gigabit 1000 */
 #define L2CB_V10                       0xc0
 #define L2CB_V11                       0xc1
+#define L2CB_V20                       0xc0
+#define L2CB_V21                       0xc1
 
 /* register definition */
 #define REG_DEVICE_CAP                 0x5C
@@ -87,6 +89,9 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
 #define LINK_CTRL_L1_EN                        0x02
 #define LINK_CTRL_EXT_SYNC             0x80
 
+#define REG_PCIE_IND_ACC_ADDR          0x80
+#define REG_PCIE_IND_ACC_DATA          0x84
+
 #define REG_DEV_SERIALNUM_CTRL         0x200
 #define REG_DEV_MAC_SEL_MASK           0x0 /* 0:EUI; 1:MAC */
 #define REG_DEV_MAC_SEL_SHIFT          0

diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index 36d3783ebfa02add59cd16088efe8e016f02b5e6..1bf5bbfe778e998e9f0ca86897adc6d7001e3ed6 100644 (file)
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -727,6 +727,8 @@ static const struct atl1c_platform_patch plats[] __devinitdata = {
 
 static void __devinit atl1c_patch_assign(struct atl1c_hw *hw)
 {
+       struct pci_dev  *pdev = hw->adapter->pdev;
+       u32 misc_ctrl;
        int i = 0;
 
        hw->msi_lnkpatch = false;
@@ -741,6 +743,18 @@ static void __devinit atl1c_patch_assign(struct atl1c_hw *hw)
                }
                i++;
        }
+
+       if (hw->device_id == PCI_DEVICE_ID_ATHEROS_L2C_B2 &&
+           hw->revision_id == L2CB_V21) {
+               /* config acess mode */
+               pci_write_config_dword(pdev, REG_PCIE_IND_ACC_ADDR,
+                                      REG_PCIE_DEV_MISC_CTRL);
+               pci_read_config_dword(pdev, REG_PCIE_IND_ACC_DATA, &misc_ctrl);
+               misc_ctrl &= ~0x100;
+               pci_write_config_dword(pdev, REG_PCIE_IND_ACC_ADDR,
+                                      REG_PCIE_DEV_MISC_CTRL);
+               pci_write_config_dword(pdev, REG_PCIE_IND_ACC_DATA, misc_ctrl);
+       }
 }
 /**
  * atl1c_sw_init - Initialize general software structures (struct atl1c_adapter)
@@ -768,7 +782,7 @@ static int __devinit atl1c_sw_init(struct atl1c_adapter *adapter)
        hw->device_id = pdev->device;
        hw->subsystem_vendor_id = pdev->subsystem_vendor;
        hw->subsystem_id = pdev->subsystem_device;
-       AT_READ_REG(hw, PCI_CLASS_REVISION, &revision);
+       pci_read_config_dword(pdev, PCI_CLASS_REVISION, &revision);
        hw->revision_id = revision & 0xFF;
        /* before link up, we assume hibernate is true */
        hw->hibernate = true;