agp/intel: Use a write-combining map for updating PTEs

Rewriting the PTE entries using an WC mapping is roughly an order of
magnitude faster than through the uncached mapping. This makes an
observable difference on workloads that cycle through large numbers of
buffers, for example Chromium using ShmPixmaps where virtually all the
CPU time is currently spent rebinding the userptr.

v2: Limit the WC mapping to older generations as we have observed that
the TLB invalidation on SandyBridge+ is unreliable with WC updates.
See i-g-t/tests/gem_gtt_cpu_tlb

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 7fa655ac24d844048221c91887be3cc9ea224f5b..e01f5eaaec82a9317724c90337d9d8e45da1bb39 100644 (file)
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -666,9 +666,14 @@ static int intel_gtt_init(void)
 
        gtt_map_size = intel_private.base.gtt_total_entries * 4;
 
-       intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
-                                   gtt_map_size);
-       if (!intel_private.gtt) {
+       intel_private.gtt = NULL;
+       if (INTEL_GTT_GEN < 6)
+               intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr,
+                                              gtt_map_size);
+       if (intel_private.gtt == NULL)
+               intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
+                                           gtt_map_size);
+       if (intel_private.gtt == NULL) {
                intel_private.driver->cleanup();
                iounmap(intel_private.registers);
                return -ENOMEM;