#define DAT_MCM_VER 1
#define DAT_MCM_UD_QKEY 0x78655322
#define DAT_MCM_PDATA_SIZE 64
-#define DAT_MCM_WR 192 /* work request size (ib_wr + 7 sge's), 64 byte aligned */
#define ALIGN_64(o) ((o + 64 - 1) & ~(64-1))
#define ALIGN_P64(o) ((((uintptr_t)o) + 64 - 1)& ~(64-1))
/* Revisions:
* v1 - Initial release
* v2 - Support 3 separate EP's per device (Operations/CM, unsolicited events, transmit)
+ * v3 - reduce SGE from 7 to 4, add post_send inline support
*/
-#define DAT_MIX_VER 2
+#define DAT_MIX_VER 3
#define DAT_MIX_MSG_MAX 256
typedef enum dat_mix_ops
} dat_mix_qp_attr_t;
/*
- * todo, move posting WR's to aperture windows ??
- * ok for now since we can post async and queue them up.
* For initial prototyping write streams we don't have many
* completions. SCIF should be 2x speeds so once we pipeline
* it will keep up with IB speeds.
uint32_t m_len; /* size */
uint32_t m_seg; /* segment size */
uint32_t wr_len; /* size */
+ uint32_t m_inline; /* mpxyd inline threshold for SCIF dma */
} dat_mix_qp_t;
} dat_mix_dto_comp_t;
-#define DAT_MIX_SGE_MAX 7
+#define DAT_MIX_SGE_MAX 4
typedef struct dat_mix_send
{
dat_mix_hdr_t hdr;