viafb: reset correct PLL

Looks like we did reset the PLL of the (whatever) engine instead of
the PLL of the secondary display (IGA2, LCDCK). This patch fixes it.

Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Cc: Joseph Chan <JosephChan@via.com.tw>

diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index 7dcb4d5bb9c3aa18dbb9e8517cd27e2c6a31d1c9..53b06514cd1e03fdd78f27e61fdef1575c2ece5a 100644 (file)
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -1688,8 +1688,8 @@ void viafb_set_vclock(u32 clk, int set_iga)
        }
 
        if (set_iga == IGA2) {
-               viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0);
-               viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0);
+               viafb_write_reg_mask(SR40, VIASR, 0x04, BIT2);
+               viafb_write_reg_mask(SR40, VIASR, 0x00, BIT2);
        }
 
        /* Fire! */