]> git.openfabrics.org - ~shefty/rdma-dev.git/commitdiff
powerpc/86xx: Add new LAW & MCM device tree nodes for all 86xx systems
authorKumar Gala <galak@kernel.crashing.org>
Mon, 27 Apr 2009 16:02:16 +0000 (11:02 -0500)
committerKumar Gala <galak@kernel.crashing.org>
Tue, 19 May 2009 05:46:21 +0000 (00:46 -0500)
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
arch/powerpc/boot/dts/gef_ppc9a.dts
arch/powerpc/boot/dts/gef_sbc310.dts
arch/powerpc/boot/dts/gef_sbc610.dts
arch/powerpc/boot/dts/mpc8610_hpcd.dts
arch/powerpc/boot/dts/mpc8641_hpcn.dts
arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts
arch/powerpc/boot/dts/sbc8641d.dts

index 53a7a6255909b10fe8d732fa27ba0b4b0f46a3e0..38dd0052f6c9f06069af33d459cda9779e063ebf 100644 (file)
                reg = <0xfef00000 0x100000>;    // CCSRBAR 1M
                bus-frequency = <33333333>;
 
+               mcm-law@0 {
+                       compatible = "fsl,mcm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               mcm@1000 {
+                       compatible = "fsl,mpc8641-mcm", "fsl,mcm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                i2c1: i2c@3000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
index 1569117e5ddc6fd8ac0bd7f6afd53507ee5978c1..155776ceac259bb7aabc930552b4664d287a5dfb 100644 (file)
                reg = <0xfef00000 0x100000>;    // CCSRBAR 1M
                bus-frequency = <33333333>;
 
+               mcm-law@0 {
+                       compatible = "fsl,mcm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               mcm@1000 {
+                       compatible = "fsl,mpc8641-mcm", "fsl,mcm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                i2c1: i2c@3000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
index 6582dbd36da7ff5b99de958f7bec0841ca7270db..6898d7e87fba29a88ce07444e373e09bdd55fc66 100644 (file)
                reg = <0xfef00000 0x100000>;    // CCSRBAR 1M
                bus-frequency = <33333333>;
 
+               mcm-law@0 {
+                       compatible = "fsl,mcm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               mcm@1000 {
+                       compatible = "fsl,mpc8641-mcm", "fsl,mcm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                i2c1: i2c@3000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
index 4f081bb17320115a133bccdf2fbb4e4027e4be25..252db6e4e03160a3f01acb09a4d57a57285babb1 100644 (file)
                reg = <0xe0000000 0x1000>;
                bus-frequency = <0>;
 
+               mcm-law@0 {
+                       compatible = "fsl,mcm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               mcm@1000 {
+                       compatible = "fsl,mpc8610-mcm", "fsl,mcm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                i2c@3000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
index 51852e6e842a1957f9728c6794933746c37e62fc..8bcccd7b5d703af15641385c0c410bf00cf3402e 100644 (file)
                reg = <0xffe00000 0x00001000>;  // CCSRBAR
                bus-frequency = <0>;
 
+               mcm-law@0 {
+                       compatible = "fsl,mcm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               mcm@1000 {
+                       compatible = "fsl,mpc8641-mcm", "fsl,mcm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                i2c@3000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
index b5dc94204d03b80b1c1911cec39767ad71a96c3b..d4c909d1c00c254ba243f73c863341f400995625 100644 (file)
                reg = <0x0f 0xffe00000 0x0 0x00001000>; // CCSRBAR
                bus-frequency = <0>;
 
+               mcm-law@0 {
+                       compatible = "fsl,mcm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               mcm@1000 {
+                       compatible = "fsl,mpc8641-mcm", "fsl,mcm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                i2c@3000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
index cfd5782226b3704376204f82488be13240be683c..aa8f931a0e9be2d10cbb486b07a2abe74c49e283 100644 (file)
                reg = <0xf8000000 0x00001000>;  // CCSRBAR
                bus-frequency = <0>;
 
+               mcm-law@0 {
+                       compatible = "fsl,mcm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               mcm@1000 {
+                       compatible = "fsl,mpc8641-mcm", "fsl,mcm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                i2c@3000 {
                        #address-cells = <1>;
                        #size-cells = <0>;