powerpc: make POWER7 setup code name generic

We are going to reuse this in POWER8 so make the name generic.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index cde12f8a4ebc4e98342491a2fcb91bd31fb26f05..8f619342f14c9b64fa03579b12c245ccad7ab489 100644 (file)
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -38,7 +38,7 @@ obj-$(CONFIG_PPC64)           += setup_64.o sys_ppc32.o \
                                   paca.o nvram_64.o firmware.o
 obj-$(CONFIG_HAVE_HW_BREAKPOINT)       += hw_breakpoint.o
 obj-$(CONFIG_PPC_BOOK3S_64)    += cpu_setup_ppc970.o cpu_setup_pa6t.o
-obj-$(CONFIG_PPC_BOOK3S_64)    += cpu_setup_power7.o
+obj-$(CONFIG_PPC_BOOK3S_64)    += cpu_setup_power.o
 obj64-$(CONFIG_RELOCATABLE)    += reloc_64.o
 obj-$(CONFIG_PPC_BOOK3E_64)    += exceptions-64e.o idle_book3e.o
 obj-$(CONFIG_PPC_A2)           += cpu_setup_a2.o

diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
new file mode 100644 (file)
index 0000000..76797c5
--- /dev/null
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -0,0 +1,95 @@
+/*
+ * This file contains low level CPU setup functions.
+ *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ */
+
+#include <asm/processor.h>
+#include <asm/page.h>
+#include <asm/cputable.h>
+#include <asm/ppc_asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/cache.h>
+
+/* Entry: r3 = crap, r4 = ptr to cputable entry
+ *
+ * Note that we can be called twice for pseudo-PVRs
+ */
+_GLOBAL(__setup_cpu_power7)
+       mflr    r11
+       bl      __init_hvmode_206
+       mtlr    r11
+       beqlr
+       li      r0,0
+       mtspr   SPRN_LPID,r0
+       bl      __init_LPCR
+       bl      __init_TLB
+       mtlr    r11
+       blr
+
+_GLOBAL(__restore_cpu_power7)
+       mflr    r11
+       mfmsr   r3
+       rldicl. r0,r3,4,63
+       beqlr
+       li      r0,0
+       mtspr   SPRN_LPID,r0
+       bl      __init_LPCR
+       bl      __init_TLB
+       mtlr    r11
+       blr
+
+__init_hvmode_206:
+       /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
+       mfmsr   r3
+       rldicl. r0,r3,4,63
+       bnelr
+       ld      r5,CPU_SPEC_FEATURES(r4)
+       LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
+       xor     r5,r5,r6
+       std     r5,CPU_SPEC_FEATURES(r4)
+       blr
+
+__init_LPCR:
+       /* Setup a sane LPCR:
+        *
+        *   LPES = 0b01 (HSRR0/1 used for 0x500)
+        *   PECE = 0b111
+        *   DPFD = 4
+        *   HDICE = 0
+        *   VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
+        *   VRMASD = 0b10000 (L=1, LP=00)
+        *
+        * Other bits untouched for now
+        */
+       mfspr   r3,SPRN_LPCR
+       li      r5,1
+       rldimi  r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
+       ori     r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
+       li      r5,4
+       rldimi  r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
+       clrrdi  r3,r3,1         /* clear HDICE */
+       li      r5,4
+       rldimi  r3,r5, LPCR_VC_SH, 0
+       li      r5,0x10
+       rldimi  r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
+       mtspr   SPRN_LPCR,r3
+       isync
+       blr
+
+__init_TLB:
+       /* Clear the TLB */
+       li      r6,128
+       mtctr   r6
+       li      r7,0xc00        /* IS field = 0b11 */
+       ptesync
+2:     tlbiel  r7
+       addi    r7,r7,0x1000
+       bdnz    2b
+       ptesync
+1:     blr

diff --git a/arch/powerpc/kernel/cpu_setup_power7.S b/arch/powerpc/kernel/cpu_setup_power7.S
deleted file mode 100644 (file)
index 76797c5..0000000
--- a/arch/powerpc/kernel/cpu_setup_power7.S
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * This file contains low level CPU setup functions.
- *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- */
-
-#include <asm/processor.h>
-#include <asm/page.h>
-#include <asm/cputable.h>
-#include <asm/ppc_asm.h>
-#include <asm/asm-offsets.h>
-#include <asm/cache.h>
-
-/* Entry: r3 = crap, r4 = ptr to cputable entry
- *
- * Note that we can be called twice for pseudo-PVRs
- */
-_GLOBAL(__setup_cpu_power7)
-       mflr    r11
-       bl      __init_hvmode_206
-       mtlr    r11
-       beqlr
-       li      r0,0
-       mtspr   SPRN_LPID,r0
-       bl      __init_LPCR
-       bl      __init_TLB
-       mtlr    r11
-       blr
-
-_GLOBAL(__restore_cpu_power7)
-       mflr    r11
-       mfmsr   r3
-       rldicl. r0,r3,4,63
-       beqlr
-       li      r0,0
-       mtspr   SPRN_LPID,r0
-       bl      __init_LPCR
-       bl      __init_TLB
-       mtlr    r11
-       blr
-
-__init_hvmode_206:
-       /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
-       mfmsr   r3
-       rldicl. r0,r3,4,63
-       bnelr
-       ld      r5,CPU_SPEC_FEATURES(r4)
-       LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
-       xor     r5,r5,r6
-       std     r5,CPU_SPEC_FEATURES(r4)
-       blr
-
-__init_LPCR:
-       /* Setup a sane LPCR:
-        *
-        *   LPES = 0b01 (HSRR0/1 used for 0x500)
-        *   PECE = 0b111
-        *   DPFD = 4
-        *   HDICE = 0
-        *   VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
-        *   VRMASD = 0b10000 (L=1, LP=00)
-        *
-        * Other bits untouched for now
-        */
-       mfspr   r3,SPRN_LPCR
-       li      r5,1
-       rldimi  r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
-       ori     r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
-       li      r5,4
-       rldimi  r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
-       clrrdi  r3,r3,1         /* clear HDICE */
-       li      r5,4
-       rldimi  r3,r5, LPCR_VC_SH, 0
-       li      r5,0x10
-       rldimi  r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
-       mtspr   SPRN_LPCR,r3
-       isync
-       blr
-
-__init_TLB:
-       /* Clear the TLB */
-       li      r6,128
-       mtctr   r6
-       li      r7,0xc00        /* IS field = 0b11 */
-       ptesync
-2:     tlbiel  r7
-       addi    r7,r7,0x1000
-       bdnz    2b
-       ptesync
-1:     blr