tp->qpe = dapl_os_get_env_val("DAPL_UCM_QP_SIZE", DCM_QP_SIZE*10);
tp->cqe = dapl_os_get_env_val("DAPL_UCM_CQ_SIZE", DCM_CQ_SIZE*10);
tp->burst = dapl_os_get_env_val("DAPL_UCM_TX_BURST", DCM_TX_BURST*2);
+ tp->drep_time = dapl_os_get_env_val("DAPL_UCM_DREP_TIME", DCM_DREP_TIME*2);
}
/* default = 11-bit, 2KB entries; 18 bit, 256KB total */
goto bail;
}
- dapl_log(DAPL_DBG_TYPE_CM,
- "CM (%d+%d)- pd %p Timers(s): req %d rtu %d wait %d -"
- " idx(%d,%d): Array %d Entry %d = %d\n",
- hlen, mlen, tp->pd, tp->rep_time/1000, tp->rtu_time/1000,
- tp->wait_time/1000, tp->cm_array_bits,
- tp->cm_entry_bits, array_sz, entry_sz,
- array_sz * entry_sz);
+ dapl_log(DAPL_DBG_TYPE_CM_STATS,
+ "CM Timers(ms): [%d] creq %d,%d rtu %d tw %d dreq %d,%d "
+ "QP %d CQ %d,%d, idx(%d,%d) %d ports\n",
+ tp->ranks, tp->rep_time, tp->retries, tp->rtu_time,
+ tp->wait_time, tp->drep_time, tp->dreq_cnt,
+ tp->qpe, tp->cqe, tp->burst, tp->cm_array_bits,
+ tp->cm_entry_bits, array_sz * entry_sz);
/* default == 2K idx size, grow to 256K total CM slots */
tp->cm_idxr = dapl_os_alloc(sizeof(void*) * array_sz);