xeon-phi: adjust mlx5_ib bug fix releated to large memory region registration

Updates patch from commit 422cdc19af80d1aae4fd86bf28a5e0998b84454d
The umr check value was off by one.

Signed-off-by: Jerrie Coffman <jerrie.l.coffman@intel.com>

diff --git a/tech-preview/xeon-phi/0014-mlx5-get_dma_mr-workaround.patch b/tech-preview/xeon-phi/0014-mlx5-get_dma_mr-workaround.patch
index ab9049bc8c0a286d6091a3fcaeb05392295c6094..c044b345c9375493e5e346d67aa82507cf8fb47b 100644 (file)
--- a/tech-preview/xeon-phi/0014-mlx5-get_dma_mr-workaround.patch
+++ b/tech-preview/xeon-phi/0014-mlx5-get_dma_mr-workaround.patch
@@ -10,7 +10,7 @@ diff -Nrup a/drivers/infiniband/hw/mlx5/mr.c b/drivers/infiniband/hw/mlx5/mr.c
  static int use_umr(int order)
  {
 -      return order <= 17;
-+      return order <= 13;
++      return order <= 12;
  }
  
  static void prep_umr_reg_wqe(struct ib_pd *pd, struct ib_send_wr *wr,