[ARM] 5461/1: Freescale STMP platform support

Header files for STMP37xx boards

Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mach-stmp37xx/include/mach/entry-macro.S b/arch/arm/mach-stmp37xx/include/mach/entry-macro.S
new file mode 100644 (file)
index 0000000..fed2787
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/entry-macro.S
@@ -0,0 +1,37 @@
+/*
+ * Low-level IRQ helper macros for Freescale STMP37XX
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+               .macro  disable_fiq
+               .endm
+
+               .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+               mov     \base, #0xf0000000      @ vm address of IRQ controller
+               ldr     \irqnr, [\base, #0x30]  @ HW_ICOLL_STAT
+               cmp     \irqnr, #0x3f
+               movne   \irqstat, #0            @ Ack this IRQ
+               strne   \irqstat, [\base, #0x00]@ HW_ICOLL_VECTOR
+               moveqs  \irqnr, #0              @ Zero flag set for no IRQ
+
+               .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm

diff --git a/arch/arm/mach-stmp37xx/include/mach/irqs.h b/arch/arm/mach-stmp37xx/include/mach/irqs.h
new file mode 100644 (file)
index 0000000..98f1293
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/irqs.h
@@ -0,0 +1,99 @@
+/*
+ * Freescale STMP37XX interrupts
+ *
+ * Copyright (C) 2005 Sigmatel Inc
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef _ASM_ARCH_IRQS_H
+#define _ASM_ARCH_IRQS_H
+
+#define IRQ_DEBUG_UART          0
+#define IRQ_COMMS_RX              1
+#define IRQ_COMMS_TX              1
+#define IRQ_SSP2_ERROR          2
+#define IRQ_VDD5V                    3
+#define IRQ_HEADPHONE_SHORT        4
+#define IRQ_DAC_DMA                5
+#define IRQ_DAC_ERROR            6
+#define IRQ_ADC_DMA                7
+#define IRQ_ADC_ERROR            8
+#define IRQ_SPDIF_DMA            9
+#define IRQ_SAIF2_DMA            9
+#define IRQ_SPDIF_ERROR                10
+#define IRQ_SAIF1_IRQ            10
+#define IRQ_SAIF2_IRQ            10
+#define IRQ_USB_CTRL              11
+#define IRQ_USB_WAKEUP          12
+#define IRQ_GPMI_DMA              13
+#define IRQ_SSP1_DMA              14
+#define IRQ_SSP_ERROR            15
+#define IRQ_GPIO0                    16
+#define IRQ_GPIO1                    17
+#define IRQ_GPIO2                    18
+#define IRQ_SAIF1_DMA            19
+#define IRQ_SSP2_DMA              20
+#define IRQ_ECC8_IRQ              21
+#define IRQ_RTC_ALARM            22
+#define IRQ_UARTAPP_TX_DMA          23
+#define IRQ_UARTAPP_INTERNAL      24
+#define IRQ_UARTAPP_RX_DMA          25
+#define IRQ_I2C_DMA                26
+#define IRQ_I2C_ERROR            27
+#define IRQ_TIMER0                  28
+#define IRQ_TIMER1                  29
+#define IRQ_TIMER2                  30
+#define IRQ_TIMER3                  31
+#define IRQ_BATT_BRNOUT                32
+#define IRQ_VDDD_BRNOUT                33
+#define IRQ_VDDIO_BRNOUT              34
+#define IRQ_VDD18_BRNOUT              35
+#define IRQ_TOUCH_DETECT              36
+#define IRQ_LRADC_CH0            37
+#define IRQ_LRADC_CH1            38
+#define IRQ_LRADC_CH2            39
+#define IRQ_LRADC_CH3            40
+#define IRQ_LRADC_CH4            41
+#define IRQ_LRADC_CH5            42
+#define IRQ_LRADC_CH6            43
+#define IRQ_LRADC_CH7            44
+#define IRQ_LCDIF_DMA            45
+#define IRQ_LCDIF_ERROR                46
+#define IRQ_DIGCTL_DEBUG_TRAP    47
+#define IRQ_RTC_1MSEC            48
+#define IRQ_DRI_DMA                49
+#define IRQ_DRI_ATTENTION            50
+#define IRQ_GPMI_ATTENTION          51
+#define IRQ_IR                  52
+#define IRQ_DCP_VMI                53
+#define IRQ_DCP                        54
+#define IRQ_RESERVED_55                55
+#define IRQ_RESERVED_56                56
+#define IRQ_RESERVED_57                57
+#define IRQ_RESERVED_58                58
+#define IRQ_RESERVED_59                59
+#define SW_IRQ_60                    60
+#define SW_IRQ_61                    61
+#define SW_IRQ_62                    62
+#define SW_IRQ_63                    63
+
+#define NR_REAL_IRQS           64
+#define NR_IRQS                        (NR_REAL_IRQS + 32 * 3)
+
+/* TIMER and BRNOUT are FIQ capable */
+#define FIQ_START                      IRQ_TIMER0
+
+/* Hard disk IRQ is a GPMI attention IRQ */
+#define IRQ_HARDDISK           IRQ_GPMI_ATTENTION
+
+#endif /* _ASM_ARCH_IRQS_H */

diff --git a/arch/arm/mach-stmp37xx/include/mach/pins.h b/arch/arm/mach-stmp37xx/include/mach/pins.h
new file mode 100644 (file)
index 0000000..d56de0c
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/pins.h
@@ -0,0 +1,147 @@
+/*
+ * Freescale STMP37XX SoC pin multiplexing
+ *
+ * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_ARCH_PINS_H
+#define __ASM_ARCH_PINS_H
+
+/*
+ * Define all STMP37XX pins, a pin name corresponds to a STMP37xx hardware
+ * interface  this pin belongs to.
+ */
+
+/* Bank 0 */
+#define PINID_GPMI_D00         STMP3XXX_PINID(0, 0)
+#define PINID_GPMI_D01         STMP3XXX_PINID(0, 1)
+#define PINID_GPMI_D02         STMP3XXX_PINID(0, 2)
+#define PINID_GPMI_D03         STMP3XXX_PINID(0, 3)
+#define PINID_GPMI_D04         STMP3XXX_PINID(0, 4)
+#define PINID_GPMI_D05         STMP3XXX_PINID(0, 5)
+#define PINID_GPMI_D06         STMP3XXX_PINID(0, 6)
+#define PINID_GPMI_D07         STMP3XXX_PINID(0, 7)
+#define PINID_GPMI_D08         STMP3XXX_PINID(0, 8)
+#define PINID_GPMI_D09         STMP3XXX_PINID(0, 9)
+#define PINID_GPMI_D10         STMP3XXX_PINID(0, 10)
+#define PINID_GPMI_D11         STMP3XXX_PINID(0, 11)
+#define PINID_GPMI_D12         STMP3XXX_PINID(0, 12)
+#define PINID_GPMI_D13         STMP3XXX_PINID(0, 13)
+#define PINID_GPMI_D14         STMP3XXX_PINID(0, 14)
+#define PINID_GPMI_D15         STMP3XXX_PINID(0, 15)
+#define PINID_GPMI_A0          STMP3XXX_PINID(0, 16)
+#define PINID_GPMI_A1          STMP3XXX_PINID(0, 17)
+#define PINID_GPMI_A2          STMP3XXX_PINID(0, 18)
+#define PINID_GPMI_RDY0                STMP3XXX_PINID(0, 19)
+#define PINID_GPMI_RDY2                STMP3XXX_PINID(0, 20)
+#define PINID_GPMI_RDY3                STMP3XXX_PINID(0, 21)
+#define PINID_GPMI_RESETN      STMP3XXX_PINID(0, 22)
+#define PINID_GPMI_IRQ         STMP3XXX_PINID(0, 23)
+#define PINID_GPMI_WRN         STMP3XXX_PINID(0, 24)
+#define PINID_GPMI_RDN         STMP3XXX_PINID(0, 25)
+#define PINID_UART2_CTS                STMP3XXX_PINID(0, 26)
+#define PINID_UART2_RTS                STMP3XXX_PINID(0, 27)
+#define PINID_UART2_RX         STMP3XXX_PINID(0, 28)
+#define PINID_UART2_TX         STMP3XXX_PINID(0, 29)
+
+/* Bank 1 */
+#define PINID_LCD_D00          STMP3XXX_PINID(1, 0)
+#define PINID_LCD_D01          STMP3XXX_PINID(1, 1)
+#define PINID_LCD_D02          STMP3XXX_PINID(1, 2)
+#define PINID_LCD_D03          STMP3XXX_PINID(1, 3)
+#define PINID_LCD_D04          STMP3XXX_PINID(1, 4)
+#define PINID_LCD_D05          STMP3XXX_PINID(1, 5)
+#define PINID_LCD_D06          STMP3XXX_PINID(1, 6)
+#define PINID_LCD_D07          STMP3XXX_PINID(1, 7)
+#define PINID_LCD_D08          STMP3XXX_PINID(1, 8)
+#define PINID_LCD_D09          STMP3XXX_PINID(1, 9)
+#define PINID_LCD_D10          STMP3XXX_PINID(1, 10)
+#define PINID_LCD_D11          STMP3XXX_PINID(1, 11)
+#define PINID_LCD_D12          STMP3XXX_PINID(1, 12)
+#define PINID_LCD_D13          STMP3XXX_PINID(1, 13)
+#define PINID_LCD_D14          STMP3XXX_PINID(1, 14)
+#define PINID_LCD_D15          STMP3XXX_PINID(1, 15)
+#define PINID_LCD_RESET        STMP3XXX_PINID(1, 16)
+#define PINID_LCD_RS           STMP3XXX_PINID(1, 17)
+#define PINID_LCD_WR_RWN       STMP3XXX_PINID(1, 18)
+#define PINID_LCD_RD_E         STMP3XXX_PINID(1, 19)
+#define PINID_LCD_CS           STMP3XXX_PINID(1, 20)
+#define PINID_LCD_BUSY         STMP3XXX_PINID(1, 21)
+#define PINID_SSP1_CMD         STMP3XXX_PINID(1, 22)
+#define PINID_SSP1_SCK         STMP3XXX_PINID(1, 23)
+#define PINID_SSP1_DATA0       STMP3XXX_PINID(1, 24)
+#define PINID_SSP1_DATA1       STMP3XXX_PINID(1, 25)
+#define PINID_SSP1_DATA2       STMP3XXX_PINID(1, 26)
+#define PINID_SSP1_DATA3       STMP3XXX_PINID(1, 27)
+#define PINID_SSP1_DETECT      STMP3XXX_PINID(1, 28)
+
+/* Bank 2 */
+#define PINID_PWM0             STMP3XXX_PINID(2, 0)
+#define PINID_PWM1             STMP3XXX_PINID(2, 1)
+#define PINID_PWM2             STMP3XXX_PINID(2, 2)
+#define PINID_PWM3             STMP3XXX_PINID(2, 3)
+#define PINID_PWM4             STMP3XXX_PINID(2, 4)
+#define PINID_I2C_SCL          STMP3XXX_PINID(2, 5)
+#define PINID_I2C_SDA          STMP3XXX_PINID(2, 6)
+#define PINID_ROTTARYA         STMP3XXX_PINID(2, 7)
+#define PINID_ROTTARYB         STMP3XXX_PINID(2, 8)
+#define PINID_EMI_CKE          STMP3XXX_PINID(2, 9)
+#define PINID_EMI_RASN         STMP3XXX_PINID(2, 10)
+#define PINID_EMI_CASN         STMP3XXX_PINID(2, 11)
+#define PINID_EMI_CE0N         STMP3XXX_PINID(2, 12)
+#define PINID_EMI_CE1N         STMP3XXX_PINID(2, 13)
+#define PINID_EMI_CE2N         STMP3XXX_PINID(2, 14)
+#define PINID_EMI_CE3N         STMP3XXX_PINID(2, 15)
+#define PINID_EMI_A00          STMP3XXX_PINID(2, 16)
+#define PINID_EMI_A01          STMP3XXX_PINID(2, 17)
+#define PINID_EMI_A02          STMP3XXX_PINID(2, 18)
+#define PINID_EMI_A03          STMP3XXX_PINID(2, 19)
+#define PINID_EMI_A04          STMP3XXX_PINID(2, 20)
+#define PINID_EMI_A05          STMP3XXX_PINID(2, 21)
+#define PINID_EMI_A06          STMP3XXX_PINID(2, 22)
+#define PINID_EMI_A07          STMP3XXX_PINID(2, 23)
+#define PINID_EMI_A08          STMP3XXX_PINID(2, 24)
+#define PINID_EMI_A09          STMP3XXX_PINID(2, 25)
+#define PINID_EMI_A10          STMP3XXX_PINID(2, 26)
+#define PINID_EMI_A11          STMP3XXX_PINID(2, 27)
+#define PINID_EMI_A12          STMP3XXX_PINID(2, 28)
+#define PINID_EMI_A13          STMP3XXX_PINID(2, 29)
+#define PINID_EMI_A14          STMP3XXX_PINID(2, 30)
+#define PINID_EMI_WEN          STMP3XXX_PINID(2, 31)
+
+/* Bank 3 */
+#define PINID_EMI_D00          STMP3XXX_PINID(3, 0)
+#define PINID_EMI_D01          STMP3XXX_PINID(3, 1)
+#define PINID_EMI_D02          STMP3XXX_PINID(3, 2)
+#define PINID_EMI_D03          STMP3XXX_PINID(3, 3)
+#define PINID_EMI_D04          STMP3XXX_PINID(3, 4)
+#define PINID_EMI_D05          STMP3XXX_PINID(3, 5)
+#define PINID_EMI_D06          STMP3XXX_PINID(3, 6)
+#define PINID_EMI_D07          STMP3XXX_PINID(3, 7)
+#define PINID_EMI_D08          STMP3XXX_PINID(3, 8)
+#define PINID_EMI_D09          STMP3XXX_PINID(3, 9)
+#define PINID_EMI_D10          STMP3XXX_PINID(3, 10)
+#define PINID_EMI_D11          STMP3XXX_PINID(3, 11)
+#define PINID_EMI_D12          STMP3XXX_PINID(3, 12)
+#define PINID_EMI_D13          STMP3XXX_PINID(3, 13)
+#define PINID_EMI_D14          STMP3XXX_PINID(3, 14)
+#define PINID_EMI_D15          STMP3XXX_PINID(3, 15)
+#define PINID_EMI_DQS0         STMP3XXX_PINID(3, 16)
+#define PINID_EMI_DQS1         STMP3XXX_PINID(3, 17)
+#define PINID_EMI_DQM0         STMP3XXX_PINID(3, 18)
+#define PINID_EMI_DQM1         STMP3XXX_PINID(3, 19)
+#define PINID_EMI_CLK          STMP3XXX_PINID(3, 20)
+#define PINID_EMI_CLKN         STMP3XXX_PINID(3, 21)
+
+#endif /* __ASM_ARCH_PINS_H */