drm/i915: add LCPLL control registers

Those are used to control the display core clock.

v2: change the enable bit setting, spotted by Rodrigo Vivi.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5fe8e2dbef2d9ae76b9af08f90bcf809625cb775..8c44fe0b4fa4260b679f6c395798c42c293a609d 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4180,4 +4180,11 @@
 #define  PIPE_CLK_SEL_DISABLED (0x0<<29)
 #define  PIPE_CLK_SEL_PORT(x)  ((x+1)<<29)
 
+/* LCPLL Control */
+#define LCPLL_CTL                              0x130040
+#define  LCPLL_PLL_DISABLE             (1<<31)
+#define  LCPLL_PLL_LOCK                        (1<<30)
+#define  LCPLL_CD_CLOCK_DISABLE        (1<<25)
+#define  LCPLL_CD2X_CLOCK_DISABLE      (1<<23)
+
 #endif /* _I915_REG_H_ */