]> git.openfabrics.org - ~shefty/rdma-dev.git/commitdiff
ARM: SAMSUNG: Add tx_st_done variable
authorPadmavathi Venna <padma.v@samsung.com>
Tue, 5 Jul 2011 08:13:56 +0000 (17:13 +0900)
committerKukjin Kim <kgene.kim@samsung.com>
Wed, 6 Jul 2011 06:03:08 +0000 (15:03 +0900)
tx_st_done is required for checking the transmission status of SPI
channels with different fifo levels

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
arch/arm/mach-s3c64xx/dev-spi.c
arch/arm/mach-s5p64x0/dev-spi.c
arch/arm/mach-s5pc100/dev-spi.c
arch/arm/mach-s5pv210/dev-spi.c
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h

index 82db072cb836b78899e917f4691bacdc3857557b..5e6b42089eb44d7048b39cc2855403cd44cc0ddc 100644 (file)
@@ -88,6 +88,7 @@ static struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
        .cfg_gpio = s3c64xx_spi_cfg_gpio,
        .fifo_lvl_mask = 0x7f,
        .rx_lvl_offset = 13,
+       .tx_st_done = 21,
 };
 
 static u64 spi_dmamask = DMA_BIT_MASK(32);
@@ -132,6 +133,7 @@ static struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
        .cfg_gpio = s3c64xx_spi_cfg_gpio,
        .fifo_lvl_mask = 0x7f,
        .rx_lvl_offset = 13,
+       .tx_st_done = 21,
 };
 
 struct platform_device s3c64xx_device_spi1 = {
index e78ee18c76e321bf3a8b43862b3fa0dd0e5e6bc1..ac825e82632645c0a79300aad63ab85776cfded6 100644 (file)
@@ -112,12 +112,14 @@ static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
        .cfg_gpio       = s5p6440_spi_cfg_gpio,
        .fifo_lvl_mask  = 0x1ff,
        .rx_lvl_offset  = 15,
+       .tx_st_done     = 25,
 };
 
 static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
        .cfg_gpio       = s5p6450_spi_cfg_gpio,
        .fifo_lvl_mask  = 0x1ff,
        .rx_lvl_offset  = 15,
+       .tx_st_done     = 25,
 };
 
 static u64 spi_dmamask = DMA_BIT_MASK(32);
@@ -160,12 +162,14 @@ static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
        .cfg_gpio       = s5p6440_spi_cfg_gpio,
        .fifo_lvl_mask  = 0x7f,
        .rx_lvl_offset  = 15,
+       .tx_st_done     = 25,
 };
 
 static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
        .cfg_gpio       = s5p6450_spi_cfg_gpio,
        .fifo_lvl_mask  = 0x7f,
        .rx_lvl_offset  = 15,
+       .tx_st_done     = 25,
 };
 
 struct platform_device s5p64x0_device_spi1 = {
index 57b19794d9bbb50a5013023ed3d1b7e5902f27d0..2b58c9a2cf70eded1ca2735acab99ec20685dd9f 100644 (file)
@@ -90,6 +90,7 @@ static struct s3c64xx_spi_info s5pc100_spi0_pdata = {
        .fifo_lvl_mask = 0x7f,
        .rx_lvl_offset = 13,
        .high_speed = 1,
+       .tx_st_done = 21,
 };
 
 static u64 spi_dmamask = DMA_BIT_MASK(32);
@@ -134,6 +135,7 @@ static struct s3c64xx_spi_info s5pc100_spi1_pdata = {
        .fifo_lvl_mask = 0x7f,
        .rx_lvl_offset = 13,
        .high_speed = 1,
+       .tx_st_done = 21,
 };
 
 struct platform_device s5pc100_device_spi1 = {
@@ -176,6 +178,7 @@ static struct s3c64xx_spi_info s5pc100_spi2_pdata = {
        .fifo_lvl_mask = 0x7f,
        .rx_lvl_offset = 13,
        .high_speed = 1,
+       .tx_st_done = 21,
 };
 
 struct platform_device s5pc100_device_spi2 = {
index e3249a47e3b1de90bc8ed5e5345debb75de29260..eaf9a7bff7a0bb6facc39dd27ba12592ec1dfb2b 100644 (file)
@@ -85,6 +85,7 @@ static struct s3c64xx_spi_info s5pv210_spi0_pdata = {
        .fifo_lvl_mask = 0x1ff,
        .rx_lvl_offset = 15,
        .high_speed = 1,
+       .tx_st_done = 25,
 };
 
 static u64 spi_dmamask = DMA_BIT_MASK(32);
@@ -129,6 +130,7 @@ static struct s3c64xx_spi_info s5pv210_spi1_pdata = {
        .fifo_lvl_mask = 0x7f,
        .rx_lvl_offset = 15,
        .high_speed = 1,
+       .tx_st_done = 25,
 };
 
 struct platform_device s5pv210_device_spi1 = {
index 0ffe34a215544b1008dc0d0ff6dbf0bc852da0cf..4c16fa3621bb813f1dbd80f25e9a987dbd5e04ca 100644 (file)
@@ -39,6 +39,7 @@ struct s3c64xx_spi_csinfo {
  * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
  * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number
  * @high_speed: If the controller supports HIGH_SPEED_EN bit
+ * @tx_st_done: Depends on tx fifo_lvl field
  */
 struct s3c64xx_spi_info {
        int src_clk_nr;
@@ -53,6 +54,7 @@ struct s3c64xx_spi_info {
        int fifo_lvl_mask;
        int rx_lvl_offset;
        int high_speed;
+       int tx_st_done;
 };
 
 /**