MIPS: ath79: add USB controller registration code for the QCA955X SoCs

Register platfom devices for the built-in USB
controllers of the SoCs.

Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4952/
Signed-off-by: John Crispin <blogic@openwrt.org>

diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c
index 02124d02cf6e4a5f7aafbf05bb498a28e135f420..8227265bcc2d6ec27b467fd76d2a1a7e2d70ba43 100644 (file)
--- a/arch/mips/ath79/dev-usb.c
+++ b/arch/mips/ath79/dev-usb.c
@@ -208,6 +208,19 @@ static void __init ar934x_usb_setup(void)
                           &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
 }
 
+static void __init qca955x_usb_setup(void)
+{
+       ath79_usb_register("ehci-platform", 0,
+                          QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
+                          ATH79_IP3_IRQ(0),
+                          &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+
+       ath79_usb_register("ehci-platform", 1,
+                          QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,
+                          ATH79_IP3_IRQ(1),
+                          &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+}
+
 void __init ath79_register_usb(void)
 {
        if (soc_is_ar71xx())
@@ -222,6 +235,8 @@ void __init ath79_register_usb(void)
                ar933x_usb_setup();
        else if (soc_is_ar934x())
                ar934x_usb_setup();
+       else if (soc_is_qca955x())
+               qca955x_usb_setup();
        else
                BUG();
 }

diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index b7fa9d14d20f3a6edc02bc0c102823ffbb1e048e..4de183112917b8d3457915446af49746f9909913 100644 (file)
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -109,6 +109,9 @@
 
 #define QCA955X_WMAC_BASE      (AR71XX_APB_BASE + 0x00100000)
 #define QCA955X_WMAC_SIZE      0x20000
+#define QCA955X_EHCI0_BASE     0x1b000000
+#define QCA955X_EHCI1_BASE     0x1b400000
+#define QCA955X_EHCI_SIZE      0x1000
 
 /*
  * DDR_CTRL block