drm/i915/bdw: Interrupts with logical rings

We need to attend context switch interrupts from all rings. Also, fixed writing
IMR/IER and added HWSTAM at ring init time.

Notice that, if added to irq_enable_mask, the context switch interrupts would
be incorrectly masked out when the user interrupts are due to no users waiting
on a sequence number. Therefore, this commit adds a bitmask of interrupts to
be kept unmasked at all times.

v2: Disable HWSTAM, as suggested by Damien (nobody listens to these interrupts,
anyway).

v3: Add new get/put_irq functions.

Signed-off-by: Thomas Daniel <thomas.daniel@intel.com> (v1)
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> (v2 & v3)
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Drop the GEN8_ prefix from the context switch interrupt
define and move it to its brethren.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 36eb1f234608d5035d2fe7c7a105484c290a34db..00957fa0b87721018005b11494564d5668287896 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1647,6 +1647,8 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
                                notify_ring(dev, &dev_priv->ring[RCS]);
                        if (bcs & GT_RENDER_USER_INTERRUPT)
                                notify_ring(dev, &dev_priv->ring[BCS]);
+                       if ((rcs | bcs) & GT_CONTEXT_SWITCH_INTERRUPT)
+                               DRM_DEBUG_DRIVER("TODO: Context switch\n");
                } else
                        DRM_ERROR("The master control interrupt lied (GT0)!\n");
        }
@@ -1659,9 +1661,13 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
                        vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
                        if (vcs & GT_RENDER_USER_INTERRUPT)
                                notify_ring(dev, &dev_priv->ring[VCS]);
+                       if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
+                               DRM_DEBUG_DRIVER("TODO: Context switch\n");
                        vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
                        if (vcs & GT_RENDER_USER_INTERRUPT)
                                notify_ring(dev, &dev_priv->ring[VCS2]);
+                       if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
+                               DRM_DEBUG_DRIVER("TODO: Context switch\n");
                } else
                        DRM_ERROR("The master control interrupt lied (GT1)!\n");
        }
@@ -1685,6 +1691,8 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
                        vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
                        if (vcs & GT_RENDER_USER_INTERRUPT)
                                notify_ring(dev, &dev_priv->ring[VECS]);
+                       if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
+                               DRM_DEBUG_DRIVER("TODO: Context switch\n");
                } else
                        DRM_ERROR("The master control interrupt lied (GT3)!\n");
        }
@@ -3788,12 +3796,17 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
        /* These are interrupts we'll toggle with the ring mask register */
        uint32_t gt_interrupts[] = {
                GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
+                       GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
                        GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
-                       GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
+                       GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
+                       GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
                GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
-                       GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
+                       GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
+                       GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
+                       GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
                0,
-               GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
+               GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
+                       GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
                };
 
        for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3388afb90a93167b289eaa509d46502e3d2399fc..f79c20d49d99b6b7aa64e988d0d98830aee20b2f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1087,6 +1087,7 @@ enum punit_power_well {
 #define RING_ACTHD_UDW(base)   ((base)+0x5c)
 #define RING_NOPID(base)       ((base)+0x94)
 #define RING_IMR(base)         ((base)+0xa8)
+#define RING_HWSTAM(base)      ((base)+0x98)
 #define RING_TIMESTAMP(base)   ((base)+0x358)
 #define   TAIL_ADDR            0x001FFFF8
 #define   HEAD_WRAP_COUNT      0xFFE00000
@@ -1403,6 +1404,7 @@ enum punit_power_well {
 #define GT_BSD_CS_ERROR_INTERRUPT              (1 << 15)
 #define GT_BSD_USER_INTERRUPT                  (1 << 12)
 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
+#define GT_CONTEXT_SWITCH_INTERRUPT            (1 <<  8)
 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT    (1 <<  5) /* !snb */
 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT     (1 <<  4)
 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT    (1 <<  3)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 8a524baa8a6b8ec5e18ad8fbd089c58cbf625bec..009a8b5c088e98d9982b5187f284ccb9498555dd 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -319,6 +319,9 @@ static int gen8_init_common_ring(struct intel_engine_cs *ring)
        struct drm_device *dev = ring->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
 
+       I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
+       I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
+
        I915_WRITE(RING_MODE_GEN7(ring),
                   _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
                   _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
@@ -357,6 +360,39 @@ static int gen8_init_render_ring(struct intel_engine_cs *ring)
        return ret;
 }
 
+static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
+{
+       struct drm_device *dev = ring->dev;
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       unsigned long flags;
+
+       if (!dev->irq_enabled)
+               return false;
+
+       spin_lock_irqsave(&dev_priv->irq_lock, flags);
+       if (ring->irq_refcount++ == 0) {
+               I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
+               POSTING_READ(RING_IMR(ring->mmio_base));
+       }
+       spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+
+       return true;
+}
+
+static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
+{
+       struct drm_device *dev = ring->dev;
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       unsigned long flags;
+
+       spin_lock_irqsave(&dev_priv->irq_lock, flags);
+       if (--ring->irq_refcount == 0) {
+               I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
+               POSTING_READ(RING_IMR(ring->mmio_base));
+       }
+       spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+}
+
 static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
                           u32 invalidate_domains,
                           u32 unused)
@@ -545,6 +581,10 @@ static int logical_render_ring_init(struct drm_device *dev)
        ring->mmio_base = RENDER_RING_BASE;
        ring->irq_enable_mask =
                GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
+       ring->irq_keep_mask =
+               GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
+       if (HAS_L3_DPF(dev))
+               ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
 
        ring->init = gen8_init_render_ring;
        ring->cleanup = intel_fini_pipe_control;
@@ -552,6 +592,8 @@ static int logical_render_ring_init(struct drm_device *dev)
        ring->set_seqno = gen8_set_seqno;
        ring->emit_request = gen8_emit_request;
        ring->emit_flush = gen8_emit_flush_render;
+       ring->irq_get = gen8_logical_ring_get_irq;
+       ring->irq_put = gen8_logical_ring_put_irq;
 
        return logical_ring_init(dev, ring);
 }
@@ -566,12 +608,16 @@ static int logical_bsd_ring_init(struct drm_device *dev)
        ring->mmio_base = GEN6_BSD_RING_BASE;
        ring->irq_enable_mask =
                GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
+       ring->irq_keep_mask =
+               GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
 
        ring->init = gen8_init_common_ring;
        ring->get_seqno = gen8_get_seqno;
        ring->set_seqno = gen8_set_seqno;
        ring->emit_request = gen8_emit_request;
        ring->emit_flush = gen8_emit_flush;
+       ring->irq_get = gen8_logical_ring_get_irq;
+       ring->irq_put = gen8_logical_ring_put_irq;
 
        return logical_ring_init(dev, ring);
 }
@@ -586,12 +632,16 @@ static int logical_bsd2_ring_init(struct drm_device *dev)
        ring->mmio_base = GEN8_BSD2_RING_BASE;
        ring->irq_enable_mask =
                GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
+       ring->irq_keep_mask =
+               GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
 
        ring->init = gen8_init_common_ring;
        ring->get_seqno = gen8_get_seqno;
        ring->set_seqno = gen8_set_seqno;
        ring->emit_request = gen8_emit_request;
        ring->emit_flush = gen8_emit_flush;
+       ring->irq_get = gen8_logical_ring_get_irq;
+       ring->irq_put = gen8_logical_ring_put_irq;
 
        return logical_ring_init(dev, ring);
 }
@@ -606,12 +656,16 @@ static int logical_blt_ring_init(struct drm_device *dev)
        ring->mmio_base = BLT_RING_BASE;
        ring->irq_enable_mask =
                GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
+       ring->irq_keep_mask =
+               GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
 
        ring->init = gen8_init_common_ring;
        ring->get_seqno = gen8_get_seqno;
        ring->set_seqno = gen8_set_seqno;
        ring->emit_request = gen8_emit_request;
        ring->emit_flush = gen8_emit_flush;
+       ring->irq_get = gen8_logical_ring_get_irq;
+       ring->irq_put = gen8_logical_ring_put_irq;
 
        return logical_ring_init(dev, ring);
 }
@@ -626,12 +680,16 @@ static int logical_vebox_ring_init(struct drm_device *dev)
        ring->mmio_base = VEBOX_RING_BASE;
        ring->irq_enable_mask =
                GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
+       ring->irq_keep_mask =
+               GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
 
        ring->init = gen8_init_common_ring;
        ring->get_seqno = gen8_get_seqno;
        ring->set_seqno = gen8_set_seqno;
        ring->emit_request = gen8_emit_request;
        ring->emit_flush = gen8_emit_flush;
+       ring->irq_get = gen8_logical_ring_get_irq;
+       ring->irq_put = gen8_logical_ring_put_irq;
 
        return logical_ring_init(dev, ring);
 }

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index e497837c7724ae40150461c594f3d39f59524273..cb529ee10c8fde4e7a6fb771a031c185cb72a9e1 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -224,6 +224,7 @@ struct  intel_engine_cs {
        } semaphore;
 
        /* Execlists */
+       u32             irq_keep_mask; /* bitmask for interrupts that should not be masked */
        int             (*emit_request)(struct intel_ringbuffer *ringbuf);
        int             (*emit_flush)(struct intel_ringbuffer *ringbuf,
                                      u32 invalidate_domains,