sparc64: Run the kernel always in the TSO memory model.

The fact of the matter is, all UltraSPARC-III and later chips only
implement TSO.  They don't implement PSO and RMO memory models at all.

Only the Ultra-I and Ultra-II family chips implement RMO and they are
only helped marginally by using this setting when executing kernel
code.

The big plus to doing this is that we can eliminate all of the non-Sync
memory barriers in the kernel except for the ones used in the optimized
memcpy/memset code (these use block load and store operations which
have their own memory ordering rules).

Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/arch/sparc/include/asm/spinlock_64.h b/arch/sparc/include/asm/spinlock_64.h
index 120cfe4577c752bc44a417cdf2e4c1cef986f1c9..fbac9d00744a5e085c603c57aa579ef7d71f26ee 100644 (file)
--- a/arch/sparc/include/asm/spinlock_64.h
+++ b/arch/sparc/include/asm/spinlock_64.h
@@ -13,17 +13,12 @@
  * and rebuild your kernel.
  */
 
-/* All of these locking primitives are expected to work properly
- * even in an RMO memory model, which currently is what the kernel
- * runs in.
- *
- * There is another issue.  Because we play games to save cycles
- * in the non-contention case, we need to be extra careful about
- * branch targets into the "spinning" code.  They live in their
- * own section, but the newer V9 branches have a shorter range
- * than the traditional 32-bit sparc branch variants.  The rule
- * is that the branches that go into and out of the spinner sections
- * must be pre-V9 branches.
+/* Because we play games to save cycles in the non-contention case, we
+ * need to be extra careful about branch targets into the "spinning"
+ * code.  They live in their own section, but the newer V9 branches
+ * have a shorter range than the traditional 32-bit sparc branch
+ * variants.  The rule is that the branches that go into and out of
+ * the spinner sections must be pre-V9 branches.
  */
 
 #define __raw_spin_is_locked(lp)       ((lp)->lock != 0)

diff --git a/arch/sparc64/kernel/etrap.S b/arch/sparc64/kernel/etrap.S
index 29ce489bc1889d2b01cf59fc432562098b574e55..786b185e6e3fa8d37e6cac8b820b0654b1b787c3 100644 (file)
--- a/arch/sparc64/kernel/etrap.S
+++ b/arch/sparc64/kernel/etrap.S
@@ -16,9 +16,9 @@
 #include <asm/mmu.h>
 
 #define                TASK_REGOFF             (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ)
-#define                ETRAP_PSTATE1           (PSTATE_RMO | PSTATE_PRIV)
+#define                ETRAP_PSTATE1           (PSTATE_TSO | PSTATE_PRIV)
 #define                ETRAP_PSTATE2           \
-               (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)
+               (PSTATE_TSO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)
 
 /*
  * On entry, %g7 is return address - 0x4.
@@ -130,7 +130,7 @@ etrap_save: save    %g2, -STACK_BIAS, %sp
                stx     %g6, [%sp + PTREGS_OFF + PT_V9_G6]
                stx     %g7, [%sp + PTREGS_OFF + PT_V9_G7]
                or      %l7, %l0, %l7
-               sethi   %hi(TSTATE_RMO | TSTATE_PEF), %l0
+               sethi   %hi(TSTATE_TSO | TSTATE_PEF), %l0
                or      %l7, %l0, %l7
                wrpr    %l2, %tnpc
                wrpr    %l7, (TSTATE_PRIV | TSTATE_IE), %tstate

diff --git a/arch/sparc64/kernel/rtrap.S b/arch/sparc64/kernel/rtrap.S
index 97a993c1f7f31bd62e7b310b08077b084622adff..6892cf556f452cb97f3aad4bbf5264cf05424971 100644 (file)
--- a/arch/sparc64/kernel/rtrap.S
+++ b/arch/sparc64/kernel/rtrap.S
@@ -14,9 +14,9 @@
 #include <asm/visasm.h>
 #include <asm/processor.h>
 
-#define                RTRAP_PSTATE            (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_IE)
-#define                RTRAP_PSTATE_IRQOFF     (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV)
-#define                RTRAP_PSTATE_AG_IRQOFF  (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_AG)
+#define                RTRAP_PSTATE            (PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV|PSTATE_IE)
+#define                RTRAP_PSTATE_IRQOFF     (PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV)
+#define                RTRAP_PSTATE_AG_IRQOFF  (PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV|PSTATE_AG)
 
                .text
                .align                  32