return 0;
}
-#define tm6000_wrt(dev,req,reg,val, data...) \
- { const static u8 _val[] = data; \
- tm6000_read_write_usb(dev,USB_DIR_OUT | USB_TYPE_VENDOR, \
- req,reg, val, (u8 *) _val, ARRAY_SIZE(_val)); \
- }
-
-/*
-TM5600/6000 register values to set video standards.
- There's an adjust, common to all, for composite video
- Additional adjustments are required for S-Video, based on std.
-
- Standards values for TV S-Video Changes
-REG PAL PAL_M PAL_N SECAM NTSC Comp. PAL PAL_M PAL_N SECAM NTSC
-0xdf 0x1f 0x1f 0x1f 0x1f 0x1f
-0xe2 0x00 0x00 0x00 0x00 0x00
-0xe8 0x0f 0x0f 0x0f 0x0f 0x0f 0x00 0x00 0x00 0x00 0x00
-0xeb 0x60 0x60 0x60 0x60 0x60 0x64 0x64 0x64 0x64 0x64 0x64
-0xd5 0x5f 0x5f 0x5f 0x4f 0x4f 0x4f 0x4f 0x4f 0x4f 0x4f
-0xe3 0x00 0x00 0x00 0x00 0x00 0x10 0x10 0x10 0x10 0x10 0x10
-0xe5 0x00 0x00 0x00 0x00 0x00 0x10 0x10 0x10 0x10 0x10
-0x3f 0x01 0x01 0x01 0x01 0x01
-0x00 0x32 0x04 0x36 0x38 0x00 0x33 0x05 0x37 0x39 0x01
-0x01 0x0e 0x0e 0x0e 0x0e 0x0f
-0x02 0x5f 0x5f 0x5f 0x5f 0x5f
-0x03 0x02 0x00 0x02 0x02 0x00 0x04 0x04 0x04 0x03 0x03
-0x07 0x01 0x01 0x01 0x01 0x01 0x00 0x00
-0x17 0xcd 0xcd 0xcd 0xcd 0xcd 0x8b
-0x18 0x25 0x1e 0x1e 0x24 0x1e
-0x19 0xd5 0x83 0x91 0x92 0x8b
-0x1a 0x63 0x0a 0x1f 0xe8 0xa2
-0x1b 0x50 0xe0 0x0c 0xed 0xe9
-0x1c 0x1c 0x1c 0x1c 0x1c 0x1c
-0x1d 0xcc 0xcc 0xcc 0xcc 0xcc
-0x1e 0xcc 0xcc 0xcc 0xcc 0xcc
-0x1f 0xcd 0xcd 0xcd 0xcd 0xcd
-0x2e 0x8c 0x88 0x8c 0x8c 0x88 0x88
-0x30 0x2c 0x20 0x2c 0x2c 0x22 0x2a 0x22 0x22 0x2a
-0x31 0xc1 0x61 0xc1 0xc1 0x61
-0x33 0x0c 0x0c 0x0c 0x2c 0x1c
-0x35 0x1c 0x1c 0x1c 0x18 0x1c
-0x82 0x52 0x52 0x52 0x42 0x42
-0x04 0xdc 0xdc 0xdc 0xdd
-0x0d 0x07 0x07 0x07 0x87 0x07
-0x3f 0x00 0x00 0x00 0x00 0x00
-*/
-
-
-void tm6000_get_std_res(struct tm6000_core *dev)
-{
- /* Currently, those are the only supported resoltions */
- if (dev->norm & V4L2_STD_525_60) {
- dev->height=480;
- } else {
- dev->height=576;
- }
- dev->width=720;
-
-printk("tm6000: res= %dx%d\n",dev->width,dev->height);
-}
-
-int tm6000_set_standard (struct tm6000_core *dev, v4l2_std_id *norm)
-{
- dev->norm=*norm;
- tm6000_get_std_res(dev);
-
- /* HACK: Should use, instead, the common code!!! */
- if (*norm & V4L2_STD_PAL_M) {
-printk("calling PAL/M hack\n");
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xdf, 0x1f);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xe2, 0x00);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xe8, 0x0f);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, 0x60);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xd5, 0x5f);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xe3, 0x00);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xe5, 0x00);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x3f, 0x01);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00, 0x04);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x01, 0x0e);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x02, 0x5f);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x03, 0x00);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x07, 0x01);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x18, 0x1e);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x19, 0x83);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1a, 0x0a);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1b, 0xe0);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1c, 0x1c);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1d, 0xcc);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1e, 0xcc);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1f, 0xcd);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x2e, 0x88);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x30, 0x20);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x31, 0x61);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x33, 0x0c);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x35, 0x1c);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x82, 0x52);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x04, 0xdc);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x0d, 0x07);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x3f, 0x00);
-
- /* Enables audio and AV */
- /* maybe it should be, instead, 0x20 */
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xcc, 0x60);
- tm6000_set_reg (dev, REQ_08_SET_GET_AVREG_BIT, 0x01, 0x80);
-
- return 0;
- }
-
- if (*norm & V4L2_STD_PAL) {
-printk("calling PAL hack\n");
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xdf, 0x1f);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xe2, 0x00);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xe8, 0x0f);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, 0x60);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xd5, 0x5f);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xe3, 0x00);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xe5, 0x00);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x3f, 0x01);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00, 0x32);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x01, 0x0e);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x02, 0x5f);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x03, 0x02);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x07, 0x01);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x18, 0x25);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x19, 0xd5);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1a, 0x63);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1b, 0x50);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1c, 0x1c);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1d, 0xcc);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1e, 0xcc);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1f, 0xcd);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x2e, 0x8c);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x30, 0x2c);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x31, 0xc1);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x33, 0x0c);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x35, 0x1c);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x82, 0x52);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x04, 0xdc);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x0d, 0x07);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x3f, 0x00);
-
- return 0;
- }
-
- /* */
-// tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x02, 0x01);
-// tm6000_set_reg (dev, REQ_04_EN_DISABLE_MCU_INT, 0x02, 0x00);
-
- /* Set registers common to all standards */
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xdf, 0x1f);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xe2, 0x00);
-
- switch (dev->input) {
- case TM6000_INPUT_TV:
- /* Seems to disable ADC2 - needed for TV and RCA */
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xe8, 0x0f);
-
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, 0x60);
-
- if (*norm & V4L2_STD_PAL) {
- /* Enable UV_FLT_EN */
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xd5, 0x5f);
- } else {
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xd5, 0x4f);
- }
-
- /* E3: Select input 0 */
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xe3, 0x00);
-
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xe5, 0x10);
-
- break;
- case TM6000_INPUT_COMPOSITE:
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, 0x64);
- /* E3: Select input 1 */
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xe3, 0x10);
- break;
- case TM6000_INPUT_SVIDEO:
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xe8, 0x00);
-
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, 0x64);
-
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xd5, 0x4f);
- /* E3: Select input 1 */
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xe3, 0x10);
-
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xe5, 0x10);
-
- break;
- }
-
- /* Software reset */
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x3f, 0x01);
-
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x02, 0x5f);
-
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x07, 0x01);
-// tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x17, 0xcd);
-
- /* Horizontal Sync DTO = 0x1ccccccd */
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1c, 0x1c);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1d, 0xcc);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1e, 0xcc);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1f, 0xcd);
-
- /* Vertical Height */
- if (*norm & V4L2_STD_525_60) {
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x31, 0x61);
- } else {
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x31, 0xc1);
- }
-
- /* Horizontal Length */
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x2f, 640/8);
-
- if (*norm & V4L2_STD_PAL) {
- /* Common to All PAL Standards */
-
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x01, 0x0e);
-
- /* Vsync Hsinc Lockout End */
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x33, 0x0c);
-
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x35, 0x1c);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x82, 0x52);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x04, 0xdc);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x0d, 0x07);
- if (*norm & V4L2_STD_PAL_M) {
-
- /* Chroma DTO */
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x18, 0x1e);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x19, 0x83);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1a, 0x0a);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1b, 0xe0);
-
- /* Active Video Horiz Start Time */
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x2e, 0x88);
-
- if (dev->input==TM6000_INPUT_SVIDEO) {
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00, 0x05);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x03, 0x04);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x30, 0x22);
- } else {
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00, 0x04);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x03, 0x00);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x30, 0x20);
- }
- } else if (*norm & V4L2_STD_PAL_N) {
- /* Chroma DTO */
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x18, 0x1e);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x19, 0x91);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1a, 0x1f);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1b, 0x0c);
-
- if (dev->input==TM6000_INPUT_SVIDEO) {
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00, 0x37);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x03, 0x04);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x2e, 0x88);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x30, 0x22);
- } else {
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00, 0x36);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x03, 0x02);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x2e, 0x8c);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x30, 0x2c);
- }
- } else { // Other PAL standards
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x18, 0x25);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x19, 0xd5);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1a, 0x63);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1b, 0x50);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x2e, 0x8c);
-
- if (dev->input==TM6000_INPUT_SVIDEO) {
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00, 0x33);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x03, 0x04);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x30, 0x2a);
-
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x30, 0x2c);
- } else {
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00, 0x32);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x03, 0x02);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x30, 0x2c);
- }
- }
- } if (*norm & V4L2_STD_SECAM) {
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x01, 0x0e);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x18, 0x24);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x19, 0x92);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1a, 0xe8);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1b, 0xed);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x2e, 0x8c);
-
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x33, 0x2c);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x35, 0x18);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x82, 0x42);
- // Register 0x04 is not initialized on SECAM
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x0d, 0x87);
-
- if (dev->input==TM6000_INPUT_SVIDEO) {
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00, 0x39);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x03, 0x03);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x30, 0x2a);
- } else {
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00, 0x38);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x03, 0x02);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x30, 0x2c);
- }
- } else { /* NTSC */
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x01, 0x0f);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x18, 0x1e);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x19, 0x8b);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1a, 0xa2);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x1b, 0xe9);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x2e, 0x88);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x30, 0x22);
-
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x33, 0x1c);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x35, 0x1c);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x82, 0x42);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x0d, 0x07);
- if (dev->input==TM6000_INPUT_SVIDEO) {
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00, 0x01);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x03, 0x03);
-
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x07, 0x00);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x17, 0x8b);
- } else {
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00, 0x00);
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x03, 0x00);
- }
- }
-
-
- /* End of software reset */
- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x3f, 0x00);
-
- msleep(40);
-
- return 0;
-}
-
int tm6000_set_audio_bitrate (struct tm6000_core *dev, int bitrate)
{
int val;
--- /dev/null
+/*
+ tm6000-stds.c - driver for TM5600/TM6000 USB video capture devices
+
+ Copyright (C) 2007 Mauro Carvalho Chehab <mchehab@redhat.com>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation version 2
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include "tm6000.h"
+#include "tm6000-regs.h"
+
+struct tm6000_reg_settings {
+ unsigned char req;
+ unsigned char reg;
+ unsigned char value;
+};
+
+struct tm6000_std_tv_settings {
+ v4l2_std_id id;
+ struct tm6000_reg_settings sif[12];
+ struct tm6000_reg_settings nosif[12];
+ struct tm6000_reg_settings common[25];
+};
+
+struct tm6000_std_settings {
+ v4l2_std_id id;
+ struct tm6000_reg_settings common[37];
+};
+
+static struct tm6000_std_tv_settings tv_stds[] = {
+ {
+ .id = V4L2_STD_PAL_M,
+ .sif = {
+ {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x08},
+ {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1},
+ {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x62},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfe},
+ {REQ_07_SET_GET_AVREG, 0xfe, 0xcb},
+ {0, 0, 0},
+ },
+ .nosif = {
+ {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f},
+ {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1},
+ {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc},
+ {REQ_07_SET_GET_AVREG, 0xfe, 0x8b},
+ {0, 0, 0},
+ },
+ .common = {
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x00, 0x04},
+ {REQ_07_SET_GET_AVREG, 0x01, 0x0e},
+ {REQ_07_SET_GET_AVREG, 0x02, 0x5f},
+ {REQ_07_SET_GET_AVREG, 0x03, 0x00},
+ {REQ_07_SET_GET_AVREG, 0x07, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x18, 0x1e},
+ {REQ_07_SET_GET_AVREG, 0x19, 0x83},
+ {REQ_07_SET_GET_AVREG, 0x1a, 0x0a},
+ {REQ_07_SET_GET_AVREG, 0x1b, 0xe0},
+ {REQ_07_SET_GET_AVREG, 0x1c, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x1d, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1e, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1f, 0xcd},
+ {REQ_07_SET_GET_AVREG, 0x2e, 0x88},
+ {REQ_07_SET_GET_AVREG, 0x30, 0x20},
+ {REQ_07_SET_GET_AVREG, 0x31, 0x61},
+ {REQ_07_SET_GET_AVREG, 0x33, 0x0c},
+ {REQ_07_SET_GET_AVREG, 0x35, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x82, 0x52},
+ {REQ_07_SET_GET_AVREG, 0x83, 0x6F},
+
+ {REQ_07_SET_GET_AVREG, 0x04, 0xdc},
+ {REQ_07_SET_GET_AVREG, 0x0d, 0x07},
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x00},
+ {0, 0, 0},
+ },
+ }, {
+ .id = V4L2_STD_PAL_Nc,
+ .sif = {
+ {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x08},
+ {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1},
+ {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x62},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfe},
+ {REQ_07_SET_GET_AVREG, 0xfe, 0xcb},
+ {0, 0, 0},
+ },
+ .nosif = {
+ {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f},
+ {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1},
+ {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc},
+ {REQ_07_SET_GET_AVREG, 0xfe, 0x8b},
+ {0, 0, 0},
+ },
+ .common = {
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x00, 0x36},
+ {REQ_07_SET_GET_AVREG, 0x01, 0x0e},
+ {REQ_07_SET_GET_AVREG, 0x02, 0x5f},
+ {REQ_07_SET_GET_AVREG, 0x03, 0x02},
+ {REQ_07_SET_GET_AVREG, 0x07, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x18, 0x1e},
+ {REQ_07_SET_GET_AVREG, 0x19, 0x91},
+ {REQ_07_SET_GET_AVREG, 0x1a, 0x1f},
+ {REQ_07_SET_GET_AVREG, 0x1b, 0x0c},
+ {REQ_07_SET_GET_AVREG, 0x1c, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x1d, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1e, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1f, 0xcd},
+ {REQ_07_SET_GET_AVREG, 0x2e, 0x8c},
+ {REQ_07_SET_GET_AVREG, 0x30, 0x2c},
+ {REQ_07_SET_GET_AVREG, 0x31, 0xc1},
+ {REQ_07_SET_GET_AVREG, 0x33, 0x0c},
+ {REQ_07_SET_GET_AVREG, 0x35, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x82, 0x52},
+ {REQ_07_SET_GET_AVREG, 0x83, 0x6F},
+
+ {REQ_07_SET_GET_AVREG, 0x04, 0xdc},
+ {REQ_07_SET_GET_AVREG, 0x0d, 0x07},
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x00},
+ {0, 0, 0},
+ },
+ }, {
+ .id = V4L2_STD_PAL,
+ .sif = {
+ {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x08},
+ {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1},
+ {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x62},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfe},
+ {REQ_07_SET_GET_AVREG, 0xfe, 0xcb},
+ {0, 0, 0}
+ },
+ .nosif = {
+ {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f},
+ {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1},
+ {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc},
+ {REQ_07_SET_GET_AVREG, 0xfe, 0x8b},
+ {0, 0, 0},
+ },
+ .common = {
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x00, 0x32},
+ {REQ_07_SET_GET_AVREG, 0x01, 0x0e},
+ {REQ_07_SET_GET_AVREG, 0x02, 0x5f},
+ {REQ_07_SET_GET_AVREG, 0x03, 0x02},
+ {REQ_07_SET_GET_AVREG, 0x07, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x18, 0x25},
+ {REQ_07_SET_GET_AVREG, 0x19, 0xd5},
+ {REQ_07_SET_GET_AVREG, 0x1a, 0x63},
+ {REQ_07_SET_GET_AVREG, 0x1b, 0x50},
+ {REQ_07_SET_GET_AVREG, 0x1c, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x1d, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1e, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1f, 0xcd},
+ {REQ_07_SET_GET_AVREG, 0x2e, 0x8c},
+ {REQ_07_SET_GET_AVREG, 0x30, 0x2c},
+ {REQ_07_SET_GET_AVREG, 0x31, 0xc1},
+ {REQ_07_SET_GET_AVREG, 0x33, 0x0c},
+ {REQ_07_SET_GET_AVREG, 0x35, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x82, 0x52},
+ {REQ_07_SET_GET_AVREG, 0x83, 0x6F},
+
+ {REQ_07_SET_GET_AVREG, 0x04, 0xdc},
+ {REQ_07_SET_GET_AVREG, 0x0d, 0x07},
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x00},
+ {0, 0, 0},
+ },
+ }, {
+ .id = V4L2_STD_SECAM,
+ .sif = {
+ {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x08},
+ {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1},
+ {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x62},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfe},
+ {REQ_07_SET_GET_AVREG, 0xfe, 0xcb},
+ {0, 0, 0},
+ },
+ .nosif = {
+ {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f},
+ {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1},
+ {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc},
+ {REQ_07_SET_GET_AVREG, 0xfe, 0x8b},
+ {0, 0, 0},
+ },
+ .common = {
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x00, 0x38},
+ {REQ_07_SET_GET_AVREG, 0x01, 0x0e},
+ {REQ_07_SET_GET_AVREG, 0x02, 0x5f},
+ {REQ_07_SET_GET_AVREG, 0x03, 0x02},
+ {REQ_07_SET_GET_AVREG, 0x07, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x18, 0x24},
+ {REQ_07_SET_GET_AVREG, 0x19, 0x92},
+ {REQ_07_SET_GET_AVREG, 0x1a, 0xe8},
+ {REQ_07_SET_GET_AVREG, 0x1b, 0xed},
+ {REQ_07_SET_GET_AVREG, 0x1c, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x1d, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1e, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1f, 0xcd},
+ {REQ_07_SET_GET_AVREG, 0x2e, 0x8c},
+ {REQ_07_SET_GET_AVREG, 0x30, 0x2c},
+ {REQ_07_SET_GET_AVREG, 0x31, 0xc1},
+ {REQ_07_SET_GET_AVREG, 0x33, 0x2c},
+ {REQ_07_SET_GET_AVREG, 0x35, 0x18},
+ {REQ_07_SET_GET_AVREG, 0x82, 0x42},
+ {REQ_07_SET_GET_AVREG, 0x83, 0xFF},
+
+ {REQ_07_SET_GET_AVREG, 0x0d, 0x07},
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x00},
+ {0, 0, 0},
+ },
+ }, {
+ .id = V4L2_STD_NTSC,
+ .sif = {
+ {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x08},
+ {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1},
+ {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x62},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfe},
+ {REQ_07_SET_GET_AVREG, 0xfe, 0xcb},
+ {0, 0, 0},
+ },
+ .nosif = {
+ {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f},
+ {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1},
+ {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc},
+ {REQ_07_SET_GET_AVREG, 0xfe, 0x8b},
+ {0, 0, 0},
+ },
+ .common = {
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x00, 0x00},
+ {REQ_07_SET_GET_AVREG, 0x01, 0x0f},
+ {REQ_07_SET_GET_AVREG, 0x02, 0x5f},
+ {REQ_07_SET_GET_AVREG, 0x03, 0x00},
+ {REQ_07_SET_GET_AVREG, 0x07, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x18, 0x1e},
+ {REQ_07_SET_GET_AVREG, 0x19, 0x8b},
+ {REQ_07_SET_GET_AVREG, 0x1a, 0xa2},
+ {REQ_07_SET_GET_AVREG, 0x1b, 0xe9},
+ {REQ_07_SET_GET_AVREG, 0x1c, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x1d, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1e, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1f, 0xcd},
+ {REQ_07_SET_GET_AVREG, 0x2e, 0x88},
+ {REQ_07_SET_GET_AVREG, 0x30, 0x22},
+ {REQ_07_SET_GET_AVREG, 0x31, 0x61},
+ {REQ_07_SET_GET_AVREG, 0x33, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x35, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x82, 0x42},
+ {REQ_07_SET_GET_AVREG, 0x83, 0x6F},
+
+ {REQ_07_SET_GET_AVREG, 0x04, 0xdd},
+ {REQ_07_SET_GET_AVREG, 0x0d, 0x07},
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x00},
+ {0, 0, 0},
+ },
+ },
+};
+
+static struct tm6000_std_settings composite_stds[] = {
+ {
+ .id = V4L2_STD_PAL_M,
+ .common = {
+ {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f},
+ {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1},
+ {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc},
+ {REQ_07_SET_GET_AVREG, 0xfe, 0x8b},
+
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x00, 0x04},
+ {REQ_07_SET_GET_AVREG, 0x01, 0x0e},
+ {REQ_07_SET_GET_AVREG, 0x02, 0x5f},
+ {REQ_07_SET_GET_AVREG, 0x03, 0x00},
+ {REQ_07_SET_GET_AVREG, 0x07, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x18, 0x1e},
+ {REQ_07_SET_GET_AVREG, 0x19, 0x83},
+ {REQ_07_SET_GET_AVREG, 0x1a, 0x0a},
+ {REQ_07_SET_GET_AVREG, 0x1b, 0xe0},
+ {REQ_07_SET_GET_AVREG, 0x1c, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x1d, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1e, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1f, 0xcd},
+ {REQ_07_SET_GET_AVREG, 0x2e, 0x88},
+ {REQ_07_SET_GET_AVREG, 0x30, 0x20},
+ {REQ_07_SET_GET_AVREG, 0x31, 0x61},
+ {REQ_07_SET_GET_AVREG, 0x33, 0x0c},
+ {REQ_07_SET_GET_AVREG, 0x35, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x82, 0x52},
+ {REQ_07_SET_GET_AVREG, 0x83, 0x6F},
+
+ {REQ_07_SET_GET_AVREG, 0x04, 0xdc},
+ {REQ_07_SET_GET_AVREG, 0x0d, 0x07},
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x00},
+ {0, 0, 0},
+ },
+ }, {
+ .id = V4L2_STD_PAL_Nc,
+ .common = {
+ {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f},
+ {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1},
+ {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc},
+ {REQ_07_SET_GET_AVREG, 0xfe, 0x8b},
+
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x00, 0x36},
+ {REQ_07_SET_GET_AVREG, 0x01, 0x0e},
+ {REQ_07_SET_GET_AVREG, 0x02, 0x5f},
+ {REQ_07_SET_GET_AVREG, 0x03, 0x02},
+ {REQ_07_SET_GET_AVREG, 0x07, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x18, 0x1e},
+ {REQ_07_SET_GET_AVREG, 0x19, 0x91},
+ {REQ_07_SET_GET_AVREG, 0x1a, 0x1f},
+ {REQ_07_SET_GET_AVREG, 0x1b, 0x0c},
+ {REQ_07_SET_GET_AVREG, 0x1c, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x1d, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1e, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1f, 0xcd},
+ {REQ_07_SET_GET_AVREG, 0x2e, 0x8c},
+ {REQ_07_SET_GET_AVREG, 0x30, 0x2c},
+ {REQ_07_SET_GET_AVREG, 0x31, 0xc1},
+ {REQ_07_SET_GET_AVREG, 0x33, 0x0c},
+ {REQ_07_SET_GET_AVREG, 0x35, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x82, 0x52},
+ {REQ_07_SET_GET_AVREG, 0x83, 0x6F},
+
+ {REQ_07_SET_GET_AVREG, 0x04, 0xdc},
+ {REQ_07_SET_GET_AVREG, 0x0d, 0x07},
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x00},
+ {0, 0, 0},
+ },
+ }, {
+ .id = V4L2_STD_PAL,
+ .common = {
+ {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f},
+ {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1},
+ {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc},
+ {REQ_07_SET_GET_AVREG, 0xfe, 0x8b},
+
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x00, 0x32},
+ {REQ_07_SET_GET_AVREG, 0x01, 0x0e},
+ {REQ_07_SET_GET_AVREG, 0x02, 0x5f},
+ {REQ_07_SET_GET_AVREG, 0x03, 0x02},
+ {REQ_07_SET_GET_AVREG, 0x07, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x18, 0x25},
+ {REQ_07_SET_GET_AVREG, 0x19, 0xd5},
+ {REQ_07_SET_GET_AVREG, 0x1a, 0x63},
+ {REQ_07_SET_GET_AVREG, 0x1b, 0x50},
+ {REQ_07_SET_GET_AVREG, 0x1c, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x1d, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1e, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1f, 0xcd},
+ {REQ_07_SET_GET_AVREG, 0x2e, 0x8c},
+ {REQ_07_SET_GET_AVREG, 0x30, 0x2c},
+ {REQ_07_SET_GET_AVREG, 0x31, 0xc1},
+ {REQ_07_SET_GET_AVREG, 0x33, 0x0c},
+ {REQ_07_SET_GET_AVREG, 0x35, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x82, 0x52},
+ {REQ_07_SET_GET_AVREG, 0x83, 0x6F},
+
+ {REQ_07_SET_GET_AVREG, 0x04, 0xdc},
+ {REQ_07_SET_GET_AVREG, 0x0d, 0x07},
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x00},
+ {0, 0, 0},
+ },
+ }, {
+ .id = V4L2_STD_SECAM,
+ .common = {
+ {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f},
+ {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1},
+ {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc},
+ {REQ_07_SET_GET_AVREG, 0xfe, 0x8b},
+
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x00, 0x38},
+ {REQ_07_SET_GET_AVREG, 0x01, 0x0e},
+ {REQ_07_SET_GET_AVREG, 0x02, 0x5f},
+ {REQ_07_SET_GET_AVREG, 0x03, 0x02},
+ {REQ_07_SET_GET_AVREG, 0x07, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x18, 0x24},
+ {REQ_07_SET_GET_AVREG, 0x19, 0x92},
+ {REQ_07_SET_GET_AVREG, 0x1a, 0xe8},
+ {REQ_07_SET_GET_AVREG, 0x1b, 0xed},
+ {REQ_07_SET_GET_AVREG, 0x1c, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x1d, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1e, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1f, 0xcd},
+ {REQ_07_SET_GET_AVREG, 0x2e, 0x8c},
+ {REQ_07_SET_GET_AVREG, 0x30, 0x2c},
+ {REQ_07_SET_GET_AVREG, 0x31, 0xc1},
+ {REQ_07_SET_GET_AVREG, 0x33, 0x2c},
+ {REQ_07_SET_GET_AVREG, 0x35, 0x18},
+ {REQ_07_SET_GET_AVREG, 0x82, 0x42},
+ {REQ_07_SET_GET_AVREG, 0x83, 0xFF},
+
+ {REQ_07_SET_GET_AVREG, 0x0d, 0x07},
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x00},
+ {0, 0, 0},
+ },
+ }, {
+ .id = V4L2_STD_NTSC,
+ .common = {
+ {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f},
+ {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1},
+ {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc},
+ {REQ_07_SET_GET_AVREG, 0xfe, 0x8b},
+
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x00, 0x00},
+ {REQ_07_SET_GET_AVREG, 0x01, 0x0f},
+ {REQ_07_SET_GET_AVREG, 0x02, 0x5f},
+ {REQ_07_SET_GET_AVREG, 0x03, 0x00},
+ {REQ_07_SET_GET_AVREG, 0x07, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x18, 0x1e},
+ {REQ_07_SET_GET_AVREG, 0x19, 0x8b},
+ {REQ_07_SET_GET_AVREG, 0x1a, 0xa2},
+ {REQ_07_SET_GET_AVREG, 0x1b, 0xe9},
+ {REQ_07_SET_GET_AVREG, 0x1c, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x1d, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1e, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1f, 0xcd},
+ {REQ_07_SET_GET_AVREG, 0x2e, 0x88},
+ {REQ_07_SET_GET_AVREG, 0x30, 0x22},
+ {REQ_07_SET_GET_AVREG, 0x31, 0x61},
+ {REQ_07_SET_GET_AVREG, 0x33, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x35, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x82, 0x42},
+ {REQ_07_SET_GET_AVREG, 0x83, 0x6F},
+
+ {REQ_07_SET_GET_AVREG, 0x04, 0xdd},
+ {REQ_07_SET_GET_AVREG, 0x0d, 0x07},
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x00},
+ {0, 0, 0},
+ },
+ },
+};
+
+static struct tm6000_std_settings svideo_stds[] = {
+ {
+ .id = V4L2_STD_PAL_M,
+ .common = {
+ {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xfc},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00},
+ {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc},
+ {REQ_07_SET_GET_AVREG, 0xfe, 0x8a},
+
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x00, 0x05},
+ {REQ_07_SET_GET_AVREG, 0x01, 0x0e},
+ {REQ_07_SET_GET_AVREG, 0x02, 0x5f},
+ {REQ_07_SET_GET_AVREG, 0x03, 0x04},
+ {REQ_07_SET_GET_AVREG, 0x07, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x18, 0x1e},
+ {REQ_07_SET_GET_AVREG, 0x19, 0x83},
+ {REQ_07_SET_GET_AVREG, 0x1a, 0x0a},
+ {REQ_07_SET_GET_AVREG, 0x1b, 0xe0},
+ {REQ_07_SET_GET_AVREG, 0x1c, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x1d, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1e, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1f, 0xcd},
+ {REQ_07_SET_GET_AVREG, 0x2e, 0x88},
+ {REQ_07_SET_GET_AVREG, 0x30, 0x22},
+ {REQ_07_SET_GET_AVREG, 0x31, 0x61},
+ {REQ_07_SET_GET_AVREG, 0x33, 0x0c},
+ {REQ_07_SET_GET_AVREG, 0x35, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x82, 0x52},
+ {REQ_07_SET_GET_AVREG, 0x83, 0x6F},
+
+ {REQ_07_SET_GET_AVREG, 0x04, 0xdc},
+ {REQ_07_SET_GET_AVREG, 0x0d, 0x07},
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x00},
+ {0, 0, 0},
+ },
+ }, {
+ .id = V4L2_STD_PAL_Nc,
+ .common = {
+ {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xfc},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00},
+ {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc},
+ {REQ_07_SET_GET_AVREG, 0xfe, 0x8a},
+
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x00, 0x37},
+ {REQ_07_SET_GET_AVREG, 0x01, 0x0e},
+ {REQ_07_SET_GET_AVREG, 0x02, 0x5f},
+ {REQ_07_SET_GET_AVREG, 0x03, 0x04},
+ {REQ_07_SET_GET_AVREG, 0x07, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x18, 0x1e},
+ {REQ_07_SET_GET_AVREG, 0x19, 0x91},
+ {REQ_07_SET_GET_AVREG, 0x1a, 0x1f},
+ {REQ_07_SET_GET_AVREG, 0x1b, 0x0c},
+ {REQ_07_SET_GET_AVREG, 0x1c, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x1d, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1e, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1f, 0xcd},
+ {REQ_07_SET_GET_AVREG, 0x2e, 0x88},
+ {REQ_07_SET_GET_AVREG, 0x30, 0x22},
+ {REQ_07_SET_GET_AVREG, 0x31, 0xc1},
+ {REQ_07_SET_GET_AVREG, 0x33, 0x0c},
+ {REQ_07_SET_GET_AVREG, 0x35, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x82, 0x52},
+ {REQ_07_SET_GET_AVREG, 0x83, 0x6F},
+
+ {REQ_07_SET_GET_AVREG, 0x04, 0xdc},
+ {REQ_07_SET_GET_AVREG, 0x0d, 0x07},
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x00},
+ {0, 0, 0},
+ },
+ }, {
+ .id = V4L2_STD_PAL,
+ .common = {
+ {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xfc},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00},
+ {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc},
+ {REQ_07_SET_GET_AVREG, 0xfe, 0x8a},
+
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x00, 0x33},
+ {REQ_07_SET_GET_AVREG, 0x01, 0x0e},
+ {REQ_07_SET_GET_AVREG, 0x02, 0x5f},
+ {REQ_07_SET_GET_AVREG, 0x03, 0x04},
+ {REQ_07_SET_GET_AVREG, 0x07, 0x00},
+ {REQ_07_SET_GET_AVREG, 0x18, 0x25},
+ {REQ_07_SET_GET_AVREG, 0x19, 0xd5},
+ {REQ_07_SET_GET_AVREG, 0x1a, 0x63},
+ {REQ_07_SET_GET_AVREG, 0x1b, 0x50},
+ {REQ_07_SET_GET_AVREG, 0x1c, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x1d, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1e, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1f, 0xcd},
+ {REQ_07_SET_GET_AVREG, 0x2e, 0x8c},
+ {REQ_07_SET_GET_AVREG, 0x30, 0x2a},
+ {REQ_07_SET_GET_AVREG, 0x31, 0xc1},
+ {REQ_07_SET_GET_AVREG, 0x33, 0x0c},
+ {REQ_07_SET_GET_AVREG, 0x35, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x82, 0x52},
+ {REQ_07_SET_GET_AVREG, 0x83, 0x6F},
+
+ {REQ_07_SET_GET_AVREG, 0x04, 0xdc},
+ {REQ_07_SET_GET_AVREG, 0x0d, 0x07},
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x00},
+ {0, 0, 0},
+ },
+ }, {
+ .id = V4L2_STD_SECAM,
+ .common = {
+ {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xfc},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00},
+ {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc},
+ {REQ_07_SET_GET_AVREG, 0xfe, 0x8a},
+
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x00, 0x39},
+ {REQ_07_SET_GET_AVREG, 0x01, 0x0e},
+ {REQ_07_SET_GET_AVREG, 0x02, 0x5f},
+ {REQ_07_SET_GET_AVREG, 0x03, 0x03},
+ {REQ_07_SET_GET_AVREG, 0x07, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x18, 0x24},
+ {REQ_07_SET_GET_AVREG, 0x19, 0x92},
+ {REQ_07_SET_GET_AVREG, 0x1a, 0xe8},
+ {REQ_07_SET_GET_AVREG, 0x1b, 0xed},
+ {REQ_07_SET_GET_AVREG, 0x1c, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x1d, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1e, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1f, 0xcd},
+ {REQ_07_SET_GET_AVREG, 0x2e, 0x8c},
+ {REQ_07_SET_GET_AVREG, 0x30, 0x2a},
+ {REQ_07_SET_GET_AVREG, 0x31, 0xc1},
+ {REQ_07_SET_GET_AVREG, 0x33, 0x2c},
+ {REQ_07_SET_GET_AVREG, 0x35, 0x18},
+ {REQ_07_SET_GET_AVREG, 0x82, 0x42},
+ {REQ_07_SET_GET_AVREG, 0x83, 0xFF},
+
+ {REQ_07_SET_GET_AVREG, 0x0d, 0x07},
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x00},
+ {0, 0, 0},
+ },
+ }, {
+ .id = V4L2_STD_NTSC,
+ .common = {
+ {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xfc},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8},
+ {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00},
+ {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2},
+ {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe0},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68},
+ {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc},
+ {REQ_07_SET_GET_AVREG, 0xfe, 0x8a},
+
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x00, 0x01},
+ {REQ_07_SET_GET_AVREG, 0x01, 0x0f},
+ {REQ_07_SET_GET_AVREG, 0x02, 0x5f},
+ {REQ_07_SET_GET_AVREG, 0x03, 0x03},
+ {REQ_07_SET_GET_AVREG, 0x07, 0x00},
+ {REQ_07_SET_GET_AVREG, 0x17, 0x8b},
+ {REQ_07_SET_GET_AVREG, 0x18, 0x1e},
+ {REQ_07_SET_GET_AVREG, 0x19, 0x8b},
+ {REQ_07_SET_GET_AVREG, 0x1a, 0xa2},
+ {REQ_07_SET_GET_AVREG, 0x1b, 0xe9},
+ {REQ_07_SET_GET_AVREG, 0x1c, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x1d, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1e, 0xcc},
+ {REQ_07_SET_GET_AVREG, 0x1f, 0xcd},
+ {REQ_07_SET_GET_AVREG, 0x2e, 0x88},
+ {REQ_07_SET_GET_AVREG, 0x30, 0x22},
+ {REQ_07_SET_GET_AVREG, 0x31, 0x61},
+ {REQ_07_SET_GET_AVREG, 0x33, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x35, 0x1c},
+ {REQ_07_SET_GET_AVREG, 0x82, 0x42},
+ {REQ_07_SET_GET_AVREG, 0x83, 0x6F},
+
+ {REQ_07_SET_GET_AVREG, 0x04, 0xdd},
+ {REQ_07_SET_GET_AVREG, 0x0d, 0x07},
+ {REQ_07_SET_GET_AVREG, 0x3f, 0x00},
+ {0, 0, 0},
+ },
+ },
+};
+
+void tm6000_get_std_res(struct tm6000_core *dev)
+{
+ /* Currently, those are the only supported resoltions */
+ if (dev->norm & V4L2_STD_525_60) {
+ dev->height = 480;
+ } else {
+ dev->height = 576;
+ }
+ dev->width = 720;
+}
+
+static int tm6000_load_std(struct tm6000_core *dev,
+ struct tm6000_reg_settings *set, int max_size)
+{
+ int i, rc;
+
+ /* Load board's initialization table */
+ for (i = 0; max_size; i++) {
+ if (!set[i].req)
+ return 0;
+
+ rc = tm6000_set_reg(dev, set[i].req, set[i].reg, set[i].value);
+ if (rc < 0) {
+ printk(KERN_ERR "Error %i while setting "
+ "req %d, reg %d to value %d\n",
+ rc, set[i].req, set[i].reg, set[i].value);
+ return rc;
+ }
+ }
+
+ return 0;
+}
+
+static int tm6000_set_tv(struct tm6000_core *dev, int pos)
+{
+ int rc;
+
+ rc = tm6000_load_std(dev, tv_stds[pos].common,
+ sizeof(tv_stds[pos].common));
+
+ return rc;
+}
+
+int tm6000_set_standard(struct tm6000_core *dev, v4l2_std_id * norm)
+{
+ int i, rc = 0;
+
+ dev->norm = *norm;
+ tm6000_get_std_res(dev);
+
+ switch (dev->input) {
+ case TM6000_INPUT_TV:
+ for (i = 0; i < ARRAY_SIZE(tv_stds); i++) {
+ if (*norm & tv_stds[i].id) {
+ rc = tm6000_set_tv(dev, i);
+ goto ret;
+ }
+ }
+ return -EINVAL;
+ case TM6000_INPUT_SVIDEO:
+ for (i = 0; i < ARRAY_SIZE(svideo_stds); i++) {
+ if (*norm & svideo_stds[i].id) {
+ rc = tm6000_load_std(dev, svideo_stds[i].common,
+ sizeof(svideo_stds[i].
+ common));
+ goto ret;
+ }
+ }
+ return -EINVAL;
+ case TM6000_INPUT_COMPOSITE:
+ for (i = 0; i < ARRAY_SIZE(composite_stds); i++) {
+ if (*norm & composite_stds[i].id) {
+ rc = tm6000_load_std(dev,
+ composite_stds[i].common,
+ sizeof(composite_stds[i].
+ common));
+ goto ret;
+ }
+ }
+ return -EINVAL;
+ }
+
+ret:
+ if (rc < 0)
+ return rc;
+
+ msleep(40);
+
+ return 0;
+}
projects / ~emulex / infiniband.git / commitdiff