extern char mlnx_uvp_lib_name[];\r
extern uint32_t g_skip_tavor_reset;\r
extern uint32_t g_disable_tavor_reset;\r
+extern uint32_t g_tune_pci;\r
\r
\r
#define MLNX_MAX_HCA 4\r
UCHAR g_slog_buf[ MAX_LOG_BUF_LEN ];\r
uint32_t g_skip_tavor_reset=0; /* skip reset for Tavor cards */\r
uint32_t g_disable_tavor_reset=1; /* disable Tavor reset for the next driver load */\r
+uint32_t g_tune_pci=0; /* 0 - skip tuning PCI configuration space of HCAs */\r
UNICODE_STRING g_param_path;\r
\r
\r
{\r
NTSTATUS status;\r
/* Remember the terminating entry in the table below. */\r
- RTL_QUERY_REGISTRY_TABLE table[5];\r
+ RTL_QUERY_REGISTRY_TABLE table[6];\r
\r
HCA_ENTER( HCA_DBG_DEV );\r
\r
table[3].DefaultData = &g_disable_tavor_reset;\r
table[3].DefaultLength = sizeof(ULONG);\r
\r
+ table[4].Flags = RTL_QUERY_REGISTRY_DIRECT;\r
+ table[4].Name = L"TunePci";\r
+ table[4].EntryContext = &g_tune_pci;\r
+ table[4].DefaultType = REG_DWORD;\r
+ table[4].DefaultData = &g_tune_pci;\r
+ table[4].DefaultLength = sizeof(ULONG);\r
+\r
/* Have at it! */\r
status = RtlQueryRegistryValues( RTL_REGISTRY_ABSOLUTE, \r
g_param_path.Buffer, table, NULL, NULL );\r
\r
HCA_PRINT( TRACE_LEVEL_INFORMATION, HCA_DBG_INIT, \r
- ("debug level %d debug flags 0x%.8x SkipTavorReset %d DisableTavorReset %d\n",\r
+ ("debug level %d debug flags 0x%.8x SkipTavorReset %d DisableTavorReset %d TunePci %d\n",\r
g_mthca_dbg_level , g_mthca_dbg_flags,\r
- g_skip_tavor_reset, g_disable_tavor_reset ));\r
+ g_skip_tavor_reset, g_disable_tavor_reset,\r
+ g_tune_pci ));\r
\r
HCA_EXIT( HCA_DBG_DEV );\r
return status;\r
p_uplink_info->u.pci_x.capabilities = UPLINK_BUS_PCIX_133;\r
\r
/* Update the command field to max the read byte count if needed. */\r
- if( (pPciXCap->Command & 0x000C) != 0x000C )\r
+ if ( g_tune_pci && (pPciXCap->Command & 0x000C) != 0x000C )\r
{\r
HCA_PRINT( TRACE_LEVEL_WARNING, HCA_DBG_PNP,\r
("Updating max recv byte count of PCI-X capability.\n"));\r
if ((pPciExpCap->LinkStatus & 15) == 1)\r
p_uplink_info->u.pci_e.link_speed = UPLINK_BUS_PCIE_SDR;\r
p_uplink_info->u.pci_e.link_width = (uint8_t)((pPciExpCap->LinkStatus >> 4) & 0x03f);\r
- \r
- /* Update Max_Read_Request_Size. */\r
- HCA_PRINT( TRACE_LEVEL_WARNING ,HCA_DBG_PNP,\r
- ("Updating max recv byte count of PCI-Express capability.\n"));\r
- pPciExpCap->DevControl = (pPciExpCap->DevControl & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);\r
- len = hcaBusIfc.SetBusData( hcaBusIfc.Context, PCI_WHICHSPACE_CONFIG,\r
- &pPciExpCap->DevControl,\r
- capOffset + offsetof( PCI_PCIEXP_CAPABILITY, DevControl),\r
- sizeof( pPciExpCap->DevControl ) );\r
- if( len != sizeof( pPciExpCap->DevControl ) )\r
- {\r
- HCA_PRINT( TRACE_LEVEL_ERROR, HCA_DBG_PNP, \r
- ("Failed to update PCI-Exp maximum read byte count.\n"));\r
- goto tweakErr;\r
+\r
+ if (g_tune_pci) {\r
+ /* Update Max_Read_Request_Size. */\r
+ HCA_PRINT( TRACE_LEVEL_WARNING ,HCA_DBG_PNP,\r
+ ("Updating max recv byte count of PCI-Express capability.\n"));\r
+ pPciExpCap->DevControl = (pPciExpCap->DevControl & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);\r
+ len = hcaBusIfc.SetBusData( hcaBusIfc.Context, PCI_WHICHSPACE_CONFIG,\r
+ &pPciExpCap->DevControl,\r
+ capOffset + offsetof( PCI_PCIEXP_CAPABILITY, DevControl),\r
+ sizeof( pPciExpCap->DevControl ) );\r
+ if( len != sizeof( pPciExpCap->DevControl ) )\r
+ {\r
+ HCA_PRINT( TRACE_LEVEL_ERROR, HCA_DBG_PNP, \r
+ ("Failed to update PCI-Exp maximum read byte count.\n"));\r
+ goto tweakErr;\r
+ }\r
}\r
}\r
\r
HKR,"Parameters","DebugFlags",%REG_DWORD%,0x0000ffff\r
HKR,"Parameters","SkipTavorReset",%REG_DWORD%,0\r
HKR,"Parameters","DisableTavorResetOnFailure",%REG_DWORD%,1\r
+HKR,"Parameters","TunePci",%REG_DWORD%,0\r
HKLM,"System\CurrentControlSet\Control\WMI\GlobalLogger\8bf1f640-63fe-4743-b9ef-fa38c695bfde","Flags",%REG_DWORD%,0xffff\r
HKLM,"System\CurrentControlSet\Control\WMI\GlobalLogger\8bf1f640-63fe-4743-b9ef-fa38c695bfde","Level",%REG_DWORD%,0x3\r
\r