DIRS=\\r
- mt23108 \\r
mthca\r
-DIRS=\\r
- vapi \\r
- kernel \\r
- user\r
-#\r
-# DO NOT EDIT THIS FILE!!! Edit .\sources. if you want to add a new source\r
-# file to this component. This file merely indirects to the real make file\r
-# that is shared by all the driver components of the OpenIB Windows project.\r
-#\r
-\r
-!INCLUDE ..\..\..\inc\openib.def\r
-TARGETNAME=thca\r
-TARGETPATH=..\..\..\bin\kernel\obj$(BUILD_ALT_DIR)\r
-TARGETTYPE=DRIVER\r
-\r
-SOURCES= hca_driver.c \\r
- hca_data.c \\r
- hca_direct.c \\r
- hca_mcast.c \\r
- hca_memory.c \\r
- hca_verbs.c \\r
- hca_smp.c \\r
- hca.rc\r
-\r
-MT_HOME=..\vapi\r
-\r
-INCLUDES=\\r
- ..\..\..\inc;..\..\..\inc\kernel; \\r
- $(MT_HOME)\tavor_arch_db; \\r
- $(MT_HOME)\Hca\verbs; \\r
- $(MT_HOME)\Hca\verbs\common; \\r
- $(MT_HOME)\mlxsys\mtl_types; \\r
- $(MT_HOME)\mlxsys\mtl_types\win; \\r
- $(MT_HOME)\mlxsys\mtl_types\win\win; \\r
- $(MT_HOME)\mlxsys\mtl_common; \\r
- $(MT_HOME)\mlxsys\mtl_common\os_dep\win; \\r
- $(MT_HOME)\mlxsys\mosal; \\r
- $(MT_HOME)\mlxsys\mosal\os_dep\win; \\r
- $(MT_HOME)\Hca\hcahal; \\r
- $(MT_HOME)\Hca\hcahal\tavor; \\r
- $(MT_HOME)\Hca\hcahal\tavor\os_dep\win; \\r
- $(MT_HOME)\Hca\hcahal\tavor\thhul_hob; \\r
- $(MT_HOME)\Hca\hcahal\tavor\thhul_pdm; \\r
- $(MT_HOME)\Hca\hcahal\tavor\thhul_cqm; \\r
- $(MT_HOME)\Hca\hcahal\tavor\thhul_qpm; \\r
- $(MT_HOME)\Hca\hcahal\tavor\thhul_mwm; \\r
- $(MT_HOME)\Hca\hcahal\tavor\util; \\r
- $(MT_HOME)\Hca\hcahal\tavor\thh_hob; \\r
- $(MT_HOME)\Hca\hcahal\tavor\cmdif; \\r
- $(MT_HOME)\Hca\hcahal\tavor\eventp; \\r
- $(MT_HOME)\Hca\hcahal\tavor\uar; \\r
- $(MT_HOME)\Hca\hcahal\tavor\mrwm; \\r
- $(MT_HOME)\Hca\hcahal\tavor\udavm; \\r
- $(MT_HOME)\Hca\hcahal\tavor\mcgm; \\r
- $(MT_HOME)\Hca\hcahal\tavor\ddrmm; \\r
- $(MT_HOME)\Hca\hcahal\tavor\uldm; \\r
- $(MT_HOME)\mlxsys\os_dep\win\tdriver;\r
-\r
-C_DEFINES=$(C_DEFINES) -DDRIVER -DDEPRECATE_DDK_FUNCTIONS -D__MSC__ \\r
- -D__KERNEL__ -D__WIN__ -D__LITTLE_ENDIAN -DMT_LITTLE_ENDIAN \\r
- -DUSE_RELAY_MOD_NAME -DMAX_ERROR=4 -DIVAPI_THH \\r
- -DMTL_MODULE=HCA\r
-\r
-TARGETLIBS= \\r
- $(TARGETPATH)\*\complib.lib \\r
- $(TARGETPATH)\*\mt23108.lib \\r
- $(DDK_LIB_PATH)\wdmguid.lib\r
-\r
-MSC_WARNING_LEVEL= /W4\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#include <oib_ver.h>\r
-\r
-#define VER_FILETYPE VFT_DRV\r
-#define VER_FILESUBTYPE VFT2_UNKNOWN\r
-\r
-#ifdef _DEBUG_\r
-#define VER_FILEDESCRIPTION_STR "Tavor HCA Filter Driver (Debug)"\r
-#else\r
-#define VER_FILEDESCRIPTION_STR "Tavor HCA Filter Driver"\r
-#endif\r
-\r
-#define VER_INTERNALNAME_STR "thca.sys"\r
-#define VER_ORIGINALFILENAME_STR "thca.sys"\r
-\r
-#include <common.ver>\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies, Inc. All rights reserved. \r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#include "hca_data.h"\r
-#include "hca_debug.h"\r
-\r
-static cl_spinlock_t hob_lock;\r
-\r
-#if 1\r
-u_int32_t g_mlnx_dbg_lvl = CL_DBG_ERROR ;\r
-#else\r
-u_int32_t g_mlnx_dbg_lvl = CL_DBG_ERROR |\r
- MLNX_DBG_QPN |\r
- MLNX_DBG_MEM |\r
- MLNX_DBG_INFO |\r
- MLNX_DBG_TRACE |\r
- // MLNX_DBG_DIRECT |\r
- 0;\r
-#endif\r
-\r
-u_int32_t g_mlnx_dpc2thread = 0;\r
-\r
-#ifdef MODULE_LICENSE\r
-MODULE_LICENSE("Proprietary");\r
-#endif\r
-\r
-MODULE_PARM(g_mlnx_dbg_lvl, "i");\r
-MODULE_PARM(g_mlnx_dpc2thread, "i");\r
-\r
-cl_qlist_t mlnx_hca_list;\r
-//mlnx_hca_t mlnx_hca_array[MLNX_MAX_HCA];\r
-//uint32_t mlnx_num_hca = 0;\r
-\r
-mlnx_hob_t mlnx_hob_array[MLNX_NUM_HOBKL]; // kernel HOB - one per HCA (cmdif access)\r
-\r
-mlnx_hobul_t *mlnx_hobul_array[MLNX_NUM_HOBUL]; // kernel HOBUL - one per HCA (kar access)\r
-\r
-/* User verb library name */\r
-/* TODO: Move to linux osd file.\r
-char mlnx_uvp_lib_name[MAX_LIB_NAME] = {"libmlnx_uvp.so"};\r
-*/\r
-\r
-static void\r
-mlnx_async_dpc(\r
- IN cl_async_proc_item_t *async_item_p );\r
-\r
-#if MLNX_COMP_MODEL\r
-static void\r
-mlnx_comp_dpc(\r
- IN PRKDPC p_dpc,\r
- IN void *context,\r
- IN void *pfn_comp_cb,\r
- IN void *unused );\r
-#else\r
-static void\r
-mlnx_comp_dpc(\r
- IN cl_async_proc_item_t *async_item_p );\r
-#endif\r
-\r
-// ### Callback Interface\r
-static void\r
-mlnx_comp_cb(\r
- IN HH_hca_hndl_t hh_hndl,\r
- IN HH_cq_hndl_t hh_cq,\r
- IN void *private_data);\r
-\r
-static void\r
-mlnx_async_cb(\r
- IN HH_hca_hndl_t hh_hndl,\r
- IN HH_event_record_t *hh_er_p,\r
- IN void *private_data);\r
-\r
-/////////////////////////////////////////////////////////\r
-// ### HCA\r
-/////////////////////////////////////////////////////////\r
-void\r
-mlnx_hca_insert(\r
- IN mlnx_hca_t *p_hca )\r
-{\r
- cl_spinlock_acquire( &hob_lock );\r
- cl_qlist_insert_tail( &mlnx_hca_list, &p_hca->list_item );\r
- cl_spinlock_release( &hob_lock );\r
-}\r
-\r
-void\r
-mlnx_hca_remove(\r
- IN mlnx_hca_t *p_hca )\r
-{\r
- cl_spinlock_acquire( &hob_lock );\r
- cl_qlist_remove_item( &mlnx_hca_list, &p_hca->list_item );\r
- cl_spinlock_release( &hob_lock );\r
-}\r
-\r
-mlnx_hca_t*\r
-mlnx_hca_from_guid(\r
- IN ib_net64_t guid )\r
-{\r
- cl_list_item_t *p_item;\r
- mlnx_hca_t *p_hca = NULL;\r
-\r
- cl_spinlock_acquire( &hob_lock );\r
- p_item = cl_qlist_head( &mlnx_hca_list );\r
- while( p_item != cl_qlist_end( &mlnx_hca_list ) )\r
- {\r
- p_hca = PARENT_STRUCT( p_item, mlnx_hca_t, list_item );\r
- if( p_hca->guid == guid )\r
- break;\r
- p_item = cl_qlist_next( p_item );\r
- p_hca = NULL;\r
- }\r
- cl_spinlock_release( &hob_lock );\r
- return p_hca;\r
-}\r
-\r
-mlnx_hca_t*\r
-mlnx_hca_from_hh_hndl(\r
- IN HH_hca_hndl_t hh_hndl )\r
-{\r
- cl_list_item_t *p_item;\r
- mlnx_hca_t *p_hca = NULL;\r
-\r
- cl_spinlock_acquire( &hob_lock );\r
- p_item = cl_qlist_head( &mlnx_hca_list );\r
- while( p_item != cl_qlist_end( &mlnx_hca_list ) )\r
- {\r
- p_hca = PARENT_STRUCT( p_item, mlnx_hca_t, list_item );\r
- if( p_hca->hh_hndl == hh_hndl )\r
- break;\r
- p_item = cl_qlist_next( p_item );\r
- p_hca = NULL;\r
- }\r
- cl_spinlock_release( &hob_lock );\r
- return p_hca;\r
-}\r
-\r
-\r
-/*\r
-void\r
-mlnx_names_from_guid(\r
- IN ib_net64_t guid,\r
- OUT char **hca_name_p,\r
- OUT char **dev_name_p)\r
-{\r
- unsigned int idx;\r
-\r
- if (!hca_name_p) return;\r
- if (!dev_name_p) return;\r
-\r
- for (idx = 0; idx < mlnx_num_hca; idx++)\r
- {\r
- if (mlnx_hca_array[idx].ifx.guid == guid)\r
- {\r
- *hca_name_p = mlnx_hca_array[idx].hca_name_p;\r
- *dev_name_p = mlnx_hca_array[idx].dev_name_p;\r
- }\r
- }\r
-}\r
-*/\r
-\r
-/////////////////////////////////////////////////////////\r
-// ### HOB\r
-/////////////////////////////////////////////////////////\r
-cl_status_t\r
-mlnx_hobs_init( void )\r
-{\r
- u_int32_t idx;\r
-\r
- cl_qlist_init( &mlnx_hca_list );\r
-\r
- for (idx = 0; idx < MLNX_NUM_HOBKL; idx++)\r
- {\r
- mlnx_hob_array[idx].hh_hndl = NULL;\r
- mlnx_hob_array[idx].comp_cb_p = NULL;\r
- mlnx_hob_array[idx].async_cb_p = NULL;\r
- mlnx_hob_array[idx].ca_context = NULL;\r
- mlnx_hob_array[idx].async_proc_mgr_p = NULL;\r
- mlnx_hob_array[idx].cl_device_h = NULL;\r
- // mlnx_hob_array[idx].port_lmc_p = NULL;\r
- mlnx_hob_array[idx].index = idx;\r
- mlnx_hob_array[idx].mark = E_MARK_INVALID;\r
- }\r
- return cl_spinlock_init( &hob_lock );\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-ib_api_status_t\r
-mlnx_hobs_insert(\r
- IN mlnx_hca_t *p_hca,\r
- OUT mlnx_hob_t **hob_pp)\r
-{\r
- u_int32_t idx;\r
- ib_api_status_t status = IB_ERROR;\r
- mlnx_cache_t *p_cache;\r
-\r
- p_cache = (mlnx_cache_t*)cl_pzalloc( sizeof(mlnx_cache_t) * 2 );\r
- if( !p_cache )\r
- return IB_INSUFFICIENT_MEMORY;\r
-\r
- cl_spinlock_acquire(&hob_lock);\r
- for (idx = 0; idx < MLNX_NUM_HOBKL; idx++)\r
- {\r
- if (!mlnx_hob_array[idx].hh_hndl)\r
- {\r
- mlnx_hob_array[idx].hh_hndl = p_hca->hh_hndl;\r
- mlnx_hob_array[idx].mark = E_MARK_CA;\r
- if (hob_pp) *hob_pp = &mlnx_hob_array[idx];\r
- status = IB_SUCCESS;\r
- break;\r
- }\r
- }\r
- cl_spinlock_release(&hob_lock);\r
-\r
- if (IB_SUCCESS == status)\r
- (*hob_pp)->cache = p_cache;\r
- else\r
- cl_free( p_cache );\r
-\r
- return status;\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-ib_api_status_t\r
-mlnx_hobs_set_cb(\r
- IN mlnx_hob_t *hob_p, \r
- IN ci_completion_cb_t comp_cb_p,\r
- IN ci_async_event_cb_t async_cb_p,\r
- IN const void* const ib_context)\r
-{\r
- cl_status_t cl_status;\r
-\r
- // Verify handle\r
- CL_ASSERT((hob_p - mlnx_hob_array) < MLNX_NUM_HOBKL);\r
-\r
- // Setup the callbacks\r
- if (!hob_p->async_proc_mgr_p)\r
- {\r
- hob_p->async_proc_mgr_p = cl_malloc( sizeof( cl_async_proc_t ) );\r
- if( !hob_p->async_proc_mgr_p )\r
- {\r
- return IB_INSUFFICIENT_MEMORY;\r
- }\r
- cl_async_proc_construct( hob_p->async_proc_mgr_p );\r
- cl_status = cl_async_proc_init( hob_p->async_proc_mgr_p, MLNX_NUM_CB_THR, "CBthread" );\r
- if( cl_status != CL_SUCCESS )\r
- {\r
- cl_async_proc_destroy( hob_p->async_proc_mgr_p );\r
- cl_free(hob_p->async_proc_mgr_p);\r
- hob_p->async_proc_mgr_p = NULL;\r
- return IB_INSUFFICIENT_RESOURCES;\r
- }\r
- }\r
-\r
- if (hob_p->hh_hndl)\r
- {\r
- THH_hob_set_async_eventh(hob_p->hh_hndl,\r
- mlnx_async_cb,\r
- &hob_p->index); // This is the context our CB wants to receive\r
- THH_hob_set_comp_eventh( hob_p->hh_hndl,\r
- mlnx_comp_cb,\r
- &hob_p->index); // This is the context our CB wants to receive\r
- hob_p->comp_cb_p = comp_cb_p;\r
- hob_p->async_cb_p = async_cb_p;\r
- hob_p->ca_context = ib_context; // This is the context our CB forwards to IBAL\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("CL: hca_idx %d context 0x%p\n", hob_p - mlnx_hob_array, ib_context));\r
- return IB_SUCCESS;\r
- }\r
- return IB_ERROR;\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-ib_api_status_t\r
-mlnx_hobs_get_context(\r
- IN mlnx_hob_t *hob_p,\r
- OUT void **context_p)\r
-{\r
- // Verify handle\r
- CL_ASSERT((hob_p - mlnx_hob_array) < MLNX_NUM_HOBKL);\r
-\r
- if (hob_p->hh_hndl)\r
- {\r
- if (context_p) *context_p = &hob_p->index;\r
- return IB_SUCCESS;\r
- }\r
- return IB_ERROR;\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-void\r
-mlnx_hobs_remove(\r
- IN mlnx_hob_t *hob_p)\r
-{\r
- cl_async_proc_t *p_async_proc;\r
- mlnx_cache_t *p_cache;\r
-\r
- // Verify handle\r
- CL_ASSERT((hob_p - mlnx_hob_array) < MLNX_NUM_HOBKL);\r
-\r
- cl_spinlock_acquire( &hob_lock );\r
-\r
- hob_p->mark = E_MARK_INVALID;\r
-\r
- p_async_proc = hob_p->async_proc_mgr_p;\r
- hob_p->async_proc_mgr_p = NULL;\r
-\r
- p_cache = hob_p->cache;\r
- hob_p->cache = NULL;\r
-\r
- hob_p->hh_hndl = NULL;\r
- hob_p->comp_cb_p = NULL;\r
- hob_p->async_cb_p = NULL;\r
- hob_p->ca_context = NULL;\r
- hob_p->cl_device_h = NULL;\r
-\r
- cl_spinlock_release( &hob_lock );\r
-\r
- if( p_async_proc )\r
- {\r
- cl_async_proc_destroy( p_async_proc );\r
- cl_free( p_async_proc );\r
- }\r
-\r
- if( p_cache )\r
- cl_free( p_cache );\r
-\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("CL: hobs_remove idx %d hh_hndl 0x%p\n", hob_p - mlnx_hob_array, hob_p->hh_hndl));\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-ib_api_status_t\r
-mlnx_hobs_lookup(\r
- IN HH_hca_hndl_t hndl,\r
- OUT mlnx_hob_t **hca_p)\r
-{\r
- u_int32_t idx;\r
-\r
- if (!hca_p)\r
- return IB_ERROR;\r
-\r
- cl_spinlock_acquire( &hob_lock );\r
- for (idx = 0; idx < MLNX_NUM_HOBKL; idx++)\r
- {\r
- if (hndl == mlnx_hob_array[idx].hh_hndl)\r
- {\r
- *hca_p = &mlnx_hob_array[idx];\r
- cl_spinlock_release( &hob_lock );\r
- return IB_SUCCESS;\r
- }\r
- }\r
- cl_spinlock_release( &hob_lock );\r
- return IB_ERROR;\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-void\r
-mlnx_hobs_get_handle(\r
- IN mlnx_hob_t *hob_p,\r
- OUT HH_hca_hndl_t *hndl_p)\r
-{\r
- // Verify handle\r
- CL_ASSERT((hob_p - mlnx_hob_array) < MLNX_NUM_HOBKL);\r
-\r
- if (hndl_p)\r
- *hndl_p = hob_p->hh_hndl;\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-mlnx_hobul_t *\r
-mlnx_hobs_get_hobul(\r
- IN mlnx_hob_t *hob_p)\r
-{\r
- // Verify handle\r
- if ((hob_p - mlnx_hob_array) >= MLNX_NUM_HOBKL)\r
- return NULL;\r
-\r
- return mlnx_hobul_array[hob_p->index];\r
-}\r
-\r
-\r
-static int priv_ceil_log2(u_int32_t n)\r
-{\r
- int shift;\r
-\r
- for (shift = 31; shift >0; shift--)\r
- if (n & (1 << shift)) break;\r
-\r
- if (((unsigned)1 << shift) < n) shift++;\r
-\r
- return shift;\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-// ### HOBUL\r
-/////////////////////////////////////////////////////////\r
-ib_api_status_t\r
-mlnx_hobul_new(\r
- IN mlnx_hob_t *hob_p,\r
- IN HH_hca_hndl_t hh_hndl,\r
- IN void *resources_p)\r
-{\r
- mlnx_hobul_t *hobul_p;\r
- HH_hca_dev_t *hca_ul_info;\r
- ib_api_status_t status;\r
- VAPI_hca_cap_t hca_caps;\r
- u_int32_t i;\r
-#if MLNX_COMP_MODEL == 1\r
- static uint32_t proc_num = 0;\r
-#endif\r
-\r
- // Verify handle\r
- CL_ASSERT((hob_p - mlnx_hob_array) < MLNX_NUM_HOBKL);\r
-\r
- if (NULL == (hobul_p = cl_zalloc( sizeof(mlnx_hobul_t))))\r
- return IB_INSUFFICIENT_MEMORY;\r
-\r
- // The following will NULL all pointers/sizes (used in cleanup)\r
-// cl_memclr(hobul_p, sizeof (mlnx_hobul_t));\r
-\r
- hobul_p->hh_hndl = hh_hndl;\r
-\r
- if (HH_OK != THHUL_hob_create(resources_p, hh_hndl->dev_id, &hobul_p->hhul_hndl))\r
- {\r
- status = IB_INSUFFICIENT_RESOURCES;\r
- goto cleanup;\r
- }\r
-\r
- hca_ul_info = (HH_hca_dev_t *)hh_hndl;\r
-\r
- if (hca_ul_info)\r
- {\r
- hobul_p->vendor_id = hca_ul_info->vendor_id;\r
- hobul_p->device_id = hca_ul_info->dev_id;\r
- hobul_p->hca_ul_resources_p = resources_p;\r
- hobul_p->cq_ul_resources_sz = hca_ul_info->cq_ul_resources_sz;\r
- hobul_p->qp_ul_resources_sz = hca_ul_info->qp_ul_resources_sz;\r
- hobul_p->pd_ul_resources_sz = hca_ul_info->pd_ul_resources_sz;\r
- }\r
-\r
- if (HH_OK != THH_hob_query(hh_hndl, &hca_caps))\r
- {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
-\r
- hobul_p->cq_idx_mask = MASK32(priv_ceil_log2(hca_caps.max_num_cq));\r
- hobul_p->qp_idx_mask = MASK32(priv_ceil_log2(hca_caps.max_num_qp)); // Currently mask = 0xFFFF\r
- hobul_p->max_pd = MASK32(priv_ceil_log2(hca_caps.max_pd_num)) + 1;\r
- hobul_p->max_cq = hobul_p->cq_idx_mask + 1;\r
- hobul_p->max_qp = hobul_p->qp_idx_mask + 1;\r
-\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("CL: sizes cq 0%x qp 0%x pd 0%x\n", hca_caps.max_num_cq, hca_caps.max_num_qp, hca_caps.max_pd_num));\r
-\r
- /* create and initialize the data stucture for CQs */\r
- hobul_p->cq_info_tbl = cl_zalloc(hobul_p->max_cq * sizeof (cq_info_t));\r
-\r
- /* create and initialize the data stucture for QPs */\r
- hobul_p->qp_info_tbl = cl_zalloc(hobul_p->max_qp * sizeof (qp_info_t));\r
-\r
- /* create and initialize the data stucture for PDs */\r
- hobul_p->pd_info_tbl = cl_zalloc(hobul_p->max_pd * sizeof (pd_info_t));\r
-\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("CL: alloc failed? cq=%d qp=%d pd=%d\n",\r
- !hobul_p->cq_info_tbl, !hobul_p->qp_info_tbl, !hobul_p->pd_info_tbl));\r
-\r
- if (!hobul_p->pd_info_tbl ||\r
- !hobul_p->qp_info_tbl ||\r
- !hobul_p->cq_info_tbl)\r
- {\r
- status = IB_INSUFFICIENT_MEMORY;\r
- goto cleanup;\r
- }\r
-\r
- /* Initialize all mutexes. */\r
- for( i = 0; i < hobul_p->max_cq; i++ )\r
- {\r
- cl_mutex_construct( &hobul_p->cq_info_tbl[i].mutex );\r
-#if MLNX_COMP_MODEL\r
- KeInitializeDpc( &hobul_p->cq_info_tbl[i].dpc,\r
- mlnx_comp_dpc, &hobul_p->cq_info_tbl[i] );\r
-#if MLNX_COMP_MODEL == 1\r
- KeSetTargetProcessorDpc( &hobul_p->cq_info_tbl[i].dpc,\r
- (CCHAR)(proc_num++ % cl_proc_count()) );\r
-#endif /* MLNX_COMP_MODEL == 1 */\r
-#endif /* MLNX_COMP_MODEL */\r
- }\r
-\r
- for( i = 0; i < hobul_p->max_qp; i++ )\r
- cl_mutex_construct( &hobul_p->qp_info_tbl[i].mutex );\r
-\r
- for( i = 0; i < hobul_p->max_pd; i++ )\r
- cl_mutex_construct( &hobul_p->pd_info_tbl[i].mutex );\r
-\r
- for( i = 0; i < hobul_p->max_cq; i++ )\r
- {\r
- if( cl_mutex_init( &hobul_p->cq_info_tbl[i].mutex ) != CL_SUCCESS )\r
- {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
- }\r
-\r
- for( i = 0; i < hobul_p->max_qp; i++ )\r
- {\r
- if( cl_mutex_init( &hobul_p->qp_info_tbl[i].mutex ) != CL_SUCCESS )\r
- {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
- }\r
-\r
- for( i = 0; i < hobul_p->max_pd; i++ )\r
- {\r
- if( cl_mutex_init( &hobul_p->pd_info_tbl[i].mutex ) != CL_SUCCESS )\r
- {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
- }\r
-\r
- hobul_p->log2_mpt_size = ((THH_hca_ul_resources_t *)resources_p)->log2_mpt_size;\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("log2_mpt_size = %d\n", hobul_p->log2_mpt_size));\r
-\r
- cl_spinlock_acquire(&hob_lock);\r
- mlnx_hobul_array[hob_p->index] = hobul_p;\r
- cl_spinlock_release(&hob_lock);\r
-\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- if (hobul_p->hhul_hndl) THHUL_hob_destroy( hobul_p->hhul_hndl );\r
- if (hobul_p->pd_info_tbl)\r
- {\r
- for( i = 0; i < hobul_p->max_pd; i++ )\r
- cl_mutex_destroy( &hobul_p->pd_info_tbl[i].mutex );\r
- cl_free(hobul_p->pd_info_tbl);\r
- }\r
- if (hobul_p->qp_info_tbl)\r
- {\r
- for( i = 0; i < hobul_p->max_qp; i++ )\r
- cl_mutex_destroy( &hobul_p->qp_info_tbl[i].mutex );\r
- cl_free(hobul_p->qp_info_tbl);\r
- }\r
- if (hobul_p->cq_info_tbl)\r
- {\r
- for( i = 0; i < hobul_p->max_cq; i++ )\r
- cl_mutex_destroy( &hobul_p->cq_info_tbl[i].mutex );\r
- cl_free(hobul_p->cq_info_tbl);\r
- }\r
- if (hobul_p) cl_free( hobul_p);\r
- return status;\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-void\r
-mlnx_hobul_get(\r
- IN mlnx_hob_t *hob_p,\r
- OUT void **resources_p )\r
-{\r
- mlnx_hobul_t *hobul_p;\r
-\r
- // Verify handle\r
- CL_ASSERT((hob_p - mlnx_hob_array) < MLNX_NUM_HOBKL);\r
-\r
- hobul_p = mlnx_hobul_array[hob_p->index];\r
-\r
- if (hobul_p && resources_p)\r
- {\r
- *resources_p = hobul_p->hca_ul_resources_p;\r
- }\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-void\r
-mlnx_hobul_delete(\r
- IN mlnx_hob_t *hob_p)\r
-{\r
- mlnx_hobul_t *hobul_p;\r
- u_int32_t i;\r
-\r
- // Verify handle\r
- CL_ASSERT((hob_p - mlnx_hob_array) < MLNX_NUM_HOBKL);\r
-\r
- cl_spinlock_acquire(&hob_lock);\r
- hobul_p = mlnx_hobul_array[hob_p->index];\r
- mlnx_hobul_array[hob_p->index] = NULL;\r
- cl_spinlock_release(&hob_lock);\r
-\r
- if (!hobul_p) return;\r
-\r
- if (hobul_p->hhul_hndl) THHUL_hob_destroy( hobul_p->hhul_hndl );\r
- if (hobul_p->pd_info_tbl)\r
- {\r
- for( i = 0; i < hobul_p->max_pd; i++ )\r
- cl_mutex_destroy( &hobul_p->pd_info_tbl[i].mutex );\r
- cl_free(hobul_p->pd_info_tbl);\r
- }\r
- if (hobul_p->qp_info_tbl)\r
- {\r
- for( i = 0; i < hobul_p->max_qp; i++ )\r
- cl_mutex_destroy( &hobul_p->qp_info_tbl[i].mutex );\r
- cl_free(hobul_p->qp_info_tbl);\r
- }\r
- if (hobul_p->cq_info_tbl)\r
- {\r
- for( i = 0; i < hobul_p->max_cq; i++ )\r
- {\r
- KeRemoveQueueDpc( &hobul_p->cq_info_tbl[i].dpc );\r
- cl_mutex_destroy( &hobul_p->cq_info_tbl[i].mutex );\r
- }\r
- cl_free(hobul_p->cq_info_tbl);\r
- }\r
- if (hobul_p) cl_free( hobul_p);\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-// ### Callbacks\r
-/////////////////////////////////////////////////////////\r
-\r
-ib_async_event_t\r
-mlnx_map_vapi_event_type(\r
- IN unsigned event_id,\r
- OUT ENUM_EVENT_CLASS *event_class_p)\r
-{\r
- switch (event_id)\r
- {\r
- case VAPI_QP_PATH_MIGRATED:\r
- if (event_class_p) *event_class_p = E_EV_QP;\r
- return IB_AE_QP_APM;\r
-\r
- case VAPI_QP_COMM_ESTABLISHED:\r
- if (event_class_p) *event_class_p = E_EV_QP;\r
- return IB_AE_QP_COMM;\r
-\r
- case VAPI_SEND_QUEUE_DRAINED:\r
- if (event_class_p) *event_class_p = E_EV_QP;\r
- return IB_AE_SQ_DRAINED;\r
-\r
- case VAPI_CQ_ERROR:\r
- if (event_class_p) *event_class_p = E_EV_CQ;\r
- return IB_AE_CQ_ERROR;\r
-\r
- case VAPI_LOCAL_WQ_INV_REQUEST_ERROR:\r
- if (event_class_p) *event_class_p = E_EV_QP;\r
- return IB_AE_WQ_REQ_ERROR;\r
-\r
- case VAPI_LOCAL_WQ_ACCESS_VIOL_ERROR:\r
- if (event_class_p) *event_class_p = E_EV_QP;\r
- return IB_AE_WQ_ACCESS_ERROR;\r
-\r
- case VAPI_LOCAL_WQ_CATASTROPHIC_ERROR:\r
- if (event_class_p) *event_class_p = E_EV_QP;\r
- return IB_AE_QP_FATAL;\r
-\r
- case VAPI_PATH_MIG_REQ_ERROR:\r
- if (event_class_p) *event_class_p = E_EV_QP;\r
- return IB_AE_QP_APM_ERROR;\r
-\r
- case VAPI_LOCAL_CATASTROPHIC_ERROR:\r
- if (event_class_p) *event_class_p = E_EV_CA;\r
- return IB_AE_LOCAL_FATAL;\r
-\r
- case VAPI_PORT_ERROR:\r
- /*\r
- * In tavor_hca\src\Hca\hcahal\tavor\eventp\event_irqh.c:\r
- * TAVOR_IF_EV_TYPE_PORT_ERR maps one of two port events:\r
- * - TAVOR_IF_SUB_EV_PORT_DOWN\r
- * - TAVOR_IF_SUB_EV_PORT_UP\r
- * \r
- * These map to (respectively)\r
- * - VAPI_PORT_ERROR\r
- * - VAPI_PORT_ACTIVE\r
- */\r
- if (event_class_p) *event_class_p = E_EV_CA;\r
- return IB_AE_PORT_DOWN; /* INIT, ARMED, DOWN */\r
-\r
- case VAPI_PORT_ACTIVE:\r
- if (event_class_p) *event_class_p = E_EV_CA;\r
- return IB_AE_PORT_ACTIVE; /* ACTIVE STATE */\r
-\r
- case VAPI_CLIENT_REREGISTER:\r
- if (event_class_p) *event_class_p = E_EV_CA;\r
- return IB_AE_CLIENT_REREGISTER; /* ACTIVE STATE */\r
-\r
- default:\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("FAIL to map %d (last known %d) returning %d\n",\r
- event_id, VAPI_PORT_ACTIVE, IB_AE_LOCAL_FATAL));\r
- if (event_class_p) *event_class_p = E_EV_CA;\r
- return IB_AE_LOCAL_FATAL;\r
- }\r
-}\r
-\r
-void\r
-mlnx_conv_vapi_event(\r
- IN HH_event_record_t *hh_event_p,\r
- IN ib_event_rec_t *ib_event_p,\r
- OUT ENUM_EVENT_CLASS *event_class_p)\r
-{\r
-\r
- // ib_event_p->context is handled by the caller\r
- //\r
- ib_event_p->type = mlnx_map_vapi_event_type(hh_event_p->etype, event_class_p);\r
-\r
- // no traps currently generated\r
- // ib_event_p->trap_info.lid = ;\r
- // ib_event_p->trap_info.port_guid = ;\r
- // ib_event_p->trap_info.port_num = hh_er;\r
-}\r
-\r
-void\r
-mlnx_async_cb(\r
- IN HH_hca_hndl_t hh_hndl,\r
- IN HH_event_record_t *hh_er_p,\r
- IN void *private_data)\r
-{\r
- u_int32_t obj_idx;\r
- mlnx_hob_t *hob_p;\r
-\r
- mlnx_cb_data_t cb_data;\r
- mlnx_cb_data_t *cb_data_p;\r
-\r
- CL_TRACE(MLNX_DBG_DIRECT, g_mlnx_dbg_lvl, ("ASYNC CB %p (0x%x)\n",\r
- private_data, (private_data) ? *(u_int32_t *)private_data : 0xB5));\r
-\r
- if (!private_data || !hh_er_p) return;\r
-\r
- obj_idx = *(u_int32_t *)private_data;\r
- if (obj_idx >= MLNX_NUM_HOBKL) return;\r
-\r
- hob_p = mlnx_hob_array + obj_idx;\r
-\r
- // g_mlnx_dpc2thread will be initialized as a module paramter (default - disabled(0))\r
- if (g_mlnx_dpc2thread)\r
- {\r
- cb_data_p = cl_malloc(sizeof(mlnx_cb_data_t));\r
- if (!cb_data_p) return;\r
-\r
- cb_data_p->hh_hndl = hh_hndl;\r
- cb_data_p->private_data = private_data;\r
- cl_memcpy(&cb_data_p->hh_er, hh_er_p, sizeof(HH_event_record_t));\r
- cb_data_p->async_item.pfn_callback = mlnx_async_dpc;\r
- cl_async_proc_queue(hob_p->async_proc_mgr_p, &cb_data_p->async_item );\r
- } else\r
- {\r
- cb_data_p = &cb_data;\r
-\r
- cb_data_p->hh_hndl = hh_hndl;\r
- cb_data_p->private_data = private_data;\r
- cl_memcpy(&cb_data_p->hh_er, hh_er_p, sizeof(HH_event_record_t));\r
- mlnx_async_dpc( &cb_data_p->async_item );\r
- }\r
-}\r
-\r
-static void\r
-mlnx_async_dpc(\r
- IN cl_async_proc_item_t *async_item_p )\r
-{\r
- HH_event_record_t *hh_er_p;\r
- u_int32_t obj_idx;\r
- mlnx_hob_t *hob_p;\r
- mlnx_hobul_t *hobul_p;\r
- mlnx_cb_data_t *cb_data_p;\r
-\r
- ENUM_EVENT_CLASS event_class;\r
- ib_event_rec_t event_r;\r
-\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("ASYNC DPC %p\n", async_item_p));\r
-\r
- cb_data_p = PARENT_STRUCT( async_item_p, mlnx_cb_data_t, async_item );\r
-\r
- if (!cb_data_p) return;\r
-\r
- hh_er_p = &cb_data_p->hh_er;\r
- obj_idx = *(u_int32_t *)cb_data_p->private_data;\r
- hob_p = mlnx_hob_array + obj_idx;\r
- hobul_p = mlnx_hobul_array[obj_idx];\r
-\r
- CL_TRACE(MLNX_DBG_DIRECT, g_mlnx_dbg_lvl, ("ASYNC DPC type %d ca_context %p\n",\r
- hh_er_p->etype, hob_p->ca_context));\r
-\r
- if (!hob_p ||\r
- !hobul_p ||\r
- !hob_p->hh_hndl ||\r
- !hob_p->async_cb_p)\r
- {\r
- goto cleanup;\r
- }\r
-\r
- cl_memclr(&event_r, sizeof(event_r));\r
- mlnx_conv_vapi_event(hh_er_p, &event_r, &event_class);\r
-\r
- switch(event_class)\r
- {\r
- case E_EV_CA:\r
- event_r.context = (void *)hob_p->ca_context;\r
- break;\r
-\r
- case E_EV_QP:\r
- {\r
- obj_idx = hh_er_p->event_modifier.qpn & hobul_p->qp_idx_mask;\r
- if (obj_idx < hobul_p->max_qp)\r
- event_r.context = (void *)hobul_p->qp_info_tbl[obj_idx].qp_context;\r
- else\r
- {\r
- CL_TRACE(MLNX_DBG_DIRECT, g_mlnx_dbg_lvl, ("ASYNC DPC bad qpn 0x%x max 0x%x\n", obj_idx, hobul_p->max_qp));\r
- goto cleanup;\r
- }\r
- }\r
- break;\r
-\r
- case E_EV_CQ:\r
- {\r
- obj_idx = hh_er_p->event_modifier.cq & hobul_p->cq_idx_mask;\r
- if (obj_idx < hobul_p->max_cq)\r
- event_r.context = (void *)hobul_p->cq_info_tbl[obj_idx].cq_context;\r
- else\r
- {\r
- CL_TRACE(MLNX_DBG_DIRECT, g_mlnx_dbg_lvl, ("ASYNC DPC bad cqn 0x%x max 0x%x\n", obj_idx, hobul_p->max_cq));\r
- goto cleanup;\r
- }\r
- }\r
- break;\r
-\r
- case E_EV_LAST:\r
- default:\r
- // CL_ASSERT(0); // This shouldn't happen\r
- CL_TRACE(MLNX_DBG_DIRECT, g_mlnx_dbg_lvl, ("ASYNC DPC unknown event_class 0x%x\n", event_class));\r
- break;\r
- }\r
-\r
- // Call the registered CB\r
- (*hob_p->async_cb_p)(&event_r);\r
- // Fall Through\r
-cleanup:\r
- if (g_mlnx_dpc2thread)\r
- {\r
- cl_free(cb_data_p);\r
- }\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-void\r
-mlnx_comp_cb(\r
- IN HH_hca_hndl_t hh_hndl,\r
- IN HH_cq_hndl_t hh_cq,\r
- IN void *private_data)\r
-{\r
-#if MLNX_COMP_MODEL\r
- u_int32_t cq_num;\r
- u_int32_t hca_idx;\r
- mlnx_hob_t *hob_p;\r
- mlnx_hobul_t *hobul_p;\r
-#if MLNX_COMP_MODEL == 2\r
- static uint32_t proc_num = 0;\r
-#endif\r
-\r
- CL_TRACE(MLNX_DBG_DIRECT, g_mlnx_dbg_lvl, ("COMP CB cq 0x%x %p\n", hh_cq, private_data));\r
-\r
- UNUSED_PARAM( hh_hndl );\r
-\r
- hca_idx = *(u_int32_t *)private_data;\r
- hob_p = mlnx_hob_array + hca_idx;\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- cq_num = hh_cq & hobul_p->cq_idx_mask;\r
-\r
- if (NULL != hob_p && NULL != hobul_p &&\r
- hob_p->hh_hndl && hob_p->comp_cb_p)\r
- {\r
- if (cq_num < hobul_p->max_cq)\r
- {\r
-#if MLNX_COMP_MODEL == 2\r
- KeSetTargetProcessorDpc( &hobul_p->cq_info_tbl[cq_num].dpc,\r
- (CCHAR)(proc_num++ % cl_proc_count()) );\r
-#endif /* MLNX_COMP_MODEL == 2 */\r
- KeInsertQueueDpc( &hobul_p->cq_info_tbl[cq_num].dpc,\r
- hob_p, NULL );\r
- }\r
- else\r
- {\r
- HCA_TRACE( HCA_DBG_ERROR, ("CQ index out of range!!!\n") );\r
- }\r
- }\r
-#else /* MLNX_COMP_MODEL */\r
- u_int32_t obj_idx;\r
- mlnx_hob_t *hob_p;\r
-\r
- mlnx_cb_data_t cb_data;\r
- mlnx_cb_data_t *cb_data_p;\r
-\r
- CL_TRACE(MLNX_DBG_DIRECT, g_mlnx_dbg_lvl, ("COMP CB cq 0x%x %p\n", hh_cq, private_data));\r
-\r
- if (!private_data) return;\r
-\r
- obj_idx = *(u_int32_t *)private_data;\r
- hob_p = mlnx_hob_array + obj_idx;\r
- if (!hob_p) return;\r
-\r
- if (g_mlnx_dpc2thread)\r
- {\r
- cb_data_p = cl_malloc(sizeof(mlnx_cb_data_t));\r
- if (!cb_data_p) return;\r
-\r
- cb_data_p->hh_hndl = hh_hndl;\r
- cb_data_p->hh_cq = hh_cq;\r
- cb_data_p->private_data = private_data;\r
-\r
- cb_data_p->async_item.pfn_callback = mlnx_comp_dpc;\r
-\r
- // Report completion through async_proc\r
- cl_async_proc_queue(hob_p->async_proc_mgr_p, &cb_data_p->async_item );\r
-\r
- } else\r
- {\r
- cb_data_p = &cb_data;\r
-\r
- cb_data_p->hh_hndl = hh_hndl;\r
- cb_data_p->hh_cq = hh_cq;\r
- cb_data_p->private_data = private_data;\r
-\r
- // Report completion directly from DPC (verbs should NOT sleep)\r
- mlnx_comp_dpc( &cb_data_p->async_item );\r
- }\r
-#endif /* MLNX_COMP_MODEL */\r
-}\r
-\r
-#if MLNX_COMP_MODEL\r
-static void\r
-mlnx_comp_dpc(\r
- IN PRKDPC p_dpc,\r
- IN void *context,\r
- IN void *arg1,\r
- IN void *unused )\r
-{\r
- mlnx_hob_t *hob_p = (mlnx_hob_t*)arg1;\r
- UNUSED_PARAM( p_dpc );\r
- UNUSED_PARAM( unused );\r
-\r
- hob_p->comp_cb_p( (void*)((cq_info_t*)context)->cq_context );\r
-}\r
-#else /* MLNX_COMP_MODEL */\r
-static void\r
-mlnx_comp_dpc(\r
- IN cl_async_proc_item_t *async_item_p )\r
-{\r
- u_int32_t cq_num;\r
- u_int32_t hca_idx;\r
- mlnx_hob_t *hob_p;\r
- mlnx_hobul_t *hobul_p;\r
- mlnx_cb_data_t *cb_data_p;\r
-\r
- CL_TRACE(MLNX_DBG_DIRECT, g_mlnx_dbg_lvl, ("COMP DPC %p\n", async_item_p));\r
-\r
- cb_data_p = PARENT_STRUCT( async_item_p, mlnx_cb_data_t, async_item );\r
- if (!cb_data_p) return;\r
-\r
- hca_idx = *(u_int32_t *)cb_data_p->private_data;\r
- hob_p = mlnx_hob_array + hca_idx;\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- cq_num = (u_int32_t)cb_data_p->hh_cq & hobul_p->cq_idx_mask;\r
-\r
- if (NULL != hob_p && NULL != hobul_p &&\r
- hob_p->hh_hndl && hob_p->comp_cb_p)\r
- {\r
- if (cq_num < hobul_p->max_cq)\r
- {\r
- (*hob_p->comp_cb_p)((void *)hobul_p->cq_info_tbl[cq_num].cq_context);\r
- }\r
- }\r
-\r
- if (g_mlnx_dpc2thread)\r
- {\r
- cl_free(cb_data_p);\r
- }\r
-}\r
-#endif /* MLNX_COMP_MODEL */\r
-\r
-// ### Conversions\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-VAPI_mrw_acl_t\r
-map_ibal_acl(\r
- IN ib_access_t ibal_acl)\r
-{\r
- VAPI_mrw_acl_t vapi_acl = 0;\r
-\r
- if (ibal_acl & IB_AC_RDMA_READ) vapi_acl |= VAPI_EN_REMOTE_READ;\r
- if (ibal_acl & IB_AC_RDMA_WRITE) vapi_acl |= VAPI_EN_REMOTE_WRITE;\r
- if (ibal_acl & IB_AC_ATOMIC) vapi_acl |= VAPI_EN_REMOTE_ATOM;\r
- if (ibal_acl & IB_AC_LOCAL_WRITE) vapi_acl |= VAPI_EN_LOCAL_WRITE;\r
- if (ibal_acl & IB_AC_MW_BIND) vapi_acl |= VAPI_EN_MEMREG_BIND;\r
-\r
- return vapi_acl;\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-ib_access_t\r
-map_vapi_acl(\r
- IN VAPI_mrw_acl_t vapi_acl)\r
-{\r
- ib_access_t ibal_acl = 0;\r
-\r
- if (vapi_acl & VAPI_EN_REMOTE_READ) ibal_acl |= IB_AC_RDMA_READ;\r
- if (vapi_acl & VAPI_EN_REMOTE_WRITE) ibal_acl |= IB_AC_RDMA_WRITE;\r
- if (vapi_acl & VAPI_EN_REMOTE_ATOM) ibal_acl |= IB_AC_ATOMIC;\r
- if (vapi_acl & VAPI_EN_LOCAL_WRITE) ibal_acl |= IB_AC_LOCAL_WRITE;\r
- if (vapi_acl & VAPI_EN_MEMREG_BIND) ibal_acl |= IB_AC_MW_BIND;\r
-\r
- return ibal_acl;\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-static VAPI_rdma_atom_acl_t \r
-map_ibal_qp_acl(\r
- IN ib_access_t ibal_acl)\r
-{\r
- VAPI_rdma_atom_acl_t vapi_qp_acl = 0;\r
-\r
- if (ibal_acl & IB_AC_RDMA_WRITE) vapi_qp_acl |= VAPI_EN_REM_WRITE;\r
- if (ibal_acl & IB_AC_RDMA_READ) vapi_qp_acl |= VAPI_EN_REM_READ;\r
- if (ibal_acl & IB_AC_ATOMIC) vapi_qp_acl |= VAPI_EN_REM_ATOMIC_OP;\r
-\r
- return vapi_qp_acl;\r
-\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-static ib_access_t\r
-map_vapi_qp_acl(\r
- IN VAPI_rdma_atom_acl_t vapi_qp_acl)\r
-{\r
- ib_access_t ibal_acl = IB_AC_LOCAL_WRITE;\r
-\r
- if (vapi_qp_acl & VAPI_EN_REM_WRITE) ibal_acl |= IB_AC_RDMA_WRITE;\r
- if (vapi_qp_acl & VAPI_EN_REM_READ) ibal_acl |= IB_AC_RDMA_READ;\r
- if (vapi_qp_acl & VAPI_EN_REM_ATOMIC_OP) ibal_acl |= IB_AC_ATOMIC;\r
-\r
- return ibal_acl;\r
-}\r
-\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-ib_api_status_t\r
-mlnx_lock_region(\r
- IN mlnx_mro_t *mro_p,\r
- IN boolean_t um_call )\r
-{\r
- MOSAL_iobuf_t old_iobuf;\r
-\r
- // Find context\r
- if( um_call )\r
- mro_p->mr_prot_ctx = MOSAL_get_current_prot_ctx();\r
- else\r
- mro_p->mr_prot_ctx = MOSAL_get_kernel_prot_ctx();\r
-\r
- // Save pointer to existing locked region.\r
- old_iobuf = mro_p->mr_iobuf;\r
-\r
- // Lock Region\r
- if (MT_OK != MOSAL_iobuf_register((MT_virt_addr_t)mro_p->mr_start,\r
- (MT_size_t)mro_p->mr_size,\r
- mro_p->mr_prot_ctx,\r
- mro_p->mr_mosal_perm,\r
- &mro_p->mr_iobuf,\r
- 0 ))\r
- {\r
- return IB_ERROR;\r
- }\r
-\r
- if( old_iobuf )\r
- {\r
- if( MT_OK != MOSAL_iobuf_deregister( old_iobuf ) )\r
- return IB_ERROR;\r
- }\r
-\r
- return IB_SUCCESS;\r
-}\r
-\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-ib_api_status_t\r
-mlnx_conv_ibal_mr_create(\r
- IN u_int32_t pd_idx,\r
- IN OUT mlnx_mro_t *mro_p,\r
- IN VAPI_mr_change_t change_flags,\r
- IN ib_mr_create_t const *p_mr_create,\r
- IN boolean_t um_call,\r
- OUT HH_mr_t *mr_props_p )\r
-{\r
- ib_api_status_t status;\r
-\r
- /* Set ACL information first since it is used to lock the region. */\r
- if( change_flags & VAPI_MR_CHANGE_ACL )\r
- {\r
- mro_p->mr_acl = map_ibal_acl( p_mr_create->access_ctrl );\r
- // This computation should be externalized by THH\r
- mro_p->mr_mosal_perm =\r
- MOSAL_PERM_READ |\r
- ((mro_p->mr_acl & VAPI_EN_LOCAL_WRITE) ? MOSAL_PERM_WRITE : 0);\r
- }\r
-\r
- if( change_flags & VAPI_MR_CHANGE_TRANS )\r
- {\r
- CL_TRACE(MLNX_DBG_MEM, g_mlnx_dbg_lvl, ("addr 0x%p size %"PRId64"\n", (void *)p_mr_create->vaddr, p_mr_create->length));\r
- // Build TPT entries\r
- mro_p->mr_start = (IB_virt_addr_t)p_mr_create->vaddr;\r
- mro_p->mr_size = p_mr_create->length;\r
- if (IB_SUCCESS != (status = mlnx_lock_region(mro_p, um_call)))\r
- {\r
- return status;\r
- }\r
- }\r
-\r
- /* Now fill in the MR properties. */\r
- mr_props_p->start = mro_p->mr_start;\r
- mr_props_p->size = mro_p->mr_size;\r
- mr_props_p->acl = mro_p->mr_acl;\r
- mr_props_p->pd = pd_idx;\r
-\r
- // Setup MTT info\r
- mr_props_p->tpt.tpt_type = HH_TPT_IOBUF;\r
- mr_props_p->tpt.tpt.iobuf = mro_p->mr_iobuf;\r
-\r
- return IB_SUCCESS;\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-// On entry mro_p->mr_start holds the pmr address\r
-/////////////////////////////////////////////////////////\r
-ib_api_status_t\r
-mlnx_conv_ibal_pmr_create(\r
- IN u_int32_t pd_idx,\r
- IN mlnx_mro_t *mro_p,\r
- IN ib_phys_create_t const *p_pmr_create,\r
- OUT HH_mr_t *mr_props_p )\r
-{\r
- VAPI_phy_addr_t* buf_lst = NULL;\r
- VAPI_size_t* sz_lst = NULL;\r
- u_int32_t i;\r
- u_int32_t page_shift = priv_ceil_log2(p_pmr_create->hca_page_size);\r
- u_int64_t page_mask = (1 << page_shift) - 1;\r
- u_int64_t tot_sz = 0;\r
-\r
- CL_TRACE(MLNX_DBG_MEM, g_mlnx_dbg_lvl, \r
- ("PRE: addr %p size 0x%"PRIx64" shift %d\n",\r
- (void *)(uintn_t)mro_p->mr_start, p_pmr_create->length, page_mask));\r
- mro_p->mr_start = (mro_p->mr_start & ~page_mask) | (p_pmr_create->buf_offset & page_mask);\r
- CL_TRACE(MLNX_DBG_MEM, g_mlnx_dbg_lvl, \r
- ("POST: addr %p\n", (void *)(uintn_t)mro_p->mr_start));\r
-\r
- mr_props_p->start = mro_p->mr_start;\r
- mr_props_p->size = p_pmr_create->length;\r
- mr_props_p->acl = map_ibal_acl(p_pmr_create->access_ctrl);\r
- mr_props_p->pd = pd_idx;\r
-\r
-#ifdef _DEBUG_\r
- mro_p->mr_size = mr_props_p->size;\r
-// mro_p->mr_first_page_addr = 0;\r
-// mro_p->mr_num_pages = (mro_p->mr_end >> PAGESHIFT) + 1 - (mro_p->mr_start >> PAGESHIFT);\r
-// CL_TRACE(MLNX_DBG_MEM, g_mlnx_dbg_lvl, ("1st pg addr 0x%p pages %d\n",\r
-// (void *)mro_p->mr_first_page_addr, p_pmr_create->num_bufs));\r
- CL_TRACE(MLNX_DBG_MEM, g_mlnx_dbg_lvl, ("1st phys addr 0x%"PRIx64" phys pages %d\n",\r
- p_pmr_create->range_array[0].base_addr, p_pmr_create->num_ranges));\r
-#endif\r
-\r
- // Build TPT entries\r
- if (!p_pmr_create->range_array)\r
- {\r
- return IB_INVALID_PARAMETER;\r
- }\r
-\r
- if (p_pmr_create->hca_page_size !=\r
- MT_DOWN_ALIGNX_PHYS(p_pmr_create->hca_page_size, page_shift))\r
- {\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("phys buf size is not page aligned\n"));\r
- return IB_INVALID_PARAMETER;\r
- }\r
-\r
- for (i = 0; i < p_pmr_create->num_ranges; i++)\r
- {\r
- uint64_t start_addr = p_pmr_create->range_array[i].base_addr;\r
- uint64_t end_addr = start_addr + p_pmr_create->range_array[i].size;\r
-\r
- if( end_addr < start_addr ) {\r
- CL_TRACE( CL_DBG_ERROR, g_mlnx_dbg_lvl, ("phys buf end < start\n") );\r
- return IB_INVALID_PARAMETER;\r
- }\r
-\r
- if (start_addr !=\r
- MT_DOWN_ALIGNX_PHYS(start_addr, page_shift))\r
- {\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("phys buf start adrs is not page aligned\n"));\r
- return IB_INVALID_PARAMETER;\r
- }\r
-\r
- tot_sz += p_pmr_create->range_array[i].size;\r
- }\r
-\r
- if( tot_sz < p_pmr_create->length + p_pmr_create->buf_offset )\r
- {\r
- HCA_TRACE_EXIT( HCA_DBG_ERROR, \r
- ("length(0x"PRIx64") + buf offset(0x"PRIx64") larger than sum "\r
- "of phys ranges(0x"PRIx64")\n",\r
- p_pmr_create->length, p_pmr_create->buf_offset, tot_sz) );\r
- return IB_INVALID_PARAMETER;\r
- }\r
-\r
- if( p_pmr_create->buf_offset > p_pmr_create->range_array[0].size )\r
- {\r
- HCA_TRACE_EXIT( HCA_DBG_ERROR,\r
- ("buf offset(0x%x) > than 1st phy range size(0x"PRIx64")\n",\r
- p_pmr_create->buf_offset, p_pmr_create->range_array[0].size) );\r
- return IB_INVALID_PARAMETER;\r
- }\r
-\r
- /* Memory registration must be done at PASSIVE_LEVEL, so paged memory here is fine. */\r
- buf_lst = (VAPI_phy_addr_t*)cl_pzalloc( sizeof(VAPI_phy_addr_t)*(p_pmr_create->num_ranges));\r
- if (!buf_lst)\r
- {\r
- HCA_TRACE_EXIT( HCA_DBG_ERROR,\r
- ("Failed to allocate range address list.\n") );\r
- return IB_INSUFFICIENT_MEMORY;\r
- }\r
-\r
-\r
- /* Memory registration must be done at PASSIVE_LEVEL, so paged memory here is fine. */\r
- sz_lst = (VAPI_size_t*)cl_pzalloc( sizeof(VAPI_size_t)*(p_pmr_create->num_ranges));\r
- if (!sz_lst)\r
- {\r
- cl_free( buf_lst );\r
- HCA_TRACE_EXIT( HCA_DBG_ERROR,\r
- ("Failed to allocate range size list.\n") );\r
- return IB_INSUFFICIENT_MEMORY;\r
- }\r
-\r
- for (i = 0; i < p_pmr_create->num_ranges; i++)\r
- {\r
- buf_lst[i] = p_pmr_create->range_array[i].base_addr;\r
- sz_lst[i] = p_pmr_create->range_array[i].size;\r
- }\r
-\r
- mr_props_p->tpt.tpt_type = HH_TPT_BUF;\r
- mr_props_p->tpt.num_entries = p_pmr_create->num_ranges;\r
- mr_props_p->tpt.tpt.buf_lst.buf_sz_lst = sz_lst;\r
- mr_props_p->tpt.tpt.buf_lst.phys_buf_lst = buf_lst; \r
- mr_props_p->tpt.tpt.buf_lst.iova_offset = p_pmr_create->buf_offset;\r
-\r
- return IB_SUCCESS;\r
-}\r
-\r
-\r
-u_int8_t\r
-mlnx_gid_to_index(\r
- IN HH_hca_hndl_t hh_hndl,\r
- IN u_int8_t port_num,\r
- IN u_int8_t *raw_gid)\r
-{\r
- ib_gid_t *gid_table_p = NULL;\r
- u_int8_t index = 0; // default return value\r
- u_int8_t i;\r
-\r
- gid_table_p = cl_zalloc( 64*sizeof(ib_gid_t));\r
-\r
- mlnx_get_hca_gid_tbl(hh_hndl, port_num, 64, gid_table_p);\r
-\r
- for (i = 0; i < 64; i++)\r
- {\r
- if (!cl_memcmp(raw_gid, gid_table_p[i].raw, sizeof(ib_gid_t)))\r
- {\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("1: found GID at index %d\n", i));\r
- index = i;\r
- break;\r
- }\r
- }\r
-\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("2: found GID at index %d\n", index));\r
-\r
- cl_free( gid_table_p);\r
- return index;\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-void\r
-mlnx_conv_ibal_av(\r
- IN HH_hca_hndl_t hh_hndl,\r
- IN const ib_av_attr_t *ibal_av_p,\r
- OUT VAPI_ud_av_t *vapi_av_p)\r
-{\r
- vapi_av_p->port = ibal_av_p->port_num;\r
- vapi_av_p->sl = ibal_av_p->sl;\r
- vapi_av_p->dlid = cl_ntoh16 (ibal_av_p->dlid);\r
-\r
- vapi_av_p->static_rate =\r
- (ibal_av_p->static_rate == IB_PATH_RECORD_RATE_10_GBS? 0 : 3);\r
- ib_grh_get_ver_class_flow( ibal_av_p->grh.ver_class_flow, NULL,\r
- &vapi_av_p->traffic_class, &vapi_av_p->flow_label );\r
- vapi_av_p->src_path_bits = ibal_av_p->path_bits; // PATH:\r
- //vapi_av_p->src_path_bits = 0;\r
-\r
- /* For global destination or Multicast address:*/\r
- if (ibal_av_p->grh_valid)\r
- {\r
- vapi_av_p->grh_flag = TRUE;\r
- vapi_av_p->hop_limit = ibal_av_p->grh.hop_limit;\r
- // CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("raw %p, &raw %p\n", ibal_av_p->grh.src_gid.raw, &ibal_av_p->grh.src_gid.raw));\r
- vapi_av_p->sgid_index = mlnx_gid_to_index(hh_hndl, ibal_av_p->port_num, (u_int8_t *)ibal_av_p->grh.src_gid.raw);\r
- cl_memcpy(vapi_av_p->dgid, ibal_av_p->grh.dest_gid.raw, sizeof(vapi_av_p->dgid));\r
- }\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-void\r
-mlnx_conv_vapi_av(\r
- IN HH_hca_hndl_t hh_hndl,\r
- IN const VAPI_ud_av_t *vapi_av_p,\r
- OUT ib_av_attr_t *ibal_av_p)\r
-{\r
- uint8_t ver;\r
-\r
- ibal_av_p->port_num = vapi_av_p->port;\r
- ibal_av_p->sl = vapi_av_p->sl;\r
- ibal_av_p->dlid = cl_ntoh16(vapi_av_p->dlid);\r
-\r
- /* For global destination or Multicast address:*/\r
- ibal_av_p->grh_valid = vapi_av_p->grh_flag;\r
-\r
- ver = 2;\r
- ibal_av_p->grh.ver_class_flow = ib_grh_set_ver_class_flow( ver,\r
- vapi_av_p->traffic_class,\r
- vapi_av_p->flow_label);\r
- ibal_av_p->grh.hop_limit = vapi_av_p->hop_limit;\r
-\r
- THH_hob_get_sgid(hh_hndl,\r
- vapi_av_p->port,\r
- vapi_av_p->sgid_index,\r
- &ibal_av_p->grh.src_gid.raw);\r
-\r
- cl_memcpy(ibal_av_p->grh.dest_gid.raw, vapi_av_p->dgid, sizeof(vapi_av_p->dgid));\r
-\r
- ibal_av_p->static_rate = (vapi_av_p->static_rate?\r
- IB_PATH_RECORD_RATE_2_5_GBS : IB_PATH_RECORD_RATE_10_GBS);\r
- ibal_av_p->path_bits = vapi_av_p->src_path_bits;\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-int\r
-mlnx_map_vapi_cqe_status(\r
- IN VAPI_wc_status_t vapi_status)\r
-{\r
- switch (vapi_status)\r
- {\r
- case IB_COMP_SUCCESS: return IB_WCS_SUCCESS;\r
- case IB_COMP_LOC_LEN_ERR: return IB_WCS_LOCAL_LEN_ERR;\r
- case IB_COMP_LOC_QP_OP_ERR: return IB_WCS_LOCAL_OP_ERR;\r
- case IB_COMP_LOC_PROT_ERR: return IB_WCS_LOCAL_PROTECTION_ERR;\r
- case IB_COMP_WR_FLUSH_ERR: return IB_WCS_WR_FLUSHED_ERR;\r
- case IB_COMP_MW_BIND_ERR: return IB_WCS_MEM_WINDOW_BIND_ERR;\r
- case IB_COMP_REM_INV_REQ_ERR: return IB_WCS_REM_INVALID_REQ_ERR;\r
- case IB_COMP_REM_ACCESS_ERR: return IB_WCS_REM_ACCESS_ERR;\r
- case IB_COMP_REM_OP_ERR: return IB_WCS_REM_OP_ERR;\r
- case IB_COMP_RETRY_EXC_ERR: return IB_WCS_TIMEOUT_RETRY_ERR;\r
- case IB_COMP_RNR_RETRY_EXC_ERR: return IB_WCS_RNR_RETRY_ERR;\r
- case IB_COMP_REM_ABORT_ERR: return IB_WCS_REM_ACCESS_ERR; // ???\r
- case IB_COMP_FATAL_ERR: return IB_WCS_REM_ACCESS_ERR; // ???\r
- case IB_COMP_GENERAL_ERR: return IB_WCS_REM_ACCESS_ERR; // ???\r
- default:\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("FAIL to map %d (last known %d) returning %d\n",\r
- vapi_status, IB_COMP_GENERAL_ERR, IB_WCS_REM_ACCESS_ERR));\r
- return IB_WCS_REM_ACCESS_ERR;\r
- }\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-int\r
-mlnx_map_vapi_cqe_type(\r
- IN VAPI_cqe_opcode_t opcode)\r
-{\r
- switch (opcode)\r
- {\r
- case VAPI_CQE_SQ_SEND_DATA: return IB_WC_SEND;\r
- case VAPI_CQE_SQ_RDMA_WRITE: return IB_WC_RDMA_WRITE;\r
- case VAPI_CQE_SQ_RDMA_READ: return IB_WC_RDMA_READ;\r
- case VAPI_CQE_SQ_COMP_SWAP: return IB_WC_COMPARE_SWAP;\r
- case VAPI_CQE_SQ_FETCH_ADD: return IB_WC_FETCH_ADD;\r
- case VAPI_CQE_SQ_BIND_MRW: return IB_WC_MW_BIND;\r
- case VAPI_CQE_RQ_SEND_DATA: return IB_WC_RECV;\r
- case VAPI_CQE_RQ_RDMA_WITH_IMM: return IB_WC_RECV_RDMA_WRITE;\r
- default:\r
- return IB_WC_SEND;\r
- }\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-// Map Remote Node Addr Type\r
-/////////////////////////////////////////////////////////\r
-int\r
-mlnx_map_vapi_rna_type(\r
- IN VAPI_remote_node_addr_type_t rna)\r
-{\r
- switch (rna)\r
- {\r
- case VAPI_RNA_UD: return IB_QPT_UNRELIABLE_DGRM;\r
- case VAPI_RNA_RAW_ETY: return IB_QPT_RAW_ETHER;\r
- case VAPI_RNA_RAW_IPV6: return IB_QPT_RAW_IPV6;\r
- default:\r
- return IB_QPT_RELIABLE_CONN;\r
- }\r
-}\r
-\r
-//////////////////////////////////////////////////////////////\r
-// Convert from VAPI memory-region attributes to IBAL \r
-//////////////////////////////////////////////////////////////\r
-void\r
-mlnx_conv_vapi_mr_attr(\r
- IN ib_pd_handle_t pd_h,\r
- IN HH_mr_info_t *mr_info_p,\r
- OUT ib_mr_attr_t *mr_query_p)\r
-{\r
- mr_query_p->h_pd = pd_h;\r
- mr_query_p->local_lb = mr_info_p->local_start;\r
- mr_query_p->local_ub = mr_info_p->local_start + mr_info_p->local_size;\r
- mr_query_p->remote_lb = mr_info_p->remote_start;\r
- mr_query_p->remote_ub = mr_info_p->remote_start + mr_info_p->remote_size;\r
-\r
- mr_query_p->access_ctrl = map_vapi_acl(mr_info_p->acl);\r
- mr_query_p->lkey = mr_info_p->lkey;\r
- mr_query_p->rkey = cl_hton32(mr_info_p->rkey);\r
-}\r
-\r
-//////////////////////////////////////////////////////////////\r
-// Convert from IBAL memory-window bind request to VAPI \r
-//////////////////////////////////////////////////////////////\r
-void\r
-mlnx_conv_bind_req(\r
- IN HHUL_qp_hndl_t hhul_qp_hndl,\r
- IN ib_bind_wr_t* const p_mw_bind,\r
- OUT HHUL_mw_bind_t *bind_prop_p)\r
-{\r
- bind_prop_p->qp = hhul_qp_hndl;\r
- bind_prop_p->id = p_mw_bind->wr_id;\r
- bind_prop_p->acl = map_ibal_acl(p_mw_bind->access_ctrl);\r
- bind_prop_p->size = p_mw_bind->local_ds.length;\r
- bind_prop_p->start = (VAPI_virt_addr_t)(MT_virt_addr_t)p_mw_bind->local_ds.vaddr;\r
- bind_prop_p->mr_lkey = p_mw_bind->local_ds.lkey;\r
- bind_prop_p->comp_type = \r
- (p_mw_bind->send_opt & IB_SEND_OPT_SIGNALED) ? VAPI_SIGNALED : VAPI_UNSIGNALED;\r
-}\r
-\r
-\r
-/////////////////////////////////////////////////////////\r
-// Map IBAL qp type to VAPI transport and special qp_type\r
-/////////////////////////////////////////////////////////\r
-int\r
-mlnx_map_ibal_qp_type(\r
- IN ib_qp_type_t ibal_qpt,\r
- OUT VAPI_special_qp_t *vapi_qp_type_p)\r
-{\r
- switch (ibal_qpt)\r
- {\r
- case IB_QPT_RELIABLE_CONN:\r
- if (vapi_qp_type_p) *vapi_qp_type_p = VAPI_REGULAR_QP;\r
- return IB_TS_RC;\r
-\r
- case IB_QPT_UNRELIABLE_CONN:\r
- if (vapi_qp_type_p) *vapi_qp_type_p = VAPI_REGULAR_QP;\r
- return IB_TS_UC;\r
-\r
- case IB_QPT_UNRELIABLE_DGRM:\r
- if (vapi_qp_type_p) *vapi_qp_type_p = VAPI_REGULAR_QP;\r
- return IB_TS_UD;\r
-\r
- case IB_QPT_QP0:\r
- if (vapi_qp_type_p) *vapi_qp_type_p = VAPI_SMI_QP;\r
- return IB_TS_UD;\r
-\r
- case IB_QPT_QP1:\r
- if (vapi_qp_type_p) *vapi_qp_type_p = VAPI_GSI_QP;\r
- return IB_TS_UD;\r
-\r
- case IB_QPT_RAW_IPV6:\r
- if (vapi_qp_type_p) *vapi_qp_type_p = VAPI_RAW_IPV6_QP; // TBD: ??\r
- return IB_TS_RAW;\r
-\r
- case IB_QPT_RAW_ETHER:\r
- if (vapi_qp_type_p) *vapi_qp_type_p = VAPI_RAW_ETY_QP; // TBD: ??\r
- return IB_TS_RAW;\r
-\r
- case IB_QPT_MAD:\r
- if (vapi_qp_type_p) *vapi_qp_type_p = VAPI_GSI_QP;\r
- return IB_TS_UD;\r
-\r
- case IB_QPT_QP0_ALIAS:\r
- if (vapi_qp_type_p) *vapi_qp_type_p = VAPI_SMI_QP;\r
- return IB_TS_UD;\r
-\r
- case IB_QPT_QP1_ALIAS:\r
- if (vapi_qp_type_p) *vapi_qp_type_p = VAPI_GSI_QP;\r
- return IB_TS_UD;\r
-\r
- default:\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("FAIL to map ibal_qp_type %d (last known %d) returning %d\n",\r
- ibal_qpt, IB_QPT_QP1_ALIAS, IB_TS_RAW));\r
- if (vapi_qp_type_p) *vapi_qp_type_p = VAPI_RAW_ETY_QP;\r
- return IB_TS_RAW;\r
- }\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-// QP and CQ value must be handled by caller\r
-/////////////////////////////////////////////////////////\r
-void\r
-mlnx_conv_qp_create_attr(\r
- IN const ib_qp_create_t *create_attr_p,\r
- OUT HHUL_qp_init_attr_t *init_attr_p,\r
- OUT VAPI_special_qp_t *vapi_qp_type_p)\r
-{\r
- init_attr_p->ts_type = mlnx_map_ibal_qp_type(create_attr_p->qp_type, vapi_qp_type_p);\r
-\r
- init_attr_p->qp_cap.max_oust_wr_sq = create_attr_p->sq_depth;\r
- init_attr_p->qp_cap.max_oust_wr_rq = create_attr_p->rq_depth;\r
- init_attr_p->qp_cap.max_sg_size_sq = create_attr_p->sq_sge;\r
- init_attr_p->qp_cap.max_sg_size_rq = create_attr_p->rq_sge;\r
-\r
- init_attr_p->sq_sig_type = (create_attr_p->sq_signaled) ? VAPI_SIGNAL_ALL_WR : VAPI_SIGNAL_REQ_WR;\r
- init_attr_p->rq_sig_type = VAPI_SIGNAL_ALL_WR;\r
-\r
- init_attr_p->srq = HHUL_INVAL_SRQ_HNDL;\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-// NOTE: ibal_qp_state is non linear - so we cannot use a LUT\r
-/////////////////////////////////////////////////////////\r
-VAPI_qp_state_t\r
-mlnx_map_ibal_qp_state(\r
- IN ib_qp_state_t ibal_qp_state)\r
-{\r
- VAPI_qp_state_t vapi_qp_state = VAPI_RESET;\r
-\r
- if (ibal_qp_state & IB_QPS_RESET) vapi_qp_state = VAPI_RESET;\r
- else if (ibal_qp_state & IB_QPS_INIT) vapi_qp_state = VAPI_INIT;\r
- else if (ibal_qp_state & IB_QPS_RTR) vapi_qp_state = VAPI_RTR;\r
- else if (ibal_qp_state & IB_QPS_RTS) vapi_qp_state = VAPI_RTS;\r
- else if (ibal_qp_state & IB_QPS_SQD) vapi_qp_state = VAPI_SQD;\r
- else if (ibal_qp_state & IB_QPS_SQERR) vapi_qp_state = VAPI_SQE;\r
- else if (ibal_qp_state & IB_QPS_ERROR) vapi_qp_state = VAPI_ERR;\r
-\r
- return vapi_qp_state;\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-ib_qp_state_t\r
-mlnx_map_vapi_qp_state(\r
- IN VAPI_qp_state_t vapi_qp_state)\r
-{\r
- switch (vapi_qp_state)\r
- {\r
- case VAPI_RESET: return IB_QPS_RESET;\r
- case VAPI_INIT: return IB_QPS_INIT;\r
- case VAPI_RTR: return IB_QPS_RTR;\r
- case VAPI_RTS: return IB_QPS_RTS;\r
- case VAPI_SQD: return IB_QPS_SQD;\r
- case VAPI_SQE: return IB_QPS_SQERR;\r
- case VAPI_ERR: return IB_QPS_ERROR;\r
- // TBD: IB_QPS_SQD_DRAINING\r
- // TBD: IB_QPS_SQD_DRAINED\r
- default:\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("FAIL to map vapi_qp_state %d (last known %d) returning %d\n",\r
- vapi_qp_state, VAPI_ERR, IB_QPS_INIT));\r
- return IB_QPS_INIT;\r
- }\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-ib_apm_state_t\r
-mlnx_map_vapi_apm_state(\r
- IN VAPI_mig_state_t vapi_apm_state)\r
-{\r
- switch (vapi_apm_state)\r
- {\r
- case VAPI_MIGRATED: return IB_APM_MIGRATED;\r
- case VAPI_REARM: return IB_APM_REARM;\r
- case VAPI_ARMED: return IB_APM_ARMED;\r
-\r
- default:\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("FAIL to map vapi_apm_state %d (last known %d) returning %d\n",\r
- vapi_apm_state, VAPI_ARMED, 0));\r
- return 0;\r
- }\r
-}\r
-\r
-#if 0\r
-/////////////////////////////////////////////////////////\r
-// UNUSED: IBAL uses same encoding as THH\r
-/////////////////////////////////////////////////////////\r
-static\r
-u_int32_t ibal_mtu_to_vapi(u_int32_t ibal_mtu)\r
-{\r
- u_int32_t mtu = 0;\r
-\r
- // MTU256=1, MTU512=2, MTU1024=3\r
- while (ibal_mtu >>= 1) mtu++;\r
- return mtu - 7;\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-static\r
-u_int32_t vapi_mtu_to_ibal(u_int32_t vapi_mtu)\r
-{\r
- return (1 << (vapi_mtu + 7));\r
-}\r
-#endif\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-void\r
-mlnx_conv_vapi_qp_attr(\r
- IN HH_hca_hndl_t hh_hndl,\r
- IN VAPI_qp_attr_t *hh_qp_attr_p,\r
- OUT ib_qp_attr_t *qp_attr_p)\r
-{\r
- qp_attr_p->access_ctrl = map_vapi_qp_acl(hh_qp_attr_p->remote_atomic_flags);\r
- qp_attr_p->pkey_index = (uint16_t)hh_qp_attr_p->pkey_ix;\r
- qp_attr_p->sq_depth = hh_qp_attr_p->cap.max_oust_wr_sq;\r
- qp_attr_p->rq_depth = hh_qp_attr_p->cap.max_oust_wr_rq;\r
- qp_attr_p->sq_sge = hh_qp_attr_p->cap.max_sg_size_sq;\r
- qp_attr_p->rq_sge = hh_qp_attr_p->cap.max_sg_size_rq;\r
- qp_attr_p->sq_max_inline = hh_qp_attr_p->cap.max_inline_data_sq;\r
- qp_attr_p->init_depth = hh_qp_attr_p->ous_dst_rd_atom; // outstanding outgoing\r
- qp_attr_p->resp_res = hh_qp_attr_p->qp_ous_rd_atom; // outstanding as target (in)\r
-\r
- qp_attr_p->num = cl_ntoh32(hh_qp_attr_p->qp_num);\r
- CL_TRACE(MLNX_DBG_QPN, g_mlnx_dbg_lvl, ("ibal_qpn 0x%x = hh_qpn 0x%x\n",\r
- qp_attr_p->num,\r
- hh_qp_attr_p->qp_num));\r
-\r
- qp_attr_p->dest_num = cl_ntoh32(hh_qp_attr_p->dest_qp_num);\r
- CL_TRACE(MLNX_DBG_QPN, g_mlnx_dbg_lvl, ("ibal_dest 0x%x = hh_dest 0x%x\n",\r
- qp_attr_p->dest_num,\r
- hh_qp_attr_p->dest_qp_num));\r
- qp_attr_p->qkey = cl_ntoh32 (hh_qp_attr_p->qkey);\r
-\r
- qp_attr_p->sq_psn = cl_ntoh32 (hh_qp_attr_p->sq_psn);\r
- qp_attr_p->rq_psn = cl_ntoh32 (hh_qp_attr_p->rq_psn);\r
-\r
- qp_attr_p->primary_port = hh_qp_attr_p->port;\r
- qp_attr_p->alternate_port = hh_qp_attr_p->alt_port;\r
-\r
- qp_attr_p->state = mlnx_map_vapi_qp_state(hh_qp_attr_p->qp_state);\r
- qp_attr_p->apm_state = mlnx_map_vapi_apm_state(hh_qp_attr_p->path_mig_state);\r
-\r
- mlnx_conv_vapi_av(hh_hndl, &hh_qp_attr_p->av, &qp_attr_p->primary_av);\r
- qp_attr_p->primary_av.conn.path_mtu = (u_int8_t)hh_qp_attr_p->path_mtu;\r
- qp_attr_p->primary_av.conn.local_ack_timeout = hh_qp_attr_p->timeout; \r
- qp_attr_p->primary_av.conn.seq_err_retry_cnt = hh_qp_attr_p->retry_count;\r
- qp_attr_p->primary_av.conn.rnr_retry_cnt = hh_qp_attr_p->rnr_retry;\r
-\r
- mlnx_conv_vapi_av(hh_hndl, &hh_qp_attr_p->alt_av, &qp_attr_p->alternate_av);\r
- qp_attr_p->alternate_av.conn. path_mtu = (u_int8_t)hh_qp_attr_p->path_mtu;\r
- qp_attr_p->alternate_av.conn.local_ack_timeout = hh_qp_attr_p->timeout;\r
- qp_attr_p->alternate_av.conn.seq_err_retry_cnt = hh_qp_attr_p->retry_count;\r
- qp_attr_p->alternate_av.conn.rnr_retry_cnt = hh_qp_attr_p->rnr_retry;\r
-}\r
-#if 0\r
-XXX:\r
-QP_ATTR_QP_STATE\r
-QP_ATTR_EN_SQD_ASYN_NOTIF\r
-QP_ATTR_QP_NUM\r
-+ QP_ATTR_REMOTE_ATOMIC_FLAGS\r
-+ QP_ATTR_PKEY_IX\r
-+ QP_ATTR_PORT\r
-+ QP_ATTR_QKEY\r
-+ QP_ATTR_RQ_PSN\r
-+ QP_ATTR_AV\r
-\r
-QP_ATTR_PATH_MTU\r
-+ QP_ATTR_TIMEOUT\r
-+ QP_ATTR_RETRY_COUNT\r
-+ QP_ATTR_RNR_RETRY\r
-QP_ATTR_QP_OUS_RD_ATOM\r
-\r
-- QP_ATTR_ALT_PATH\r
-\r
-+ QP_ATTR_MIN_RNR_TIMER\r
-QP_ATTR_SQ_PSN\r
-QP_ATTR_OUS_DST_RD_ATOM\r
-QP_ATTR_PATH_MIG_STATE\r
-QP_ATTR_CAP\r
-#endif\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-ib_api_status_t\r
-mlnx_conv_qp_modify_attr(\r
- IN HH_hca_hndl_t hh_hndl,\r
- IN ib_qp_type_t qp_type,\r
- IN const ib_qp_mod_t *modify_attr_p,\r
- OUT VAPI_qp_attr_t *qp_attr_p, \r
- OUT VAPI_qp_attr_mask_t *attr_mask_p)\r
-{\r
-\r
- qp_attr_p->qp_state = mlnx_map_ibal_qp_state(modify_attr_p->req_state);\r
- *attr_mask_p = QP_ATTR_QP_STATE;\r
-\r
- switch(modify_attr_p->req_state)\r
- {\r
- case IB_QPS_RESET:\r
- break;\r
-\r
- case IB_QPS_INIT:\r
- *attr_mask_p |= QP_ATTR_PORT |\r
- QP_ATTR_QKEY |\r
- QP_ATTR_PKEY_IX ;\r
-\r
- qp_attr_p->port = modify_attr_p->state.init.primary_port;\r
- qp_attr_p->qkey = cl_ntoh32 (modify_attr_p->state.init.qkey);\r
- qp_attr_p->pkey_ix = modify_attr_p->state.init.pkey_index;\r
- if (IB_QPT_RELIABLE_CONN == qp_type)\r
- {\r
- *attr_mask_p |= QP_ATTR_REMOTE_ATOMIC_FLAGS;\r
- qp_attr_p->remote_atomic_flags = map_ibal_qp_acl(modify_attr_p->state.init.access_ctrl);\r
- } else\r
- {\r
- qp_attr_p->remote_atomic_flags = 0;\r
- }\r
- break;\r
-\r
- case IB_QPS_RTR:\r
- /* VAPI doesn't support modifying the WQE depth ever. */\r
- if( modify_attr_p->state.rtr.opts & IB_MOD_QP_SQ_DEPTH ||\r
- modify_attr_p->state.rtr.opts & IB_MOD_QP_RQ_DEPTH )\r
- {\r
- return IB_UNSUPPORTED;\r
- }\r
-\r
- *attr_mask_p |= QP_ATTR_RQ_PSN |\r
- QP_ATTR_DEST_QP_NUM |\r
- QP_ATTR_QP_OUS_RD_ATOM |\r
- QP_ATTR_MIN_RNR_TIMER |\r
- QP_ATTR_AV ;\r
-\r
- qp_attr_p->rq_psn = cl_ntoh32 (modify_attr_p->state.rtr.rq_psn);\r
- qp_attr_p->dest_qp_num = cl_ntoh32 (modify_attr_p->state.rtr.dest_qp);\r
- qp_attr_p->qp_ous_rd_atom = modify_attr_p->state.rtr.resp_res;\r
-\r
- qp_attr_p->min_rnr_timer = modify_attr_p->state.rtr.rnr_nak_timeout;\r
-\r
-#if 1\r
- CL_TRACE(MLNX_DBG_QPN, g_mlnx_dbg_lvl, ("modify_qp: hh_dest 0x%x = ibal_dest 0x%x\n",\r
- qp_attr_p->dest_qp_num, modify_attr_p->state.rtr.dest_qp));\r
-#endif\r
-\r
- // Convert primary RC AV (mandatory)\r
- cl_memclr(&qp_attr_p->av, sizeof(VAPI_ud_av_t));\r
- mlnx_conv_ibal_av(hh_hndl,\r
- &modify_attr_p->state.rtr.primary_av, &qp_attr_p->av);\r
-\r
- if (IB_QPT_RELIABLE_CONN == qp_type)\r
- {\r
- *attr_mask_p |= QP_ATTR_PATH_MTU;\r
- qp_attr_p->path_mtu = modify_attr_p->state.rtr.primary_av.conn.path_mtu; // MTU\r
- *attr_mask_p |= QP_ATTR_TIMEOUT;\r
- qp_attr_p->timeout = modify_attr_p->state.rtr.primary_av.conn.local_ack_timeout; // XXX: conv\r
- *attr_mask_p |= QP_ATTR_RETRY_COUNT;\r
- qp_attr_p->retry_count = modify_attr_p->state.rtr.primary_av.conn.seq_err_retry_cnt;\r
- *attr_mask_p |= QP_ATTR_RNR_RETRY;\r
- qp_attr_p->rnr_retry = modify_attr_p->state.rtr.primary_av.conn.rnr_retry_cnt;\r
- }\r
-\r
- // Convert Remote Atomic Flags\r
- if (modify_attr_p->state.rtr.opts & IB_MOD_QP_ACCESS_CTRL)\r
- {\r
- *attr_mask_p |= QP_ATTR_REMOTE_ATOMIC_FLAGS;\r
- qp_attr_p->remote_atomic_flags = map_ibal_qp_acl(modify_attr_p->state.rtr.access_ctrl);\r
- }\r
-\r
- // Convert alternate RC AV\r
- if (modify_attr_p->state.rtr.opts & IB_MOD_QP_ALTERNATE_AV)\r
- {\r
- *attr_mask_p |= QP_ATTR_ALT_PATH;\r
- cl_memclr(&qp_attr_p->alt_av, sizeof(VAPI_ud_av_t));\r
- mlnx_conv_ibal_av(hh_hndl,\r
- &modify_attr_p->state.rtr.alternate_av, &qp_attr_p->alt_av);\r
-\r
- if (IB_QPT_RELIABLE_CONN == qp_type)\r
- {\r
- qp_attr_p->alt_timeout = modify_attr_p->state.rtr.alternate_av.conn.local_ack_timeout; // XXX: conv\r
-#if 0\r
- /* Incompliant with spec 1.1! Data already set before */\r
- qp_attr_p->retry_count = modify_attr_p->state.rtr.alternate_av.conn.seq_err_retry_cnt;\r
- qp_attr_p->rnr_retry = modify_attr_p->state.rtr.alternate_av.conn.rnr_retry_cnt;\r
-#endif\r
- }\r
- }\r
- break;\r
-\r
- case IB_QPS_RTS:\r
- /* VAPI doesn't support modifying the WQE depth ever. */\r
- if( modify_attr_p->state.rts.opts & IB_MOD_QP_SQ_DEPTH ||\r
- modify_attr_p->state.rts.opts & IB_MOD_QP_RQ_DEPTH )\r
- {\r
- return IB_UNSUPPORTED;\r
- }\r
-\r
- *attr_mask_p |= QP_ATTR_SQ_PSN |\r
- QP_ATTR_RETRY_COUNT |\r
- QP_ATTR_RNR_RETRY |\r
- QP_ATTR_TIMEOUT|\r
- QP_ATTR_OUS_DST_RD_ATOM |\r
- QP_ATTR_MIN_RNR_TIMER;\r
-\r
- qp_attr_p->sq_psn = cl_ntoh32 (modify_attr_p->state.rts.sq_psn);\r
-\r
- if (modify_attr_p->state.rts.opts & IB_MOD_QP_ACCESS_CTRL)\r
- {\r
- *attr_mask_p |= QP_ATTR_REMOTE_ATOMIC_FLAGS;\r
- qp_attr_p->remote_atomic_flags = map_ibal_qp_acl(modify_attr_p->state.rts.access_ctrl);\r
- }\r
-\r
- qp_attr_p->timeout = modify_attr_p->state.rts.local_ack_timeout; // XXX: conv\r
- qp_attr_p->ous_dst_rd_atom = modify_attr_p->state.rts.init_depth;\r
- qp_attr_p->retry_count = modify_attr_p->state.rts.retry_cnt;\r
- qp_attr_p->rnr_retry = modify_attr_p->state.rts.rnr_retry_cnt;\r
- qp_attr_p->min_rnr_timer = modify_attr_p->state.rts.rnr_nak_timeout;\r
-\r
- // Update the responder resources for RDMA/ATOMIC (optional for SQD->RTS)\r
- if (modify_attr_p->state.rts.opts & IB_MOD_QP_RESP_RES) {\r
- *attr_mask_p |= QP_ATTR_QP_OUS_RD_ATOM;\r
- qp_attr_p->qp_ous_rd_atom = modify_attr_p->state.rts.resp_res;\r
- }\r
-\r
- // Convert alternate RC AV\r
- if (modify_attr_p->state.rts.opts & IB_MOD_QP_ALTERNATE_AV)\r
- {\r
- *attr_mask_p |= QP_ATTR_ALT_PATH;\r
- cl_memclr(&qp_attr_p->alt_av, sizeof(VAPI_ud_av_t));\r
- mlnx_conv_ibal_av(hh_hndl,\r
- &modify_attr_p->state.rts.alternate_av, &qp_attr_p->alt_av);\r
- if (IB_QPT_RELIABLE_CONN == qp_type)\r
- {\r
- qp_attr_p->alt_timeout = modify_attr_p->state.rts.alternate_av.conn.local_ack_timeout; // XXX: conv\r
-#if 0\r
- /* Incompliant with spec 1.1! Data already set before */\r
- qp_attr_p->retry_count = modify_attr_p->state.rts.alternate_av.conn.seq_err_retry_cnt;\r
- qp_attr_p->rnr_retry = modify_attr_p->state.rts.alternate_av.conn.rnr_retry_cnt;\r
-#endif\r
- }\r
- }\r
- break;\r
-\r
- // TBD: The following are treated equally (SQ Drain)\r
- case IB_QPS_SQD:\r
- case IB_QPS_SQD_DRAINING:\r
- case IB_QPS_SQD_DRAINED:\r
- *attr_mask_p |= QP_ATTR_EN_SQD_ASYN_NOTIF;\r
- qp_attr_p->en_sqd_asyn_notif = (MT_bool)modify_attr_p->state.sqd.sqd_event;\r
- break;\r
-\r
- case IB_QPS_SQERR:\r
- case IB_QPS_ERROR:\r
- case IB_QPS_TIME_WAIT:\r
- default:\r
- break;\r
- }\r
- CL_TRACE(MLNX_DBG_QPN, g_mlnx_dbg_lvl, ("CL: conv_qp_modify: new state %d attr_mask 0x%x\n", qp_attr_p->qp_state, *attr_mask_p));\r
- return IB_SUCCESS;\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-static VAPI_wr_opcode_t\r
-map_ibal_send_opcode(\r
- IN ib_wr_type_t ibal_opcode,\r
- IN boolean_t imm)\r
-{\r
- VAPI_wr_opcode_t vapi_opcode;\r
-\r
- switch (ibal_opcode)\r
- {\r
- case WR_SEND: vapi_opcode = VAPI_SEND;\r
- break;\r
- case WR_RDMA_WRITE: vapi_opcode = VAPI_RDMA_WRITE;\r
- break;\r
- case WR_RDMA_READ: vapi_opcode = VAPI_RDMA_READ;\r
- break;\r
- case WR_COMPARE_SWAP: vapi_opcode = VAPI_ATOMIC_CMP_AND_SWP;\r
- break;\r
- case WR_FETCH_ADD: vapi_opcode = VAPI_ATOMIC_FETCH_AND_ADD;\r
- break;\r
- default: vapi_opcode = VAPI_SEND;\r
- break;\r
- }\r
- if (imm && (VAPI_SEND == vapi_opcode || VAPI_RDMA_WRITE == vapi_opcode)) vapi_opcode++;\r
- return vapi_opcode;\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-ib_api_status_t\r
-mlnx_conv_send_desc(\r
- IN IB_ts_t transport,\r
- IN const ib_send_wr_t *ibal_send_wqe_p,\r
- OUT VAPI_sr_desc_t *vapi_send_desc_p)\r
-{\r
- boolean_t imm = FALSE;\r
- u_int32_t idx;\r
- register VAPI_sg_lst_entry_t *sg_lst_p;\r
- register ib_local_ds_t *ds_array;\r
-\r
-\r
- switch (transport)\r
- {\r
- case IB_TS_UD:\r
- CL_TRACE(MLNX_DBG_DIRECT, g_mlnx_dbg_lvl, ("mapping %s QP\n", "UD"));\r
- {\r
- mlnx_avo_t *avo_p = (mlnx_avo_t *)ibal_send_wqe_p->dgrm.ud.h_av;\r
-\r
- vapi_send_desc_p->remote_qp = cl_ntoh32 (ibal_send_wqe_p->dgrm.ud.remote_qp);\r
- vapi_send_desc_p->remote_qkey = cl_ntoh32 (ibal_send_wqe_p->dgrm.ud.remote_qkey);\r
-\r
- if (!avo_p || avo_p->mark != E_MARK_AV)\r
- return IB_INVALID_AV_HANDLE;\r
-\r
- vapi_send_desc_p->remote_ah = avo_p->h_av; // was ah.hhul\r
- break;\r
- }\r
-\r
- case IB_TS_RC:\r
- CL_TRACE(MLNX_DBG_DIRECT, g_mlnx_dbg_lvl, ("mapping %s QP\n", "RC"));\r
- // vapi_send_desc_p->remote_qp = 0;\r
- // vapi_send_desc_p->remote_qkey = 0;\r
- vapi_send_desc_p->remote_addr = ibal_send_wqe_p->remote_ops.vaddr;\r
- vapi_send_desc_p->r_key = ibal_send_wqe_p->remote_ops.rkey;\r
- vapi_send_desc_p->compare_add = ibal_send_wqe_p->remote_ops.atomic1;\r
- vapi_send_desc_p->swap = ibal_send_wqe_p->remote_ops.atomic2;\r
- break;\r
-\r
- default: // TBD: RAW, RD\r
- return IB_UNSUPPORTED;\r
- }\r
-\r
- imm = (0 != (ibal_send_wqe_p->send_opt & IB_SEND_OPT_IMMEDIATE));\r
- vapi_send_desc_p->fence = (MT_bool)(0 != (ibal_send_wqe_p->send_opt & IB_SEND_OPT_FENCE));\r
- vapi_send_desc_p->set_se = (MT_bool)(0 != (ibal_send_wqe_p->send_opt & IB_SEND_OPT_SOLICITED));\r
- vapi_send_desc_p->comp_type = (ibal_send_wqe_p->send_opt & IB_SEND_OPT_SIGNALED) ?\r
-VAPI_SIGNALED : VAPI_UNSIGNALED;\r
-\r
- vapi_send_desc_p->id = ibal_send_wqe_p->wr_id;\r
- vapi_send_desc_p->opcode = map_ibal_send_opcode(ibal_send_wqe_p->wr_type, imm);\r
-\r
- if (imm)\r
- vapi_send_desc_p->imm_data = cl_ntoh32 (ibal_send_wqe_p->immediate_data);\r
-\r
- vapi_send_desc_p->sg_lst_len = ibal_send_wqe_p->num_ds;\r
-\r
- sg_lst_p = vapi_send_desc_p->sg_lst_p;\r
- ds_array = ibal_send_wqe_p->ds_array;\r
- for (idx = 0; idx < ibal_send_wqe_p->num_ds; idx++)\r
- {\r
- sg_lst_p->addr = ds_array->vaddr;\r
- sg_lst_p->len = ds_array->length;\r
- sg_lst_p->lkey = ds_array->lkey;\r
- // CL_TRACE(MLNX_DBG_DIRECT, g_mlnx_dbg_lvl, ("post_send (conv) addr %Lx size %d key 0x%x\n", sg_lst_p->addr, sg_lst_p->len, sg_lst_p->lkey));\r
- sg_lst_p++;\r
- ds_array++;\r
- }\r
- CL_TRACE(MLNX_DBG_DIRECT, g_mlnx_dbg_lvl, ("send: rqpn 0x%x rkey 0x%x\n", \r
- vapi_send_desc_p->remote_qp,\r
- vapi_send_desc_p->remote_qkey));\r
- return IB_SUCCESS;\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-ib_api_status_t\r
-mlnx_conv_recv_desc(\r
- IN const ib_recv_wr_t *ibal_recv_wqe_p,\r
- OUT VAPI_rr_desc_t *vapi_recv_desc_p)\r
-{\r
- u_int32_t idx;\r
- register VAPI_sg_lst_entry_t *sg_lst_p;\r
- register ib_local_ds_t *ds_array;\r
-\r
- vapi_recv_desc_p->id = ibal_recv_wqe_p->wr_id;\r
- vapi_recv_desc_p->sg_lst_len = ibal_recv_wqe_p->num_ds;\r
- vapi_recv_desc_p->opcode = VAPI_RECEIVE;\r
- vapi_recv_desc_p->comp_type = VAPI_SIGNALED;\r
-\r
- sg_lst_p = vapi_recv_desc_p->sg_lst_p;\r
- ds_array = ibal_recv_wqe_p->ds_array;\r
- for (idx = 0; idx < ibal_recv_wqe_p->num_ds; idx++)\r
- {\r
- sg_lst_p->addr = ds_array->vaddr;\r
- sg_lst_p->len = ds_array->length;\r
- sg_lst_p->lkey = ds_array->lkey;\r
- // CL_TRACE(MLNX_DBG_DIRECT, g_mlnx_dbg_lvl, ("post_recv (conv) addr 0x%Lx size %d key 0x%x\n", sg_lst_p->addr, sg_lst_p->len, sg_lst_p->lkey));\r
- sg_lst_p++;\r
- ds_array++;\r
- }\r
-\r
- return IB_SUCCESS;\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-void\r
-vapi_port_cap_to_ibal(\r
- IN IB_port_cap_mask_t vapi_port_cap,\r
- OUT ib_port_cap_t *ibal_port_cap_p)\r
-{\r
- if (vapi_port_cap & IB_CAP_MASK_IS_CONN_MGMT_SUP)\r
- ibal_port_cap_p->cm = TRUE;\r
- if (vapi_port_cap & IB_CAP_MASK_IS_SNMP_TUNN_SUP)\r
- ibal_port_cap_p->snmp = TRUE;\r
- if (vapi_port_cap & IB_CAP_MASK_IS_DEVICE_MGMT_SUP)\r
- ibal_port_cap_p->dev_mgmt = TRUE;\r
- if (vapi_port_cap & IB_CAP_MASK_IS_VENDOR_CLS_SUP)\r
- ibal_port_cap_p->vend = TRUE;\r
- if (vapi_port_cap & IB_CAP_MASK_IS_SM_DISABLED)\r
- ibal_port_cap_p->sm_disable = TRUE;\r
- if (vapi_port_cap & IB_CAP_MASK_IS_SM)\r
- ibal_port_cap_p->sm = TRUE;\r
- if (vapi_port_cap & IB_CAP_MASK_IS_CLIENT_REREGISTRATION_SUP)\r
- ibal_port_cap_p->client_reregister= TRUE;\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-void\r
-mlnx_conv_vapi_hca_cap(\r
- IN HH_hca_dev_t *hca_info_p,\r
- IN VAPI_hca_cap_t *vapi_hca_cap_p,\r
- IN VAPI_hca_port_t *vapi_hca_ports,\r
- OUT ib_ca_attr_t *ca_attr_p)\r
-{\r
- u_int8_t port_num;\r
- VAPI_hca_port_t *vapi_port_p;\r
- ib_port_attr_t *ibal_port_p;\r
-\r
- ca_attr_p->vend_id = hca_info_p->vendor_id;\r
- ca_attr_p->dev_id = (uint16_t)hca_info_p->dev_id;\r
- ca_attr_p->revision = (uint16_t)hca_info_p->hw_ver;\r
- ca_attr_p->fw_ver = hca_info_p->fw_ver;\r
-\r
- ca_attr_p->ca_guid = *(UNALIGNED64 u_int64_t *)vapi_hca_cap_p->node_guid;\r
- ca_attr_p->num_ports = vapi_hca_cap_p->phys_port_num;\r
- ca_attr_p->max_qps = vapi_hca_cap_p->max_num_qp;\r
- ca_attr_p->max_wrs = vapi_hca_cap_p->max_qp_ous_wr;\r
- ca_attr_p->max_sges = vapi_hca_cap_p->max_num_sg_ent;\r
- ca_attr_p->max_rd_sges = vapi_hca_cap_p->max_num_sg_ent_rd;\r
- ca_attr_p->max_cqs = vapi_hca_cap_p->max_num_cq;\r
- ca_attr_p->max_cqes = vapi_hca_cap_p->max_num_ent_cq;\r
- ca_attr_p->max_pds = vapi_hca_cap_p->max_pd_num;\r
- ca_attr_p->init_regions = vapi_hca_cap_p->max_num_mr;\r
- ca_attr_p->init_windows = vapi_hca_cap_p->max_mw_num;\r
- ca_attr_p->init_region_size = vapi_hca_cap_p->max_mr_size;\r
- ca_attr_p->max_addr_handles = vapi_hca_cap_p->max_ah_num;\r
- ca_attr_p->atomicity = vapi_hca_cap_p->atomic_cap;\r
- ca_attr_p->max_partitions = vapi_hca_cap_p->max_pkeys;\r
- ca_attr_p->max_qp_resp_res = vapi_hca_cap_p->max_qp_ous_rd_atom;\r
- ca_attr_p->max_resp_res = vapi_hca_cap_p->max_res_rd_atom;\r
- ca_attr_p->max_qp_init_depth = vapi_hca_cap_p->max_qp_init_rd_atom;\r
- ca_attr_p->max_ipv6_qps = vapi_hca_cap_p->max_raw_ipv6_qp;\r
- ca_attr_p->max_ether_qps = vapi_hca_cap_p->max_raw_ethy_qp;\r
- ca_attr_p->max_mcast_grps = vapi_hca_cap_p->max_mcast_grp_num;\r
- ca_attr_p->max_mcast_qps = vapi_hca_cap_p->max_total_mcast_qp_attach_num;\r
- ca_attr_p->max_qps_per_mcast_grp = vapi_hca_cap_p->max_mcast_qp_attach_num;\r
- ca_attr_p->local_ack_delay = vapi_hca_cap_p->local_ca_ack_delay;\r
- ca_attr_p->bad_pkey_ctr_support = vapi_hca_cap_p->flags & VAPI_BAD_PKEY_COUNT_CAP;\r
- ca_attr_p->bad_qkey_ctr_support = vapi_hca_cap_p->flags & VAPI_BAD_QKEY_COUNT_CAP;\r
- ca_attr_p->raw_mcast_support = vapi_hca_cap_p->flags & VAPI_RAW_MULTI_CAP;\r
- ca_attr_p->apm_support = vapi_hca_cap_p->flags & VAPI_AUTO_PATH_MIG_CAP;\r
- ca_attr_p->av_port_check = vapi_hca_cap_p->flags & VAPI_UD_AV_PORT_ENFORCE_CAP;\r
- ca_attr_p->change_primary_port = vapi_hca_cap_p->flags & VAPI_CHANGE_PHY_PORT_CAP;\r
- ca_attr_p->modify_wr_depth = vapi_hca_cap_p->flags & VAPI_RESIZE_OUS_WQE_CAP;\r
- ca_attr_p->hw_agents = FALSE; // in the context of IBAL then agent is implemented on the host\r
-\r
- ca_attr_p->num_page_sizes = 1;\r
- ca_attr_p->p_page_size[0] = PAGESIZE; // TBD: extract an array of page sizes from HCA cap\r
-\r
- for (port_num = 0; port_num < vapi_hca_cap_p->phys_port_num; port_num++)\r
- {\r
- // Setup port pointers\r
- ibal_port_p = &ca_attr_p->p_port_attr[port_num];\r
- vapi_port_p = &vapi_hca_ports[port_num];\r
-\r
- // Port Cabapilities\r
- cl_memclr(&ibal_port_p->cap, sizeof(ib_port_cap_t));\r
- vapi_port_cap_to_ibal(vapi_port_p->capability_mask, &ibal_port_p->cap);\r
-\r
- // Port Atributes\r
- ibal_port_p->port_num = port_num + 1;\r
- ibal_port_p->port_guid = ibal_port_p->p_gid_table[0].unicast.interface_id;\r
- ibal_port_p->lid = cl_ntoh16(vapi_port_p->lid);\r
- ibal_port_p->lmc = vapi_port_p->lmc;\r
- ibal_port_p->max_vls = vapi_port_p->max_vl_num;\r
- ibal_port_p->sm_lid = cl_ntoh16(vapi_port_p->sm_lid);\r
- ibal_port_p->sm_sl = vapi_port_p->sm_sl;\r
- ibal_port_p->link_state = (vapi_port_p->state != 0) ? (uint8_t)vapi_port_p->state : IB_LINK_DOWN;\r
- ibal_port_p->num_gids = vapi_port_p->gid_tbl_len;\r
- ibal_port_p->num_pkeys = vapi_port_p->pkey_tbl_len;\r
- ibal_port_p->pkey_ctr = (uint16_t)vapi_port_p->bad_pkey_counter;\r
- ibal_port_p->qkey_ctr = (uint16_t)vapi_port_p->qkey_viol_counter;\r
- ibal_port_p->max_msg_size = vapi_port_p->max_msg_sz;\r
- ibal_port_p->mtu = (u_int8_t)vapi_port_p->max_mtu;\r
-\r
- ibal_port_p->subnet_timeout = 5; // TBD: currently 128us\r
- // ibal_port_p->local_ack_timeout = 3; // TBD: currently ~32 usec\r
-#if 0\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("Port %d port_guid 0x%"PRIx64"\n",\r
- ibal_port_p->port_num, ibal_port_p->port_guid));\r
-#endif\r
- }\r
-}\r
-\r
-/////////////////////////////////////////////////////////\r
-/////////////////////////////////////////////////////////\r
-ib_api_status_t\r
-mlnx_get_hca_pkey_tbl(\r
- IN HH_hca_hndl_t hh_hndl,\r
- IN u_int8_t port_num,\r
- IN u_int16_t num_entries,\r
- OUT void* table_p)\r
-{\r
- u_int16_t size;\r
- ib_net16_t *pkey_p;\r
-\r
- if (HH_OK != THH_hob_get_pkey_tbl( hh_hndl, port_num, num_entries, &size, table_p))\r
- return IB_ERROR;\r
-\r
- pkey_p = (ib_net16_t *)table_p;\r
-#if 0\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("port %d pkey0 0x%x pkey1 0x%x\n", port_num, pkey_p[0], pkey_p[1]));\r
-#endif\r
- return IB_SUCCESS;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_get_hca_gid_tbl(\r
- IN HH_hca_hndl_t hh_hndl,\r
- IN u_int8_t port_num,\r
- IN u_int16_t num_entries,\r
- OUT void* table_p)\r
-{\r
- u_int16_t size;\r
-\r
- if (HH_OK != THH_hob_get_gid_tbl( hh_hndl, port_num, num_entries, &size, table_p))\r
- return IB_ERROR;\r
-\r
- return IB_SUCCESS;\r
-}\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies, Inc. All rights reserved. \r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef __HCA_DATA_H__\r
-#define __HCA_DATA_H__\r
-\r
-\r
-#include <iba/ib_ci.h>\r
-#include <complib/comp_lib.h>\r
-\r
-#include <vapi.h>\r
-#include <evapi.h>\r
-#include <hh.h>\r
-#include <thh.h>\r
-#include <thh_hob.h>\r
-#include <tavor_dev_defs.h>\r
-#include <thh_init.h>\r
-#include <hhul.h>\r
-#include <thhul_hob.h>\r
-#include <thhul_pdm.h>\r
-#include <thhul_cqm.h>\r
-#include <thhul_qpm.h>\r
-\r
-extern u_int32_t g_mlnx_dbg_lvl;\r
-extern uint32_t g_sqp_max_avs;\r
-extern char mlnx_uvp_lib_name[];\r
-\r
-#define MLNX_DBG_INFO (1<<1)\r
-#define MLNX_DBG_TRACE (1<<2)\r
-#define MLNX_DBG_VERBOSE (1<<3)\r
-// for data path debugging\r
-#define MLNX_DBG_DIRECT (1<<4)\r
-#define MLNX_DBG_QPN (1<<5)\r
-#define MLNX_DBG_MEM (1<<6)\r
-\r
-#define MLNX_MAX_HCA 4\r
-#define MLNX_NUM_HOBKL MLNX_MAX_HCA\r
-#define MLNX_NUM_HOBUL MLNX_MAX_HCA\r
-#define MLNX_NUM_CB_THR 1\r
-#define MLNX_SIZE_CB_POOL 256\r
-#define MLNX_UAL_ALLOC_HCA_UL_RES 1\r
-#define MLNX_UAL_FREE_HCA_UL_RES 2\r
-\r
-\r
-// Defines for QP ops\r
-#define MLNX_MAX_NUM_SGE 8\r
-#define MLNX_MAX_WRS_PER_CHAIN 4\r
-\r
-#define MLNX_NUM_RESERVED_QPS 16\r
-\r
-/*\r
- * Completion model.\r
- * 0: No DPC processor assignment\r
- * 1: DPCs per-CQ, processor affinity set at CQ initialization time.\r
- * 2: DPCs per-CQ, processor affinity set at runtime.\r
- * 3: DPCs per-CQ, no processor affinity set.\r
- */\r
-#define MLNX_COMP_MODEL 3\r
-\r
-#define PD_HCA_FROM_HNDL(hndl) (((pd_info_t *)hndl)->hca_idx)\r
-#define PD_NUM_FROM_HNDL(hndl) (((pd_info_t *)hndl)->pd_num)\r
-#define CQ_HCA_FROM_HNDL(hndl) (((cq_info_t *)hndl)->hca_idx)\r
-#define CQ_NUM_FROM_HNDL(hndl) (((cq_info_t *)hndl)->cq_num)\r
-#define QP_HCA_FROM_HNDL(hndl) (((qp_info_t *)hndl)->hca_idx)\r
-#define QP_NUM_FROM_HNDL(hndl) (((qp_info_t *)hndl)->qp_num)\r
-\r
-#define PD_HNDL_FROM_PD(pd_num) (&hobul_p->pd_info_tbl[pd_num])\r
-#define CQ_HNDL_FROM_CQ(cq_num) (&hobul_p->cq_info_tbl[cq_num])\r
-#define QP_HNDL_FROM_QP(qp_num) (&hobul_p->qp_info_tbl[qp_num])\r
-\r
-#ifdef _DEBUG_\r
-#define VALIDATE_INDEX(index, limit, error, label) \\r
- { \\r
- if (index >= limit) \\r
- { \\r
- status = error; \\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("file %s line %d\n", __FILE__, __LINE__)); \\r
- goto label; \\r
- } \\r
- }\r
-#else\r
-#define VALIDATE_INDEX(index, limit, error, label)\r
-#endif\r
-\r
-\r
-\r
-// Typedefs\r
-\r
-typedef enum {\r
- E_EV_CA=1,\r
- E_EV_QP,\r
- E_EV_CQ,\r
- E_EV_LAST\r
-} ENUM_EVENT_CLASS;\r
-\r
-typedef enum {\r
- E_MARK_CA=1, // Channel Adaptor\r
- E_MARK_PD, // Protection Domain\r
- E_MARK_CQ, // Completion Queue\r
- E_MARK_QP, // Queue Pair\r
- E_MARK_AV, // Address Vector (UD)\r
- E_MARK_MG, // Multicast Group\r
- E_MARK_MR, // Memory Region\r
- E_MARK_MW, // Memory Windows\r
- E_MARK_INVALID,\r
-} ENUM_MARK;\r
-\r
-typedef enum {\r
- E_MR_PHYS=1,\r
- E_MR_SHARED,\r
- E_MR_ANY,\r
- E_MR_INVALID\r
-} ENUM_MR_TYPE;\r
-\r
-/*\r
- * Attribute cache for port info saved to expedite local MAD processing.\r
- * Note that the cache accounts for the worst case GID and PKEY table size\r
- * but is allocated from paged pool, so it's nothing to worry about.\r
- */\r
-\r
-typedef struct _guid_block\r
-{\r
- boolean_t valid;\r
- ib_guid_info_t tbl;\r
-\r
-} mlnx_guid_block_t;\r
-\r
-typedef struct _port_info_cache\r
-{\r
- boolean_t valid;\r
- ib_port_info_t info;\r
-\r
-} mlnx_port_info_cache_t;\r
-\r
-typedef struct _pkey_block\r
-{\r
- boolean_t valid;\r
- ib_pkey_table_t tbl;\r
-\r
-} mlnx_pkey_block_t;\r
-\r
-typedef struct _sl_vl_cache\r
-{\r
- boolean_t valid;\r
- ib_slvl_table_t tbl;\r
-\r
-} mlnx_sl_vl_cache_t;\r
-\r
-typedef struct _vl_arb_block\r
-{\r
- boolean_t valid;\r
- ib_vl_arb_table_t tbl;\r
-\r
-} mlnx_vl_arb_block_t;\r
-\r
-typedef struct _attr_cache\r
-{\r
- mlnx_guid_block_t guid_block[32];\r
- mlnx_port_info_cache_t port_info;\r
- mlnx_pkey_block_t pkey_tbl[2048];\r
- mlnx_sl_vl_cache_t sl_vl;\r
- mlnx_vl_arb_block_t vl_arb[4];\r
-\r
-} mlnx_cache_t;\r
-\r
-typedef struct _ib_ca {\r
- ENUM_MARK mark;\r
- HH_hca_hndl_t hh_hndl;\r
- ci_completion_cb_t comp_cb_p;\r
- ci_async_event_cb_t async_cb_p;\r
- const void *ca_context;\r
- void *cl_device_h;\r
- u_int32_t index;\r
- cl_async_proc_t *async_proc_mgr_p;\r
- mlnx_cache_t *cache; // Cached port attributes.\r
- const void * __ptr64 p_dev_obj; // store underlying device object\r
-} mlnx_hob_t;\r
-\r
-typedef struct _ib_um_ca\r
-{\r
- MDL *p_mdl;\r
- void *p_mapped_addr;\r
- HH_hca_hndl_t hh_hndl;\r
- mlnx_hob_t *hob_p;\r
- /* The next two fields must be grouped together as the are mapped to UM. */\r
- HH_hca_dev_t dev_info;\r
- uint8_t ul_hca_res[1]; // Beginning of UL resource buffer.\r
-} mlnx_um_ca_t;\r
-\r
-typedef struct {\r
- cl_async_proc_item_t async_item;\r
- HH_hca_hndl_t hh_hndl;\r
- HH_cq_hndl_t hh_cq; // for completion\r
- HH_event_record_t hh_er; // for async events\r
- void *private_data;\r
-} mlnx_cb_data_t;\r
-\r
-typedef struct {\r
- cl_list_item_t list_item;\r
- HH_hca_hndl_t hh_hndl;\r
- struct _hca_if {\r
- HH_hca_hndl_t hh_hndl;\r
- void * kernel_crspace_addr;\r
- ULONG kernel_crspace_size;\r
- } s;\r
-// char *hca_name_p;\r
- net64_t guid;\r
- const void* __ptr64 p_dev_obj; // hca device object\r
-// ci_interface_t ifx;\r
-} mlnx_hca_t;\r
-\r
-typedef struct _ib_pd { /* struct of PD related resources */\r
- ENUM_MARK mark;\r
- cl_mutex_t mutex;\r
- u_int32_t kernel_mode;\r
- atomic32_t count;\r
- u_int32_t hca_idx;\r
- // mlnx_hob_t *hob_p;\r
- HH_hca_hndl_t hh_hndl; /* For HH direct access */\r
- HH_pd_hndl_t pd_num; /* For HH-UL direct access */\r
- HHUL_pd_hndl_t hhul_pd_hndl;\r
- void *pd_ul_resources_p;\r
-} pd_info_t;\r
-\r
-typedef struct _ib_cq { /* struct of CQ related resources */\r
- ENUM_MARK mark;\r
- cl_mutex_t mutex;\r
- u_int32_t hca_idx;\r
- u_int32_t kernel_mode;\r
- // mlnx_hob_t *hob_p;\r
- HH_hca_hndl_t hh_hndl; /* For HH direct access */\r
- HH_cq_hndl_t cq_num; /* For HH-UL direct access */\r
-// HH_pd_hndl_t pd_num; /* For HH-UL direct access */\r
- HHUL_cq_hndl_t hhul_cq_hndl;\r
- void *cq_ul_resources_p;\r
- const void *cq_context;\r
- KDPC dpc;\r
- atomic32_t spl_qp_cnt;\r
-\r
-} cq_info_t;\r
-\r
-typedef struct _ib_qp {\r
- ENUM_MARK mark;\r
- cl_mutex_t mutex;\r
- u_int32_t hca_idx;\r
- u_int32_t kernel_mode;\r
- // mlnx_hob_t *hob_p;\r
- HH_hca_hndl_t hh_hndl; // For HH direct access */\r
- HHUL_qp_hndl_t hhul_qp_hndl;\r
- IB_wqpn_t qp_num; // For direct HH-UL access */\r
- HH_pd_hndl_t pd_num; // For HH-UL direct access */\r
- IB_port_t port; // Valid for special QPs only */\r
- ib_qp_type_t qp_type; // Required for qp_query\r
- u_int32_t sq_signaled; // Required for qp_query\r
- ib_cq_handle_t h_sq_cq;\r
- ib_cq_handle_t h_rq_cq;\r
- u_int32_t sq_size;\r
- u_int32_t rq_size;\r
- VAPI_sr_desc_t *send_desc_p;\r
- VAPI_rr_desc_t *recv_desc_p;\r
- VAPI_sg_lst_entry_t *send_sge_p;\r
- VAPI_sg_lst_entry_t *recv_sge_p;\r
- void *qp_ul_resources_p;\r
- const void *qp_context;\r
-} qp_info_t;\r
-\r
-typedef struct HOBUL_t {\r
- HH_hca_hndl_t hh_hndl; /* For HH direct access */\r
- HHUL_hca_hndl_t hhul_hndl; /* user level HCA resources handle for HH */\r
- u_int32_t cq_idx_mask; /* */\r
- u_int32_t qp_idx_mask; /* */\r
- u_int32_t vendor_id; /* \ */\r
- u_int32_t device_id; /* > 3 items needed for initializing user level */\r
- void *hca_ul_resources_p; /* / */\r
- MT_size_t cq_ul_resources_sz; /* Needed for allocating user resources for CQs */\r
- MT_size_t qp_ul_resources_sz; /* Needed for allocating user resources for QPs */\r
- MT_size_t pd_ul_resources_sz; /* Needed for allocating user resources for PDs */\r
- u_int32_t max_cq; /* Max num. of CQs - size of following table */\r
- cq_info_t *cq_info_tbl;\r
- u_int32_t max_qp; /* Max num. of QPs - size of following table */\r
- qp_info_t *qp_info_tbl;\r
- u_int32_t max_pd; /* Max num. of PDs - size of following table */\r
- pd_info_t *pd_info_tbl;\r
- u_int32_t log2_mpt_size;\r
- atomic32_t count;\r
-} mlnx_hobul_t, *mlnx_hobul_hndl_t;\r
-\r
-typedef struct _ib_mr {\r
- ENUM_MARK mark;\r
- ENUM_MR_TYPE mr_type;\r
- u_int64_t mr_start; // TBD: IA64\r
- u_int64_t mr_size; // TBD: IA64\r
-// u_int64_t mr_first_page_addr; // TBD : IA64\r
-// u_int32_t mr_num_pages;\r
- ib_pd_handle_t mr_pd_handle;\r
- MOSAL_iobuf_t mr_iobuf;\r
- VAPI_mrw_acl_t mr_acl;\r
- VAPI_lkey_t mr_lkey;\r
- MOSAL_protection_ctx_t mr_prot_ctx;\r
- MOSAL_mem_perm_t mr_mosal_perm;\r
-} mlnx_mro_t;\r
-\r
-typedef struct _ib_mw {\r
- ENUM_MARK mark;\r
- u_int32_t hca_idx;\r
- u_int32_t pd_idx;\r
- u_int32_t mw_rkey;\r
-} mlnx_mwo_t;\r
-\r
-typedef struct _ib_mcast {\r
- ENUM_MARK mark;\r
- IB_gid_t mcast_gid;\r
- u_int32_t hca_idx;\r
- u_int32_t qp_num;\r
- u_int32_t kernel_mode;\r
-} mlnx_mcast_t;\r
-\r
-typedef struct _ib_av {\r
- ENUM_MARK mark;\r
- u_int32_t hca_idx;\r
- u_int32_t pd_idx;\r
- u_int32_t user_mode;\r
- HHUL_ud_av_hndl_t h_av;\r
-} mlnx_avo_t;\r
-\r
-typedef mlnx_hob_t *mlnx_hca_h;\r
-\r
-// Global Variables\r
-//extern mlnx_hca_t mlnx_hca_array[];\r
-//extern uint32_t mlnx_num_hca;\r
-\r
-extern mlnx_hob_t mlnx_hob_array[];\r
-extern mlnx_hobul_t *mlnx_hobul_array[];\r
-\r
-// Functions\r
-void\r
-setup_ci_interface(\r
- IN const ib_net64_t ca_guid,\r
- OUT ci_interface_t *p_interface );\r
-\r
-void\r
-mlnx_hca_insert(\r
- IN mlnx_hca_t *p_hca );\r
-\r
-void\r
-mlnx_hca_remove(\r
- IN mlnx_hca_t *p_hca );\r
-\r
-mlnx_hca_t*\r
-mlnx_hca_from_guid(\r
- IN ib_net64_t guid );\r
-\r
-mlnx_hca_t*\r
-mlnx_hca_from_hh_hndl(\r
- IN HH_hca_hndl_t hh_hndl );\r
-\r
-/*\r
-void\r
-mlnx_names_from_guid(\r
- IN ib_net64_t guid,\r
- OUT char **hca_name_p,\r
- OUT char **dev_name_p);\r
-*/\r
-\r
-cl_status_t\r
-mlnx_hobs_init( void );\r
-\r
-ib_api_status_t\r
-mlnx_hobs_insert(\r
- IN mlnx_hca_t *p_hca,\r
- OUT mlnx_hob_t **hob_p);\r
-\r
-void\r
-mlnx_hobs_get_handle(\r
- IN mlnx_hob_t *hob_p,\r
- OUT HH_hca_hndl_t *hndl_p);\r
-\r
-ib_api_status_t\r
-mlnx_hobs_set_cb(\r
- IN mlnx_hob_t *hob_p, \r
- IN ci_completion_cb_t comp_cb_p,\r
- IN ci_async_event_cb_t async_cb_p,\r
- IN const void* const ib_context);\r
-\r
-ib_api_status_t\r
-mlnx_hobs_get_context(\r
- IN mlnx_hob_t *hob_p,\r
- OUT void **context_p);\r
-\r
-ib_api_status_t\r
-mlnx_hobs_create_device(\r
- IN mlnx_hob_t *hob_p,\r
- OUT char* dev_name);\r
-\r
-void\r
-mlnx_hobs_remove(\r
- IN mlnx_hob_t *hob_p);\r
-\r
-ib_api_status_t\r
-mlnx_hobs_lookup(\r
- IN HH_hca_hndl_t hndl,\r
- OUT mlnx_hob_t **hca_p);\r
-\r
-mlnx_hobul_t *\r
-mlnx_hobs_get_hobul(\r
- IN mlnx_hob_t *hob_p);\r
-\r
-ib_api_status_t\r
-mlnx_hobul_new(\r
- IN mlnx_hob_t *hob_p,\r
- IN HH_hca_hndl_t hh_hndl,\r
- IN void *resources_p);\r
-\r
-void\r
-mlnx_hobul_get(\r
- IN mlnx_hob_t *hob_p,\r
- OUT void **resources_p );\r
-\r
-void\r
-mlnx_hobul_delete(\r
- IN mlnx_hob_t *hob_p);\r
-\r
-// Conversion Functions\r
-\r
-VAPI_mrw_acl_t\r
-map_ibal_acl(\r
- IN ib_access_t ibal_acl);\r
-\r
-ib_access_t\r
-map_vapi_acl(\r
- IN VAPI_mrw_acl_t vapi_acl);\r
-\r
-ib_api_status_t\r
-mlnx_lock_region(\r
- IN mlnx_mro_t *mro_p,\r
- IN boolean_t um_call );\r
-\r
-ib_api_status_t\r
-mlnx_conv_ibal_mr_create(\r
- IN u_int32_t pd_idx,\r
- IN OUT mlnx_mro_t *mro_p,\r
- IN VAPI_mr_change_t change_flags,\r
- IN ib_mr_create_t const *p_mr_create,\r
- IN boolean_t um_call,\r
- OUT HH_mr_t *mr_props_p );\r
-\r
-ib_api_status_t\r
-mlnx_conv_ibal_pmr_create(\r
- IN u_int32_t pd_idx,\r
- IN mlnx_mro_t *mro_p,\r
- IN ib_phys_create_t const *p_pmr_create,\r
- OUT HH_mr_t *mr_props_p );\r
-\r
-void\r
-mlnx_conv_ibal_av(\r
- IN HH_hca_hndl_t hh_hndl,\r
- IN const ib_av_attr_t *ibal_av_p,\r
- OUT VAPI_ud_av_t *vapi_av_p);\r
-\r
-void\r
-mlnx_conv_vapi_av(\r
- IN HH_hca_hndl_t hh_hndl,\r
- IN const VAPI_ud_av_t *vapi_av_p,\r
- OUT ib_av_attr_t *ibal_av_p);\r
-\r
-int\r
-mlnx_map_vapi_cqe_status(\r
- IN VAPI_wc_status_t vapi_status);\r
-\r
-int\r
-mlnx_map_vapi_cqe_type(\r
- IN VAPI_cqe_opcode_t opcode);\r
-\r
-int\r
-mlnx_map_vapi_rna_type(\r
- IN VAPI_remote_node_addr_type_t rna);\r
-\r
-void\r
-mlnx_conv_vapi_mr_attr(\r
- IN ib_pd_handle_t pd_h,\r
- IN HH_mr_info_t *mr_info_p,\r
- OUT ib_mr_attr_t *mr_query_p);\r
-\r
-void\r
-mlnx_conv_bind_req(\r
- IN HHUL_qp_hndl_t hhul_qp_hndl,\r
- IN ib_bind_wr_t* const p_mw_bind,\r
- OUT HHUL_mw_bind_t *bind_prop_p);\r
-\r
-int\r
-mlnx_map_ibal_qp_type(\r
- IN ib_qp_type_t ibal_qpt,\r
- OUT VAPI_special_qp_t *vapi_qp_type_p);\r
-\r
-void\r
-mlnx_conv_qp_create_attr(\r
- IN const ib_qp_create_t *create_attr_p,\r
- IN HHUL_qp_init_attr_t *init_attr_p,\r
- OUT VAPI_special_qp_t *vapi_qp_type_p);\r
-\r
-void\r
-mlnx_conv_vapi_qp_attr(\r
- IN HH_hca_hndl_t hh_hndl,\r
- IN VAPI_qp_attr_t *hh_qp_attr_p,\r
- OUT ib_qp_attr_t *qp_attr_p);\r
-\r
-ib_api_status_t\r
-mlnx_conv_qp_modify_attr(\r
- IN HH_hca_hndl_t hh_hndl,\r
- IN ib_qp_type_t qp_type,\r
- IN const ib_qp_mod_t *modify_attr_p,\r
- OUT VAPI_qp_attr_t *qp_attr_p, \r
- OUT VAPI_qp_attr_mask_t *attr_mask_p);\r
-\r
-ib_api_status_t\r
-mlnx_conv_send_desc(\r
- IN IB_ts_t transport,\r
- IN const ib_send_wr_t *ibal_send_wqe_p,\r
- OUT VAPI_sr_desc_t *vapi_send_desc_p);\r
-\r
-ib_api_status_t\r
-mlnx_conv_recv_desc(\r
- IN const ib_recv_wr_t *ibal_recv_wqe_p,\r
- OUT VAPI_rr_desc_t *vapi_recv_desc_p);\r
-\r
-void\r
-mlnx_conv_vapi_hca_cap(\r
- IN HH_hca_dev_t *hca_info_p,\r
- IN VAPI_hca_cap_t *vapi_hca_cap_p,\r
- IN VAPI_hca_port_t *vapi_hca_ports,\r
- OUT ib_ca_attr_t *ca_attr_p);\r
-\r
-ib_api_status_t\r
-mlnx_get_hca_pkey_tbl(\r
- IN HH_hca_hndl_t hh_hndl,\r
- IN u_int8_t port_num,\r
- IN u_int16_t num_entries,\r
- OUT void* table);\r
-\r
-ib_api_status_t\r
-mlnx_get_hca_gid_tbl(\r
- IN HH_hca_hndl_t hh_hndl,\r
- IN u_int8_t port_num,\r
- IN u_int16_t num_entries,\r
- OUT void* table);\r
-\r
-ib_api_status_t\r
-mlnx_local_mad (\r
- IN const ib_ca_handle_t h_ca,\r
- IN const uint8_t port_num,\r
- IN const ib_av_attr_t *p_av_src_attr, \r
- IN const ib_mad_t *p_mad_in,\r
- OUT ib_mad_t *p_mad_out );\r
-\r
-void\r
-mlnx_memory_if(\r
- IN OUT ci_interface_t *p_interface );\r
-\r
-void\r
-mlnx_ecc_if(\r
- IN OUT ci_interface_t *p_interface );\r
-\r
-void\r
-mlnx_direct_if(\r
- IN OUT ci_interface_t *p_interface );\r
-\r
-void\r
-mlnx_mcast_if(\r
- IN OUT ci_interface_t *p_interface );\r
-\r
-ib_api_status_t\r
-fw_access_ctrl(\r
- IN const void* __ptr64 context,\r
- IN const void* __ptr64* const handle_array OPTIONAL,\r
- IN uint32_t num_handles,\r
- IN ib_ci_op_t* const p_ci_op,\r
- IN OUT ci_umv_buf_t *p_umv_buf OPTIONAL);\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#if !defined( _HCA_DEBUG_H_ )\r
-#define _HCA_DEBUG_H_\r
-\r
-#include <complib/cl_debug.h>\r
-\r
-\r
-#define HCA_DBG_DEV (1 << 0)\r
-#define HCA_DBG_PNP (1 << 1)\r
-#define HCA_DBG_PO (1 << 2)\r
-\r
-#define HCA_DBG_ERROR CL_DBG_ERROR\r
-#define HCA_DBG_FULL CL_DBG_ALL\r
-\r
-\r
-extern uint32_t g_mlnx_dbg_lvl;\r
-\r
-\r
-#define HCA_ENTER( msg_lvl ) \\r
- CL_ENTER( msg_lvl, g_mlnx_dbg_lvl )\r
-\r
-#define HCA_EXIT( msg_lvl ) \\r
- CL_EXIT( msg_lvl, g_mlnx_dbg_lvl )\r
-\r
-#define HCA_TRACE( msg_lvl, msg ) \\r
- CL_TRACE( msg_lvl, g_mlnx_dbg_lvl, msg )\r
-\r
-#define HCA_TRACE_EXIT( msg_lvl, msg ) \\r
- CL_TRACE_EXIT( msg_lvl, g_mlnx_dbg_lvl, msg )\r
-\r
-#define HCA_PRINT( msg_lvl, msg ) \\r
- CL_PRINT( msg_lvl, g_mlnx_dbg_lvl, msg )\r
-\r
-#endif /* !defined( _HCA_DEBUG_H_ ) */\r
-\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies, Inc. All rights reserved. \r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#include "hca_data.h"\r
-\r
-\r
-/* Controls whether to use the VAPI entrypoints in THH, or the IBAL native ones. */\r
-#define MLNX_SEND_NATIVE 1\r
-#define MLNX_RECV_NATIVE 1\r
-#define MLNX_POLL_NATIVE 1\r
-\r
-\r
-/*\r
-* Work Request Processing Verbs.\r
-*/\r
-ib_api_status_t\r
-mlnx_post_send (\r
- IN const ib_qp_handle_t h_qp,\r
- IN ib_send_wr_t *p_send_wr,\r
- OUT ib_send_wr_t **pp_failed )\r
-{\r
- ib_api_status_t status = IB_SUCCESS;\r
- qp_info_t *qp_info_p = (qp_info_t *)h_qp;\r
- u_int32_t qp_idx = 0;\r
- mlnx_hobul_t *hobul_p;\r
-#if !MLNX_SEND_NATIVE\r
- HH_ret_t ret;\r
- VAPI_sr_desc_t send_desc;\r
- VAPI_special_qp_t vapi_qp_type;\r
- IB_ts_t transport;\r
- ib_send_wr_t *wqe_p;\r
-#endif\r
-\r
- // CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("hca %x qp %x\n", qp_info_p->hca_idx, qp_info_p->qp_num));\r
- if( !p_send_wr )\r
- {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
-\r
- if (!qp_info_p || E_MARK_QP != qp_info_p->mark) {\r
- status = IB_INVALID_QP_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- VALIDATE_INDEX(qp_info_p->hca_idx, MLNX_MAX_HCA, IB_INVALID_QP_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[qp_info_p->hca_idx];\r
-\r
- CL_ASSERT(hobul_p);\r
- CL_ASSERT(hobul_p->qp_info_tbl);\r
-\r
- qp_idx = qp_info_p->qp_num & hobul_p->qp_idx_mask;\r
- VALIDATE_INDEX(qp_idx, hobul_p->max_qp, IB_INVALID_QP_HANDLE, cleanup);\r
-\r
-#if MLNX_SEND_NATIVE\r
- return THHUL_qpm_post_send_wrs( hobul_p->hhul_hndl,\r
- qp_info_p->hhul_qp_hndl, p_send_wr, pp_failed );\r
-#else\r
- // Assuming that posting all WQE will succeed. Errors are handled below.\r
- *pp_failed = NULL;\r
-\r
- // Loop and post all descriptors in list, bail out on failure.\r
- transport = mlnx_map_ibal_qp_type(qp_info_p->qp_type, &vapi_qp_type);\r
-\r
- if (VAPI_REGULAR_QP != vapi_qp_type)\r
- {\r
- memset(&send_desc, 0, sizeof(send_desc));\r
- // send_desc.sg_lst_p = &sg_lst_a[0];\r
- send_desc.sg_lst_p = hobul_p->qp_info_tbl[qp_idx].send_sge_p;\r
- if (!send_desc.sg_lst_p) {\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("hca %x qp %x\n", qp_info_p->hca_idx, qp_idx));\r
- }\r
- CL_ASSERT(send_desc.sg_lst_p);\r
- for (wqe_p = p_send_wr; wqe_p; wqe_p = wqe_p->p_next)\r
- {\r
- // sq_size is a misnomer, it is really max_sge\r
- CL_ASSERT( hobul_p->qp_info_tbl[qp_idx].sq_size >= wqe_p->num_ds);\r
-\r
- status = mlnx_conv_send_desc( transport, wqe_p, &send_desc);\r
- if (IB_SUCCESS != status) break;\r
-\r
- if (HH_OK != (ret = THHUL_qpm_post_send_req(hobul_p->hhul_hndl,\r
- qp_info_p->hhul_qp_hndl,\r
- &send_desc)))\r
- {\r
- status = (HH_EAGAIN == ret) ? IB_INSUFFICIENT_RESOURCES :\r
- (HH_EINVAL_SG_NUM == ret) ? IB_INVALID_MAX_SGE : \r
- IB_ERROR;\r
- *pp_failed = wqe_p;\r
- // wqe_p->p_next = NULL;\r
- goto cleanup;\r
- }\r
- }\r
- }\r
- else {\r
- // For regular QP use real send multiple\r
- VAPI_sr_desc_t desc_list[MLNX_MAX_WRS_PER_CHAIN];\r
- VAPI_sg_lst_entry_t sg_list[MLNX_MAX_WRS_PER_CHAIN][MLNX_MAX_NUM_SGE];\r
- u_int32_t num_wrs;\r
-\r
- wqe_p = p_send_wr;\r
- while (wqe_p) {\r
- for (num_wrs = 0; (num_wrs < MLNX_MAX_WRS_PER_CHAIN) && wqe_p; \r
- wqe_p = wqe_p->p_next, num_wrs++)\r
- {\r
- desc_list[num_wrs].sg_lst_p = &sg_list[num_wrs][0];\r
- status = mlnx_conv_send_desc(transport, wqe_p, &desc_list[num_wrs]);\r
- if (status != IB_SUCCESS) {\r
- CL_TRACE(MLNX_DBG_DIRECT, g_mlnx_dbg_lvl,\r
- ("FAILED to map the send_desc %d\n", num_wrs));\r
- break;\r
- }\r
- }\r
- if (num_wrs > 0) {\r
- if (num_wrs > 1) {\r
- ret = THHUL_qpm_post_send_reqs(hobul_p->hhul_hndl,\r
- qp_info_p->hhul_qp_hndl,\r
- num_wrs, desc_list);\r
- } else {\r
- ret = THHUL_qpm_post_send_req(hobul_p->hhul_hndl,\r
- qp_info_p->hhul_qp_hndl,\r
- desc_list);\r
- }\r
- if (HH_OK != ret) {\r
- status = (HH_EAGAIN == ret) ? IB_INSUFFICIENT_RESOURCES :\r
- (HH_EINVAL_SG_NUM == ret) ? IB_INVALID_MAX_SGE : \r
- IB_ERROR;\r
- *pp_failed = wqe_p;\r
- // wqe_p->p_next = NULL;\r
- goto cleanup;\r
- }\r
- } else {\r
- /* no work requests this round */\r
- CL_TRACE (MLNX_DBG_DIRECT, g_mlnx_dbg_lvl, ("NO WRs\n"));\r
- *pp_failed = wqe_p;\r
- break;\r
- }\r
- }\r
- }\r
-\r
- return status;\r
-#endif\r
-\r
-cleanup:\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- return status;\r
-}\r
-\r
-ib_api_status_t \r
-mlnx_post_recv (\r
- IN const ib_qp_handle_t h_qp,\r
- IN ib_recv_wr_t *p_recv_wr,\r
- OUT ib_recv_wr_t **pp_failed OPTIONAL )\r
-{\r
- ib_api_status_t status = IB_SUCCESS;\r
- qp_info_t *qp_info_p = (qp_info_t *)h_qp;\r
-\r
- u_int32_t qp_idx = 0;\r
- mlnx_hobul_t *hobul_p;\r
-#if !MLNX_RECV_NATIVE\r
- HH_ret_t ret;\r
- ib_recv_wr_t *wqe_p;\r
- IB_ts_t transport;\r
- VAPI_rr_desc_t recv_desc;\r
- VAPI_special_qp_t vapi_qp_type;\r
-#endif\r
-\r
- // CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("hca %x qp %x\n",\r
- // qp_info_p->hca_idx, qp_info_p->qp_num));\r
- if( !p_recv_wr )\r
- {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
-\r
- if (!qp_info_p || E_MARK_QP != qp_info_p->mark) {\r
- status = IB_INVALID_QP_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- VALIDATE_INDEX(qp_info_p->hca_idx, MLNX_MAX_HCA, IB_INVALID_QP_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[qp_info_p->hca_idx];\r
-\r
- CL_ASSERT(hobul_p);\r
- CL_ASSERT(hobul_p->qp_info_tbl);\r
-\r
- qp_idx = qp_info_p->qp_num & hobul_p->qp_idx_mask;\r
- VALIDATE_INDEX(qp_idx, hobul_p->max_qp, IB_INVALID_QP_HANDLE, cleanup);\r
-\r
-#if MLNX_RECV_NATIVE\r
- return THHUL_qpm_post_recv_wrs( hobul_p->hhul_hndl, qp_info_p->hhul_qp_hndl,\r
- p_recv_wr, pp_failed );\r
-#else\r
- // Assuming that posting all WQE will succeed. Errors are handled below.\r
- *pp_failed = NULL;\r
-\r
- // Loop and post all descriptors in list, bail out on failure.\r
- transport = mlnx_map_ibal_qp_type(qp_info_p->qp_type, &vapi_qp_type);\r
-\r
- if (VAPI_REGULAR_QP != vapi_qp_type)\r
- {\r
- memset(&recv_desc, 0, sizeof(recv_desc));\r
- recv_desc.sg_lst_p = hobul_p->qp_info_tbl[qp_idx].recv_sge_p;\r
- for (wqe_p = p_recv_wr; wqe_p; wqe_p = wqe_p->p_next)\r
- {\r
- // rq_size is a misnomer, it is really max_sge\r
- CL_ASSERT( hobul_p->qp_info_tbl[qp_idx].rq_size >= wqe_p->num_ds);\r
-\r
- mlnx_conv_recv_desc(wqe_p, &recv_desc);\r
- if (HH_OK != (ret = THHUL_qpm_post_recv_req(hobul_p->hhul_hndl, qp_info_p->hhul_qp_hndl, &recv_desc)))\r
- {\r
- status = (HH_EAGAIN == ret) ? IB_INSUFFICIENT_RESOURCES :\r
- (HH_EINVAL_SG_NUM == ret) ? IB_INVALID_MAX_SGE : \r
- IB_ERROR;\r
-\r
- *pp_failed = wqe_p;\r
- // wqe_p->p_next = NULL;\r
- goto cleanup;\r
- }\r
- }\r
- }\r
- else {\r
- // For regular QP use real send multiple\r
- VAPI_rr_desc_t desc_list[MLNX_MAX_WRS_PER_CHAIN];\r
- VAPI_sg_lst_entry_t sg_list[MLNX_MAX_WRS_PER_CHAIN][MLNX_MAX_NUM_SGE];\r
- u_int32_t num_wrs;\r
-\r
- wqe_p = p_recv_wr;\r
- while (wqe_p) {\r
- for (num_wrs = 0; (num_wrs < MLNX_MAX_WRS_PER_CHAIN) && wqe_p; \r
- wqe_p = wqe_p->p_next, num_wrs++)\r
- {\r
- desc_list [num_wrs].sg_lst_p = &sg_list [num_wrs][0];\r
- status = mlnx_conv_recv_desc(wqe_p, &desc_list[num_wrs]);\r
- if (status != IB_SUCCESS) {\r
- CL_TRACE(MLNX_DBG_DIRECT, g_mlnx_dbg_lvl,\r
- ("FAILED to map the recv_desc %d\n", num_wrs));\r
- break;\r
- }\r
- }\r
- // CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("num_wrs %d\n", num_wrs));\r
- if (num_wrs > 0) {\r
- if (num_wrs > 1) {\r
- ret = THHUL_qpm_post_recv_reqs (hobul_p->hhul_hndl,\r
- qp_info_p->hhul_qp_hndl,\r
- num_wrs, desc_list);\r
- } else {\r
- ret = THHUL_qpm_post_recv_req (hobul_p->hhul_hndl,\r
- qp_info_p->hhul_qp_hndl,\r
- desc_list);\r
- }\r
- if (HH_OK != ret) {\r
- status = (HH_EAGAIN == ret) ? IB_INSUFFICIENT_RESOURCES :\r
- (HH_EINVAL_SG_NUM == ret) ? IB_INVALID_MAX_SGE : \r
- IB_ERROR;\r
- *pp_failed = wqe_p;\r
- // wqe_p->p_next = NULL;\r
- goto cleanup;\r
- }\r
- } else {\r
- /* no work requests this round */\r
- CL_TRACE (MLNX_DBG_DIRECT, g_mlnx_dbg_lvl, ("NO WRs\n"));\r
- *pp_failed = wqe_p;\r
- break;\r
- }\r
- }\r
- }\r
-\r
- return status;\r
-#endif\r
-\r
-cleanup:\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- return status;\r
-}\r
-\r
-/*\r
-* Completion Processing and Completion Notification Request Verbs.\r
-*/\r
-\r
-ib_api_status_t\r
-mlnx_peek_cq(\r
- IN const ib_cq_handle_t h_cq,\r
- OUT uint32_t* const p_n_cqes )\r
-{\r
- ib_api_status_t status = IB_UNKNOWN_ERROR;\r
-\r
- u_int32_t hca_idx = CQ_HCA_FROM_HNDL(h_cq);\r
- u_int32_t cq_num = CQ_NUM_FROM_HNDL(h_cq);\r
- u_int32_t cq_idx;\r
- mlnx_hobul_t *hobul_p;\r
- HHUL_cq_hndl_t hhul_cq_hndl;\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_CQ_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p || NULL == hobul_p->cq_info_tbl || NULL == hobul_p->pd_info_tbl) {\r
- status = IB_INVALID_CQ_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- cq_idx = cq_num & hobul_p->cq_idx_mask;\r
- VALIDATE_INDEX(cq_idx, hobul_p->max_cq, IB_INVALID_CQ_HANDLE, cleanup);\r
- if (hobul_p->cq_info_tbl[cq_idx].cq_num != cq_num ||\r
- E_MARK_CQ != hobul_p->cq_info_tbl[cq_idx].mark)\r
- {\r
- status = IB_INVALID_CQ_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- hhul_cq_hndl = hobul_p->cq_info_tbl[cq_idx].hhul_cq_hndl;\r
-\r
- status = THHUL_cqm_count_cqe( \r
- hobul_p->hhul_hndl, hhul_cq_hndl, p_n_cqes );\r
- if( status != IB_SUCCESS )\r
- goto cleanup;\r
-\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_poll_cq (\r
- IN const ib_cq_handle_t h_cq,\r
- IN OUT ib_wc_t** const pp_free_wclist,\r
- OUT ib_wc_t** const pp_done_wclist )\r
-{\r
- ib_api_status_t status = IB_UNKNOWN_ERROR;\r
-\r
- u_int32_t hca_idx = CQ_HCA_FROM_HNDL(h_cq);\r
- u_int32_t cq_num = CQ_NUM_FROM_HNDL(h_cq);\r
- u_int32_t cq_idx;\r
- mlnx_hobul_t *hobul_p;\r
- HHUL_cq_hndl_t hhul_cq_hndl;\r
-#if !MLNX_POLL_NATIVE\r
- HH_ret_t ret;\r
- VAPI_wc_desc_t comp_desc;\r
- ib_wc_t *wc_p;\r
-#endif\r
-\r
- if (!pp_free_wclist || !pp_done_wclist || !*pp_free_wclist) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_CQ_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p || NULL == hobul_p->cq_info_tbl || NULL == hobul_p->pd_info_tbl) {\r
- status = IB_INVALID_CQ_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- cq_idx = cq_num & hobul_p->cq_idx_mask;\r
- VALIDATE_INDEX(cq_idx, hobul_p->max_cq, IB_INVALID_CQ_HANDLE, cleanup);\r
- if (hobul_p->cq_info_tbl[cq_idx].cq_num != cq_num ||\r
- E_MARK_CQ != hobul_p->cq_info_tbl[cq_idx].mark) {\r
- status = IB_INVALID_CQ_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- hhul_cq_hndl = hobul_p->cq_info_tbl[cq_idx].hhul_cq_hndl;\r
-\r
- return THHUL_cqm_poll4wc(hobul_p->hhul_hndl, hhul_cq_hndl,\r
- pp_free_wclist, pp_done_wclist );\r
-\r
-cleanup:\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_enable_cq_notify (\r
- IN const ib_cq_handle_t h_cq,\r
- IN const boolean_t solicited )\r
-{\r
- ib_api_status_t status = IB_UNKNOWN_ERROR;\r
-\r
- u_int32_t hca_idx = CQ_HCA_FROM_HNDL(h_cq);\r
- u_int32_t cq_num = CQ_NUM_FROM_HNDL(h_cq);\r
- u_int32_t cq_idx;\r
- mlnx_hobul_t *hobul_p;\r
- HHUL_cq_hndl_t hhul_cq_hndl;\r
- VAPI_cq_notif_type_t hh_request;\r
-\r
- hh_request = (solicited) ?\r
- VAPI_SOLIC_COMP: /* Notify on solicited completion event only */\r
- VAPI_NEXT_COMP; /* Notify on next completion */\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_CQ_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p || NULL == hobul_p->cq_info_tbl || NULL == hobul_p->pd_info_tbl) {\r
- status = IB_INVALID_CQ_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- cq_idx = cq_num & hobul_p->cq_idx_mask;\r
- VALIDATE_INDEX(cq_idx, hobul_p->max_cq, IB_INVALID_CQ_HANDLE, cleanup);\r
- if (hobul_p->cq_info_tbl[cq_idx].cq_num != cq_num ||\r
- E_MARK_CQ != hobul_p->cq_info_tbl[cq_idx].mark)\r
- {\r
- status = IB_INVALID_CQ_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- hhul_cq_hndl = hobul_p->cq_info_tbl[cq_idx].hhul_cq_hndl;\r
-\r
- if (HH_OK != THHUL_cqm_req_comp_notif(hobul_p->hhul_hndl, hhul_cq_hndl, hh_request))\r
- {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
-\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_enable_ncomp_cq_notify (\r
- IN const ib_cq_handle_t h_cq,\r
- IN const uint32_t n_cqes )\r
-{\r
- ib_api_status_t status = IB_UNKNOWN_ERROR;\r
-\r
- u_int32_t hca_idx = CQ_HCA_FROM_HNDL(h_cq);\r
- u_int32_t cq_num = CQ_NUM_FROM_HNDL(h_cq);\r
- u_int32_t cq_idx;\r
- mlnx_hobul_t *hobul_p;\r
- HHUL_cq_hndl_t hhul_cq_hndl;\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_CQ_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p || NULL == hobul_p->cq_info_tbl || NULL == hobul_p->pd_info_tbl) {\r
- status = IB_INVALID_CQ_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- cq_idx = cq_num & hobul_p->cq_idx_mask;\r
- VALIDATE_INDEX(cq_idx, hobul_p->max_cq, IB_INVALID_CQ_HANDLE, cleanup);\r
- if (hobul_p->cq_info_tbl[cq_idx].cq_num != cq_num ||\r
- E_MARK_CQ != hobul_p->cq_info_tbl[cq_idx].mark)\r
- {\r
- status = IB_INVALID_CQ_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- hhul_cq_hndl = hobul_p->cq_info_tbl[cq_idx].hhul_cq_hndl;\r
-\r
- if (HH_OK != THHUL_cqm_req_ncomp_notif(\r
- hobul_p->hhul_hndl, hhul_cq_hndl, n_cqes ))\r
- {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
-\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_bind_mw (\r
- IN const ib_mw_handle_t h_mw,\r
- IN const ib_qp_handle_t h_qp,\r
- IN ib_bind_wr_t* const p_mw_bind,\r
- OUT net32_t* const p_rkey )\r
-{\r
- ib_api_status_t status = IB_UNKNOWN_ERROR;\r
-\r
- u_int32_t hca_idx = QP_HCA_FROM_HNDL(h_qp);\r
- u_int32_t qp_num = QP_NUM_FROM_HNDL(h_qp);\r
- u_int32_t qp_idx = 0;\r
- u_int32_t new_key;\r
- mlnx_hobul_t *hobul_p;\r
- mlnx_mwo_t *mwo_p;\r
- HHUL_qp_hndl_t hhul_qp_hndl;\r
- HHUL_mw_bind_t bind_props;\r
-\r
- // CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- mwo_p = (mlnx_mwo_t *)h_mw;\r
- if (!mwo_p || mwo_p->mark != E_MARK_MW) {\r
- status = IB_INVALID_MW_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- if (!p_rkey) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_QP_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p || NULL == hobul_p->qp_info_tbl || NULL == hobul_p->pd_info_tbl) {\r
- status = IB_INVALID_QP_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- qp_idx = qp_num & hobul_p->qp_idx_mask;\r
- // CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("line %d - qp_idx 0x%x\n", __LINE__, qp_idx));\r
-\r
- VALIDATE_INDEX(qp_idx, hobul_p->max_qp, IB_INVALID_QP_HANDLE, cleanup);\r
-\r
-#if 0\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("line %d - qp_num 0x%x valid %d\n",\r
- __LINE__,\r
- hobul_p->qp_info_tbl[qp_idx].qp_num,\r
- E_MARK_QP == hobul_p->qp_info_tbl[qp_idx].mark));\r
-#endif\r
- if (hobul_p->qp_info_tbl[qp_idx].qp_num != qp_num ||\r
- E_MARK_QP != hobul_p->qp_info_tbl[qp_idx].mark) {\r
- status = IB_INVALID_QP_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- /* Trap the RKEY passed in not matching. */\r
- if ( cl_ntoh32( p_mw_bind->current_rkey ) != mwo_p->mw_rkey ) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
-\r
- hhul_qp_hndl = hobul_p->qp_info_tbl[qp_idx].hhul_qp_hndl;\r
-\r
- mlnx_conv_bind_req(hobul_p->qp_info_tbl[qp_idx].hhul_qp_hndl, p_mw_bind, &bind_props);\r
-\r
- // Binding a window to zero length is in fact an unbinding\r
- // IF unbinding, window rkey remains the same.\r
- // IF binding, new r_key tag is the previous tag incremented by 1:\r
- new_key = mwo_p->mw_rkey;\r
- if( bind_props.size > 0 ) {\r
- new_key += (1 << hobul_p->log2_mpt_size);\r
- }\r
-\r
- if (HH_OK != THHUL_qpm_post_bind_req(&bind_props, new_key))\r
- {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
-\r
- *p_rkey = cl_hton32( new_key );\r
- // CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- // CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-void\r
-mlnx_direct_if(\r
- IN OUT ci_interface_t *p_interface )\r
-{\r
- p_interface->post_send = mlnx_post_send;\r
- p_interface->post_recv = mlnx_post_recv;\r
-\r
- p_interface->enable_ncomp_cq_notify = mlnx_enable_ncomp_cq_notify;\r
- p_interface->peek_cq = mlnx_peek_cq;\r
- p_interface->poll_cq = mlnx_poll_cq;\r
- p_interface->enable_cq_notify = mlnx_enable_cq_notify;\r
-\r
- p_interface->bind_mw = mlnx_bind_mw;\r
-}\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-/*\r
- * Provides the driver entry points for the Tavor VPD.\r
- */\r
-\r
-\r
-#include "hca_driver.h"\r
-#include <wdmguid.h>\r
-#include <initguid.h>\r
-#pragma warning( push, 3 )\r
-#include "MdCard.h"\r
-#pragma warning( pop )\r
-#include <iba/ib_ci_ifc.h>\r
-#include <complib/cl_init.h>\r
-\r
-\r
-/*\r
- * UVP name does not include file extension. For debug builds, UAL\r
- * will append "d.dll". For release builds, UAL will append ".dll"\r
- */\r
-char mlnx_uvp_lib_name[MAX_LIB_NAME] = {"mt23108u"};\r
-\r
-\r
-NTSTATUS\r
-DriverEntry(\r
- IN PDRIVER_OBJECT p_driver_obj,\r
- IN PUNICODE_STRING p_registry_path );\r
-\r
-static NTSTATUS\r
-__read_registry(\r
- IN UNICODE_STRING* const p_Param_Path );\r
-\r
-static void\r
-hca_drv_unload(\r
- IN PDRIVER_OBJECT p_driver_obj );\r
-\r
-static NTSTATUS\r
-hca_sysctl(\r
- IN PDEVICE_OBJECT p_dev_obj,\r
- IN PIRP p_irp );\r
-\r
-static NTSTATUS\r
-hca_add_device(\r
- IN PDRIVER_OBJECT p_driver_obj,\r
- IN PDEVICE_OBJECT p_pdo );\r
-//\r
-//static NTSTATUS\r
-//hca_enable(\r
-// IN DEVICE_OBJECT* const p_dev_obj );\r
-//\r
-//static NTSTATUS\r
-//hca_disable(\r
-// IN DEVICE_OBJECT* const p_dev_obj );\r
-\r
-static NTSTATUS\r
-hca_start(\r
- IN DEVICE_OBJECT* const p_dev_obj,\r
- IN IRP* const p_irp, \r
- OUT cl_irp_action_t* const p_action );\r
-\r
-static void\r
-hca_release_resources(\r
- IN DEVICE_OBJECT* const p_dev_obj );\r
-\r
-//static NTSTATUS\r
-//hca_deactivate(\r
-// IN DEVICE_OBJECT* const p_dev_obj,\r
-// IN IRP* const p_irp, \r
-// OUT cl_irp_action_t* const p_action );\r
-//\r
-static NTSTATUS\r
-hca_query_bus_relations(\r
- IN DEVICE_OBJECT* const p_dev_obj,\r
- IN IRP* const p_irp, \r
- OUT cl_irp_action_t* const p_action );\r
-\r
-static NTSTATUS\r
-hca_set_power(\r
- IN DEVICE_OBJECT* const p_dev_obj,\r
- IN IRP* const p_irp, \r
- OUT cl_irp_action_t* const p_action );\r
-\r
-static ci_interface_t*\r
-__alloc_hca_ifc(\r
- IN hca_dev_ext_t* const p_ext );\r
-\r
-static NTSTATUS\r
-__get_ci_interface(\r
- IN DEVICE_OBJECT* const p_dev_obj );\r
-\r
-static NTSTATUS\r
-__get_hca_handle(\r
- IN hca_dev_ext_t* const p_ext );\r
-\r
-static NTSTATUS\r
-__hca_register(\r
- IN DEVICE_OBJECT *p_dev_obj );\r
-\r
-//static void\r
-//__work_item_pnp_cb(\r
-// IN DEVICE_OBJECT *p_dev_obj,\r
-// IN hca_work_item_context_t *p_context );\r
-\r
-static NTSTATUS\r
-__pnp_notify_target(\r
- IN TARGET_DEVICE_REMOVAL_NOTIFICATION *p_notify,\r
- IN void *context );\r
-\r
-static NTSTATUS\r
-__pnp_notify_ifc(\r
- IN DEVICE_INTERFACE_CHANGE_NOTIFICATION *p_notify,\r
- IN void *context );\r
-\r
-static NTSTATUS\r
-fw_access_pciconf (\r
- IN BUS_INTERFACE_STANDARD *p_BusInterface,\r
- IN ULONG op_flag,\r
- IN PVOID p_buffer,\r
- IN ULONG offset,\r
- IN ULONG POINTER_ALIGNMENT length );\r
-\r
-static NTSTATUS\r
-fw_get_pci_bus_interface(\r
- IN DEVICE_OBJECT *p_dev_obj,\r
- OUT BUS_INTERFACE_STANDARD *p_BusInterface );\r
-\r
-static NTSTATUS\r
-fw_flash_write_data (\r
- IN BUS_INTERFACE_STANDARD *p_BusInterface,\r
- IN PVOID p_buffer,\r
- IN ULONG offset,\r
- IN ULONG POINTER_ALIGNMENT length );\r
-\r
-static NTSTATUS\r
-fw_flash_read_data (\r
- IN BUS_INTERFACE_STANDARD *p_BusInterface,\r
- IN PVOID p_buffer,\r
- IN ULONG offset,\r
- IN ULONG POINTER_ALIGNMENT length );\r
-\r
-static NTSTATUS\r
-fw_flash_get_ca_guid(\r
- IN DEVICE_OBJECT *p_dev_obj,\r
- OUT uint64_t *ca_guid );\r
-\r
-static NTSTATUS\r
-fw_flash_read4( \r
- IN BUS_INTERFACE_STANDARD *p_BusInterface,\r
- IN uint32_t addr, \r
- IN OUT uint32_t *p_data);\r
-\r
-static NTSTATUS\r
-fw_flash_readbuf(\r
- IN BUS_INTERFACE_STANDARD *p_BusInterface,\r
- IN uint32_t offset,\r
- IN OUT void *p_data,\r
- IN uint32_t len);\r
-static NTSTATUS\r
-fw_set_bank(\r
- IN BUS_INTERFACE_STANDARD *p_BusInterface,\r
- IN uint32_t bank );\r
-\r
-static NTSTATUS\r
-fw_flash_init(\r
- IN BUS_INTERFACE_STANDARD *p_BusInterface );\r
-\r
-static NTSTATUS\r
-fw_flash_deinit(\r
- IN BUS_INTERFACE_STANDARD *p_BusInterface );\r
-\r
-#ifdef ALLOC_PRAGMA\r
-#pragma alloc_text (INIT, DriverEntry)\r
-#pragma alloc_text (INIT, __read_registry)\r
-#pragma alloc_text (PAGE, hca_drv_unload)\r
-#pragma alloc_text (PAGE, hca_sysctl)\r
-#pragma alloc_text (PAGE, hca_add_device)\r
-#pragma alloc_text (PAGE, hca_start)\r
-//#pragma alloc_text (PAGE, hca_deactivate)\r
-//#pragma alloc_text (PAGE, hca_enable)\r
-//#pragma alloc_text (PAGE, hca_disable)\r
-#pragma alloc_text (PAGE, hca_release_resources)\r
-#pragma alloc_text (PAGE, hca_query_bus_relations)\r
-#pragma alloc_text (PAGE, hca_set_power)\r
-#pragma alloc_text (PAGE, __alloc_hca_ifc)\r
-#pragma alloc_text (PAGE, __get_ci_interface)\r
-#pragma alloc_text (PAGE, __get_hca_handle)\r
-#pragma alloc_text (PAGE, __hca_register)\r
-//#pragma alloc_text (PAGE, __work_item_pnp_cb)\r
-#pragma alloc_text (PAGE, __pnp_notify_target)\r
-#pragma alloc_text (PAGE, __pnp_notify_ifc)\r
-#pragma alloc_text (PAGE, fw_flash_get_ca_guid)\r
-#endif\r
-\r
-\r
-static const cl_vfptr_pnp_po_t hca_vfptr_pnp = {\r
- "Tavor HCA VPD",\r
- hca_start, /* StartDevice */\r
- cl_irp_skip,\r
- cl_irp_skip,\r
- cl_do_sync_pnp,\r
- cl_irp_skip, /* QueryRemove */\r
- hca_release_resources,\r
- cl_do_remove, /* Remove */\r
- cl_irp_skip, /* CancelRemove */\r
- cl_irp_skip, /* SurpriseRemove */\r
- cl_irp_skip, \r
- cl_irp_skip,\r
- cl_irp_skip,\r
- cl_do_sync_pnp,\r
- hca_query_bus_relations,\r
- cl_irp_ignore,\r
- cl_irp_skip,\r
- cl_irp_ignore,\r
- cl_irp_ignore,\r
- cl_irp_ignore,\r
- cl_irp_ignore,\r
- cl_irp_ignore,\r
- cl_irp_ignore,\r
- cl_irp_ignore,\r
- cl_irp_ignore,\r
- cl_irp_ignore,\r
- cl_irp_ignore,\r
- cl_irp_ignore, /* QueryPower */\r
- hca_set_power, /* SetPower */\r
- cl_irp_ignore, /* PowerSequence */\r
- cl_irp_ignore /* WaitWake */\r
-};\r
-\r
-\r
-NTSTATUS\r
-DriverEntry(\r
- IN PDRIVER_OBJECT p_driver_obj,\r
- IN PUNICODE_STRING p_registry_path )\r
-{\r
- NTSTATUS status;\r
- cl_status_t cl_status;\r
-\r
- HCA_ENTER( HCA_DBG_DEV );\r
-\r
- status = CL_INIT;\r
- if( !NT_SUCCESS(status) )\r
- {\r
- HCA_TRACE_EXIT( HCA_DBG_ERROR,\r
- ("cl_init returned %08X.\n", status) );\r
- return status;\r
- }\r
-\r
- status = __read_registry( p_registry_path );\r
- if( !NT_SUCCESS( status ) )\r
- {\r
- CL_DEINIT;\r
- HCA_TRACE_EXIT( HCA_DBG_ERROR,\r
- ("__read_registry_path returned 0x%X.\n", status) );\r
- return status;\r
- }\r
-\r
- /* Initializae Adapter DB */\r
- cl_status = mlnx_hobs_init();\r
- if( cl_status != CL_SUCCESS )\r
- {\r
- CL_DEINIT;\r
- HCA_TRACE_EXIT( HCA_DBG_ERROR,\r
- ("mlnx_hobs_init returned %#x.\n", cl_status) );\r
- return cl_to_ntstatus( cl_status );\r
- }\r
-// cl_memclr( mlnx_hca_array, MLNX_MAX_HCA * sizeof(ci_interface_t) );\r
-\r
- p_driver_obj->MajorFunction[IRP_MJ_PNP] = cl_pnp;\r
- p_driver_obj->MajorFunction[IRP_MJ_POWER] = cl_power;\r
- p_driver_obj->MajorFunction[IRP_MJ_SYSTEM_CONTROL] = hca_sysctl;\r
- p_driver_obj->DriverUnload = hca_drv_unload;\r
- p_driver_obj->DriverExtension->AddDevice = hca_add_device;\r
-\r
- HCA_EXIT( HCA_DBG_DEV );\r
- return STATUS_SUCCESS;\r
-}\r
-\r
-\r
-static NTSTATUS\r
-__read_registry(\r
- IN UNICODE_STRING* const p_registry_path )\r
-{\r
- NTSTATUS status;\r
- /* Remember the terminating entry in the table below. */\r
- RTL_QUERY_REGISTRY_TABLE table[2];\r
- UNICODE_STRING param_path;\r
-\r
- HCA_ENTER( HCA_DBG_DEV );\r
-\r
- RtlInitUnicodeString( ¶m_path, NULL );\r
- param_path.MaximumLength = p_registry_path->Length + \r
- sizeof(L"\\Parameters");\r
- param_path.Buffer = cl_zalloc( param_path.MaximumLength );\r
- if( !param_path.Buffer )\r
- {\r
- HCA_TRACE_EXIT( HCA_DBG_ERROR, \r
- ("Failed to allocate parameters path buffer.\n") );\r
- return STATUS_INSUFFICIENT_RESOURCES;\r
- }\r
-\r
- RtlAppendUnicodeStringToString( ¶m_path, p_registry_path );\r
- RtlAppendUnicodeToString( ¶m_path, L"\\Parameters" );\r
-\r
- /*\r
- * Clear the table. This clears all the query callback pointers,\r
- * and sets up the terminating table entry.\r
- */\r
- cl_memclr( table, sizeof(table) );\r
-\r
- /* Setup the table entries. */\r
- table[0].Flags = RTL_QUERY_REGISTRY_DIRECT;\r
- table[0].Name = L"DebugFlags";\r
- table[0].EntryContext = &g_mlnx_dbg_lvl;\r
- table[0].DefaultType = REG_DWORD;\r
- table[0].DefaultData = &g_mlnx_dbg_lvl;\r
- table[0].DefaultLength = sizeof(ULONG);\r
-\r
- /* Have at it! */\r
- status = RtlQueryRegistryValues( RTL_REGISTRY_ABSOLUTE, \r
- param_path.Buffer, table, NULL, NULL );\r
-\r
- cl_free( param_path.Buffer );\r
- HCA_EXIT( HCA_DBG_DEV );\r
- return status;\r
-}\r
-\r
-\r
-static void\r
-hca_drv_unload(\r
- IN PDRIVER_OBJECT p_driver_obj )\r
-{\r
- HCA_ENTER( HCA_DBG_DEV );\r
-\r
- UNUSED_PARAM( p_driver_obj );\r
-\r
- CL_DEINIT;\r
-\r
- HCA_EXIT( HCA_DBG_DEV );\r
-}\r
-\r
-\r
-static NTSTATUS\r
-hca_sysctl(\r
- IN PDEVICE_OBJECT p_dev_obj,\r
- IN PIRP p_irp )\r
-{\r
- NTSTATUS status;\r
- hca_dev_ext_t *p_ext;\r
-\r
- HCA_ENTER( HCA_DBG_DEV );\r
-\r
- p_ext = p_dev_obj->DeviceExtension;\r
-\r
- IoSkipCurrentIrpStackLocation( p_irp );\r
- status = IoCallDriver( p_ext->cl_ext.p_next_do, p_irp );\r
-\r
- HCA_EXIT( HCA_DBG_DEV );\r
- return status;\r
-}\r
-\r
-\r
-static NTSTATUS\r
-hca_add_device(\r
- IN PDRIVER_OBJECT p_driver_obj,\r
- IN PDEVICE_OBJECT p_pdo )\r
-{\r
- NTSTATUS status;\r
- DEVICE_OBJECT *p_dev_obj, *p_next_do;\r
- hca_dev_ext_t *p_ext;\r
- //cl_status_t cl_status;\r
-\r
- HCA_ENTER( HCA_DBG_PNP );\r
-\r
- /*\r
- * Create the device so that we have a device extension to store stuff in.\r
- */\r
- status = IoCreateDevice( p_driver_obj, sizeof(hca_dev_ext_t),\r
- NULL, FILE_DEVICE_INFINIBAND, FILE_DEVICE_SECURE_OPEN,\r
- FALSE, &p_dev_obj );\r
- if( !NT_SUCCESS( status ) )\r
- {\r
- HCA_TRACE_EXIT( HCA_DBG_ERROR,\r
- ("IoCreateDevice returned 0x%08X.\n", status) );\r
- return status;\r
- }\r
-\r
- p_ext = p_dev_obj->DeviceExtension;\r
-\r
- //cl_status = cl_event_init( &p_ext->mutex, FALSE );\r
- //if( cl_status != CL_SUCCESS )\r
- //{\r
- // IoDeleteDevice( p_dev_obj );\r
- // HCA_TRACE_EXIT( HCA_DBG_ERROR,\r
- // ("cl_mutex_init returned %#x.\n", cl_status) );\r
- // return cl_to_ntstatus( cl_status );\r
- //}\r
- //cl_event_signal( &p_ext->mutex );\r
-\r
- /* Attach to the device stack. */\r
- p_next_do = IoAttachDeviceToDeviceStack( p_dev_obj, p_pdo );\r
- if( !p_next_do )\r
- {\r
- //cl_event_destroy( &p_ext->mutex );\r
- IoDeleteDevice( p_dev_obj );\r
- HCA_TRACE_EXIT( HCA_DBG_ERROR,\r
- ("IoAttachDeviceToDeviceStack failed.\n") );\r
- return STATUS_NO_SUCH_DEVICE;\r
- }\r
-\r
- /* Inititalize the complib extension. */\r
- cl_init_pnp_po_ext( p_dev_obj, p_next_do, p_pdo, g_mlnx_dbg_lvl,\r
- &hca_vfptr_pnp, NULL );\r
-\r
- p_ext->state = HCA_ADDED;\r
-\r
- HCA_EXIT( HCA_DBG_PNP );\r
- return status;\r
-}\r
-\r
-\r
-static NTSTATUS\r
-__get_ci_interface(\r
- IN DEVICE_OBJECT* const p_dev_obj )\r
-{\r
- NTSTATUS status;\r
- IRP *p_irp;\r
- hca_dev_ext_t *p_ext;\r
- IO_STATUS_BLOCK io_status;\r
- IO_STACK_LOCATION *p_io_stack;\r
- KEVENT event;\r
-\r
- HCA_ENTER( HCA_DBG_PNP );\r
-\r
- p_ext = p_dev_obj->DeviceExtension;\r
-\r
- KeInitializeEvent( &event, NotificationEvent, FALSE );\r
-\r
- /* Query for the verbs interface. */\r
- p_irp = IoBuildSynchronousFsdRequest( IRP_MJ_PNP, p_ext->p_al_dev,\r
- NULL, 0, NULL, &event, &io_status );\r
- if( !p_irp )\r
- {\r
- HCA_TRACE_EXIT( HCA_DBG_ERROR,\r
- ("IoBuildSynchronousFsdRequest failed.\n") );\r
- return STATUS_INSUFFICIENT_RESOURCES;\r
- }\r
-\r
- /* Format the IRP. */\r
- p_io_stack = IoGetNextIrpStackLocation( p_irp );\r
- p_io_stack->MinorFunction = IRP_MN_QUERY_INTERFACE;\r
- p_io_stack->Parameters.QueryInterface.Version = IB_CI_INTERFACE_VERSION;\r
- p_io_stack->Parameters.QueryInterface.Size = sizeof(ib_ci_ifc_t);\r
- p_io_stack->Parameters.QueryInterface.Interface = \r
- (INTERFACE*)&p_ext->ci_ifc;\r
- p_io_stack->Parameters.QueryInterface.InterfaceSpecificData = NULL;\r
- p_io_stack->Parameters.QueryInterface.InterfaceType = \r
- &GUID_IB_CI_INTERFACE;\r
- p_irp->IoStatus.Status = STATUS_NOT_SUPPORTED;\r
-\r
- /* Send the IRP. */\r
- status = IoCallDriver( p_ext->p_al_dev, p_irp );\r
- if( status == STATUS_PENDING )\r
- {\r
- KeWaitForSingleObject( &event, Executive, KernelMode, \r
- FALSE, NULL );\r
-\r
- status = io_status.Status;\r
- }\r
-\r
- if( !NT_SUCCESS( status ) )\r
- {\r
- HCA_TRACE_EXIT( HCA_DBG_ERROR,\r
- ("Query interface for verbs returned %08x.\n", status) );\r
- return status;\r
- }\r
-\r
- HCA_EXIT( HCA_DBG_PNP );\r
- return status;\r
-}\r
-\r
-\r
-static NTSTATUS\r
-__get_hca_handle(\r
- IN hca_dev_ext_t* const p_ext )\r
-{\r
- NTSTATUS status;\r
- IRP *p_irp;\r
- IO_STATUS_BLOCK io_status;\r
- IO_STACK_LOCATION *p_io_stack;\r
- KEVENT event;\r
-\r
- HCA_ENTER( HCA_DBG_PNP );\r
-\r
- KeInitializeEvent( &event, NotificationEvent, FALSE );\r
-\r
- /* Query for the verbs interface. */\r
- p_irp = IoBuildSynchronousFsdRequest( IRP_MJ_PNP, p_ext->cl_ext.p_next_do,\r
- NULL, 0, NULL, &event, &io_status );\r
- if( !p_irp )\r
- {\r
- HCA_TRACE_EXIT( HCA_DBG_ERROR,\r
- ("IoBuildSynchronousFsdRequest failed.\n") );\r
- return STATUS_INSUFFICIENT_RESOURCES;\r
- }\r
-\r
- /* Format the IRP. */\r
- p_io_stack = IoGetNextIrpStackLocation( p_irp );\r
- p_io_stack->MinorFunction = IRP_MN_QUERY_INTERFACE;\r
- p_io_stack->Parameters.QueryInterface.Version = 1;\r
- p_io_stack->Parameters.QueryInterface.Size = 0;\r
- p_io_stack->Parameters.QueryInterface.Interface = NULL;\r
- { \r
- void *p = &p_ext->hca.s;\r
- memset( p, 0, sizeof(p_ext->hca.s) );\r
- p_io_stack->Parameters.QueryInterface.InterfaceSpecificData = p;\r
- }\r
- p_io_stack->Parameters.QueryInterface.InterfaceType = \r
- &GUID_MD_INTERFACE;\r
- p_irp->IoStatus.Status = STATUS_NOT_SUPPORTED;\r
-\r
- /* Send the IRP. */\r
- status = IoCallDriver( p_ext->cl_ext.p_next_do, p_irp );\r
- if( status == STATUS_PENDING )\r
- {\r
- KeWaitForSingleObject( &event, Executive, KernelMode, \r
- FALSE, NULL );\r
-\r
- status = io_status.Status;\r
- }\r
-\r
- if( !NT_SUCCESS( status ) )\r
- {\r
- HCA_TRACE_EXIT( HCA_DBG_ERROR,\r
- ("Query interface for HCA handle returned %08x.\n", status) );\r
- return status;\r
- }\r
- p_ext->hca.hh_hndl = p_ext->hca.s.hh_hndl;\r
- \r
- HCA_EXIT( HCA_DBG_PNP );\r
- return status;\r
-}\r
-\r
-\r
-static NTSTATUS\r
-__pnp_notify_target(\r
- IN TARGET_DEVICE_REMOVAL_NOTIFICATION *p_notify,\r
- IN void *context )\r
-{\r
- NTSTATUS status = STATUS_SUCCESS;\r
- DEVICE_OBJECT *p_dev_obj;\r
- hca_dev_ext_t *p_ext;\r
-\r
- HCA_ENTER( HCA_DBG_PNP );\r
-\r
- p_dev_obj = context;\r
- p_ext = p_dev_obj->DeviceExtension;\r
-\r
- if( IsEqualGUID( &p_notify->Event, &GUID_TARGET_DEVICE_QUERY_REMOVE ) )\r
- {\r
- if( p_ext->state == HCA_REGISTERED )\r
- {\r
- /* Release AL's CI interface. */\r
- p_ext->ci_ifc.wdm.InterfaceDereference( p_ext->ci_ifc.wdm.Context );\r
- p_ext->state = HCA_STARTED;\r
- }\r
-\r
- /* Release AL's file object so that it can unload. */\r
- CL_ASSERT( p_ext->p_al_file_obj );\r
- CL_ASSERT( p_ext->p_al_file_obj == p_notify->FileObject );\r
- ObDereferenceObject( p_ext->p_al_file_obj );\r
- p_ext->p_al_file_obj = NULL;\r
- p_ext->p_al_dev = NULL;\r
- }\r
- else if( IsEqualGUID( &p_notify->Event, \r
- &GUID_TARGET_DEVICE_REMOVE_COMPLETE ) )\r
- {\r
- if( p_ext->state == HCA_REGISTERED )\r
- {\r
- /* Release AL's CI interface. */\r
- p_ext->ci_ifc.wdm.InterfaceDereference( p_ext->ci_ifc.wdm.Context );\r
- p_ext->state = HCA_STARTED;\r
- }\r
-\r
- /* Release AL's file object so that it can unload. */\r
- if( p_ext->p_al_file_obj )\r
- {\r
- ObDereferenceObject( p_ext->p_al_file_obj );\r
- p_ext->p_al_file_obj = NULL;\r
- p_ext->p_al_dev = NULL;\r
- }\r
-\r
- /* Cancel our target device change registration. */\r
- IoUnregisterPlugPlayNotification( p_ext->pnp_target_entry );\r
- p_ext->pnp_target_entry = NULL;\r
- }\r
- else if( IsEqualGUID( &p_notify->Event, \r
- &GUID_TARGET_DEVICE_REMOVE_CANCELLED ) )\r
- {\r
- /* Cancel our target device change registration. */\r
- IoUnregisterPlugPlayNotification( p_ext->pnp_target_entry );\r
- p_ext->pnp_target_entry = NULL;\r
-\r
- /* Get the device object pointer for the AL. */\r
- CL_ASSERT( !p_ext->p_al_file_obj );\r
- CL_ASSERT( !p_ext->p_al_dev );\r
- p_ext->p_al_file_obj = p_notify->FileObject;\r
- p_ext->p_al_dev = IoGetRelatedDeviceObject( p_ext->p_al_file_obj );\r
-\r
- status = IoRegisterPlugPlayNotification( \r
- EventCategoryTargetDeviceChange, 0, p_ext->p_al_file_obj, \r
- p_dev_obj->DriverObject, __pnp_notify_target, p_dev_obj, \r
- &p_ext->pnp_target_entry );\r
- if( !NT_SUCCESS( status ) )\r
- {\r
- HCA_TRACE_EXIT( HCA_DBG_ERROR, \r
- ("IoRegisterPlugPlayNotification returned %08x.\n") );\r
- return status;\r
- }\r
-\r
- __hca_register( p_dev_obj );\r
- }\r
-\r
- HCA_EXIT( HCA_DBG_PNP );\r
- return status;\r
-}\r
-\r
-\r
-static ci_interface_t*\r
-__alloc_hca_ifc(\r
- IN hca_dev_ext_t* const p_ext )\r
-{\r
- ci_interface_t *p_ifc;\r
-\r
- HCA_ENTER( HCA_DBG_PNP );\r
-\r
- p_ifc = ExAllocatePoolWithTag( PagedPool, sizeof(ci_interface_t), 'fiha' );\r
- if( !p_ifc )\r
- {\r
- HCA_TRACE_EXIT( HCA_DBG_ERROR,\r
- ("Failed to allocate ci_interface_t (%d bytes).\n",\r
- sizeof(ci_interface_t)) );\r
- return NULL;\r
- }\r
-\r
- setup_ci_interface( p_ext->hca.guid, p_ifc );\r
-\r
- p_ifc->p_hca_dev = p_ext->cl_ext.p_pdo;\r
- p_ifc->vend_id = p_ext->hca.hh_hndl->vendor_id;\r
- p_ifc->dev_id = (uint16_t)p_ext->hca.hh_hndl->dev_id;\r
- p_ifc->dev_revision = (uint16_t)p_ext->hca.hh_hndl->hw_ver;\r
-\r
- HCA_EXIT( HCA_DBG_PNP );\r
- return p_ifc;\r
-}\r
-\r
-\r
-static NTSTATUS\r
-__hca_register(\r
- IN DEVICE_OBJECT *p_dev_obj )\r
-{\r
- hca_dev_ext_t *p_ext;\r
- NTSTATUS status;\r
- ib_api_status_t ib_status;\r
- ci_interface_t *p_hca_ifc;\r
-\r
- HCA_ENTER( HCA_DBG_PNP );\r
- \r
- p_ext = p_dev_obj->DeviceExtension;\r
-\r
- ASSERT( p_ext->state == HCA_STARTED );\r
- ASSERT( p_ext->p_al_dev );\r
-\r
- /* Get the AL's lower interface. */\r
- status = __get_ci_interface( p_dev_obj );\r
- if( !NT_SUCCESS( status ) )\r
- {\r
- HCA_TRACE( HCA_DBG_ERROR,\r
- ("__get_ci_interface returned %08x.\n", status) );\r
- return status;\r
- }\r
-\r
- /* Allocate and populate our HCA interface structure. */\r
- p_hca_ifc = __alloc_hca_ifc( p_ext );\r
- if( !p_hca_ifc )\r
- {\r
- HCA_TRACE( HCA_DBG_ERROR, ("__alloc_hca_ifc failed.\n") );\r
- return STATUS_NO_MEMORY;\r
- }\r
-\r
- /* Notify AL that we're available... */\r
- ib_status = p_ext->ci_ifc.register_ca( p_hca_ifc );\r
- ExFreePool( p_hca_ifc );\r
- if( ib_status != IB_SUCCESS )\r
- {\r
- p_ext->ci_ifc.wdm.InterfaceDereference( p_ext->ci_ifc.wdm.Context );\r
- return STATUS_INSUFFICIENT_RESOURCES;\r
- }\r
-\r
- p_ext->state = HCA_REGISTERED;\r
- return STATUS_SUCCESS;\r
-}\r
-\r
-\r
-//static void\r
-//__work_item_pnp_cb(\r
-// IN DEVICE_OBJECT *p_dev_obj,\r
-// IN hca_work_item_context_t *p_context )\r
-//{\r
-// hca_dev_ext_t *p_ext;\r
-// NTSTATUS status;\r
-//\r
-// HCA_ENTER( HCA_DBG_PNP );\r
-// \r
-// p_ext = p_dev_obj->DeviceExtension;\r
-//\r
-// cl_event_wait_on( &p_ext->mutex, EVENT_NO_TIMEOUT, FALSE );\r
-// do\r
-// {\r
-// /* Check the state under protection of the mutex. */\r
-// if( p_ext->state != HCA_ADDED &&\r
-// p_ext->state != HCA_STARTED )\r
-// {\r
-// HCA_TRACE( HCA_DBG_ERROR, ("Invalid state.\n") );\r
-// break;\r
-// }\r
-//\r
-// ASSERT( !p_ext->p_al_dev );\r
-//\r
-// /* Get the AL device object. */\r
-// HCA_TRACE( HCA_DBG_PNP, ("Calling IoGetDeviceObjectPointer.\n") );\r
-// status = IoGetDeviceObjectPointer( &p_context->sym_link_name,\r
-// FILE_ALL_ACCESS, &p_ext->p_al_file_obj, &p_ext->p_al_dev );\r
-// if( !NT_SUCCESS( status ) )\r
-// {\r
-// HCA_TRACE( HCA_DBG_ERROR,\r
-// ("IoGetDeviceObjectPointer returned %08x.\n", status) );\r
-// break;\r
-// }\r
-//\r
-// cl_event_signal( &p_ext->mutex );\r
-// /* Register for removal notification of the IB Fabric root device. */\r
-// HCA_TRACE( HCA_DBG_PNP, \r
-// ("Registering for target notifications.\n") );\r
-// status = IoRegisterPlugPlayNotification( \r
-// EventCategoryTargetDeviceChange, 0, p_ext->p_al_file_obj, \r
-// p_dev_obj->DriverObject, __pnp_notify_target, p_dev_obj, \r
-// &p_ext->pnp_target_entry );\r
-// cl_event_wait_on( &p_ext->mutex, EVENT_NO_TIMEOUT, FALSE );\r
-// if( !NT_SUCCESS( status ) )\r
-// {\r
-// ObDereferenceObject( p_ext->p_al_file_obj );\r
-// HCA_TRACE( HCA_DBG_ERROR, \r
-// ("IoRegisterPlugPlayNotification returned %08x.\n", status) );\r
-// break;\r
-// }\r
-//\r
-// if( p_ext->state == HCA_STARTED )\r
-// {\r
-// /* Queue the work item again to complete the registration. */\r
-// IoQueueWorkItem( p_context->p_item, __work_item_started_cb, \r
-// DelayedWorkQueue, p_context->p_item );\r
-// }\r
-// else\r
-// {\r
-// /* Free the work item. */\r
-// IoFreeWorkItem( p_context->p_item );\r
-// }\r
-// } while( !p_ext );\r
-//\r
-// cl_event_signal( &p_ext->mutex );\r
-// cl_free( p_context );\r
-// return;\r
-//}\r
-\r
-\r
-static NTSTATUS\r
-__pnp_notify_ifc(\r
- IN DEVICE_INTERFACE_CHANGE_NOTIFICATION *p_notify,\r
- IN void *context )\r
-{\r
- NTSTATUS status;\r
- DEVICE_OBJECT *p_dev_obj;\r
- hca_dev_ext_t *p_ext;\r
-\r
- HCA_ENTER( HCA_DBG_PNP );\r
-\r
- p_dev_obj = context;\r
- p_ext = p_dev_obj->DeviceExtension;\r
-\r
- if( !IsEqualGUID( &p_notify->Event, &GUID_DEVICE_INTERFACE_ARRIVAL ) )\r
- {\r
- HCA_EXIT( HCA_DBG_PNP );\r
- return STATUS_SUCCESS;\r
- }\r
-\r
- /*\r
- * Sanity check. We should only be getting notifications of the \r
- * CI interface exported by AL.\r
- */\r
- ASSERT( \r
- IsEqualGUID( &p_notify->InterfaceClassGuid, &GUID_IB_CI_INTERFACE ) );\r
-\r
- if( p_ext->state != HCA_STARTED )\r
- {\r
- HCA_TRACE( HCA_DBG_ERROR, ("Invalid state: %d\n", p_ext->state) );\r
- return STATUS_SUCCESS;\r
- }\r
-\r
- ASSERT( !p_ext->p_al_dev );\r
- ASSERT( !p_ext->p_al_file_obj );\r
-\r
- /* Get the AL device object. */\r
- HCA_TRACE( HCA_DBG_PNP, ("Calling IoGetDeviceObjectPointer.\n") );\r
- status = IoGetDeviceObjectPointer( p_notify->SymbolicLinkName,\r
- FILE_ALL_ACCESS, &p_ext->p_al_file_obj, &p_ext->p_al_dev );\r
- if( !NT_SUCCESS( status ) )\r
- {\r
- HCA_TRACE( HCA_DBG_ERROR,\r
- ("IoGetDeviceObjectPointer returned %08x.\n", status) );\r
- return STATUS_SUCCESS;\r
- }\r
-\r
- /* Register for removal notification of the IB Fabric root device. */\r
- HCA_TRACE( HCA_DBG_PNP, \r
- ("Registering for target notifications.\n") );\r
- status = IoRegisterPlugPlayNotification( \r
- EventCategoryTargetDeviceChange, 0, p_ext->p_al_file_obj, \r
- p_dev_obj->DriverObject, __pnp_notify_target, p_dev_obj, \r
- &p_ext->pnp_target_entry );\r
- if( !NT_SUCCESS( status ) )\r
- {\r
- ObDereferenceObject( p_ext->p_al_file_obj );\r
- p_ext->p_al_file_obj = NULL;\r
- p_ext->p_al_dev = NULL;\r
- HCA_TRACE( HCA_DBG_ERROR, \r
- ("IoRegisterPlugPlayNotification returned %08x.\n", status) );\r
- return STATUS_SUCCESS;\r
- }\r
-\r
- status = __hca_register( p_dev_obj );\r
- if( !NT_SUCCESS( status ) )\r
- {\r
- IoUnregisterPlugPlayNotification( p_ext->pnp_target_entry );\r
- p_ext->pnp_target_entry = NULL;\r
- ObDereferenceObject( p_ext->p_al_file_obj );\r
- p_ext->p_al_file_obj = NULL;\r
- p_ext->p_al_dev = NULL;\r
- HCA_TRACE( HCA_DBG_ERROR,\r
- ("__get_ci_interface returned %08x.\n", status) );\r
- return STATUS_SUCCESS;\r
- }\r
-\r
- HCA_EXIT( HCA_DBG_PNP );\r
- return STATUS_SUCCESS;\r
-}\r
-//\r
-//\r
-//static NTSTATUS\r
-//hca_enable(\r
-// IN DEVICE_OBJECT* const p_dev_obj )\r
-//{\r
-// PIO_WORKITEM p_item;\r
-// hca_dev_ext_t *p_ext;\r
-//\r
-// HCA_ENTER( HCA_DBG_PNP );\r
-//\r
-// p_ext = p_dev_obj->DeviceExtension;\r
-//\r
-// /* Check for the AL device reference. */\r
-// if( p_ext->p_al_dev )\r
-// {\r
-// __hca_register( p_dev_obj );\r
-// }\r
-// p_ext->state = HCA_STARTED;\r
-//\r
-// HCA_EXIT( HCA_DBG_PNP );\r
-// return STATUS_SUCCESS;\r
-//}\r
-\r
-\r
-static NTSTATUS\r
-hca_start(\r
- IN DEVICE_OBJECT* const p_dev_obj,\r
- IN IRP* const p_irp, \r
- OUT cl_irp_action_t* const p_action )\r
-{\r
- NTSTATUS status;\r
- hca_dev_ext_t *p_ext;\r
-\r
- HCA_ENTER( HCA_DBG_PNP );\r
-\r
- /* Handled on the way up. */\r
- status = cl_do_sync_pnp( p_dev_obj, p_irp, p_action );\r
- if( !NT_SUCCESS( status ) )\r
- {\r
- HCA_TRACE_EXIT( HCA_DBG_ERROR, \r
- ("Lower drivers failed IRP_MN_START_DEVICE.\n") );\r
- return status;\r
- }\r
-\r
- p_ext = p_dev_obj->DeviceExtension;\r
-\r
- /* Get the HH HCA handle for this instance. */\r
- status = __get_hca_handle( p_ext );\r
- if( !NT_SUCCESS( status ) )\r
- {\r
- HCA_TRACE_EXIT( HCA_DBG_ERROR,\r
- ("Failed to get HH HCA handle.\n") );\r
- return status;\r
- }\r
-\r
- {\r
- VAPI_hca_cap_t hca_cap;\r
- int rc;\r
-\r
- if (HH_OK != THH_hob_open_hca(p_ext->hca.hh_hndl, NULL, NULL)) {\r
- status = IB_ERROR;\r
- return status;\r
- }\r
- \r
- rc = THH_hob_query(p_ext->hca.hh_hndl, &hca_cap);\r
- if (rc != HH_OK) {\r
- HCA_TRACE( HCA_DBG_ERROR, ("Error on getting guid (%#x).\n", rc) );\r
- status = IB_ERROR;\r
- return status;\r
- }\r
- p_ext->hca.guid = *(uint64_t *)hca_cap.node_guid;\r
- p_ext->hca.p_dev_obj = p_ext->cl_ext.p_pdo;\r
-\r
- THH_hob_close_hca(p_ext->hca.hh_hndl);\r
- }\r
-\r
- mlnx_hca_insert( &p_ext->hca );\r
-\r
- /*\r
- * Change the state since the PnP callback can happen\r
- * before the callback returns.\r
- */\r
- p_ext->state = HCA_STARTED;\r
- /* Register for interface arrival of the IB_AL device. */\r
- status = IoRegisterPlugPlayNotification(\r
- EventCategoryDeviceInterfaceChange,\r
- PNPNOTIFY_DEVICE_INTERFACE_INCLUDE_EXISTING_INTERFACES,\r
- (void*)&GUID_IB_CI_INTERFACE, p_dev_obj->DriverObject,\r
- __pnp_notify_ifc, p_dev_obj, &p_ext->pnp_ifc_entry );\r
- if( !NT_SUCCESS( status ) )\r
- {\r
- p_ext->state = HCA_ADDED;\r
- HCA_TRACE( HCA_DBG_ERROR, \r
- ("IoRegisterPlugPlayNotification returned %08x.\n", status) );\r
- }\r
-\r
- HCA_EXIT( HCA_DBG_PNP );\r
- return status;\r
-}\r
-\r
-\r
-static void\r
-hca_release_resources(\r
- IN DEVICE_OBJECT* const p_dev_obj )\r
-{\r
- hca_dev_ext_t *p_ext;\r
-\r
- HCA_ENTER( HCA_DBG_PNP );\r
-\r
- p_ext = p_dev_obj->DeviceExtension;\r
-\r
- if( p_ext->state == HCA_REGISTERED )\r
- {\r
- CL_ASSERT( p_ext->ci_ifc.deregister_ca );\r
- CL_ASSERT( p_ext->p_al_dev );\r
- CL_ASSERT( p_ext->p_al_file_obj );\r
- /* Notify AL that the CA is being removed. */\r
- p_ext->ci_ifc.deregister_ca( p_ext->hca.guid );\r
- /* Release AL's CI interface. */\r
- p_ext->ci_ifc.wdm.InterfaceDereference( p_ext->ci_ifc.wdm.Context );\r
- }\r
-\r
- if( p_ext->pnp_target_entry )\r
- {\r
- ASSERT( p_ext->pnp_ifc_entry );\r
- IoUnregisterPlugPlayNotification( p_ext->pnp_target_entry );\r
- }\r
-\r
- if( p_ext->pnp_ifc_entry )\r
- IoUnregisterPlugPlayNotification( p_ext->pnp_ifc_entry );\r
-\r
- if( p_ext->p_al_file_obj )\r
- ObDereferenceObject( p_ext->p_al_file_obj );\r
-\r
- //cl_event_destroy( &p_ext->mutex );\r
-\r
- HCA_EXIT( HCA_DBG_PNP );\r
-}\r
-//\r
-//\r
-//static NTSTATUS\r
-//hca_disable(\r
-// IN DEVICE_OBJECT* const p_dev_obj )\r
-//{\r
-// hca_dev_ext_t *p_ext;\r
-//\r
-// HCA_ENTER( HCA_DBG_PNP );\r
-//\r
-// p_ext = p_dev_obj->DeviceExtension;\r
-//\r
-// ASSERT( p_ext->state == HCA_STARTED );\r
-//\r
-// if( p_ext->state = HCA_REGISTERED )\r
-// {\r
-// /* Notify AL that the CA is being removed. */\r
-// p_ext->ci_ifc.deregister_ca( p_ext->hca.guid );\r
-// /* Release AL's CI interface. */\r
-// p_ext->ci_ifc.wdm.InterfaceDereference( p_ext->ci_ifc.wdm.Context );\r
-//\r
-// p_ext->state = HCA_STARTED;\r
-// }\r
-//\r
-// HCA_EXIT( HCA_DBG_PNP );\r
-// return STATUS_SUCCESS;\r
-//}\r
-//\r
-//\r
-//static NTSTATUS\r
-//hca_deactivate(\r
-// IN DEVICE_OBJECT* const p_dev_obj,\r
-// IN IRP* const p_irp, \r
-// OUT cl_irp_action_t* const p_action )\r
-//{\r
-// NTSTATUS status;\r
-// hca_dev_ext_t *p_ext;\r
-//\r
-// HCA_ENTER( HCA_DBG_PNP );\r
-//\r
-// UNUSED_PARAM( p_irp );\r
-//\r
-// p_ext = p_dev_obj->DeviceExtension;\r
-//\r
-// *p_action = IrpSkip;\r
-//\r
-// status = hca_disable( p_dev_obj );\r
-//\r
-// mlnx_hca_remove( &p_ext->hca );\r
-//\r
-// p_ext->hca.hh_hndl = NULL;\r
-//\r
-// p_ext->state = HCA_ADDED;\r
-//\r
-// HCA_EXIT( HCA_DBG_PNP );\r
-// return status;\r
-//}\r
-\r
-\r
-static NTSTATUS\r
-hca_query_bus_relations(\r
- IN DEVICE_OBJECT* const p_dev_obj,\r
- IN IRP* const p_irp, \r
- OUT cl_irp_action_t* const p_action )\r
-{\r
- NTSTATUS status;\r
- DEVICE_RELATIONS *p_rel;\r
- hca_dev_ext_t *p_ext;\r
-\r
- HCA_ENTER( HCA_DBG_PNP );\r
-\r
- p_ext = p_dev_obj->DeviceExtension;\r
-\r
- //cl_event_wait_on( &p_ext->mutex, EVENT_NO_TIMEOUT, FALSE );\r
- if( p_ext->state == HCA_REGISTERED )\r
- {\r
- status = p_ext->ci_ifc.get_relations( p_ext->hca.guid, p_irp );\r
- if( !NT_SUCCESS( status ) )\r
- {\r
- //cl_event_signal( &p_ext->mutex );\r
- *p_action = IrpComplete;\r
- HCA_TRACE_EXIT( HCA_DBG_ERROR,\r
- ("AL get_relations returned %08x.\n", status) );\r
- return status;\r
- }\r
- }\r
- else\r
- {\r
- status = cl_alloc_relations( p_irp, 1 );\r
- if( !NT_SUCCESS( status ) )\r
- {\r
- HCA_TRACE_EXIT( HCA_DBG_ERROR,\r
- ("cl_alloc_relations returned %08x.\n", status) );\r
- return status;\r
- }\r
-\r
- p_rel = (DEVICE_RELATIONS*)p_irp->IoStatus.Information;\r
- p_rel->Count = 0;\r
- p_rel->Objects[0] = NULL;\r
- }\r
-\r
- //cl_event_signal( &p_ext->mutex );\r
-\r
- *p_action = IrpPassDown;\r
- HCA_EXIT( HCA_DBG_PNP );\r
- return STATUS_SUCCESS;\r
-}\r
-\r
-\r
-static NTSTATUS\r
-hca_set_power(\r
- IN DEVICE_OBJECT* const p_dev_obj,\r
- IN IRP* const p_irp, \r
- OUT cl_irp_action_t* const p_action )\r
-{\r
- NTSTATUS status;\r
- hca_dev_ext_t *p_ext;\r
- IO_STACK_LOCATION *p_io_stack;\r
-\r
- HCA_ENTER( HCA_DBG_PNP );\r
-\r
- p_ext = p_dev_obj->DeviceExtension;\r
-\r
- *p_action = IrpSkip;\r
-\r
- p_io_stack = IoGetCurrentIrpStackLocation( p_irp );\r
-\r
- if( p_io_stack->Parameters.Power.Type != DevicePowerState )\r
- return STATUS_SUCCESS;\r
-\r
- switch( p_io_stack->Parameters.Power.State.DeviceState )\r
- {\r
- case PowerDeviceD0:\r
- if( p_ext->p_al_dev )\r
- status = __hca_register( p_dev_obj );\r
- else\r
- status = STATUS_SUCCESS;\r
- break;\r
-\r
- default:\r
- if( p_ext->state == HCA_REGISTERED )\r
- {\r
- /* Notify AL that the CA is being removed. */\r
- p_ext->ci_ifc.deregister_ca( p_ext->hca.guid );\r
- /* Release AL's CI interface. */\r
- p_ext->ci_ifc.wdm.InterfaceDereference( p_ext->ci_ifc.wdm.Context );\r
-\r
- p_ext->state = HCA_STARTED;\r
- }\r
- status = STATUS_SUCCESS;\r
- break;\r
- }\r
-\r
- if( !NT_SUCCESS( status ) )\r
- *p_action = IrpComplete;\r
-\r
- HCA_EXIT( HCA_DBG_PNP );\r
- return status;\r
-}\r
-\r
-typedef struct Primary_Sector{\r
- uint32_t fi_addr;\r
- uint32_t fi_size;\r
- uint32_t signature;\r
- uint32_t fw_reserved[5];\r
- uint32_t vsd[56];\r
- uint32_t branch_to;\r
- uint32_t crc016;\r
-} primary_sector_t;\r
-\r
-static uint32_t old_dir;\r
-static uint32_t old_pol;\r
-static uint32_t old_mod;\r
-static uint32_t old_dat;\r
-\r
-static NTSTATUS\r
-fw_access_pciconf (\r
- IN BUS_INTERFACE_STANDARD *p_BusInterface,\r
- IN ULONG op_flag,\r
- IN PVOID p_buffer,\r
- IN ULONG offset,\r
- IN ULONG POINTER_ALIGNMENT length )\r
-{\r
-\r
- ULONG bytes; \r
- NTSTATUS status = STATUS_SUCCESS;\r
-\r
- PAGED_CODE();\r
-\r
- if (p_BusInterface)\r
- {\r
-\r
- bytes = p_BusInterface->SetBusData(\r
- p_BusInterface->Context,\r
- PCI_WHICHSPACE_CONFIG,\r
- (PVOID)&offset,\r
- PCI_CONF_ADDR,\r
- sizeof(ULONG) );\r
-\r
- if( op_flag == 0 )\r
- {\r
- if ( bytes )\r
- bytes = p_BusInterface->GetBusData(\r
- p_BusInterface->Context,\r
- PCI_WHICHSPACE_CONFIG,\r
- p_buffer,\r
- PCI_CONF_DATA,\r
- length );\r
- if ( !bytes )\r
- status = STATUS_NOT_SUPPORTED;\r
- }\r
-\r
- else\r
- {\r
- if ( bytes )\r
- bytes = p_BusInterface->SetBusData(\r
- p_BusInterface->Context,\r
- PCI_WHICHSPACE_CONFIG,\r
- p_buffer,\r
- PCI_CONF_DATA,\r
- length);\r
-\r
- if ( !bytes )\r
- status = STATUS_NOT_SUPPORTED;\r
- }\r
- }\r
- return status;\r
-}\r
-\r
-static NTSTATUS\r
-fw_get_pci_bus_interface(\r
- IN DEVICE_OBJECT *p_dev_obj,\r
- OUT BUS_INTERFACE_STANDARD *p_BusInterface )\r
-{\r
- KEVENT event;\r
- NTSTATUS status;\r
- PIRP p_irp;\r
- IO_STATUS_BLOCK ioStatus;\r
- PIO_STACK_LOCATION p_irpStack;\r
- PDEVICE_OBJECT p_target_obj;\r
-\r
- KeInitializeEvent( &event, NotificationEvent, FALSE );\r
-\r
- p_target_obj = IoGetAttachedDeviceReference( p_dev_obj );\r
-\r
- p_irp = IoBuildSynchronousFsdRequest( IRP_MJ_PNP,\r
- p_target_obj,\r
- NULL,\r
- 0,\r
- NULL,\r
- &event,\r
- &ioStatus );\r
- if (p_irp == NULL)\r
- {\r
- HCA_TRACE( HCA_DBG_ERROR,\r
- ("IoBuildSynchronousFsdRequest failed.\n") );\r
- status = STATUS_INSUFFICIENT_RESOURCES;\r
- goto End;\r
- }\r
- p_irpStack = IoGetNextIrpStackLocation( p_irp );\r
- p_irpStack->MinorFunction = IRP_MN_QUERY_INTERFACE;\r
- p_irpStack->Parameters.QueryInterface.InterfaceType = (LPGUID) &GUID_BUS_INTERFACE_STANDARD;\r
- p_irpStack->Parameters.QueryInterface.Size = sizeof(BUS_INTERFACE_STANDARD);\r
- p_irpStack->Parameters.QueryInterface.Version = 1;\r
- p_irpStack->Parameters.QueryInterface.Interface = (PINTERFACE) p_BusInterface;\r
- p_irpStack->Parameters.QueryInterface.InterfaceSpecificData = NULL;\r
-\r
- p_irp->IoStatus.Status = STATUS_NOT_SUPPORTED;\r
- \r
- status = IoCallDriver( p_target_obj, p_irp );\r
-\r
- if ( status == STATUS_PENDING )\r
- {\r
- KeWaitForSingleObject( &event, Executive, KernelMode, FALSE, NULL );\r
- status = ioStatus.Status;\r
- }\r
-End:\r
- // Done with reference\r
- ObDereferenceObject( p_target_obj );\r
- return status;\r
-}\r
-\r
-static NTSTATUS\r
-__map_crspace(\r
- IN mlnx_hob_t * p_hob,\r
- IN PVOID p_buf,\r
- IN ULONG buf_size\r
- )\r
-{\r
- NTSTATUS status;\r
- PMDL mdl_p;\r
- mlnx_hca_t *p_hca = mlnx_hca_from_hh_hndl(p_hob->hh_hndl);\r
- PVOID ua, ka; \r
- ULONG sz; \r
- struct _map_crspace *res_p = (struct _map_crspace *)p_buf;\r
-\r
- HCA_ENTER( HCA_DBG_PNP );\r
-\r
- // sanity checks\r
- if ( buf_size < sizeof *res_p ) {\r
- status = STATUS_INVALID_PARAMETER;\r
- goto out;\r
- }\r
- if (p_hca == NULL) {\r
- status = STATUS_UNSUCCESSFUL;\r
- goto out;\r
- }\r
- ka = p_hca->s.kernel_crspace_addr;\r
- sz = p_hca->s.kernel_crspace_size;\r
- if ( sz == 0 || ka == NULL) {\r
- HCA_TRACE( HCA_DBG_ERROR, ("No kernel mapping of CR space.\n") );\r
- status = STATUS_UNSUCCESSFUL;\r
- goto out;\r
- }\r
-\r
- // prepare for mapping to user space \r
- mdl_p = IoAllocateMdl( ka, sz, FALSE,FALSE,NULL);\r
- if (mdl_p == NULL) {\r
- HCA_TRACE( HCA_DBG_ERROR, ("IoAllocateMdl failed.\n") );\r
- status = STATUS_INSUFFICIENT_RESOURCES;\r
- goto out;\r
- }\r
-\r
- // fill MDL\r
- MmBuildMdlForNonPagedPool(mdl_p); \r
- \r
- // map the buffer into user space \r
- ua = MmMapLockedPagesSpecifyCache( mdl_p, UserMode, MmNonCached, \r
- NULL, FALSE, NormalPagePriority );\r
- if (ua == NULL) {\r
- HCA_TRACE( HCA_DBG_ERROR, ("MmMapLockedPagesSpecifyCache failed.\n") );\r
- IoFreeMdl( mdl_p );\r
- status = STATUS_UNSUCCESSFUL;\r
- goto out;\r
- }\r
- \r
- // fill the structure\r
- res_p->va = ua;\r
- res_p->size = sz;\r
- res_p->ctx = mdl_p;\r
- status = STATUS_SUCCESS;\r
-\r
-out: \r
- HCA_EXIT( HCA_DBG_PNP );\r
- return status;\r
-}\r
-\r
-static NTSTATUS\r
-__unmap_crspace(\r
- IN PVOID p_buf,\r
- IN ULONG buf_size\r
- )\r
-{\r
- NTSTATUS status;\r
- PMDL mdl_p;\r
- PVOID ua;\r
- struct _unmap_crspace *parm = (struct _unmap_crspace *)p_buf;\r
-\r
- HCA_ENTER( HCA_DBG_PNP );\r
-\r
- // sanity checks\r
- if ( buf_size < sizeof *parm ) {\r
- status = STATUS_INVALID_PARAMETER;\r
- goto out;\r
- }\r
- mdl_p = parm->ctx;\r
- ua = parm->va;\r
- if ( mdl_p == NULL || ua == NULL) {\r
- status = STATUS_INVALID_PARAMETER;\r
- goto out;\r
- }\r
-\r
- // do the work\r
- MmUnmapLockedPages(ua, mdl_p);\r
- IoFreeMdl( mdl_p );\r
- status = STATUS_SUCCESS;\r
-\r
-out: \r
- HCA_EXIT( HCA_DBG_PNP );\r
- return status;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-fw_access_ctrl(\r
- IN const void* __ptr64 p_context,\r
- IN const void* __ptr64* const handle_array OPTIONAL,\r
- IN uint32_t num_handles,\r
- IN ib_ci_op_t* const p_ci_op,\r
- IN OUT ci_umv_buf_t *p_umv_buf )\r
-{\r
- DEVICE_OBJECT *p_dev_obj;\r
- static BUS_INTERFACE_STANDARD BusInterface;\r
- static uint32_t if_ready;\r
- NTSTATUS status;\r
- PVOID p_data;\r
- ULONG offset;\r
- ULONG POINTER_ALIGNMENT length;\r
- ib_ci_op_t *p_ci;\r
- mlnx_hob_t *p_hob;\r
-\r
- UNREFERENCED_PARAMETER(handle_array);\r
- UNREFERENCED_PARAMETER(num_handles);\r
- UNREFERENCED_PARAMETER(p_umv_buf);\r
-\r
- status = STATUS_SUCCESS;\r
- if( p_umv_buf )\r
- p_hob = ((mlnx_um_ca_t* __ptr64)p_context)->hob_p;\r
- else\r
- p_hob = (mlnx_hob_t *)(const void *)p_context;\r
-\r
- p_dev_obj = (DEVICE_OBJECT *)(const void *)p_hob->p_dev_obj;\r
- p_ci = p_ci_op;\r
-\r
- if ( !p_ci )\r
- return STATUS_INVALID_DEVICE_REQUEST;\r
- if ( !p_ci->buf_size )\r
- return STATUS_INVALID_DEVICE_REQUEST;\r
-\r
- length = p_ci->buf_size;\r
- offset = p_ci->buf_info;\r
- p_data = p_ci->p_buf;\r
-\r
- switch ( p_ci->command )\r
- {\r
- case FW_MAP_CRSPACE:\r
- status = __map_crspace(p_hob, p_data, length);\r
- break;\r
- \r
- case FW_UNMAP_CRSPACE:\r
- status = __unmap_crspace(p_data, length);\r
- break;\r
- \r
- case FW_READ: // read data from flash\r
- if ( if_ready )\r
- {\r
- status = fw_flash_read_data(&BusInterface, p_data, offset, length);\r
- }\r
- break;\r
- case FW_WRITE: // write data to flash\r
- if ( if_ready )\r
- {\r
-\r
- status = fw_flash_write_data(&BusInterface, p_data, offset, length);\r
- }\r
- break;\r
- case FW_READ_CMD:\r
- if ( if_ready )\r
- {\r
- status = fw_access_pciconf(&BusInterface, 0 , p_data, offset, 4);\r
- }\r
- break;\r
- case FW_WRITE_CMD:\r
- if ( if_ready )\r
- {\r
- status = fw_access_pciconf(&BusInterface, 1 , p_data, offset, 4);\r
- }\r
- break;\r
- case FW_CLOSE_IF: // close BusInterface\r
- if (if_ready )\r
- {\r
- if_ready = 0;\r
- BusInterface.InterfaceDereference((PVOID)BusInterface.Context);\r
- }\r
- return status;\r
- case FW_OPEN_IF: // open BusInterface\r
- if ( !if_ready )\r
- {\r
- status = fw_get_pci_bus_interface(p_dev_obj, &BusInterface);\r
- \r
- if ( NT_SUCCESS( status ) )\r
- {\r
- if_ready = 1;\r
- status = STATUS_SUCCESS;\r
- }\r
- }\r
- return status;\r
- default:\r
- status = STATUS_NOT_SUPPORTED;\r
- }\r
-\r
- if ( status != STATUS_SUCCESS )\r
- {\r
- if ( if_ready )\r
- {\r
- if_ready = 0;\r
- BusInterface.InterfaceDereference((PVOID)BusInterface.Context);\r
- }\r
- HCA_TRACE_EXIT( HCA_DBG_ERROR,\r
- ("fw_access_ctrl failed returns %08x.\n", status) );\r
- }\r
- return status;\r
-}\r
-\r
-static NTSTATUS\r
-fw_flash_write_data (\r
- IN BUS_INTERFACE_STANDARD *p_BusInterface,\r
- IN PVOID p_buffer,\r
- IN ULONG offset,\r
- IN ULONG POINTER_ALIGNMENT length )\r
-{\r
- NTSTATUS status;\r
- uint32_t cnt = 0;\r
- uint32_t lcl_data;\r
-\r
- lcl_data = (*((uint32_t*)p_buffer) << 24);\r
-\r
- status = fw_access_pciconf(p_BusInterface, FW_WRITE , &lcl_data, FLASH_OFFSET+4, length );\r
- if ( status != STATUS_SUCCESS )\r
- return status;\r
- lcl_data = ( WRITE_BIT | (offset & ADDR_MSK));\r
- \r
- status = fw_access_pciconf(p_BusInterface, FW_WRITE , &lcl_data, FLASH_OFFSET, 4 );\r
- if ( status != STATUS_SUCCESS )\r
- return status;\r
-\r
- lcl_data = 0;\r
- \r
- do\r
- {\r
- if (++cnt > 5000)\r
- {\r
- return STATUS_DEVICE_NOT_READY;\r
- }\r
-\r
- status = fw_access_pciconf(p_BusInterface, FW_READ , &lcl_data, FLASH_OFFSET, 4 );\r
- if ( status != STATUS_SUCCESS )\r
- return status;\r
-\r
- } while(lcl_data & CMD_MASK);\r
-\r
- return status;\r
-}\r
-\r
-static NTSTATUS\r
-fw_flash_read_data (\r
- IN BUS_INTERFACE_STANDARD *p_BusInterface,\r
- IN PVOID p_buffer,\r
- IN ULONG offset,\r
- IN ULONG POINTER_ALIGNMENT length )\r
-{\r
- NTSTATUS status = STATUS_SUCCESS;\r
- uint32_t cnt = 0;\r
- uint32_t lcl_data = ( READ_BIT | (offset & ADDR_MSK));\r
- \r
- status = fw_access_pciconf(p_BusInterface, FW_WRITE, &lcl_data, FLASH_OFFSET, 4 );\r
- if ( status != STATUS_SUCCESS )\r
- return status;\r
-\r
- lcl_data = 0;\r
- do\r
- {\r
- // Timeout checks\r
- if (++cnt > 5000 )\r
- {\r
- return STATUS_DEVICE_NOT_READY;\r
- }\r
-\r
- status = fw_access_pciconf(p_BusInterface, FW_READ, &lcl_data, FLASH_OFFSET, 4 );\r
- \r
- if ( status != STATUS_SUCCESS )\r
- return status;\r
-\r
- } while(lcl_data & CMD_MASK);\r
-\r
- status = fw_access_pciconf(p_BusInterface, FW_READ, p_buffer, FLASH_OFFSET+4, length );\r
- return status;\r
-}\r
-\r
-static NTSTATUS\r
-fw_flash_get_ca_guid(\r
- IN DEVICE_OBJECT *p_dev_obj,\r
- OUT net64_t *ca_guid )\r
-{\r
- NTSTATUS status = STATUS_SUCCESS;\r
- BUS_INTERFACE_STANDARD BusInterface;\r
-\r
- uint32_t NODE_GUIDH, NODE_GUIDL;\r
- uint32_t prim_ptr = 0;\r
- uint32_t signature, offset, sect_size;\r
-\r
- primary_sector_t ps;\r
- cl_memset( &ps, 0, sizeof(primary_sector_t));\r
-\r
- status = fw_get_pci_bus_interface(p_dev_obj, &BusInterface);\r
-\r
- if ( !NT_SUCCESS( status ) )\r
- return status;\r
- \r
- status = fw_flash_init (&BusInterface);\r
- if (status != STATUS_SUCCESS )\r
- goto err1;\r
-\r
- status = fw_flash_read_data(&BusInterface, &signature, FW_SIG_OFFSET, 4);\r
- if (status != STATUS_SUCCESS )\r
- goto err2;\r
-\r
- if (signature == FW_SIGNATURE)\r
- {\r
- //Fail Safe image\r
-\r
- /* Find the sector size offset. */\r
- status = fw_flash_read_data(\r
- &BusInterface, &offset, FW_SECT_PTR_OFFSET, 4 );\r
- if( status != STATUS_SUCCESS )\r
- goto err2;\r
-\r
- offset &= 0x0000FFFF;\r
-\r
- status = fw_flash_read_data(\r
- &BusInterface, §_size, FW_SECT_OFFSET + offset, 4 );\r
- if( status != STATUS_SUCCESS )\r
- goto err2;\r
-\r
- sect_size = 1 << (sect_size & 0x0000FFFF);\r
-\r
- /* Try to read the GUIDs from the primary image. */\r
- status = fw_flash_readbuf(&BusInterface, sect_size, &ps, sizeof(ps));\r
- if ( status == STATUS_SUCCESS && ps.signature != FW_SIGNATURE )\r
- {\r
- /* Hmm, that didn't work. Try the secondary image. */\r
- status = fw_flash_readbuf(\r
- &BusInterface, sect_size * 2, &ps, sizeof(ps) );\r
- }\r
- if( status == STATUS_SUCCESS )\r
- {\r
- signature = ps.signature;\r
- status = fw_flash_read_data(&BusInterface, &prim_ptr, ps.fi_addr+0x24, 4);\r
- if (status == STATUS_SUCCESS )\r
- prim_ptr = prim_ptr + ps.fi_addr;\r
- }\r
- else\r
- {\r
- signature = 0;\r
- }\r
- }\r
- else\r
- {\r
- // Short image\r
- HCA_TRACE( HCA_DBG_ERROR,\r
- ("Invalid signature %08x, assuming short image.\n", signature) );\r
- prim_ptr = signature; \r
- signature = FW_SIGNATURE;\r
- }\r
-\r
- if ( signature == FW_SIGNATURE && prim_ptr < MAX_FLASH_SIZE )\r
- {\r
- /* now we can read ca guid\r
- * since we read it in host mode fw_flash_read4() \r
- * swaps it back in BE - how it was stored in FW\r
- */\r
- if (( status = fw_flash_read4(&BusInterface, prim_ptr, &NODE_GUIDL)) == STATUS_SUCCESS )\r
- if (( status = fw_flash_read4(&BusInterface, prim_ptr+4, &NODE_GUIDH)) == STATUS_SUCCESS )\r
- {\r
- *ca_guid = NODE_GUIDH;\r
- *ca_guid = (*ca_guid << 32) | NODE_GUIDL;\r
- }\r
- }\r
- else \r
- {\r
- //invalid GUID pointer\r
- status = STATUS_NO_SUCH_DEVICE;\r
- }\r
-err2:\r
- fw_flash_deinit(&BusInterface);\r
-err1:\r
- BusInterface.InterfaceDereference((PVOID)BusInterface.Context);\r
- return status;\r
-}\r
-\r
-static NTSTATUS\r
-fw_flash_read4( \r
- IN BUS_INTERFACE_STANDARD *p_BusInterface,\r
- IN uint32_t addr, \r
- IN OUT uint32_t *p_data)\r
-{\r
- NTSTATUS status = STATUS_SUCCESS;\r
- uint32_t lcl_data = 0;\r
- uint32_t bank;\r
- static uint32_t curr_bank = 0xffffffff;\r
-\r
- if (addr & 0x3)\r
- {\r
- HCA_TRACE( HCA_DBG_ERROR, ("Invalid address %08x\n", addr) );\r
- return STATUS_INVALID_PARAMETER;\r
- }\r
-\r
- bank = addr & BANK_MASK;\r
- if (bank != curr_bank)\r
- {\r
- curr_bank = bank;\r
- if ((status = fw_set_bank(p_BusInterface, bank)) != STATUS_SUCCESS )\r
- {\r
- HCA_TRACE( HCA_DBG_ERROR, ("fw_set_bank returned %08x\n", status) );\r
- return STATUS_INVALID_PARAMETER;\r
- }\r
- }\r
- status = fw_flash_read_data(p_BusInterface, &lcl_data, addr, 4);\r
- *p_data = cl_ntoh32(lcl_data);\r
- return STATUS_SUCCESS;\r
-}\r
-\r
-static NTSTATUS\r
-fw_flash_readbuf(\r
- IN BUS_INTERFACE_STANDARD *p_BusInterface,\r
- IN uint32_t offset,\r
- IN OUT void *p_data,\r
- IN uint32_t len)\r
-{\r
- NTSTATUS status = STATUS_SUCCESS;\r
- uint32_t *p_lcl_data;\r
- uint32_t i;\r
-\r
- if (offset & 0x3)\r
- {\r
- //Address should be 4-bytes aligned\r
- HCA_TRACE( HCA_DBG_ERROR, ("Invalid address %08x\n", offset) );\r
- return STATUS_INVALID_PARAMETER;\r
- }\r
- if (len & 0x3)\r
- {\r
- //Length should be 4-bytes aligned\r
- HCA_TRACE( HCA_DBG_ERROR, ("Invalid length %d\n", len) );\r
- return STATUS_INVALID_PARAMETER;\r
- }\r
- p_lcl_data = (uint32_t *)p_data;\r
- \r
- for ( i=0; i < (len >> 2); i++)\r
- { \r
- if ( (status = fw_flash_read_data( p_BusInterface, p_lcl_data, offset, sizeof(uint32_t) )) != STATUS_SUCCESS )\r
- return status;\r
- offset += 4;\r
- p_lcl_data++;\r
- }\r
- return STATUS_SUCCESS;\r
-} // Flash::flash_read\r
-\r
-static NTSTATUS\r
-fw_flash_writebuf(\r
- IN BUS_INTERFACE_STANDARD *p_BusInterface,\r
- IN PVOID p_buffer,\r
- IN ULONG offset,\r
- IN ULONG POINTER_ALIGNMENT length )\r
-{\r
- NTSTATUS status = STATUS_SUCCESS;\r
- uint32_t i;\r
- uint8_t *p_data = (uint8_t *)p_buffer;\r
-\r
- for ( i = 0; i < length; i++ )\r
- {\r
- status = fw_flash_write_data (p_BusInterface, p_data, offset, 1 );\r
- if (status != STATUS_SUCCESS )\r
- return status;\r
- p_data++;\r
- offset++;\r
- }\r
- return status;\r
-}\r
-static NTSTATUS\r
-fw_flash_init(\r
- IN BUS_INTERFACE_STANDARD *p_BusInterface )\r
-{\r
- uint32_t dir;\r
- uint32_t pol;\r
- uint32_t mod;\r
-\r
- uint32_t cnt=0;\r
- uint32_t data;\r
- NTSTATUS status = STATUS_SUCCESS;\r
- uint32_t semaphore = 0;\r
- \r
- while ( !semaphore )\r
- {\r
- status = fw_access_pciconf(p_BusInterface, FW_READ , &data, SEMAP63, 4);\r
- if ( status != STATUS_SUCCESS )\r
- break;\r
- if( !data )\r
- {\r
- semaphore = 1;\r
- break;\r
- }\r
- if (++cnt > 5000 )\r
- {\r
- break;\r
- }\r
- } \r
-\r
- if ( !semaphore )\r
- {\r
- return STATUS_NOT_SUPPORTED;\r
- }\r
-\r
- // Save old values\r
- \r
- status = fw_access_pciconf(p_BusInterface, FW_READ , &old_dir,GPIO_DIR_L , 4);\r
- if ( status == STATUS_SUCCESS )\r
- status = fw_access_pciconf(p_BusInterface, FW_READ , &old_pol,GPIO_POL_L , 4);\r
- if ( status == STATUS_SUCCESS )\r
- status = fw_access_pciconf(p_BusInterface, FW_READ , &old_mod,GPIO_MOD_L , 4);\r
- if ( status == STATUS_SUCCESS )\r
- status = fw_access_pciconf(p_BusInterface, FW_READ , &old_dat,GPIO_DAT_L , 4);\r
-\r
- // Set Direction=1, Polarity=0, Mode=0 for 3 GPIO lower bits\r
- dir = old_dir | 0x70;\r
- pol = old_pol & ~0x70;\r
- mod = old_mod & ~0x70;\r
-\r
- status = fw_access_pciconf(p_BusInterface, FW_WRITE , &dir,GPIO_DIR_L , 4);\r
- if ( status == STATUS_SUCCESS )\r
- status = fw_access_pciconf(p_BusInterface, FW_WRITE , &pol,GPIO_POL_L , 4);\r
- if ( status == STATUS_SUCCESS )\r
- status = fw_access_pciconf(p_BusInterface, FW_WRITE , &mod,GPIO_MOD_L , 4);\r
- if ( status == STATUS_SUCCESS )\r
- // Set CPUMODE\r
- status = fw_access_pciconf(p_BusInterface, FW_READ , &data, CPUMODE, 4);\r
- if ( status == STATUS_SUCCESS )\r
- {\r
- data &= ~CPUMODE_MSK;\r
- data |= 1 << CPUMODE_SHIFT;\r
- status = fw_access_pciconf(p_BusInterface, FW_WRITE , &data, CPUMODE, 4);\r
- }\r
- if ( status == STATUS_SUCCESS )\r
- {\r
- // Reset flash\r
- data = 0xf0;\r
- status = fw_flash_write_data(p_BusInterface, &data, 0x0, 4);\r
- }\r
- return status;\r
-}\r
-\r
-static NTSTATUS\r
-fw_flash_deinit(\r
- IN BUS_INTERFACE_STANDARD *p_BusInterface )\r
-{\r
- uint32_t data = 0;\r
- NTSTATUS status = STATUS_SUCCESS;\r
- \r
- status = fw_set_bank(p_BusInterface, 0);\r
- if ( status == STATUS_SUCCESS )\r
- // Restore origin values\r
- status = fw_access_pciconf(p_BusInterface, FW_WRITE , &old_dir,GPIO_DIR_L , 4);\r
- if ( status == STATUS_SUCCESS )\r
- status = fw_access_pciconf(p_BusInterface, FW_WRITE , &old_pol,GPIO_POL_L , 4);\r
- if ( status == STATUS_SUCCESS )\r
- status = fw_access_pciconf(p_BusInterface, FW_WRITE , &old_mod,GPIO_MOD_L , 4);\r
- if ( status == STATUS_SUCCESS )\r
- status = fw_access_pciconf(p_BusInterface, FW_WRITE , &old_dat,GPIO_DAT_L , 4);\r
- if ( status == STATUS_SUCCESS )\r
- // Free GPIO Semaphore\r
- status = fw_access_pciconf(p_BusInterface, FW_WRITE , &data, SEMAP63, 4);\r
- return status;\r
-}\r
-\r
-static NTSTATUS\r
-fw_set_bank(\r
- IN BUS_INTERFACE_STANDARD *p_BusInterface,\r
- IN uint32_t bank )\r
-{\r
- NTSTATUS status = STATUS_SUCCESS;\r
- uint32_t data = ( (uint32_t)0x70 << 24 );\r
- uint32_t mask = ((bank >> (BANK_SHIFT-4)) << 24 );\r
-\r
- status = fw_access_pciconf(p_BusInterface, FW_WRITE , &data, GPIO_DATACLEAR_L, 4);\r
- if (status == STATUS_SUCCESS)\r
- {\r
- // A1\r
- data &= mask;\r
- //data |= mask; // for A0\r
- status = fw_access_pciconf(p_BusInterface, FW_WRITE , &data, GPIO_DATASET_L, 4);\r
- }\r
- return status;\r
-}\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#if !defined( _HCA_DRIVER_H_ )\r
-#define _HCA_DRIVER_H_\r
-\r
-\r
-#include <complib/cl_types.h>\r
-#include <complib/cl_pnp_po.h>\r
-#include <complib/cl_mutex.h>\r
-#include <iba/ib_ci_ifc.h>\r
-#include "hca_debug.h"\r
-#include "hca_data.h"\r
-\r
-\r
-#if !defined(FILE_DEVICE_INFINIBAND) // Not defined in WXP DDK\r
-#define FILE_DEVICE_INFINIBAND 0x0000003B\r
-#endif\r
-\r
-/****s* HCA/hca_reg_state_t\r
-* NAME\r
-* hca_reg_state_t\r
-*\r
-* DESCRIPTION\r
-* State for tracking registration with AL. This state is independent of the\r
-* device PnP state, and both are used to properly register with AL.\r
-*\r
-* SYNOPSIS\r
-*/\r
-typedef enum _hca_reg_state\r
-{\r
- HCA_SHUTDOWN,\r
- HCA_ADDED,\r
- HCA_STARTED,\r
- HCA_REGISTERED\r
-\r
-} hca_reg_state_t;\r
-/*\r
-* VALUES\r
-* HCA_SHUTDOWN\r
-* Cleaning up.\r
-*\r
-* HCA_ADDED\r
-* AddDevice was called and successfully registered for interface\r
-* notifications.\r
-*\r
-* HCA_STARTED\r
-* IRP_MN_START_DEVICE was called. The HCA is fully functional.\r
-*\r
-* HCA_REGISTERED\r
-* Fully functional and registered with the bus root.\r
-*********/\r
-\r
-\r
-typedef struct _hca_dev_ext\r
-{\r
- cl_pnp_po_ext_t cl_ext;\r
-\r
- /* Notification entry for PnP interface events. */\r
- void *pnp_ifc_entry;\r
-\r
- /* Notification entry for PnP target events. */\r
- void *pnp_target_entry;\r
-\r
- /* Interface for the lower edge of the IB_AL device. */\r
- ib_ci_ifc_t ci_ifc;\r
-\r
- hca_reg_state_t state;\r
-\r
- DEVICE_OBJECT *p_al_dev;\r
- FILE_OBJECT *p_al_file_obj;\r
-\r
- mlnx_hca_t hca;\r
-\r
-} hca_dev_ext_t;\r
-\r
-/***********************************\r
-Firmware Update definitions\r
-***********************************/\r
-#define PCI_CONF_ADDR (0x00000058)\r
-#define PCI_CONF_DATA (0x0000005c)\r
-#define FLASH_OFFSET (0x000f01a4)\r
-#define READ_BIT (1<<29)\r
-#define WRITE_BIT (2<<29)\r
-#define ADDR_MSK (0x0007ffff)\r
-#define CMD_MASK (0xe0000000)\r
-#define BANK_SHIFT (19)\r
-#define BANK_MASK (0xfff80000)\r
-#define MAX_FLASH_SIZE (0x80000) // 512K\r
-\r
-#define SEMAP63 (0xf03fc)\r
-#define GPIO_DIR_L (0xf008c)\r
-#define GPIO_POL_L (0xf0094)\r
-#define GPIO_MOD_L (0xf009c)\r
-#define GPIO_DAT_L (0xf0084)\r
-#define GPIO_DATACLEAR_L (0xf00d4)\r
-#define GPIO_DATASET_L (0xf00dc)\r
-\r
-#define CPUMODE (0xf0150)\r
-#define CPUMODE_MSK (0xc0000000UL)\r
-#define CPUMODE_SHIFT (30)\r
-\r
-/* buffer structure for FW_MAP_CRBASE */\r
-struct _map_crspace {\r
- PVOID va; /* address of CRSPACE, mapped to user space */\r
- PVOID ctx; /* opaque operation context; to be used in FW_UNMAP_CRBASE */\r
- ULONG size; /* size of CRSPACE, mapped to user space */\r
-};\r
-\r
-struct _unmap_crspace {\r
- PVOID va; /* address of CRSPACE, mapped to user space */\r
- PVOID ctx; /* operation context, received in FW_MAP_CRBASE */\r
-};\r
-\r
-/* Definitions intended to become shared with UM. Later... */\r
-#define FW_READ 0x00\r
-#define FW_WRITE 0x01\r
-#define FW_READ_CMD 0x08\r
-#define FW_WRITE_CMD 0x09\r
-#define FW_MAP_CRSPACE 0x0A\r
-#define FW_UNMAP_CRSPACE 0x0B\r
-#define FW_OPEN_IF 0xe7\r
-#define FW_CLOSE_IF 0x7e\r
-\r
-#define FW_SIGNATURE (0x5a445a44)\r
-#define FW_SIG_OFFSET (0x24)\r
-\r
-#define FW_SECT_PTR_OFFSET (0x14)\r
-/* The real offset is 0x32, but we're reading DWORDS at a time, so we align */\r
-#define FW_SECT_OFFSET (0x30)\r
-\r
-\r
-#endif /* !defined( _HCA_DRIVER_H_ ) */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies, Inc. All rights reserved. \r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#include <iba/ib_ci.h>\r
-#include <complib/comp_lib.h>\r
-\r
-#include <vapi.h>\r
-#include <evapi.h>\r
-#include <thhul_pdm.h>\r
-#include <thhul_cqm.h>\r
-#include <thhul_qpm.h>\r
-\r
-#include "hca_data.h"\r
-\r
-/*\r
-* Multicast Support Verbs.\r
-*/\r
-ib_api_status_t\r
-mlnx_attach_mcast (\r
- IN const ib_qp_handle_t h_qp,\r
- IN const ib_gid_t *p_mcast_gid,\r
- IN const uint16_t mcast_lid,\r
- OUT ib_mcast_handle_t *ph_mcast,\r
- IN OUT ci_umv_buf_t *p_umv_buf )\r
-{\r
- ib_api_status_t status;\r
-\r
- u_int32_t hca_idx = QP_HCA_FROM_HNDL(h_qp);\r
- u_int32_t qp_num = QP_NUM_FROM_HNDL(h_qp);\r
- u_int32_t qp_idx = 0;\r
- mlnx_mcast_t *mcast_p = NULL;\r
- mlnx_hobul_t *hobul_p;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- UNUSED_PARAM( mcast_lid );\r
-\r
- if (!p_mcast_gid || !ph_mcast) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
-\r
- if (NULL == (mcast_p = cl_zalloc( sizeof(mlnx_mcast_t)))) {\r
- status = IB_INSUFFICIENT_MEMORY;\r
- goto cleanup;\r
- }\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_CA_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_QP_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- qp_idx = qp_num & hobul_p->qp_idx_mask;\r
-\r
- VALIDATE_INDEX(qp_idx, hobul_p->max_qp, IB_INVALID_QP_HANDLE, cleanup);\r
- if ( E_MARK_QP != hobul_p->qp_info_tbl[qp_idx].mark ) {\r
- status = IB_INVALID_QP_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- memcpy(&mcast_p->mcast_gid, &p_mcast_gid->raw[0], sizeof(IB_gid_t));\r
- mcast_p->hca_idx = hca_idx;\r
- mcast_p->qp_num = qp_num;\r
- mcast_p->mark = E_MARK_MG;\r
-\r
- cl_mutex_acquire(&hobul_p->qp_info_tbl[qp_idx].mutex);\r
-\r
- if (HH_OK != THH_hob_attach_to_multicast( hobul_p->hh_hndl, qp_num, mcast_p->mcast_gid)) {\r
- status = IB_ERROR;\r
- goto cleanup_locked;\r
- }\r
-\r
- cl_mutex_release(&hobul_p->qp_info_tbl[qp_idx].mutex);\r
-\r
- *ph_mcast = (ib_mcast_handle_t)mcast_p;\r
-\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = IB_SUCCESS;\r
- }\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup_locked:\r
- cl_mutex_release(&hobul_p->qp_info_tbl[qp_idx].mutex);\r
-cleanup:\r
- if (mcast_p) cl_free( mcast_p);\r
-\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = status;\r
- }\r
-\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_detach_mcast (\r
- IN const ib_mcast_handle_t h_mcast)\r
-{\r
- ib_api_status_t status;\r
- mlnx_mcast_t *mcast_p = (mlnx_mcast_t *)h_mcast;\r
-\r
- u_int32_t hca_idx;\r
- u_int32_t qp_num;\r
- u_int32_t qp_idx = 0;\r
- mlnx_hobul_t *hobul_p;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- if (!mcast_p || mcast_p->mark != E_MARK_MG) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
- hca_idx = mcast_p->hca_idx;\r
- qp_num = mcast_p->qp_num;\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_CA_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_QP_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- qp_idx = qp_num & hobul_p->qp_idx_mask;\r
-\r
- VALIDATE_INDEX(qp_idx, hobul_p->max_qp, IB_INVALID_QP_HANDLE, cleanup);\r
- if ( E_MARK_QP != hobul_p->qp_info_tbl[qp_idx].mark ) {\r
- status = IB_INVALID_QP_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- cl_mutex_acquire(&hobul_p->qp_info_tbl[qp_idx].mutex);\r
-\r
- if (HH_OK != THH_hob_detach_from_multicast( hobul_p->hh_hndl, qp_num, mcast_p->mcast_gid)) {\r
- status = IB_ERROR;\r
- goto cleanup_locked;\r
- }\r
-\r
- cl_mutex_release(&hobul_p->qp_info_tbl[qp_idx].mutex);\r
-\r
- mcast_p->mark = E_MARK_INVALID;\r
- cl_free( mcast_p);\r
-\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup_locked:\r
- cl_mutex_release(&hobul_p->qp_info_tbl[qp_idx].mutex);\r
-cleanup:\r
- if (mcast_p) {\r
- mcast_p->mark = E_MARK_INVALID;\r
- cl_free( mcast_p);\r
- }\r
-\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-\r
-void\r
-mlnx_mcast_if(\r
- IN OUT ci_interface_t *p_interface )\r
-{\r
- p_interface->attach_mcast = mlnx_attach_mcast;\r
- p_interface->detach_mcast = mlnx_detach_mcast;\r
-}\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies, Inc. All rights reserved. \r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#include "hca_data.h"\r
-\r
-/*\r
- * Memory Management Verbs.\r
- */\r
-\r
-ib_api_status_t\r
-mlnx_register_mr (\r
- IN const ib_pd_handle_t h_pd,\r
- IN const ib_mr_create_t *p_mr_create,\r
- OUT net32_t* const p_lkey,\r
- OUT net32_t* const p_rkey,\r
- OUT ib_mr_handle_t *ph_mr,\r
- IN boolean_t um_call )\r
-{\r
- u_int32_t hca_idx = PD_HCA_FROM_HNDL(h_pd);\r
- u_int32_t pd_idx = PD_NUM_FROM_HNDL(h_pd);\r
- mlnx_hobul_t *hobul_p;\r
- ib_api_status_t status;\r
-\r
- HH_mr_t mr_props;\r
- mlnx_mro_t *mro_p = NULL;\r
- u_int32_t lkey=0, rkey=0;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- if( !cl_is_blockable() )\r
- return IB_UNSUPPORTED;\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_PD_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
- VALIDATE_INDEX(pd_idx, hobul_p->max_pd, IB_INVALID_PD_HANDLE, cleanup);\r
- if (E_MARK_PD != hobul_p->pd_info_tbl[pd_idx].mark) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- if (!p_mr_create || 0 == p_mr_create->length) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup; \r
- }\r
-\r
- if (NULL == (mro_p = cl_zalloc( sizeof(mlnx_mro_t)))) {\r
- status = IB_INSUFFICIENT_MEMORY;\r
- goto cleanup; \r
- }\r
-\r
- // Convert MR properties (LOCKS THE REGION as a side effect)\r
- cl_memclr(&mr_props, sizeof(HH_mr_t));\r
- status = mlnx_conv_ibal_mr_create(pd_idx, mro_p,\r
- VAPI_MR_CHANGE_TRANS | VAPI_MR_CHANGE_PD | VAPI_MR_CHANGE_ACL,\r
- p_mr_create, um_call, &mr_props);\r
- if (status != IB_SUCCESS ) {\r
- goto cleanup;\r
- }\r
-\r
- // Register MR\r
- if (HH_OK != THH_hob_register_mr(hobul_p->hh_hndl, &mr_props, &lkey, &rkey)) {\r
- status = IB_ERROR;\r
- goto cleanup_post_lock;\r
- }\r
-\r
- if (p_lkey) *p_lkey = lkey;\r
- if (p_rkey) *p_rkey = cl_hton32( rkey );\r
-\r
- // update PD object count\r
- cl_atomic_inc(&hobul_p->pd_info_tbl[pd_idx].count);\r
-\r
- mro_p->mark = E_MARK_MR;\r
- mro_p->mr_type = E_MR_ANY;\r
- mro_p->mr_pd_handle = PD_HNDL_FROM_PD(pd_idx);\r
- mro_p->mr_lkey = lkey;\r
- if (ph_mr) *ph_mr = (ib_mr_handle_t)mro_p;\r
-\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup_post_lock:\r
- MOSAL_iobuf_deregister(mro_p->mr_iobuf);\r
-\r
-cleanup:\r
- if (mro_p) {\r
- mro_p->mark = E_MARK_INVALID;\r
- cl_free( mro_p);\r
- }\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("file %s line %d\n", __FILE__, __LINE__));\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_register_pmr (\r
- IN const ib_pd_handle_t h_pd,\r
- IN const ib_phys_create_t* const p_pmr_create,\r
- IN OUT uint64_t* const p_vaddr,\r
- OUT net32_t* const p_lkey,\r
- OUT net32_t* const p_rkey,\r
- OUT ib_mr_handle_t* const ph_mr,\r
- IN boolean_t um_call )\r
-{\r
- u_int32_t hca_idx = PD_HCA_FROM_HNDL(h_pd);\r
- u_int32_t pd_idx = PD_NUM_FROM_HNDL(h_pd);\r
- mlnx_hobul_t *hobul_p;\r
- ib_api_status_t status;\r
-\r
- HH_mr_t mr_props = { 0 };\r
- mlnx_mro_t *mro_p = NULL;\r
- u_int32_t lkey, rkey;\r
-\r
- UNUSED_PARAM( um_call );\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- if( !cl_is_blockable() )\r
- return IB_UNSUPPORTED;\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_PD_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- VALIDATE_INDEX(pd_idx, hobul_p->max_pd, IB_INVALID_PD_HANDLE, cleanup);\r
- if (E_MARK_PD != hobul_p->pd_info_tbl[pd_idx].mark) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- if (!p_vaddr || !p_pmr_create ||\r
- 0 == p_pmr_create->length ) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup; \r
- }\r
-\r
- mro_p = cl_zalloc( sizeof(mlnx_mro_t));\r
- if ( !mro_p ) {\r
- status = IB_INSUFFICIENT_MEMORY;\r
- goto cleanup; \r
- }\r
-\r
- // Convert PMR properties\r
- mro_p->mr_start = *p_vaddr;\r
- cl_memclr(&mr_props, sizeof(HH_mr_t));\r
- status = mlnx_conv_ibal_pmr_create( pd_idx, mro_p, p_pmr_create,\r
- &mr_props );\r
- if (status != IB_SUCCESS ) {\r
- goto cleanup;\r
- }\r
-\r
- // Register MR\r
- if (HH_OK != THH_hob_register_mr( hobul_p->hh_hndl, &mr_props,\r
- &lkey, &rkey )) {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
- if (p_lkey) *p_lkey = lkey;\r
- if (p_rkey) *p_rkey = cl_hton32( rkey );\r
-\r
- if( mr_props.tpt.tpt.buf_lst.buf_sz_lst )\r
- cl_free( mr_props.tpt.tpt.buf_lst.buf_sz_lst );\r
-\r
- if( mr_props.tpt.tpt.buf_lst.phys_buf_lst )\r
- cl_free( mr_props.tpt.tpt.buf_lst.phys_buf_lst );\r
-\r
- // update PD object count\r
- cl_atomic_inc(&hobul_p->pd_info_tbl[pd_idx].count);\r
-\r
- mro_p->mark = E_MARK_MR;\r
- mro_p->mr_type = E_MR_PHYS;\r
- mro_p->mr_pd_handle = PD_HNDL_FROM_PD(pd_idx);\r
- mro_p->mr_lkey = lkey;\r
- if (ph_mr) *ph_mr = (ib_mr_handle_t)mro_p;\r
- *p_vaddr = mro_p->mr_start; // return the updated address\r
-\r
- CL_TRACE(MLNX_DBG_MEM, g_mlnx_dbg_lvl, ("file %s line %d\n", __FILE__, __LINE__));\r
- CL_TRACE(MLNX_DBG_MEM, g_mlnx_dbg_lvl, ("mro_p 0x%p mark %d\n", mro_p, (mro_p ? mro_p->mark : 0xBAD)));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- if( mr_props.tpt.tpt.buf_lst.buf_sz_lst )\r
- cl_free( mr_props.tpt.tpt.buf_lst.buf_sz_lst );\r
-\r
- if( mr_props.tpt.tpt.buf_lst.phys_buf_lst )\r
- cl_free( mr_props.tpt.tpt.buf_lst.phys_buf_lst );\r
-\r
- if (mro_p) {\r
- mro_p->mark = E_MARK_INVALID;\r
- cl_free( mro_p);\r
- }\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_query_mr (\r
- IN const ib_mr_handle_t h_mr,\r
- OUT ib_mr_attr_t *p_mr_query )\r
-{\r
- u_int32_t hca_idx;\r
- u_int32_t pd_idx;\r
- mlnx_hobul_t *hobul_p;\r
- ib_api_status_t status = IB_SUCCESS;\r
-\r
- HH_mr_info_t mr_info;\r
- mlnx_mro_t *mro_p = NULL;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- if( !cl_is_blockable() )\r
- return IB_UNSUPPORTED;\r
-\r
- mro_p = (mlnx_mro_t *)h_mr;\r
- if (!mro_p || mro_p->mark != E_MARK_MR) {\r
- status = IB_INVALID_MR_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- hca_idx = PD_HCA_FROM_HNDL(mro_p->mr_pd_handle);\r
- pd_idx = PD_NUM_FROM_HNDL(mro_p->mr_pd_handle);\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_MR_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
- VALIDATE_INDEX(pd_idx, hobul_p->max_pd, IB_INVALID_MR_HANDLE, cleanup);\r
- if (E_MARK_PD != hobul_p->pd_info_tbl[pd_idx].mark) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
- CL_TRACE(MLNX_DBG_MEM, g_mlnx_dbg_lvl, ("file %s line %d\n", __FILE__, __LINE__));\r
- CL_TRACE(MLNX_DBG_MEM, g_mlnx_dbg_lvl, ("mro_p 0x%p mark %d\n", mro_p, (mro_p ? mro_p->mark : 0xBAD)));\r
-\r
- if (HH_OK != THH_hob_query_mr(hobul_p->hh_hndl, mro_p->mr_lkey, &mr_info)) {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
-\r
- mlnx_conv_vapi_mr_attr((ib_pd_handle_t)PD_HNDL_FROM_PD(pd_idx), &mr_info, p_mr_query);\r
-\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_modify_mr (\r
- IN const ib_mr_handle_t h_mr,\r
- IN const ib_mr_mod_t mem_modify_req,\r
- IN const ib_mr_create_t *p_mr_create,\r
- OUT uint32_t *p_lkey,\r
- OUT uint32_t *p_rkey,\r
- IN const ib_pd_handle_t h_pd OPTIONAL,\r
- IN boolean_t um_call )\r
-{\r
- u_int32_t hca_idx;\r
- u_int32_t pd_idx, old_pd_idx;\r
- mlnx_hobul_t *hobul_p;\r
- ib_api_status_t status;\r
-\r
- VAPI_mr_change_t change_mask;\r
- HH_mr_t mr_props;\r
- mlnx_mro_t *mro_p = NULL;\r
- u_int32_t lkey, rkey;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- if( !cl_is_blockable() )\r
- return IB_UNSUPPORTED;\r
-\r
- mro_p = (mlnx_mro_t *)h_mr;\r
- if (!mro_p || mro_p->mark != E_MARK_MR) {\r
- status = IB_INVALID_MR_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- if ( !p_mr_create || 0 == p_mr_create->length ||\r
- !p_lkey || !p_rkey)\r
- {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
-\r
- if( (mem_modify_req & IB_MR_MOD_PD) && !h_pd )\r
- {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- hca_idx = PD_HCA_FROM_HNDL(mro_p->mr_pd_handle);\r
- if( (mem_modify_req & IB_MR_MOD_PD) && h_pd )\r
- pd_idx = PD_NUM_FROM_HNDL(h_pd);\r
- else\r
- pd_idx = PD_NUM_FROM_HNDL(mro_p->mr_pd_handle);\r
-\r
- old_pd_idx = PD_NUM_FROM_HNDL(mro_p->mr_pd_handle);\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_MR_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
- VALIDATE_INDEX(pd_idx, hobul_p->max_pd, IB_INVALID_MR_HANDLE, cleanup);\r
- if (E_MARK_PD != hobul_p->pd_info_tbl[pd_idx].mark) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- CL_TRACE(MLNX_DBG_MEM, g_mlnx_dbg_lvl, ("file %s line %d\n", __FILE__, __LINE__));\r
- CL_TRACE(MLNX_DBG_MEM, g_mlnx_dbg_lvl, ("mro_p 0x%p mark %d\n", mro_p, (mro_p ? mro_p->mark : 0xBAD)));\r
-\r
- // change_mask = mem_modify_req;\r
- change_mask = 0;\r
- if (mem_modify_req & IB_MR_MOD_ADDR) change_mask |= VAPI_MR_CHANGE_TRANS;\r
- if (mem_modify_req & IB_MR_MOD_PD) change_mask |= VAPI_MR_CHANGE_PD;\r
- if (mem_modify_req & IB_MR_MOD_ACCESS) change_mask |= VAPI_MR_CHANGE_ACL;\r
-\r
- cl_memclr(&mr_props, sizeof(HH_mr_t));\r
- status = mlnx_conv_ibal_mr_create(pd_idx, mro_p, change_mask, p_mr_create,\r
- um_call, &mr_props);\r
- if ( status != IB_SUCCESS ) {\r
- goto cleanup;\r
- }\r
-\r
- if (HH_OK != THH_hob_reregister_mr(hobul_p->hh_hndl,\r
- mro_p->mr_lkey,\r
- change_mask,\r
- &mr_props, \r
- &lkey, &rkey))\r
- {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
-\r
- // update PD object count\r
- if( (mem_modify_req & IB_MR_MOD_PD) && h_pd )\r
- {\r
- mro_p->mr_pd_handle = PD_HNDL_FROM_PD( pd_idx );\r
- cl_atomic_inc(&hobul_p->pd_info_tbl[pd_idx].count);\r
- cl_atomic_dec(&hobul_p->pd_info_tbl[old_pd_idx].count);\r
- }\r
-\r
- // Update our "shadow" (TBD: old memory region may need to be unlocked)\r
- mro_p->mr_lkey = lkey;\r
-\r
- // Return new keys to the caller\r
- if (p_lkey) *p_lkey = lkey;\r
- if (p_rkey) *p_rkey = rkey;\r
-\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_modify_pmr (\r
- IN const ib_mr_handle_t h_mr,\r
- IN const ib_mr_mod_t mem_modify_req,\r
- IN const ib_phys_create_t* const p_pmr_create,\r
- IN OUT uint64_t* const p_vaddr,\r
- OUT uint32_t* const p_lkey,\r
- OUT uint32_t* const p_rkey,\r
- IN const ib_pd_handle_t h_pd OPTIONAL,\r
- IN boolean_t um_call )\r
-{\r
- u_int32_t hca_idx;\r
- u_int32_t pd_idx;\r
- mlnx_hobul_t *hobul_p;\r
- ib_api_status_t status;\r
-\r
- VAPI_mr_change_t change_mask;\r
- HH_mr_t mr_props = { 0 };\r
- mlnx_mro_t *mro_p = NULL;\r
- u_int32_t lkey, rkey;\r
-\r
- UNUSED_PARAM( um_call );\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- if( !cl_is_blockable() )\r
- return IB_UNSUPPORTED;\r
-\r
- mro_p = (mlnx_mro_t *)h_mr;\r
- if (!mro_p || mro_p->mark != E_MARK_MR) {\r
- status = IB_INVALID_MR_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- if ( !p_pmr_create || 0 == p_pmr_create->length ||\r
- !p_lkey || !p_rkey)\r
- {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
-\r
- hca_idx = PD_HCA_FROM_HNDL(mro_p->mr_pd_handle);\r
- if( h_pd )\r
- pd_idx = PD_NUM_FROM_HNDL( h_pd );\r
- else\r
- pd_idx = PD_NUM_FROM_HNDL(mro_p->mr_pd_handle);\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_MR_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
- VALIDATE_INDEX(pd_idx, hobul_p->max_pd, IB_INVALID_MR_HANDLE, cleanup);\r
- if (E_MARK_PD != hobul_p->pd_info_tbl[pd_idx].mark) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- // change_mask = mem_modify_req;\r
- change_mask = 0;\r
- if (mem_modify_req & IB_MR_MOD_ADDR) change_mask |= VAPI_MR_CHANGE_TRANS;\r
- if (mem_modify_req & IB_MR_MOD_PD) change_mask |= VAPI_MR_CHANGE_PD;\r
- if (mem_modify_req & IB_MR_MOD_ACCESS) change_mask |= VAPI_MR_CHANGE_ACL;\r
-\r
- // Convert PMR properties\r
- mro_p->mr_start = *p_vaddr;\r
- cl_memclr(&mr_props, sizeof(HH_mr_t));\r
- if (IB_SUCCESS != (status = mlnx_conv_ibal_pmr_create(pd_idx, mro_p, p_pmr_create, &mr_props))) {\r
- goto cleanup;\r
- }\r
-\r
- if (HH_OK != THH_hob_reregister_mr(hobul_p->hh_hndl,\r
- mro_p->mr_lkey,\r
- change_mask,\r
- &mr_props, \r
- &lkey, &rkey))\r
- {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
-\r
- if( mr_props.tpt.tpt.buf_lst.buf_sz_lst )\r
- cl_free( mr_props.tpt.tpt.buf_lst.buf_sz_lst );\r
-\r
- if( mr_props.tpt.tpt.buf_lst.phys_buf_lst )\r
- cl_free( mr_props.tpt.tpt.buf_lst.phys_buf_lst );\r
-\r
- // Update our "shadow"\r
- mro_p->mr_lkey = lkey;\r
-\r
- // Return new keys to the caller\r
- if (p_lkey) *p_lkey = lkey;\r
- if (p_rkey) *p_rkey = rkey;\r
-\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- if( mr_props.tpt.tpt.buf_lst.buf_sz_lst )\r
- cl_free( mr_props.tpt.tpt.buf_lst.buf_sz_lst );\r
-\r
- if( mr_props.tpt.tpt.buf_lst.phys_buf_lst )\r
- cl_free( mr_props.tpt.tpt.buf_lst.phys_buf_lst );\r
-\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_register_smr (\r
- IN const ib_mr_handle_t h_mr,\r
- IN const ib_pd_handle_t h_pd,\r
- IN const ib_access_t access_ctrl,\r
- IN OUT uint64_t* const p_vaddr,\r
- OUT net32_t* const p_lkey,\r
- OUT net32_t* const p_rkey,\r
- OUT ib_mr_handle_t* const ph_mr,\r
- IN boolean_t um_call )\r
-{\r
- u_int32_t hca_idx = PD_HCA_FROM_HNDL(h_pd);\r
- u_int32_t pd_idx = PD_NUM_FROM_HNDL(h_pd);\r
- mlnx_hobul_t *hobul_p;\r
- ib_api_status_t status;\r
-\r
- HH_smr_t smr_props;\r
- mlnx_mro_t *base_mro_p = NULL;\r
- mlnx_mro_t *new_mro_p = NULL;\r
- u_int32_t lkey, rkey;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- if( !cl_is_blockable() )\r
- return IB_UNSUPPORTED;\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_PD_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
- VALIDATE_INDEX(pd_idx, hobul_p->max_pd, IB_INVALID_PD_HANDLE, cleanup);\r
- if (E_MARK_PD != hobul_p->pd_info_tbl[pd_idx].mark) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- if (!ph_mr || !p_vaddr || !p_lkey || !p_rkey ) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup; \r
- }\r
-\r
- base_mro_p = (mlnx_mro_t *)h_mr;\r
- if (!base_mro_p || base_mro_p->mark != E_MARK_MR) {\r
- status = IB_INVALID_MR_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- // Convert SMR properties\r
- smr_props.lkey = base_mro_p->mr_lkey; // L-Key of the region to share with\r
- // This region start virtual addr\r
- smr_props.start = *p_vaddr;\r
- // PD handle for new memory region\r
- smr_props.pd = PD_NUM_FROM_HNDL(base_mro_p->mr_pd_handle);\r
- smr_props.acl = map_ibal_acl(access_ctrl); // Access control (R/W permission local/remote\r
-\r
- // Allocate new handle for shared region\r
- if (NULL == (new_mro_p = cl_zalloc( sizeof(mlnx_mro_t)))) {\r
- status = IB_INSUFFICIENT_MEMORY;\r
- goto cleanup; \r
- }\r
-\r
- new_mro_p->mr_start = *p_vaddr;\r
- new_mro_p->mr_size = base_mro_p->mr_size;\r
-\r
- // This computation should be externalized by THH\r
- new_mro_p->mr_mosal_perm =\r
- MOSAL_PERM_READ |\r
- ((smr_props.acl & VAPI_EN_LOCAL_WRITE) ? MOSAL_PERM_WRITE : 0);\r
-\r
- if (IB_SUCCESS != (status = mlnx_lock_region(new_mro_p, um_call ))) {\r
- goto cleanup;\r
- }\r
-\r
- // Register MR\r
- if (HH_OK != THH_hob_register_smr(hobul_p->hh_hndl, &smr_props, &lkey, &rkey)) {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
-\r
- // Return modified values\r
- *p_vaddr = smr_props.start;\r
- *p_lkey = lkey;\r
- *p_rkey = cl_hton32( rkey );\r
-\r
- // update PD object count\r
- cl_atomic_inc(&hobul_p->pd_info_tbl[pd_idx].count);\r
-\r
- new_mro_p->mark = E_MARK_MR;\r
- new_mro_p->mr_type = E_MR_SHARED;\r
- new_mro_p->mr_pd_handle = PD_HNDL_FROM_PD(pd_idx);\r
- new_mro_p->mr_lkey = lkey;\r
-\r
- *ph_mr = (ib_mr_handle_t)new_mro_p;\r
-\r
-// CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("new_mro_p 0x%p page 0x%x, %d\n",\r
-// new_mro_p, new_mro_p->mr_first_page_addr, new_mro_p->mr_num_pages));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- if (new_mro_p) {\r
- new_mro_p->mark = E_MARK_INVALID;\r
- cl_free( new_mro_p);\r
- }\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_deregister_mr (\r
- IN const ib_mr_handle_t h_mr)\r
-{\r
- mlnx_mro_t *mro_p = NULL;\r
- u_int32_t hca_idx;\r
- u_int32_t pd_idx;\r
- mlnx_hobul_t *hobul_p;\r
- ib_api_status_t status;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- if( !cl_is_blockable() )\r
- return IB_UNSUPPORTED;\r
-\r
- mro_p = (mlnx_mro_t *)h_mr;\r
- if (!mro_p || mro_p->mark != E_MARK_MR) {\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("file %s line %d\n", __FILE__, __LINE__));\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("mro_p 0x%p mark %d\n", mro_p, (mro_p ? mro_p->mark : 0xBAD)));\r
- status = IB_INVALID_MR_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- hca_idx = PD_HCA_FROM_HNDL(mro_p->mr_pd_handle);\r
- pd_idx = PD_NUM_FROM_HNDL(mro_p->mr_pd_handle);\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_MR_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
- VALIDATE_INDEX(pd_idx, hobul_p->max_pd, IB_INVALID_MR_HANDLE, cleanup);\r
- if (E_MARK_PD != hobul_p->pd_info_tbl[pd_idx].mark) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- THH_hob_deregister_mr(hobul_p->hh_hndl, mro_p->mr_lkey);\r
-\r
- if (mro_p->mr_type != E_MR_PHYS) {\r
- MOSAL_iobuf_deregister(mro_p->mr_iobuf);\r
- }\r
-\r
- // update PD object count\r
- cl_atomic_dec(&hobul_p->pd_info_tbl[pd_idx].count);\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("pd %d count %d\n", pd_idx, hobul_p->pd_info_tbl[pd_idx].count));\r
-\r
- if (mro_p) {\r
- mro_p->mark = E_MARK_INVALID;\r
- cl_free( mro_p);\r
- }\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- if (mro_p) {\r
- mro_p->mark = E_MARK_INVALID;\r
- cl_free( mro_p);\r
- }\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-\r
-\r
-ib_api_status_t\r
-mlnx_alloc_fmr(\r
- IN const ib_pd_handle_t h_pd,\r
- IN const mlnx_fmr_create_t* const p_fmr_create,\r
- OUT mlnx_fmr_handle_t* const ph_fmr\r
- )\r
-{\r
- UNUSED_PARAM( h_pd );\r
- UNUSED_PARAM( p_fmr_create );\r
- UNUSED_PARAM( ph_fmr );\r
- return IB_UNSUPPORTED;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_map_phys_fmr (\r
- IN const mlnx_fmr_handle_t h_fmr,\r
- IN const uint64_t* const page_list,\r
- IN const int list_len,\r
- IN OUT uint64_t* const p_vaddr,\r
- OUT net32_t* const p_lkey,\r
- OUT net32_t* const p_rkey\r
- )\r
-{\r
- UNUSED_PARAM( h_fmr );\r
- UNUSED_PARAM( page_list );\r
- UNUSED_PARAM( list_len );\r
- UNUSED_PARAM( p_vaddr );\r
- UNUSED_PARAM( p_lkey );\r
- UNUSED_PARAM( p_rkey );\r
- return IB_UNSUPPORTED;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_unmap_fmr (\r
- IN const mlnx_fmr_handle_t *ph_fmr)\r
-{\r
- UNUSED_PARAM( ph_fmr );\r
- return IB_UNSUPPORTED;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_dealloc_fmr (\r
- IN const mlnx_fmr_handle_t h_fmr\r
- )\r
-{\r
- UNUSED_PARAM( h_fmr );\r
- return IB_UNSUPPORTED;\r
-}\r
-\r
-\r
-/*\r
-* Memory Window Verbs.\r
-*/\r
-\r
-ib_api_status_t\r
-mlnx_create_mw (\r
- IN const ib_pd_handle_t h_pd,\r
- OUT net32_t* const p_rkey,\r
- OUT ib_mw_handle_t *ph_mw,\r
- IN OUT ci_umv_buf_t *p_umv_buf )\r
-{\r
- u_int32_t hca_idx = PD_HCA_FROM_HNDL(h_pd);\r
- u_int32_t pd_idx = PD_NUM_FROM_HNDL(h_pd);\r
- mlnx_hobul_t *hobul_p;\r
- mlnx_mwo_t *mwo_p = NULL;\r
- ib_api_status_t status;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- if( !cl_is_blockable() )\r
- return IB_UNSUPPORTED;\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_PD_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
- VALIDATE_INDEX(pd_idx, hobul_p->max_pd, IB_INVALID_PD_HANDLE, cleanup);\r
- if (E_MARK_PD != hobul_p->pd_info_tbl[pd_idx].mark) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- if (!p_rkey || !ph_mw) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
-\r
- if (NULL == (mwo_p = cl_zalloc( sizeof(mlnx_mwo_t)))) {\r
- status = IB_INSUFFICIENT_MEMORY;\r
- goto cleanup; \r
- }\r
-\r
- if (HH_OK != THH_hob_alloc_mw(hobul_p->hh_hndl, pd_idx, (IB_rkey_t *)&mwo_p->mw_rkey))\r
- {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
-\r
- // update PD object count\r
- cl_atomic_inc(&hobul_p->pd_info_tbl[pd_idx].count);\r
-\r
- mwo_p->mark = E_MARK_MW;\r
- mwo_p->hca_idx = hca_idx;\r
- mwo_p->pd_idx = pd_idx;\r
- *p_rkey = cl_hton32( mwo_p->mw_rkey );\r
-\r
- *ph_mw = (ib_mw_handle_t)mwo_p;\r
-\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = IB_SUCCESS;\r
- }\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- if (mwo_p) {\r
- mwo_p->mark = E_MARK_INVALID;\r
- cl_free( mwo_p);\r
- }\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = status;\r
- }\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_query_mw (\r
- IN const ib_mw_handle_t h_mw,\r
- OUT ib_pd_handle_t *ph_pd,\r
- OUT net32_t* const p_rkey,\r
- IN OUT ci_umv_buf_t *p_umv_buf )\r
-{\r
- mlnx_mwo_t *mwo_p = NULL;\r
- u_int32_t hca_idx;\r
- u_int32_t pd_idx;\r
- mlnx_hobul_t *hobul_p;\r
- ib_api_status_t status;\r
-\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- if( !cl_is_blockable() )\r
- return IB_UNSUPPORTED;\r
-\r
- mwo_p = (mlnx_mwo_t *)h_mw;\r
- if (!mwo_p || mwo_p->mark != E_MARK_MW) {\r
- status = IB_INVALID_MW_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- hca_idx = mwo_p->hca_idx;\r
- pd_idx = mwo_p->pd_idx;\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_MW_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_MW_HANDLE;\r
- goto cleanup;\r
- }\r
- VALIDATE_INDEX(pd_idx, hobul_p->max_pd, IB_INVALID_MW_HANDLE, cleanup);\r
- if (E_MARK_PD != hobul_p->pd_info_tbl[pd_idx].mark) {\r
- status = IB_INVALID_MW_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- if (ph_pd) *ph_pd = (ib_pd_handle_t)PD_HNDL_FROM_PD(pd_idx);\r
- if (p_rkey) *p_rkey = cl_hton32( mwo_p->mw_rkey );\r
-\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = IB_SUCCESS;\r
- }\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = status;\r
- }\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_destroy_mw (\r
- IN const ib_mw_handle_t h_mw)\r
-{\r
- mlnx_mwo_t *mwo_p = NULL;\r
- u_int32_t hca_idx;\r
- u_int32_t pd_idx;\r
- mlnx_hobul_t *hobul_p;\r
- ib_api_status_t status;\r
-\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- if( !cl_is_blockable() )\r
- return IB_UNSUPPORTED;\r
-\r
- mwo_p = (mlnx_mwo_t *)h_mw;\r
- if (!mwo_p || mwo_p->mark != E_MARK_MW) {\r
- status = IB_INVALID_MW_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- hca_idx = mwo_p->hca_idx;\r
- pd_idx = mwo_p->pd_idx;\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_MW_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
- VALIDATE_INDEX(pd_idx, hobul_p->max_pd, IB_INVALID_MW_HANDLE, cleanup);\r
- if (E_MARK_PD != hobul_p->pd_info_tbl[pd_idx].mark) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- if (HH_OK != THH_hob_free_mw(hobul_p->hh_hndl, (IB_rkey_t)mwo_p->mw_rkey))\r
- {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
-\r
- // update PD object count\r
- cl_atomic_dec(&hobul_p->pd_info_tbl[pd_idx].count);\r
-\r
- if (mwo_p) {\r
- mwo_p->mark = E_MARK_INVALID;\r
- cl_free( mwo_p);\r
- }\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- if (mwo_p) {\r
- mwo_p->mark = E_MARK_INVALID;\r
- cl_free( mwo_p);\r
- }\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-\r
-void\r
-mlnx_memory_if(\r
- IN OUT ci_interface_t *p_interface )\r
-{\r
- p_interface->register_mr = mlnx_register_mr;\r
- p_interface->register_pmr = mlnx_register_pmr;\r
- p_interface->query_mr = mlnx_query_mr;\r
- p_interface->modify_mr = mlnx_modify_mr;\r
- p_interface->modify_pmr = mlnx_modify_pmr;\r
- p_interface->register_smr = mlnx_register_smr;\r
- p_interface->deregister_mr = mlnx_deregister_mr;\r
-\r
- p_interface->alloc_mlnx_fmr = mlnx_alloc_fmr;\r
- p_interface->map_phys_mlnx_fmr = mlnx_map_phys_fmr;\r
- p_interface->unmap_mlnx_fmr = mlnx_unmap_fmr;\r
- p_interface->dealloc_mlnx_fmr = mlnx_dealloc_fmr;\r
-\r
- p_interface->create_mw = mlnx_create_mw;\r
- p_interface->query_mw = mlnx_query_mw;\r
- p_interface->destroy_mw = mlnx_destroy_mw;\r
-}\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2006 Voltaire Corporation. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-/*\r
- * SMP handling of IB Access Layer VPD for Mellanox MT23108 HCA\r
- */\r
-\r
-\r
-#include "hca_data.h"\r
-#include "hca_debug.h"\r
-\r
-\r
-boolean_t\r
-mlnx_cachable_guid_info(\r
- IN const mlnx_cache_t* const p_cache,\r
- IN const ib_mad_t *p_mad_in,\r
- OUT ib_mad_t *p_mad_out )\r
-{\r
- uint32_t idx;\r
-\r
- /* Get the table selector from the attribute */\r
- idx = cl_ntoh32( p_mad_in->attr_mod );\r
-\r
- /*\r
- * TODO: Setup the response to fail the MAD instead of sending\r
- * it down to the HCA.\r
- */\r
- if( idx > 31 )\r
- return FALSE;\r
-\r
- if( !p_cache->guid_block[idx].valid )\r
- return FALSE;\r
-\r
- /*\r
- * If a SET, see if the set is identical to the cache,\r
- * in which case it's a no-op.\r
- */\r
- if( p_mad_in->method == IB_MAD_METHOD_SET )\r
- {\r
- if( cl_memcmp( ib_smp_get_payload_ptr( (ib_smp_t*)p_mad_in ),\r
- &p_cache->guid_block[idx].tbl, sizeof(ib_guid_info_t) ) )\r
- {\r
- /* The set is requesting a change. */\r
- return FALSE;\r
- }\r
- }\r
-\r
- /* Setup the response mad. */\r
- cl_memcpy( p_mad_out, p_mad_in, MAD_BLOCK_SIZE );\r
- p_mad_out->method = (IB_MAD_METHOD_RESP_MASK | IB_MAD_METHOD_GET);\r
- if( p_mad_out->mgmt_class == IB_MCLASS_SUBN_DIR )\r
- p_mad_out->status = IB_SMP_DIRECTION;\r
- else\r
- p_mad_out->status = 0;\r
-\r
- /* Copy the cached data. */\r
- cl_memcpy( ib_smp_get_payload_ptr( (ib_smp_t*)p_mad_out ),\r
- &p_cache->guid_block[idx].tbl, sizeof(ib_guid_info_t) );\r
-\r
- return TRUE;\r
-}\r
-\r
-\r
-boolean_t\r
-mlnx_cachable_pkey_table(\r
- IN const mlnx_cache_t* const p_cache,\r
- IN const ib_mad_t *p_mad_in,\r
- OUT ib_mad_t *p_mad_out )\r
-{\r
- uint16_t idx;\r
-\r
- /* Get the table selector from the attribute */\r
- idx = ((uint16_t)cl_ntoh32( p_mad_in->attr_mod ));\r
-\r
- /*\r
- * TODO: Setup the response to fail the MAD instead of sending\r
- * it down to the HCA.\r
- */\r
- if( idx > 2047 )\r
- return FALSE;\r
-\r
- if( !p_cache->pkey_tbl[idx].valid )\r
- return FALSE;\r
-\r
- /*\r
- * If a SET, see if the set is identical to the cache,\r
- * in which case it's a no-op.\r
- */\r
- if( p_mad_in->method == IB_MAD_METHOD_SET )\r
- {\r
- if( cl_memcmp( ib_smp_get_payload_ptr( (ib_smp_t*)p_mad_in ),\r
- &p_cache->pkey_tbl[idx].tbl, sizeof(ib_pkey_table_t) ) )\r
- {\r
- /* The set is requesting a change. */\r
- return FALSE;\r
- }\r
- }\r
-\r
- /* Setup the response mad. */\r
- cl_memcpy( p_mad_out, p_mad_in, MAD_BLOCK_SIZE );\r
- p_mad_out->method = (IB_MAD_METHOD_RESP_MASK | IB_MAD_METHOD_GET);\r
- if( p_mad_out->mgmt_class == IB_MCLASS_SUBN_DIR )\r
- p_mad_out->status = IB_SMP_DIRECTION;\r
- else\r
- p_mad_out->status = 0;\r
-\r
- /* Copy the cached data. */\r
- cl_memcpy( ib_smp_get_payload_ptr( (ib_smp_t*)p_mad_out ),\r
- &p_cache->pkey_tbl[idx].tbl, sizeof(ib_pkey_table_t) );\r
-\r
- return TRUE;\r
-}\r
-\r
-\r
-boolean_t\r
-mlnx_cachable_sl_vl_table(\r
- IN const mlnx_cache_t* const p_cache,\r
- IN const ib_mad_t *p_mad_in,\r
- OUT ib_mad_t *p_mad_out )\r
-{\r
- if( !p_cache->sl_vl.valid )\r
- return FALSE;\r
-\r
- /*\r
- * If a SET, see if the set is identical to the cache,\r
- * in which case it's a no-op.\r
- */\r
- if( p_mad_in->method == IB_MAD_METHOD_SET )\r
- {\r
- if( cl_memcmp( ib_smp_get_payload_ptr( (ib_smp_t*)p_mad_in ),\r
- &p_cache->sl_vl.tbl, sizeof(ib_slvl_table_t) ) )\r
- {\r
- /* The set is requesting a change. */\r
- return FALSE;\r
- }\r
- }\r
-\r
- /* Setup the response mad. */\r
- cl_memcpy( p_mad_out, p_mad_in, MAD_BLOCK_SIZE );\r
- p_mad_out->method = (IB_MAD_METHOD_RESP_MASK | IB_MAD_METHOD_GET);\r
- if( p_mad_out->mgmt_class == IB_MCLASS_SUBN_DIR )\r
- p_mad_out->status = IB_SMP_DIRECTION;\r
- else\r
- p_mad_out->status = 0;\r
-\r
- /* Copy the cached data. */\r
- cl_memcpy( ib_smp_get_payload_ptr( (ib_smp_t*)p_mad_out ),\r
- &p_cache->sl_vl.tbl, sizeof(ib_slvl_table_t) );\r
-\r
- return TRUE;\r
-}\r
-\r
-\r
-boolean_t\r
-mlnx_cachable_vl_arb_table(\r
- IN const mlnx_cache_t* const p_cache,\r
- IN const ib_mad_t *p_mad_in,\r
- OUT ib_mad_t *p_mad_out )\r
-{\r
- uint16_t idx;\r
-\r
- /* Get the table selector from the attribute */\r
- idx = ((uint16_t)(cl_ntoh32( p_mad_in->attr_mod ) >> 16)) - 1;\r
-\r
- /*\r
- * TODO: Setup the response to fail the MAD instead of sending\r
- * it down to the HCA.\r
- */\r
- if( idx > 3 )\r
- return FALSE;\r
-\r
- if( !p_cache->vl_arb[idx].valid )\r
- return FALSE;\r
-\r
- /*\r
- * If a SET, see if the set is identical to the cache,\r
- * in which case it's a no-op.\r
- */\r
- if( p_mad_in->method == IB_MAD_METHOD_SET )\r
- {\r
- if( cl_memcmp( ib_smp_get_payload_ptr( (ib_smp_t*)p_mad_in ),\r
- &p_cache->vl_arb[idx].tbl, sizeof(ib_vl_arb_table_t) ) )\r
- {\r
- /* The set is requesting a change. */\r
- return FALSE;\r
- }\r
- }\r
-\r
- /* Setup the response mad. */\r
- cl_memcpy( p_mad_out, p_mad_in, MAD_BLOCK_SIZE );\r
- p_mad_out->method = (IB_MAD_METHOD_RESP_MASK | IB_MAD_METHOD_GET);\r
- if( p_mad_out->mgmt_class == IB_MCLASS_SUBN_DIR )\r
- p_mad_out->status = IB_SMP_DIRECTION;\r
- else\r
- p_mad_out->status = 0;\r
-\r
- /* Copy the cached data. */\r
- cl_memcpy( ib_smp_get_payload_ptr( (ib_smp_t*)p_mad_out ),\r
- &p_cache->vl_arb[idx].tbl, sizeof(ib_vl_arb_table_t) );\r
-\r
- return TRUE;\r
-}\r
-\r
-\r
-boolean_t\r
-mlnx_cachable_port_info(\r
- IN const mlnx_cache_t* const p_cache,\r
- IN const uint8_t port_num,\r
- IN const ib_mad_t *p_mad_in,\r
- OUT ib_mad_t *p_mad_out )\r
-{\r
- ib_port_info_t *p_port_info;\r
-\r
- UNUSED_PARAM( p_mad_out );\r
-\r
- if( !p_cache->port_info.valid )\r
- return FALSE;\r
-\r
- if( p_mad_in->method == IB_MAD_METHOD_GET )\r
- return FALSE;\r
-\r
- /*\r
- * NOTE: Even though the input MAD is const, we modify it to change\r
- * some parameters to no-ops to compensate for problems in the HCA chip.\r
- */\r
- p_port_info =\r
- (ib_port_info_t*)ib_smp_get_payload_ptr( (ib_smp_t*)p_mad_in );\r
-\r
- /* We can only cache requests for the same port that the SMP came in on. */\r
- if( p_mad_in->attr_mod != 0 &&\r
- cl_ntoh32( p_mad_in->attr_mod ) != port_num )\r
- {\r
- return FALSE;\r
- }\r
-\r
- /*\r
- * to avoid unnecessary glitches in port state, we translate these\r
- * fields to NOP when there is no change. Note these fields cannot\r
- * change within the hardware without a Set going through here.\r
- */\r
- if( p_port_info->link_width_enabled ==\r
- p_cache->port_info.info.link_width_enabled )\r
- {\r
- p_port_info->link_width_enabled = 0;\r
- }\r
- if( (p_port_info->state_info2 & 0x0F) ==\r
- (p_cache->port_info.info.state_info2 & 0x0F) )\r
- {\r
- p_port_info->state_info2 &= 0xF0;\r
- }\r
- if( (p_port_info->link_speed & 0x0F) ==\r
- (p_cache->port_info.info.link_speed & 0x0F) )\r
- {\r
- p_port_info->link_speed &= 0xF0;\r
- }\r
- if( (p_port_info->vl_enforce & 0xF0) ==\r
- (p_cache->port_info.info.vl_enforce & 0xF0) )\r
- {\r
- p_port_info->vl_enforce &= 0x0F;\r
- }\r
-\r
- /*\r
- * We modified the input MAD to change things to no-ops, but\r
- * we can't actually fulfill the MAD with cached data.\r
- */\r
- return FALSE;\r
-}\r
-\r
-\r
-boolean_t\r
-mlnx_cachable_mad(\r
- IN const ib_ca_handle_t h_ca,\r
- IN const uint8_t port_num,\r
- IN const ib_mad_t *p_mad_in,\r
- OUT ib_mad_t *p_mad_out )\r
-{\r
- if( p_mad_in->mgmt_class!= IB_MCLASS_SUBN_DIR &&\r
- p_mad_in->mgmt_class != IB_MCLASS_SUBN_LID )\r
- {\r
- return FALSE;\r
- }\r
-\r
- switch( p_mad_in->attr_id )\r
- {\r
- case IB_MAD_ATTR_GUID_INFO:\r
- return mlnx_cachable_guid_info(\r
- &h_ca->cache[port_num-1], p_mad_in, p_mad_out );\r
-\r
- case IB_MAD_ATTR_P_KEY_TABLE:\r
- return mlnx_cachable_pkey_table(\r
- &h_ca->cache[port_num-1], p_mad_in, p_mad_out );\r
-\r
- case IB_MAD_ATTR_SLVL_TABLE:\r
- return mlnx_cachable_sl_vl_table(\r
- &h_ca->cache[port_num-1], p_mad_in, p_mad_out );\r
-\r
- case IB_MAD_ATTR_VL_ARBITRATION:\r
- return mlnx_cachable_vl_arb_table(\r
- &h_ca->cache[port_num-1], p_mad_in, p_mad_out );\r
-\r
- case IB_MAD_ATTR_PORT_INFO:\r
- return mlnx_cachable_port_info(\r
- &h_ca->cache[port_num-1], port_num, p_mad_in, p_mad_out );\r
-\r
- default:\r
- break;\r
- }\r
- return FALSE;\r
-}\r
-\r
-\r
-void\r
-mlnx_update_guid_info(\r
- IN mlnx_cache_t* const p_cache,\r
- IN const ib_mad_t* const p_mad_out )\r
-{\r
- uint32_t idx;\r
-\r
- /* Get the table selector from the attribute */\r
- idx = cl_ntoh32( p_mad_out->attr_mod );\r
-\r
- /*\r
- * We only get successful MADs here, so invalid settings\r
- * shouldn't happen.\r
- */\r
- CL_ASSERT( idx <= 31 );\r
-\r
- cl_memcpy( &p_cache->guid_block[idx].tbl,\r
- ib_smp_get_payload_ptr( (ib_smp_t*)p_mad_out ),\r
- sizeof(ib_guid_info_t) );\r
- p_cache->guid_block[idx].valid = TRUE;\r
-}\r
-\r
-\r
-void\r
-mlnx_update_pkey_table(\r
- IN mlnx_cache_t* const p_cache,\r
- IN const ib_mad_t* const p_mad_out )\r
-{\r
- uint16_t idx;\r
-\r
- /* Get the table selector from the attribute */\r
- idx = ((uint16_t)cl_ntoh32( p_mad_out->attr_mod ));\r
-\r
- ASSERT( idx <= 2047 );\r
-\r
- cl_memcpy( &p_cache->pkey_tbl[idx].tbl,\r
- ib_smp_get_payload_ptr( (ib_smp_t*)p_mad_out ),\r
- sizeof(ib_pkey_table_t) );\r
- p_cache->pkey_tbl[idx].valid = TRUE;\r
-}\r
-\r
-\r
-void\r
-mlnx_update_sl_vl_table(\r
- IN mlnx_cache_t* const p_cache,\r
- IN const ib_mad_t* const p_mad_out )\r
-{\r
- cl_memcpy( &p_cache->sl_vl.tbl,\r
- ib_smp_get_payload_ptr( (ib_smp_t*)p_mad_out ),\r
- sizeof(ib_slvl_table_t) );\r
- p_cache->sl_vl.valid = TRUE;\r
-}\r
-\r
-\r
-void\r
-mlnx_update_vl_arb_table(\r
- IN mlnx_cache_t* const p_cache,\r
- IN const ib_mad_t* const p_mad_out )\r
-{\r
- uint16_t idx;\r
-\r
- /* Get the table selector from the attribute */\r
- idx = ((uint16_t)(cl_ntoh32( p_mad_out->attr_mod ) >> 16)) - 1;\r
-\r
- CL_ASSERT( idx <= 3 );\r
-\r
- cl_memcpy( &p_cache->vl_arb[idx].tbl,\r
- ib_smp_get_payload_ptr( (ib_smp_t*)p_mad_out ),\r
- sizeof(ib_vl_arb_table_t) );\r
- p_cache->vl_arb[idx].valid = TRUE;\r
-}\r
-\r
-\r
-void\r
-mlnx_update_port_info(\r
- IN const mlnx_cache_t* const p_cache,\r
- IN const uint8_t port_num,\r
- IN const ib_mad_t* const p_mad_out )\r
-{\r
- UNUSED_PARAM( p_cache );\r
-\r
- /* We can only cache requests for the same port that the SMP came in on. */\r
- /* TODO: Add synchronization to support getting data from other ports. */\r
- if( p_mad_out->attr_mod != 0 &&\r
- cl_ntoh32( p_mad_out->attr_mod ) != port_num )\r
- {\r
- return;\r
- }\r
-\r
- /* TODO: Setup the capabilites mask properly. */\r
-}\r
-\r
-\r
-void\r
-mlnx_update_cache(\r
- IN const ib_ca_handle_t h_ca,\r
- IN const uint8_t port_num,\r
- IN const ib_mad_t *p_mad_out )\r
-{\r
- if( p_mad_out->mgmt_class != IB_MCLASS_SUBN_DIR &&\r
- p_mad_out->mgmt_class != IB_MCLASS_SUBN_LID )\r
- {\r
- return;\r
- }\r
-\r
- /* Any successful response updates the cache. */\r
- if( p_mad_out->status )\r
- return;\r
-\r
-\r
- switch( p_mad_out->attr_id )\r
- {\r
- case IB_MAD_ATTR_GUID_INFO:\r
- mlnx_update_guid_info(\r
- &h_ca->cache[port_num-1], p_mad_out );\r
- break;\r
-\r
- case IB_MAD_ATTR_P_KEY_TABLE:\r
- mlnx_update_pkey_table(\r
- &h_ca->cache[port_num-1], p_mad_out );\r
- break;\r
-\r
- case IB_MAD_ATTR_SLVL_TABLE:\r
- mlnx_update_sl_vl_table(\r
- &h_ca->cache[port_num-1], p_mad_out );\r
- break;\r
-\r
- case IB_MAD_ATTR_VL_ARBITRATION:\r
- mlnx_update_vl_arb_table(\r
- &h_ca->cache[port_num-1], p_mad_out );\r
- break;\r
-\r
- case IB_MAD_ATTR_PORT_INFO:\r
- mlnx_update_port_info(\r
- &h_ca->cache[port_num-1], port_num, p_mad_out );\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
-}\r
-\r
-\r
-/*\r
- * Local MAD Support Verbs. For CAs that do not support\r
- * agents in HW.\r
- */\r
-ib_api_status_t\r
-mlnx_local_mad (\r
- IN const ib_ca_handle_t h_ca,\r
- IN const uint8_t port_num,\r
- IN const ib_av_attr_t *p_av_src_attr,\r
- IN const ib_mad_t *p_mad_in,\r
- OUT ib_mad_t *p_mad_out )\r
-{\r
- ib_api_status_t status;\r
-\r
- mlnx_hob_t *hob_p = (mlnx_hob_t *)h_ca;\r
- u_int32_t hca_idx;\r
- mlnx_hobul_t *hobul_p;\r
- HH_hca_dev_t *hca_ul_info;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- UNUSED_PARAM(*p_av_src_attr);\r
-\r
- if (port_num > 2) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
-\r
- if (!hob_p || E_MARK_CA != hob_p->mark) {\r
- status = IB_INVALID_CA_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- hca_idx = hob_p->index;\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_CA_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- hca_ul_info = (HH_hca_dev_t *)hobul_p->hh_hndl;\r
- if (NULL == hca_ul_info) {\r
- status = IB_INVALID_CA_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- if( !mlnx_cachable_mad( h_ca, port_num, p_mad_in, p_mad_out ) )\r
- {\r
- if( HH_OK != THH_hob_process_local_mad( hobul_p->hh_hndl, port_num,\r
- 0x0, 0, (void *)p_mad_in, p_mad_out ) )\r
- {\r
- HCA_TRACE( HCA_DBG_ERROR,\r
- ("MAD failed:\n\tClass 0x%x\n\tMethod 0x%x\n\tAttr 0x%x",\r
- p_mad_in->mgmt_class, p_mad_in->method, p_mad_in->attr_id ) );\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
- if( (p_mad_in->mgmt_class == IB_MCLASS_SUBN_DIR ||\r
- p_mad_in->mgmt_class == IB_MCLASS_SUBN_LID) &&\r
- p_mad_in->attr_id == IB_MAD_ATTR_PORT_INFO )\r
- {\r
- ib_port_info_t *p_pi_in, *p_pi_out;\r
-\r
- if( p_mad_in->mgmt_class == IB_MCLASS_SUBN_DIR )\r
- {\r
- p_pi_in = (ib_port_info_t*)\r
- ib_smp_get_payload_ptr( (ib_smp_t*)p_mad_in );\r
- p_pi_out = (ib_port_info_t*)\r
- ib_smp_get_payload_ptr( (ib_smp_t*)p_mad_out );\r
- }\r
- else\r
- {\r
- p_pi_in = (ib_port_info_t*)(p_mad_in + 1);\r
- p_pi_out = (ib_port_info_t*)(p_mad_out + 1);\r
- }\r
-\r
- /* Work around FW bug 33958 */\r
- p_pi_out->subnet_timeout &= 0x7F;\r
- if( p_mad_in->method == IB_MAD_METHOD_SET )\r
- p_pi_out->subnet_timeout |= (p_pi_in->subnet_timeout & 0x80);\r
- }\r
-\r
- mlnx_update_cache( h_ca, port_num, p_mad_out );\r
- }\r
-\r
- /* Modify direction for Direct MAD */\r
- if ( p_mad_in->mgmt_class == IB_MCLASS_SUBN_DIR )\r
- p_mad_out->status |= IB_SMP_DIRECTION;\r
-\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies, Inc. All rights reserved. \r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#include "hca_data.h"\r
-#include "hca_debug.h"\r
-\r
-\r
-#define PTR_ALIGN(size) (((size) + sizeof(void*) - 1) & ~(sizeof(void*) - 1))\r
-\r
-\r
-/* Matches definition in IbAccess for MaxSMPsWatermark */\r
-uint32_t g_sqp_max_avs = ((4096/sizeof(ib_mad_t))*32*5);\r
-\r
-\r
-// Local declarations\r
-ib_api_status_t\r
-mlnx_query_qp (\r
- IN const ib_qp_handle_t h_qp,\r
- OUT ib_qp_attr_t *p_qp_attr,\r
- IN OUT ci_umv_buf_t *p_umv_buf );\r
-\r
-/* \r
-* CA Access Verbs\r
-*/\r
-ib_api_status_t\r
-mlnx_open_ca (\r
- IN const ib_net64_t ca_guid, // IN const char * ca_name,\r
- IN const ci_completion_cb_t pfn_completion_cb,\r
- IN const ci_async_event_cb_t pfn_async_event_cb,\r
- IN const void*const ca_context,\r
- OUT ib_ca_handle_t *ph_ca)\r
-{\r
-// char * ca_name = NULL;\r
-// char * dev_name = NULL;\r
- mlnx_hca_t *p_hca;\r
- HH_hca_dev_t * hca_ul_info;\r
- void * hca_ul_resources_p = NULL; // (THH_hca_ul_resources_t *)\r
- ib_api_status_t status;\r
- mlnx_hob_t *new_ca = NULL;\r
- MOSAL_protection_ctx_t prot_ctx;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("context 0x%p\n", ca_context));\r
-\r
- p_hca = mlnx_hca_from_guid( ca_guid );\r
- if( !p_hca ) {\r
- HCA_EXIT( MLNX_DBG_TRACE );\r
- return IB_NOT_FOUND;\r
- }\r
-\r
- //// Verify that the device has been discovered (it'd better be)\r
- //mlnx_names_from_guid(ca_guid, &ca_name, &dev_name);\r
- //if (!ca_name) {\r
- // CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- // return IB_NOT_FOUND;\r
- //}\r
-\r
- //// We have name - lookup device\r
- //if (HH_OK != HH_lookup_hca(ca_name, &hh_hndl)) {\r
- // CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- // return IB_NOT_FOUND;\r
- //}\r
-\r
- hca_ul_info = p_hca->hh_hndl;\r
-\r
- {\r
- // We are opening the HCA in kernel mode.\r
- // if a HOBKL exists for this device (i.e. it is open) - return E_BUSY\r
- if (IB_SUCCESS == mlnx_hobs_lookup(p_hca->hh_hndl, &new_ca)) {\r
- if (ph_ca) *ph_ca = (ib_ca_handle_t)new_ca;\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_RESOURCE_BUSY;\r
- }\r
-\r
- // Create a mapping from hca index to hh_hndl\r
- status = mlnx_hobs_insert(p_hca, &new_ca);\r
- if (IB_SUCCESS != status) {\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
- }\r
-\r
- /* save copy of HCA device object */\r
- new_ca->p_dev_obj = p_hca->p_dev_obj;\r
-\r
- // Initialize the device driver\r
- if (HH_OK != THH_hob_open_hca(p_hca->hh_hndl, NULL, NULL)) {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
- \r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("context 0x%p\n", ca_context));\r
- status = mlnx_hobs_set_cb(new_ca,\r
- pfn_completion_cb,\r
- pfn_async_event_cb,\r
- ca_context);\r
- if (IB_SUCCESS != status) {\r
- goto cleanup;\r
- }\r
-\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("ul_resource sizes: hca %d pd %d\n",\r
- hca_ul_info->hca_ul_resources_sz,\r
- hca_ul_info->pd_ul_resources_sz));\r
-\r
- hca_ul_resources_p = cl_zalloc( hca_ul_info->hca_ul_resources_sz);\r
-\r
- /* get the kernel protection context */ \r
- prot_ctx = MOSAL_get_kernel_prot_ctx();\r
- }\r
-\r
- if (!hca_ul_resources_p) {\r
- status = IB_INSUFFICIENT_MEMORY;\r
- goto cleanup;\r
- }\r
-\r
- if (HH_OK != THH_hob_alloc_ul_res(p_hca->hh_hndl, prot_ctx, hca_ul_resources_p)) {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
-\r
- // TBD: !!! in user mode (kernel hobul_idx != hob_idx)\r
- status = mlnx_hobul_new(new_ca, p_hca->hh_hndl, hca_ul_resources_p);\r
- if (IB_SUCCESS != status) {\r
- goto cleanup;\r
- }\r
-\r
- // Return the HOBUL index\r
- if (ph_ca) *ph_ca = new_ca;\r
-\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- if (hca_ul_resources_p)\r
- cl_free( hca_ul_resources_p);\r
- THH_hob_close_hca(p_hca->hh_hndl);\r
- mlnx_hobs_remove(new_ca);\r
-\r
- // For user mode call - return status to user mode\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_query_ca (\r
- IN const ib_ca_handle_t h_ca,\r
- OUT ib_ca_attr_t *p_ca_attr,\r
- IN OUT uint32_t *p_byte_count,\r
- IN OUT ci_umv_buf_t *p_umv_buf )\r
-{\r
- ib_api_status_t status;\r
-\r
- mlnx_hob_t *hob_p = (mlnx_hob_t *)h_ca;\r
- HH_hca_hndl_t hh_hndl = NULL;\r
- HH_hca_dev_t *hca_ul_info;\r
- VAPI_hca_cap_t hca_cap;\r
- VAPI_hca_port_t *hca_ports = NULL;\r
- uint32_t size, required_size;\r
- u_int8_t port_num, num_ports;\r
- u_int32_t num_gids, num_pkeys;\r
- u_int32_t num_page_sizes = 1; // TBD: what is actually supported\r
- uint8_t *last_p;\r
- void *hca_ul_resources_p = NULL;\r
- u_int32_t priv_op;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- if (NULL == p_byte_count) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
-\r
- mlnx_hobs_get_handle(hob_p, &hh_hndl);\r
- if (NULL == hh_hndl) {\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("returning E_NODEV dev\n"));\r
- status = IB_INVALID_CA_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- hca_ul_info = (HH_hca_dev_t *)hh_hndl;\r
-\r
- if (HH_OK != THH_hob_query(hh_hndl, &hca_cap)) {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
-\r
- num_ports = hca_cap.phys_port_num; /* Number of physical ports of the HCA */ \r
-\r
- if (NULL == (hca_ports = cl_zalloc( num_ports * sizeof(VAPI_hca_port_t)))) {\r
- CL_TRACE (CL_DBG_ERROR, g_mlnx_dbg_lvl,\r
- ("Failed to cl_zalloc ports array\n"));\r
- status = IB_INSUFFICIENT_MEMORY;\r
- goto cleanup;\r
- }\r
-\r
- // Loop on ports and get their properties\r
- num_gids = 0;\r
- num_pkeys = 0;\r
- required_size = PTR_ALIGN(sizeof(ib_ca_attr_t)) +\r
- PTR_ALIGN(sizeof(u_int32_t) * num_page_sizes) +\r
- PTR_ALIGN(sizeof(ib_port_attr_t) * num_ports);\r
- for (port_num = 0; port_num < num_ports; port_num++) {\r
- if (HH_OK != THH_hob_query_port_prop(hh_hndl, port_num+1, &hca_ports[port_num])) {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
-\r
- num_gids = hca_ports[port_num].gid_tbl_len;\r
- size = PTR_ALIGN(sizeof(ib_gid_t) * num_gids);\r
- required_size += size;\r
-\r
- num_pkeys = hca_ports[port_num].pkey_tbl_len;\r
- size = PTR_ALIGN(sizeof(u_int16_t) * num_pkeys);\r
- required_size += size;\r
- }\r
-\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- /*\r
- * Prepare the buffer with the size including hca_ul_resources_sz\r
- * NO ALIGNMENT for this size \r
- */\r
-\r
- if (p_umv_buf->p_inout_buf)\r
- {\r
- cl_memcpy (&priv_op, p_umv_buf->p_inout_buf, sizeof (priv_op));\r
- CL_TRACE(MLNX_DBG_TRACE, g_mlnx_dbg_lvl, ("priv_op = %d\n", priv_op));\r
-\r
- /* \r
- * Yes, UVP request for hca_ul_info\r
- */\r
- if (p_umv_buf->input_size != \r
- (sizeof (HH_hca_dev_t) + sizeof (priv_op) ))\r
- {\r
- *p_byte_count = required_size;\r
- p_umv_buf->output_size = 0;\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
- cl_memcpy( (uint8_t* __ptr64)p_umv_buf->p_inout_buf + sizeof (priv_op), \r
- hca_ul_info, sizeof (HH_hca_dev_t));\r
- p_umv_buf->output_size = p_umv_buf->input_size;\r
- }\r
- }\r
-\r
- if (NULL == p_ca_attr || *p_byte_count < required_size) {\r
- *p_byte_count = required_size;\r
- status = IB_INSUFFICIENT_MEMORY;\r
- if ( p_ca_attr != NULL) {\r
- CL_TRACE (CL_DBG_ERROR, g_mlnx_dbg_lvl,\r
- ("Failed *p_byte_count < required_size\n"));\r
- }\r
- goto cleanup;\r
- }\r
-\r
- // Space is sufficient - setup table pointers\r
- last_p = (uint8_t*)p_ca_attr;\r
- last_p += PTR_ALIGN(sizeof(*p_ca_attr));\r
-\r
- p_ca_attr->p_page_size = (uint32_t*)last_p;\r
- last_p += PTR_ALIGN(num_page_sizes * sizeof(u_int32_t));\r
-\r
- p_ca_attr->p_port_attr = (ib_port_attr_t *)last_p;\r
- last_p += PTR_ALIGN(num_ports * sizeof(ib_port_attr_t));\r
-\r
- for (port_num = 0; port_num < num_ports; port_num++) {\r
- p_ca_attr->p_port_attr[port_num].p_gid_table = (ib_gid_t *)last_p;\r
- size = PTR_ALIGN(sizeof(ib_gid_t) * hca_ports[port_num].gid_tbl_len);\r
- last_p += size;\r
-\r
- p_ca_attr->p_port_attr[port_num].p_pkey_table = (u_int16_t *)last_p;\r
- size = PTR_ALIGN(sizeof(u_int16_t) * hca_ports[port_num].pkey_tbl_len);\r
- last_p += size;\r
- }\r
-\r
- // Separate the loops to ensure that table pointers are always setup\r
- for (port_num = 0; port_num < num_ports; port_num++) {\r
- status = mlnx_get_hca_pkey_tbl(hh_hndl, port_num+1,\r
- hca_ports[port_num].pkey_tbl_len,\r
- p_ca_attr->p_port_attr[port_num].p_pkey_table);\r
- if (IB_SUCCESS != status) {\r
- CL_TRACE (CL_DBG_ERROR, g_mlnx_dbg_lvl,\r
- ("Failed to mlnx_get_hca_pkey_tbl for port_num:%d\n",port_num));\r
- goto cleanup;\r
- }\r
-\r
- status = mlnx_get_hca_gid_tbl(hh_hndl, port_num+1,\r
- hca_ports[port_num].gid_tbl_len,\r
- &p_ca_attr->p_port_attr[port_num].p_gid_table[0].raw);\r
- if (IB_SUCCESS != status) {\r
- CL_TRACE (CL_DBG_ERROR, g_mlnx_dbg_lvl,\r
- ("Failed to mlnx_get_hca_gid_tbl for port_num:%d\n",port_num));\r
- goto cleanup;\r
- }\r
-\r
-#if 0\r
- {\r
- int i;\r
-\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("port %d gid0:", port_num));\r
- for (i = 0; i < 16; i++)\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, (" 0x%x", p_ca_attr->p_port_attr[port_num].p_gid_table[0].raw[i]));\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("\n"));\r
- }\r
-#endif\r
- }\r
-\r
- // Convert query result into IBAL structure (no cl_memset())\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- // p_ca_attr->size = required_size - hca_ul_info->hca_ul_resources_sz;\r
- p_ca_attr->size = required_size;\r
- }\r
- else\r
- {\r
- p_ca_attr->size = required_size;\r
- }\r
-\r
- // !!! GID/PKEY tables must be queried before this call !!!\r
- mlnx_conv_vapi_hca_cap(hca_ul_info, &hca_cap, hca_ports, p_ca_attr);\r
-\r
- // verify: required space == used space\r
- CL_ASSERT( required_size == (((uintn_t)last_p) - ((uintn_t)p_ca_attr)) );\r
-\r
-#if 0\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("Space required %d used %d\n",\r
- required_size,\r
- ((uintn_t)last_p) - ((uintn_t)p_ca_attr))));\r
-#endif\r
-\r
- if( p_umv_buf && p_umv_buf->command ) p_umv_buf->status = IB_SUCCESS;\r
- if (hca_ul_resources_p) cl_free (hca_ul_resources_p);\r
- if (hca_ports) cl_free( hca_ports );\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- if( p_umv_buf && p_umv_buf->command ) p_umv_buf->status = status;\r
- if (hca_ul_resources_p) cl_free (hca_ul_resources_p);\r
- if (hca_ports) cl_free( hca_ports);\r
- if( p_ca_attr != NULL || status != IB_INSUFFICIENT_MEMORY )\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_modify_ca (\r
- IN const ib_ca_handle_t h_ca,\r
- IN const uint8_t port_num,\r
- IN const ib_ca_mod_t modca_cmd,\r
- IN const ib_port_attr_mod_t *p_port_attr)\r
-{\r
- ib_api_status_t status;\r
-\r
- mlnx_hob_t *hob_p = (mlnx_hob_t *)h_ca;\r
- HH_hca_hndl_t hh_hndl = NULL;\r
-\r
- VAPI_hca_attr_t hca_attr;\r
- VAPI_hca_attr_mask_t hca_attr_mask = 0;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- mlnx_hobs_get_handle(hob_p, &hh_hndl);\r
- if (NULL == hh_hndl) {\r
- status = IB_INVALID_CA_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- cl_memclr(&hca_attr, sizeof(hca_attr));\r
- if (modca_cmd & IB_CA_MOD_IS_SM) {\r
- hca_attr_mask |= HCA_ATTR_IS_SM;\r
- hca_attr.is_sm = (MT_bool)p_port_attr->cap.sm;\r
- }\r
- if (modca_cmd & IB_CA_MOD_IS_SNMP_SUPPORTED) {\r
- hca_attr_mask |= HCA_ATTR_IS_SNMP_TUN_SUP;\r
- hca_attr.is_snmp_tun_sup = (MT_bool)p_port_attr->cap.snmp;\r
- }\r
- if (modca_cmd & IB_CA_MOD_IS_DEV_MGMT_SUPPORTED) {\r
- hca_attr_mask |= HCA_ATTR_IS_DEV_MGT_SUP;\r
- hca_attr.is_dev_mgt_sup = (MT_bool)p_port_attr->cap.dev_mgmt;\r
- }\r
- if (modca_cmd & IB_CA_MOD_IS_VEND_SUPPORTED) {\r
- hca_attr_mask |= HCA_ATTR_IS_VENDOR_CLS_SUP;\r
- hca_attr.is_vendor_cls_sup = (MT_bool)p_port_attr->cap.vend;\r
- }\r
- if (modca_cmd & IB_CA_MOD_IS_CLIENT_REREGISTER_SUPPORTED) {\r
- hca_attr_mask |= HCA_ATTR_IS_CLIENT_REREGISTRATION_SUP;\r
- hca_attr.is_client_reregister_sup= (MT_bool)p_port_attr->cap.client_reregister;\r
- }\r
- if (modca_cmd & IB_CA_MOD_QKEY_CTR) {\r
- if (p_port_attr->qkey_ctr == 0)\r
- hca_attr.reset_qkey_counter = TRUE;\r
- }\r
-\r
- if (0 != hca_attr_mask) {\r
- if (HH_OK != THH_hob_modify( hh_hndl, port_num, &hca_attr, &hca_attr_mask))\r
- {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
- }\r
-\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_close_ca (\r
- IN ib_ca_handle_t h_ca)\r
-{\r
- ib_api_status_t status;\r
-\r
- HH_hca_hndl_t hh_hndl = NULL;\r
- mlnx_hob_t *hob_p = (mlnx_hob_t *)h_ca;\r
- HH_hca_dev_t *hca_ul_info;\r
- void *hca_ul_resources_p = NULL;\r
- mlnx_hobul_t *hobul_p;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- hobul_p = mlnx_hobul_array[hob_p->index];\r
- if( !hobul_p ) {\r
- status = IB_INVALID_CA_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- if( hobul_p->count ) {\r
- status = IB_RESOURCE_BUSY;\r
- goto cleanup;\r
- }\r
-\r
- mlnx_hobs_get_handle(hob_p, &hh_hndl);\r
- if (NULL == hh_hndl) {\r
- status = IB_INVALID_CA_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- hca_ul_info = (HH_hca_dev_t *)hh_hndl;\r
- mlnx_hobul_get(hob_p, &hca_ul_resources_p);\r
-\r
- if (hca_ul_resources_p) {\r
- THH_hob_free_ul_res(hh_hndl, hca_ul_resources_p);\r
- cl_free( hca_ul_resources_p);\r
- }\r
- mlnx_hobul_delete(hob_p);\r
- THH_hob_close_hca(hh_hndl);\r
- mlnx_hobs_remove(hob_p);\r
-\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-\r
-static ib_api_status_t\r
-mlnx_um_open(\r
- IN const ib_ca_handle_t h_ca,\r
- IN OUT ci_umv_buf_t* const p_umv_buf,\r
- OUT ib_ca_handle_t* const ph_um_ca )\r
-{\r
- ib_api_status_t status;\r
-\r
- mlnx_hob_t *hob_p = (mlnx_hob_t *)h_ca;\r
- HH_hca_hndl_t hh_hndl = NULL;\r
- HH_hca_dev_t *hca_ul_info;\r
- mlnx_um_ca_t *p_um_ca;\r
- MOSAL_protection_ctx_t prot_ctx;\r
-\r
- HCA_ENTER( MLNX_DBG_TRACE );\r
-\r
- mlnx_hobs_get_handle( hob_p, &hh_hndl );\r
- if( !hh_hndl )\r
- {\r
- HCA_TRACE(MLNX_DBG_INFO, ("returning E_NODEV dev\n"));\r
- status = IB_INVALID_CA_HANDLE;\r
- goto mlnx_um_open_err1;\r
- }\r
-\r
- hca_ul_info = (HH_hca_dev_t *)hh_hndl;\r
-\r
- if( !p_umv_buf->command )\r
- {\r
- p_um_ca = (mlnx_um_ca_t*)cl_zalloc( sizeof(mlnx_um_ca_t) );\r
- if( !p_um_ca )\r
- {\r
- p_umv_buf->status = IB_INSUFFICIENT_MEMORY;\r
- goto mlnx_um_open_err1;\r
- }\r
- /* Copy the dev info. */\r
- p_um_ca->dev_info = *hca_ul_info;\r
- p_um_ca->hob_p = hob_p;\r
- *ph_um_ca = (ib_ca_handle_t)p_um_ca;\r
- p_umv_buf->status = IB_SUCCESS;\r
- p_umv_buf->output_size = 0;\r
- HCA_EXIT( MLNX_DBG_TRACE );\r
- return IB_SUCCESS;\r
- }\r
-\r
- /*\r
- * Prepare the buffer with the size including hca_ul_resources_sz\r
- * NO ALIGNMENT for this size \r
- */\r
- if( !p_umv_buf->p_inout_buf ||\r
- p_umv_buf->output_size < sizeof(void*) )\r
- {\r
- p_umv_buf->status = IB_INVALID_PARAMETER;\r
- goto mlnx_um_open_err1;\r
- }\r
-\r
- HCA_TRACE( MLNX_DBG_TRACE, ("priv_op = %d\n", p_umv_buf->command ));\r
-\r
- /* Yes, UVP request for hca_ul_info. */\r
- p_um_ca = (mlnx_um_ca_t*)cl_zalloc(\r
- sizeof(mlnx_um_ca_t) + hca_ul_info->hca_ul_resources_sz - 1 );\r
- if( !p_um_ca )\r
- {\r
- p_umv_buf->status = IB_INSUFFICIENT_MEMORY;\r
- goto mlnx_um_open_err1;\r
- }\r
-\r
- p_um_ca->p_mdl = IoAllocateMdl( &p_um_ca->dev_info,\r
- (ULONG)(sizeof(HH_hca_dev_t) + hca_ul_info->hca_ul_resources_sz),\r
- FALSE, TRUE, NULL );\r
- if( !p_um_ca->p_mdl )\r
- {\r
- p_umv_buf->status = IB_ERROR;\r
- goto mlnx_um_open_err2;\r
- }\r
- /* Build the page list... */\r
- MmBuildMdlForNonPagedPool( p_um_ca->p_mdl );\r
-\r
- /* Map the memory into the calling process's address space. */\r
- __try\r
- {\r
- p_um_ca->p_mapped_addr =\r
- MmMapLockedPagesSpecifyCache( p_um_ca->p_mdl,\r
- UserMode, MmCached, NULL, FALSE, NormalPagePriority );\r
- }\r
- __except(EXCEPTION_EXECUTE_HANDLER)\r
- {\r
- p_umv_buf->status = IB_ERROR;\r
- goto mlnx_um_open_err3;\r
- }\r
-\r
- /* Register with THH (attach to the HCA). */\r
- prot_ctx = MOSAL_get_current_prot_ctx();\r
- if( THH_hob_alloc_ul_res(hh_hndl, prot_ctx, p_um_ca->ul_hca_res) != HH_OK )\r
- {\r
- HCA_TRACE( CL_DBG_ERROR, ("Failed to get ul_res\n"));\r
- p_umv_buf->status = IB_ERROR;\r
- }\r
-\r
- if( p_umv_buf->status == IB_SUCCESS )\r
- {\r
- /* Copy the dev info. */\r
- p_um_ca->dev_info = *hca_ul_info;\r
- p_um_ca->hob_p = hob_p;\r
- *ph_um_ca = (ib_ca_handle_t)p_um_ca;\r
- (*(void** __ptr64)p_umv_buf->p_inout_buf) = p_um_ca->p_mapped_addr;\r
- p_umv_buf->status = IB_SUCCESS;\r
- }\r
- else\r
- {\r
- MmUnmapLockedPages( p_um_ca->p_mapped_addr, p_um_ca->p_mdl );\r
-mlnx_um_open_err3:\r
- IoFreeMdl( p_um_ca->p_mdl );\r
-mlnx_um_open_err2:\r
- cl_free( p_um_ca );\r
-mlnx_um_open_err1:\r
- *ph_um_ca = NULL;\r
- }\r
-\r
- //*ph_um_ca = NULL;\r
- p_umv_buf->output_size = sizeof(void*);\r
- HCA_EXIT( MLNX_DBG_TRACE );\r
- return p_umv_buf->status;\r
-}\r
-\r
-\r
-static void\r
-mlnx_um_close(\r
- IN ib_ca_handle_t h_ca,\r
- IN ib_ca_handle_t h_um_ca )\r
-{\r
- mlnx_hob_t *hob_p = (mlnx_hob_t *)h_ca;\r
- HH_hca_hndl_t hh_hndl = NULL;\r
- mlnx_um_ca_t *p_um_ca = (mlnx_um_ca_t*)h_um_ca;\r
-\r
- HCA_ENTER( MLNX_DBG_TRACE );\r
-\r
- mlnx_hobs_get_handle( hob_p, &hh_hndl );\r
- if( !hh_hndl )\r
- goto mlnx_um_close_cleanup;\r
-\r
- if( !p_um_ca )\r
- return;\r
-\r
- if( !p_um_ca->p_mapped_addr )\r
- goto done;\r
-\r
- THH_hob_free_ul_res( hh_hndl, p_um_ca->ul_hca_res );\r
-\r
-mlnx_um_close_cleanup:\r
- MmUnmapLockedPages( p_um_ca->p_mapped_addr, p_um_ca->p_mdl );\r
- IoFreeMdl( p_um_ca->p_mdl );\r
-done:\r
- cl_free( p_um_ca );\r
-\r
- HCA_EXIT( MLNX_DBG_TRACE );\r
-}\r
-\r
-\r
-/*\r
-* Protection Domain and Reliable Datagram Domain Verbs\r
-*/\r
-\r
-ib_api_status_t\r
-mlnx_allocate_pd (\r
- IN const ib_ca_handle_t h_ca,\r
- IN const ib_pd_type_t type,\r
- OUT ib_pd_handle_t *ph_pd,\r
- IN OUT ci_umv_buf_t *p_umv_buf )\r
-{\r
- mlnx_hob_t *hob_p;\r
- mlnx_hobul_t *hobul_p;\r
- HH_hca_dev_t *hca_ul_info;\r
- HHUL_pd_hndl_t hhul_pd_hndl = 0;\r
- void *pd_ul_resources_p = NULL;\r
- u_int32_t pd_idx;\r
- ib_api_status_t status;\r
- MOSAL_protection_ctx_t prot_ctx;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- if( p_umv_buf )\r
- hob_p = ((mlnx_um_ca_t *)h_ca)->hob_p;\r
- else\r
- hob_p = (mlnx_hob_t *)h_ca;\r
- \r
- hobul_p = mlnx_hobs_get_hobul(hob_p);\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_CA_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- hca_ul_info = (HH_hca_dev_t *)hobul_p->hh_hndl;\r
- if (NULL == hca_ul_info) {\r
- status = IB_INVALID_CA_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- // For user mode calls - obtain and verify the vendor information\r
- if ((p_umv_buf->input_size - sizeof (u_int32_t)) != \r
- hca_ul_info->pd_ul_resources_sz ||\r
- NULL == p_umv_buf->p_inout_buf) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
- pd_ul_resources_p = (void *)p_umv_buf->p_inout_buf;\r
-\r
- /* get the current protection context */ \r
- prot_ctx = MOSAL_get_current_prot_ctx();\r
- }\r
- else\r
- {\r
- // for kernel mode calls - allocate app resources. Use prep->call->done sequence\r
- pd_ul_resources_p = cl_zalloc( hca_ul_info->pd_ul_resources_sz);\r
- if (NULL == pd_ul_resources_p) {\r
- status = IB_INSUFFICIENT_MEMORY;\r
- goto cleanup;\r
- }\r
-\r
- switch( type )\r
- {\r
- case IB_PDT_SQP:\r
- if (HH_OK != THHUL_pdm_alloc_pd_avs_prep(hobul_p->hhul_hndl,\r
- g_sqp_max_avs, PD_FOR_SQP, &hhul_pd_hndl, pd_ul_resources_p))\r
- {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
- break;\r
-\r
- case IB_PDT_UD:\r
- if (HH_OK != THHUL_pdm_alloc_pd_avs_prep(hobul_p->hhul_hndl,\r
- g_sqp_max_avs, PD_NO_FLAGS, &hhul_pd_hndl, pd_ul_resources_p))\r
- {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
- break;\r
-\r
- default:\r
- if (HH_OK != THHUL_pdm_alloc_pd_prep(hobul_p->hhul_hndl, &hhul_pd_hndl, pd_ul_resources_p)) {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
- }\r
- /* get the current protection context */ \r
- prot_ctx = MOSAL_get_kernel_prot_ctx();\r
- }\r
-\r
- // Allocate the PD (cmdif)\r
- if (HH_OK != THH_hob_alloc_pd(hobul_p->hh_hndl, prot_ctx, pd_ul_resources_p, &pd_idx)) {\r
- status = IB_INSUFFICIENT_RESOURCES;\r
- goto cleanup_pd;\r
- }\r
-\r
- if( !(p_umv_buf && p_umv_buf->command) )\r
- {\r
- // Manage user level resources\r
- if (HH_OK != THHUL_pdm_alloc_pd_done(hobul_p->hhul_hndl, hhul_pd_hndl, pd_idx, pd_ul_resources_p)) {\r
- THH_hob_free_pd(hobul_p->hh_hndl, pd_idx);\r
- status = IB_ERROR;\r
- goto cleanup_pd;\r
- }\r
- }\r
-\r
- VALIDATE_INDEX(pd_idx, hobul_p->max_pd, IB_ERROR, cleanup_pd);\r
-\r
- // Save data refs for future use\r
- cl_mutex_acquire(&hobul_p->pd_info_tbl[pd_idx].mutex);\r
- hobul_p->pd_info_tbl[pd_idx].pd_num = pd_idx;\r
- hobul_p->pd_info_tbl[pd_idx].hca_idx = hob_p->index;\r
- hobul_p->pd_info_tbl[pd_idx].hhul_pd_hndl = hhul_pd_hndl;\r
- hobul_p->pd_info_tbl[pd_idx].pd_ul_resources_p = pd_ul_resources_p;\r
- hobul_p->pd_info_tbl[pd_idx].count = 0;\r
- hobul_p->pd_info_tbl[pd_idx].kernel_mode = !(p_umv_buf && p_umv_buf->command);\r
- hobul_p->pd_info_tbl[pd_idx].mark = E_MARK_PD;\r
- cl_mutex_release(&hobul_p->pd_info_tbl[pd_idx].mutex);\r
-\r
- cl_atomic_inc( &hobul_p->count );\r
-\r
- if (ph_pd) *ph_pd = (ib_pd_handle_t)PD_HNDL_FROM_PD(pd_idx);\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("hca_idx 0x%x pd_idx 0x%x returned 0x%p\n", hob_p->index, pd_idx, *ph_pd));\r
-\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = p_umv_buf->input_size;\r
- /* \r
- * Copy the pd_idx back to user\r
- */\r
- cl_memcpy (((uint8_t* __ptr64)p_umv_buf->p_inout_buf + hca_ul_info->pd_ul_resources_sz),\r
- &pd_idx, sizeof (pd_idx));\r
- p_umv_buf->status = IB_SUCCESS;\r
- }\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup_pd:\r
- THHUL_pdm_free_pd_prep(hobul_p->hhul_hndl, hhul_pd_hndl, FALSE);\r
- THHUL_pdm_free_pd_done(hobul_p->hhul_hndl, hhul_pd_hndl);\r
-\r
-cleanup:\r
- if( !(p_umv_buf && p_umv_buf->command) && pd_ul_resources_p )\r
- cl_free( pd_ul_resources_p);\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = status;\r
- }\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_deallocate_pd (\r
- IN ib_pd_handle_t h_pd)\r
-{\r
- u_int32_t hca_idx = PD_HCA_FROM_HNDL(h_pd);\r
- u_int32_t pd_idx = PD_NUM_FROM_HNDL(h_pd);\r
- mlnx_hobul_t *hobul_p;\r
- HHUL_pd_hndl_t hhul_pd_hndl;\r
- ib_api_status_t status;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_CA_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
- VALIDATE_INDEX(pd_idx, hobul_p->max_pd, IB_INVALID_PD_HANDLE, cleanup);\r
- if (E_MARK_PD != hobul_p->pd_info_tbl[pd_idx].mark) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- cl_mutex_acquire(&hobul_p->pd_info_tbl[pd_idx].mutex);\r
-\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("pd %d count %d k_mod %d\n", pd_idx, hobul_p->pd_info_tbl[pd_idx].count, hobul_p->pd_info_tbl[pd_idx].kernel_mode));\r
-\r
- if (0 != hobul_p->pd_info_tbl[pd_idx].count) {\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("pd %d count %d\n", pd_idx, hobul_p->pd_info_tbl[pd_idx].count));\r
- status = IB_RESOURCE_BUSY;\r
- goto cleanup_locked;\r
- }\r
-\r
- hhul_pd_hndl = hobul_p->pd_info_tbl[pd_idx].hhul_pd_hndl;\r
-\r
- // PREP:\r
- if (hobul_p->pd_info_tbl[pd_idx].kernel_mode) {\r
- if (HH_OK != THHUL_pdm_free_pd_prep(hobul_p->hhul_hndl, hhul_pd_hndl, FALSE)) {\r
- status = IB_ERROR;\r
- goto cleanup_locked;\r
- }\r
- }\r
-\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("pd %d before free_pd hh_hndl %p\n", \r
- pd_idx, hobul_p->hh_hndl));\r
-\r
- if (HH_OK != THH_hob_free_pd(hobul_p->hh_hndl, pd_idx)) {\r
- status = IB_ERROR;\r
- goto cleanup_locked;\r
- }\r
-\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("pd %d after free_pd\n", pd_idx));\r
-\r
- if (hobul_p->pd_info_tbl[pd_idx].kernel_mode) {\r
- if (HH_OK != THHUL_pdm_free_pd_done(hobul_p->hhul_hndl, hhul_pd_hndl)) {\r
- status = IB_ERROR;\r
- goto cleanup_locked;\r
- }\r
- if (hobul_p->pd_info_tbl[pd_idx].pd_ul_resources_p)\r
- cl_free( hobul_p->pd_info_tbl[pd_idx].pd_ul_resources_p);\r
- }\r
-\r
- hobul_p->pd_info_tbl[pd_idx].mark = E_MARK_INVALID;\r
- hobul_p->pd_info_tbl[pd_idx].pd_ul_resources_p = NULL;\r
-\r
- cl_mutex_release(&hobul_p->pd_info_tbl[pd_idx].mutex);\r
-\r
- cl_atomic_dec( &hobul_p->count );\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup_locked:\r
- cl_mutex_release(&hobul_p->pd_info_tbl[pd_idx].mutex);\r
-\r
-cleanup:\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-/* \r
-* Address Vector Management Verbs\r
-*/\r
-ib_api_status_t\r
-mlnx_create_av (\r
- IN const ib_pd_handle_t h_pd,\r
- IN const ib_av_attr_t *p_addr_vector,\r
- OUT ib_av_handle_t *ph_av,\r
- IN OUT ci_umv_buf_t *p_umv_buf )\r
-{\r
- u_int32_t hca_idx = PD_HCA_FROM_HNDL(h_pd);\r
- u_int32_t pd_idx = PD_NUM_FROM_HNDL(h_pd);\r
- HHUL_ud_av_hndl_t av_h;\r
- mlnx_hobul_t *hobul_p;\r
- mlnx_avo_t *avo_p = NULL;\r
- HHUL_pd_hndl_t hhul_pd_hndl;\r
- ib_api_status_t status;\r
-\r
- VAPI_ud_av_t av;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_CA_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
- VALIDATE_INDEX(pd_idx, hobul_p->max_pd, IB_INVALID_PD_HANDLE, cleanup);\r
- if (E_MARK_PD != hobul_p->pd_info_tbl[pd_idx].mark) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
- hhul_pd_hndl = hobul_p->pd_info_tbl[pd_idx].hhul_pd_hndl;\r
-\r
- if (NULL == (avo_p = cl_zalloc( sizeof(mlnx_avo_t)))) {\r
- status = IB_INSUFFICIENT_MEMORY;\r
- goto cleanup;\r
- }\r
-\r
- cl_memclr(&av, sizeof(av));\r
- mlnx_conv_ibal_av(hobul_p->hh_hndl, p_addr_vector, &av);\r
- // This creates a non priviledged ud_av.\r
- // To create a privilged ud_av call THH_hob_create_ud_av()\r
- if (HH_OK != THHUL_pdm_create_ud_av(hobul_p->hhul_hndl, hhul_pd_hndl, &av, &av_h)) {\r
- status = IB_INSUFFICIENT_RESOURCES;\r
- goto cleanup;\r
- }\r
-\r
- // update PD object count\r
- cl_atomic_inc(&hobul_p->pd_info_tbl[pd_idx].count);\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("pd %d count %d\n", pd_idx, hobul_p->pd_info_tbl[pd_idx].count));\r
-\r
-\r
- avo_p->mark = E_MARK_AV;\r
- avo_p->hca_idx = hca_idx;\r
- avo_p->pd_idx = pd_idx;\r
- avo_p->h_av = av_h;\r
-\r
- if (ph_av) *ph_av = (ib_av_handle_t)avo_p;\r
-\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->status = IB_SUCCESS;\r
- }\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- if (avo_p) {\r
- avo_p->mark = E_MARK_INVALID;\r
- cl_free( avo_p);\r
- }\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = status;\r
- }\r
-\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_query_av (\r
- IN const ib_av_handle_t h_av,\r
- OUT ib_av_attr_t *p_addr_vector,\r
- OUT ib_pd_handle_t *ph_pd,\r
- IN OUT ci_umv_buf_t *p_umv_buf )\r
-{\r
- mlnx_avo_t *avo_p = (mlnx_avo_t *)h_av;\r
- mlnx_hobul_t *hobul_p;\r
- ib_api_status_t status;\r
-\r
- VAPI_ud_av_t av;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- if (!avo_p || avo_p->mark != E_MARK_AV) {\r
- status = IB_INVALID_AV_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- VALIDATE_INDEX(avo_p->hca_idx, MLNX_MAX_HCA, IB_INVALID_CA_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[avo_p->hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_AV_HANDLE;\r
- goto cleanup;\r
- }\r
- VALIDATE_INDEX(avo_p->pd_idx, hobul_p->max_pd, IB_INVALID_PD_HANDLE, cleanup);\r
- if (E_MARK_PD != hobul_p->pd_info_tbl[avo_p->pd_idx].mark) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- if (p_addr_vector) {\r
- if (HH_OK != THHUL_pdm_query_ud_av(hobul_p->hhul_hndl, avo_p->h_av, &av)) {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
- mlnx_conv_vapi_av(hobul_p->hh_hndl, &av, p_addr_vector);\r
- }\r
-\r
- if (ph_pd) *ph_pd = (ib_pd_handle_t)PD_HNDL_FROM_PD(avo_p->pd_idx);\r
-\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = IB_SUCCESS;\r
- }\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = status;\r
- }\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_modify_av (\r
- IN const ib_av_handle_t h_av,\r
- IN const ib_av_attr_t *p_addr_vector,\r
- IN OUT ci_umv_buf_t *p_umv_buf )\r
-{\r
- mlnx_avo_t *avo_p = (mlnx_avo_t *)h_av;\r
- mlnx_hobul_t *hobul_p;\r
- ib_api_status_t status;\r
-\r
- VAPI_ud_av_t av;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- if (!avo_p || avo_p->mark != E_MARK_AV) {\r
- status = IB_INVALID_AV_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- VALIDATE_INDEX(avo_p->hca_idx, MLNX_MAX_HCA, IB_INVALID_CA_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[avo_p->hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_AV_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- cl_memclr(&av, sizeof(av));\r
- mlnx_conv_ibal_av(hobul_p->hh_hndl, p_addr_vector, &av);\r
- if (HH_OK != THHUL_pdm_modify_ud_av(hobul_p->hhul_hndl, avo_p->h_av, &av)) {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
-\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = IB_SUCCESS;\r
- }\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = status;\r
- }\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_destroy_av (\r
- IN const ib_av_handle_t h_av)\r
-{\r
- mlnx_avo_t *avo_p = (mlnx_avo_t *)h_av;\r
- mlnx_hobul_t *hobul_p;\r
- ib_api_status_t status;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- if (!avo_p || avo_p->mark != E_MARK_AV) {\r
- status = IB_INVALID_AV_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- VALIDATE_INDEX(avo_p->hca_idx, MLNX_MAX_HCA, IB_INVALID_CA_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[avo_p->hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_AV_HANDLE;\r
- goto cleanup;\r
- }\r
- VALIDATE_INDEX(avo_p->pd_idx, hobul_p->max_pd, IB_INVALID_PD_HANDLE, cleanup);\r
- if (E_MARK_PD != hobul_p->pd_info_tbl[avo_p->pd_idx].mark) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- // This destroy's a non priviledged ud_av.\r
- // To destroy a privilged ud_av call THH_hob_destroy_ud_av()\r
- if (HH_OK != THHUL_pdm_destroy_ud_av(hobul_p->hhul_hndl, avo_p->h_av)) {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
-\r
- // update PD object count\r
- cl_atomic_dec(&hobul_p->pd_info_tbl[avo_p->pd_idx].count);\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("pd %d count %d\n", avo_p->pd_idx, hobul_p->pd_info_tbl[avo_p->pd_idx].count));\r
-\r
- avo_p->mark = E_MARK_INVALID;\r
- cl_free( avo_p);\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup:\r
- if (avo_p) {\r
- avo_p->mark = E_MARK_INVALID;\r
- cl_free( avo_p);\r
- }\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-/*\r
-* Queue Pair Management Verbs\r
-*/\r
-\r
-ib_api_status_t\r
-mlnx_create_qp (\r
- IN const ib_pd_handle_t h_pd,\r
- IN const void *qp_context,\r
- IN const ib_qp_create_t *p_create_attr,\r
- OUT ib_qp_attr_t *p_qp_attr,\r
- OUT ib_qp_handle_t *ph_qp,\r
- IN OUT ci_umv_buf_t *p_umv_buf )\r
-{\r
- ib_api_status_t status;\r
- ib_qp_handle_t h_qp;\r
-\r
- u_int32_t hca_idx = PD_HCA_FROM_HNDL(h_pd);\r
- u_int32_t pd_idx = PD_NUM_FROM_HNDL(h_pd);\r
- u_int32_t qp_num;\r
- u_int32_t qp_idx;\r
- u_int32_t send_cq_num;\r
- u_int32_t send_cq_idx;\r
- u_int32_t recv_cq_num;\r
- u_int32_t recv_cq_idx;\r
- mlnx_hobul_t *hobul_p;\r
- HH_hca_dev_t *hca_ul_info;\r
- HH_qp_init_attr_t hh_qp_init_attr;\r
- HHUL_qp_init_attr_t ul_qp_init_attr;\r
- HHUL_qp_hndl_t hhul_qp_hndl = NULL;\r
- VAPI_qp_cap_t hh_qp_cap;\r
- void *qp_ul_resources_p = NULL;\r
- VAPI_sg_lst_entry_t *send_sge_p = NULL;\r
- VAPI_sg_lst_entry_t *recv_sge_p = NULL;\r
- u_int32_t num_sge;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_CA_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
- VALIDATE_INDEX(pd_idx, hobul_p->max_pd, IB_INVALID_PD_HANDLE, cleanup);\r
- if (E_MARK_PD != hobul_p->pd_info_tbl[pd_idx].mark) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- hca_ul_info = (HH_hca_dev_t *)hobul_p->hh_hndl;\r
- if (NULL == hca_ul_info) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- // The create attributes must be provided\r
- if (!p_create_attr) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
-\r
- // convert input parameters\r
- cl_memclr(&ul_qp_init_attr, sizeof(ul_qp_init_attr));\r
- mlnx_conv_qp_create_attr(p_create_attr, &ul_qp_init_attr, NULL);\r
- send_cq_num = CQ_NUM_FROM_HNDL(p_create_attr->h_sq_cq);\r
- recv_cq_num = CQ_NUM_FROM_HNDL(p_create_attr->h_rq_cq);\r
- send_cq_idx = send_cq_num & hobul_p->cq_idx_mask;\r
- recv_cq_idx = recv_cq_num & hobul_p->cq_idx_mask;\r
- VALIDATE_INDEX(send_cq_idx, hobul_p->max_cq, IB_INVALID_CQ_HANDLE, cleanup);\r
- if ( E_MARK_CQ != hobul_p->cq_info_tbl[send_cq_idx].mark) {\r
- status = IB_INVALID_CQ_HANDLE;\r
- goto cleanup;\r
- }\r
- VALIDATE_INDEX(recv_cq_idx, hobul_p->max_cq, IB_INVALID_CQ_HANDLE, cleanup);\r
- if ( E_MARK_CQ != hobul_p->cq_info_tbl[recv_cq_idx].mark) {\r
- status = IB_INVALID_CQ_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- ul_qp_init_attr.pd = hobul_p->pd_info_tbl[pd_idx].hhul_pd_hndl;\r
- ul_qp_init_attr.sq_cq = hobul_p->cq_info_tbl[send_cq_idx].hhul_cq_hndl;\r
- ul_qp_init_attr.rq_cq = hobul_p->cq_info_tbl[recv_cq_idx].hhul_cq_hndl;\r
-\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- // For user mode calls - obtain and verify the vendor information\r
- if ((p_umv_buf->input_size - sizeof (u_int32_t)) != \r
- hca_ul_info->qp_ul_resources_sz ||\r
- NULL == p_umv_buf->p_inout_buf) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
- qp_ul_resources_p = (void *)p_umv_buf->p_inout_buf;\r
-\r
- } else {\r
- // for kernel mode calls - allocate app resources. Use prep->call->done sequence\r
- qp_ul_resources_p = cl_zalloc( hca_ul_info->qp_ul_resources_sz);\r
- if (!qp_ul_resources_p) {\r
- status = IB_INSUFFICIENT_MEMORY;\r
- goto cleanup;\r
- }\r
-\r
- if (HH_OK != THHUL_qpm_create_qp_prep(hobul_p->hhul_hndl, &ul_qp_init_attr, &hhul_qp_hndl, &hh_qp_cap, qp_ul_resources_p)) {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
- // TBD: if not same report error to IBAL\r
- ul_qp_init_attr.qp_cap = hh_qp_cap; // struct assign\r
- }\r
-\r
- // Convert HHUL to HH structure (for HH create_qp)\r
- hh_qp_init_attr.pd = pd_idx;\r
- hh_qp_init_attr.rdd = 0; // TBD: RDD\r
- if( ul_qp_init_attr.srq != HHUL_INVAL_SRQ_HNDL )\r
- {\r
- // TBD: HH handle from HHUL handle.\r
- CL_ASSERT( ul_qp_init_attr.srq == HHUL_INVAL_SRQ_HNDL );\r
- }\r
- else\r
- {\r
- hh_qp_init_attr.srq = HH_INVAL_SRQ_HNDL;\r
- }\r
- hh_qp_init_attr.sq_cq = send_cq_num;\r
- hh_qp_init_attr.rq_cq = recv_cq_num;\r
- hh_qp_init_attr.sq_sig_type = ul_qp_init_attr.sq_sig_type;\r
- hh_qp_init_attr.rq_sig_type = ul_qp_init_attr.rq_sig_type;\r
- hh_qp_init_attr.ts_type = ul_qp_init_attr.ts_type;\r
- hh_qp_init_attr.qp_cap = ul_qp_init_attr.qp_cap; // struct assign\r
-\r
- // Allocate the QP (cmdif)\r
- if (HH_OK != THH_hob_create_qp(hobul_p->hh_hndl, &hh_qp_init_attr, qp_ul_resources_p, &qp_num)) {\r
- status = IB_INSUFFICIENT_RESOURCES;\r
- goto cleanup_qp;\r
- }\r
-\r
- if( !(p_umv_buf && p_umv_buf->command) )\r
- {\r
- // Manage user level resources\r
- if (HH_OK != THHUL_qpm_create_qp_done(hobul_p->hhul_hndl, hhul_qp_hndl, qp_num, qp_ul_resources_p)) {\r
- THH_hob_destroy_qp(hobul_p->hh_hndl, qp_num);\r
- status = IB_ERROR;\r
- goto cleanup_qp;\r
- }\r
-\r
- // Create SQ and RQ iov\r
- num_sge = ul_qp_init_attr.qp_cap.max_sg_size_sq;\r
- send_sge_p = cl_zalloc( num_sge * sizeof(VAPI_sg_lst_entry_t));\r
- if (!send_sge_p) {\r
- status = IB_INSUFFICIENT_MEMORY;\r
- goto cleanup_qp;\r
- }\r
-\r
- num_sge = ul_qp_init_attr.qp_cap.max_sg_size_rq;\r
- recv_sge_p = cl_zalloc( num_sge * sizeof(VAPI_sg_lst_entry_t));\r
- if (!recv_sge_p) {\r
- status = IB_INSUFFICIENT_MEMORY;\r
- goto cleanup_qp;\r
- }\r
- }\r
-\r
- // Save data refs for future use\r
- qp_idx = qp_num & hobul_p->qp_idx_mask;\r
- VALIDATE_INDEX(qp_idx, hobul_p->max_qp, IB_ERROR, cleanup_qp);\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("hobul_p 0x%p mask 0x%x qp_idx 0x%x qp_num 0x%x\n",\r
- hobul_p, hobul_p->qp_idx_mask, qp_idx, qp_num));\r
-\r
- h_qp = (ib_qp_handle_t)QP_HNDL_FROM_QP(qp_idx);\r
- cl_mutex_acquire(&h_qp->mutex);\r
- h_qp->pd_num = pd_idx;\r
- h_qp->hhul_qp_hndl = hhul_qp_hndl;\r
- h_qp->qp_type = p_create_attr->qp_type;\r
- h_qp->sq_signaled = p_create_attr->sq_signaled;\r
- h_qp->qp_context = qp_context;\r
- h_qp->qp_ul_resources_p = qp_ul_resources_p;\r
- h_qp->sq_size = ul_qp_init_attr.qp_cap.max_sg_size_sq;\r
- h_qp->rq_size = ul_qp_init_attr.qp_cap.max_sg_size_rq;\r
- h_qp->send_sge_p = send_sge_p;\r
- h_qp->recv_sge_p = recv_sge_p;\r
- h_qp->qp_num = qp_num;\r
- h_qp->h_sq_cq = &hobul_p->cq_info_tbl[send_cq_idx];\r
- h_qp->h_rq_cq = &hobul_p->cq_info_tbl[recv_cq_idx];\r
- h_qp->kernel_mode = !(p_umv_buf && p_umv_buf->command);\r
- h_qp->mark = E_MARK_QP;\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("qp num 0x%x idx 0x%x cq_s 0x%x cq_r 0x%x\n",\r
- qp_num, qp_idx, send_cq_idx, recv_cq_idx));\r
- cl_mutex_release(&h_qp->mutex);\r
- // Update PD object count\r
- cl_atomic_inc(&hobul_p->pd_info_tbl[pd_idx].count);\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("pd %d count %d\n", pd_idx, hobul_p->pd_info_tbl[pd_idx].count));\r
-\r
- // Query QP to obtain requested attributes\r
- if (p_qp_attr) {\r
- if (IB_SUCCESS != (status = mlnx_query_qp (h_qp, p_qp_attr, p_umv_buf)))\r
- {\r
- if( !(p_umv_buf && p_umv_buf->command) )\r
- goto cleanup_qp;\r
- else\r
- goto cleanup;\r
- }\r
- }\r
-\r
- if (ph_qp) *ph_qp = h_qp;\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = p_umv_buf->input_size;\r
- p_umv_buf->status = IB_SUCCESS;\r
- /* \r
- * Copy the qp_idx back to user\r
- */\r
- cl_memcpy (((uint8_t* __ptr64)p_umv_buf->p_inout_buf + hca_ul_info->qp_ul_resources_sz),\r
- &qp_num, sizeof (qp_num));\r
- }\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup_qp:\r
- if (send_sge_p) cl_free( send_sge_p);\r
- if (recv_sge_p) cl_free( recv_sge_p);\r
- if( !(p_umv_buf && p_umv_buf->command) )\r
- THHUL_qpm_destroy_qp_done(hobul_p->hhul_hndl, hhul_qp_hndl);\r
-\r
-cleanup:\r
- if( !(p_umv_buf && p_umv_buf->command) && qp_ul_resources_p)\r
- cl_free( qp_ul_resources_p);\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = status;\r
- }\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_create_spl_qp (\r
- IN const ib_pd_handle_t h_pd,\r
- IN const uint8_t port_num,\r
- IN const void *qp_context,\r
- IN const ib_qp_create_t *p_create_attr,\r
- OUT ib_qp_attr_t *p_qp_attr,\r
- OUT ib_qp_handle_t *ph_qp )\r
-{\r
- ib_api_status_t status;\r
- ib_qp_handle_t h_qp;\r
- ci_umv_buf_t *p_umv_buf = NULL;\r
-\r
- u_int32_t hca_idx = PD_HCA_FROM_HNDL(h_pd);\r
- u_int32_t pd_idx = PD_NUM_FROM_HNDL(h_pd);\r
- u_int32_t qp_num;\r
- u_int32_t qp_idx;\r
- u_int32_t send_cq_num;\r
- u_int32_t send_cq_idx;\r
- u_int32_t recv_cq_num;\r
- u_int32_t recv_cq_idx;\r
- mlnx_hobul_t *hobul_p;\r
- HH_hca_dev_t *hca_ul_info;\r
- HH_qp_init_attr_t hh_qp_init_attr;\r
- HHUL_qp_init_attr_t ul_qp_init_attr;\r
- HHUL_qp_hndl_t hhul_qp_hndl = NULL;\r
- VAPI_special_qp_t vapi_qp_type;\r
- VAPI_qp_cap_t hh_qp_cap;\r
- void *qp_ul_resources_p = NULL;\r
- VAPI_sg_lst_entry_t *send_sge_p = NULL;\r
- VAPI_sg_lst_entry_t *recv_sge_p = NULL;\r
- u_int32_t num_sge;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_CA_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
- VALIDATE_INDEX(pd_idx, hobul_p->max_pd, IB_INVALID_PD_HANDLE, cleanup);\r
- if (E_MARK_PD != hobul_p->pd_info_tbl[pd_idx].mark) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- hca_ul_info = (HH_hca_dev_t *)hobul_p->hh_hndl;\r
- if (NULL == hca_ul_info) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- // The create attributes must be provided\r
- if (!p_create_attr) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
-\r
- // convert input parameters\r
- cl_memclr(&ul_qp_init_attr, sizeof(ul_qp_init_attr));\r
- mlnx_conv_qp_create_attr(p_create_attr, &ul_qp_init_attr, &vapi_qp_type);\r
- send_cq_num = CQ_NUM_FROM_HNDL(p_create_attr->h_sq_cq);\r
- recv_cq_num = CQ_NUM_FROM_HNDL(p_create_attr->h_rq_cq);\r
- send_cq_idx = send_cq_num & hobul_p->cq_idx_mask;\r
- recv_cq_idx = recv_cq_num & hobul_p->cq_idx_mask;\r
- VALIDATE_INDEX(send_cq_idx, hobul_p->max_cq, IB_INVALID_CQ_HANDLE, cleanup);\r
- if ( E_MARK_CQ != hobul_p->cq_info_tbl[send_cq_idx].mark) {\r
- status = IB_INVALID_CQ_HANDLE;\r
- goto cleanup;\r
- }\r
- VALIDATE_INDEX(recv_cq_idx, hobul_p->max_cq, IB_INVALID_CQ_HANDLE, cleanup);\r
- if ( E_MARK_CQ != hobul_p->cq_info_tbl[recv_cq_idx].mark) {\r
- status = IB_INVALID_CQ_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- ul_qp_init_attr.pd = hobul_p->pd_info_tbl[pd_idx].hhul_pd_hndl;\r
- ul_qp_init_attr.sq_cq = hobul_p->cq_info_tbl[send_cq_idx].hhul_cq_hndl;\r
- ul_qp_init_attr.rq_cq = hobul_p->cq_info_tbl[recv_cq_idx].hhul_cq_hndl;\r
-\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- // For user mode calls - obtain and verify the vendor information\r
- if (p_umv_buf->input_size != hca_ul_info->qp_ul_resources_sz ||\r
- NULL == p_umv_buf->p_inout_buf) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
- qp_ul_resources_p = (void *)p_umv_buf->p_inout_buf;\r
-\r
- } else {\r
- // For kernel mode calls - allocate app resources. Use prep->call->done sequence\r
- qp_ul_resources_p = cl_zalloc( hca_ul_info->qp_ul_resources_sz);\r
- if (!qp_ul_resources_p) {\r
- status = IB_INSUFFICIENT_MEMORY;\r
- goto cleanup;\r
- }\r
-\r
- if (HH_OK != THHUL_qpm_special_qp_prep(hobul_p->hhul_hndl,\r
- vapi_qp_type,\r
- port_num, \r
- &ul_qp_init_attr,\r
- &hhul_qp_hndl,\r
- &hh_qp_cap,\r
- qp_ul_resources_p)) {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
- // TBD: if not same report error to IBAL\r
- ul_qp_init_attr.qp_cap = hh_qp_cap; // struct assign\r
- }\r
-\r
- // Convert HHUL to HH structure (for HH create_qp)\r
- hh_qp_init_attr.pd = pd_idx;\r
- hh_qp_init_attr.rdd = 0; // TBD: RDD\r
- if( ul_qp_init_attr.srq != HHUL_INVAL_SRQ_HNDL )\r
- {\r
- // TBD: HH handle from HHUL handle.\r
- CL_ASSERT( ul_qp_init_attr.srq == HHUL_INVAL_SRQ_HNDL );\r
- }\r
- else\r
- {\r
- hh_qp_init_attr.srq = HH_INVAL_SRQ_HNDL;\r
- }\r
- hh_qp_init_attr.sq_cq = send_cq_num;\r
- hh_qp_init_attr.rq_cq = recv_cq_num;\r
- hh_qp_init_attr.sq_sig_type = ul_qp_init_attr.sq_sig_type;\r
- hh_qp_init_attr.rq_sig_type = ul_qp_init_attr.rq_sig_type;\r
- hh_qp_init_attr.ts_type = VAPI_TS_UD;\r
- hh_qp_init_attr.qp_cap = ul_qp_init_attr.qp_cap; // struct assign\r
-\r
- // Allocate the QP (cmdif)\r
- if (HH_OK != THH_hob_get_special_qp( hobul_p->hh_hndl,\r
- vapi_qp_type,\r
- port_num,\r
- &hh_qp_init_attr,\r
- qp_ul_resources_p,\r
- &qp_num))\r
- {\r
- status = IB_ERROR;\r
- goto cleanup_qp;\r
- }\r
-\r
- if( !(p_umv_buf && p_umv_buf->command) )\r
- {\r
- // Manage user level resources\r
- if (HH_OK != THHUL_qpm_create_qp_done(hobul_p->hhul_hndl, hhul_qp_hndl, qp_num, qp_ul_resources_p)) {\r
- THH_hob_destroy_qp(hobul_p->hh_hndl, qp_num);\r
- status = IB_ERROR;\r
- goto cleanup_qp;\r
- }\r
-\r
- // Create SQ and RQ iov\r
- num_sge = ul_qp_init_attr.qp_cap.max_sg_size_sq;\r
- send_sge_p = cl_zalloc( num_sge * sizeof(VAPI_sg_lst_entry_t));\r
- if (!send_sge_p) {\r
- status = IB_INSUFFICIENT_MEMORY;\r
- goto cleanup_qp;\r
- }\r
-\r
- num_sge = ul_qp_init_attr.qp_cap.max_sg_size_rq;\r
- recv_sge_p = cl_zalloc( num_sge * sizeof(VAPI_sg_lst_entry_t));\r
- if (!recv_sge_p) {\r
- status = IB_INSUFFICIENT_MEMORY;\r
- goto cleanup_qp;\r
- }\r
- }\r
-\r
- // Save data refs for future use\r
- qp_idx = qp_num & hobul_p->qp_idx_mask;\r
- VALIDATE_INDEX(qp_idx, hobul_p->max_qp, IB_ERROR, cleanup_qp);\r
-\r
- h_qp = (ib_qp_handle_t)QP_HNDL_FROM_QP(qp_idx);\r
- cl_mutex_acquire(&h_qp->mutex);\r
- h_qp->pd_num = pd_idx;\r
- h_qp->hhul_qp_hndl = hhul_qp_hndl;\r
- h_qp->qp_type = p_create_attr->qp_type;\r
- h_qp->sq_signaled = p_create_attr->sq_signaled;\r
- h_qp->qp_context = qp_context;\r
- h_qp->qp_ul_resources_p = qp_ul_resources_p;\r
- h_qp->sq_size = ul_qp_init_attr.qp_cap.max_sg_size_sq;\r
- h_qp->rq_size = ul_qp_init_attr.qp_cap.max_sg_size_rq;\r
- h_qp->send_sge_p = send_sge_p;\r
- h_qp->recv_sge_p = recv_sge_p;\r
- h_qp->qp_num = qp_num;\r
- h_qp->h_sq_cq = &hobul_p->cq_info_tbl[send_cq_idx];\r
- h_qp->h_rq_cq = &hobul_p->cq_info_tbl[recv_cq_idx];\r
- h_qp->kernel_mode = !(p_umv_buf && p_umv_buf->command);\r
- h_qp->mark = E_MARK_QP;\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("qp num 0x%x idx 0x%x cq_s 0x%x cq_r 0x%x\n",\r
- qp_num, qp_idx, send_cq_idx, recv_cq_idx));\r
- cl_mutex_release(&h_qp->mutex);\r
-\r
- /* Mark the CQ's associated with this special QP as being high priority. */\r
- cl_atomic_inc( &h_qp->h_sq_cq->spl_qp_cnt );\r
- KeSetImportanceDpc( &h_qp->h_sq_cq->dpc, HighImportance );\r
- cl_atomic_inc( &h_qp->h_rq_cq->spl_qp_cnt );\r
- KeSetImportanceDpc( &h_qp->h_rq_cq->dpc, HighImportance );\r
-\r
- // Update PD object count\r
- cl_atomic_inc(&hobul_p->pd_info_tbl[pd_idx].count);\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("pd %d count %d\n", pd_idx, hobul_p->pd_info_tbl[pd_idx].count));\r
-\r
- // Query QP to obtain requested attributes\r
- if (p_qp_attr) {\r
- if (IB_SUCCESS != (status = mlnx_query_qp (h_qp, p_qp_attr, p_umv_buf))) {\r
- goto cleanup;\r
- }\r
- }\r
-\r
- if (ph_qp) *ph_qp = h_qp;\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = p_umv_buf->input_size;\r
- p_umv_buf->status = IB_SUCCESS;\r
- }\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup_qp:\r
- if (send_sge_p) cl_free( send_sge_p);\r
- if (recv_sge_p) cl_free( recv_sge_p);\r
- if( !(p_umv_buf && p_umv_buf->command) )\r
- THHUL_qpm_destroy_qp_done(hobul_p->hhul_hndl, hhul_qp_hndl);\r
-\r
-cleanup:\r
- if( !(p_umv_buf && p_umv_buf->command) && qp_ul_resources_p )\r
- cl_free( qp_ul_resources_p);\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = status;\r
- }\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_modify_qp (\r
- IN const ib_qp_handle_t h_qp,\r
- IN const ib_qp_mod_t *p_modify_attr,\r
- OUT ib_qp_attr_t *p_qp_attr OPTIONAL,\r
- IN OUT ci_umv_buf_t *p_umv_buf OPTIONAL )\r
-{\r
- ib_api_status_t status;\r
-\r
- u_int32_t hca_idx = QP_HCA_FROM_HNDL(h_qp);\r
- u_int32_t qp_num = QP_NUM_FROM_HNDL(h_qp);\r
- u_int32_t qp_idx = 0;\r
- mlnx_hobul_t *hobul_p;\r
- HHUL_qp_hndl_t hhul_qp_hndl;\r
- VAPI_qp_attr_mask_t hh_qp_attr_mask;\r
- VAPI_qp_attr_t hh_qp_attr;\r
- VAPI_qp_state_t hh_qp_state;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_CA_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_QP_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- qp_idx = qp_num & hobul_p->qp_idx_mask;\r
- VALIDATE_INDEX(qp_idx, hobul_p->max_qp, IB_INVALID_QP_HANDLE, cleanup);\r
- if ( E_MARK_QP != hobul_p->qp_info_tbl[qp_idx].mark) {\r
- status = IB_INVALID_QP_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, \r
- ("Before acquire mutex to modify qp_idx 0x%x\n", \r
- qp_idx));\r
-\r
- cl_mutex_acquire(&hobul_p->qp_info_tbl[qp_idx].mutex);\r
-\r
- hhul_qp_hndl = hobul_p->qp_info_tbl[qp_idx].hhul_qp_hndl;\r
-\r
- // Obtain curernt state of QP\r
- if (HH_OK != THH_hob_query_qp(hobul_p->hh_hndl, hobul_p->qp_info_tbl[qp_idx].qp_num, &hh_qp_attr))\r
- {\r
- status = IB_ERROR;\r
- goto cleanup_locked;\r
- }\r
- hh_qp_state = hh_qp_attr.qp_state; // The current (pre-modify) state\r
-\r
- // Convert the input parameters. Use query result as default (no cl_memset())\r
- // cl_memclr(&hh_qp_attr, sizeof(hh_qp_attr));\r
- status = mlnx_conv_qp_modify_attr(hobul_p->hh_hndl,\r
- hobul_p->qp_info_tbl[qp_idx].qp_type,\r
- p_modify_attr, &hh_qp_attr, &hh_qp_attr_mask);\r
- if( status != IB_SUCCESS )\r
- goto cleanup_locked;\r
-\r
- if (HH_OK != THH_hob_modify_qp(hobul_p->hh_hndl,\r
- hobul_p->qp_info_tbl[qp_idx].qp_num,\r
- hh_qp_state, &hh_qp_attr, &hh_qp_attr_mask))\r
- {\r
- status = IB_ERROR;\r
- goto cleanup_locked;\r
- }\r
-\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, \r
- ("After hob_modify_qp qp_idx 0x%x k_mod %d\n", \r
- qp_idx, hobul_p->qp_info_tbl[qp_idx].kernel_mode));\r
-\r
- // Notify HHUL of the new (post-modify) state. This is done for both k-mode calls only\r
- if (hobul_p->qp_info_tbl[qp_idx].kernel_mode) {\r
- if (HH_OK != THHUL_qpm_modify_qp_done(hobul_p->hhul_hndl, hhul_qp_hndl, hh_qp_attr.qp_state))\r
- {\r
- status = IB_ERROR;\r
- goto cleanup_locked;\r
- } \r
- } \r
- cl_mutex_release(&hobul_p->qp_info_tbl[qp_idx].mutex);\r
-\r
- if ((p_qp_attr) && !(p_umv_buf && p_umv_buf->command)) {\r
- if (IB_SUCCESS != (status = mlnx_query_qp (h_qp, p_qp_attr, p_umv_buf))) {\r
- goto cleanup;\r
- }\r
- }\r
-\r
- if ( p_umv_buf && p_umv_buf->command && (! hobul_p->qp_info_tbl[qp_idx].kernel_mode)) {\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, \r
- ("mod_qp qp_idx %d umv_buf %p inout_buf %p\n", \r
- qp_idx, p_umv_buf, p_umv_buf->p_inout_buf));\r
- if (p_umv_buf->p_inout_buf) {\r
- p_umv_buf->output_size = sizeof (VAPI_qp_state_t);\r
- cl_memcpy (p_umv_buf->p_inout_buf, &(hh_qp_attr.qp_state), \r
- (size_t)p_umv_buf->output_size);\r
- p_umv_buf->status = IB_SUCCESS;\r
- }\r
- }\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-\r
-cleanup_locked:\r
- cl_mutex_release(&hobul_p->qp_info_tbl[qp_idx].mutex);\r
-\r
-cleanup:\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = status;\r
- }\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_query_qp (\r
- IN const ib_qp_handle_t h_qp,\r
- OUT ib_qp_attr_t *p_qp_attr,\r
- IN OUT ci_umv_buf_t *p_umv_buf )\r
-{\r
- ib_api_status_t status;\r
-\r
- u_int32_t hca_idx = QP_HCA_FROM_HNDL(h_qp);\r
- u_int32_t qp_num = QP_NUM_FROM_HNDL(h_qp);\r
- u_int32_t qp_idx = 0;\r
- mlnx_hobul_t *hobul_p;\r
- VAPI_qp_attr_t hh_qp_attr;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_CA_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_QP_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- qp_idx = qp_num & hobul_p->qp_idx_mask;\r
- VALIDATE_INDEX(qp_idx, hobul_p->max_qp, IB_INVALID_QP_HANDLE, cleanup);\r
- if ( E_MARK_QP != hobul_p->qp_info_tbl[qp_idx].mark) {\r
- status = IB_INVALID_QP_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- cl_mutex_acquire(&h_qp->mutex);\r
-\r
- if (HH_OK != THH_hob_query_qp(hobul_p->hh_hndl, h_qp->qp_num, &hh_qp_attr)) {\r
- status = IB_ERROR;\r
- goto cleanup_locked;\r
- }\r
-\r
- // Convert query result into IBAL structure (no cl_memset())\r
- mlnx_conv_vapi_qp_attr(hobul_p->hh_hndl, &hh_qp_attr, p_qp_attr);\r
- p_qp_attr->qp_type = h_qp->qp_type;\r
- p_qp_attr->h_pd = (ib_pd_handle_t)PD_HNDL_FROM_PD(h_qp->pd_num);\r
- p_qp_attr->h_sq_cq = h_qp->h_sq_cq;\r
- p_qp_attr->h_rq_cq = h_qp->h_rq_cq;\r
- p_qp_attr->sq_signaled = h_qp->sq_signaled;\r
-\r
- cl_mutex_release(&h_qp->mutex);\r
-\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = IB_SUCCESS;\r
- }\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup_locked:\r
- cl_mutex_release(&hobul_p->qp_info_tbl[qp_idx].mutex);\r
-cleanup:\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = status;\r
- }\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_destroy_qp (\r
- IN const ib_qp_handle_t h_qp,\r
- IN const uint64_t timewait )\r
-{\r
- ib_api_status_t status;\r
-\r
- u_int32_t hca_idx = QP_HCA_FROM_HNDL(h_qp);\r
- u_int32_t qp_num = QP_NUM_FROM_HNDL(h_qp);\r
- u_int32_t pd_idx = 0;\r
- u_int32_t qp_idx = 0;\r
- mlnx_hobul_t *hobul_p;\r
- HHUL_qp_hndl_t hhul_qp_hndl;\r
-\r
- UNUSED_PARAM( timewait );\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("hca %d qp 0x%x\n", hca_idx, qp_num));\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_CA_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_QP_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- qp_idx = qp_num & hobul_p->qp_idx_mask;\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("hobul_p 0x%p mask 0x%x qp_idx 0x%x mark %d\n",\r
- hobul_p, hobul_p->qp_idx_mask, qp_idx, hobul_p->qp_info_tbl[qp_idx].mark));\r
-\r
- VALIDATE_INDEX(qp_idx, hobul_p->max_qp, IB_INVALID_QP_HANDLE, cleanup);\r
- if ( E_MARK_QP != hobul_p->qp_info_tbl[qp_idx].mark) {\r
- if (E_MARK_INVALID == hobul_p->qp_info_tbl[qp_idx].mark) {\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status IB_INVALID_QP_HANDLE\n"));\r
- return IB_SUCCESS; // Already freed\r
- }\r
- status = IB_INVALID_QP_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- cl_mutex_acquire(&hobul_p->qp_info_tbl[qp_idx].mutex);\r
-\r
- hhul_qp_hndl = hobul_p->qp_info_tbl[qp_idx].hhul_qp_hndl;\r
- pd_idx = hobul_p->qp_info_tbl[qp_idx].pd_num;\r
- VALIDATE_INDEX(pd_idx, hobul_p->max_pd, IB_ERROR, cleanup_locked);\r
-\r
- if (E_MARK_PD != hobul_p->pd_info_tbl[pd_idx].mark) {\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("file %s line %d\n", __FILE__, __LINE__));\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("pd_idx 0x%x mark %d\n", pd_idx, hobul_p->pd_info_tbl[pd_idx].mark));\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup_locked;\r
- }\r
-\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, \r
- ("Before THH_destroy qp_idx 0x%x k_mod %d pd_idx 0x%x\n",\r
- qp_idx, hobul_p->qp_info_tbl[qp_idx].kernel_mode, pd_idx));\r
-\r
- // PREP: no PREP required for destroy_qp\r
- if (HH_OK != THH_hob_destroy_qp(hobul_p->hh_hndl, qp_num)) {\r
- status = IB_ERROR;\r
- goto cleanup_locked;\r
- }\r
-\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, \r
- ("After THH_destroy qp_idx 0x%x k_mod %d pd_idx 0x%x\n",\r
- qp_idx, hobul_p->qp_info_tbl[qp_idx].kernel_mode, pd_idx));\r
-\r
- if (hobul_p->qp_info_tbl[qp_idx].kernel_mode) {\r
- if (HH_OK != THHUL_qpm_destroy_qp_done(hobul_p->hhul_hndl, hhul_qp_hndl)) {\r
- status = IB_ERROR;\r
- goto cleanup_locked;\r
- }\r
- if (hobul_p->qp_info_tbl[qp_idx].qp_ul_resources_p)\r
- cl_free( hobul_p->qp_info_tbl[qp_idx].qp_ul_resources_p);\r
- if (hobul_p->qp_info_tbl[qp_idx].send_sge_p)\r
- cl_free( hobul_p->qp_info_tbl[qp_idx].send_sge_p);\r
- if (hobul_p->qp_info_tbl[qp_idx].recv_sge_p)\r
- cl_free( hobul_p->qp_info_tbl[qp_idx].recv_sge_p);\r
- }\r
-\r
- if( h_qp->qp_type == IB_QPT_QP0 || h_qp->qp_type == IB_QPT_QP1 )\r
- {\r
- if( !cl_atomic_dec( &h_qp->h_sq_cq->spl_qp_cnt ) )\r
- KeSetImportanceDpc( &h_qp->h_sq_cq->dpc, MediumImportance );\r
- if( !cl_atomic_dec( &h_qp->h_rq_cq->spl_qp_cnt ) )\r
- KeSetImportanceDpc( &h_qp->h_rq_cq->dpc, MediumImportance );\r
- }\r
-\r
- hobul_p->qp_info_tbl[qp_idx].mark = E_MARK_INVALID;\r
- hobul_p->qp_info_tbl[qp_idx].qp_ul_resources_p = NULL;\r
- cl_mutex_release(&hobul_p->qp_info_tbl[qp_idx].mutex);\r
-\r
- // Update PD object count\r
- cl_atomic_dec(&hobul_p->pd_info_tbl[pd_idx].count);\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("pd %d count %d\n", pd_idx, hobul_p->pd_info_tbl[pd_idx].count));\r
-\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup_locked:\r
- cl_mutex_release(&hobul_p->qp_info_tbl[qp_idx].mutex);\r
-cleanup:\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-/*\r
-* Completion Queue Managment Verbs.\r
-*/\r
-\r
-ib_api_status_t\r
-mlnx_create_cq (\r
- IN const ib_ca_handle_t h_ca,\r
- IN const void *cq_context,\r
- IN OUT uint32_t *p_size,\r
- OUT ib_cq_handle_t *ph_cq,\r
- IN OUT ci_umv_buf_t *p_umv_buf )\r
-{\r
- ib_api_status_t status;\r
-\r
- mlnx_hob_t *hob_p;\r
- u_int32_t cq_idx;\r
- u_int32_t cq_num;\r
- u_int32_t cq_size = 0;\r
- mlnx_hobul_t *hobul_p;\r
- HH_hca_dev_t *hca_ul_info;\r
- HHUL_cq_hndl_t hhul_cq_hndl = NULL;\r
- void *cq_ul_resources_p = NULL;\r
- MOSAL_protection_ctx_t prot_ctx;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- if( p_umv_buf )\r
- hob_p = ((mlnx_um_ca_t *)h_ca)->hob_p;\r
- else\r
- hob_p = (mlnx_hob_t *)h_ca;\r
-\r
- hobul_p = mlnx_hobs_get_hobul(hob_p);\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_CA_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- hca_ul_info = (HH_hca_dev_t *)hobul_p->hh_hndl;\r
- if (NULL == hca_ul_info) {\r
- status = IB_INVALID_PD_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- // The size must be provided\r
- if (!p_size) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
- // TBD: verify that the number requested does not exceed to maximum allowed\r
-\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- // For user mode calls - obtain and verify the vendor information\r
- if ((p_umv_buf->input_size - sizeof (u_int32_t)) != \r
- hca_ul_info->cq_ul_resources_sz ||\r
- NULL == p_umv_buf->p_inout_buf) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
- cq_ul_resources_p = (void *)p_umv_buf->p_inout_buf;\r
-\r
- /* get the current protection context */ \r
- prot_ctx = MOSAL_get_current_prot_ctx();\r
- } else {\r
- // for kernel mode calls - allocate app resources. Use prep->call->done sequence\r
- cq_ul_resources_p = cl_zalloc( hca_ul_info->cq_ul_resources_sz);\r
- if (!cq_ul_resources_p) {\r
- status = IB_INSUFFICIENT_MEMORY;\r
- goto cleanup;\r
- }\r
- if (HH_OK != THHUL_cqm_create_cq_prep(hobul_p->hhul_hndl, *p_size, &hhul_cq_hndl, &cq_size, cq_ul_resources_p)) {\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
- /* get the current protection context */ \r
- prot_ctx = MOSAL_get_kernel_prot_ctx();\r
- }\r
-\r
- // Allocate the CQ (cmdif)\r
- if (HH_OK != THH_hob_create_cq(hobul_p->hh_hndl, prot_ctx, cq_ul_resources_p, &cq_num)) {\r
- status = IB_INSUFFICIENT_RESOURCES;\r
- goto cleanup_cq;\r
- }\r
-\r
- if( !(p_umv_buf && p_umv_buf->command) )\r
- {\r
- // Manage user level resources\r
- if (HH_OK != THHUL_cqm_create_cq_done(hobul_p->hhul_hndl, hhul_cq_hndl, cq_num, cq_ul_resources_p)) {\r
- THH_hob_destroy_cq(hobul_p->hh_hndl, cq_num);\r
- status = IB_ERROR;\r
- goto cleanup_cq;\r
- }\r
- }\r
-\r
- // Save data refs for future use\r
- cq_idx = cq_num & hobul_p->cq_idx_mask;\r
- VALIDATE_INDEX(cq_idx, hobul_p->max_cq, IB_ERROR, cleanup_cq);\r
- cl_mutex_acquire(&hobul_p->cq_info_tbl[cq_idx].mutex);\r
- hobul_p->cq_info_tbl[cq_idx].hca_idx = hob_p->index;\r
- hobul_p->cq_info_tbl[cq_idx].cq_num = cq_num;\r
-// hobul_p->cq_info_tbl[cq_idx].pd_num = pd_idx;\r
- hobul_p->cq_info_tbl[cq_idx].hhul_cq_hndl = hhul_cq_hndl;\r
- hobul_p->cq_info_tbl[cq_idx].cq_context = cq_context;\r
- hobul_p->cq_info_tbl[cq_idx].cq_ul_resources_p = cq_ul_resources_p;\r
- hobul_p->cq_info_tbl[cq_idx].kernel_mode = !(p_umv_buf && p_umv_buf->command);\r
- hobul_p->cq_info_tbl[cq_idx].mark = E_MARK_CQ;\r
- cl_mutex_release(&hobul_p->cq_info_tbl[cq_idx].mutex);\r
-\r
- // Update CA object count\r
- cl_atomic_inc(&hobul_p->count);\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("HCA %d count %d\n", h_ca->index, hobul_p->count));\r
-\r
- *p_size = cq_size;\r
- if (ph_cq) *ph_cq = (ib_cq_handle_t)CQ_HNDL_FROM_CQ(cq_idx);\r
-\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = p_umv_buf->input_size;\r
- p_umv_buf->status = IB_SUCCESS;\r
- /* \r
- * Copy the cq_idx back to user\r
- */\r
- cl_memcpy (((uint8_t* __ptr64)p_umv_buf->p_inout_buf + hca_ul_info->cq_ul_resources_sz),\r
- &cq_num, sizeof (cq_num));\r
- }\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup_cq:\r
- THHUL_cqm_destroy_cq_done(hobul_p->hhul_hndl, hhul_cq_hndl);\r
-\r
-cleanup:\r
- if( !(p_umv_buf && p_umv_buf->command) && cq_ul_resources_p )\r
- cl_free( cq_ul_resources_p);\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = status;\r
- }\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_resize_cq (\r
- IN const ib_cq_handle_t h_cq,\r
- IN OUT uint32_t *p_size,\r
- IN OUT ci_umv_buf_t *p_umv_buf )\r
-{\r
- ib_api_status_t status;\r
-\r
- u_int32_t hca_idx = CQ_HCA_FROM_HNDL(h_cq);\r
- u_int32_t cq_num = CQ_NUM_FROM_HNDL(h_cq);\r
- u_int32_t cq_idx;\r
- mlnx_hobul_t *hobul_p;\r
-\r
- HHUL_cq_hndl_t hhul_cq_hndl;\r
- void *cq_ul_resources_p = NULL;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- if (!p_size) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_CQ_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_CQ_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- cq_idx = cq_num & hobul_p->cq_idx_mask;\r
- VALIDATE_INDEX(cq_idx, hobul_p->max_cq, IB_INVALID_CQ_HANDLE, cleanup);\r
- if ( E_MARK_CQ != hobul_p->cq_info_tbl[cq_idx].mark) {\r
- status = IB_INVALID_CQ_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- cl_mutex_acquire(&hobul_p->cq_info_tbl[cq_idx].mutex);\r
-\r
- hhul_cq_hndl = hobul_p->cq_info_tbl[cq_idx].hhul_cq_hndl;\r
-\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- // For user mode calls - obtain and verify the vendor information\r
- if( p_umv_buf->input_size != hobul_p->cq_ul_resources_sz ||\r
- NULL == p_umv_buf->p_inout_buf )\r
- {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup_locked;\r
- }\r
- cq_ul_resources_p = (void *)p_umv_buf->p_inout_buf;\r
-\r
- } else {\r
- // for kernel mode calls - obtain the saved app resources. Use prep->call->done sequence\r
- cq_ul_resources_p = hobul_p->cq_info_tbl[cq_idx].cq_ul_resources_p;\r
-\r
- status = THHUL_cqm_resize_cq_prep(\r
- hobul_p->hhul_hndl, hhul_cq_hndl,\r
- *p_size, p_size, cq_ul_resources_p );\r
- if( status != IB_SUCCESS )\r
- goto cleanup_locked;\r
- }\r
-\r
- if (HH_OK != THH_hob_resize_cq(hobul_p->hh_hndl, cq_num, cq_ul_resources_p)) {\r
- status = IB_ERROR;\r
- goto cleanup_locked;\r
- }\r
-\r
- // DONE: when called on behalf of kernel module\r
- if (hobul_p->cq_info_tbl[cq_idx].kernel_mode) {\r
- if (HH_OK != THHUL_cqm_resize_cq_done( hobul_p->hhul_hndl, hhul_cq_hndl, cq_ul_resources_p))\r
- {\r
- status = IB_ERROR;\r
- goto cleanup_locked;\r
- }\r
- }\r
-\r
- cl_mutex_release(&hobul_p->cq_info_tbl[cq_idx].mutex);\r
-\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = p_umv_buf->input_size;\r
- p_umv_buf->status = IB_SUCCESS;\r
- }\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup_locked:\r
- cl_mutex_release(&hobul_p->cq_info_tbl[cq_idx].mutex);\r
-\r
-cleanup:\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = status;\r
- }\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_query_cq (\r
- IN const ib_cq_handle_t h_cq,\r
- OUT uint32_t *p_size,\r
- IN OUT ci_umv_buf_t *p_umv_buf )\r
-{\r
- ib_api_status_t status;\r
-\r
- u_int32_t hca_idx = CQ_HCA_FROM_HNDL(h_cq);\r
- u_int32_t cq_num = CQ_NUM_FROM_HNDL(h_cq);\r
- u_int32_t cq_idx;\r
- mlnx_hobul_t *hobul_p;\r
- HHUL_cq_hndl_t hhul_cq_hndl;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- if (!p_size) {\r
- status = IB_INVALID_PARAMETER;\r
- goto cleanup;\r
- }\r
-\r
- /* Query is fully handled in user-mode. */\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- status = IB_INVALID_CQ_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_CQ_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_CQ_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- cq_idx = cq_num & hobul_p->cq_idx_mask;\r
- VALIDATE_INDEX(cq_idx, hobul_p->max_cq, IB_INVALID_CQ_HANDLE, cleanup);\r
- if ( E_MARK_CQ != hobul_p->cq_info_tbl[cq_idx].mark) {\r
- status = IB_INVALID_CQ_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- cl_mutex_acquire(&hobul_p->cq_info_tbl[cq_idx].mutex);\r
-\r
- hhul_cq_hndl = hobul_p->cq_info_tbl[cq_idx].hhul_cq_hndl;\r
- if (HH_OK != THHUL_cqm_query_cq(hobul_p->hhul_hndl, hhul_cq_hndl, p_size)){\r
- status = IB_ERROR;\r
- goto cleanup_locked;\r
- }\r
-\r
- cl_mutex_release(&hobul_p->cq_info_tbl[cq_idx].mutex);\r
-\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup_locked:\r
- cl_mutex_release(&hobul_p->cq_info_tbl[cq_idx].mutex);\r
-\r
-cleanup:\r
- if( p_umv_buf && p_umv_buf->command )\r
- {\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = status;\r
- }\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_destroy_cq (\r
- IN const ib_cq_handle_t h_cq)\r
-{\r
- ib_api_status_t status;\r
-\r
- u_int32_t hca_idx = CQ_HCA_FROM_HNDL(h_cq);\r
- u_int32_t cq_num = CQ_NUM_FROM_HNDL(h_cq);\r
- u_int32_t cq_idx;\r
-// u_int32_t pd_idx = 0;\r
- mlnx_hobul_t *hobul_p;\r
- HHUL_cq_hndl_t hhul_cq_hndl;\r
-\r
- CL_ENTER(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
-\r
- VALIDATE_INDEX(hca_idx, MLNX_MAX_HCA, IB_INVALID_CQ_HANDLE, cleanup);\r
- hobul_p = mlnx_hobul_array[hca_idx];\r
- if (NULL == hobul_p) {\r
- status = IB_INVALID_CQ_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- cq_idx = cq_num & hobul_p->cq_idx_mask;\r
- VALIDATE_INDEX(cq_idx, hobul_p->max_cq, IB_INVALID_CQ_HANDLE, cleanup);\r
- if ( E_MARK_CQ != hobul_p->cq_info_tbl[cq_idx].mark) {\r
- status = IB_INVALID_CQ_HANDLE;\r
- goto cleanup;\r
- }\r
-\r
- cl_mutex_acquire(&hobul_p->cq_info_tbl[cq_idx].mutex);\r
-\r
- hhul_cq_hndl = hobul_p->cq_info_tbl[cq_idx].hhul_cq_hndl;\r
-// pd_idx = hobul_p->cq_info_tbl[cq_idx].pd_num;\r
-// VALIDATE_INDEX(pd_idx, hobul_p->max_pd, IB_ERROR, cleanup);\r
-// if (E_MARK_PD != hobul_p->pd_info_tbl[pd_idx].mark) {\r
-// status = IB_INVALID_PD_HANDLE;\r
-// goto cleanup_locked;\r
-// }\r
-\r
- // PREP: no PREP required for destroy_cq\r
- if (HH_OK != THH_hob_destroy_cq(hobul_p->hh_hndl, cq_num)) {\r
- status = IB_ERROR;\r
- goto cleanup_locked;\r
- }\r
-\r
- if (hobul_p->cq_info_tbl[cq_idx].kernel_mode) {\r
- if (HH_OK != THHUL_cqm_destroy_cq_done(hobul_p->hhul_hndl, hhul_cq_hndl)) {\r
- status = IB_ERROR;\r
- goto cleanup_locked;\r
- }\r
- if (hobul_p->cq_info_tbl[cq_idx].cq_ul_resources_p)\r
- cl_free( hobul_p->cq_info_tbl[cq_idx].cq_ul_resources_p);\r
- }\r
-\r
- hobul_p->cq_info_tbl[cq_idx].mark = E_MARK_INVALID;\r
- hobul_p->cq_info_tbl[cq_idx].cq_ul_resources_p = NULL;\r
- cl_mutex_release(&hobul_p->cq_info_tbl[cq_idx].mutex);\r
-\r
- // Update CA object count\r
- cl_atomic_dec(&hobul_p->count);\r
- CL_TRACE(MLNX_DBG_INFO, g_mlnx_dbg_lvl, ("CA %d count %d\n", hca_idx, hobul_p->count));\r
-\r
-\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return IB_SUCCESS;\r
-\r
-cleanup_locked:\r
- cl_mutex_release(&hobul_p->cq_info_tbl[cq_idx].mutex);\r
-\r
-cleanup:\r
- CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- CL_EXIT(MLNX_DBG_TRACE, g_mlnx_dbg_lvl);\r
- return status;\r
-}\r
-\r
-\r
-void\r
-setup_ci_interface(\r
- IN const ib_net64_t ca_guid,\r
- IN OUT ci_interface_t *p_interface )\r
-{\r
- cl_memclr(p_interface, sizeof(*p_interface));\r
-\r
- /* Guid of the CA. */\r
- p_interface->guid = ca_guid;\r
-\r
- /* Version of this interface. */\r
- p_interface->version = VERBS_VERSION;\r
-\r
- /* UVP name */\r
- cl_memcpy( p_interface->libname, mlnx_uvp_lib_name, MAX_LIB_NAME);\r
-\r
- CL_TRACE(MLNX_DBG_TRACE, g_mlnx_dbg_lvl, ("UVP filename %s\n", p_interface->libname)); \r
-\r
- /* The real interface. */\r
- p_interface->open_ca = mlnx_open_ca;\r
- p_interface->query_ca = mlnx_query_ca;\r
- p_interface->modify_ca = mlnx_modify_ca; // ++\r
- p_interface->close_ca = mlnx_close_ca;\r
- p_interface->um_open_ca = mlnx_um_open;\r
- p_interface->um_close_ca = mlnx_um_close;\r
-\r
- p_interface->allocate_pd = mlnx_allocate_pd;\r
- p_interface->deallocate_pd = mlnx_deallocate_pd;\r
-\r
- p_interface->create_av = mlnx_create_av;\r
- p_interface->query_av = mlnx_query_av;\r
- p_interface->modify_av = mlnx_modify_av;\r
- p_interface->destroy_av = mlnx_destroy_av;\r
-\r
- p_interface->create_qp = mlnx_create_qp;\r
- p_interface->create_spl_qp = mlnx_create_spl_qp;\r
- p_interface->modify_qp = mlnx_modify_qp;\r
- p_interface->query_qp = mlnx_query_qp;\r
- p_interface->destroy_qp = mlnx_destroy_qp;\r
-\r
- p_interface->create_cq = mlnx_create_cq;\r
- p_interface->resize_cq = mlnx_resize_cq;\r
- p_interface->query_cq = mlnx_query_cq;\r
- p_interface->destroy_cq = mlnx_destroy_cq;\r
-\r
- p_interface->local_mad = mlnx_local_mad;\r
- \r
- p_interface->vendor_call = fw_access_ctrl;\r
-\r
- mlnx_memory_if(p_interface);\r
- mlnx_direct_if(p_interface);\r
- mlnx_mcast_if(p_interface);\r
-\r
-\r
- return;\r
-}\r
-\r
-#if 0\r
-CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("file %s line %d\n", __FILE__, __LINE__));\r
-#endif\r
-; Mellanox Technologies InfiniBand HCAs.\r
-; Copyright 2005 SilverStorm Technologies all Rights Reserved.\r
-\r
-[Version]\r
-Signature="$Windows NT$"\r
-Class=InfiniBandHca\r
-ClassGUID={58517E00-D3CF-40c9-A679-CEE5752F4491}\r
-Provider=%OPENIB%\r
-DriverVer=03/08/2006,1.0.0000.614\r
-\r
-; ================= Destination directory section =====================\r
-\r
-[DestinationDirs]\r
-DefaultDestDir=%DIRID_DRIVERS%\r
-ClassCopyFiles=%DIRID_SYSTEM%\r
-MT23108.UMCopyFiles=%DIRID_SYSTEM%\r
-MT23108.WOW64CopyFiles=%DIRID_SYSTEM_X86%\r
-\r
-; ================= Class Install section =====================\r
-\r
-[ClassInstall32]\r
-CopyFiles=ClassCopyFiles\r
-AddReg=ClassAddReg\r
-\r
-[ClassCopyFiles]\r
-IbInstaller.dll\r
-\r
-[ClassAddReg]\r
-HKR,,,,"InfiniBand Host Channel Adapters"\r
-HKR,,Icon,,-5\r
-HKR,,SilentInstall,,1\r
-HKLM,"System\CurrentControlSet\Control\CoDeviceInstallers", \\r
- {58517E00-D3CF-40c9-A679-CEE5752F4491},%REG_MULTI_SZ_APPEND%, \\r
- "IbInstaller.dll,IbCoInstaller"\r
-\r
-; ================= Device Install section =====================\r
-\r
-[SourceDisksNames.x86]\r
-1=%DiskId%,,,\x86\r
-\r
-[SourceDisksNames.amd64]\r
-1=%DiskId%,,,\amd64\r
-\r
-[SourceDisksNames.ia64]\r
-1=%DiskId%,,,\ia64\r
-\r
-[SourceDisksFiles]\r
-IbInstaller.dll=1\r
-mt23108.sys=1\r
-thca.sys=1\r
-mt23108u.dll=1\r
-mt23108ud.dll=1\r
-\r
-[SourceDisksFiles.amd64]\r
-IbInstaller.dll=1\r
-mt23108.sys=1\r
-thca.sys=1\r
-mt23108u.dll=1\r
-mt23108ud.dll=1\r
-mtuvp32.dll=1\r
-mtuvp32d.dll=1\r
-\r
-[SourceDisksFiles.ia64]\r
-IbInstaller.dll=1\r
-ibal.sys=1\r
-mt23108.sys=1\r
-thca.sys=1\r
-mt23108u.dll=1\r
-mt23108ud.dll=1\r
-mtuvp32.dll=1\r
-mtuvp32d.dll=1\r
-\r
-[Manufacturer]\r
-%MTL% = HCA.DeviceSection,ntx86,ntamd64,ntia64\r
-\r
-[HCA.DeviceSection]\r
-; empty since we don't support W9x/Me\r
-\r
-[HCA.DeviceSection.ntx86]\r
-%MT23108.DeviceDesc% = MT23108.DDInstall,PCI\VEN_15B3&DEV_5A44\r
-%MT25208.DeviceDesc% = MT23108.DDInstall,PCI\VEN_15B3&DEV_6278\r
-\r
-[HCA.DeviceSection.ntamd64]\r
-%MT23108.DeviceDesc% = MT23108.DDInstall,PCI\VEN_15B3&DEV_5A44\r
-%MT25208.DeviceDesc% = MT23108.DDInstall,PCI\VEN_15B3&DEV_6278\r
-\r
-[HCA.DeviceSection.ntia64]\r
-%MT23108.DeviceDesc% = MT23108.DDInstall,PCI\VEN_15B3&DEV_5A44\r
-%MT25208.DeviceDesc% = MT23108.DDInstall,PCI\VEN_15B3&DEV_6278\r
-\r
-[MT23108.DDInstall.ntx86]\r
-CopyFiles = MT23108.CopyFiles\r
-CopyFiles = MT23108.UMCopyFiles\r
-\r
-[MT23108.DDInstall.ntamd64]\r
-CopyFiles = MT23108.CopyFiles\r
-CopyFiles = MT23108.UMCopyFiles\r
-CopyFiles = MT23108.WOW64CopyFiles\r
-\r
-[MT23108.DDInstall.ntia64]\r
-CopyFiles = MT23108.CopyFiles\r
-CopyFiles = MT23108.UMCopyFiles\r
-CopyFiles = MT23108.WOW64CopyFiles\r
-\r
-[MT23108.DDInstall.ntx86.HW]\r
-AddReg = MT23108.FiltersReg\r
-\r
-[MT23108.DDInstall.ntamd64.HW]\r
-AddReg = MT23108.FiltersReg\r
-\r
-[MT23108.DDInstall.ntia64.HW]\r
-AddReg = MT23108.FiltersReg\r
-\r
-[MT23108.DDInstall.ntx86.Services]\r
-AddService = thca,%SPSVCINST_NULL%,THCA.ServiceInstall\r
-AddService = mt23108,%SPSVCINST_ASSOCSERVICE%,MT23108.ServiceInstall\r
-\r
-[MT23108.DDInstall.ntamd64.Services]\r
-AddService = thca,%SPSVCINST_NULL%,THCA.ServiceInstall\r
-AddService = mt23108,%SPSVCINST_ASSOCSERVICE%,MT23108.ServiceInstall\r
-\r
-[MT23108.DDInstall.ntia64.Services]\r
-AddService = thca,%SPSVCINST_NULL%,THCA.ServiceInstall\r
-AddService = mt23108,%SPSVCINST_ASSOCSERVICE%,MT23108.ServiceInstall\r
-\r
-[MT23108.CopyFiles]\r
-mt23108.sys\r
-thca.sys\r
-\r
-[MT23108.UMCopyFiles]\r
-mt23108u.dll,,,2\r
-mt23108ud.dll,,,2\r
-\r
-[MT23108.WOW64CopyFiles]\r
-mt23108u.dll,mtuvp32.dll,,2\r
-mt23108ud.dll,mtuvp32d.dll,,2\r
-\r
-;\r
-; ============= Service Install section ==============\r
-;\r
-\r
-[MT23108.ServiceInstall]\r
-DisplayName = %MT23108.ServiceDesc%\r
-ServiceType = %SERVICE_KERNEL_DRIVER%\r
-StartType = %SERVICE_DEMAND_START%\r
-ErrorControl = %SERVICE_ERROR_NORMAL%\r
-ServiceBinary = %12%\mt23108.sys\r
-LoadOrderGroup = extended base\r
-AddReg = MT23108.ParamsReg\r
-\r
-[THCA.ServiceInstall]\r
-DisplayName = %THCA.ServiceDesc%\r
-ServiceType = %SERVICE_KERNEL_DRIVER%\r
-StartType = %SERVICE_DEMAND_START%\r
-ErrorControl = %SERVICE_ERROR_NORMAL%\r
-ServiceBinary = %12%\thca.sys\r
-LoadOrderGroup = extended base\r
-AddReg = THCA.ParamsReg\r
-\r
-[MT23108.FiltersReg]\r
-HKR,,"UpperFilters", 0x00010000,"thca"\r
-\r
-[MT23108.ParamsReg]\r
-HKR,"Parameters","DebugLevel",%REG_DWORD%,2\r
-HKR,"Parameters","ConfAddr",%REG_DWORD%,88\r
-HKR,"Parameters","ConfData",%REG_DWORD%,92\r
-HKR,"Parameters","DdrMapOffset",%REG_DWORD%,0x100000\r
-HKR,"Parameters","DdrMapSize",%REG_DWORD%,0x1600000\r
-HKR,"Parameters","ResetCard",%REG_DWORD%,0\r
-\r
-[THCA.ParamsReg]\r
-HKR,"Parameters","DebugFlags",%REG_DWORD%,0x80000000\r
-\r
-[Strings]\r
-OPENIB = "OpenIB Alliance"\r
-MTL = "Mellanox Technologies Ltd."\r
-MT23108.ServiceDesc = "Mellanox MT23108 InfiniBand HCA Driver"\r
-MT23108.DeviceDesc = "InfiniHost (MT23108) - Mellanox InfiniBand HCA [MT23108 Driver]"\r
-MT25208.DeviceDesc = "InfiniHost (MT25208) - Mellanox InfiniBand HCA for PCI Express [MT23108 Driver]"\r
-THCA.ServiceDesc = "Mellanox HCA VPD for IBAL"\r
-DiskId = "OpenIB InfiniBand HCA installation disk"\r
-SPSVCINST_NULL = 0x0\r
-SPSVCINST_ASSOCSERVICE = 0x00000002\r
-SERVICE_KERNEL_DRIVER = 1\r
-SERVICE_DEMAND_START = 3\r
-SERVICE_ERROR_NORMAL = 1\r
-REG_DWORD = 0x00010001\r
-REG_MULTI_SZ_APPEND = 0x00010008\r
-DIRID_SYSTEM = 11\r
-DIRID_DRIVERS = 12\r
-DIRID_SYSTEM_X86 = 16425\r
-#\r
-# DO NOT EDIT THIS FILE!!! Edit .\sources. if you want to add a new source\r
-# file to this component. This file merely indirects to the real make file\r
-# that is shared by all the driver components of the OpenIB Windows project.\r
-#\r
-\r
-!INCLUDE ..\..\..\inc\openib.def\r
-!if $(FREEBUILD)\r
-TARGETNAME=mt23108u\r
-!else\r
-TARGETNAME=mt23108ud\r
-!endif\r
-TARGETPATH=..\..\..\bin\user\obj$(BUILD_ALT_DIR)\r
-TARGETTYPE=DYNLINK\r
-DLLDEF=$(O)\uvpd_exports.def\r
-USE_NTDLL=1\r
-DLLENTRY=DllMain\r
-\r
-SOURCES= \\r
- uvpd.rc \\r
- mlnx_ual_av.c \\r
- mlnx_ual_ca.c \\r
- mlnx_ual_cq.c \\r
- mlnx_ual_main.c \\r
- mlnx_ual_mcast.c \\r
- mlnx_ual_mrw.c \\r
- mlnx_ual_osbypass.c \\r
- mlnx_ual_pd.c \\r
- mlnx_ual_qp.c\r
-\r
-MT_HOME=..\vapi\r
-\r
-INCLUDES= \\r
- .\; \\r
- ..\..\..\inc; \\r
- ..\..\..\inc\user; \\r
- $(MT_HOME)\mlxsys\tools; \\r
- $(MT_HOME)\Hca\verbs; \\r
- $(MT_HOME)\Hca\hcahal; \\r
- $(MT_HOME)\mlxsys\mtl_common; \\r
- $(MT_HOME)\mlxsys\mtl_common\os_dep\win; \\r
- $(MT_HOME)\mlxsys\mosal; \\r
- $(MT_HOME)\mlxsys\mosal\os_dep\win; \\r
- $(MT_HOME)\mlxsys\mtl_types; \\r
- $(MT_HOME)\mlxsys\mtl_types\win; \\r
- $(MT_HOME)\mlxsys\mtl_types\win\win; \\r
- $(MT_HOME)\mlxsys\mtl_types\win\win32; \\r
- $(MT_HOME)\Hca\hcahal\tavor; \\r
- $(MT_HOME)\Hca\hcahal\tavor\util; \\r
- $(MT_HOME)\Hca\hcahal\tavor\thhul_hob; \\r
- $(MT_HOME)\Hca\hcahal\tavor\thhul_pdm; \\r
- $(MT_HOME)\Hca\hcahal\tavor\thhul_cqm; \\r
- $(MT_HOME)\Hca\hcahal\tavor\thhul_qpm; \\r
- $(MT_HOME)\Hca\hcahal\tavor\thhul_mwm;\r
-\r
-USER_C_FLAGS=$(USER_C_FLAGS) /DIVAPI_THH /DCL_NO_TRACK_MEM\r
-\r
-TARGETLIBS=\\r
- $(TARGETPATH)\*\vapi.lib \\r
- $(SDK_LIB_PATH)\user32.lib \\r
- $(SDK_LIB_PATH)\kernel32.lib \\r
-!if $(FREEBUILD)\r
- $(TARGETPATH)\*\complib.lib \\r
- $(TARGETPATH)\*\ibal.lib\r
-!else\r
- $(TARGETPATH)\*\complibd.lib \\r
- $(TARGETPATH)\*\ibald.lib\r
-!endif\r
-\r
-MSC_WARNING_LEVEL= /W3\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include <iba/ib_types.h>\r
-#include <iba/ib_uvp.h>\r
-\r
-\r
-typedef struct _ib_ca\r
-{\r
- HH_hca_dev_t * __ptr64 p_hca_ul_info;\r
- void *p_hca_ul_resources;\r
- ib_ca_attr_t *p_hca_attr;\r
- HHUL_hca_hndl_t hhul_hca_hndl;\r
- u_int32_t priv_op;\r
- void *p_al_ci_ca;\r
-\r
-} mlnx_ual_hobul_t;\r
-\r
-\r
-typedef struct _ib_pd\r
-{\r
- mlnx_ual_hobul_t *p_hobul;\r
- void *p_pd_ul_resources;\r
- HHUL_pd_hndl_t hhul_pd_hndl;\r
- u_int32_t pd_idx;\r
-\r
-#define MLNX_MAX_AVS_PER_PD 0xFFFFFFFF\r
-\r
-} mlnx_ual_pd_info_t;\r
-\r
-\r
-typedef struct _ib_cq\r
-{\r
- mlnx_ual_hobul_t *p_hobul; \r
- void *p_cq_ul_resources;\r
- HHUL_cq_hndl_t hhul_cq_hndl;\r
- u_int32_t cq_idx;\r
- u_int32_t cq_size;\r
-\r
-} mlnx_ual_cq_info_t;\r
-\r
-\r
-typedef struct _ib_qp\r
-{\r
- ib_pd_handle_t h_uvp_pd; \r
- void *p_qp_ul_resources;\r
- HHUL_qp_hndl_t hhul_qp_hndl;\r
- u_int32_t qp_idx;\r
- VAPI_qp_cap_t ul_qp_cap;\r
- IB_ts_t type;\r
-\r
-} mlnx_ual_qp_info_t;\r
-\r
-\r
-typedef struct _ib_mw\r
-{\r
- ib_pd_handle_t h_uvp_pd; \r
- u_int32_t rkey;\r
- HHUL_mw_hndl_t hhul_mw_hndl;\r
-\r
-} mlnx_ual_mw_info_t;\r
-\r
-\r
-typedef struct _ib_av\r
-{\r
- ib_pd_handle_t h_uvp_pd; \r
- ib_av_attr_t *p_i_av_attr;\r
- HHUL_ud_av_hndl_t h_av;\r
-\r
-} mlnx_ual_av_info_t;\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies, Inc. All rights reserved. \r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "mlnx_ual_main.h"\r
-\r
-extern u_int32_t mlnx_dbg_lvl;\r
-\r
-void\r
-mlnx_get_av_interface (\r
- IN OUT uvp_interface_t *p_uvp )\r
-{\r
-\r
- CL_ASSERT(p_uvp);\r
-\r
- /*\r
- * Address Vector Management Verbs\r
- */\r
- p_uvp->pre_create_av = mlnx_pre_create_av;\r
- p_uvp->post_create_av = mlnx_post_create_av;\r
- p_uvp->pre_query_av = mlnx_pre_query_av;\r
- p_uvp->post_query_av = mlnx_post_query_av;\r
- p_uvp->pre_modify_av = mlnx_pre_modify_av;\r
- p_uvp->post_modify_av = mlnx_post_modify_av;\r
- p_uvp->pre_destroy_av = mlnx_pre_destroy_av;\r
- p_uvp->post_destroy_av = mlnx_post_destroy_av;\r
-\r
-}\r
-\r
-\r
-u_int8_t\r
-gid_to_index_lookup (\r
- IN ib_ca_attr_t *p_ca_attr,\r
- IN u_int8_t port_num,\r
- IN u_int8_t *raw_gid)\r
-{\r
- ib_gid_t *p_gid_table = NULL;\r
- u_int8_t i, index = 0;\r
- u_int16_t num_gids;\r
-\r
- p_gid_table = p_ca_attr->p_port_attr[port_num].p_gid_table;\r
- CL_ASSERT (p_gid_table);\r
-\r
- num_gids = p_ca_attr->p_port_attr[port_num].num_gids;\r
- CL_TRACE (MLNX_TRACE_LVL_6, mlnx_dbg_lvl,\r
- ("Port %d has %d gids\n", port_num, num_gids));\r
-\r
- for (i = 0; i < num_gids; i++)\r
- {\r
- if (cl_memcmp (raw_gid, p_gid_table[i].raw, sizeof (ib_gid_t)))\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_6, mlnx_dbg_lvl,\r
- ("found GID at index %d\n", i));\r
- index = i;\r
- break;\r
- }\r
- }\r
- return index;\r
-}\r
-\r
-\r
-void\r
-map_itom_av_attr (\r
- IN ib_ca_attr_t *p_ca_attr,\r
- IN const ib_av_attr_t *p_av_attr,\r
- OUT VAPI_ud_av_t *p_hhul_av)\r
-{\r
- u_int8_t ver;\r
- u_int8_t tclass;\r
- u_int32_t flow_lbl;\r
-\r
- p_hhul_av->sl = p_av_attr->sl;\r
- p_hhul_av->port = p_av_attr->port_num;\r
- p_hhul_av->dlid = CL_NTOH16 (p_av_attr->dlid);\r
- /*\r
- * VAPI uses static rate as IPD.\r
- * 0 is matched links. 3 is suitable for 4x to 1x.\r
- */\r
- p_hhul_av->static_rate =\r
- (p_av_attr->static_rate == IB_PATH_RECORD_RATE_10_GBS? 0 : 3);\r
-\r
- p_hhul_av->src_path_bits = 0;\r
- /* p_hhul_av->src_path_bits = p_av_attr->path_bits; */\r
- CL_TRACE (MLNX_TRACE_LVL_6, mlnx_dbg_lvl,\r
- ("ib_av_attr->path_bits %d\n", p_av_attr->path_bits));\r
- p_hhul_av->grh_flag = (MT_bool)p_av_attr->grh_valid;\r
-\r
- if (p_av_attr->grh_valid)\r
- {\r
- ib_grh_get_ver_class_flow (p_av_attr->grh.ver_class_flow,\r
- &ver, &tclass, &flow_lbl);\r
-\r
- p_hhul_av->hop_limit = p_av_attr->grh.hop_limit;\r
- p_hhul_av->sgid_index = \r
- gid_to_index_lookup (p_ca_attr, \r
- p_av_attr->port_num,\r
- (u_int8_t *) p_av_attr->grh.src_gid.raw); \r
-\r
- cl_memcpy (p_hhul_av->dgid, p_av_attr->grh.dest_gid.raw, \r
- sizeof (IB_gid_t));\r
- \r
- p_hhul_av->traffic_class = tclass;\r
- p_hhul_av->flow_label = flow_lbl;\r
- }\r
-} \r
-\r
-ib_api_status_t\r
-mlnx_pre_create_av (\r
- IN const ib_pd_handle_t h_uvp_pd,\r
- IN const ib_av_attr_t *p_av_attr,\r
- IN OUT ci_umv_buf_t *p_umv_buf,\r
- OUT ib_av_handle_t *ph_uvp_av)\r
-{\r
- ib_api_status_t status = IB_VERBS_PROCESSING_DONE;\r
-\r
- UNREFERENCED_PARAMETER(ph_uvp_av);\r
-\r
- FUNC_ENTER;\r
- CL_ASSERT(p_umv_buf);\r
- /* \r
- * Saving the av_attribute for the post to create the av\r
- */ \r
- p_umv_buf->input_size = p_umv_buf->output_size = sizeof (ib_av_attr_t);\r
- p_umv_buf->p_inout_buf = cl_zalloc (p_umv_buf->input_size);\r
-\r
- if (p_umv_buf->p_inout_buf == NULL)\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("FAILED to create priv buffer\n"));\r
- status = IB_INSUFFICIENT_MEMORY;\r
- goto cleanup;\r
- }\r
- cl_memcpy (p_umv_buf->p_inout_buf, p_av_attr, sizeof (ib_av_attr_t));\r
- /*\r
- * We are going to create the AV entirely in user mode.\r
- * To signal the AL about that we return IB_VERBS_PROCESSING_DONE\r
- */\r
-cleanup:\r
- FUNC_EXIT;\r
- return status;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_create_av (\r
- IN const ib_pd_handle_t h_uvp_pd,\r
- IN ib_api_status_t ioctl_status,\r
- IN OUT ib_av_handle_t *ph_uvp_av,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- ib_api_status_t status;\r
- mlnx_ual_hobul_t *p_hobul;\r
- mlnx_ual_pd_info_t *p_pd_info = (mlnx_ual_pd_info_t *)((void*)h_uvp_pd);\r
- ib_av_attr_t *p_av_attr;\r
- VAPI_ud_av_t hhul_av;\r
- mlnx_ual_av_info_t *p_new_av = NULL;\r
-\r
- FUNC_ENTER;\r
- CL_ASSERT (p_pd_info);\r
- CL_ASSERT (p_umv_buf);\r
-\r
- p_hobul = p_pd_info->p_hobul;\r
- CL_ASSERT (p_hobul);\r
-\r
- /* \r
- * Set initial value for handle \r
- */\r
- *ph_uvp_av = NULL;\r
- \r
- status = ioctl_status;\r
-\r
- if (IB_SUCCESS == status)\r
- {\r
- if (sizeof (ib_av_attr_t) != p_umv_buf->output_size) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Priv buffer has different size\n"));\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
- p_av_attr = (ib_av_attr_t *) p_umv_buf->p_inout_buf;\r
- CL_ASSERT (p_av_attr);\r
-\r
- p_new_av = cl_zalloc (sizeof (mlnx_ual_av_info_t));\r
-\r
- map_itom_av_attr (p_hobul->p_hca_attr, p_av_attr, &hhul_av);\r
-\r
- if (HH_OK != \r
- THHUL_pdm_create_ud_av (p_hobul->hhul_hca_hndl,\r
- p_pd_info->hhul_pd_hndl,\r
- &hhul_av,\r
- &p_new_av->h_av))\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("FAILED to create usermode UD AV\n"));\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
-\r
- p_new_av->p_i_av_attr = p_av_attr;\r
- p_new_av->h_uvp_pd = h_uvp_pd;\r
- *ph_uvp_av = p_new_av;\r
- p_umv_buf->p_inout_buf = NULL;\r
- }\r
-\r
- /* \r
- * clean_up if required\r
- */\r
-cleanup:\r
- if ((IB_SUCCESS != status) && (IB_SUCCESS == ioctl_status))\r
- {\r
- if (p_new_av) \r
- {\r
- if (p_new_av->p_i_av_attr);\r
- {\r
- cl_free (p_new_av->p_i_av_attr);\r
- }\r
- cl_free (p_new_av);\r
- }\r
- }\r
-\r
- FUNC_EXIT;\r
- return;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_query_av (\r
- IN const ib_av_handle_t h_uvp_av,\r
- IN OUT ci_umv_buf_t *p_umv_buf )\r
-{\r
- FUNC_ENTER;\r
- FUNC_EXIT;\r
- return IB_VERBS_PROCESSING_DONE;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_query_av (\r
- IN const ib_av_handle_t h_uvp_av,\r
- IN ib_api_status_t ioctl_status,\r
- IN OUT ib_av_attr_t *p_addr_vector,\r
- IN OUT ib_pd_handle_t *ph_pd,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- ib_api_status_t status;\r
- mlnx_ual_av_info_t *p_av_info = (mlnx_ual_av_info_t *)((void*) h_uvp_av);\r
-\r
- FUNC_ENTER;\r
- CL_ASSERT(p_umv_buf);\r
- CL_ASSERT(p_av_info);\r
-\r
- status = ioctl_status;\r
-\r
- if (status == IB_SUCCESS)\r
- {\r
- cl_memcpy (p_addr_vector, p_av_info->p_i_av_attr, sizeof (ib_av_attr_t));\r
- status = IB_VERBS_PROCESSING_DONE;\r
- }\r
- \r
- FUNC_EXIT;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_modify_av (\r
- IN const ib_av_handle_t h_uvp_av,\r
- IN const ib_av_attr_t *p_addr_vector,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- ib_api_status_t status = IB_VERBS_PROCESSING_DONE;\r
-\r
- mlnx_ual_av_info_t *p_av_info = (mlnx_ual_av_info_t *)((void*) h_uvp_av);\r
- mlnx_ual_pd_info_t *p_pd_info;\r
- mlnx_ual_hobul_t *p_hobul;\r
- VAPI_ud_av_t hhul_av;\r
-\r
- FUNC_ENTER;\r
- CL_ASSERT (p_umv_buf);\r
-\r
- p_pd_info = (mlnx_ual_pd_info_t *)((void*) p_av_info->h_uvp_pd);\r
- CL_ASSERT (p_pd_info);\r
-\r
- p_hobul = p_pd_info->p_hobul;\r
- CL_ASSERT (p_hobul);\r
-\r
- map_itom_av_attr (p_hobul->p_hca_attr, p_addr_vector, &hhul_av);\r
-\r
- if (HH_OK !=\r
- THHUL_pdm_modify_ud_av (p_hobul->hhul_hca_hndl, \r
- p_av_info->h_av,\r
- &hhul_av))\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Failed to modify AV\n"));\r
- status = IB_ERROR;\r
- }\r
- else\r
- {\r
- cl_memcpy (p_av_info->p_i_av_attr, p_addr_vector, sizeof (ib_av_attr_t));\r
- }\r
-\r
- FUNC_EXIT;\r
-\r
- return status;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_modify_av (\r
- IN const ib_av_handle_t h_uvp_av,\r
- IN ib_api_status_t ioctl_status,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- FUNC_ENTER;\r
- FUNC_EXIT;\r
- return;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_destroy_av (\r
- IN const ib_av_handle_t h_uvp_av)\r
-{\r
- FUNC_ENTER;\r
- FUNC_EXIT;\r
- return IB_VERBS_PROCESSING_DONE;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_destroy_av (\r
- IN const ib_av_handle_t h_uvp_av,\r
- IN ib_api_status_t ioctl_status)\r
-{\r
- mlnx_ual_hobul_t *p_hobul;\r
- mlnx_ual_pd_info_t *p_pd_info;\r
- mlnx_ual_av_info_t *p_av_info = (mlnx_ual_av_info_t *)((void*) h_uvp_av);\r
-\r
- FUNC_ENTER;\r
- CL_ASSERT (p_av_info);\r
-\r
- p_pd_info = (mlnx_ual_pd_info_t *)((void*) p_av_info->h_uvp_pd);\r
- CL_ASSERT (p_pd_info);\r
-\r
- p_hobul = p_pd_info->p_hobul;\r
- CL_ASSERT (p_hobul);\r
-\r
- if (HH_OK !=\r
- THHUL_pdm_destroy_ud_av (p_hobul->hhul_hca_hndl,\r
- p_av_info->h_av))\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Failed to destroy av\n"));\r
- }\r
- \r
- /*\r
- * We still have to clean resources even THHUL failed\r
- */ \r
- if (p_av_info->p_i_av_attr);\r
- {\r
- cl_free (p_av_info->p_i_av_attr);\r
- }\r
- cl_free (p_av_info);\r
-\r
- FUNC_EXIT;\r
- return;\r
-}\r
-\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies, Inc. All rights reserved. \r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "mlnx_ual_main.h"\r
-//#include "hca_dev.h"\r
-\r
-extern u_int32_t mlnx_dbg_lvl;\r
-\r
-void\r
-mlnx_get_ca_interface (\r
- IN OUT uvp_interface_t *p_uvp )\r
-{\r
- CL_ASSERT(p_uvp);\r
-\r
- /*\r
- * HCA Access Verbs\r
- */\r
- p_uvp->pre_open_ca = mlnx_pre_open_ca;\r
- p_uvp->post_open_ca = mlnx_post_open_ca;\r
-\r
- \r
- p_uvp->pre_query_ca = mlnx_pre_query_ca;\r
- p_uvp->post_query_ca = mlnx_post_query_ca;\r
-\r
- p_uvp->pre_modify_ca = NULL;\r
- p_uvp->post_modify_ca = NULL;\r
-\r
- p_uvp->pre_close_ca = mlnx_pre_close_ca;\r
- p_uvp->post_close_ca = mlnx_post_close_ca;\r
-\r
-}\r
-\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_open_ca (\r
- IN const ib_net64_t ca_guid,\r
- IN OUT ci_umv_buf_t *p_umv_buf,\r
- OUT ib_ca_handle_t *ph_uvp_ca)\r
-{\r
- UNREFERENCED_PARAMETER(ph_uvp_ca);\r
- \r
- FUNC_ENTER;\r
- if( p_umv_buf )\r
- {\r
- if( !p_umv_buf->p_inout_buf )\r
- {\r
- p_umv_buf->p_inout_buf = cl_zalloc( sizeof(mlnx_ual_hobul_t) );\r
- if( !p_umv_buf->p_inout_buf )\r
- {\r
- return IB_INSUFFICIENT_MEMORY;\r
- }\r
- }\r
- p_umv_buf->input_size = p_umv_buf->output_size = sizeof(mlnx_ual_hobul_t);\r
- p_umv_buf->command = TRUE;\r
- }\r
- FUNC_EXIT;\r
- return IB_SUCCESS;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_post_open_ca (\r
- IN const ib_net64_t ca_guid,\r
- IN ib_api_status_t ioctl_status,\r
- IN OUT ib_ca_handle_t *ph_uvp_ca,\r
- IN ci_umv_buf_t *p_umv_buf )\r
-{\r
- ib_api_status_t status = ioctl_status;\r
- mlnx_ual_hobul_t *new_ca = (mlnx_ual_hobul_t *)p_umv_buf->p_inout_buf;\r
-\r
- FUNC_ENTER;\r
-\r
- if (IB_SUCCESS == status)\r
- {\r
- *ph_uvp_ca = (ib_ca_handle_t)new_ca;\r
-\r
- /*\r
- * hca_ul_info will be intialized now\r
- */\r
- new_ca->p_hca_ul_resources = (new_ca->p_hca_ul_info + 1 );\r
- new_ca->p_hca_attr = NULL;\r
-\r
- /* Create user layer CA Object */\r
- if (HH_OK != \r
- THHUL_hob_create(new_ca->p_hca_ul_resources, \r
- new_ca->p_hca_ul_info->dev_id,\r
- &new_ca->hhul_hca_hndl)) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Failed to create THHUL_hob object\n"));\r
- status = IB_INSUFFICIENT_RESOURCES;\r
- }\r
- }\r
-\r
- /* \r
- * Free resources for ERROR cases\r
- * Clean-up if required\r
- */\r
- if( status != IB_SUCCESS )\r
- cl_free( new_ca );\r
-\r
- FUNC_EXIT;\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_pre_query_ca (\r
- IN ib_ca_handle_t h_uvp_ca,\r
- IN ib_ca_attr_t *p_ca_attr,\r
- IN size_t byte_count,\r
- IN ci_umv_buf_t *p_umv_buf )\r
-{\r
- ib_api_status_t status = IB_SUCCESS;\r
-\r
- FUNC_ENTER;\r
-\r
- CL_ASSERT(h_uvp_ca);\r
-\r
- /* hca_ul_info should be filled up by open_ca() */\r
- if ( h_uvp_ca->p_hca_ul_info->status != HH_HCA_STATUS_OPENED )\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Device is not opened\n"));\r
- status = IB_INVALID_CA_HANDLE;\r
- return status;\r
- }\r
- /*\r
- * First time call query_ca - populate our internal cached attributes\r
- * so we can access the GID table. Note that query_ca calls *always*\r
- * get their attributes from the kernel.\r
- */\r
- if ( !h_uvp_ca->p_hca_attr )\r
- {\r
- /*\r
- * Assume if user buffer is valid then byte_cnt is valid too \r
- * so we can preallocate ca attr buffer for post ioctl data saving\r
- *\r
- * Note that we squirel the buffer away into the umv_buf and only\r
- * set it into the HCA if the query is successful.\r
- */\r
- if ( p_ca_attr != NULL )\r
- {\r
- p_umv_buf->p_inout_buf = cl_zalloc(byte_count);\r
- if ( !p_umv_buf->p_inout_buf )\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Failed to alloc new_ca\n"));\r
- status = IB_INSUFFICIENT_RESOURCES;\r
- return status;\r
- }\r
- }\r
- p_umv_buf->input_size = p_umv_buf->output_size = 0;\r
- }\r
-\r
- FUNC_EXIT;\r
- return status;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_query_ca (\r
- IN ib_ca_handle_t h_uvp_ca,\r
- IN ib_api_status_t ioctl_status,\r
- IN ib_ca_attr_t *p_ca_attr,\r
- IN size_t byte_count,\r
- IN ci_umv_buf_t *p_umv_buf )\r
-{\r
- FUNC_ENTER;\r
-\r
- CL_ASSERT(h_uvp_ca);\r
- CL_ASSERT(p_umv_buf);\r
-\r
- if ( ioctl_status == IB_SUCCESS && p_ca_attr &&\r
- byte_count && !h_uvp_ca->p_hca_attr )\r
- {\r
- CL_ASSERT( byte_count >= p_ca_attr->size );\r
- h_uvp_ca->p_hca_attr = p_umv_buf->p_inout_buf;\r
- ib_copy_ca_attr( h_uvp_ca->p_hca_attr, p_ca_attr );\r
- }\r
- else if (p_umv_buf->p_inout_buf) \r
- {\r
- cl_free (p_umv_buf->p_inout_buf);\r
- }\r
-\r
- FUNC_EXIT;\r
- return;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_modify_ca (\r
- IN ib_ca_handle_t h_uvp_ca,\r
- IN uint8_t port_num,\r
- IN ib_ca_mod_t ca_mod,\r
- IN const ib_port_attr_mod_t* p_port_attr_mod)\r
-{\r
- FUNC_ENTER;\r
- FUNC_EXIT;\r
- return IB_SUCCESS;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_modify_ca (\r
- IN ib_ca_handle_t h_uvp_ca,\r
- IN ib_api_status_t ioctl_status)\r
-{\r
- FUNC_ENTER;\r
- FUNC_EXIT;\r
- return;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_close_ca (\r
- IN ib_ca_handle_t h_uvp_ca)\r
-{\r
- FUNC_ENTER;\r
- FUNC_EXIT;\r
- return IB_SUCCESS;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_post_close_ca (\r
- IN ib_ca_handle_t h_uvp_ca,\r
- IN ib_api_status_t ioctl_status )\r
-{\r
- mlnx_ual_hobul_t *p_hobul = (mlnx_ual_hobul_t *)((void*)h_uvp_ca);\r
-\r
- FUNC_ENTER;\r
-\r
- CL_ASSERT(p_hobul);\r
-\r
- if (p_hobul->hhul_hca_hndl)\r
- {\r
- if (HH_OK != THHUL_hob_destroy (p_hobul->hhul_hca_hndl))\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Failed to destroy THHUL_hob object\n"));\r
- return IB_SUCCESS;\r
- }\r
- }\r
-\r
- if (p_hobul->p_hca_attr)\r
- {\r
- cl_free( p_hobul->p_hca_attr);\r
- p_hobul->p_hca_attr = NULL;\r
- }\r
- cl_free(p_hobul);\r
- \r
- FUNC_EXIT;\r
- return IB_SUCCESS;\r
-}\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies, Inc. All rights reserved. \r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "mlnx_ual_main.h"\r
-\r
-extern u_int32_t mlnx_dbg_lvl;\r
-\r
-void\r
-mlnx_get_cq_interface (\r
- IN OUT uvp_interface_t *p_uvp )\r
-{\r
- FUNC_ENTER;\r
-\r
- CL_ASSERT(p_uvp);\r
-\r
- /*\r
- * Completion Queue Management Verbs\r
- */\r
- p_uvp->pre_create_cq = mlnx_pre_create_cq;\r
- p_uvp->post_create_cq = mlnx_post_create_cq;\r
- \r
- p_uvp->pre_query_cq = mlnx_pre_query_cq;\r
- p_uvp->post_query_cq = NULL;\r
-\r
- p_uvp->pre_resize_cq = mlnx_pre_resize_cq;\r
- p_uvp->post_resize_cq = mlnx_post_resize_cq;\r
-\r
- p_uvp->pre_destroy_cq = mlnx_pre_destroy_cq;\r
- p_uvp->post_destroy_cq = mlnx_post_destroy_cq;\r
-\r
- FUNC_EXIT;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_create_cq (\r
- IN const ib_ca_handle_t h_uvp_ca,\r
- IN OUT uint32_t* const p_size,\r
- IN OUT ci_umv_buf_t *p_umv_buf,\r
- OUT ib_cq_handle_t *ph_uvp_cq)\r
-{\r
- ib_api_status_t status = IB_SUCCESS;\r
- HH_ret_t hh_ret = HH_OK;\r
- mlnx_ual_hobul_t *p_hobul = (mlnx_ual_hobul_t *)((void*)h_uvp_ca);\r
-\r
- mlnx_ual_cq_info_t *p_new_cq = NULL;\r
- size_t size;\r
-\r
- UNREFERENCED_PARAMETER(ph_uvp_cq);\r
- \r
- FUNC_ENTER;\r
-\r
- CL_ASSERT(p_umv_buf);\r
-\r
- CL_ASSERT(p_hobul);\r
-\r
- do \r
- {\r
- /* CA should be initialized */\r
- if (!p_hobul->p_hca_ul_info) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("INVALID hca_ul_info buffer\n"));\r
- status = IB_INVALID_CA_HANDLE;\r
- break;\r
- }\r
- \r
- if (!p_hobul->p_hca_ul_resources) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("INVALID hca_ul_resources buffer\n"));\r
- status = IB_RESOURCE_BUSY;\r
- break;\r
- }\r
-\r
- p_new_cq = cl_zalloc (sizeof(mlnx_ual_cq_info_t));\r
- if (!p_new_cq) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Failed alloc new CQ\n"));\r
- status = IB_INSUFFICIENT_MEMORY;\r
- break;\r
- }\r
-\r
- p_new_cq->p_cq_ul_resources = \r
- cl_zalloc(p_hobul->p_hca_ul_info->cq_ul_resources_sz);\r
- if (!p_new_cq->p_cq_ul_resources) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Failed alloc new CQ UL resources\n"));\r
- status = IB_INSUFFICIENT_MEMORY;\r
- break;\r
- }\r
-\r
- hh_ret = THHUL_cqm_create_cq_prep (p_hobul->hhul_hca_hndl,\r
- *p_size,\r
- &p_new_cq->hhul_cq_hndl,\r
- &p_new_cq->cq_size,\r
- p_new_cq->p_cq_ul_resources);\r
- if (hh_ret != HH_OK)\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Calling THHUL_cqm_create_cq_prep Failed\n"));\r
- status = IB_RESOURCE_BUSY;\r
- break;\r
- }\r
-\r
- if (*p_size != p_new_cq->cq_size)\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("The created cq_size %d different than *p_size %d\n",\r
- p_new_cq->cq_size, *p_size));\r
- cl_memcpy ((void *)p_size, &p_new_cq->cq_size, sizeof (p_new_cq->cq_size));\r
- }\r
-\r
- /* \r
- * Store the parent PD of this CQ\r
- */ \r
- p_new_cq->p_hobul = p_hobul;\r
-\r
- size = p_hobul->p_hca_ul_info->cq_ul_resources_sz + \r
- sizeof (u_int32_t) + sizeof (mlnx_ual_cq_info_t *);\r
- p_umv_buf->p_inout_buf = cl_zalloc(size);\r
-\r
- if (!p_umv_buf->p_inout_buf)\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Failed alloc user private buffer\n"));\r
- status = IB_INSUFFICIENT_MEMORY;\r
- break;\r
- }\r
- /* \r
- * We only set the input_size up to qp_ul_resources_sz + sizeof (qp_idx)\r
- * The rest of the buffer we store the pointer to our allocated\r
- * qp_info struct in order to retrieve it later in the post.\r
- */\r
- p_umv_buf->input_size = p_umv_buf->output_size = \r
- (uint32_t)size - sizeof (mlnx_ual_cq_info_t *); \r
- \r
- cl_memcpy (p_umv_buf->p_inout_buf,\r
- p_new_cq->p_cq_ul_resources,\r
- p_hobul->p_hca_ul_info->cq_ul_resources_sz);\r
- /* \r
- * Store the pointer of our qp_info struct to inout_buf and retrieve\r
- * it later in the post\r
- */\r
- cl_memcpy (((u_int8_t *)p_umv_buf->p_inout_buf + size - \r
- sizeof (mlnx_ual_cq_info_t *)),\r
- &p_new_cq,\r
- sizeof (mlnx_ual_cq_info_t *));\r
- p_umv_buf->command = TRUE;\r
- } while (0);\r
-\r
- /* \r
- * clean_up if required \r
- */\r
- if (IB_SUCCESS != status) \r
- {\r
- if (p_new_cq) \r
- {\r
- if (p_new_cq->p_cq_ul_resources);\r
- {\r
- cl_free (p_new_cq->p_cq_ul_resources);\r
- }\r
- if (hh_ret == HH_OK && p_new_cq->hhul_cq_hndl )\r
- {\r
- THHUL_cqm_destroy_cq_done (p_hobul->hhul_hca_hndl, \r
- p_new_cq->hhul_cq_hndl);\r
- }\r
- if (p_umv_buf->p_inout_buf)\r
- {\r
- cl_free ( p_umv_buf->p_inout_buf);\r
- }\r
- cl_free (p_new_cq);\r
- }\r
- }\r
-\r
- FUNC_EXIT;\r
- return status;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_create_cq (\r
- IN const ib_ca_handle_t h_uvp_ca,\r
- IN ib_api_status_t ioctl_status,\r
- IN const uint32_t size,\r
- IN OUT ib_cq_handle_t *ph_uvp_cq,\r
- IN ci_umv_buf_t *p_umv_buf )\r
-{\r
- mlnx_ual_hobul_t *p_hobul = (mlnx_ual_hobul_t *)((void*)h_uvp_ca);\r
- MT_size_t buf_size = 0;\r
- mlnx_ual_cq_info_t *p_new_cq = NULL;\r
-\r
-\r
- FUNC_ENTER;\r
-\r
- CL_ASSERT(p_umv_buf);\r
-\r
- CL_ASSERT(p_hobul);\r
-\r
- buf_size = p_hobul->p_hca_ul_info->cq_ul_resources_sz + \r
- sizeof (u_int32_t) + sizeof (mlnx_ual_cq_info_t *);\r
-\r
- /* Retrieve our cq_info back from priv buffer */\r
- cl_memcpy (&p_new_cq,\r
- ((u_int8_t *)p_umv_buf->p_inout_buf + buf_size - \r
- sizeof (mlnx_ual_cq_info_t *)),\r
- sizeof (mlnx_ual_cq_info_t *));\r
- CL_ASSERT(p_new_cq);\r
-\r
- *ph_uvp_cq = p_new_cq;\r
-\r
- if ( ioctl_status == IB_SUCCESS )\r
- {\r
- if (IB_SUCCESS != p_umv_buf->status) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Bad status %ld\n", p_umv_buf->status));\r
- goto err;\r
- }\r
- else if ((buf_size - sizeof (mlnx_ual_cq_info_t *)) != \r
- p_umv_buf->output_size) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Bad user priv buffer size (exp - 4) = %d, res = %ld\n",\r
- buf_size, p_umv_buf->output_size));\r
- goto err;\r
- }\r
-\r
- cl_memcpy (p_new_cq->p_cq_ul_resources,\r
- p_umv_buf->p_inout_buf,\r
- p_hobul->p_hca_ul_info->cq_ul_resources_sz);\r
-\r
- cl_memcpy (&p_new_cq->cq_idx,\r
- ((u_int8_t *)p_umv_buf->p_inout_buf + \r
- p_hobul->p_hca_ul_info->cq_ul_resources_sz),\r
- sizeof (u_int32_t));\r
-\r
- if (HH_OK !=\r
- THHUL_cqm_create_cq_done (p_hobul->hhul_hca_hndl,\r
- p_new_cq->hhul_cq_hndl,\r
- p_new_cq->cq_idx,\r
- p_new_cq->p_cq_ul_resources))\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Call THHUL_cqm_create_cq_done Failed\n"));\r
- goto err;\r
- }\r
-\r
- CL_TRACE (MLNX_TRACE_LVL_7, mlnx_dbg_lvl,\r
- ("Newly created CQ cq_idx 0x%x (CQ size %d)\n",p_new_cq->cq_idx, p_new_cq->cq_size)); \r
- }\r
- else\r
- {\r
-err:\r
- if (p_new_cq->p_cq_ul_resources)\r
- cl_free (p_new_cq->p_cq_ul_resources);\r
-\r
- cl_free (p_new_cq);\r
- *ph_uvp_cq = NULL;\r
- }\r
-\r
- cl_free (p_umv_buf->p_inout_buf);\r
- p_umv_buf->p_inout_buf = NULL;\r
-\r
- FUNC_EXIT;\r
- return;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_resize_cq (\r
- IN const ib_cq_handle_t h_uvp_cq,\r
- IN OUT uint32_t* const p_size,\r
- IN OUT ci_umv_buf_t *p_umv_buf )\r
-{\r
- mlnx_ual_cq_info_t *p_cq_info = (mlnx_ual_cq_info_t *)((void*) h_uvp_cq);\r
- mlnx_ual_hobul_t *p_hobul;\r
- ib_api_status_t status = IB_SUCCESS;\r
- void *p_cq_ul_resources;\r
-\r
- FUNC_ENTER;\r
-\r
- p_hobul = p_cq_info->p_hobul;\r
-\r
- CL_ASSERT(p_umv_buf);\r
- CL_ASSERT(p_hobul);\r
-\r
- do \r
- {\r
- p_cq_ul_resources = \r
- cl_zalloc (p_hobul->p_hca_ul_info->cq_ul_resources_sz);\r
- if (!p_cq_ul_resources)\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Failed to alloc cq_ul_res\n"));\r
- status = IB_INSUFFICIENT_MEMORY;\r
- break;\r
- }\r
-\r
- CL_TRACE (MLNX_TRACE_LVL_8, mlnx_dbg_lvl,\r
- ("Before resize_cq_prep *p_size = %d\n", *p_size));\r
- status = THHUL_cqm_resize_cq_prep ( p_hobul->hhul_hca_hndl,\r
- p_cq_info->hhul_cq_hndl,\r
- *p_size, &p_cq_info->cq_size,\r
- p_cq_ul_resources);\r
- if( status != IB_SUCCESS )\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("THHUL_cqm_resize_cq_prep failed\n"));\r
- break;\r
- }\r
- CL_TRACE (MLNX_TRACE_LVL_8, mlnx_dbg_lvl,\r
- ("After resize_cq_prep *p_size = %d\n", *p_size));\r
-\r
- p_umv_buf->p_inout_buf = p_cq_ul_resources;\r
- p_umv_buf->input_size = (uint32_t)p_hobul->p_hca_ul_info->cq_ul_resources_sz;\r
- p_umv_buf->output_size = p_umv_buf->input_size;\r
- p_umv_buf->command = TRUE;\r
-\r
- } while (0);\r
-\r
- FUNC_EXIT;\r
- return status;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_resize_cq (\r
- IN const ib_cq_handle_t h_uvp_cq,\r
- IN ib_api_status_t ioctl_status,\r
- IN const uint32_t size,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- ib_api_status_t status;\r
- mlnx_ual_cq_info_t *p_cq_info = (mlnx_ual_cq_info_t *)((void*) h_uvp_cq);\r
- //mlnx_ual_pd_info_t *p_pd_info;\r
- mlnx_ual_hobul_t *p_hobul;\r
-\r
- FUNC_ENTER;\r
- CL_ASSERT (p_cq_info);\r
- CL_ASSERT(p_umv_buf);\r
-\r
- //p_pd_info = (mlnx_ual_pd_info_t *) p_cq_info->h_uvp_pd;\r
- //CL_ASSERT (p_pd_info);\r
-\r
- p_hobul = p_cq_info->p_hobul;\r
- CL_ASSERT (p_hobul);\r
-\r
- status = ioctl_status;\r
-\r
- do \r
- {\r
- if (IB_SUCCESS == status)\r
- {\r
- if (IB_SUCCESS != p_umv_buf->status) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Bad status %ld\n", p_umv_buf->status));\r
- status = p_umv_buf->status;\r
- break;\r
- }\r
- else if (p_umv_buf->output_size != \r
- (p_hobul->p_hca_ul_info->cq_ul_resources_sz) )\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Bad priv buf size %ld\n", p_umv_buf->output_size));\r
- status = IB_ERROR;\r
- break;\r
- }\r
- \r
- if (HH_OK != THHUL_cqm_resize_cq_done (\r
- p_hobul->hhul_hca_hndl,\r
- p_cq_info->hhul_cq_hndl,\r
- p_umv_buf->p_inout_buf))\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("THHUL_cqm_resize_cq_done failed\n"));\r
- status = IB_ERROR;\r
- break;\r
- }\r
- }\r
-\r
- } while (0);\r
-\r
- if (IB_SUCCESS != status) \r
- {\r
- /* \r
- * Undo resize\r
- */\r
- if (HH_OK != THHUL_cqm_resize_cq_done (\r
- p_hobul->hhul_hca_hndl,\r
- p_cq_info->hhul_cq_hndl,\r
- NULL))\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Failed to UNDO resize (serious)\n"));\r
- }\r
- }\r
-\r
- cl_free (p_umv_buf->p_inout_buf);\r
-\r
- FUNC_EXIT;\r
- return;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_query_cq (\r
- IN const ib_cq_handle_t h_uvp_cq,\r
- OUT uint32_t* const p_size,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- mlnx_ual_cq_info_t *p_cq_info = (mlnx_ual_cq_info_t *)((void*) h_uvp_cq);\r
-\r
- FUNC_ENTER;\r
-\r
- *p_size = p_cq_info->cq_size;\r
-\r
- FUNC_EXIT;\r
- return IB_VERBS_PROCESSING_DONE;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_destroy_cq (\r
- IN const ib_cq_handle_t h_uvp_cq)\r
-{\r
- FUNC_ENTER;\r
- FUNC_EXIT;\r
- return IB_SUCCESS;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_destroy_cq (\r
- IN const ib_cq_handle_t h_uvp_cq,\r
- IN ib_api_status_t ioctl_status)\r
-{\r
- mlnx_ual_cq_info_t *p_cq_info = (mlnx_ual_cq_info_t *) ((void*)h_uvp_cq);\r
- //mlnx_ual_pd_info_t *p_pd_info;\r
- mlnx_ual_hobul_t *p_hobul;\r
-\r
- FUNC_ENTER;\r
- CL_ASSERT (p_cq_info);\r
-\r
- //p_pd_info = (mlnx_ual_pd_info_t *) p_cq_info->h_uvp_pd;\r
- //CL_ASSERT (p_pd_info);\r
-\r
- p_hobul = p_cq_info->p_hobul;\r
- CL_ASSERT (p_hobul);\r
-\r
- THHUL_cqm_destroy_cq_done (p_hobul->hhul_hca_hndl,\r
- p_cq_info->hhul_cq_hndl);\r
-\r
- if (p_cq_info->p_cq_ul_resources) \r
- {\r
- cl_free (p_cq_info->p_cq_ul_resources );\r
- p_cq_info->p_cq_ul_resources = NULL; \r
- }\r
- cl_free (p_cq_info);\r
-\r
- FUNC_EXIT;\r
- return;\r
-}\r
-\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies, Inc. All rights reserved. \r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "mlnx_ual_main.h"\r
-\r
-u_int32_t mlnx_dbg_lvl = 0; // MLNX_TRACE_LVL_8;\r
-\r
-\r
-static void uvp_init();\r
-\r
-\r
-extern BOOL APIENTRY\r
-_DllMainCRTStartupForGS(\r
- IN HINSTANCE h_module,\r
- IN DWORD ul_reason_for_call, \r
- IN LPVOID lp_reserved );\r
-\r
-\r
-BOOL APIENTRY\r
-DllMain(\r
- IN HINSTANCE h_module,\r
- IN DWORD ul_reason_for_call, \r
- IN LPVOID lp_reserved )\r
-{\r
- switch( ul_reason_for_call )\r
- {\r
- case DLL_PROCESS_ATTACH:\r
- if( !_DllMainCRTStartupForGS(\r
- h_module, ul_reason_for_call, lp_reserved ) )\r
- {\r
- return FALSE;\r
- }\r
-\r
- uvp_init();\r
- break;\r
-\r
- default:\r
- return _DllMainCRTStartupForGS(\r
- h_module, ul_reason_for_call, lp_reserved );\r
- }\r
- return TRUE;\r
-}\r
-\r
-\r
-/*\r
- * UVP Shared Library Init routine\r
-*/\r
-\r
-static void\r
-uvp_init()\r
-{\r
-#define ENV_BUFSIZE 20\r
- TCHAR envstr[ENV_BUFSIZE];\r
- \r
- /*\r
- * Override default debugging level if environment variable is set\r
- */\r
- if (( GetEnvironmentVariable("MLNX_TRACE_LVL", envstr, ENV_BUFSIZE)) != 0 ) {\r
- switch(strtoul(envstr,NULL,0)) {\r
- case 0:\r
- mlnx_dbg_lvl=0;\r
- break;\r
- case 1:\r
- mlnx_dbg_lvl = MLNX_TRACE_LVL_1;\r
- break;\r
- case 2:\r
- mlnx_dbg_lvl = MLNX_TRACE_LVL_2;\r
- break;\r
- case 3:\r
- mlnx_dbg_lvl = MLNX_TRACE_LVL_3;\r
- break;\r
- case 4:\r
- mlnx_dbg_lvl = MLNX_TRACE_LVL_4;\r
- break;\r
- case 5:\r
- mlnx_dbg_lvl = MLNX_TRACE_LVL_5;\r
- break;\r
- case 6:\r
- mlnx_dbg_lvl = MLNX_TRACE_LVL_6;\r
- break;\r
- case 7:\r
- mlnx_dbg_lvl = MLNX_TRACE_LVL_7;\r
- break;\r
- case 8:\r
- mlnx_dbg_lvl = MLNX_TRACE_LVL_8;\r
- break;\r
- default:\r
- mlnx_dbg_lvl = MLNX_TRACE_LVL_8;\r
- }\r
- }\r
- /*\r
- * Open the MOSAL device\r
- */\r
- \r
- //MOSAL_user_lib_init();\r
-}\r
-\r
-__declspec(dllexport) ib_api_status_t\r
-uvp_get_interface (\r
- IN OUT uvp_interface_t *p_uvp )\r
-{\r
- FUNC_ENTER;\r
-\r
- CL_ASSERT(p_uvp);\r
- /*\r
- * Version of the header file this interface export can handle\r
- */\r
- p_uvp->version = 0x100;\r
- p_uvp->guid = 0x12345678;\r
-\r
- /*\r
- * CA Management\r
- */\r
- mlnx_get_ca_interface (p_uvp);\r
- \r
- /*\r
- * Protection Domain\r
- */\r
- mlnx_get_pd_interface (p_uvp);\r
-\r
- /*\r
- * QP Management Verbs\r
- */\r
- mlnx_get_qp_interface (p_uvp);\r
-\r
- /*\r
- * Completion Queue Management Verbs\r
- */\r
- mlnx_get_cq_interface (p_uvp);\r
-\r
- /*\r
- * AV Management\r
- */\r
- mlnx_get_av_interface(p_uvp);\r
-\r
- /*\r
- * Memory Region / Window Management Verbs\r
- */\r
- mlnx_get_mrw_interface (p_uvp);\r
-\r
- /*\r
- * Multicast Support Verbs\r
- */\r
- mlnx_get_mcast_interface (p_uvp);\r
-\r
- /*\r
- * OS bypass (send, receive, poll/notify cq)\r
- */\r
- mlnx_get_osbypass_interface(p_uvp);\r
-\r
- \r
- /*\r
- * Local MAD support, for HCA's that do not support\r
- * Agents in the HW.\r
- * ??? Do we need this for user-mode ???\r
- */\r
-\r
- FUNC_EXIT;\r
- return IB_SUCCESS;\r
-}\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies, Inc. All rights reserved. \r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef __UAL_MAIN_H__\r
-#define __UAL_MAIN_H__\r
-\r
-#include <hh.h>\r
-#include <hhul.h>\r
-#include <thhul_hob.h>\r
-#include <thhul_pdm.h>\r
-#include <thhul_cqm.h>\r
-#include <thhul_qpm.h>\r
-#include <thhul_mwm.h>\r
-\r
-//#include <iba/ib_ci.h>\r
-#include "hca_data.h"\r
-#include <complib/cl_debug.h>\r
-#include <complib/cl_byteswap.h>\r
-#include <complib/cl_memory.h>\r
-//#include <complib/cl_device.h>\r
-\r
-/*\r
- * Debug level\r
- */\r
-#define MLNX_TRACE_LVL_8 0x000000ff\r
-#define MLNX_TRACE_LVL_7 0x0000007f\r
-#define MLNX_TRACE_LVL_6 0x0000003f\r
-#define MLNX_TRACE_LVL_5 0x0000001f\r
-#define MLNX_TRACE_LVL_4 0x0000000f\r
-#define MLNX_TRACE_LVL_3 0x00000007\r
-#define MLNX_TRACE_LVL_2 0x00000003\r
-#define MLNX_TRACE_LVL_1 0x00000001\r
-#define MLNX_ENTER_EXIT MLNX_TRACE_LVL_8\r
-\r
-#define FUNC_ENTER CL_ENTER(MLNX_ENTER_EXIT, mlnx_dbg_lvl)\r
-#define FUNC_EXIT CL_EXIT(MLNX_ENTER_EXIT, mlnx_dbg_lvl)\r
-\r
-#define MAX_WRS_PER_CHAIN 16\r
-#define MAX_NUM_SGE 32\r
-\r
-#define MLNX_SGE_SIZE 16\r
-#define MLNX_UAL_ALLOC_HCA_UL_RES 1\r
-#define MLNX_UAL_FREE_HCA_UL_RES 2\r
-\r
-typedef unsigned __int3264 cl_dev_handle_t;\r
-\r
-\r
-/*\r
- * PROTOTYPES\r
- */\r
-\r
-/************* CA operations *************************/\r
-void \r
-mlnx_get_ca_interface (\r
- IN OUT uvp_interface_t *p_uvp );\r
-\r
-\r
-ib_api_status_t \r
-mlnx_pre_open_ca (\r
- IN const ib_net64_t ca_guid,\r
- IN OUT ci_umv_buf_t *p_umv_buf,\r
- OUT ib_ca_handle_t *ph_uvp_ca);\r
- \r
- \r
-ib_api_status_t\r
-mlnx_post_open_ca (\r
- IN const ib_net64_t ca_guid,\r
- IN ib_api_status_t ioctl_status,\r
- IN OUT ib_ca_handle_t *ph_uvp_ca,\r
- IN ci_umv_buf_t *p_umv_buf );\r
-\r
-\r
-ib_api_status_t \r
-mlnx_pre_query_ca (\r
- IN ib_ca_handle_t h_uvp_ca,\r
- IN ib_ca_attr_t *p_ca_attr,\r
- IN size_t byte_count,\r
- IN ci_umv_buf_t *p_umv_buf );\r
-\r
-void \r
-mlnx_post_query_ca (\r
- IN ib_ca_handle_t h_uvp_ca,\r
- IN ib_api_status_t ioctl_status,\r
- IN ib_ca_attr_t *p_ca_attr,\r
- IN size_t byte_count,\r
- IN ci_umv_buf_t *p_umv_buf );\r
-\r
-ib_api_status_t \r
-mlnx_pre_modify_ca (\r
- IN ib_ca_handle_t h_uvp_ca,\r
- IN uint8_t port_num,\r
- IN ib_ca_mod_t modca_cmd,\r
- IN const ib_port_attr_mod_t* p_port_attr_mod );\r
-\r
-void \r
-mlnx_post_modify_ca (\r
- IN ib_ca_handle_t h_uvp_ca,\r
- IN ib_api_status_t ioctl_status);\r
-\r
-ib_api_status_t \r
-mlnx_pre_close_ca (\r
- IN ib_ca_handle_t h_uvp_ca );\r
-\r
-ib_api_status_t\r
-mlnx_post_close_ca (\r
- IN ib_ca_handle_t h_uvp_ca,\r
- IN ib_api_status_t ioctl_status );\r
-\r
-\r
-/************* PD Management *************************/\r
-void \r
-mlnx_get_pd_interface (\r
- IN OUT uvp_interface_t *p_uvp );\r
- \r
-ib_api_status_t \r
-mlnx_pre_allocate_pd (\r
- IN const ib_ca_handle_t h_uvp_ca,\r
- IN OUT ci_umv_buf_t *p_umv_buf,\r
- OUT ib_pd_handle_t *ph_uvp_pd);\r
-\r
-void \r
-mlnx_post_allocate_pd (\r
- IN ib_ca_handle_t h_uvp_ca,\r
- IN ib_api_status_t ioctl_status,\r
- IN OUT ib_pd_handle_t *ph_uvp_pd,\r
- IN ci_umv_buf_t *p_umv_buf );\r
-\r
-ib_api_status_t \r
-mlnx_pre_deallocate_pd (\r
- IN const ib_pd_handle_t h_uvp_pd);\r
-\r
-void \r
-mlnx_post_deallocate_pd (\r
- IN const ib_pd_handle_t h_uvp_pd,\r
- IN ib_api_status_t ioctl_status );\r
-\r
-\r
-/************* AV Management *************************/\r
-void\r
-mlnx_get_av_interface (\r
- IN OUT uvp_interface_t *p_uvp );\r
-\r
-ib_api_status_t \r
-mlnx_pre_create_av (\r
- IN const ib_pd_handle_t h_uvp_pd,\r
- IN const ib_av_attr_t *p_addr_vector,\r
- IN OUT ci_umv_buf_t *p_umv_buf,\r
- OUT ib_av_handle_t *ph_uvp_av);\r
-\r
-\r
-void\r
-mlnx_post_create_av (\r
- IN const ib_pd_handle_t h_uvp_pd,\r
- IN ib_api_status_t ioctl_status,\r
- IN OUT ib_av_handle_t *ph_uvp_av,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-ib_api_status_t \r
-mlnx_pre_query_av (\r
- IN const ib_av_handle_t h_uvp_av,\r
- IN OUT ci_umv_buf_t *p_umv_buf );\r
-\r
-void \r
-mlnx_post_query_av (\r
- IN const ib_av_handle_t h_uvp_av,\r
- IN ib_api_status_t ioctl_status,\r
- IN OUT ib_av_attr_t *p_addr_vector,\r
- IN OUT ib_pd_handle_t *ph_pd,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-ib_api_status_t \r
-mlnx_pre_modify_av (\r
- IN const ib_av_handle_t h_uvp_av,\r
- IN const ib_av_attr_t *p_addr_vector,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-void \r
-mlnx_post_modify_av (\r
- IN const ib_av_handle_t h_uvp_av,\r
- IN ib_api_status_t ioctl_status,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-ib_api_status_t \r
-mlnx_pre_destroy_av (\r
- IN const ib_av_handle_t h_uvp_av);\r
-\r
-void \r
-mlnx_post_destroy_av (\r
- IN const ib_av_handle_t h_uvp_av,\r
- IN ib_api_status_t ioctl_status);\r
-\r
-\r
-/************* CQ Management *************************/\r
-void \r
-mlnx_get_cq_interface (\r
- IN OUT uvp_interface_t *p_uvp );\r
-\r
-ib_api_status_t \r
-mlnx_pre_create_cq (\r
- IN const ib_ca_handle_t h_uvp_ca,\r
- IN OUT uint32_t* const p_size,\r
- IN OUT ci_umv_buf_t *p_umv_buf,\r
- OUT ib_cq_handle_t *ph_uvp_cq);\r
-\r
-void \r
-mlnx_post_create_cq (\r
- IN const ib_ca_handle_t h_uvp_ca,\r
- IN ib_api_status_t ioctl_status,\r
- IN const uint32_t size,\r
- IN OUT ib_cq_handle_t *ph_uvp_cq,\r
- IN ci_umv_buf_t *p_umv_buf );\r
-\r
-ib_api_status_t \r
-mlnx_pre_resize_cq (\r
- IN const ib_cq_handle_t h_uvp_cq,\r
- IN OUT uint32_t* const p_size,\r
- IN OUT ci_umv_buf_t *p_umv_buf );\r
-\r
-void \r
-mlnx_post_resize_cq (\r
- IN const ib_cq_handle_t h_uvp_cq,\r
- IN ib_api_status_t ioctl_status,\r
- IN const uint32_t size,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-ib_api_status_t \r
-mlnx_pre_query_cq (\r
- IN const ib_cq_handle_t h_uvp_cq,\r
- OUT uint32_t* const p_size,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-ib_api_status_t \r
-mlnx_pre_destroy_cq (\r
- IN const ib_cq_handle_t h_uvp_cq);\r
-\r
-void \r
-mlnx_post_destroy_cq (\r
- IN const ib_cq_handle_t h_uvp_cq,\r
- IN ib_api_status_t ioctl_status);\r
-\r
-/************* QP Management *************************/\r
-void \r
-mlnx_get_qp_interface (\r
- IN OUT uvp_interface_t *p_uvp );\r
-\r
-ib_api_status_t \r
-mlnx_pre_create_qp (\r
- IN const ib_pd_handle_t h_uvp_pd,// Fix me: if needed\r
- IN const ib_qp_create_t *p_create_attr,\r
- IN OUT ci_umv_buf_t *p_umv_buf,\r
- OUT ib_qp_handle_t *ph_uvp_qp);\r
-\r
-ib_api_status_t \r
-mlnx_post_create_qp (\r
- IN const ib_pd_handle_t h_uvp_pd,\r
- IN ib_api_status_t ioctl_status,\r
- IN OUT ib_qp_handle_t *ph_uvp_qp,\r
- IN ci_umv_buf_t *p_umv_buf );\r
-\r
-ib_api_status_t \r
-mlnx_pre_modify_qp (\r
- IN const ib_qp_handle_t h_uvp_qp,\r
- IN const ib_qp_mod_t *p_modify_attr, // Fixme\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-void \r
-mlnx_post_modify_qp (\r
- IN const ib_qp_handle_t h_uvp_qp,\r
- IN ib_api_status_t ioctl_status,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-ib_api_status_t \r
-mlnx_pre_query_qp (\r
- IN ib_qp_handle_t h_uvp_qp,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-void \r
-mlnx_post_query_qp (\r
- IN ib_qp_handle_t h_uvp_qp,\r
- IN ib_api_status_t ioctl_status,\r
- IN ib_qp_attr_t *p_query_attr,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-ib_api_status_t \r
-mlnx_pre_destroy_qp (\r
- IN const ib_qp_handle_t h_uvp_qp);\r
-\r
-void \r
-mlnx_post_destroy_qp (\r
- IN const ib_qp_handle_t h_uvp_qp,\r
- IN ib_api_status_t ioctl_status );\r
-\r
-/************* MR/MW Management *************************/\r
-void \r
-mlnx_get_mrw_interface (\r
- IN OUT uvp_interface_t *p_uvp );\r
-\r
-ib_api_status_t \r
-mlnx_pre_register_mr (\r
- IN const ib_pd_handle_t h_uvp_pd,\r
- IN const ib_mr_create_t *p_mr_create,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-void \r
-mlnx_post_register_mr (\r
- IN const ib_pd_handle_t h_uvp_pd,\r
- IN ib_api_status_t ioctl_status,\r
- IN const uint32_t *p_lkey,\r
- IN const uint32_t *p_rkey,\r
- OUT const ib_mr_handle_t *ph_uvp_mr,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-ib_api_status_t \r
-mlnx_pre_query_mr (\r
- IN const ib_mr_handle_t h_uvp_mr,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-void \r
-mlnx_post_query_mr (\r
- IN const ib_mr_handle_t h_uvp_mr,\r
- IN ib_api_status_t ioctl_status,\r
- IN const ib_mr_attr_t *p_mr_query,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-ib_api_status_t \r
-mlnx_pre_modify_mr (\r
- IN const ib_mr_handle_t h_uvp_mr,\r
- IN const ib_pd_handle_t h_uvp_pd OPTIONAL,\r
- IN const ib_mr_mod_t mr_mod_mask,\r
- IN const ib_mr_create_t *p_mr_create OPTIONAL,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-void \r
-mlnx_post_modify_mr (\r
- IN const ib_mr_handle_t h_uvp_mr,\r
- IN const ib_pd_handle_t h_uvp_pd OPTIONAL,\r
- IN ib_api_status_t ioctl_status,\r
- IN const uint32_t *p_lkey,\r
- IN const uint32_t *p_rkey,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-ib_api_status_t \r
-mlnx_pre_register_smr (\r
- IN const ib_pd_handle_t h_uvp_pd,\r
- IN const ib_mr_handle_t h_uvp_mr,\r
- IN const ib_access_t access_ctrl,\r
- IN void *p_vaddr,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-void \r
-mlnx_post_register_smr (\r
- IN const ib_pd_handle_t h_uvp_pd,\r
- IN const ib_mr_handle_t h_uvp_mr,\r
- IN ib_api_status_t ioctl_status,\r
- IN const void *p_vaddr,\r
- IN const uint32_t *p_lkey,\r
- IN const uint32_t *p_rkey,\r
- OUT const ib_mr_handle_t *ph_uvp_smr,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-ib_api_status_t \r
-mlnx_pre_deregister_mr (\r
- IN const ib_mr_handle_t h_uvp_mr,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-void \r
-mlnx_post_deregister_mr (\r
- IN const ib_mr_handle_t h_uvp_mr,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-ib_api_status_t \r
-mlnx_pre_create_mw (\r
- IN const ib_pd_handle_t h_uvp_pd,\r
- IN OUT ci_umv_buf_t *p_umv_buf,\r
- OUT ib_mw_handle_t *ph_uvp_mw);\r
-\r
-void \r
-mlnx_post_create_mw (\r
- IN const ib_pd_handle_t h_uvp_pd,\r
- IN ib_api_status_t ioctl_status,\r
- IN net32_t rkey,\r
- IN OUT ib_mw_handle_t *ph_uvp_mw,\r
- IN ci_umv_buf_t *p_umv_buf );\r
-\r
-ib_api_status_t \r
-mlnx_pre_query_mw (\r
- IN const ib_mw_handle_t h_uvp_mw,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-void \r
-mlnx_post_query_mw (\r
- IN const ib_mw_handle_t h_uvp_mw,\r
- IN ib_api_status_t ioctl_status,\r
- IN net32_t rkey,\r
- OUT ib_pd_handle_t *ph_pd,\r
- IN ci_umv_buf_t *p_umv_buf );\r
-\r
-ib_api_status_t \r
-mlnx_pre_destroy_mw (\r
- IN const ib_mw_handle_t h_uvp_mw);\r
- // IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-void \r
-mlnx_post_destroy_mw (\r
- IN const ib_mw_handle_t h_uvp_mw,\r
- IN ib_api_status_t ioctl_status);\r
-\r
-\r
-/************* MCAST Management *************************/\r
-void \r
-mlnx_get_mcast_interface (\r
- IN OUT uvp_interface_t *p_uvp );\r
-\r
-\r
-ib_api_status_t \r
-mlnx_pre_attach_mcast (\r
- IN const ib_qp_handle_t h_uvp_qp,\r
- IN const ib_gid_t *p_mcast_gid,\r
- IN const uint16_t mcast_lid,\r
- IN OUT ci_umv_buf_t *p_umv_buf,\r
- OUT ib_mcast_handle_t *ph_mcast);\r
-\r
-void \r
-mlnx_post_attach_mcast (\r
- IN const ib_qp_handle_t h_uvp_qp,\r
- IN ib_api_status_t ioctl_status,\r
- IN OUT ib_mcast_handle_t *ph_mcast,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-ib_api_status_t \r
-mlnx_pre_detach_mcast (\r
- IN ib_mcast_handle_t h_uvp_mcast,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-void \r
-mlnx_post_detach_mcast (\r
- IN ib_mcast_handle_t h_uvp_mcast,\r
- IN ib_api_status_t ioctl_status,\r
- IN OUT ci_umv_buf_t *p_umv_buf);\r
-\r
-\r
-/************* OS BYPASS Management *************************/\r
-void \r
-mlnx_get_osbypass_interface (\r
- IN OUT uvp_interface_t *p_uvp );\r
-\r
-ib_api_status_t \r
-mlnx_post_send (\r
- IN const void* __ptr64 h_qp,\r
- IN ib_send_wr_t* const p_send_wr,\r
- OUT ib_send_wr_t** pp_send_failure );\r
-\r
-ib_api_status_t \r
-mlnx_post_recv (\r
- IN const void* __ptr64 h_qp,\r
- IN ib_recv_wr_t* const p_recv_wr,\r
- OUT ib_recv_wr_t** pp_recv_failure );\r
-\r
-ib_api_status_t \r
-mlnx_bind_mw (\r
- IN const ib_mw_handle_t h_uvp_mw,\r
- IN const ib_qp_handle_t h_uvp_qp,\r
- IN ib_bind_wr_t *p_mw_bind,\r
- OUT net32_t* const p_rkey );\r
-\r
-ib_api_status_t \r
-mlnx_poll_cq (\r
- IN const void* __ptr64 h_cq,\r
- IN OUT ib_wc_t** const pp_free_wclist,\r
- OUT ib_wc_t** const pp_done_wclist );\r
-\r
-ib_api_status_t \r
-mlnx_enable_cq_notify (\r
- IN const void* __ptr64 h_cq,\r
- IN const boolean_t solicited );\r
-\r
-ib_api_status_t \r
-mlnx_enable_ncomp_cq_notify (\r
- IN const void* __ptr64 h_cq,\r
- IN const uint32_t n_cqes );\r
-\r
-ib_api_status_t\r
-mlnx_peek_cq (\r
- IN const void* __ptr64 h_cq,\r
- OUT uint32_t* const p_n_cqes );\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies, Inc. All rights reserved. \r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "mlnx_ual_main.h"\r
-\r
-extern u_int32_t mlnx_dbg_lvl;\r
-\r
-void\r
-mlnx_get_mcast_interface (\r
- IN OUT uvp_interface_t *p_uvp )\r
-{\r
- FUNC_ENTER;\r
-\r
- CL_ASSERT(p_uvp);\r
-\r
- /*\r
- * Multicast Support Verbs\r
- */\r
- p_uvp->pre_attach_mcast = NULL;\r
- p_uvp->post_attach_mcast = NULL;\r
- p_uvp->pre_detach_mcast = NULL;\r
- p_uvp->post_detach_mcast = NULL;\r
-\r
- FUNC_EXIT;\r
-}\r
-\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_attach_mcast (\r
- IN const ib_qp_handle_t h_uvp_qp,\r
- IN const ib_gid_t *p_mcast_gid,\r
- IN const uint16_t mcast_lid,\r
- IN OUT ci_umv_buf_t *p_umv_buf,\r
- OUT ib_mcast_handle_t *ph_mcast)\r
-{\r
- UNREFERENCED_PARAMETER(ph_mcast);\r
- \r
- FUNC_ENTER;\r
-#if 1\r
- CL_ASSERT(p_umv_buf);\r
- p_umv_buf->p_inout_buf = NULL;;\r
- p_umv_buf->input_size = 0;\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->command = TRUE;\r
-#endif\r
-\r
- FUNC_EXIT;\r
- return IB_SUCCESS;\r
-}\r
-\r
-\r
-\r
-void\r
-mlnx_post_attach_mcast (\r
- IN const ib_qp_handle_t h_uvp_qp,\r
- IN ib_api_status_t ioctl_status,\r
- IN OUT ib_mcast_handle_t *ph_mcast,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- FUNC_ENTER;\r
- FUNC_EXIT;\r
- return;\r
-}\r
-\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_detach_mcast (\r
- IN ib_mcast_handle_t h_uvp_mcast,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- FUNC_ENTER;\r
-#if 1\r
- CL_ASSERT(p_umv_buf);\r
- p_umv_buf->p_inout_buf = NULL;;\r
- p_umv_buf->input_size = 0;\r
- p_umv_buf->output_size = 0;\r
-#endif\r
-\r
- FUNC_EXIT;\r
- return IB_SUCCESS;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_detach_mcast (\r
- IN ib_mcast_handle_t h_uvp_mcast,\r
- IN ib_api_status_t ioctl_status,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- FUNC_ENTER;\r
- FUNC_EXIT;\r
- return;\r
-}\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies, Inc. All rights reserved. \r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "mlnx_ual_main.h"\r
-\r
-extern u_int32_t mlnx_dbg_lvl;\r
-\r
-void\r
-mlnx_get_mrw_interface (\r
- IN OUT uvp_interface_t *p_uvp )\r
-{\r
- FUNC_ENTER;\r
-\r
- CL_ASSERT(p_uvp);\r
-\r
- /*\r
- * Memory Management Verbs\r
- */\r
-// p_uvp->pre_register_mr = NULL;\r
-// p_uvp->post_register_mr = NULL;\r
-// p_uvp->pre_query_mr = NULL;\r
-// p_uvp->post_query_mr = NULL;\r
-// p_uvp->pre_deregister_mr = NULL;\r
-// p_uvp->post_deregister_mr = NULL;\r
-// p_uvp->pre_modify_mr = NULL;\r
-// p_uvp->post_modify_mr = NULL;\r
-// p_uvp->pre_register_smr = NULL;\r
-// p_uvp->post_register_smr = NULL;\r
-\r
- /*\r
- * Memory Window Verbs\r
- */\r
- p_uvp->pre_create_mw = mlnx_pre_create_mw;\r
- p_uvp->post_create_mw = mlnx_post_create_mw;\r
- p_uvp->pre_query_mw = mlnx_pre_query_mw;\r
- p_uvp->post_query_mw = mlnx_post_query_mw;\r
- p_uvp->pre_destroy_mw = mlnx_pre_destroy_mw;\r
- p_uvp->post_destroy_mw = mlnx_post_destroy_mw;\r
-\r
- /* register_pmr is not supported in user-mode */\r
-\r
- FUNC_EXIT;\r
-}\r
-\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_register_mr (\r
- IN const ib_pd_handle_t h_uvp_pd,\r
- IN const ib_mr_create_t *p_mr_create,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- FUNC_ENTER;\r
- CL_ASSERT(p_umv_buf);\r
- p_umv_buf->p_inout_buf = NULL;;\r
- p_umv_buf->input_size = 0;\r
- p_umv_buf->output_size = 0;\r
-\r
- FUNC_EXIT;\r
- return IB_SUCCESS;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_register_mr (\r
- IN const ib_pd_handle_t h_uvp_pd,\r
- IN ib_api_status_t ioctl_status,\r
- IN const uint32_t *p_lkey,\r
- IN const uint32_t *p_rkey,\r
- OUT const ib_mr_handle_t *ph_uvp_mr,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- FUNC_ENTER;\r
- FUNC_EXIT;\r
- return;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_query_mr (\r
- IN const ib_mr_handle_t h_uvp_mr,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- FUNC_ENTER;\r
- CL_ASSERT(p_umv_buf);\r
- p_umv_buf->p_inout_buf = NULL;;\r
- p_umv_buf->input_size = 0;\r
- p_umv_buf->output_size = 0;\r
-\r
- FUNC_EXIT;\r
- return IB_SUCCESS;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_query_mr (\r
- IN const ib_mr_handle_t h_uvp_mr,\r
- IN ib_api_status_t ioctl_status,\r
- IN const ib_mr_attr_t *p_mr_query,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- FUNC_ENTER;\r
- FUNC_EXIT;\r
- return;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_modify_mr (\r
- IN const ib_mr_handle_t h_uvp_mr,\r
- IN const ib_pd_handle_t h_uvp_pd OPTIONAL,\r
- IN const ib_mr_mod_t mr_mod_mask,\r
- IN const ib_mr_create_t *p_mr_create OPTIONAL,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- FUNC_ENTER;\r
- CL_ASSERT(p_umv_buf);\r
- p_umv_buf->p_inout_buf = NULL;;\r
- p_umv_buf->input_size = 0;\r
- p_umv_buf->output_size = 0;\r
-\r
- FUNC_EXIT;\r
- return IB_SUCCESS;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_modify_mr (\r
- IN const ib_mr_handle_t h_uvp_mr,\r
- IN const ib_pd_handle_t h_uvp_pd OPTIONAL,\r
- IN ib_api_status_t ioctl_status,\r
- IN const uint32_t *p_lkey,\r
- IN const uint32_t *p_rkey,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- FUNC_ENTER;\r
- FUNC_EXIT;\r
- return;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_register_smr (\r
- IN const ib_pd_handle_t h_uvp_pd,\r
- IN const ib_mr_handle_t h_uvp_mr,\r
- IN const ib_access_t access_ctrl,\r
- IN void *p_vaddr,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- FUNC_ENTER;\r
- CL_ASSERT(p_umv_buf);\r
- p_umv_buf->p_inout_buf = NULL;;\r
- p_umv_buf->input_size = 0;\r
- p_umv_buf->output_size = 0;\r
-\r
- FUNC_EXIT;\r
- return IB_SUCCESS;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_register_smr (\r
- IN const ib_pd_handle_t h_uvp_pd,\r
- IN const ib_mr_handle_t h_uvp_mr,\r
- IN ib_api_status_t ioctl_status,\r
- IN const void *p_vaddr,\r
- IN const uint32_t *p_lkey,\r
- IN const uint32_t *p_rkey,\r
- OUT const ib_mr_handle_t *ph_uvp_smr,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- FUNC_ENTER;\r
- FUNC_EXIT;\r
- return;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_deregister_mr (\r
- IN const ib_mr_handle_t h_uvp_mr,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- FUNC_ENTER;\r
- FUNC_EXIT;\r
- return IB_SUCCESS;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_deregister_mr (\r
- IN const ib_mr_handle_t h_uvp_mr,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- FUNC_ENTER;\r
- FUNC_EXIT;\r
- return;\r
-}\r
- \r
-\r
-ib_api_status_t\r
-mlnx_pre_create_mw (\r
- IN const ib_pd_handle_t h_uvp_pd,\r
- IN OUT ci_umv_buf_t *p_umv_buf,\r
- OUT ib_mw_handle_t *ph_uvp_mw)\r
-{\r
- ib_api_status_t status = IB_SUCCESS;\r
- mlnx_ual_pd_info_t *p_pd_info = (mlnx_ual_pd_info_t *)((void*) h_uvp_pd);\r
- mlnx_ual_hobul_t *p_hobul;\r
- mlnx_ual_mw_info_t *p_new_mw;\r
-\r
- UNREFERENCED_PARAMETER(ph_uvp_mw);\r
- \r
- FUNC_ENTER;\r
- CL_ASSERT(p_umv_buf);\r
- CL_ASSERT(p_pd_info);\r
-\r
- p_hobul = p_pd_info->p_hobul;\r
- CL_ASSERT(p_hobul);\r
-\r
- p_new_mw = cl_zalloc (sizeof (mlnx_ual_mw_info_t));\r
- if (p_new_mw == NULL)\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Failed to alloc memory\n"));\r
- status = IB_INSUFFICIENT_MEMORY;\r
- goto cleanup;\r
- }\r
- p_new_mw->h_uvp_pd = h_uvp_pd;\r
-\r
- p_umv_buf->input_size = p_umv_buf->output_size = \r
- sizeof (mlnx_ual_mw_info_t *);\r
-\r
- p_umv_buf->p_inout_buf = cl_zalloc (p_umv_buf->input_size);\r
- if (p_umv_buf->p_inout_buf == NULL)\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Failed to alloc memory for priv buffer\n"));\r
- status = IB_INSUFFICIENT_MEMORY;\r
- goto cleanup;\r
- }\r
- p_umv_buf->status = IB_SUCCESS;\r
- p_umv_buf->command = TRUE;\r
-\r
- cl_memcpy (p_umv_buf->p_inout_buf, &p_new_mw, p_umv_buf->input_size);\r
-\r
-cleanup:\r
- if (IB_SUCCESS != status)\r
- {\r
- if (p_new_mw)\r
- {\r
- cl_free (p_new_mw);\r
- }\r
- }\r
-\r
- FUNC_EXIT;\r
- return status;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_create_mw (\r
- IN const ib_pd_handle_t h_uvp_pd,\r
- IN ib_api_status_t ioctl_status,\r
- IN net32_t rkey,\r
- IN OUT ib_mw_handle_t *ph_uvp_mw,\r
- IN ci_umv_buf_t *p_umv_buf )\r
-{\r
- ib_api_status_t status;\r
- mlnx_ual_pd_info_t *p_pd_info = (mlnx_ual_pd_info_t *)((void*) h_uvp_pd);\r
- mlnx_ual_hobul_t *p_hobul;\r
- mlnx_ual_mw_info_t *p_new_mw;\r
-\r
- FUNC_ENTER;\r
- CL_ASSERT(p_umv_buf);\r
- CL_ASSERT(p_pd_info);\r
-\r
- p_hobul = p_pd_info->p_hobul;\r
- CL_ASSERT(p_hobul);\r
- \r
-\r
- status = ioctl_status;\r
-\r
- CL_ASSERT (p_umv_buf->p_inout_buf);\r
- cl_memcpy (&p_new_mw, p_umv_buf->p_inout_buf, p_umv_buf->input_size);\r
- \r
-\r
- *ph_uvp_mw = (ib_mw_handle_t) p_new_mw;\r
-\r
- if (IB_SUCCESS == status)\r
- {\r
- if (IB_SUCCESS != p_umv_buf->status) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Bad status %ld\n", p_umv_buf->status));\r
- status = p_umv_buf->status;\r
- goto cleanup;\r
- }\r
-\r
- p_new_mw->rkey = rkey;\r
-\r
- if (HH_OK !=\r
- THHUL_mwm_alloc_mw (p_hobul->hhul_hca_hndl,\r
- rkey,\r
- &p_new_mw->hhul_mw_hndl))\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("thhul_alloc_mw failed\n"));\r
- status = IB_ERROR;\r
- goto cleanup;\r
- }\r
- }\r
- else\r
- {\r
- cl_free (p_new_mw);\r
- }\r
-\r
-cleanup:\r
- cl_free (p_umv_buf->p_inout_buf);\r
- p_umv_buf->p_inout_buf = NULL;\r
-\r
- FUNC_EXIT;\r
- return;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_query_mw (\r
- IN const ib_mw_handle_t h_uvp_mw,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- FUNC_ENTER;\r
- CL_ASSERT(p_umv_buf);\r
- p_umv_buf->p_inout_buf = NULL;;\r
- p_umv_buf->input_size = 0;\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = IB_SUCCESS;\r
- p_umv_buf->command = TRUE;\r
- FUNC_EXIT;\r
- return IB_SUCCESS;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_query_mw (\r
- IN const ib_mw_handle_t h_uvp_mw,\r
- IN ib_api_status_t ioctl_status,\r
- IN net32_t rkey,\r
- OUT ib_pd_handle_t *ph_pd,\r
- IN ci_umv_buf_t *p_umv_buf )\r
-{\r
- FUNC_ENTER;\r
- *ph_pd = ((mlnx_ual_mw_info_t *)((void*)h_uvp_mw))->h_uvp_pd;\r
-\r
- FUNC_EXIT;\r
- return;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_destroy_mw (\r
- IN const ib_mw_handle_t h_uvp_mw)\r
-{\r
- FUNC_ENTER;\r
- FUNC_EXIT;\r
- return IB_SUCCESS;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_destroy_mw (\r
- IN const ib_mw_handle_t h_uvp_mw,\r
- IN ib_api_status_t ioctl_status)\r
-{\r
- ib_api_status_t status = IB_SUCCESS;\r
- mlnx_ual_pd_info_t *p_pd_info;\r
- mlnx_ual_hobul_t *p_hobul;\r
- mlnx_ual_mw_info_t *p_mw_info = (mlnx_ual_mw_info_t *)((void*) h_uvp_mw);\r
-\r
- FUNC_ENTER;\r
- CL_ASSERT(p_mw_info);\r
-\r
- p_pd_info = (mlnx_ual_pd_info_t *)((void*) p_mw_info->h_uvp_pd);\r
- CL_ASSERT(p_pd_info);\r
-\r
- p_hobul = p_pd_info->p_hobul;\r
- CL_ASSERT(p_hobul);\r
-\r
- if (HH_OK !=\r
- THHUL_mwm_free_mw (p_hobul->hhul_hca_hndl, p_mw_info->hhul_mw_hndl))\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("thhul_free_mw failed\n"));\r
- status = IB_ERROR;\r
- }\r
-\r
- if (status == IB_SUCCESS)\r
- {\r
- cl_free (p_mw_info);\r
- }\r
-\r
- FUNC_EXIT;\r
- return;\r
-}\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies, Inc. All rights reserved. \r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "mlnx_ual_main.h"\r
-\r
-//#define MTPERF\r
-#include <mtperf.h>\r
-//EZ: Hack could not find where defined?\r
-int PERF_time_this;\r
-MTPERF_EXTERN_SEGMENT(Perf_only_ibal);\r
-\r
-extern u_int32_t mlnx_dbg_lvl;\r
-\r
-void\r
-mlnx_get_osbypass_interface (\r
- IN OUT uvp_interface_t *p_uvp )\r
-{\r
-\r
- CL_ASSERT(p_uvp);\r
-\r
- /*\r
- * Work Request Processing Verbs\r
- * Should the types be same as Verbs?\r
- */\r
- p_uvp->post_send = mlnx_post_send;\r
- p_uvp->post_recv = mlnx_post_recv;\r
-\r
- /*\r
- * Completion Processing and \r
- * Completion Notification Request Verbs.\r
- * Should the types be same as Verbs?\r
- */\r
- p_uvp->poll_cq = mlnx_poll_cq;\r
- p_uvp->rearm_cq = mlnx_enable_cq_notify;\r
- p_uvp->rearm_n_cq = mlnx_enable_ncomp_cq_notify;\r
- p_uvp->peek_cq = mlnx_peek_cq;\r
-\r
- /* Memory window bind */\r
- p_uvp->bind_mw = mlnx_bind_mw;\r
-}\r
-\r
-\r
-static VAPI_mrw_acl_t\r
-map_itom_access_ctrl (\r
- IN ib_access_t i_acl)\r
-{\r
- VAPI_mrw_acl_t m_acl = 0;\r
-\r
- if (i_acl & IB_AC_RDMA_READ) m_acl |= VAPI_EN_REMOTE_READ;\r
- if (i_acl & IB_AC_RDMA_WRITE) m_acl |= VAPI_EN_REMOTE_WRITE;\r
- if (i_acl & IB_AC_ATOMIC) m_acl |= VAPI_EN_REMOTE_ATOM;\r
- if (i_acl & IB_AC_LOCAL_WRITE) m_acl |= VAPI_EN_LOCAL_WRITE;\r
- if (i_acl & IB_AC_MW_BIND) m_acl |= VAPI_EN_MEMREG_BIND;\r
-\r
- return m_acl;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_post_send (\r
- IN const void* __ptr64 h_qp,\r
- IN ib_send_wr_t* const p_send_wr,\r
- OUT ib_send_wr_t** pp_send_failure )\r
-{\r
- ib_api_status_t status = IB_SUCCESS;\r
- mlnx_ual_qp_info_t *p_qp_info = (mlnx_ual_qp_info_t *)((void*) h_qp);\r
- mlnx_ual_pd_info_t *p_pd_info;\r
- mlnx_ual_hobul_t *p_hobul;\r
-\r
- FUNC_ENTER;\r
- CL_ASSERT (p_qp_info);\r
-\r
- p_pd_info = (mlnx_ual_pd_info_t *)((void*) p_qp_info->h_uvp_pd);\r
- CL_ASSERT (p_pd_info);\r
-\r
- p_hobul = (mlnx_ual_hobul_t *) p_pd_info->p_hobul;\r
- CL_ASSERT (p_hobul);\r
-\r
- CL_ASSERT( p_send_wr );\r
-\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Send QP idx %x\n", p_qp_info->qp_idx));\r
- status = THHUL_qpm_post_send_wrs( p_hobul->hhul_hca_hndl,\r
- p_qp_info->hhul_qp_hndl,\r
- p_send_wr, \r
- pp_send_failure );\r
- if ( status != IB_SUCCESS )\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl, \r
- ("Post_send failed status %x\n", status));\r
- }\r
-\r
- FUNC_EXIT;\r
- return status;\r
-}\r
-\r
-\r
-ib_api_status_t \r
-mlnx_post_recv (\r
- IN const void* __ptr64 h_qp,\r
- IN ib_recv_wr_t* const p_recv_wr,\r
- OUT ib_recv_wr_t** pp_recv_failure )\r
-{\r
- ib_api_status_t status = IB_SUCCESS;\r
- mlnx_ual_qp_info_t *p_qp_info = (mlnx_ual_qp_info_t *)((void*) h_qp);\r
- mlnx_ual_pd_info_t *p_pd_info;\r
- mlnx_ual_hobul_t *p_hobul;\r
-\r
- FUNC_ENTER;\r
- CL_ASSERT (p_qp_info);\r
-\r
- p_pd_info = (mlnx_ual_pd_info_t *)((void*)p_qp_info->h_uvp_pd);\r
- CL_ASSERT (p_pd_info);\r
-\r
- p_hobul = (mlnx_ual_hobul_t *) p_pd_info->p_hobul;\r
- CL_ASSERT (p_hobul);\r
-\r
- CL_ASSERT( p_recv_wr );\r
-\r
- status = THHUL_qpm_post_recv_wrs( p_hobul->hhul_hca_hndl, p_qp_info->hhul_qp_hndl,\r
- p_recv_wr, pp_recv_failure );\r
- \r
- if ( status != IB_SUCCESS )\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl, \r
- ("Post_recv failed status %x\n", status));\r
- }\r
-\r
- FUNC_EXIT;\r
- return status;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_bind_mw (\r
- IN const ib_mw_handle_t h_uvp_mw,\r
- IN const ib_qp_handle_t h_uvp_qp,\r
- IN ib_bind_wr_t *p_mw_bind,\r
- OUT net32_t* const p_rkey )\r
-{\r
- ib_api_status_t status = IB_SUCCESS;\r
- HHUL_mw_bind_t m_bind_prop;\r
- HH_ret_t hh_ret;\r
- mlnx_ual_mw_info_t *p_mw_info = (mlnx_ual_mw_info_t *)((void*) h_uvp_mw);\r
- mlnx_ual_qp_info_t *p_qp_info = (mlnx_ual_qp_info_t *)((void*) h_uvp_qp);\r
- mlnx_ual_pd_info_t *p_pd_info;\r
- mlnx_ual_hobul_t *p_hobul;\r
- \r
-\r
- FUNC_ENTER;\r
- CL_ASSERT (p_mw_info);\r
- CL_ASSERT (p_qp_info);\r
-\r
- p_pd_info = (mlnx_ual_pd_info_t *)((void*) p_qp_info->h_uvp_pd);\r
- CL_ASSERT (p_pd_info);\r
-\r
- p_hobul = (mlnx_ual_hobul_t *) p_pd_info->p_hobul;\r
- CL_ASSERT (p_hobul);\r
-\r
- m_bind_prop.qp = p_qp_info->hhul_qp_hndl;\r
- m_bind_prop.id = p_mw_bind->wr_id;\r
- m_bind_prop.acl = map_itom_access_ctrl (p_mw_bind->access_ctrl);\r
- m_bind_prop.size = p_mw_bind->local_ds.length;\r
- m_bind_prop.start = (VAPI_virt_addr_t) (MT_virt_addr_t) \r
- p_mw_bind->local_ds.vaddr;\r
- m_bind_prop.mr_lkey = p_mw_bind->local_ds.lkey;\r
- m_bind_prop.comp_type = (p_mw_bind->send_opt & IB_SEND_OPT_SIGNALED) ?\r
- VAPI_SIGNALED : VAPI_UNSIGNALED;\r
-\r
- if (HH_OK !=\r
- (hh_ret = THHUL_mwm_bind_mw (p_hobul->hhul_hca_hndl,\r
- p_mw_info->hhul_mw_hndl,\r
- &m_bind_prop,\r
- p_rkey)))\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("thhul_bind_mw get error status %d\n", hh_ret));\r
- status = IB_ERROR;\r
- }\r
-\r
- FUNC_EXIT;\r
- return status;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_poll_cq (\r
- IN const void* __ptr64 h_cq,\r
- IN OUT ib_wc_t** const pp_free_wclist,\r
- OUT ib_wc_t** const pp_done_wclist )\r
-{\r
- ib_api_status_t status = IB_UNKNOWN_ERROR;\r
- mlnx_ual_hobul_t *p_hobul;\r
- mlnx_ual_cq_info_t *p_cq_info = (mlnx_ual_cq_info_t *)((void*) h_cq);\r
-\r
- FUNC_ENTER;\r
- CL_ASSERT (p_cq_info);\r
-\r
- p_hobul = (mlnx_ual_hobul_t *) p_cq_info->p_hobul;\r
- CL_ASSERT (p_hobul);\r
-\r
- if (!pp_free_wclist || !*pp_free_wclist || !pp_done_wclist)\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,("Passed in bad params\n"));\r
- status = IB_INVALID_PARAMETER;\r
- return status;\r
- }\r
-\r
- status = THHUL_cqm_poll4wc(p_hobul->hhul_hca_hndl, p_cq_info->hhul_cq_hndl,\r
- pp_free_wclist, pp_done_wclist );\r
-\r
- FUNC_EXIT;\r
- return status;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_enable_cq_notify (\r
- IN const void* __ptr64 h_cq,\r
- IN const boolean_t solicited )\r
-{\r
- ib_api_status_t status = IB_SUCCESS;\r
- mlnx_ual_hobul_t *p_hobul;\r
- mlnx_ual_cq_info_t *p_cq_info = (mlnx_ual_cq_info_t *)((void*) h_cq);\r
- HH_ret_t hh_ret;\r
- VAPI_cq_notif_type_t hh_request;\r
-\r
- FUNC_ENTER;\r
- CL_ASSERT (p_cq_info);\r
-\r
- p_hobul = (mlnx_ual_hobul_t *) p_cq_info->p_hobul;\r
- CL_ASSERT (p_hobul);\r
-\r
- hh_request = (solicited) ? VAPI_SOLIC_COMP : VAPI_NEXT_COMP;\r
-\r
- if (HH_OK !=\r
- (hh_ret = THHUL_cqm_req_comp_notif (p_hobul->hhul_hca_hndl,\r
- p_cq_info->hhul_cq_hndl,\r
- hh_request) ))\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("req_comp_notif return error status %d\n", hh_ret));\r
- status = IB_ERROR;\r
- }\r
-\r
- FUNC_EXIT;\r
- return status;\r
-}\r
-ib_api_status_t\r
-mlnx_enable_ncomp_cq_notify (\r
- IN const void* __ptr64 h_cq,\r
- IN const uint32_t n_cqes )\r
-{\r
- ib_api_status_t status = IB_SUCCESS;\r
- mlnx_ual_hobul_t *p_hobul;\r
- mlnx_ual_cq_info_t *p_cq_info = (mlnx_ual_cq_info_t *)((void*) h_cq);\r
- HH_ret_t hh_ret;\r
-\r
- FUNC_ENTER;\r
- CL_ASSERT (p_cq_info);\r
-\r
- p_hobul = (mlnx_ual_hobul_t *) p_cq_info->p_hobul;\r
- CL_ASSERT (p_hobul);\r
-\r
- hh_ret = THHUL_cqm_req_ncomp_notif(p_hobul->hhul_hca_hndl, p_cq_info->hhul_cq_hndl, n_cqes);\r
- if (hh_ret != HH_OK )\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("req_ncomp_notif return error status %d\n", hh_ret));\r
- status = IB_ERROR;\r
- }\r
-\r
- FUNC_EXIT;\r
- return status;\r
-}\r
-\r
-ib_api_status_t\r
-mlnx_peek_cq(\r
- IN const void* __ptr64 h_cq,\r
- OUT uint32_t* const p_n_cqes )\r
-{\r
- ib_api_status_t status = IB_UNKNOWN_ERROR;\r
- mlnx_ual_cq_info_t *p_cq_info = (mlnx_ual_cq_info_t *)((void*) h_cq);\r
- mlnx_ual_hobul_t *p_hobul;\r
-\r
- FUNC_ENTER;\r
-\r
- CL_ASSERT (p_cq_info);\r
- \r
- p_hobul = (mlnx_ual_hobul_t *)p_cq_info->p_hobul;\r
-\r
- CL_ASSERT (p_hobul);\r
- \r
- status = THHUL_cqm_count_cqe( p_hobul->hhul_hca_hndl, p_cq_info->hhul_cq_hndl, p_n_cqes );\r
-\r
- if( status != IB_SUCCESS )\r
- {\r
- CL_TRACE(MLNX_TRACE_LVL_1, mlnx_dbg_lvl, ("completes with ERROR status %d\n", status));\r
- }\r
-\r
- FUNC_EXIT;\r
- return status;\r
-\r
-}\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies, Inc. All rights reserved. \r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#include "mlnx_ual_main.h"\r
-\r
-extern u_int32_t mlnx_dbg_lvl;\r
-\r
-void\r
-mlnx_get_pd_interface (\r
- IN OUT uvp_interface_t *p_uvp )\r
-{\r
- FUNC_ENTER;\r
-\r
- CL_ASSERT(p_uvp);\r
-\r
- /*\r
- * Protection Domain\r
- */\r
- p_uvp->pre_allocate_pd = mlnx_pre_allocate_pd;\r
- p_uvp->post_allocate_pd = mlnx_post_allocate_pd;\r
- p_uvp->pre_deallocate_pd = mlnx_pre_deallocate_pd;\r
- p_uvp->post_deallocate_pd = mlnx_post_deallocate_pd;\r
-\r
- FUNC_EXIT;\r
-}\r
-\r
-\r
- \r
-ib_api_status_t\r
-mlnx_pre_allocate_pd (\r
- IN const ib_ca_handle_t h_uvp_ca,\r
- IN OUT ci_umv_buf_t *p_umv_buf,\r
- OUT ib_pd_handle_t *ph_uvp_pd)\r
-{\r
- ib_api_status_t status = IB_SUCCESS;\r
- mlnx_ual_hobul_t *p_hobul = (mlnx_ual_hobul_t *)((void *)h_uvp_ca);\r
- mlnx_ual_pd_info_t *p_new_pd = NULL;\r
- MT_size_t size;\r
-\r
- UNREFERENCED_PARAMETER(ph_uvp_pd);\r
-\r
- FUNC_ENTER;\r
-\r
- CL_ASSERT(p_hobul);\r
- CL_ASSERT(p_umv_buf);\r
-\r
- do \r
- {\r
- /* CA should be initialized */\r
- if (!p_hobul->p_hca_ul_info) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("INVALID hca_ul_info buffer\n"));\r
- status = IB_INVALID_CA_HANDLE;\r
- break;\r
- }\r
- \r
- /* Currently supporting multiple PDs per process */\r
- if (!p_hobul->p_hca_ul_resources) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("INVALID hca_ul_resources buffer\n"));\r
- status = IB_RESOURCE_BUSY;\r
- break;\r
- }\r
-\r
- p_new_pd = cl_zalloc (sizeof(mlnx_ual_pd_info_t));\r
- if (!p_new_pd) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Failed alloc new PD\n"));\r
- status = IB_INSUFFICIENT_MEMORY;\r
- break;\r
- }\r
-\r
- p_new_pd->p_pd_ul_resources = \r
- cl_zalloc(p_hobul->p_hca_ul_info->pd_ul_resources_sz);\r
- if (!p_new_pd->p_pd_ul_resources) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Failed alloc new PD UL resources\n"));\r
- status = IB_INSUFFICIENT_MEMORY;\r
- break;\r
- }\r
-\r
- if (HH_OK != \r
- THHUL_pdm_alloc_pd_avs_prep (p_hobul->hhul_hca_hndl,\r
- MLNX_MAX_AVS_PER_PD,\r
- PD_NO_FLAGS, // TBD \r
- &p_new_pd->hhul_pd_hndl,\r
- p_new_pd->p_pd_ul_resources))\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Calling THHUL_alloc_pd_prep Failed\n"));\r
- status = IB_RESOURCE_BUSY;\r
- break;\r
- }\r
- p_new_pd->p_hobul = p_hobul;\r
- \r
- size = p_hobul->p_hca_ul_info->pd_ul_resources_sz + \r
- sizeof (u_int32_t) + sizeof (mlnx_ual_pd_info_t *);\r
-\r
- p_umv_buf->p_inout_buf = cl_zalloc(size);\r
-\r
- if (!p_umv_buf->p_inout_buf)\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Failed alloc user private buffer\n"));\r
- status = IB_INSUFFICIENT_MEMORY;\r
- break;\r
- }\r
- p_umv_buf->command = TRUE;\r
- p_umv_buf->input_size = p_umv_buf->output_size = \r
- (uint32_t)size - sizeof (mlnx_ual_pd_info_t *); \r
- \r
- CL_TRACE (MLNX_TRACE_LVL_6, mlnx_dbg_lvl,\r
- ("umv_buf->input_size %ld, pd_ul_res_sz %d\n",\r
- p_umv_buf->input_size, \r
- p_hobul->p_hca_ul_info->pd_ul_resources_sz));\r
-\r
- cl_memcpy (p_umv_buf->p_inout_buf,\r
- p_new_pd->p_pd_ul_resources,\r
- p_hobul->p_hca_ul_info->pd_ul_resources_sz);\r
- cl_memcpy (( (u_int8_t *)p_umv_buf->p_inout_buf + size - \r
- sizeof (mlnx_ual_pd_info_t *)),\r
- &p_new_pd,\r
- sizeof (mlnx_ual_pd_info_t *));\r
- \r
- } while (0);\r
-\r
- /* \r
- * clean_up if required \r
- */\r
- if (IB_SUCCESS != status) \r
- {\r
- if (p_new_pd) \r
- {\r
- if (p_new_pd->p_pd_ul_resources);\r
- {\r
- cl_free (p_new_pd->p_pd_ul_resources);\r
-\r
- if (!p_umv_buf->p_inout_buf)\r
- {\r
- THHUL_pdm_free_pd_prep (p_hobul->hhul_hca_hndl, \r
- p_new_pd->hhul_pd_hndl, FALSE);\r
- THHUL_pdm_free_pd_done (p_hobul->hhul_hca_hndl, \r
- p_new_pd->hhul_pd_hndl);\r
- }\r
- }\r
- cl_free (p_new_pd);\r
- }\r
- }\r
- \r
- FUNC_EXIT;\r
- return status;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_allocate_pd (\r
- IN ib_ca_handle_t h_uvp_ca,\r
- IN ib_api_status_t ioctl_status,\r
- IN OUT ib_pd_handle_t *ph_uvp_pd,\r
- IN ci_umv_buf_t *p_umv_buf )\r
-{\r
- mlnx_ual_hobul_t *p_hobul = (mlnx_ual_hobul_t *)((void *)h_uvp_ca);\r
- mlnx_ual_pd_info_t *p_new_pd;\r
-\r
- MT_size_t size;\r
-\r
- FUNC_ENTER;\r
-\r
- CL_ASSERT(p_hobul);\r
- CL_ASSERT(p_umv_buf);\r
-\r
- size = p_hobul->p_hca_ul_info->pd_ul_resources_sz + \r
- sizeof (u_int32_t) + sizeof (mlnx_ual_pd_info_t *);\r
-\r
- cl_memcpy (&p_new_pd,\r
- ((u_int8_t *)p_umv_buf->p_inout_buf + size - \r
- sizeof (mlnx_ual_pd_info_t*)),\r
- sizeof (mlnx_ual_pd_info_t *));\r
- CL_ASSERT(p_new_pd);\r
- *ph_uvp_pd = (ib_pd_handle_t) p_new_pd;\r
-\r
- if ( ioctl_status == IB_SUCCESS )\r
- {\r
- if (IB_SUCCESS != p_umv_buf->status) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("post_allocate_pd return status %s\n", \r
- ib_get_err_str(p_umv_buf->status)));\r
- goto err;\r
- }\r
- else if ((size - sizeof (mlnx_ual_pd_info_t *)) != \r
- p_umv_buf->output_size )\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Bad user priv buffer size exp = %d, res = %ld\n",\r
- size, p_umv_buf->output_size));\r
- goto err;\r
- }\r
-\r
- cl_memcpy (p_new_pd->p_pd_ul_resources,\r
- p_umv_buf->p_inout_buf,\r
- p_hobul->p_hca_ul_info->pd_ul_resources_sz);\r
- cl_memcpy (&p_new_pd->pd_idx,\r
- ((u_int8_t *)p_umv_buf->p_inout_buf + \r
- p_hobul->p_hca_ul_info->pd_ul_resources_sz),\r
- sizeof (u_int32_t));\r
-\r
- if (HH_OK !=\r
- THHUL_pdm_alloc_pd_done (p_hobul->hhul_hca_hndl,\r
- p_new_pd->hhul_pd_hndl,\r
- p_new_pd->pd_idx,\r
- p_new_pd->p_pd_ul_resources))\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Call THHUL_pdm_alloc_pd_done Failed\n"));\r
- goto err;\r
- }\r
- }\r
- else\r
- {\r
-err:\r
- if (p_new_pd->p_pd_ul_resources)\r
- cl_free (p_new_pd->p_pd_ul_resources);\r
-\r
- cl_free (p_new_pd);\r
- *ph_uvp_pd = NULL;\r
- }\r
-\r
- cl_free (p_umv_buf->p_inout_buf);\r
-\r
- FUNC_EXIT;\r
- return;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_deallocate_pd (\r
- IN const ib_pd_handle_t h_uvp_pd)\r
-{\r
- ib_api_status_t status = IB_SUCCESS;\r
- mlnx_ual_pd_info_t *p_pd_info = (mlnx_ual_pd_info_t *)((void *)h_uvp_pd);\r
- mlnx_ual_hobul_t *p_hobul;\r
-\r
- FUNC_ENTER;\r
-\r
- CL_ASSERT(p_pd_info);\r
-\r
- p_hobul = p_pd_info->p_hobul;\r
- CL_ASSERT(p_hobul);\r
-\r
- do \r
- {\r
- if (!p_pd_info->p_pd_ul_resources) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("INVALID PD UL resources\n"));\r
- status = IB_INVALID_PD_HANDLE;\r
- break;\r
- }\r
-\r
- if (HH_OK != THHUL_pdm_free_pd_prep(p_hobul->hhul_hca_hndl, p_pd_info->hhul_pd_hndl, FALSE))\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Calling THHUL_free_pd_prep Failed\n"));\r
- status = IB_RESOURCE_BUSY;\r
- break;\r
- }\r
- } while (0);\r
- \r
- FUNC_EXIT;\r
- return IB_SUCCESS;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_deallocate_pd (\r
- IN const ib_pd_handle_t h_uvp_pd,\r
- IN ib_api_status_t ioctl_status )\r
-{\r
- mlnx_ual_pd_info_t *p_pd_info = (mlnx_ual_pd_info_t *)((void *)h_uvp_pd);\r
- mlnx_ual_hobul_t *p_hobul;\r
- UNREFERENCED_PARAMETER(ioctl_status);\r
-\r
- FUNC_ENTER;\r
- CL_ASSERT(p_pd_info);\r
-\r
- p_hobul = p_pd_info->p_hobul;\r
- CL_ASSERT(p_hobul);\r
-\r
- if (p_pd_info->p_pd_ul_resources) \r
- {\r
- cl_free (p_pd_info->p_pd_ul_resources );\r
- p_pd_info->p_pd_ul_resources = NULL; \r
- }\r
-\r
- THHUL_pdm_free_pd_done (p_hobul->hhul_hca_hndl, p_pd_info->hhul_pd_hndl); \r
- cl_free (p_pd_info);\r
- FUNC_EXIT;\r
- return;\r
-}\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies, Inc. All rights reserved. \r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "mlnx_ual_main.h"\r
-\r
-\r
-extern u_int32_t mlnx_dbg_lvl;\r
-\r
-void\r
-mlnx_get_qp_interface (\r
- IN OUT uvp_interface_t *p_uvp )\r
-{\r
- FUNC_ENTER;\r
-\r
- CL_ASSERT(p_uvp);\r
-\r
- /*\r
- * QP Management Verbs\r
- */\r
- p_uvp->pre_create_qp = mlnx_pre_create_qp;\r
- p_uvp->post_create_qp = mlnx_post_create_qp;\r
-\r
- // !!! none for create_spl_qp, UAL will return error !!!\r
-\r
- p_uvp->pre_modify_qp = mlnx_pre_modify_qp;\r
- p_uvp->post_modify_qp = mlnx_post_modify_qp;\r
- p_uvp->pre_query_qp = NULL;\r
- p_uvp->post_query_qp = mlnx_post_query_qp;\r
- p_uvp->pre_destroy_qp = mlnx_pre_destroy_qp;\r
- p_uvp->post_destroy_qp = mlnx_post_destroy_qp;\r
-\r
- FUNC_EXIT;\r
-}\r
-\r
-\r
-IB_ts_t\r
-map_ibal_qp_type (ib_qp_type_t ibal_qp_type)\r
-{\r
- if (ibal_qp_type == IB_QPT_RELIABLE_CONN) return IB_TS_RC;\r
- else if (ibal_qp_type == IB_QPT_UNRELIABLE_CONN) return IB_TS_UC;\r
- // else if (ibal_qp_type == IB_QPT_RELIABLE_DGRM) return IB_TS_RD;\r
- else if (ibal_qp_type == IB_QPT_UNRELIABLE_DGRM) return IB_TS_UD;\r
- else if (ibal_qp_type == IB_QPT_RAW_IPV6) return IB_TS_RAW;\r
- else if (ibal_qp_type == IB_QPT_RAW_ETHER) return IB_TS_RAW;\r
- else return IB_TS_UD;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_create_qp (\r
- IN const ib_pd_handle_t h_uvp_pd,\r
- IN const ib_qp_create_t *p_create_attr,\r
- IN OUT ci_umv_buf_t *p_umv_buf,\r
- OUT ib_qp_handle_t *ph_uvp_qp)\r
-{\r
- ib_api_status_t status = IB_SUCCESS;\r
- mlnx_ual_pd_info_t *p_pd_info = (mlnx_ual_pd_info_t *)((void *)h_uvp_pd);\r
- mlnx_ual_hobul_t *p_hobul;\r
- mlnx_ual_qp_info_t *p_new_qp = NULL;\r
- HHUL_qp_init_attr_t ul_qp_init_attr;\r
- MT_size_t size;\r
-\r
- UNREFERENCED_PARAMETER(ph_uvp_qp);\r
-\r
- FUNC_ENTER;\r
- CL_ASSERT(p_pd_info);\r
- CL_ASSERT(p_umv_buf);\r
- CL_ASSERT(p_create_attr);\r
-\r
- p_hobul = p_pd_info->p_hobul;\r
- CL_ASSERT(p_hobul);\r
-\r
- do \r
- {\r
- /* CA should be initialized */\r
- if (!p_hobul->p_hca_ul_info) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("INVALID hca_ul_info buffer\n"));\r
- status = IB_INVALID_CA_HANDLE;\r
- break;\r
- }\r
- \r
- if (!p_hobul->p_hca_ul_resources) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("INVALID hca_ul_resources buffer\n"));\r
- status = IB_RESOURCE_BUSY;\r
- break;\r
- }\r
-\r
- if (!p_pd_info->p_pd_ul_resources) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("INVALID pd_ul_resources buffer\n"));\r
- status = IB_RESOURCE_BUSY;\r
- break;\r
- }\r
-\r
- p_new_qp = cl_zalloc (sizeof(mlnx_ual_qp_info_t));\r
- if (!p_new_qp) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Failed alloc new QP\n"));\r
- status = IB_INSUFFICIENT_MEMORY;\r
- break;\r
- }\r
-\r
- p_new_qp->p_qp_ul_resources = \r
- cl_zalloc(p_hobul->p_hca_ul_info->qp_ul_resources_sz);\r
- if (!p_new_qp->p_qp_ul_resources) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Failed alloc new QP UL resources\n"));\r
- status = IB_INSUFFICIENT_MEMORY;\r
- break;\r
- }\r
-\r
- cl_memclr (&ul_qp_init_attr, sizeof (HHUL_qp_init_attr_t));\r
-\r
- ul_qp_init_attr.qp_cap.max_oust_wr_sq = p_create_attr->sq_depth;\r
- ul_qp_init_attr.qp_cap.max_oust_wr_rq = p_create_attr->rq_depth;\r
- ul_qp_init_attr.qp_cap.max_sg_size_sq = p_create_attr->sq_sge;\r
- ul_qp_init_attr.qp_cap.max_sg_size_rq = p_create_attr->rq_sge;\r
- ul_qp_init_attr.ts_type = map_ibal_qp_type (p_create_attr->qp_type);\r
- ul_qp_init_attr.srq = HHUL_INVAL_SRQ_HNDL;\r
- /*\r
- * save the qp_type to qp_info to use later on\r
- */\r
- p_new_qp->type = ul_qp_init_attr.ts_type;\r
- ul_qp_init_attr.sq_sig_type =\r
- (p_create_attr->sq_signaled) ? VAPI_SIGNAL_ALL_WR:VAPI_SIGNAL_REQ_WR;\r
- ul_qp_init_attr.rq_sig_type = VAPI_SIGNAL_ALL_WR;\r
- ul_qp_init_attr.pd = p_pd_info->hhul_pd_hndl; \r
- ul_qp_init_attr.sq_cq = \r
- ((mlnx_ual_cq_info_t *)(p_create_attr->h_sq_cq))->hhul_cq_hndl; \r
- ul_qp_init_attr.rq_cq = \r
- ((mlnx_ual_cq_info_t *)(p_create_attr->h_rq_cq))->hhul_cq_hndl; \r
-\r
- if (HH_OK != \r
- THHUL_qpm_create_qp_prep (p_hobul->hhul_hca_hndl,\r
- &ul_qp_init_attr,\r
- &p_new_qp->hhul_qp_hndl,\r
- &p_new_qp->ul_qp_cap,\r
- p_new_qp->p_qp_ul_resources))\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Calling THHUL_qpm_create_qp_prep Failed\n"));\r
- status = IB_RESOURCE_BUSY;\r
- break;\r
- }\r
-\r
- /* \r
- * Store the parent PD of this QP\r
- */ \r
- p_new_qp->h_uvp_pd = h_uvp_pd;\r
- \r
- size = p_hobul->p_hca_ul_info->qp_ul_resources_sz + \r
- sizeof (u_int32_t) + sizeof (mlnx_ual_qp_info_t *);\r
- p_umv_buf->p_inout_buf = cl_zalloc(size);\r
- if (!p_umv_buf->p_inout_buf)\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Failed alloc user private buffer\n"));\r
- status = IB_INSUFFICIENT_MEMORY;\r
- break;\r
- }\r
- \r
- /* \r
- * We only set the input_size up to qp_ul_resources_sz + sizeof (qp_idx)\r
- * The rest of the buffer we store the pointer to our allocated\r
- * qp_info struct in order to retrieve it later in the post.\r
- */\r
- p_umv_buf->input_size = p_umv_buf->output_size = \r
- (uint32_t)size - sizeof (mlnx_ual_qp_info_t *);\r
-\r
- cl_memcpy (p_umv_buf->p_inout_buf,\r
- p_new_qp->p_qp_ul_resources,\r
- p_hobul->p_hca_ul_info->qp_ul_resources_sz);\r
- /* \r
- * Store the pointer of our qp_info struct to inout_buf and retrieve\r
- * it later in the post\r
- */\r
- cl_memcpy ( ( (u_int8_t *)p_umv_buf->p_inout_buf + size - \r
- sizeof (mlnx_ual_qp_info_t *)),\r
- &p_new_qp,\r
- sizeof (mlnx_ual_qp_info_t *));\r
- p_umv_buf->command = TRUE;\r
- \r
- } while (0);\r
-\r
- /* \r
- * clean_up if required \r
- */\r
- if (IB_SUCCESS != status) \r
- {\r
- if (p_new_qp) \r
- {\r
- if (p_new_qp->hhul_qp_hndl)\r
- {\r
- THHUL_qpm_destroy_qp_done (p_hobul->hhul_hca_hndl, \r
- p_new_qp->hhul_qp_hndl);\r
- }\r
- if (p_new_qp->p_qp_ul_resources);\r
- {\r
- cl_free (p_new_qp->p_qp_ul_resources);\r
- }\r
- cl_free (p_new_qp);\r
- }\r
- if (p_umv_buf->p_inout_buf)\r
- {\r
- cl_free ( p_umv_buf->p_inout_buf );\r
- }\r
- }\r
-\r
- FUNC_EXIT;\r
- return IB_SUCCESS;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_post_create_qp (\r
- IN const ib_pd_handle_t h_uvp_pd,\r
- IN ib_api_status_t ioctl_status,\r
- IN OUT ib_qp_handle_t *ph_uvp_qp,\r
- IN ci_umv_buf_t *p_umv_buf )\r
-{\r
- mlnx_ual_pd_info_t *p_pd_info = (mlnx_ual_pd_info_t *)((void*)h_uvp_pd);\r
- mlnx_ual_hobul_t *p_hobul;\r
- mlnx_ual_qp_info_t *p_new_qp;\r
- MT_size_t buf_size;\r
- ib_api_status_t status = IB_SUCCESS;\r
- \r
- FUNC_ENTER;\r
- CL_ASSERT(p_pd_info);\r
- CL_ASSERT(p_umv_buf);\r
-\r
- p_hobul = p_pd_info->p_hobul;\r
- CL_ASSERT(p_hobul);\r
-\r
- buf_size = p_hobul->p_hca_ul_info->qp_ul_resources_sz + \r
- sizeof (u_int32_t) + sizeof (mlnx_ual_qp_info_t *);\r
-\r
- /* Retrieve our qp_info back from priv buffer */\r
- cl_memcpy (&p_new_qp, ((u_int8_t *)p_umv_buf->p_inout_buf + buf_size -\r
- sizeof (mlnx_ual_qp_info_t *)), sizeof (mlnx_ual_qp_info_t *));\r
- CL_ASSERT(p_new_qp);\r
-\r
- *ph_uvp_qp = (ib_qp_handle_t) p_new_qp;\r
-\r
- if ( ioctl_status == IB_SUCCESS )\r
- {\r
- if (IB_SUCCESS != p_umv_buf->status) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Bad status %ld\n", p_umv_buf->status));\r
- status = p_umv_buf->status;\r
- goto err;\r
- }\r
- else if ((buf_size - sizeof (mlnx_ual_qp_info_t *)) != \r
- p_umv_buf->output_size) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Bad user priv buffer size exp = %d, res = %ld\n",\r
- buf_size, p_umv_buf->output_size));\r
- status = IB_ERROR;\r
- goto err;\r
- }\r
-\r
- cl_memcpy (p_new_qp->p_qp_ul_resources,\r
- p_umv_buf->p_inout_buf,\r
- p_hobul->p_hca_ul_info->qp_ul_resources_sz);\r
-\r
- cl_memcpy (&p_new_qp->qp_idx,\r
- ((u_int8_t *)p_umv_buf->p_inout_buf + \r
- p_hobul->p_hca_ul_info->qp_ul_resources_sz),\r
- sizeof (u_int32_t));\r
-\r
- if (HH_OK !=\r
- THHUL_qpm_create_qp_done (p_hobul->hhul_hca_hndl,\r
- p_new_qp->hhul_qp_hndl,\r
- p_new_qp->qp_idx,\r
- p_new_qp->p_qp_ul_resources))\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Call THHUL_qpm_create_qp_done Failed\n"));\r
- status = IB_ERROR;\r
- goto err;\r
- }\r
-\r
- CL_TRACE (MLNX_TRACE_LVL_7, mlnx_dbg_lvl,\r
- ("Newly created QP qp_idx 0x%x\n",p_new_qp->qp_idx)); \r
- }\r
- else\r
- {\r
-err:\r
- if (p_new_qp->p_qp_ul_resources)\r
- cl_free (p_new_qp->p_qp_ul_resources);\r
-\r
- cl_free (p_new_qp);\r
- *ph_uvp_qp = NULL;\r
- }\r
-\r
- cl_free (p_umv_buf->p_inout_buf);\r
- p_umv_buf->p_inout_buf = NULL;\r
-\r
- FUNC_EXIT;\r
- return status;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_modify_qp (\r
- IN const ib_qp_handle_t h_uvp_qp,\r
- IN const ib_qp_mod_t *p_modify_attr,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- ib_api_status_t status = IB_SUCCESS;\r
- UNREFERENCED_PARAMETER(h_uvp_qp);\r
- UNREFERENCED_PARAMETER(p_modify_attr);\r
-\r
- FUNC_ENTER;\r
- CL_ASSERT(p_umv_buf);\r
-\r
- /*\r
- * Prepare the buffer to get the qp_state back\r
- */\r
- p_umv_buf->input_size = sizeof (VAPI_qp_state_t);\r
- p_umv_buf->output_size = p_umv_buf->input_size;\r
- p_umv_buf->command = TRUE;\r
- p_umv_buf->p_inout_buf = cl_zalloc (p_umv_buf->input_size);\r
- if (!p_umv_buf->p_inout_buf)\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Failed to allocate mem for priv buffer\n"));\r
- status = IB_INSUFFICIENT_MEMORY;\r
- }\r
- FUNC_EXIT;\r
- return status;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_modify_qp (\r
- IN const ib_qp_handle_t h_uvp_qp,\r
- IN ib_api_status_t ioctl_status,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- ib_api_status_t status;\r
- mlnx_ual_qp_info_t *p_qp_info = (mlnx_ual_qp_info_t *)((void *) h_uvp_qp);\r
- mlnx_ual_pd_info_t *p_pd_info;\r
- mlnx_ual_hobul_t *p_hobul;\r
- VAPI_qp_state_t cur_qp_state;\r
-\r
- FUNC_ENTER;\r
- CL_ASSERT(p_qp_info);\r
- CL_ASSERT(p_umv_buf);\r
-\r
- p_pd_info = (mlnx_ual_pd_info_t *)((void *) p_qp_info->h_uvp_pd);\r
- CL_ASSERT(p_pd_info);\r
- \r
- p_hobul = p_pd_info->p_hobul; \r
- CL_ASSERT(p_hobul);\r
-\r
- status = ioctl_status;\r
-\r
- do\r
- {\r
- if (IB_SUCCESS == status) \r
- {\r
- if (IB_SUCCESS != p_umv_buf->status) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Bad status %ld\n", p_umv_buf->status));\r
- status = p_umv_buf->status;\r
- break;\r
- }\r
- else if (sizeof (VAPI_qp_state_t) != p_umv_buf->output_size) \r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Bad user priv buffer size exp = %zd, res = %ld\n",\r
- sizeof (VAPI_qp_state_t), p_umv_buf->output_size));\r
- status = IB_ERROR;\r
- break;\r
- }\r
-\r
- cl_memcpy (&cur_qp_state,\r
- p_umv_buf->p_inout_buf,\r
- sizeof (VAPI_qp_state_t));\r
-\r
- CL_TRACE (MLNX_TRACE_LVL_6, mlnx_dbg_lvl,\r
- ("Committed to modify QP to state %d\n", cur_qp_state));\r
-\r
- if (HH_OK !=\r
- THHUL_qpm_modify_qp_done (p_hobul->hhul_hca_hndl,\r
- p_qp_info->hhul_qp_hndl,\r
- cur_qp_state))\r
- {\r
- status = IB_ERROR;\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("Call THHUL_qpm_modify_qp_done Failed\n"));\r
- break;\r
- }\r
- }\r
-\r
- } while (0);\r
-\r
- cl_free (p_umv_buf->p_inout_buf);\r
-\r
- FUNC_EXIT;\r
- return;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_query_qp (\r
- IN ib_qp_handle_t h_uvp_qp,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- UNREFERENCED_PARAMETER(h_uvp_qp);\r
- FUNC_ENTER;\r
- CL_ASSERT(p_umv_buf);\r
- p_umv_buf->p_inout_buf = NULL;\r
- p_umv_buf->input_size = 0;\r
- p_umv_buf->output_size = 0;\r
- p_umv_buf->status = IB_SUCCESS;\r
- p_umv_buf->command = TRUE;\r
- FUNC_EXIT;\r
- return IB_SUCCESS;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_query_qp (\r
- IN ib_qp_handle_t h_uvp_qp,\r
- IN ib_api_status_t ioctl_status,\r
- IN OUT ib_qp_attr_t *p_query_attr,\r
- IN OUT ci_umv_buf_t *p_umv_buf)\r
-{\r
- mlnx_ual_qp_info_t *p_qp_info = (mlnx_ual_qp_info_t *)((void *) h_uvp_qp);\r
-\r
- FUNC_ENTER;\r
-\r
- UNREFERENCED_PARAMETER(p_umv_buf);\r
-\r
- if( ioctl_status == IB_SUCCESS )\r
- {\r
- p_query_attr->sq_max_inline = p_qp_info->ul_qp_cap.max_inline_data_sq;\r
- p_query_attr->sq_sge = p_qp_info->ul_qp_cap.max_sg_size_sq;\r
- p_query_attr->sq_depth = p_qp_info->ul_qp_cap.max_oust_wr_sq;\r
- p_query_attr->rq_sge = p_qp_info->ul_qp_cap.max_sg_size_rq;\r
- p_query_attr->rq_depth = p_qp_info->ul_qp_cap.max_oust_wr_rq;\r
- }\r
-\r
- FUNC_EXIT;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-mlnx_pre_destroy_qp (\r
- IN const ib_qp_handle_t h_uvp_qp)\r
-{\r
- UNREFERENCED_PARAMETER(h_uvp_qp);\r
- FUNC_ENTER;\r
- FUNC_EXIT;\r
- return IB_SUCCESS;\r
-}\r
-\r
-\r
-void\r
-mlnx_post_destroy_qp (\r
- IN const ib_qp_handle_t h_uvp_qp,\r
- IN ib_api_status_t ioctl_status)\r
-{\r
- mlnx_ual_qp_info_t *p_qp_info = (mlnx_ual_qp_info_t *)((void *) h_uvp_qp);\r
- mlnx_ual_pd_info_t *p_pd_info;\r
- mlnx_ual_hobul_t *p_hobul;\r
-\r
- UNREFERENCED_PARAMETER(ioctl_status);\r
-\r
- FUNC_ENTER;\r
- CL_ASSERT(p_qp_info);\r
-\r
- p_pd_info = (mlnx_ual_pd_info_t *)((void *)p_qp_info->h_uvp_pd);\r
- CL_ASSERT(p_pd_info);\r
- \r
- p_hobul = p_pd_info->p_hobul; \r
- CL_ASSERT(p_hobul);\r
-\r
- if (HH_OK !=\r
- THHUL_qpm_destroy_qp_done (p_hobul->hhul_hca_hndl, \r
- p_qp_info->hhul_qp_hndl))\r
- {\r
- CL_TRACE (MLNX_TRACE_LVL_1, mlnx_dbg_lvl,\r
- ("THHUL_destroy_qp_done failed\n"));\r
- }\r
-\r
- if (p_qp_info->p_qp_ul_resources);\r
- {\r
- cl_free (p_qp_info->p_qp_ul_resources);\r
- p_qp_info->p_qp_ul_resources = NULL; \r
- }\r
-\r
- cl_free (p_qp_info);\r
-\r
- FUNC_EXIT;\r
- return;\r
-}\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#include <oib_ver.h>\r
-\r
-#define VER_FILETYPE VFT_DLL\r
-#define VER_FILESUBTYPE VFT2_UNKNOWN\r
-\r
-#ifdef _DEBUG_\r
-#define VER_FILEDESCRIPTION_STR "Tavor HCA User Mode Verb Provider (Debug)"\r
-#define VER_INTERNALNAME_STR "mt23108ud.dll"\r
-#define VER_ORIGINALFILENAME_STR "mt23108ud.dll"\r
-#else\r
-#define VER_FILEDESCRIPTION_STR "Tavor HCA User Mode Verb Provider"\r
-#define VER_INTERNALNAME_STR "mt23108u.dll"\r
-#define VER_ORIGINALFILENAME_STR "mt23108u.dll"\r
-#endif\r
-\r
-#include <common.ver>\r
-#if DBG\r
-LIBRARY mt23108ud.dll\r
-#else\r
-LIBRARY mt23108u.dll\r
-#endif\r
-\r
-#ifndef _WIN64\r
-EXPORTS\r
-uvp_get_interface\r
-#endif\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#define C_HH_C\r
-\r
-\r
-#include <hh.h>\r
-#include <hh_init.h>\r
-\r
-static HH_hca_dev_t HH_hca_dev_tbl[MAX_HCA_DEV_NUM];\r
-static HH_hca_dev_t* const devBegin = &HH_hca_dev_tbl[0];\r
-static HH_hca_dev_t* const devEnd = &HH_hca_dev_tbl[0] + MAX_HCA_DEV_NUM;\r
-\r
-static HH_if_ops_t invalid_ops;\r
-static HH_if_ops_t zombie_ops;\r
-\r
-/* forward declarations */\r
-static HH_hca_dev_t* find_free_dev(void);\r
-static void init_trivial_ops(void);\r
-\r
-\r
-/************************************************************************/\r
-/* To ease debugging, hook for trivial return statement.\r
- * Otherwise, calling stack Thru macros may be hard to get,\.\r
- */\r
-static inline HH_ret_t self_return(HH_ret_t rc)\r
-{ return rc; }\r
-\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t HH_add_hca_dev(\r
- HH_hca_dev_t* dev_info,\r
- HH_hca_hndl_t* hca_hndl_p\r
-)\r
-{\r
- HH_ret_t rc = HH_EAGAIN;\r
- HH_hca_dev_t* dev = find_free_dev();\r
- MTL_TRACE4(MT_FLFMT("HH_add_hca_dev"));\r
- if (dev != devEnd)\r
- {\r
- rc = HH_OK;\r
- *dev = *dev_info; /* the whole struct */\r
- MTL_DEBUG4(MT_FLFMT("dev=0x%p, desc=%s res_sz:{hca="SIZE_T_FMT", pd="SIZE_T_FMT", cq="SIZE_T_FMT", qp="SIZE_T_FMT"}"),\r
- dev, dev->dev_desc,\r
- dev->hca_ul_resources_sz, dev->pd_ul_resources_sz,\r
- dev->cq_ul_resources_sz, dev->qp_ul_resources_sz);\r
- *hca_hndl_p = dev;\r
- }\r
- return rc;\r
-} /* HH_add_hca_dev */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t HH_rem_hca_dev(HH_hca_hndl_t hca_hndl)\r
-{\r
- HH_ret_t rc = ((devBegin <= hca_hndl) && (hca_hndl < devEnd) &&\r
- (hca_hndl->if_ops != NULL)\r
- ? HH_OK : HH_ENODEV);\r
-/***TODO: There needs to be a method for reclaiming zombie entries.\r
-This is needed because the entries are marked as zombie when the HCA \r
-receives an IRP_MN_STOP_DEVICE IRP (which doesn't unload the driver),\r
-and a new entry is consumed when the device receives the\r
-IRP_MN_START_DEVICE IRP.\r
-***/\r
- if (rc == HH_OK)\r
- {\r
- hca_hndl->status = HH_HCA_STATUS_ZOMBIE;\r
- hca_hndl->if_ops = &zombie_ops;\r
- }\r
- return rc;\r
-} /* HH_rem_hca_dev */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t HH_list_hcas(u_int32_t buf_entries,\r
- u_int32_t* num_of_hcas_p,\r
- HH_hca_hndl_t* hca_list_buf_p)\r
-{\r
- HH_ret_t rc = ((hca_list_buf_p != NULL) || (buf_entries == 0)\r
- ? HH_OK : HH_EINVAL);\r
- u_int32_t nActual = 0;\r
- HH_hca_dev_t* dev = devBegin;\r
-\r
- MTL_DEBUG4(MT_FLFMT("HH_list_hcas: buf_entries=%d, N="VIRT_ADDR_FMT", devBegin=0x%p"), \r
- buf_entries, devEnd-devBegin, devBegin);\r
- for (; dev != devEnd; ++dev)\r
- {\r
- HH_if_ops_t* dev_if_ops = dev->if_ops;\r
- if ((dev_if_ops != &invalid_ops) && (dev_if_ops != &zombie_ops) )\r
- {\r
- if (buf_entries <= nActual) /* == even would be sufficient... */\r
- {\r
- hca_list_buf_p = NULL; /* user supplied buffer exceeded */\r
- rc = HH_EAGAIN;\r
- }\r
- ++nActual;\r
- if (hca_list_buf_p)\r
- {\r
- MTL_DEBUG4(MT_FLFMT("nActual=%d, dev=%p"), nActual, dev);\r
- *hca_list_buf_p++ = dev;\r
- MTL_DEBUG4(MT_FLFMT("dev=0x%p, res_sz:{hca="SIZE_T_FMT", pd="SIZE_T_FMT", cq="SIZE_T_FMT", qp="SIZE_T_FMT"}"),\r
- dev, dev->hca_ul_resources_sz, dev->pd_ul_resources_sz,\r
- dev->cq_ul_resources_sz, dev->qp_ul_resources_sz);\r
- }\r
- }\r
- }\r
- *num_of_hcas_p = nActual; /* valid result, even if rc != HH_OK */\r
- return rc;\r
-} /* HH_list_hcas */\r
-\r
-/************************************************************************/\r
-HH_ret_t HH_lookup_hca(const char * name, HH_hca_hndl_t* hca_handle_p)\r
-{\r
- HH_hca_dev_t* dev;\r
-\r
- if (!hca_handle_p)\r
- return HH_EINVAL;\r
-\r
- for (dev = devBegin; dev != devEnd; ++dev)\r
- {\r
- HH_if_ops_t* dev_if_ops = dev->if_ops;\r
- if ((dev_if_ops != &invalid_ops) && (dev_if_ops != &zombie_ops) )\r
- {\r
- if (!strcmp(name, dev->dev_desc)) {\r
- *hca_handle_p = dev;\r
- return HH_OK;\r
- }\r
- }\r
- }\r
- return HH_ENODEV;\r
-}\r
-\r
-/************************************************************************/\r
-/************************************************************************/\r
-/** Internal functions **/\r
-\r
-/************************************************************************/\r
-static HH_hca_dev_t* find_free_dev()\r
-{\r
- HH_hca_dev_t* dev = devBegin;\r
- while ((dev != devEnd) && (dev->if_ops != &invalid_ops))\r
- {\r
- ++dev;\r
- }\r
- MTL_TRACE4("%s[%d]%s(): devB=%p, devE=%p, dev=%p\n", \r
- __FILE__, __LINE__, __FUNCTION__, devBegin, devEnd, dev);\r
- return dev;\r
-} /* find_free_dev */\r
-\r
-\r
-#include "invalid.ic"\r
-#include "zombie.ic"\r
-#include "hhenosys.ic"\r
-\r
-/************************************************************************/\r
-void HH_ifops_tbl_set_enosys(HH_if_ops_t* tbl)\r
-{\r
- enosys_init(tbl);\r
-}\r
-\r
-\r
-/************************************************************************/\r
-static void init_trivial_ops(void)\r
-{\r
- static int beenThereDoneThat = 0;\r
- if (beenThereDoneThat == 0)\r
- {\r
- beenThereDoneThat = 1;\r
- invalid_init(&invalid_ops);\r
- zombie_init(&zombie_ops);\r
- }\r
-} /* init_trivial_ops */\r
-\r
-\r
-\r
-/* Dummy function */\r
-HH_ret_t HHIF_dummy()\r
-{\r
- return(HH_OK);\r
-}\r
-\r
-\r
-#ifdef MT_KERNEL\r
-\r
-\r
-MODULE_LICENSE("GPL");\r
-int init_hh_driver(void)\r
-{\r
- HH_hca_dev_t* dev = devBegin;\r
- MTL_TRACE('1', "%s: installing hh_mod\n", __FUNCTION__);\r
- init_trivial_ops();\r
- while (dev != devEnd)\r
- {\r
- dev->if_ops = &invalid_ops;\r
- ++dev;\r
- }\r
- return(0);\r
-}\r
-\r
-void cleanup_hh_driver(void)\r
-{\r
- MTL_TRACE('1', "%s: remove hh_mod\n", __FUNCTION__);\r
- return;\r
-}\r
-\r
-\r
-#if defined( __WIN__ )\r
-\r
-int HH_init_module(void)\r
-{\r
- return( init_hh_driver() );\r
-}\r
-\r
-void HH_cleanup_module(void)\r
-{\r
- cleanup_hh_driver();\r
-}\r
-\r
-#elif !defined( VXWORKS_OS )\r
-\r
-int init_module(void)\r
-{\r
- return(init_hh_driver());\r
-}\r
-\r
-void cleanup_module(void)\r
-{\r
- cleanup_hh_driver();\r
- return;\r
-}\r
-\r
-#endif\r
-\r
-#endif\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_HH_H\r
-#define H_HH_H\r
-\r
-#include <mtl_common.h>\r
-#include <ib_defs.h>\r
-#include <vapi_types.h>\r
-#include <hh_common.h>\r
-#include <mosal.h>\r
-\r
-/*\r
- * Global defines\r
- *\r
- */\r
-\r
-\r
-/*\r
- * Typedefs\r
- *\r
- */\r
-\r
-typedef enum\r
-{\r
- HH_HCA_STATUS_INVALID, /* Invalid context entry */\r
- HH_HCA_STATUS_ZOMBIE, /* HCA was removed but still has outstanding resources */\r
- HH_HCA_STATUS_CLOSED,\r
- HH_HCA_STATUS_OPENED\r
-} HH_hca_status_t;\r
-\r
-\r
-/*\r
- * Device information (public object/context)\r
- *\r
- */\r
-#pragma warning( disable : 4201 )\r
-typedef struct HH_hca_dev_st {\r
- char * __ptr64 dev_desc; /* Device description (name, etc.) */\r
- char * __ptr64 user_lib; /* User level library (dyn-link) */\r
- u_int32_t vendor_id; /* IEEE's 24 bit Device Vendor ID */\r
- u_int32_t dev_id; /* Device ID */\r
- u_int32_t hw_ver; /* Hardware version (step/rev) */\r
- u_int64_t fw_ver;\r
- struct hh_if_ops* __ptr64 if_ops; /* Interface operations */\r
-\r
- /* Size (bytes) of user-level ... */\r
- union\r
- {\r
- MT_size_t hca_ul_resources_sz; /* .. resources context for an HCA */\r
- void* __ptr64 resv0;\r
- };\r
- union\r
- {\r
- MT_size_t pd_ul_resources_sz; /* .. resources context for a PD */\r
- void* __ptr64 resv1;\r
- };\r
- union\r
- {\r
- MT_size_t cq_ul_resources_sz; /* .. resources context for a CQ */\r
- void* __ptr64 resv2;\r
- };\r
- union\r
- {\r
- MT_size_t srq_ul_resources_sz; /* .. resources context for a SRQ */\r
- void* __ptr64 resv3;\r
- };\r
- union\r
- {\r
- MT_size_t qp_ul_resources_sz; /* .. resources context for a QP */\r
- void* __ptr64 resv4;\r
- };\r
-\r
- void* __ptr64 device; /* Device private data */\r
- HH_hca_status_t status; /* Device Status */\r
-} HH_hca_dev_t;\r
-#pragma warning( default : 4201 )\r
-\r
-typedef enum {\r
- HH_TPT_PAGE,\r
- HH_TPT_BUF,\r
- HH_TPT_IOBUF} HH_tpt_type_t;\r
-\r
-typedef struct {\r
-\r
- HH_tpt_type_t tpt_type;\r
-\r
- MT_size_t num_entries; /* Num. of entries */\r
- union {\r
- struct {\r
- VAPI_phy_addr_t *phys_page_lst; /* Array of physical addrs. per page */\r
- u_int8_t page_shift; /* log2 page size in this page list */\r
- } page_lst;\r
- struct {\r
- VAPI_phy_addr_t *phys_buf_lst; /* Array of physical addrs. per buffer (sys page-sz aligned) */\r
- VAPI_size_t *buf_sz_lst; /* Size of each buffer (sys page-sz multiple) */\r
- VAPI_phy_addr_t iova_offset; /* Offset of start IOVA in first buffer */\r
- } buf_lst;\r
- MOSAL_iobuf_t iobuf; /* HH_TPT_IOBUF */\r
- } tpt;\r
-} HH_tpt_t;\r
-\r
-\r
-typedef struct HH_mr_st { /* Memory region registration data */\r
- IB_virt_addr_t start; /* Start virtual address (byte addressing) */\r
- VAPI_size_t size; /* Size in bytes */\r
- HH_pd_hndl_t pd; /* PD handle for new memory region */\r
- VAPI_mrw_acl_t acl; /* Access control (R/W permission local/remote */\r
- HH_tpt_t tpt; /* TPT - physical addresses list */\r
-} HH_mr_t;\r
-\r
-\r
-typedef struct HH_smr_st { /* Shared Memory region registration data */\r
- VAPI_lkey_t lkey; /* L-Key of the region to share with */\r
- IB_virt_addr_t start; /* This region start virtual addr */\r
- HH_pd_hndl_t pd ; /* PD handle for new memory region */\r
- VAPI_mrw_acl_t acl; /* Access control (R/W permission local/remote */\r
-} HH_smr_t;\r
-\r
-\r
-typedef struct HH_mr_info_st {\r
- VAPI_lkey_t lkey; /* Local region key */\r
- VAPI_rkey_t rkey; /* Remote region key */\r
- IB_virt_addr_t local_start; /* Actual enforce local access lower limit */\r
- VAPI_size_t local_size; /* Actual enforce size for local access */\r
- IB_virt_addr_t remote_start; /* Actual enforce remote access lower limit\r
- * (volid only if remote access allowed */\r
- VAPI_size_t remote_size; /* Actual enforce size for remote access\r
- * (volid only if remote access allowed */\r
- HH_pd_hndl_t pd; /* PD handle for new memory region */\r
- VAPI_mrw_acl_t acl; /* Access control (R/W local/remote */\r
-} HH_mr_info_t;\r
-\r
-\r
-\r
-/*\r
- * Queue Pairs\r
- *\r
- */\r
-\r
-/* Initial Attributes passed during creation */\r
-typedef struct HH_qp_init_attr_st {\r
- VAPI_ts_type_t ts_type; /* Transport Type */\r
- HH_pd_hndl_t pd; /* Protection Domain for this QP */\r
- HH_rdd_hndl_t rdd; /* Reliable Datagram Domain (RD only) */\r
- HH_srq_hndl_t srq;\r
- \r
- HH_cq_hndl_t sq_cq; /* Send Queue Completion Queue Number */\r
- HH_cq_hndl_t rq_cq; /* Receive Queue Completion Queue Number */\r
- \r
- VAPI_sig_type_t sq_sig_type; /* Signal Type for Send Queue */\r
- VAPI_sig_type_t rq_sig_type; /* Signal Type for Receive Queue */\r
-\r
- VAPI_qp_cap_t qp_cap; /* Capabilities (Max(outstand)+max(S/G)) */\r
-\r
-} HH_qp_init_attr_t;\r
-\r
-\r
-/* HH Event Records */\r
-typedef struct {\r
- VAPI_event_record_type_t etype; /* event record type - see vapi.h */\r
- VAPI_event_syndrome_t syndrome; /* syndrome value (for fatal error) */\r
- union { \r
- IB_wqpn_t qpn; /* Affiliated QP Number */\r
- HH_srq_hndl_t srq; /* Affiliated SRQ handle */\r
- IB_eecn_t eecn; /* Affiliated EEC Number */\r
- HH_cq_hndl_t cq; /* Affiliated CQ handle */\r
- IB_port_t port; /* Affiliated Port Number */\r
- } event_modifier;\r
-} HH_event_record_t;\r
-\r
-\r
-typedef void (*HH_async_eventh_t)(HH_hca_hndl_t, \r
- HH_event_record_t *, \r
- void* private_context);\r
-typedef void (*HH_comp_eventh_t)(HH_hca_hndl_t, \r
- HH_cq_hndl_t, \r
- void* private_context);\r
-\r
-/***************************/\r
-/* HH API Function mapping */\r
-/***************************/\r
-\r
-\r
-typedef struct hh_if_ops {\r
-\r
- /* Global HCA resources */\r
- /************************/\r
-\r
- HH_ret_t (*HHIF_open_hca)(HH_hca_hndl_t hca_hndl,\r
- EVAPI_hca_profile_t *prop_props_p,\r
- EVAPI_hca_profile_t *sugg_props_p);\r
-\r
- HH_ret_t (*HHIF_close_hca)(HH_hca_hndl_t hca_hndl);\r
-\r
- HH_ret_t (*HHIF_alloc_ul_resources)(HH_hca_hndl_t hca_hndl,\r
- MOSAL_protection_ctx_t user_protection_context,\r
- void* hca_ul_resources_p);\r
-\r
- HH_ret_t (*HHIF_free_ul_resources)(HH_hca_hndl_t hca_hndl,\r
- void* hca_ul_resources_p);\r
-\r
- HH_ret_t (*HHIF_query_hca)(HH_hca_hndl_t hca_hndl,\r
- VAPI_hca_cap_t* hca_cap_p);\r
-\r
- HH_ret_t (*HHIF_modify_hca)(HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- VAPI_hca_attr_t* hca_attr_p,\r
- VAPI_hca_attr_mask_t* hca_attr_mask_p);\r
-\r
- HH_ret_t (*HHIF_query_port_prop)(HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- VAPI_hca_port_t* hca_port_p);\r
-\r
- HH_ret_t (*HHIF_get_pkey_tbl)(HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- u_int16_t tbl_len_in,\r
- u_int16_t* tbl_len_out,\r
- IB_pkey_t* pkey_tbl_p);\r
-\r
- HH_ret_t (*HHIF_get_gid_tbl)(HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- u_int16_t tbl_len_in,\r
- u_int16_t* tbl_len_out,\r
- IB_gid_t* gid_tbl_p);\r
-\r
- HH_ret_t (*HHIF_get_lid)(HH_hca_hndl_t hca_hndl,\r
- IB_port_t port,\r
- IB_lid_t* lid_p,\r
- u_int8_t* lmc_p);\r
-\r
-\r
- /* Protection Domain */\r
- /*********************/\r
-\r
- HH_ret_t (*HHIF_alloc_pd)(HH_hca_hndl_t hca_hndl, \r
- MOSAL_protection_ctx_t prot_ctx, \r
- void * pd_ul_resources_p, \r
- HH_pd_hndl_t *pd_num_p);\r
-\r
- HH_ret_t (*HHIF_free_pd)(HH_hca_hndl_t hca_hndl,\r
- HH_pd_hndl_t pd);\r
-\r
-\r
- /* Reliable Datagram Domain */\r
- /****************************/\r
-\r
- HH_ret_t (*HHIF_alloc_rdd)(HH_hca_hndl_t hca_hndl,\r
- HH_rdd_hndl_t* rdd_p);\r
-\r
- HH_ret_t (*HHIF_free_rdd)(HH_hca_hndl_t hca_hndl,\r
- HH_rdd_hndl_t rdd);\r
-\r
-\r
- /* Privileged UD AV */\r
- /********************/\r
-\r
- HH_ret_t (*HHIF_create_priv_ud_av)(HH_hca_hndl_t hca_hndl,\r
- HH_pd_hndl_t pd,\r
- VAPI_ud_av_t* av_p,\r
- HH_ud_av_hndl_t* ah_p);\r
-\r
- HH_ret_t (*HHIF_modify_priv_ud_av)(HH_hca_hndl_t hca_hndl,\r
- HH_ud_av_hndl_t ah,\r
- VAPI_ud_av_t* av_p);\r
-\r
- HH_ret_t (*HHIF_query_priv_ud_av)(HH_hca_hndl_t hca_hndl,\r
- HH_ud_av_hndl_t ah,\r
- VAPI_ud_av_t* av_p);\r
-\r
- HH_ret_t (*HHIF_destroy_priv_ud_av)(HH_hca_hndl_t hca_hndl,\r
- HH_ud_av_hndl_t ah);\r
-\r
-\r
- /* Memory Regions/Windows */\r
- /**************************/\r
-\r
- HH_ret_t (*HHIF_register_mr)(HH_hca_hndl_t hca_hndl,\r
- HH_mr_t* mr_props_p,\r
- VAPI_lkey_t* lkey_p,\r
- IB_rkey_t* rkey_p);\r
-\r
- HH_ret_t (*HHIF_reregister_mr)(HH_hca_hndl_t hca_hndl,\r
- VAPI_lkey_t lkey,\r
- VAPI_mr_change_t change_mask,\r
- HH_mr_t* mr_props_p,\r
- VAPI_lkey_t* lkey_p,\r
- IB_rkey_t* rkey_p);\r
-\r
- HH_ret_t (*HHIF_register_smr)(HH_hca_hndl_t hca_hndl,\r
- HH_smr_t* smr_props_p,\r
- VAPI_lkey_t* lkey_p,\r
- IB_rkey_t* rkey_p);\r
-\r
- HH_ret_t (*HHIF_deregister_mr)(HH_hca_hndl_t hca_hndl,\r
- VAPI_lkey_t lkey);\r
-\r
- HH_ret_t (*HHIF_query_mr)(HH_hca_hndl_t hca_hndl,\r
- VAPI_lkey_t lkey,\r
- HH_mr_info_t* mr_info_p);\r
-\r
- HH_ret_t (*HHIF_alloc_mw)(HH_hca_hndl_t hca_hndl,\r
- HH_pd_hndl_t pd,\r
- IB_rkey_t* initial_rkey_p);\r
-\r
- HH_ret_t (*HHIF_query_mw)(HH_hca_hndl_t hca_hndl,\r
- IB_rkey_t initial_rkey, \r
- IB_rkey_t* current_rkey_p,\r
- HH_pd_hndl_t *pd);\r
-\r
- HH_ret_t (*HHIF_free_mw)(HH_hca_hndl_t hca_hndl,\r
- IB_rkey_t initial_rkey);\r
-\r
- /* Fast Memory Regions */\r
- /***********************/\r
- HH_ret_t (*HHIF_alloc_fmr)(HH_hca_hndl_t hca_hndl,\r
- HH_pd_hndl_t pd,\r
- VAPI_mrw_acl_t acl, \r
- MT_size_t max_pages, /* Maximum number of pages that can be mapped using this region */\r
- u_int8_t log2_page_sz, /* Fixed page size for all maps on a given FMR */\r
- VAPI_lkey_t* last_lkey_p); /* To be used as the initial FMR handle */\r
-\r
- HH_ret_t (*HHIF_map_fmr)(HH_hca_hndl_t hca_hndl,\r
- VAPI_lkey_t last_lkey,\r
- EVAPI_fmr_map_t* map_p,\r
- VAPI_lkey_t* lkey_p,\r
- IB_rkey_t* rkey_p);\r
- \r
- HH_ret_t (*HHIF_unmap_fmr)(HH_hca_hndl_t hca_hndl,\r
- u_int32_t num_of_fmrs_to_unmap,\r
- VAPI_lkey_t* last_lkeys_array);\r
-\r
- HH_ret_t (*HHIF_free_fmr)(HH_hca_hndl_t hca_hndl,\r
- VAPI_lkey_t last_lkey); /* as returned on last successful mapping operation */\r
-\r
-\r
- /* Completion Queues */\r
- /*********************/\r
-\r
- HH_ret_t (*HHIF_create_cq)(HH_hca_hndl_t hca_hndl,\r
- MOSAL_protection_ctx_t user_protection_context,\r
- void* cq_ul_resources_p,\r
- HH_cq_hndl_t* cq);\r
-\r
- HH_ret_t (*HHIF_resize_cq)(HH_hca_hndl_t hca_hndl,\r
- HH_cq_hndl_t cq,\r
- void* cq_ul_resources_p);\r
-\r
- HH_ret_t (*HHIF_query_cq)(HH_hca_hndl_t hca_hndl,\r
- HH_cq_hndl_t cq,\r
- VAPI_cqe_num_t* num_o_cqes_p);\r
-\r
- HH_ret_t (*HHIF_destroy_cq)(HH_hca_hndl_t hca_hndl,\r
- HH_cq_hndl_t cq);\r
-\r
-\r
-#if defined(MT_SUSPEND_QP)\r
- HH_ret_t (*HHIF_suspend_cq)(HH_hca_hndl_t hca_hndl,\r
- HH_cq_hndl_t cq,\r
- MT_bool do_suspend);\r
-#endif\r
-\r
- /* Queue Pairs */\r
- /***************/\r
-\r
- HH_ret_t (*HHIF_create_qp)(HH_hca_hndl_t hca_hndl,\r
- HH_qp_init_attr_t* init_attr_p,\r
- void* qp_ul_resources_p,\r
- IB_wqpn_t* qpn_p);\r
-\r
- HH_ret_t (*HHIF_get_special_qp)(HH_hca_hndl_t hca_hndl,\r
- VAPI_special_qp_t qp_type,\r
- IB_port_t port,\r
- HH_qp_init_attr_t* init_attr_p,\r
- void* qp_ul_resources_p,\r
- IB_wqpn_t* sqp_hndl_p);\r
-\r
- HH_ret_t (*HHIF_modify_qp)(HH_hca_hndl_t hca_hndl,\r
- IB_wqpn_t qpn,\r
- VAPI_qp_state_t cur_qp_state,\r
- VAPI_qp_attr_t* qp_attr_p,\r
- VAPI_qp_attr_mask_t* qp_attr_mask_p);\r
-\r
- HH_ret_t (*HHIF_query_qp)(HH_hca_hndl_t hca_hndl,\r
- IB_wqpn_t qp_num,\r
- VAPI_qp_attr_t* qp_attr_p);\r
-\r
- HH_ret_t (*HHIF_destroy_qp)(HH_hca_hndl_t hca_hndl,\r
- IB_wqpn_t qp_num);\r
-\r
-#if defined(MT_SUSPEND_QP)\r
- HH_ret_t (*HHIF_suspend_qp)(HH_hca_hndl_t hca_hndl,\r
- IB_wqpn_t qp_num,\r
- MT_bool suspend_flag);\r
-#endif\r
-\r
- \r
- /* Shared Receive Queue (SRQ) */\r
- /******************************/\r
-\r
- HH_ret_t (*HHIF_create_srq)(HH_hca_hndl_t hca_hndl,\r
- HH_pd_hndl_t pd, \r
- void *srq_ul_resources_p, \r
- HH_srq_hndl_t *srq_p);\r
-\r
- HH_ret_t (*HHIF_query_srq)(HH_hca_hndl_t hca_hndl,\r
- HH_srq_hndl_t srq,\r
- u_int32_t *limit_p);\r
-\r
- HH_ret_t (*HHIF_modify_srq)(HH_hca_hndl_t hca_hndl,\r
- HH_srq_hndl_t srq,\r
- void *srq_ul_resources_p);\r
- \r
- HH_ret_t (*HHIF_destroy_srq)(HH_hca_hndl_t hca_hndl,\r
- HH_srq_hndl_t srq);\r
- \r
-\r
- /* End to End Context */\r
- /**********************/\r
-\r
- HH_ret_t (*HHIF_create_eec)(HH_hca_hndl_t hca_hndl,\r
- HH_rdd_hndl_t rdd,\r
- IB_eecn_t* eecn_p);\r
-\r
- HH_ret_t (*HHIF_modify_eec)(HH_hca_hndl_t hca_hndl,\r
- IB_eecn_t eecn,\r
- VAPI_qp_state_t cur_ee_state,\r
- VAPI_qp_attr_t* ee_attr_p,\r
- VAPI_qp_attr_mask_t* ee_attr_mask_p);\r
-\r
- HH_ret_t (*HHIF_query_eec)(HH_hca_hndl_t hca_hndl,\r
- IB_eecn_t eecn,\r
- VAPI_qp_attr_t* ee_attr_p);\r
-\r
- HH_ret_t (*HHIF_destroy_eec)(HH_hca_hndl_t hca_hndl,\r
- IB_eecn_t eecn);\r
-\r
-\r
- /* Event Handler Calls */\r
- /***********************/\r
-\r
- HH_ret_t (*HHIF_set_async_eventh)(HH_hca_hndl_t hca_hndl,\r
- HH_async_eventh_t handler,\r
- void* private_context);\r
-\r
- HH_ret_t (*HHIF_set_comp_eventh)(HH_hca_hndl_t hca_hndl,\r
- HH_comp_eventh_t handler,\r
- void* private_context);\r
-\r
-\r
- /* Multicast Groups */\r
- /********************/\r
-\r
- HH_ret_t (*HHIF_attach_to_multicast)(HH_hca_hndl_t hca_hndl,\r
- IB_wqpn_t qpn,\r
- IB_gid_t dgid);\r
-\r
- HH_ret_t (*HHIF_detach_from_multicast)(HH_hca_hndl_t hca_hndl,\r
- IB_wqpn_t qpn,\r
- IB_gid_t dgid);\r
-\r
-\r
- /* Local MAD processing */\r
- HH_ret_t (*HHIF_process_local_mad)(HH_hca_hndl_t hca_hndl,\r
- IB_port_t port,\r
- IB_lid_t slid,\r
- EVAPI_proc_mad_opt_t proc_mad_opts,\r
- void* mad_in_p,\r
- void* mad_out_p);\r
- \r
-\r
- HH_ret_t (*HHIF_ddrmm_alloc)(HH_hca_hndl_t hca_hndl,\r
- VAPI_size_t size, \r
- u_int8_t align_shift,\r
- VAPI_phy_addr_t* buf_p);\r
-\r
- HH_ret_t (*HHIF_ddrmm_query)(HH_hca_hndl_t hca_hndl, \r
- u_int8_t align_shift,\r
- VAPI_size_t* total_mem, \r
- VAPI_size_t* free_mem, \r
- VAPI_size_t* largest_chunk, \r
- VAPI_phy_addr_t* largest_free_addr_p);\r
-\r
-\r
- HH_ret_t (*HHIF_ddrmm_free)(HH_hca_hndl_t hca_hndl,\r
- VAPI_phy_addr_t buf, \r
- VAPI_size_t size);\r
-\r
-\r
-} HH_if_ops_t;\r
-\r
-\r
-/*\r
- * HH Functions mapping definition\r
- */\r
-\r
-\r
-/* Global HCA resources */\r
-/************************/\r
-#define HH_open_hca(hca_hndl, prop_props_p, sugg_props_p) \\r
- (hca_hndl)->if_ops->HHIF_open_hca(hca_hndl, prop_props_p, sugg_props_p)\r
-\r
-#define HH_close_hca(hca_hndl) \\r
- (hca_hndl)->if_ops->HHIF_close_hca(hca_hndl)\r
-\r
-#define HH_alloc_ul_resources(hca_hndl, usr_prot_ctx, hca_ul_resources_p) \\r
- (hca_hndl)->if_ops->HHIF_alloc_ul_resources(hca_hndl, usr_prot_ctx, hca_ul_resources_p)\r
-\r
-#define HH_free_ul_resources(hca_hndl, hca_ul_resources_p) \\r
- (hca_hndl)->if_ops->HHIF_free_ul_resources(hca_hndl, hca_ul_resources_p)\r
-\r
-#define HH_query_hca(hca_hndl, hca_cap_p) \\r
- (hca_hndl)->if_ops->HHIF_query_hca(hca_hndl, hca_cap_p)\r
-\r
-#define HH_modify_hca(\\r
- hca_hndl, port_num, hca_attr_p, hca_attr_mask_p) \\r
- (hca_hndl)->if_ops->HHIF_modify_hca(\\r
- hca_hndl, port_num, hca_attr_p, hca_attr_mask_p)\r
-\r
-#define HH_query_port_prop(hca_hndl, port_num, hca_port_p) \\r
- (hca_hndl)->if_ops->HHIF_query_port_prop(hca_hndl, port_num, hca_port_p)\r
-\r
-#define HH_get_pkey_tbl(\\r
- hca_hndl, port_num, tbl_len_in, tbl_len_out, pkey_tbl_p) \\r
- (hca_hndl)->if_ops->HHIF_get_pkey_tbl(\\r
- hca_hndl, port_num, tbl_len_in, tbl_len_out, pkey_tbl_p)\r
-\r
-#define HH_get_gid_tbl(\\r
- hca_hndl, port_num, tbl_len_in, tbl_len_out, pkey_tbl_p) \\r
- (hca_hndl)->if_ops->HHIF_get_gid_tbl(\\r
- hca_hndl, port_num, tbl_len_in, tbl_len_out, pkey_tbl_p)\r
-\r
-#define HH_get_lid(\\r
- hca_hndl, port, lid_p, lmc_p) \\r
- (hca_hndl)->if_ops->HHIF_get_lid(\\r
- hca_hndl, port, lid_p, lmc_p)\r
-\r
-\r
-\r
-/* Protection Domain */\r
-/*********************/\r
-#define HH_alloc_pd(hca_hndl, prot_ctx, pd_ul_resources_p, pd_num_p) \\r
- (hca_hndl)->if_ops->HHIF_alloc_pd(hca_hndl, prot_ctx, pd_ul_resources_p, pd_num_p)\r
-\r
-#define HH_free_pd(hca_hndl, pd) \\r
- (hca_hndl)->if_ops->HHIF_free_pd(hca_hndl, pd)\r
-\r
-\r
-\r
-/* Reliable Datagram Domain */\r
-/****************************/\r
-#define HH_alloc_rdd(hca_hndl, rdd_p) \\r
- (hca_hndl)->if_ops->HHIF_alloc_rdd(hca_hndl, rdd_p)\r
-\r
-#define HH_free_rdd(hca_hndl, rdd) \\r
- (hca_hndl)->if_ops->HHIF_free_rdd(hca_hndl, rdd)\r
-\r
-\r
-\r
-/* Privileged UD AV */\r
-/********************/\r
-#define HH_create_priv_ud_av(hca_hndl, pd, av_p, ah_p) \\r
- (hca_hndl)->if_ops->HHIF_create_priv_ud_av(hca_hndl, pd, av_p, ah_p)\r
-\r
-#define HH_modify_priv_ud_av(hca_hndl, ah, av_p) \\r
- (hca_hndl)->if_ops->HHIF_modify_priv_ud_av(hca_hndl, ah, av_p)\r
-\r
-#define HH_query_priv_ud_av(hca_hndl, ah, av_p) \\r
- (hca_hndl)->if_ops->HHIF_query_priv_ud_av(hca_hndl, ah, av_p)\r
-\r
-#define HH_destroy_priv_ud_av(hca_hndl, ah) \\r
- (hca_hndl)->if_ops->HHIF_destroy_priv_ud_av(hca_hndl, ah)\r
-\r
-\r
-\r
-/* Memory Regions/Windows */\r
-/**************************/\r
-#define HH_register_mr(\\r
- hca_hndl, mr_props_p, lkey_p, rkey_p) \\r
- (hca_hndl)->if_ops->HHIF_register_mr(\\r
- hca_hndl, mr_props_p, lkey_p, rkey_p)\r
-\r
-#define HH_reregister_mr(\\r
- hca_hndl, lkey, change_mask, mr_props_p, lkey_p, rkey_p) \\r
- (hca_hndl)->if_ops->HHIF_reregister_mr(\\r
- hca_hndl, lkey, change_mask, mr_props_p, lkey_p, rkey_p)\r
-\r
-#define HH_register_smr(\\r
- hca_hndl, smr_props_p, lkey_p, rkey_p) \\r
- (hca_hndl)->if_ops->HHIF_register_smr(\\r
- hca_hndl, smr_props_p, lkey_p, rkey_p)\r
-\r
-#define HH_deregister_mr(hca_hndl, lkey) \\r
- (hca_hndl)->if_ops->HHIF_deregister_mr(hca_hndl, lkey)\r
-\r
-#define HH_query_mr(hca_hndl, lkey, mr_info_p) \\r
- (hca_hndl)->if_ops->HHIF_query_mr(hca_hndl, lkey, mr_info_p)\r
-\r
-#define HH_alloc_mw(hca_hndl, pd, initial_rkey_p) \\r
- (hca_hndl)->if_ops->HHIF_alloc_mw(hca_hndl, pd, initial_rkey_p)\r
-\r
-#define HH_query_mw(hca_hndl, initial_rkey, current_rkey_p, pd_p) \\r
- (hca_hndl)->if_ops->HHIF_query_mw(hca_hndl, initial_rkey, current_rkey_p, pd_p)\r
-\r
-#define HH_free_mw(hca_hndl, initial_rkey) \\r
- (hca_hndl)->if_ops->HHIF_free_mw(hca_hndl, initial_rkey)\r
-\r
-\r
-/* Fast Memory Regions */\r
-/***********************/\r
-#define HH_alloc_fmr(hca_hndl,pd,acl,max_pages,log2_page_sz,last_lkey_p) \\r
- (hca_hndl)->if_ops->HHIF_alloc_fmr(hca_hndl,pd,acl,max_pages,log2_page_sz,last_lkey_p)\r
- \r
-#define HH_map_fmr(hca_hndl,last_lkey,map_p,lkey_p,rkey_p) \\r
- (hca_hndl)->if_ops->HHIF_map_fmr(hca_hndl,last_lkey,map_p,lkey_p,rkey_p)\r
-\r
-#define HH_unmap_fmr(hca_hndl,num_of_fmrs_to_unmap,last_lkeys_array) \\r
- (hca_hndl)->if_ops->HHIF_unmap_fmr(hca_hndl,num_of_fmrs_to_unmap,last_lkeys_array)\r
-\r
-#define HH_free_fmr(hca_hndl,last_lkey) \\r
- (hca_hndl)->if_ops->HHIF_free_fmr(hca_hndl,last_lkey)\r
- \r
-\r
-/* Completion Queues */\r
-/*********************/\r
-#define HH_create_cq(hca_hndl, usr_prot_ctx, cq_ul_resources_p, cq) \\r
- (hca_hndl)->if_ops->HHIF_create_cq(hca_hndl, usr_prot_ctx, cq_ul_resources_p, cq)\r
-\r
-#define HH_resize_cq(hca_hndl, cq, cq_ul_resources_p) \\r
- (hca_hndl)->if_ops->HHIF_resize_cq(hca_hndl, cq, cq_ul_resources_p)\r
-\r
-#define HH_query_cq(hca_hndl, cq, num_o_cqes_p) \\r
- (hca_hndl)->if_ops->HHIF_query_cq(hca_hndl, cq, num_o_cqes_p)\r
-\r
-#define HH_destroy_cq(hca_hndl, cq) \\r
- (hca_hndl)->if_ops->HHIF_destroy_cq(hca_hndl, cq)\r
-\r
-\r
-\r
-/* Queue Pairs */\r
-/***************/\r
-#define HH_create_qp(\\r
- hca_hndl, init_attr_p, qp_ul_resources_p, qpn_p) \\r
- (hca_hndl)->if_ops->HHIF_create_qp(\\r
- hca_hndl, init_attr_p, qp_ul_resources_p, qpn_p)\r
-\r
-#define HH_get_special_qp(\\r
- hca_hndl, qp_type, port, init_attr_p, qp_ul_resources_p, sqp_hndl_p) \\r
- (hca_hndl)->if_ops->HHIF_get_special_qp(\\r
- hca_hndl, qp_type, port, init_attr_p, qp_ul_resources_p, sqp_hndl_p)\r
-\r
-#define HH_modify_qp(\\r
- hca_hndl, qp_num, cur_qp_state, qp_attr_p, qp_attr_mask_p) \\r
- (hca_hndl)->if_ops->HHIF_modify_qp(\\r
- hca_hndl, qp_num, cur_qp_state, qp_attr_p, qp_attr_mask_p)\r
-\r
-#define HH_query_qp(hca_hndl, qp_num, qp_attr_p) \\r
- (hca_hndl)->if_ops->HHIF_query_qp(hca_hndl, qp_num, qp_attr_p)\r
-\r
-#define HH_destroy_qp(hca_hndl, qp_num) \\r
- (hca_hndl)->if_ops->HHIF_destroy_qp(hca_hndl, qp_num)\r
-\r
-\r
- /* Shared Receive Queue (SRQ) */\r
- /******************************/\r
-\r
-#define HH_create_srq(hca_hndl, pd, srq_ul_resources_p,srq_p) \\r
- (hca_hndl)->if_ops->HHIF_create_srq(hca_hndl, pd, srq_ul_resources_p,srq_p)\r
-\r
-#define HH_query_srq(hca_hndl, srq, limit_p) \\r
- (hca_hndl)->if_ops->HHIF_query_srq(hca_hndl, srq, limit_p)\r
-\r
-#define HH_modify_srq(hca_hndl, srq, srq_ul_resources_p) \\r
- (hca_hndl)->if_ops->HHIF_modify_srq(hca_hndl, srq, srq_ul_resources_p)\r
-\r
-#define HH_destroy_srq(hca_hndl, srq) \\r
- (hca_hndl)->if_ops->HHIF_destroy_srq(hca_hndl, srq)\r
-\r
-\r
-/* End to End Context */\r
-/**********************/\r
-#define HH_create_eec(hca_hndl, rdd, eecn_p) \\r
- (hca_hndl)->if_ops->HHIF_create_eec(hca_hndl, rdd, eecn_p)\r
-\r
-#define HH_modify_eec(\\r
- hca_hndl, eecn, cur_ee_state, ee_attr_p, ee_attr_mask_p) \\r
- (hca_hndl)->if_ops->HHIF_modify_eec(\\r
- hca_hndl, eecn, cur_ee_state, ee_attr_p, ee_attr_mask_p)\r
-\r
-#define HH_query_eec(hca_hndl, eecn, ee_attr_p) \\r
- (hca_hndl)->if_ops->HHIF_query_eec(hca_hndl, eecn, ee_attr_p)\r
-\r
-#define HH_destroy_eec(hca_hndl, eecn) \\r
- (hca_hndl)->if_ops->HHIF_destroy_eec(hca_hndl, eecn)\r
-\r
-\r
-\r
-/* Event Handler Calls */\r
-/***********************/\r
-#define HH_set_async_eventh(hca_hndl, handler, private_context) \\r
- (hca_hndl)->if_ops->HHIF_set_async_eventh(hca_hndl, handler, private_context)\r
-\r
-#define HH_set_comp_eventh(hca_hndl, handler, private_context) \\r
- (hca_hndl)->if_ops->HHIF_set_comp_eventh(hca_hndl, handler, private_context)\r
-\r
-\r
-\r
-/* Multicast Groups */\r
-/********************/\r
-#define HH_attach_to_multicast(hca_hndl, qpn, dgid) \\r
- (hca_hndl)->if_ops->HHIF_attach_to_multicast(hca_hndl, qpn, dgid)\r
-\r
-#define HH_detach_from_multicast(hca_hndl, qpn, dgid) \\r
- (hca_hndl)->if_ops->HHIF_detach_from_multicast(hca_hndl, qpn, dgid)\r
-\r
-/* Local MAD processing */\r
-/************************/\r
-#define HH_process_local_mad(\\r
- hca_hndl, port, slid, flags, mad_in_p, mad_out_p) \\r
- (hca_hndl)->if_ops->HHIF_process_local_mad(\\r
- hca_hndl, port, slid, flags, mad_in_p, mad_out_p)\r
-\r
-#define HH_ddrmm_alloc(\\r
- hca_hndl, size, align_shift, buf_p) \\r
- (hca_hndl)->if_ops->HHIF_ddrmm_alloc(\\r
- hca_hndl, size, align_shift, buf_p)\r
- \r
-#define HH_ddrmm_query(\\r
- hca_hndl, align_shift, total_mem, free_mem, largest_chunk,largest_free_addr_p) \\r
- (hca_hndl)->if_ops->HHIF_ddrmm_query(\\r
- hca_hndl, align_shift, total_mem, free_mem, largest_chunk,largest_free_addr_p)\r
-\r
-#define HH_ddrmm_free(\\r
- hca_hndl, buf, size) \\r
- (hca_hndl)->if_ops->HHIF_ddrmm_free(\\r
- hca_hndl, buf, size)\r
-\r
-#if defined(MT_SUSPEND_QP)\r
-#define HH_suspend_qp(\\r
- hca_hndl, qp_num, suspend_flag) \\r
- (hca_hndl)->if_ops->HHIF_suspend_qp(\\r
- hca_hndl, qp_num, suspend_flag)\r
-#define HH_suspend_cq(\\r
- hca_hndl, cq, do_suspend) \\r
- (hca_hndl)->if_ops->HHIF_suspend_cq(\\r
- hca_hndl, cq, do_suspend)\r
-#endif\r
-\r
-\r
-\r
-\r
-extern HH_ret_t HHIF_dummy(void);\r
-\r
-\r
-/****************************************************************************\r
- * Function: HH_add_hca_dev\r
- *\r
- * Arguments:\r
- * dev_info (IN) : device data (with strings not copied).\r
- * hca_hndl_p (OUT) : Allocated HCA object in HH\r
- *\r
- * Returns: HH_OK : operation successfull.\r
- * HH_EAGAIN : not enough resources.\r
- *\r
- * Description:\r
- * Add new HCA device to HH layer. This function should be called by an\r
- * HCA device driver for each new device it finds and set up.\r
- * Important:\r
- * Though given HCA handle is a pointer to HH_hca_dev_t, do NOT try to\r
- * copy the HH_hca_dev_t and use a pointer to the copy. The original\r
- * pointer/handle must be used !\r
- *\r
- ****************************************************************************/\r
-extern HH_ret_t HH_add_hca_dev(HH_hca_dev_t* dev_info, HH_hca_hndl_t* hca_hndl_p);\r
-\r
-\r
-/****************************************************************************\r
- * Function: HH_rem_hca_dev\r
- *\r
- * Arguments:\r
- * hca_hndl (IN) : HCA to remove\r
- *\r
- * Returns: HH_OK : operation successfull.\r
- * HH_ENODEV : no such device.\r
- *\r
- * Description:\r
- * Remove given HCA from HH. This function should be called by an\r
- * HCA device driver for each of its devices upon cleanup (or for\r
- * specific device which was "hot-removed".\r
- *\r
- ****************************************************************************/\r
-extern HH_ret_t HH_rem_hca_dev(HH_hca_hndl_t hca_hndl);\r
-\r
-/*****************************************************************************\r
- * Function: HH_lookup_hca\r
- *\r
- * Arguments:\r
- * name (IN) : device name\r
- * hca_handle_p (OUT) : HCA handle\r
- *\r
- * Returns: HH_OK : operation successfull.\r
- * HH_ENODEV : no such device.\r
- *\r
- *****************************************************************************/\r
-extern HH_ret_t HH_lookup_hca(const char * name, HH_hca_hndl_t* hca_handle_p);\r
-\r
-\r
-/*****************************************************************************\r
- * Function: HH_list_hcas\r
- *\r
- * Arguments:\r
- * buf_entries(IN) : Number of entries in given buffer\r
- * num_of_hcas_p(OUT) : Actual number of currently available HCAs\r
- * hca_list_buf_p(OUT) : A buffer of buf_sz entries of HH_hca_hndl_t\r
- * Returns: HH_OK : operation successfull.\r
- * HH_EINVAL : Invalid params (NULL ptrs).\r
- * HH_EAGAIN : buf_entries is smaller then num_of_hcas\r
- * Description:\r
- * Each device is refereced using HH_hca_hndl. In order to get list of\r
- * available devices and get a handle to each of the HCA currently\r
- * available HH provides in kernel HCA listing function (immitating usage\r
- * of ls /dev/ in user space))..\r
- *\r
- *****************************************************************************/\r
-extern HH_ret_t HH_list_hcas(u_int32_t buf_entries,\r
- u_int32_t* num_of_hcas_p,\r
- HH_hca_hndl_t* hca_list_buf_p);\r
-\r
-/************************************************************************\r
- * Set the if_ops tbl with dummy functions returning HH_ENOSYS.\r
- * This is convenient for initializing tables prior\r
- * setting them with partial real implementation.\r
- *\r
- * This way, the general HH_if_ops_t table structure can be extended,\r
- * requiring just recompilation.\r
- ************************************************************************/\r
-extern void HH_ifops_tbl_set_enosys(HH_if_ops_t* tbl);\r
-\r
-#endif /*_H_HH_H_*/\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#include <mtl_common.h>\r
-#include <vapi_types.h>\r
-#include <hh_common.h>\r
-\r
-#if defined(__DARWIN__) && defined (MT_KERNEL)\r
-#ifndef abs\r
-#define abs(x) ((x)>0?(x):-(x))\r
-#endif\r
-#endif\r
-\r
-/* We cannot use simple and efficient switch/cases,\r
- * since HH_ERROR_LIST has some different symbols with equal values!\r
- */\r
-\r
-enum { E_SYMBOL, E_MESSAGE };\r
-\r
-\r
-#undef HH_ERROR_INFO\r
-#define HH_ERROR_INFO(A, B, C) {#A, C},\r
-#define ERR_TABLE_SIZE (-VAPI_EGEN + 1)\r
-static const char *tab[ERR_TABLE_SIZE][2] = {\r
- HH_ERROR_LIST\r
-};\r
-#undef HH_ERROR_INFO\r
-\r
-static const int32_t err_nums[] = {\r
-#define HH_ERROR_INFO(A, B, C) A,\r
- HH_ERROR_LIST\r
-#undef HH_ERROR_INFO\r
- HH_ERROR_DUMMY_CODE\r
-};\r
-#define ERR_NUMS_SIZE (sizeof(err_nums)/sizeof(int32_t))\r
-\r
-\r
-/************************************************************************/\r
-static const char* HH_strerror_t(HH_ret_t errnum, unsigned int te)\r
-{\r
- const char* s = "HH Unknown Error";\r
- int ie = ERR_TABLE_SIZE;\r
- int i;\r
- for (i=0; (err_nums[i] != HH_ERROR_DUMMY_CODE) && (i < ERR_NUMS_SIZE); i++)\r
- { \r
- if (err_nums[i] == errnum)\r
- {\r
- ie = i;\r
- break;\r
- }\r
- }\r
- if (ie < ERR_TABLE_SIZE)\r
- {\r
- const char* ts = tab[ie][te];\r
- if (ts) { s = ts; }\r
- }\r
- return s;\r
-} /* HH_strerror_t */\r
-\r
-\r
-/************************************************************************/\r
-const char* HH_strerror(HH_ret_t errnum)\r
-{\r
- return HH_strerror_t(errnum, E_MESSAGE);\r
-} /* HH_strerror */\r
-\r
-\r
-/************************************************************************/\r
-const char* HH_strerror_sym(HH_ret_t errnum)\r
-{\r
- return HH_strerror_t(errnum, E_SYMBOL);\r
-} /* HH_strerror_sym */\r
-\r
-\r
-#if defined(HH_COMMON_TEST)\r
-/* Compile by\r
- gcc -g -Wall -DHH_COMMON_TEST -I. -I$MTHOME/include -o /tmp/hhc hh_common.c\r
- */\r
-#include <stdio.h>\r
-int main(int argc, char** argv)\r
-{\r
- if (argc < 2) \r
- {\r
- fprintf(stderr, "Usage: %s <error-code list>\n", argv[0]);\r
- }\r
- else\r
- {\r
- int ai;\r
- for (ai = 1; ai != argc; ++ai)\r
- {\r
- int errrc = atol(argv[ai]);\r
- printf("[%d] errrc=%d, sym=%s, doc=%s\n", ai, errrc,\r
- HH_strerror_sym(errrc), HH_strerror(errrc));\r
- }\r
- }\r
- return 0;\r
-} /* main */\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#ifndef H_HH_COMMON_H\r
-#define H_HH_COMMON_H\r
-\r
-#include <vapi_types.h>\r
-\r
-#define MAX_HCA_DEV_NUM 32\r
-\r
-\r
-/*\r
- * Typedefs\r
- *\r
- */\r
-\r
-typedef struct HH_hca_dev_st* __ptr64 HH_hca_hndl_t;\r
-typedef struct HHUL_sr_wqe_st HHUL_sr_wqe_t;\r
-typedef struct HHUL_rr_wqe_st HHUL_rr_wqe_t;\r
-\r
-typedef u_int32_t HH_pd_hndl_t;\r
-typedef u_int32_t HH_rdd_hndl_t;\r
-typedef MT_ulong_ptr_t HH_ud_av_hndl_t;\r
-typedef u_int32_t HH_cq_hndl_t;\r
-typedef u_int32_t HH_srq_hndl_t;\r
-\r
-#define HH_INVAL_SRQ_HNDL 0xFFFFFFFF\r
-\r
-typedef enum {PD_NO_FLAGS=0, PD_FOR_SQP=1} HH_pdm_pd_flags_t;\r
-\r
-\r
-/*\r
- * Return error codes\r
- * First put all VAPI codes, then all codes not in VAPI\r
- *\r
- */\r
-#if 0\r
- { /* left-brace for balance check */\r
-#endif\r
-\r
-#define HH_ERROR_LIST \\r
-HH_ERROR_INFO(HH_OK, = VAPI_OK , "Operation Succeeded")\\r
-HH_ERROR_INFO(HH_ERR, = VAPI_EGEN , "General Layer Error")\\r
-HH_ERROR_INFO(HH_EFATAL, = VAPI_EFATAL , "Fatal error") \\r
-HH_ERROR_INFO(HH_EAGAIN, = VAPI_EAGAIN , "Not Enough Resources")\\r
-HH_ERROR_INFO(HH_EINTR, = VAPI_EINTR , "Operation interrupted")\\r
-HH_ERROR_INFO(HH_EBUSY, = VAPI_EBUSY , "Resource is busy/in-use")\\r
-HH_ERROR_INFO(HH_EINVAL, = VAPI_EINVAL_PARAM , "Invalid parameter")\\r
-HH_ERROR_INFO(HH_EINVAL_PD_HNDL, = VAPI_EINVAL_PD_HNDL , "Invalid PD handle")\\r
-HH_ERROR_INFO(HH_EINVAL_AV_HNDL, = VAPI_EINVAL_AV_HNDL , "Invalid Address Vector handle")\\r
-HH_ERROR_INFO(HH_EINVAL_QP_NUM, = VAPI_EINVAL_QP_HNDL , "Invalid Queue Pair Number")\\r
-HH_ERROR_INFO(HH_EINVAL_SRQ_HNDL, = VAPI_EINVAL_SRQ_HNDL , "Invalid SRQ handle")\\r
-HH_ERROR_INFO(HH_EINVAL_EEC_NUM, = VAPI_EINVAL_EEC_HNDL , "Invalid EE-Context Number")\\r
-HH_ERROR_INFO(HH_EINVAL_CQ_HNDL, = VAPI_EINVAL_CQ_HNDL , "Invalid Completion Queue Handle")\\r
-HH_ERROR_INFO(HH_EINVAL_QP_STATE, = VAPI_EINVAL_QP_STATE , "Invalid Queue Pair State")\\r
-HH_ERROR_INFO(HH_EINVAL_HCA_ID, = VAPI_EINVAL_HCA_ID , "Wrong HCA ID")\\r
-HH_ERROR_INFO(HH_EINVAL_CQ_NOT_TYPE, = VAPI_EINVAL_NOTIF_TYPE, "Invalid Completion Notification Type")\\r
-HH_ERROR_INFO(HH_EINVAL_PARAM, = VAPI_EINVAL_PARAM, "Invalid Parameter")\\r
-HH_ERROR_INFO(HH_EINVAL_HCA_HNDL, = VAPI_EINVAL_HCA_HNDL , "Bad HCA device Handle")\\r
-HH_ERROR_INFO(HH_ENOSYS, = VAPI_ENOSYS , "Not Supported")\\r
-HH_ERROR_INFO(HH_EINVAL_PORT, = VAPI_EINVAL_PORT , "Invalid Port Number")\\r
-HH_ERROR_INFO(HH_EINVAL_OPCODE, = VAPI_EINVAL_OP , "Invalid Operation")\\r
-HH_ERROR_INFO(HH_ENOMEM, = VAPI_EAGAIN , "Not Enough Memory")\\r
-HH_ERROR_INFO(HH_E2BIG_SG_NUM, = VAPI_E2BIG_SG_NUM , "Max. SG size exceeds capabilities")\\r
-HH_ERROR_INFO(HH_E2BIG_WR_NUM, = VAPI_E2BIG_WR_NUM , "Max. WR number exceeds capabilities")\\r
-HH_ERROR_INFO(HH_EINVAL_WQE, = VAPI_E2BIG_WR_NUM , "Invalid WQE")\\r
-HH_ERROR_INFO(HH_EINVAL_SG_NUM, = VAPI_EINVAL_SG_NUM , "Invalid scatter/gather list length") \\r
-HH_ERROR_INFO(HH_EINVAL_SG_FMT, = VAPI_EINVAL_SG_FMT , "Invalid scatter/gather list format") \\r
-HH_ERROR_INFO(HH_E2BIG_CQE_NUM, = VAPI_E2BIG_CQ_NUM , "CQE number exceeds CQ cap.") \\r
-HH_ERROR_INFO(HH_CQ_EMPTY, = VAPI_CQ_EMPTY , "CQ is empty")\\r
-HH_ERROR_INFO(HH_EINVAL_VA, = VAPI_EINVAL_VA , "Invalid virtual address")\\r
-HH_ERROR_INFO(HH_EINVAL_MW, = VAPI_EINVAL_MW_HNDL , "Invalid memory window")\\r
-HH_ERROR_INFO(HH_CQ_FULL, = VAPI_EAGAIN , "CQ is full")\\r
-HH_ERROR_INFO(HH_EINVAL_MTU, = VAPI_EINVAL_MTU , "MTU violation")\\r
-HH_ERROR_INFO(HH_2BIG_MCG_SIZE, = VAPI_E2BIG_MCG_SIZE ,"Number of QPs attached to multicast groups exceeded") \\r
-HH_ERROR_INFO(HH_EINVAL_MCG_GID, = VAPI_EINVAL_MCG_GID ,"Invalid Multicast group GID") \\r
-HH_ERROR_INFO(HH_EINVAL_SERVICE_TYPE,= VAPI_EINVAL_SERVICE_TYPE , "Non supported transport service for QP.")\\r
-HH_ERROR_INFO(HH_EINVAL_MIG_STATE, = VAPI_EINVAL_MIG_STATE ,"Invalid Path Migration State") \\r
-HH_ERROR_INFO(HH_COMPLETED, = VAPI_COMPLETED ,"Poll Loop Completed") \\r
-HH_ERROR_INFO(HH_POLL_NEEDED, = VAPI_POLL_NEEDED ,"Drain CQ with poll_cq") \\r
-HH_ERROR_INFO(HH_ERROR_MIN, = VAPI_ERROR_MAX , "Dummy min error code : put all error codes after it")\\r
-HH_ERROR_INFO(HH_NO_MCG, EMPTY ,"No Multicast group was found") \\r
-HH_ERROR_INFO(HH_MCG_FULL, EMPTY ,"Multicast group is not empty") \\r
-HH_ERROR_INFO(HH_MCG_EMPTY, EMPTY ,"Multicast group is empty") \\r
-HH_ERROR_INFO(HH_ENODEV, EMPTY , "Unknown device")\\r
-HH_ERROR_INFO(HH_DISCARD, EMPTY ,"Data Discarded")\\r
-HH_ERROR_INFO(HH_ERROR_MAX, EMPTY ,"Dummy max error code : put all error codes before it") \r
-#if 0\r
- } /* right-brace for balance check */\r
-#endif\r
-\r
-enum\r
-{\r
-#define HH_ERROR_INFO(A, B, C) A B,\r
- HH_ERROR_LIST\r
-#undef HH_ERROR_INFO\r
- HH_ERROR_DUMMY_CODE\r
-}; \r
-typedef int32_t HH_ret_t;\r
-\r
-#if defined (__DLL_EXPORTS__)\r
-__declspec(dllexport) const char* HH_strerror(HH_ret_t errnum);\r
-__declspec(dllexport) const char* HH_strerror_sym(HH_ret_t errnum);\r
-#else\r
-extern const char* HH_strerror(HH_ret_t errnum);\r
-extern const char* HH_strerror_sym(HH_ret_t errnum);\r
-#endif\r
-\r
-/************************************************************************\r
- *** Low level only ***\r
- ***/\r
-\r
-typedef struct\r
-{\r
- MT_virt_addr_t addr;\r
- MT_virt_addr_t size;\r
-} HH_buff_entry_t;\r
-\r
-#if 0\r
-typedef void (*HH_async_event_t)(HH_hca_hndl_t, \r
- HH_event_record_t *, \r
- void* private_data); \r
-typedef void (*HH_comp_event_t)(HH_hca_hndl_t, \r
- HH_cq_num_t, \r
- void* private_data);\r
-#endif\r
-\r
-#endif /* H_HH_COMMON_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_HH_INIT_H\r
-#define H_HH_INIT_H\r
-\r
-#ifdef MT_KERNEL\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-int init_hh_driver(void);\r
-void cleanup_hh_driver(void);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif /* MT_KERNEL */\r
-\r
-#endif /*H_HH_INIT_H */\r
- \r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
- mrw.type = VAPI_MR;\r
- mrw.page_size = PAGE_SIZE;\r
- mrw.size = REGION_SIZE;\r
- mrw.start = va;\r
- mrw.acl = VAPI_EN_LOCAL_WRITE | VAPI_EN_REMOTE_WRITE | VAPI_EN_REMOTE_READ;\r
- \r
- mrw.phys_addr_lst_len = NUM_OF_PAGE_ENTRIES(va, REGION_SIZE); \r
- \r
- mrw.phys_addr_lst = (MT_phys_addr_t *)MALLOC(mrw.phys_addr_lst_len * sizeof(MT_phys_addr_t));\r
- if(mrw.phys_addr_lst == 0)\r
- {\r
- MTL_ERROR('1', "%s: couldn't allocate memory for phys_addr_lst\n", __FUNCTION__);\r
- return(-1);\r
- }\r
- build_tpt_lst(va, mrw.phys_addr_lst_len, mrw.phys_addr_lst);\r
- \r
- \r
- ret = GHH_init_hh_all_gamla();\r
-\r
- if(ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in initilization of Gamlas\n", __FUNCTION__);\r
- return(HH_OK);\r
- }\r
-\r
- \r
- HH_open_hca(HCA_NUM);\r
-\r
-\r
- ret = HH_create_pd(HCA_NUM,&pd_num); \r
- if(ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in create PD\n",__FUNCTION__);\r
- return(-1);\r
- }\r
-\r
-\r
- ret = HH_register_mrw(HCA_NUM, &mrw, &rkey, &lkey);\r
- if(ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in memory registration for device\n",__FUNCTION__);\r
- return(-1);\r
- }\r
- FREE(mrw.phys_addr_lst);\r
-\r
- /* Allocate memory for CQ */\r
- ret = HH_get_cq_buffer_sz(HCA_NUM,MAX_CQ_ENTRIES,&cq_buf_sz,&cq_num_ent);\r
- if(ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in getting CQ buf size\n",__FUNCTION__);\r
- return(-1);\r
- }\r
-\r
-\r
- cq_buf_va = (MT_virt_addr_t)MALLOC(cq_buf_sz);\r
- cq_mrw.type = VAPI_MR;\r
- cq_mrw.page_size = PAGE_SIZE;\r
- cq_mrw.size = cq_buf_sz;\r
- cq_mrw.start = cq_buf_va;\r
- cq_mrw.acl = VAPI_EN_LOCAL_WRITE; /* Local only ! */\r
- cq_mrw.phys_addr_lst_len = NUM_OF_PAGE_ENTRIES(cq_mrw.start, cq_mrw.size); \r
- cq_mrw.phys_addr_lst = (MT_phys_addr_t *)MALLOC(cq_mrw.phys_addr_lst_len * sizeof(MT_phys_addr_t));\r
-\r
- if(cq_mrw.phys_addr_lst == 0)\r
- {\r
- MTL_ERROR('1', "%s: couldn't allocate memory for phys_addr_lst\n", __FUNCTION__);\r
- return(-1);\r
- }\r
-\r
- build_tpt_lst(cq_mrw.start, cq_mrw.phys_addr_lst_len, cq_mrw.phys_addr_lst);\r
-\r
- ret = HH_register_mrw(HCA_NUM, &cq_mrw, &cq_buf_rkey, &cq_buf_lkey);\r
- if(ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in memory registration for device\n",__FUNCTION__);\r
- return(-1);\r
- }\r
- FREE(cq_mrw.phys_addr_lst);\r
-\r
- ret = HH_create_cq(HCA_NUM,cq_buf_va,cq_buf_lkey,cq_buf_sz,&cq_num_ent,&cq_num);\r
- if(ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: Failed to create CQ\n",__FUNCTION__);\r
- return(-1);\r
- }\r
-\r
- /* Register region for WQEs */\r
- qp_cap.max_oust_wr_rq = MAX_WQES;\r
- qp_cap.max_oust_wr_sq = MAX_WQES;\r
- qp_cap.max_sg_size_rq = MAX_SG_ENTRIES;\r
- qp_cap.max_sg_size_sq = MAX_SG_ENTRIES;\r
- ret = HH_get_wqe_buf_sz(HCA_NUM,VAPI_TS_RC,&qp_cap,&qp_wqe_buff_sz,&act_qp_cap);\r
- if(ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in getting wqe buf size\n",__FUNCTION__);\r
- return(-1);\r
- }\r
-\r
- qp_wqe_buff_va = (MT_virt_addr_t)MALLOC(qp_wqe_buff_sz);\r
- qp_wqe_mrw.type = VAPI_MR;\r
- qp_wqe_mrw.page_size = PAGE_SIZE;\r
- qp_wqe_mrw.size = qp_wqe_buff_sz;\r
- qp_wqe_mrw.start = qp_wqe_buff_va;\r
- qp_wqe_mrw.acl = VAPI_EN_LOCAL_WRITE; /* Local only ! */\r
- qp_wqe_mrw.phys_addr_lst_len = NUM_OF_PAGE_ENTRIES(qp_wqe_mrw.start, qp_wqe_mrw.size); \r
- qp_wqe_mrw.phys_addr_lst = (MT_phys_addr_t *)MALLOC(qp_wqe_mrw.phys_addr_lst_len * sizeof(MT_phys_addr_t));\r
- if(qp_wqe_mrw.phys_addr_lst == 0)\r
- {\r
- MTL_ERROR('1', "%s: couldn't allocate memory for phys_addr_lst\n", __FUNCTION__);\r
- return(-1);\r
- }\r
- build_tpt_lst(qp_wqe_mrw.start, qp_wqe_mrw.phys_addr_lst_len, qp_wqe_mrw.phys_addr_lst);\r
- \r
- ret = HH_register_mrw(HCA_NUM, &qp_wqe_mrw, &wqe_buff_rkey, &wqe_buff_lkey);\r
- if(ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in memory registration for device\n",__FUNCTION__);\r
- return(-1);\r
- }\r
- FREE(qp_wqe_mrw.phys_addr_lst);\r
-\r
-\r
- /* Open the QP */\r
- qp_init_attr.ts_type = VAPI_TS_RC; \r
- qp_init_attr.pd_num = pd_num;\r
- qp_init_attr.rdd_num = 0;\r
- qp_init_attr.wqe_buff = qp_wqe_mrw.start;\r
- qp_init_attr.wqe_buff_lkey = wqe_buff_lkey;\r
- qp_init_attr.wqe_buff_size = qp_wqe_mrw.size;\r
- \r
- qp_init_attr.rq_sig_type = VAPI_SIGNALED;\r
- qp_init_attr.rq_cq_num = cq_num;\r
- qp_init_attr.sq_sig_type = VAPI_SIGNALED;\r
- qp_init_attr.sq_cq_num = cq_num;\r
- \r
- ret = HH_create_qp(HCA_NUM,&qp_init_attr,&qp_num);\r
- if (ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in create QP\n",__FUNCTION__);\r
- return(-1);\r
- }\r
-\r
- \r
- QP_ATTR_MASK_CLR_ALL(qp_attr_mask);\r
-\r
- /* Common modifiers */\r
- qp_attr.av.dlid = RC_DLID;\r
- qp_attr.av.grh_flag = FALSE;\r
- qp_attr.av.sl = RC_SL;\r
- qp_attr.av.src_path_bits = 0;\r
- qp_attr.av.static_rate = 1; QP_ATTR_MASK_SET(qp_attr_mask,QP_ATTR_AV);\r
- qp_attr.path_mtu = RC_MTU; QP_ATTR_MASK_SET(qp_attr_mask,QP_ATTR_PATH_MTU);\r
- qp_attr.dest_qp_num = RC_DST_QP_NUM; QP_ATTR_MASK_SET(qp_attr_mask,QP_ATTR_DEST_QP_NUM);\r
- qp_attr.pkey_ix = RC_PKEY_IX; QP_ATTR_MASK_SET(qp_attr_mask,QP_ATTR_PKEY_IX);\r
- qp_attr.port = 1; QP_ATTR_MASK_SET(qp_attr_mask,QP_ATTR_PORT);\r
- qp_attr.qp_state = VAPI_RTS; QP_ATTR_MASK_SET(qp_attr_mask,QP_ATTR_QP_STATE);\r
-\r
- /* Requester Modifiers */\r
- qp_attr.rq_psn = 0; QP_ATTR_MASK_SET(qp_attr_mask,QP_ATTR_RQ_PSN);\r
-\r
- /* Responder Modifiers */\r
- qp_attr.sq_psn = 0; /* Initial PSN for requester */\r
- qp_attr.timeout = 0x1f; /* timeout */\r
- qp_attr.rnr_retry = 0; /* Retries not supported */\r
- \r
-\r
-\r
- ret = HH_modify_qp(HCA_NUM,qp_num,VAPI_RESET,&qp_attr,&qp_attr_mask);\r
- if (ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in create QP\n",__FUNCTION__);\r
- return(-1);\r
- }\r
-\r
- /* Post WQE */\r
- dest1_mrw.type = VAPI_MR;\r
- dest1_mrw.size = 4096;\r
- dest1_mrw.start = (MT_virt_addr_t)MALLOC(dest1_mrw.size);\r
-\r
- mlock((u_int32_t*)((u_int32_t)dest1_mrw.start),dest1_mrw.size); \r
-\r
- dest1_mrw.page_size = PAGE_SIZE;\r
- dest1_mrw.num = pd_num;\r
- dest1_mrw.acl = VAPI_EN_LOCAL_WRITE | VAPI_EN_REMOTE_WRITE | VAPI_EN_REMOTE_READ ;\r
- dest1_mrw.phys_addr_lst_len = NUM_OF_PAGE_ENTRIES(dest1_mrw.start, dest1_mrw.size); \r
- dest1_mrw.phys_addr_lst = (MT_phys_addr_t *)MALLOC(dest1_mrw.phys_addr_lst_len * sizeof(MT_phys_addr_t));\r
- if((dest1_mrw.phys_addr_lst == 0)||(dest1_mrw.start==0))\r
- {\r
- MTL_ERROR('1', "%s: couldn't allocate memory\n", __FUNCTION__);\r
- return(-1);\r
- }\r
- build_tpt_lst(dest1_mrw.start, dest1_mrw.phys_addr_lst_len, dest1_mrw.phys_addr_lst);\r
- ret = HH_register_mrw(HCA_NUM, &dest1_mrw, &dest1_rkey, &dest1_lkey);\r
- if(ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in memory registration for MRW\n",__FUNCTION__);\r
- return(-1);\r
- }\r
- FREE(dest1_mrw.phys_addr_lst);\r
-\r
- printf("VA: %x RKey: %x\n",dest1_mrw.start,dest1_rkey);\r
-\r
- rr_wqe_p = (HH_rr_wqe_t *)qp_wqe_buff_va;\r
- rr_wqe_p->comp_type = 0; // VAPI_SIGNALED;\r
- rr_wqe_p->id = 0x666;\r
- rr_wqe_p->next = 0;\r
- rr_wqe_p->total_len = 4096 * 8; \r
- rr_wqe_p->sg_lst_len = 1 * 8;\r
- rr_wqe_p->sg_lst_p[0].addr = dest1_mrw.start;\r
- rr_wqe_p->sg_lst_p[0].len = 4096;\r
- rr_wqe_p->sg_lst_p[0].lkey = dest1_lkey;\r
- rr_wqe_p->sg_lst_p[1].addr = dest1_mrw.start;\r
- rr_wqe_p->sg_lst_p[1].len = 4096;\r
- rr_wqe_p->sg_lst_p[1].lkey = dest1_lkey;\r
- rr_wqe_p->sg_lst_p[2].addr = dest1_mrw.start;\r
- rr_wqe_p->sg_lst_p[2].len = 4096;\r
- rr_wqe_p->sg_lst_p[2].lkey = dest1_lkey;\r
- rr_wqe_p->sg_lst_p[3].addr = dest1_mrw.start;\r
- rr_wqe_p->sg_lst_p[3].len = 4096;\r
- rr_wqe_p->sg_lst_p[3].lkey = dest1_lkey;\r
- rr_wqe_p->sg_lst_p[4].addr = dest1_mrw.start;\r
- rr_wqe_p->sg_lst_p[4].len = 4096;\r
- rr_wqe_p->sg_lst_p[4].lkey = dest1_lkey;\r
- rr_wqe_p->sg_lst_p[5].addr = dest1_mrw.start;\r
- rr_wqe_p->sg_lst_p[5].len = 4096;\r
- rr_wqe_p->sg_lst_p[5].lkey = dest1_lkey;\r
- rr_wqe_p->sg_lst_p[6].addr = dest1_mrw.start;\r
- rr_wqe_p->sg_lst_p[6].len = 4096;\r
- rr_wqe_p->sg_lst_p[6].lkey = dest1_lkey;\r
- rr_wqe_p->sg_lst_p[7].addr = dest1_mrw.start;\r
- rr_wqe_p->sg_lst_p[7].len = 4096;\r
- rr_wqe_p->sg_lst_p[7].lkey = dest1_lkey;\r
- /*\r
- rr_wqe_p->sg_lst_p[2].addr = dest1_mrw.start+16;\r
- rr_wqe_p->sg_lst_p[2].len = 33;\r
- rr_wqe_p->sg_lst_p[2].lkey = dest1_lkey;\r
- */\r
-\r
- ret = GHQPM_rq_doorbell(HH_hca_dev_tbl + HCA_NUM,qp_num, qp_wqe_buff_va);\r
- if(ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in doorbell for RQ\n",__FUNCTION__);\r
- return(-1);\r
- }\r
-\r
- /* link another WQE */\r
- rr_wqe_p->next = (MT_virt_addr_t)((void*)rr_wqe_p + \r
- sizeof(HH_rr_wqe_t) + \r
- (rr_wqe_p->sg_lst_len-1)*sizeof(HH_sg_lst_entry_t));\r
-\r
- rr_wqe_p = (HH_rr_wqe_t *)rr_wqe_p->next;\r
-\r
- rr_wqe_p->comp_type = 0; // VAPI_SIGNALED;\r
- rr_wqe_p->id = 0x666;\r
- rr_wqe_p->next = 0;\r
- rr_wqe_p->total_len = 4096 * 8; \r
- rr_wqe_p->sg_lst_len = 1 * 8;\r
- rr_wqe_p->sg_lst_p[0].addr = dest1_mrw.start;\r
- rr_wqe_p->sg_lst_p[0].len = 4096;\r
- rr_wqe_p->sg_lst_p[0].lkey = dest1_lkey;\r
- rr_wqe_p->sg_lst_p[1].addr = dest1_mrw.start;\r
- rr_wqe_p->sg_lst_p[1].len = 4096;\r
- rr_wqe_p->sg_lst_p[1].lkey = dest1_lkey;\r
- rr_wqe_p->sg_lst_p[2].addr = dest1_mrw.start;\r
- rr_wqe_p->sg_lst_p[2].len = 4096;\r
- rr_wqe_p->sg_lst_p[2].lkey = dest1_lkey;\r
- rr_wqe_p->sg_lst_p[3].addr = dest1_mrw.start;\r
- rr_wqe_p->sg_lst_p[3].len = 4096;\r
- rr_wqe_p->sg_lst_p[3].lkey = dest1_lkey;\r
- rr_wqe_p->sg_lst_p[4].addr = dest1_mrw.start;\r
- rr_wqe_p->sg_lst_p[4].len = 4096;\r
- rr_wqe_p->sg_lst_p[4].lkey = dest1_lkey;\r
- rr_wqe_p->sg_lst_p[5].addr = dest1_mrw.start;\r
- rr_wqe_p->sg_lst_p[5].len = 4096;\r
- rr_wqe_p->sg_lst_p[5].lkey = dest1_lkey;\r
- rr_wqe_p->sg_lst_p[6].addr = dest1_mrw.start;\r
- rr_wqe_p->sg_lst_p[6].len = 4096;\r
- rr_wqe_p->sg_lst_p[6].lkey = dest1_lkey;\r
- rr_wqe_p->sg_lst_p[7].addr = dest1_mrw.start;\r
- rr_wqe_p->sg_lst_p[7].len = 4096;\r
- rr_wqe_p->sg_lst_p[7].lkey = dest1_lkey;\r
- \r
-\r
-\r
-\r
- ret = GHQPM_rq_doorbell(HH_hca_dev_tbl + HCA_NUM, qp_num, qp_wqe_buff_va);\r
- if(ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in doorbell for RQ\n",__FUNCTION__);\r
- return(-1);\r
- }\r
-\r
-\r
- /* Here is a good place to send the first packet ! */\r
- \r
-#ifdef RX_STUB\r
- rx_stub(HH_hca_dev_tbl+HCA_NUM);\r
-#else\r
- GHRX_receive_poll((GHH_dev_t*)((HH_hca_dev_tbl + HCA_NUM)->device));\r
-#endif /* RX_STUB */\r
-\r
-\r
- sprintf(tmp_buf,"\n\n--------The result buf:");\r
- \r
-\r
- \r
- for (i=0;i<128;i++)\r
- {\r
- if (i%16==0) { sprintf(tmp_buf1,"\n"); strcat(tmp_buf,tmp_buf1); }\r
- sprintf(tmp_buf1,"%02X ",(u_int8_t)*((u_int8_t*)((MT_phys_addr_t)dest1_mrw.start+i)));\r
- strcat(tmp_buf,tmp_buf1);\r
- }\r
-\r
-\r
- \r
- MTL_TRACE('4',"%s\n\n",tmp_buf); \r
-\r
-\r
-\r
-\r
- ret = HH_destroy_qp(HCA_NUM,qp_num);\r
- if (ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in destroy QP\n",__FUNCTION__);\r
- return(-1);\r
- }\r
- \r
- ret = HH_destroy_cq(HCA_NUM,cq_num);\r
- if (ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in destroy CQ\n",__FUNCTION__);\r
- return(-1);\r
- }\r
- \r
- ret = HH_destroy_pd(HCA_NUM,pd_num); \r
- if (ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in destroy PD\n",__FUNCTION__);\r
- return(-1);\r
- }\r
-\r
- ret = HH_close_hca(HCA_NUM);\r
- if (ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in close HCA\n",__FUNCTION__);\r
- return(-1);\r
- }\r
-\r
- ret = HH_rem_hca_dev(HCA_NUM);\r
- if (ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in HCA remove device\n",__FUNCTION__);\r
- return(-1);\r
- }\r
-\r
- return(0);\r
-}\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#define RC_SLID 0x112\r
-#define RC_DLID 0x122\r
-#define RC_MTU MTU256\r
-#define RC_SL 1\r
-#define RC_SRC_QP_NUM 2\r
-#define RC_DST_QP_NUM 0x2\r
-#define RC_PKEY_IX 0\r
-#define RC_PKEY 0x8888\r
-#define RC_RQ_START_PSN 0\r
-\r
-\r
-\r
-HH_ret_t rx_stub(HH_hca_dev_t *dev);\r
- \r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
- HH_mrw_t mrw, mrw_sg;\r
-\r
- MT_virt_addr_t va;\r
- VAPI_rkey_t rkey, rkey_sg;\r
- VAPI_lkey_t lkey, lkey_sg;\r
-\r
- \r
- /* Protection Domain */\r
- HH_pd_num_t pd_num;\r
-\r
- /* Queue Pair Variables */\r
- VAPI_qp_cap_t qp_cap,act_qp_cap;\r
- HH_qp_init_attr_t qp_init_attr;\r
- VAPI_qp_num_t qp_num;\r
- VAPI_qp_attr_t qp_attr;\r
- VAPI_qp_attr_mask_t qp_attr_mask;\r
-\r
- size_t qp_wqe_buff_sz;\r
- HH_mrw_t qp_wqe_mrw;\r
- VAPI_rkey_t wqe_buff_rkey;\r
- VAPI_lkey_t wqe_buff_lkey;\r
- MT_virt_addr_t qp_wqe_buff_va;\r
-\r
- \r
- /* Completion Queue Configuration */\r
- size_t cq_buf_sz;\r
- u_int32_t cq_num_ent;\r
- HH_cq_num_t cq_num;\r
- HH_mrw_t cq_mrw;\r
- VAPI_rkey_t cq_buf_rkey;\r
- VAPI_rkey_t cq_buf_lkey;\r
- /*VAPI_wc_desc_t wc;*/\r
- MT_virt_addr_t cq_buf_va;\r
-\r
-\r
- /* Post Send WQE */\r
- HH_sr_wqe_t *wqe_p;\r
- HH_sg_lst_entry_t sg_lst[5];\r
-\r
- \r
- \r
- \r
-\r
- va = (MT_virt_addr_t)MALLOC(REGION_SIZE);\r
-\r
- mlock((u_int32_t*)va, REGION_SIZE);\r
-\r
- if(va == 0)\r
- {\r
- MTL_ERROR('1', "%s: couldn't allocate memory for region\n", __FUNCTION__);\r
- return(-1);\r
- }\r
- \r
- \r
- /* Device Initialization */\r
- ret = GHH_init_hh_all_gamla();\r
-\r
- if(ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in initilization of Gamlas\n", __FUNCTION__);\r
- return(HH_OK);\r
- }\r
- \r
-\r
-\r
- /*\r
- * HCA Calls\r
- *\r
- */\r
- HH_open_hca(HCA_NUM);\r
- \r
- ret = HH_create_pd(HCA_NUM,&pd_num); \r
- if(ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in create PD\n",__FUNCTION__);\r
- return(-1);\r
- }\r
- \r
-\r
-\r
-\r
- /*\r
- * Memory Registration Calls\r
- *\r
- */\r
- \r
- /* Initialize Memory Regions */\r
- mrw.type = VAPI_MR;\r
- mrw.page_size = PAGE_SIZE;\r
- mrw.size = REGION_SIZE;\r
- mrw.start = va;\r
- mrw.acl = VAPI_EN_LOCAL_WRITE | VAPI_EN_REMOTE_WRITE | VAPI_EN_REMOTE_READ;\r
- \r
- mrw.phys_addr_lst_len = NUM_OF_PAGE_ENTRIES(va, REGION_SIZE); \r
- \r
- mrw.phys_addr_lst = (MT_phys_addr_t *)MALLOC(mrw.phys_addr_lst_len * sizeof(MT_phys_addr_t));\r
-\r
- if(mrw.phys_addr_lst == 0)\r
- {\r
- MTL_ERROR('1', "%s: couldn't allocate memory for phys_addr_lst\n", __FUNCTION__);\r
- return(-1);\r
- }\r
- \r
- build_tpt_lst(va, mrw.phys_addr_lst_len, mrw.phys_addr_lst);\r
- \r
- ret = HH_register_mrw(HCA_NUM, &mrw, &rkey, &lkey);\r
- if(ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in memory registration for device\n",__FUNCTION__);\r
- return(-1);\r
- }\r
- \r
- FREE(mrw.phys_addr_lst);\r
-\r
- \r
- \r
- /* Source Data Memory Region*/\r
- mrw_sg.type = VAPI_MR;\r
- mrw_sg.page_size = PAGE_SIZE;\r
- mrw_sg.size = REGION_SIZE;\r
- mrw_sg.start = va;\r
- mrw_sg.acl = VAPI_EN_LOCAL_WRITE | VAPI_EN_REMOTE_WRITE | VAPI_EN_REMOTE_READ;\r
- \r
- mrw_sg.phys_addr_lst_len = NUM_OF_PAGE_ENTRIES(va, REGION_SIZE); \r
- \r
- mrw_sg.phys_addr_lst = (MT_phys_addr_t *)MALLOC(mrw_sg.phys_addr_lst_len * sizeof(MT_phys_addr_t));\r
- \r
-\r
- if(mrw_sg.phys_addr_lst == 0)\r
- {\r
- MTL_ERROR('1', "%s: couldn't allocate memory for phys_addr_lst\n", __FUNCTION__);\r
- return(-1);\r
- }\r
- \r
- build_tpt_lst(va, mrw_sg.phys_addr_lst_len, mrw_sg.phys_addr_lst);\r
- \r
- ret = HH_register_mrw(HCA_NUM, &mrw_sg, &rkey_sg, &lkey_sg);\r
- if(ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in memory registration for device\n",__FUNCTION__);\r
- return(-1);\r
- }\r
- \r
- FREE(mrw_sg.phys_addr_lst);\r
-\r
-\r
- \r
-\r
- \r
-\r
-\r
-\r
- /*\r
- * CQ Verbs\r
- *\r
- */\r
- ret = HH_get_cq_buffer_sz(HCA_NUM,MAX_CQ_ENTRIES,&cq_buf_sz,&cq_num_ent);\r
- \r
- if(ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in getting CQ buf size\n",__FUNCTION__);\r
- return(-1);\r
- }\r
-\r
-\r
- /* Completion Queue Memory Registration */\r
- cq_buf_va = (MT_virt_addr_t)MALLOC(cq_buf_sz);\r
- cq_mrw.type = VAPI_MR;\r
- cq_mrw.page_size = PAGE_SIZE;\r
- cq_mrw.size = cq_buf_sz;\r
- cq_mrw.start = cq_buf_va;\r
- cq_mrw.acl = VAPI_EN_LOCAL_WRITE; /* Local only ! */\r
- cq_mrw.phys_addr_lst_len = NUM_OF_PAGE_ENTRIES(cq_mrw.start, cq_mrw.size); \r
- cq_mrw.phys_addr_lst = (MT_phys_addr_t *)MALLOC(cq_mrw.phys_addr_lst_len * sizeof(MT_phys_addr_t));\r
-\r
- if(cq_mrw.phys_addr_lst == 0)\r
- {\r
- MTL_ERROR('1', "%s: couldn't allocate memory for phys_addr_lst\n", __FUNCTION__);\r
- return(-1);\r
- }\r
-\r
- build_tpt_lst(cq_mrw.start, cq_mrw.phys_addr_lst_len, cq_mrw.phys_addr_lst);\r
-\r
- ret = HH_register_mrw(HCA_NUM, &cq_mrw, &cq_buf_rkey, &cq_buf_lkey);\r
- if(ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in memory registration for device\n",__FUNCTION__);\r
- return(-1);\r
- }\r
- FREE(cq_mrw.phys_addr_lst);\r
-\r
- ret = HH_create_cq(HCA_NUM,cq_buf_va,cq_buf_lkey,cq_buf_sz,&cq_num_ent,&cq_num);\r
- if(ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: Failed to create CQ\n",__FUNCTION__);\r
- return(-1);\r
- }\r
-\r
-\r
-\r
- /*\r
- * Queue Pair Calls \r
- *\r
- */\r
-\r
- /* Register region for WQEs */\r
- qp_cap.max_oust_wr_rq = MAX_WQES;\r
- qp_cap.max_oust_wr_sq = MAX_WQES;\r
- qp_cap.max_sg_size_rq = MAX_SG_ENTRIES;\r
- qp_cap.max_sg_size_sq = MAX_SG_ENTRIES;\r
- \r
- ret = HH_get_wqe_buf_sz(HCA_NUM,VAPI_TS_RC,&qp_cap,&qp_wqe_buff_sz,&act_qp_cap);\r
- \r
- if(ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in getting wqe buf size\n",__FUNCTION__);\r
- return(-1);\r
- }\r
-\r
- /* Queue Pair Buffers */\r
- qp_wqe_buff_va = (MT_virt_addr_t)MALLOC(qp_wqe_buff_sz);\r
- qp_wqe_mrw.type = VAPI_MR;\r
- qp_wqe_mrw.page_size = PAGE_SIZE;\r
- qp_wqe_mrw.size = qp_wqe_buff_sz;\r
- qp_wqe_mrw.start = qp_wqe_buff_va;\r
- qp_wqe_mrw.acl = VAPI_EN_LOCAL_WRITE; /* Local only ! */\r
- qp_wqe_mrw.phys_addr_lst_len = NUM_OF_PAGE_ENTRIES(qp_wqe_mrw.start, qp_wqe_mrw.size); \r
- qp_wqe_mrw.phys_addr_lst = (MT_phys_addr_t *)MALLOC(qp_wqe_mrw.phys_addr_lst_len * sizeof(MT_phys_addr_t));\r
- \r
- if(qp_wqe_mrw.phys_addr_lst == 0)\r
- {\r
- MTL_ERROR('1', "%s: couldn't allocate memory for phys_addr_lst\n", __FUNCTION__);\r
- return(-1);\r
- }\r
-\r
- build_tpt_lst(qp_wqe_mrw.start, qp_wqe_mrw.phys_addr_lst_len, qp_wqe_mrw.phys_addr_lst);\r
- \r
- ret = HH_register_mrw(HCA_NUM, &qp_wqe_mrw, &wqe_buff_rkey, &wqe_buff_lkey);\r
-\r
- if(ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in memory registration for device\n",__FUNCTION__);\r
- return(-1);\r
- }\r
- FREE(qp_wqe_mrw.phys_addr_lst);\r
-\r
-\r
- /* Open the QP */\r
- qp_init_attr.ts_type = VAPI_TS_RC; \r
- qp_init_attr.pd_num = pd_num;\r
- qp_init_attr.rdd_num = 0;\r
- qp_init_attr.wqe_buff = qp_wqe_mrw.start;\r
- qp_init_attr.wqe_buff_lkey = wqe_buff_lkey;\r
- qp_init_attr.wqe_buff_size = qp_wqe_mrw.size;\r
- \r
- qp_init_attr.rq_sig_type = VAPI_SIGNALED;\r
- qp_init_attr.rq_cq_num = cq_num;\r
- qp_init_attr.sq_sig_type = VAPI_SIGNALED;\r
- qp_init_attr.sq_cq_num = cq_num;\r
- \r
- ret = HH_create_qp(HCA_NUM,&qp_init_attr,&qp_num);\r
- \r
- if (ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in create QP\n",__FUNCTION__);\r
- return(-1);\r
- }\r
- \r
- QP_ATTR_MASK_CLR_ALL(qp_attr_mask);\r
-\r
- /* Common modifiers */\r
- qp_attr.av.dlid = RC_DLID;\r
- qp_attr.av.grh_flag = FALSE;\r
- qp_attr.av.sl = RC_SL;\r
- qp_attr.av.src_path_bits = 0;\r
- qp_attr.av.static_rate = 1; QP_ATTR_MASK_SET(qp_attr_mask,QP_ATTR_AV);\r
- qp_attr.path_mtu = RC_MTU; QP_ATTR_MASK_SET(qp_attr_mask,QP_ATTR_PATH_MTU);\r
- qp_attr.dest_qp_num = RC_DST_QP_NUM; QP_ATTR_MASK_SET(qp_attr_mask,QP_ATTR_DEST_QP_NUM);\r
- qp_attr.pkey_ix = RC_PKEY_IX; QP_ATTR_MASK_SET(qp_attr_mask,QP_ATTR_PKEY_IX);\r
- qp_attr.port = 0; QP_ATTR_MASK_SET(qp_attr_mask,QP_ATTR_PORT);\r
- qp_attr.qp_state = VAPI_RTS; QP_ATTR_MASK_SET(qp_attr_mask,QP_ATTR_QP_STATE);\r
-\r
- /* Requester Modifiers */\r
- qp_attr.rq_psn = 0; QP_ATTR_MASK_SET(qp_attr_mask,QP_ATTR_RQ_PSN);\r
-\r
- /* Responder Modifiers */\r
- qp_attr.sq_psn = 0; /* Initial PSN for requester */\r
- qp_attr.timeout = 0x1f; /* timeout */\r
- qp_attr.rnr_retry = 0; /* Retries not supported */\r
- \r
-\r
- ret = HH_modify_qp(HCA_NUM,qp_num,VAPI_RESET,&qp_attr,&qp_attr_mask);\r
- if (ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in create QP\n",__FUNCTION__);\r
- return(-1);\r
- }\r
-\r
- \r
- /*\r
- * Preparing Work Queue Element\r
- *\r
- */ \r
- wqe_p = (HH_sr_wqe_t*)qp_wqe_buff_va;\r
-\r
- sg_lst[0].addr = mrw_sg.start;\r
- sg_lst[0].len = PAGE_SIZE;\r
- sg_lst[0].lkey = lkey_sg;\r
- \r
- sg_lst[1].addr = mrw_sg.start;\r
- sg_lst[1].len = PAGE_SIZE;\r
- sg_lst[1].lkey = lkey_sg;\r
- \r
- sg_lst[2].addr = mrw_sg.start;\r
- sg_lst[2].len = PAGE_SIZE;\r
- sg_lst[2].lkey = lkey_sg;\r
- \r
-\r
- wqe_p->id = 10;\r
- wqe_p->opcode = VAPI_SEND;\r
- wqe_p->sg_lst_len = 3;\r
- wqe_p->sg_total_byte_len = 3*PAGE_SIZE;\r
- wqe_p->sg_lst_p = sg_lst;\r
-\r
-\r
- printf("Hit Enter To Post first descriptor\n");\r
- getchar();\r
-\r
- ret = GHQPM_sq_doorbell(HH_hca_dev_tbl + HCA_NUM,qp_num, wqe_p);\r
- if(ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in doorbell for RQ\n",__FUNCTION__);\r
- return(-1);\r
- }\r
- printf("Hit Enter to finish program\n");\r
- getchar();\r
-\r
-\r
-\r
-// printf("Hit Enter To Post second descriptor\n");\r
-// getchar();\r
-\r
-// ret = GHQPM_sq_doorbell(HH_hca_dev_tbl + HCA_NUM,qp_num, wqe_p);\r
-// if(ret != HH_OK)\r
-// {\r
-// MTL_ERROR('1', "%s: failed in doorbell for RQ\n",__FUNCTION__);\r
-// return(-1);\r
-// }\r
-\r
-// printf("Hit Enter to finish program\n");\r
-// getchar();\r
-\r
-\r
- \r
- /*\r
- * Destroy All\r
- *\r
- */\r
- ret = HH_destroy_qp(HCA_NUM,qp_num);\r
- if (ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in destroy QP\n",__FUNCTION__);\r
- return(-1);\r
- }\r
- \r
- ret = HH_destroy_cq(HCA_NUM,cq_num);\r
- if (ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in destroy CQ\n",__FUNCTION__);\r
- return(-1);\r
- }\r
- \r
- ret = HH_destroy_pd(HCA_NUM,pd_num); \r
- if (ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in destroy PD\n",__FUNCTION__);\r
- return(-1);\r
- }\r
-\r
- ret = HH_close_hca(HCA_NUM);\r
- if (ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in close HCA\n",__FUNCTION__);\r
- return(-1);\r
- }\r
-\r
- ret = HH_rem_hca_dev(HCA_NUM);\r
- if (ret != HH_OK)\r
- {\r
- MTL_ERROR('1', "%s: failed in HCA remove device\n",__FUNCTION__);\r
- return(-1);\r
- }\r
-\r
- return(0);\r
-}\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#define RC_SLID 0x112\r
-#define RC_DLID 0x121\r
-#define RC_MTU MTU256\r
-#define RC_SL 1\r
-#define RC_SRC_QP_NUM 2\r
-#define RC_DST_QP_NUM 0x42\r
-#define RC_PKEY_IX 0\r
-#define RC_PKEY 0x8888\r
-#define RC_RQ_START_PSN 0\r
-\r
-\r
-\r
-HH_ret_t rx_stub(HH_hca_dev_t *dev);\r
- \r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id:$\r
- */\r
-\r
-\r
-static HH_ret_t enosys_open_hca(\r
- HH_hca_hndl_t hca_hndl,\r
- EVAPI_hca_profile_t *profile_p,\r
- EVAPI_hca_profile_t *sugg_profile_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_close_hca(\r
- HH_hca_hndl_t hca_hndl\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_alloc_ul_resources(\r
- HH_hca_hndl_t hca_hndl,\r
- MOSAL_protection_ctx_t user_protection_context,\r
- void* hca_ul_resources_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_free_ul_resources(\r
- HH_hca_hndl_t hca_hndl,\r
- void* hca_ul_resources_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_query_hca(\r
- HH_hca_hndl_t hca_hndl,\r
- VAPI_hca_cap_t* hca_cap_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_modify_hca(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- VAPI_hca_attr_t* hca_attr_p,\r
- VAPI_hca_attr_mask_t* hca_attr_mask_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_query_port_prop(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- VAPI_hca_port_t* hca_port_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_get_pkey_tbl(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- u_int16_t tbl_len_in,\r
- u_int16_t* tbl_len_out,\r
- IB_pkey_t* pkey_tbl_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_get_gid_tbl(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- u_int16_t tbl_len_in,\r
- u_int16_t* tbl_len_out,\r
- IB_gid_t* pkey_tbl_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_get_lid(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port,\r
- IB_lid_t* lid_p,\r
- u_int8_t* lmc_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_alloc_pd(\r
- HH_hca_hndl_t hca_hndl, \r
- MOSAL_protection_ctx_t prot_ctx, \r
- void * pd_ul_resources_p, \r
- HH_pd_hndl_t *pd_num_p\r
-) \r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_free_pd(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_pd_hndl_t pd\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_alloc_rdd(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_rdd_hndl_t* rdd_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_free_rdd(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_rdd_hndl_t rdd\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_create_priv_ud_av(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_pd_hndl_t pd,\r
- VAPI_ud_av_t* av_p,\r
- HH_ud_av_hndl_t* ah_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_modify_priv_ud_av(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_ud_av_hndl_t ah,\r
- VAPI_ud_av_t* av_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_query_priv_ud_av(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_ud_av_hndl_t ah,\r
- VAPI_ud_av_t* av_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_destroy_priv_ud_av(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_ud_av_hndl_t ah\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_register_mr(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_mr_t* mr_props_p,\r
- VAPI_lkey_t* lkey_p,\r
- IB_rkey_t* rkey_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_reregister_mr(\r
- HH_hca_hndl_t hca_hndl,\r
- VAPI_lkey_t lkey,\r
- VAPI_mr_change_t change_mask,\r
- HH_mr_t* mr_props_p,\r
- VAPI_lkey_t* lkey_p,\r
- IB_rkey_t* rkey_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_register_smr(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_smr_t* smr_props_p,\r
- VAPI_lkey_t* lkey_p,\r
- IB_rkey_t* rkey_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_deregister_mr(\r
- HH_hca_hndl_t hca_hndl,\r
- VAPI_lkey_t lkey\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_query_mr(\r
- HH_hca_hndl_t hca_hndl,\r
- VAPI_lkey_t lkey,\r
- HH_mr_info_t* mr_info_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_alloc_mw(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_pd_hndl_t pd,\r
- IB_rkey_t* initial_rkey_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_free_mw(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_rkey_t initial_rkey\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_create_cq(\r
- HH_hca_hndl_t hca_hndl,\r
- MOSAL_protection_ctx_t user_protection_context,\r
- void* cq_ul_resources_p,\r
- HH_cq_hndl_t* cq\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_resize_cq(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_cq_hndl_t cq,\r
- void* cq_ul_resources_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_query_cq(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_cq_hndl_t cq,\r
- VAPI_cqe_num_t* num_o_cqes_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_destroy_cq(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_cq_hndl_t cq\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_create_qp(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_qp_init_attr_t* init_attr_p,\r
- void* qp_ul_resources_p,\r
- IB_wqpn_t* qpn_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_get_special_qp(\r
- HH_hca_hndl_t hca_hndl,\r
- VAPI_special_qp_t qp_type,\r
- IB_port_t port,\r
- HH_qp_init_attr_t* init_attr_p,\r
- void* qp_ul_resources_p,\r
- IB_wqpn_t* sqp_hndl_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_modify_qp(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_wqpn_t qp_num,\r
- VAPI_qp_state_t cur_qp_state,\r
- VAPI_qp_attr_t* qp_attr_p,\r
- VAPI_qp_attr_mask_t* qp_attr_mask_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_query_qp(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_wqpn_t qp_num,\r
- VAPI_qp_attr_t* qp_attr_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_destroy_qp(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_wqpn_t qp_num\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_create_srq(HH_hca_hndl_t hca_hndl,\r
- HH_pd_hndl_t pd, \r
- void *srq_ul_resources_p, \r
- HH_srq_hndl_t *srq_p)\r
-{\r
- return HH_ENOSYS;\r
-}\r
- \r
-\r
-static HH_ret_t enosys_query_srq(HH_hca_hndl_t hca_hndl,\r
- HH_srq_hndl_t srq,\r
- u_int32_t *limit_p)\r
-{\r
- return HH_ENOSYS;\r
-}\r
- \r
-static HH_ret_t enosys_modify_srq(HH_hca_hndl_t hca_hndl,\r
- HH_srq_hndl_t srq,\r
- void *srq_ul_resources_p)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_destroy_srq(HH_hca_hndl_t hca_hndl,\r
- HH_srq_hndl_t srq)\r
-{\r
- return HH_ENOSYS;\r
-}\r
- \r
-\r
-static HH_ret_t enosys_create_eec(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_rdd_hndl_t rdd,\r
- IB_eecn_t* eecn_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_modify_eec(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_eecn_t eecn,\r
- VAPI_qp_state_t cur_ee_state,\r
- VAPI_qp_attr_t* ee_attr_p,\r
- VAPI_qp_attr_mask_t* ee_attr_mask_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_query_eec(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_eecn_t eecn,\r
- VAPI_qp_attr_t* ee_attr_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_destroy_eec(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_eecn_t eecn\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_set_async_eventh(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_async_eventh_t handler,\r
- void* private_data\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_set_comp_eventh(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_comp_eventh_t handler,\r
- void* private_data\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_attach_to_multicast(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_wqpn_t qpn,\r
- IB_gid_t dgid\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_detach_from_multicast(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_wqpn_t qpn,\r
- IB_gid_t dgid\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_process_local_mad(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- IB_lid_t slid,\r
- EVAPI_proc_mad_opt_t proc_mad_opts,\r
- void* mad_in_p,\r
- void* mad_out_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-\r
-static void enosys_init(HH_if_ops_t* p)\r
-{\r
- p->HHIF_open_hca = &enosys_open_hca;\r
- p->HHIF_close_hca = &enosys_close_hca;\r
- p->HHIF_alloc_ul_resources = &enosys_alloc_ul_resources;\r
- p->HHIF_free_ul_resources = &enosys_free_ul_resources;\r
- p->HHIF_query_hca = &enosys_query_hca;\r
- p->HHIF_modify_hca = &enosys_modify_hca;\r
- p->HHIF_query_port_prop = &enosys_query_port_prop;\r
- p->HHIF_get_pkey_tbl = &enosys_get_pkey_tbl;\r
- p->HHIF_get_gid_tbl = &enosys_get_gid_tbl;\r
- p->HHIF_get_lid = &enosys_get_lid;\r
- p->HHIF_alloc_pd = &enosys_alloc_pd;\r
- p->HHIF_free_pd = &enosys_free_pd;\r
- p->HHIF_alloc_rdd = &enosys_alloc_rdd;\r
- p->HHIF_free_rdd = &enosys_free_rdd;\r
- p->HHIF_create_priv_ud_av = &enosys_create_priv_ud_av;\r
- p->HHIF_modify_priv_ud_av = &enosys_modify_priv_ud_av;\r
- p->HHIF_query_priv_ud_av = &enosys_query_priv_ud_av;\r
- p->HHIF_destroy_priv_ud_av = &enosys_destroy_priv_ud_av;\r
- p->HHIF_register_mr = &enosys_register_mr;\r
- p->HHIF_reregister_mr = &enosys_reregister_mr;\r
- p->HHIF_register_smr = &enosys_register_smr;\r
- p->HHIF_deregister_mr = &enosys_deregister_mr;\r
- p->HHIF_query_mr = &enosys_query_mr;\r
- p->HHIF_alloc_mw = &enosys_alloc_mw;\r
- p->HHIF_free_mw = &enosys_free_mw;\r
- p->HHIF_create_cq = &enosys_create_cq;\r
- p->HHIF_resize_cq = &enosys_resize_cq;\r
- p->HHIF_query_cq = &enosys_query_cq;\r
- p->HHIF_destroy_cq = &enosys_destroy_cq;\r
- p->HHIF_create_qp = &enosys_create_qp;\r
- p->HHIF_get_special_qp = &enosys_get_special_qp;\r
- p->HHIF_modify_qp = &enosys_modify_qp;\r
- p->HHIF_query_qp = &enosys_query_qp;\r
- p->HHIF_destroy_qp = &enosys_destroy_qp;\r
- p->HHIF_create_eec = &enosys_create_eec;\r
- p->HHIF_modify_eec = &enosys_modify_eec;\r
- p->HHIF_query_eec = &enosys_query_eec;\r
- p->HHIF_destroy_eec = &enosys_destroy_eec;\r
- p->HHIF_set_async_eventh = &enosys_set_async_eventh;\r
- p->HHIF_set_comp_eventh = &enosys_set_comp_eventh;\r
- p->HHIF_attach_to_multicast = &enosys_attach_to_multicast;\r
- p->HHIF_detach_from_multicast = &enosys_detach_from_multicast;\r
- p->HHIF_process_local_mad = &enosys_process_local_mad;\r
- p->HHIF_create_srq = &enosys_create_srq;\r
- p->HHIF_destroy_srq = &enosys_destroy_srq;\r
- p->HHIF_query_srq = &enosys_query_srq;\r
- p->HHIF_modify_srq = &enosys_modify_srq;\r
-} /* enosys_init */\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#define C_HHUL_C\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-#include <hhul.h>\r
-#include <thhul_hob.h>\r
-/* add includes for other Mellanox devices here */\r
-\r
-\r
-\r
-extern HH_ret_t HHUL_alloc_hca_hndl\r
-(\r
- u_int32_t vendor_id,\r
- u_int32_t device_id,\r
- void* hca_ul_resources_p,\r
- HHUL_hca_hndl_t* hhul_hca_hndl_p\r
-)\r
-{\r
- HH_ret_t rc = HH_ENODEV;\r
- if (vendor_id == MT_MELLANOX_IEEE_VENDOR_ID) {\r
- /* Tavor (InfiniHost) */\r
- rc = THHUL_hob_create(hca_ul_resources_p, device_id, hhul_hca_hndl_p);\r
- } else { /* unknown vendor */\r
- return HH_ENOSYS;\r
- }\r
-\r
-\r
- if (rc == HH_OK)\r
- {\r
- struct HHUL_hca_dev_st* p = *hhul_hca_hndl_p;\r
- p->vendor_id = vendor_id;\r
- p->dev_id = device_id;\r
- }\r
- return rc;\r
-} /* HHUL_alloc_hca_hndl */\r
-\r
-\r
-#include "hhulenosys.ic"\r
-\r
-void HHUL_ifops_tbl_set_enosys(HHUL_if_ops_t* tbl)\r
-{\r
- enosys_init(tbl);\r
-}\r
-\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#ifndef H_HHUL_H\r
-#define H_HHUL_H\r
-\r
-#include <iba\ib_types.h>\r
-#include <vapi.h>\r
-#include <hh_common.h>\r
-\r
-typedef struct HHUL_hca_dev_st* HHUL_hca_hndl_t;\r
-\r
-typedef void* HHUL_mw_hndl_t;\r
-typedef void* HHUL_qp_hndl_t;\r
-typedef void* HHUL_srq_hndl_t;\r
-#define HHUL_INVAL_SRQ_HNDL ((void*)(MT_ulong_ptr_t)-1)\r
-typedef VAPI_ud_av_hndl_t HHUL_ud_av_hndl_t;\r
-typedef void* HHUL_cq_hndl_t;\r
-typedef unsigned long HHUL_pd_hndl_t;\r
-\r
-typedef struct HHUL_qp_init_attr_st {\r
- IB_ts_t ts_type;\r
- HHUL_pd_hndl_t pd;\r
- HHUL_cq_hndl_t sq_cq;\r
- HHUL_cq_hndl_t rq_cq;\r
- VAPI_sig_type_t sq_sig_type;\r
- VAPI_sig_type_t rq_sig_type;\r
- HHUL_srq_hndl_t srq; /* HHUL_INVAL_SRQ_HNDL if not associated with a SRQ */\r
- VAPI_qp_cap_t qp_cap;\r
-} HHUL_qp_init_attr_t;\r
-\r
-\r
-typedef struct HHUL_hca_dev_st HHUL_hca_dev_t;\r
-typedef struct HHUL_mw_bind_st HHUL_mw_bind_t;\r
-\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_alloc_hca_hndl\r
- *\r
- * Arguments:\r
- * vendor_id - The Vendor ID for the device to get handle for\r
- * device_id - The device ID for the device to get handle for\r
- * hca_ul_resources_p - Resources allocated by the privileged driver\r
- * hhul_hca_hndl_p - HCA handle provided for this HCA in user-level\r
- * (user-level resources context)\r
- * Returns: HH_OK,\r
- * HH_ENODEV - Unknown device type (based on vendor and device id).\r
- * HH_EAGAIN - Failed to allocate user space resources\r
- *\r
- * Description:\r
- *\r
- * This function invokes the HHUL_init_user_level()\r
- * which initilizes resources in user-level for given\r
- * HCA. The specific HHUL_init_user_level() is\r
- * selected based on device type (given in id\r
- * parameters). The hca_ul_resources_p parameter is a\r
- * copy of the resources context given by\r
- * HH_alloc_ul_resources().\r
- *\r
- ************************************************************************/\r
-extern HH_ret_t HHUL_alloc_hca_hndl\r
-(\r
- u_int32_t vendor_id,\r
- u_int32_t device_id,\r
- void* hca_ul_resources_p,\r
- HHUL_hca_hndl_t* hhul_hca_hndl_p\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_init_user_level\r
- *\r
- * This is merely a prototype function, that should have specific\r
- * implementation for each type of device.\r
- *\r
- * Arguments:\r
- * hca_ul_resourcs_p (IN) - The user-level resources context\r
- * allocated by\r
- * HH_alloc_ul_resources(). Its size is\r
- * defined by the specific instance of\r
- * this function (per device type).\r
- * hhul_hndl_p (OUT) - The user level handle of the HCA\r
- *\r
- * Returns: HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- * (NULL ptr or invalid resources context)\r
- * Description:\r
- *\r
- * This function is invoked by the HHUL wrapper for each HCA one wishes\r
- * to use in an application, when HHUL_alloc_hca_hndl is invoked. \r
- * The specificdevice function is selected based on the device type. \r
- * It should be called after allocating privileged resources using \r
- * HH_alloc_ul_resources().\r
- *\r
- * This function should allocate all the user-level HCA resources\r
- * required by given device in order to later manage the user-level HCA\r
- * operations. This includes user-level mirroring of HCA resources data\r
- * required while performing OS bypassing and other user-level context.\r
- *\r
- * The returned hhul_hndl is actually a pointer to HHUL device context.\r
- *\r
- ************************************************************************/\r
-\r
-#if 0\r
-extern HH_ret_t <deviceType>HHUL_init_user_level\r
-(\r
- void* hca_ul_resources_p,\r
- HHUL_hca_hndl_t* hhul_hndl_p\r
-);\r
-#endif\r
-\r
-typedef struct HHUL_if_ops_st {\r
- \r
- HH_ret_t (*HHULIF_cleanup_user_level)(HHUL_hca_hndl_t hhul_hndl);\r
- \r
- HH_ret_t (*HHULIF_alloc_pd_prep)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_pd_hndl_t* hhul_pd_p,\r
- void* pd_ul_resources_p);\r
- \r
- HH_ret_t (*HHULIF_alloc_pd_avs_prep)(HHUL_hca_hndl_t hca_hndl,\r
- u_int32_t max_num_avs,\r
- HH_pdm_pd_flags_t pd_flags,\r
- HHUL_pd_hndl_t* hhul_pd_p,\r
- void* pd_ul_resources_p);\r
-\r
- HH_ret_t (*HHULIF_alloc_pd_done)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_pd_hndl_t hhul_pd,\r
- HH_pd_hndl_t hh_pd,\r
- void* pd_ul_resources_p);\r
- \r
- HH_ret_t (*HHULIF_free_pd_prep)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_pd_hndl_t pd,\r
- MT_bool undo_flag);\r
-\r
- HH_ret_t (*HHULIF_free_pd_done)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_pd_hndl_t pd);\r
-\r
- HH_ret_t (*HHULIF_alloc_mw)(HHUL_hca_hndl_t hhul_hndl,\r
- IB_rkey_t initial_rkey,\r
- HHUL_mw_hndl_t* mw_p);\r
-\r
- HH_ret_t (*HHULIF_bind_mw)(HHUL_hca_hndl_t hhul_hndl,\r
- HHUL_mw_hndl_t mw,\r
- HHUL_mw_bind_t* bind_prop_p,\r
- IB_rkey_t* bind_rkey_p);\r
-\r
- HH_ret_t (*HHULIF_free_mw)(HHUL_hca_hndl_t hhul_hndl,\r
- HHUL_mw_hndl_t mw);\r
-\r
- HH_ret_t (*HHULIF_create_ud_av)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_pd_hndl_t pd,\r
- VAPI_ud_av_t* av_p,\r
- HHUL_ud_av_hndl_t* ah_p);\r
-\r
- HH_ret_t (*HHULIF_modify_ud_av)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_ud_av_hndl_t ah,\r
- VAPI_ud_av_t* av_p);\r
-\r
- HH_ret_t (*HHULIF_query_ud_av)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_ud_av_hndl_t ah,\r
- VAPI_ud_av_t* av_p);\r
-\r
- HH_ret_t (*HHULIF_destroy_ud_av)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_ud_av_hndl_t ah);\r
-\r
- HH_ret_t (*HHULIF_create_cq_prep)(HHUL_hca_hndl_t hca_hndl,\r
- VAPI_cqe_num_t num_o_cqes,\r
- HHUL_cq_hndl_t* hhul_cq_p,\r
- VAPI_cqe_num_t* num_o_cqes_p,\r
- void* cq_ul_resources_p);\r
-\r
- HH_ret_t (*HHULIF_create_cq_done)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_cq_hndl_t hhul_cq,\r
- HH_cq_hndl_t hh_cq,\r
- void* cq_ul_resources_p);\r
-\r
- ib_api_status_t (*HHULIF_resize_cq_prep)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_cq_hndl_t cq,\r
- VAPI_cqe_num_t num_o_cqes,\r
- VAPI_cqe_num_t* num_o_cqes_p,\r
- void* cq_ul_resources_p);\r
- \r
- HH_ret_t (*HHULIF_resize_cq_done)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_cq_hndl_t cq,\r
- void* cq_ul_resources_p);\r
-\r
- HH_ret_t (*HHULIF_poll4cqe)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_cq_hndl_t cq,\r
- VAPI_wc_desc_t* cqe_p);\r
- \r
- HH_ret_t (*HHULIF_poll_and_rearm_cq)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_cq_hndl_t cq,\r
- int solicitedNotification,\r
- VAPI_wc_desc_t* cqe_p);\r
-\r
- HH_ret_t (*HHULIF_peek_cq)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_cq_hndl_t cq,\r
- VAPI_cqe_num_t cqe_num);\r
-\r
-\r
- HH_ret_t (*HHULIF_req_comp_notif)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_cq_hndl_t cq,\r
- VAPI_cq_notif_type_t notif_type);\r
-\r
- HH_ret_t (*HHULIF_req_ncomp_notif)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_cq_hndl_t cq,\r
- VAPI_cqe_num_t cqe_num);\r
-\r
- HH_ret_t (*HHULIF_destroy_cq_done)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_cq_hndl_t cq);\r
-\r
- HH_ret_t (*HHULIF_create_qp_prep)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_qp_init_attr_t* qp_init_attr_p,\r
- HHUL_qp_hndl_t* qp_hndl_p,\r
- VAPI_qp_cap_t* qp_cap_out_p,\r
- void* qp_ul_resources_p);\r
-\r
- HH_ret_t (*HHULIF_special_qp_prep)(HHUL_hca_hndl_t hca_hndl,\r
- VAPI_special_qp_t special_qp_type,\r
- IB_port_t port,\r
- HHUL_qp_init_attr_t* qp_init_attr_p,\r
- HHUL_qp_hndl_t* qp_hndl_p,\r
- VAPI_qp_cap_t* qp_cap_out_p,\r
- void* qp_ul_resources_p);\r
-\r
- HH_ret_t (*HHULIF_create_qp_done)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_qp_hndl_t hhul_qp,\r
- IB_wqpn_t hh_qp,\r
- void* qp_ul_resources_p);\r
- \r
- HH_ret_t (*HHULIF_modify_qp_done)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_qp_hndl_t hhul_qp,\r
- VAPI_qp_state_t cur_state);\r
-\r
- HH_ret_t (*HHULIF_post_send_req)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_qp_hndl_t qp_hndl,\r
- VAPI_sr_desc_t* send_req_p);\r
-\r
- HH_ret_t (*HHULIF_post_send_req2)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_qp_hndl_t qp_hndl,\r
- VAPI_comp_type_t comp_type,\r
- VAPI_ud_av_hndl_t remote_ah,\r
- void* WorkReq);\r
-\r
- HH_ret_t (*HHULIF_post_inline_send_req)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_qp_hndl_t qp_hndl,\r
- VAPI_sr_desc_t* send_req_p);\r
- \r
- HH_ret_t (*HHULIF_post_send_reqs)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_qp_hndl_t qp_hndl,\r
- u_int32_t num_of_requests,\r
- VAPI_sr_desc_t* send_req_array);\r
- \r
- HH_ret_t (*HHULIF_post_gsi_send_req)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_qp_hndl_t qp_hndl,\r
- VAPI_sr_desc_t* send_req_p,\r
- VAPI_pkey_ix_t pkey_index);\r
- \r
- HH_ret_t (*HHULIF_post_recv_req)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_qp_hndl_t qp_hndl,\r
- VAPI_rr_desc_t* recv_req_p);\r
-\r
- HH_ret_t (*HHULIF_post_recv_req2)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_qp_hndl_t qp_hndl,\r
- VAPI_comp_type_t comp_type,\r
- u_int32_t sg_lst_len,\r
- VAPI_wr_id_t ReqId,\r
- VAPI_sg_lst_entry_t *sg_lst_p);\r
-\r
- HH_ret_t (*HHULIF_post_recv_reqs)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_qp_hndl_t qp_hndl,\r
- u_int32_t num_of_requests,\r
- VAPI_rr_desc_t* recv_req_array);\r
- \r
- HH_ret_t (*HHULIF_destroy_qp_done)(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_qp_hndl_t qp_hndl);\r
- \r
-HH_ret_t (*HHULIF_create_srq_prep)( \r
- /*IN*/\r
- HHUL_hca_hndl_t hca, \r
- HHUL_pd_hndl_t pd,\r
- u_int32_t max_outs,\r
- u_int32_t max_sentries,\r
- /*OUT*/\r
- HHUL_srq_hndl_t *srq_hndl_p,\r
- u_int32_t *actual_max_outs_p,\r
- u_int32_t *actual_max_sentries_p,\r
- void *srq_ul_resources_p);\r
-\r
-HH_ret_t (*HHULIF_create_srq_done)( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_srq_hndl_t hhul_srq, \r
- HH_srq_hndl_t hh_srq, \r
- void *srq_ul_resources_p);\r
-\r
-HH_ret_t (*HHULIF_modify_srq_prep)(\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/HHUL_srq_hndl_t hhul_srq,\r
- /*IN*/VAPI_srq_attr_t *srq_attr_p,\r
- /*IN*/VAPI_srq_attr_mask_t srq_attr_mask,\r
- /*OUT*/void *srq_ul_resources_p);\r
-\r
-HH_ret_t (*HHULIF_modify_srq_done)( \r
- /*IN*/HHUL_hca_hndl_t hca, \r
- /*IN*/HHUL_srq_hndl_t hhul_srq, \r
- /*IN*/void *srq_ul_resources_p,\r
- /*OUT*/u_int32_t *max_outs_wr_p /* Max. outstanding WQEs */\r
-); \r
-\r
-HH_ret_t (*HHULIF_destroy_srq_done)( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_qp_hndl_t hhul_srq \r
-);\r
-\r
-HH_ret_t (*HHULIF_post_srq)(\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_srq_hndl_t hhul_srq, \r
- /*IN*/ u_int32_t num_of_requests,\r
- /*IN*/ VAPI_rr_desc_t *recv_req_array,\r
- /*OUT*/ u_int32_t *posted_requests_p\r
-);\r
- \r
-} HHUL_if_ops_t;\r
-\r
-\r
-struct HHUL_hca_dev_st {\r
- HH_hca_hndl_t hh_hndl; /* kernel level HH handle of associated HCA */\r
- char* dev_desc; /* Device description (name, etc.) */\r
- u_int32_t vendor_id; /* IEEE's 24 bit Device Vendor ID */\r
- u_int32_t dev_id; /* Device/part ID */\r
- u_int32_t hw_ver; /* Hardware version (Stepping/Rev.) */\r
- u_int64_t fw_ver; /* Device's firmware version (device specific) */\r
- HHUL_if_ops_t* if_ops; /* Interface operations (Function map) */\r
- MT_size_t hca_ul_resources_sz; /* #bytes user-level resr. HCA context */\r
- MT_size_t pd_ul_resources_sz; /* #bytes user-level resr. PD context */\r
- MT_size_t cq_ul_resources_sz; /* #bytes user-level resr. CQ context */\r
- MT_size_t srq_ul_resources_sz; /* #bytes user-level resr. SRQ context */\r
- MT_size_t qp_ul_resources_sz; /* #bytes user-level resr. QP context */\r
- void* device; /* Pointer to device's private data */\r
- void* hca_ul_resources_p; /* Privileged User-Level resources\r
- * allocated for this HCA in process */\r
-};\r
-\r
-\r
-struct HHUL_mw_bind_st {\r
- VAPI_lkey_t mr_lkey; /* L-Key of memory region to bind to */\r
- IB_virt_addr_t start; /* Memory window.\r
- * start virtual address (byte addressing) */\r
- VAPI_size_t size; /* Size of memory window in bytes */\r
- VAPI_mrw_acl_t acl; /* Access Control (R/W permission - local/remote) */\r
- HHUL_qp_hndl_t qp; /* QP to use for posting this binding request */\r
- VAPI_wr_id_t id; /* Work request ID to be used in this binding request*/\r
- VAPI_comp_type_t comp_type; /* Create CQE or not (for QPs set to signaling per request) */\r
-};\r
-\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_cleanup_user_level\r
- * \r
- * \r
- * Arguments: hhul_hndl (IN) - The user level HCA handle\r
- * \r
- * Returns: HH_OK\r
- * HH_EINVAL_HCA_HNDL\r
- * Description:\r
- * \r
- * This function frees the device specific user level resources.\r
- * \r
- * After calling this function the device dependent layer should free the\r
- * associated privileged resources by calling the privileged call\r
- * HH_free_ul_resources(). The associated hca_ul_resources should be\r
- * saved before the call to this function in order to be able to use it\r
- * when calling HH_free_ul_resources().\r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_cleanup_user_level(hhul_hndl) \\r
- (hhul_hndl)->if_ops->HHULIF_cleanup_user_level(hhul_hndl)\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_alloc_mw\r
- * \r
- * \r
- * Arguments: hhul_hndl (IN) - The user level HCA handle\r
- * initial_rkey (IN) - The initial R-Key provided by kernel level\r
- * mw_p (OUT) - Returned memory window handle for user level\r
- * \r
- * Returns: HH_OK\r
- * HH_EINVAL_HCA_HNDL\r
- * \r
- * Description:\r
- * \r
- * In order to efficiently deal with OS bypassing while performing memory\r
- * window binding, this function should be called after a successful\r
- * return from kernel level memory window allocation. The initial R-Key\r
- * returned from the kernel level call should be used when allocating\r
- * user level memory window context.\r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_alloc_mw(hhul_hndl, initial_rkey, mw_p) \\r
- (hhul_hndl)->if_ops->HHULIF_alloc_mw(hhul_hndl, initial_rkey, mw_p)\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_bind_mw\r
- * \r
- * \r
- * Arguments: hhul_hndl (IN) - The user level HCA handle\r
- * mw (IN) - The memory window handle\r
- * bind_prop_p (IN) - Binding properties\r
- * bind_rkey_p (OUT) - The allocated R-Key for binding\r
- * \r
- * Returns: HH_OK\r
- * HH_EINVAL_HCA_HNDL\r
- * HH_EINVAL - Invalid parameters (NULL ptrs)\r
- * HH_EINVAL_MW_HNDL - Invalid memory window handle\r
- * HH_EINVAL_QP_HNDL -\r
- * Given QP handle is unknown or not in the correct\r
- * state state or is not of the correct trasport\r
- * service type (RC,UC,RD). HH_EAGAIN - No available\r
- * resources to perform given operation.\r
- * \r
- * Description:\r
- * \r
- * This function performs the posting of the memory binding WQE based on\r
- * given binding properties. Unbinding of a window may be done by\r
- * providing a 0 sized window.\r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_bind_mw(\\r
- hhul_hndl, mw, bind_prop_p, bind_rkey_p) \\r
- (hhul_hndl)->if_ops->HHULIF_bind_mw(\\r
- hhul_hndl, mw, bind_prop_p, bind_rkey_p)\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_free_mw\r
- * \r
- * \r
- * Arguments: hhul_hndl (IN) - The user level HCA handle\r
- * mw (IN) - The memory window handle\r
- * \r
- * Returns: HH_OK\r
- * HH_EINVAL_HCA_HNDL\r
- * HH_EINVAL_MW_HNDL - Invalid memory window handle\r
- * \r
- * Description:\r
- * \r
- * Free user-level context of given memory window. This function call\r
- * should be followed by an invocation to the kernel function which frees\r
- * the memory window resource.\r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_free_mw(hhul_hndl, mw) \\r
- (hhul_hndl)->if_ops->HHULIF_free_mw(hhul_hndl, mw)\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_create_ud_av\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * pd (IN) - PD of created ud_av\r
- * av_p (IN) - Given address vector to create handle for\r
- * ah_p (OUT) - The returned address handle\r
- * \r
- * Returns: HH_OK,\r
- * HH_ENODEV - Unknown device\r
- * HH_EINVAL - Invalid parameters (NULL pointer, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is not in "HH_OPENED" state\r
- * HH_EAGAIN - No available UD AV resources\r
- * \r
- * Description:\r
- * \r
- * This function allocates the privileged resources and returns a handle\r
- * which may be used when posting UD QP WQEs in a system that enforces\r
- * privileged UD AVs.\r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_create_ud_av(hca_hndl, pd, av_p, ah_p) \\r
- (hca_hndl)->if_ops->HHULIF_create_ud_av(hca_hndl, pd, av_p, ah_p)\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_modify_ud_av\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * ah (IN) - The address handle to modify\r
- * av_p (IN) - Modified address vector\r
- * \r
- * Returns: HH_OK,\r
- * HH_ENODEV - Unknown device\r
- * HH_EINVAL - Invalid parameters (NULL pointer, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is not in "HH_OPENED" state\r
- * HH_EINVAL_AV_HNDL - Unknown UD AV handle\r
- * \r
- * Description:\r
- * Modify properties of given UD address handle.\r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_modify_ud_av(hca_hndl, ah, av_p) \\r
- (hca_hndl)->if_ops->HHULIF_modify_ud_av(hca_hndl, ah, av_p)\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_query_ud_av\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * ah (IN) - The address handle to modify\r
- * av_p (IN) - Returned address vector\r
- * \r
- * Returns: HH_OK,\r
- * HH_ENODEV - Unknown device\r
- * HH_EINVAL - Invalid parameters (NULL pointer, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is not in "HH_OPENED" state\r
- * HH_EINVAL_AV_HNDL - Unknown UD AV handle\r
- * \r
- * Description:\r
- * Get address vector data for given address handle.\r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_query_ud_av(hca_hndl, ah, av_p) \\r
- (hca_hndl)->if_ops->HHULIF_query_ud_av(hca_hndl, ah, av_p)\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_destroy_ud_av\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * ah (IN) - The address handle to destroy\r
- * \r
- * Returns: HH_OK,\r
- * HH_ENODEV - Unknown device\r
- * HH_EINVAL - Invalid parameters (NULL pointer, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is not in "HH_OPENED" state\r
- * HH_EINVAL_AV_HNDL - Unknown UD AV handle\r
- * \r
- * Description:\r
- * Free privileged UD address handle resources in HCA.\r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_destroy_ud_av(hca_hndl, ah) \\r
- (hca_hndl)->if_ops->HHULIF_destroy_ud_av(hca_hndl, ah)\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_create_cq_prep\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * hh_cq - The CQ to modify\r
- * num_o_cqes (IN) - Requested minimum number of CQEs in CQ\r
- * hhul_cq_p (OUT) - Returned user-level handle for this CQ\r
- * num_o_cqes_p (OUT) - Actual number of CQEs in updated CQ\r
- * cq_ul_resources_p (OUT) - Pointer to allocated resources\r
- * context (of size cq_ul_resources_sz)\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters\r
- * (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown or not\r
- * in "HH_OPENED" state\r
- * HH_EINVAL_CQ_HNDL - Unknown CQ\r
- * HH_EAGAIN - No available resources to complete \r
- * this operation\r
- * \r
- * Description:\r
- * \r
- * Before creating the CQ in a privileged call user level resources must\r
- * be allocated. This function deals with the allocation of the required\r
- * user level resources based on given parameters.\r
- * \r
- * The resources context is returned in the cq_ul_resources_p and should\r
- * be given to kernel level call. Freeing of these resources is done\r
- * using the function HHUL_destroy_cq_done().\r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_create_cq_prep(\\r
- hca_hndl, num_o_cqes, hhul_cq_p, num_o_cqes_p, cq_ul_resources_p) \\r
- (hca_hndl)->if_ops->HHULIF_create_cq_prep(\\r
- hca_hndl, num_o_cqes, hhul_cq_p, num_o_cqes_p, cq_ul_resources_p)\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_create_cq_done\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * hhul_cq (IN) - The user level CQ handle\r
- * hh_cq (IN) - The CQ allocated by HH\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_CQ_HNDL - Unknown CQ handle\r
- * \r
- * Description:\r
- * \r
- * After creation of the CQ in the privileged call to HH_create_qp()\r
- * through VIP's checkings, this function deals with binding of allocated\r
- * CQ to pre-allocated user-level context.\r
- * \r
- * The CQ cannot be polled before calling this function.\r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_create_cq_done(hca_hndl, hhul_cq, hh_cq, cq_ul_resources_p) \\r
- (hca_hndl)->if_ops->HHULIF_create_cq_done(hca_hndl, hhul_cq, hh_cq, cq_ul_resources_p)\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_resize_cq_prep\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * cq (IN) - The CQ to modify\r
- * num_o_cqes (IN) - Requested minimum number of CQEs in CQ\r
- * num_o_cqes_p (OUT) - Actual number of CQEs in updated CQ\r
- * cq_ul_resources_p (OUT) - Pointer to updated allocated\r
- * resources context for modified CQ\r
- * (of size cq_ul_resources_sz)\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_CQ_HNDL - Unknown CQ\r
- * HH_EAGAIN - No available resources to complete this operation\r
- * HH_EBUSY - Previous resize is still in progress\r
- * \r
- * Description:\r
- * \r
- * This function prepares user-level resources for CQ modification\r
- * (e.g. alternate CQE buffer). It should be called before calling the\r
- * kernel level HH_resize_cq() (which should be called with given updated\r
- * resources context).\r
- * Only one outstanding resize is allowed.\r
- * \r
- ************************************************************************/\r
-#define HHUL_resize_cq_prep(\\r
- hca_hndl, cq, num_o_cqes, num_o_cqes_p, cq_ul_resources_p) \\r
- (hca_hndl)->if_ops->HHULIF_resize_cq_prep(\\r
- hca_hndl, cq, num_o_cqes, num_o_cqes_p, cq_ul_resources_p)\r
-\r
-/************************************************************************\r
- * Function: HHUL_resize_cq_done\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * cq (IN) - The CQ to modify\r
- * cq_ul_resources_p (IN) - Pointer to updated allocated\r
- * resources context for modified CQ\r
- * (of size cq_ul_resources_sz)\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_CQ_HNDL - Unknown CQ or given CQ is not "resizing" \r
- * (i.e. HHUL_resize_cq_prep() was not invoked for it)\r
- * HH_EAGAIN - No available resources to complete this operation\r
- * \r
- * Description:\r
- * \r
- * This function notifies the user-level that the CQ modify operation has\r
- * completed. It should be called after calling the\r
- * kernel level HH_resize_cq() (which should be called with given updated\r
- * resources context).\r
- * \r
- * In case of a failure in HH_resize_cq(), HHUL_resize_cq_done()\r
- * must be called with cq_ul_resources=NULL in order to cause cleanup of \r
- * any resources allocated for CQ modification on HHUL_resize_cq_prep()\r
- * and to assure proper CQ polling.\r
- * \r
- ************************************************************************/\r
-#define HHUL_resize_cq_done(hca_hndl, cq, cq_ul_resources_p) \\r
- (hca_hndl)->if_ops->HHULIF_resize_cq_done(hca_hndl, cq, cq_ul_resources_p)\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_poll4cqe\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * cq (IN) - The CQ to poll\r
- * cqe_p (OUT) - The returned CQE (on HH_OK)\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_CQ_HNDL - Unknown CQ\r
- * HH_CQ_EMPTY - No CQE in given CQ\r
- * \r
- * Description: Pop CQE in head of CQ.\r
- * \r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_poll4cqe(hca_hndl, cq, cqe_p) \\r
- (hca_hndl)->if_ops->HHULIF_poll4cqe(hca_hndl, cq, cqe_p)\r
-\r
-/************************************************************************\r
- * Function: HHUL_poll_and_rearm_cq\r
- *\r
- *\r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * cq (IN) - The CQ to poll\r
- * solicitedNotification (IN) - Notification event type (Next=FALSE or Solicited=TRUE)\r
- * cqe_p (OUT) - The returned CQE (on HH_OK)\r
- *\r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_CQ_HNDL - Unknown CQ\r
- * HH_CQ_EMPTY - No CQE in given CQ\r
- * HH_EAGAIN - cqe is valid, cq has been rearmed, do subsequent poll4cqe calls\r
- *\r
- * Description: if head of CQ is valid then pop head of CQ and return HH_OK\r
- * otherwise rearm the CQ and then check the head of the CQ again\r
- * if the head of the CQ is valid then pop head of CQ and return HH_EAGIN\r
- * otherwise return HH_CQ_EMPTY\r
- *\r
- *\r
- ************************************************************************/\r
-\r
-#define HHUL_poll_and_rearm_cq(hca_hndl, cq, solicitedNotification, cqe_p) \\r
- (hca_hndl)->if_ops->HHULIF_poll_and_rearm_cq(hca_hndl, cq, solicitedNotification, cqe_p)\r
-\r
- \r
-/**********************************************************\r
- * \r
- * Function: HHUL_peek_cq\r
- *\r
- * Arguments:\r
- * hca_hndl: Handle to HCA.\r
- * cq: CQ Handle.\r
- * cqe_num: Number of CQE to peek to (next CQE is #1)\r
- *\r
- * Returns:\r
- * HH_OK: At least cqe_num CQEs outstanding in given CQ\r
- * HH_CQ_EMPTY: Less than cqe_num CQEs are outstanding in given CQ\r
- * HH_E2BIG_CQ_NUM: cqe_index is beyond CQ size (or 0)\r
- * HH_EINVAL_CQ_HNDL: invalid CQ handle\r
- * HH_EINVAL_HCA_HNDL: invalid HCA handle\r
- *\r
- * Description:\r
- * Check if there are at least cqe_num CQEs outstanding in the CQ.\r
- * (i.e., peek into the cqe_num CQE in the given CQ). \r
- * No CQE is consumed from the CQ.\r
- *\r
- **********************************************************/\r
-#define HHUL_peek_cq(hca_hndl,cq,cqe_num) \\r
- (hca_hndl)->if_ops->HHULIF_peek_cq(hca_hndl, cq, cqe_num)\r
-\r
-/************************************************************************\r
- * Function: HHUL_req_comp_notif\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * cq (IN) - The CQ to poll\r
- * notif_type (IN) - Notification event type (Next or Solicited)\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_CQ_HNDL - Unknown CQ\r
- * \r
- * Description: Request completion notification for given CQ.\r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_req_comp_notif(hca_hndl, cq, notif_type) \\r
- (hca_hndl)->if_ops->HHULIF_req_comp_notif(hca_hndl, cq, notif_type)\r
-\r
-/*************************************************************************\r
- * Function: HHUL_req_ncomp_notif\r
- *\r
- * Arguments:\r
- * hca_hndl: Handle to HCA.\r
- * cq: CQ Handle.\r
- * cqe_num: Number of outstanding CQEs which trigger this notification \r
- * (This may be 1 up to CQ size, limited by HCA capability - 0x7FFF for InfiniHost)\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_CQ_HNDL: invalid CQ handle\r
- * VAPI_E2BIG_CQ_NUM: cqe_index is beyond CQ size or beyond HCA notification capability (or 0)\r
- * For InfiniHost cqe_num is limited to 0x7FFF.\r
- * VAPI_EPERM: not enough permissions.\r
- * \r
- * \r
- *\r
- * Description:\r
- * Request notification when CQ holds at least N (non-polled) CQEs\r
- * \r
- *\r
- *************************************************************************/ \r
-#define HHUL_req_ncomp_notif(hca_hndl, cq, cqe_num) \\r
- (hca_hndl)->if_ops->HHULIF_req_ncomp_notif(hca_hndl, cq, cqe_num)\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_destroy_cq_done\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * cq (IN) - The CQ to free user level resources for\r
- * \r
- * \r
- * Arguments: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_CQ_HNDL - Unknown CQ\r
- * \r
- * Description:\r
- * \r
- * This function frees the user level resources allocated during\r
- * HHUL_create_cq_prep(). It must be called after succesfully calling the\r
- * kernel level HH_destroy_cq() (or when HH_create_cq() fails).\r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_destroy_cq_done(hca_hndl, cq) \\r
- (hca_hndl)->if_ops->HHULIF_destroy_cq_done(hca_hndl, cq)\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_create_qp_prep\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * qp_init_attr_p - init attributes for the QP\r
- * qp_hndl_p (OUT) - User level QP handle\r
- * qp_cap_out_p (OUT) - Actual QP capabilities\r
- * qp_ul_resources_p (OUT) - The user-level resources context\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_QP_HNDL - Unknown QP (number)\r
- * HH_EAGAIN - No available resources to complete this operation\r
- * \r
- * Description:\r
- * \r
- * This function allocates user level resources for a new QP. It is\r
- * called before calling the kernel level HH_create_qp(). \r
- * The allocated resources context returned in qp_ul_resources_p should\r
- * be passed to HH_create_qp() in order to\r
- * synchronize the hardware context.\r
- * \r
- * Freeing of resources allocated here may be done using the function\r
- * HHUL_destroy_qp_done().\r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_create_qp_prep(\\r
- hca_hndl, qp_init_attr_p, qp_hndl_p, qp_cap_out_p, qp_ul_resources_p) \\r
- (hca_hndl)->if_ops->HHULIF_create_qp_prep(\\r
- hca_hndl, qp_init_attr_p, qp_hndl_p, qp_cap_out_p, qp_ul_resources_p)\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_special_qp_prep\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * special_qp_type (IN) - Type of special QP to prepare for\r
- * port - Port number for special QP.\r
- * qp_init_attr_p - init attributes for the QP\r
- * qp_hndl_p (OUT) - User level QP handle\r
- * qp_cap_out_p (OUT) - Actual QP capabilities\r
- * qp_ul_resources_p (OUT) - The user-level resources context\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_QP_HNDL - Unknown QP (number)\r
- * HH_EAGAIN - No available resources to complete this operation\r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_special_qp_prep(\\r
- hca_hndl, qp_type, port, qp_init_attr_p, qp_hndl_p, qp_cap_out_p, qp_ul_resources_p) \\r
- (hca_hndl)->if_ops->HHULIF_special_qp_prep(\\r
- hca_hndl, qp_type, port, qp_init_attr_p, qp_hndl_p, qp_cap_out_p, qp_ul_resources_p)\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_create_qp_done\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * hhul_qp (IN) - The user-level QP context\r
- * hh_qp (IN) - The QP number (or handle for special QP) returned\r
- * by HH on QP creation.\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_QP_HNDL - Unknown QP (for HHUL's)\r
- * \r
- * Description:\r
- * \r
- * On succesful call to HH's QP creation function this function should be\r
- * called in order to enable the QP. This function performs the binding\r
- * of the hardware QP resource allocated to the user-level QP context.\r
- * \r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_create_qp_done(hca_hndl, hhul_qp, hh_qp, qp_ul_resources_p) \\r
- (hca_hndl)->if_ops->HHULIF_create_qp_done(hca_hndl, hhul_qp, hh_qp, qp_ul_resources_p)\r
-\r
-/************************************************************************\r
- * Function: HHUL_modify_qp_done\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * hhul_qp (IN) - The user-level QP context\r
- * cur_state (IN) - state of QP after modify operation.\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_QP_HNDL - Unknown QP (for HHUL's)\r
- * \r
- * Description:\r
- * \r
- * On succesful call to HH's QP modify function this function should be\r
- * called in order to synchronize the user copy of the QP state with the\r
- * actual QP state after the modify-qp operation.\r
- * \r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_modify_qp_done(hca_hndl, hhul_qp, cur_state) \\r
- (hca_hndl)->if_ops->HHULIF_modify_qp_done(hca_hndl, hhul_qp, cur_state)\r
- \r
-/************************************************************************\r
- * Function: HHUL_post_send_req\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * qp_hndl (IN) - User level QP handle\r
- * send_req_p (IN) - Send request\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_QP_HNDL - Unknown QP (number)\r
- * HH_EAGAIN - No available resources to complete this operation\r
- * HH_EINVAL_WQE - Invalid send request (send_req_p)\r
- * HH_EINVAL_SG_NUM - Scatter/Gather list length error\r
- * HH_EINVAL_QP_STATE - Invalid QP state (not RTS)\r
- * HH_EINVAL_AV_HNDL - Invalid UD address handle (UD only)\r
- * HH_EINVAL_OPCODE - Invalid opcode for given send-q\r
- * \r
- * Description:\r
- * \r
- * This function posts a send request to the send queue of the given\r
- * QP. QP must be in RTS state.\r
- * \r
- * Every WQE successfully posted (HH_OK) must create a CQE in the CQ\r
- * associated with this send queue (unless QP explicitly moved to RESET\r
- * state).\r
- * \r
- * \r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_post_send_req(hca_hndl, qp_hndl, send_req_p) \\r
- (hca_hndl)->if_ops->HHULIF_post_send_req(hca_hndl, qp_hndl, send_req_p)\r
-\r
-#define HHUL_post_send_req2(hca_hndl,qp_hndl,comp_tp,r_ah,WorkReq ) \\r
- (hca_hndl)->if_ops->HHULIF_post_send_req2(hca_hndl, qp_hndl, comp_tp,r_ah,WorkReq)\r
- \r
-#define HHUL_post_send_reqs(hca_hndl, qp_hndl, num_of_requests, send_req_array) \\r
- (hca_hndl)->if_ops->HHULIF_post_send_reqs(hca_hndl, qp_hndl, num_of_requests,send_req_array)\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_post_inline_send_req\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * qp_hndl (IN) - User level QP handle\r
- * send_req_p (IN) - Send request with a signle gather entry\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_QP_HNDL - Unknown QP (number)\r
- * HH_EAGAIN - No available resources to complete this operation\r
- * HH_EINVAL_WQE - Invalid send request (send_req_p)\r
- * HH_EINVAL_SG_NUM - Scatter/Gather list length error\r
- * HH_EINVAL_QP_STATE - Invalid QP state (not RTS)\r
- * HH_EINVAL_AV_HNDL - Invalid UD address handle (UD only)\r
- * HH_EINVAL_OPCODE - Invalid opcode for given send-q\r
- * \r
- * Description:\r
- * \r
- * This function posts an inline send request (data copied into WQE)\r
- * The request may be send, send w/immediate, RDMA-wrire , RDMA-write w/immediate.\r
- * Gather list may be of one entry only, and data length is defined in QP capabilities\r
- * (max_inline_data_sq) - to be defined in create_qp and queries via query_qp.\r
- * \r
- ************************************************************************/\r
-#define HHUL_post_inline_send_req(hca_hndl, qp_hndl, send_req_p) \\r
- (hca_hndl)->if_ops->HHULIF_post_inline_send_req(hca_hndl, qp_hndl, send_req_p)\r
-\r
-/************************************************************************\r
- * Function: HHUL_post_gsi_send_req\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * qp_hndl (IN) - User level QP handle\r
- * send_req_p (IN) - Send request with a signle gather entry\r
- * pkey_index (IN) - Pkey index to put in outgoing\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_QP_HNDL - Unknown QP (number)\r
- * HH_EAGAIN - No available resources to complete this operation\r
- * HH_EINVAL_WQE - Invalid send request (send_req_p)\r
- * HH_EINVAL_SG_NUM - Scatter/Gather list length error\r
- * HH_EINVAL_QP_STATE - Invalid QP state (not RTS)\r
- * HH_EINVAL_AV_HNDL - Invalid UD address handle \r
- * HH_EINVAL_OPCODE - Invalid opcode for given send-q\r
- * \r
- * Description:\r
- * \r
- * This function posts an inline send request (data copied into WQE)\r
- * The request may be send, send w/immediate, RDMA-wrire , RDMA-write w/immediate.\r
- * Gather list may be of one entry only, and data length is defined in QP capabilities\r
- * (max_inline_data_sq) - to be defined in create_qp and queries via query_qp.\r
- * \r
- ************************************************************************/\r
-#define HHUL_post_gsi_send_req(hca_hndl, qp_hndl, send_req_p, pkey_index) \\r
- (hca_hndl)->if_ops->HHULIF_post_gsi_send_req(hca_hndl, qp_hndl, send_req_p, pkey_index)\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_post_recv_req\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * qp_hndl (IN) - User level QP handle\r
- * recv_req_p (IN) - Receive request\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_QP_HNDL - Unknown QP (number)\r
- * HH_EAGAIN - No available resources to complete this operation\r
- * HH_EINVAL_WQE - Invalid send request (send_req_p)\r
- * HH_EINVAL_SG_NUM - Scatter/Gather list length error\r
- * HH_EINVAL_QP_STATE - Invalid QP state (RESET or ERROR)\r
- * \r
- * Description:\r
- * \r
- * This function posts a receive request to the receive queue of the\r
- * given QP. QP must not be in RESET or ERROR state.\r
- * \r
- * Every WQE successfully posted (HH_OK) must create a CQE in the CQ\r
- * associated with this send queue (unless QP explicitly moved to RESET\r
- * state).\r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_post_recv_req(hca_hndl, qp_hndl, recv_req_p) \\r
- (hca_hndl)->if_ops->HHULIF_post_recv_req(hca_hndl, qp_hndl, recv_req_p)\r
-\r
-#define HHUL_post_recv_req2(hca_hndl, qp_hndl, comp_type,sg_lst_len,ReqId,sg_lst_p) \\r
- (hca_hndl)->if_ops->HHULIF_post_recv_req2(hca_hndl, qp_hndl, comp_type,sg_lst_len,ReqId,sg_lst_p)\r
- \r
-#define HHUL_post_recv_reqs(hca_hndl, qp_hndl, num_of_requests, recv_req_array) \\r
- (hca_hndl)->if_ops->HHULIF_post_recv_reqs(hca_hndl, qp_hndl, num_of_requests,recv_req_array)\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_destroy_qp_done\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * qp_hndl (IN) - User level handle of QP to destroy\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_QP_HNDL - Unknown QP (number)\r
- * \r
- * Description:\r
- * \r
- * This function frees the user level resources allocated during\r
- * HHUL_create_qp_prep(). It must be called after succesfully calling the\r
- * kernel level HH_destroy_qp() (or on failure of HH_create_qp() or\r
- * HH_get_special_qp() ).\r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_destroy_qp_done(hca_hndl, qp_hndl) \\r
- (hca_hndl)->if_ops->HHULIF_destroy_qp_done(hca_hndl, qp_hndl)\r
-\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_create_srq_prep\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * max_outs (IN) - Requested max. outstanding WQEs in the SRQ\r
- * max_sentries (IN)- Requested max. scatter entries per WQE\r
- * srq_hndl_p (OUT) - Returned (HHUL) SRQ handle\r
- * max_outs_p (OUT) - Actual limit on number of outstanding WQEs\r
- * max_sentries(OUT)- Actual limit on scatter entries per WQE\r
- * srq_ul_resources_p(OUT)- SRQ user-level resources context (to pass down)\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, etc.)\r
- * HH_E2BIG_WR_NUM - requested max. outstanding WQEs is higher than HCA capability\r
- * HH_E@BIG_SG_NUM - requested sentries is higher than HCA capability\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EAGAIN - No available resources to complete this operation\r
- * \r
- * Description:\r
- * This function allocates user level resources for a new SRQ. It is\r
- * called before calling the kernel level HH_create_srq(). \r
- * The allocated resources context returned in srq_ul_resources_p should\r
- * be passed to HH_create_srq() in order to synchronize the hardware context.\r
- * \r
- * Freeing of resources allocated here may be done using the function\r
- * HHUL_destroy_srq_done().\r
- * \r
- ************************************************************************/\r
-#define HHUL_create_srq_prep(hca_hndl, pd, max_outs, max_sentries, \\r
- srq_hndl_p, actual_max_outs_p, acutal_max_sentries, \\r
- srq_ul_resources_p) \\r
- (hca_hndl)->if_ops->HHULIF_create_srq_prep(hca_hndl, pd, max_outs, max_sentries, \\r
- srq_hndl_p, actual_max_outs_p, acutal_max_sentries, \\r
- srq_ul_resources_p)\r
-\r
-/************************************************************************\r
- * Function: HHUL_create_srq_done\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * hhul_srq (IN) - The user-level SRQ context\r
- * hh_srq (IN) - The SRQ handle returned by HH on SRQ creation.\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_SRQ_HNDL - Unknown SRQ (for HHUL's)\r
- * \r
- * Description:\r
- * On succesful call to HH's SRQ creation function this function should be\r
- * called in order to enable the SRQ. This function performs the binding\r
- * of the hardware SRQ resource allocated to the user-level QP context.\r
- * \r
- * \r
- ************************************************************************/\r
-#define HHUL_create_srq_done(hca_hndl, hhul_srq, hh_srq, srq_ul_resources_p) \\r
- (hca_hndl)->if_ops->HHULIF_create_srq_done(hca_hndl, hhul_srq, hh_srq, srq_ul_resources_p)\r
-\r
-/************************************************************************\r
- * Function: HHUL_modify_srq_prep\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * srq_hndl (IN) - (HHUL) SRQ handle\r
- * srq_attr_p(IN) - New attributes values\r
- * srq_attr_mask(IN)- Flags for attributes to change\r
- * srq_ul_resources_p(OUT)- SRQ user-level resources context (to pass down)\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_SRQ_HNDL\r
- * HH_E2BIG_WR_NUM - requested max. outstanding WQEs is higher than HCA capability\r
- * HH_ENOSYS - Unsupported feature (e.g., limit event)\r
- * HH_EAGAIN - No available resources to complete this operation\r
- * HH_EINVAL - Invalid parameters (NULL pointer, etc.)\r
- * \r
- * Description:\r
- * This function allocates user level resources for modifying a SRQ. It is\r
- * called before calling the kernel level HH_modify_srq(). \r
- * The allocated resources context returned in srq_ul_resources_p should\r
- * be passed to HH_modify_srq() in order to synchronize the hardware context.\r
- * \r
- * Freeing of resources allocated here may be done using the function\r
- * HHUL_modify_srq_done().\r
- * \r
- ************************************************************************/\r
-#define HHUL_modify_srq_prep(hca_hndl, srq_hndl, srq_attr_p, srq_attr_mask, \\r
- srq_ul_resources_p) \\r
- (hca_hndl)->if_ops->HHULIF_modify_srq_prep(hca_hndl, srq_hndl, srq_attr_p, srq_attr_mask,\\r
- srq_ul_resources_p)\r
-\r
-/************************************************************************\r
- * Function: HHUL_modify_srq_done\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * hhul_srq (IN) - The user-level SRQ context\r
- * srq_ul_resources_p (IN) - UL resources buffer returned from HH_modify_srq().\r
- * max_outs_wr_p (OUT) - Actual max. outstanding WQEs per SRQ (after modify)\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_SRQ_HNDL - Unknown SRQ (for HHUL's)\r
- * HH_EAGAIN - Not enough resources to complete operation.\r
- * HH_EFATAL - unexpected (consistancy) error\r
- * \r
- * Description:\r
- * On succesful call to HH_modify_srq this function should be\r
- * called in order to enable the SRQ. This function completes the transition\r
- * to the new SRQ resources (after resizing).\r
- * If this function fails, the resize is enulled.\r
- *\r
- * In case of error in HH_modify_srq - this function should be called with \r
- * srq_ul_resources_p==NULL. This would free any resources allocated during\r
- * HHUL_modify_srq_prep().\r
- * \r
- * \r
- ************************************************************************/\r
-#define HHUL_modify_srq_done(hca_hndl, hhul_srq, srq_ul_resources_p, max_outs_wr_p) \\r
- (hca_hndl)->if_ops->HHULIF_modify_srq_done(hca_hndl, hhul_srq, srq_ul_resources_p, max_outs_wr_p)\r
-\r
-/************************************************************************\r
- * Function: HHUL_destroy_srq_done\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * srq_hndl (IN) - User level handle of SRQ to destroy\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_SRQ_HNDL - Unknown SRQ\r
- * \r
- * Description:\r
- * This function frees the user level resources allocated during\r
- * HHUL_create_srq_prep(). It must be called after succesfully calling the\r
- * kernel level HH_destroy_srq() (or on failure of HH_create_srq()).\r
- * \r
- ************************************************************************/\r
-#define HHUL_destroy_srq_done(hca_hndl, hhul_srq) \\r
- (hca_hndl)->if_ops->HHULIF_destroy_srq_done(hca_hndl, hhul_srq) \r
-\r
-/************************************************************************\r
- * Function: HHUL_post_srq\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * hhul_srq (IN) - User level SRQ handle\r
- * num_of_requests (IN) - Number of requests given in recv_req_array\r
- * recv_req_array (IN) - Array of receive requests\r
- * posted_requests_p (OUT) - Actually commited/posted requests (valid also in error).\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_QP_HNDL - Unknown QP (number)\r
- * HH_EAGAIN - No available resources to complete this operation\r
- * HH_EINVAL_WQE - Invalid send request (send_req_p)\r
- * HH_EINVAL_SG_NUM - Scatter/Gather list length error\r
- * HH_EINVAL_QP_STATE - Invalid QP state (RESET or ERROR)\r
- * \r
- * Description:\r
- * This function posts receive requests to the given SRQ.\r
- * Upon error return code, returned *posted_requests_p identify the number of requests\r
- * successfully posted (or the index of the failing WQE). The error code refer to the\r
- * request in index *posted_requests_p.\r
- * \r
- ************************************************************************/\r
-#define HHUL_post_srq(hca_hndl, hhul_srq, num_of_requests, recv_req_array, posted_requests_p) \\r
- (hca_hndl)->if_ops->HHULIF_post_srq(hca_hndl, hhul_srq, num_of_requests, recv_req_array, \\r
- posted_requests_p)\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_alloc_pd_prep\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * hhul_qp_p (OUT) - Returned user-level handle for this QP\r
- * pd_ul_resources_p (OUT) - Pointer to allocated resources\r
- * context (of size pd_ul_resources_sz)\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters\r
- * (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown or not\r
- * in "HH_OPENED" state\r
- * HH_EAGAIN - No available resources to complete \r
- * this operation\r
- * \r
- * Description:\r
- * \r
- * Before creating the PD in a privileged call user level resources must\r
- * be allocated. This function deals with the allocation of the required\r
- * user level resources based on given parameters.\r
- * \r
- * The resources context is returned in the pd_ul_resources_p and should\r
- * be given to kernel level call. Freeing of these resources is done\r
- * using the function HHUL_free_pd_done().\r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_alloc_pd_prep(\\r
- hca_hndl, hhul_pd_p, pd_ul_resources_p) \\r
- (hca_hndl)->if_ops->HHULIF_alloc_pd_prep(hca_hndl, hhul_pd_p, pd_ul_resources_p)\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_alloc_pd_done\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * hhul_pd (IN) - The user level PD handle\r
- * hh_pd (IN) - The PD allocated by HH\r
- * pd_ul_resources_p (OUT) - Pointer to allocated resources\r
- * context (of size pd_ul_resources_sz)\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_PD_HNDL - Unknown CQ handle\r
- * \r
- * Description:\r
- * \r
- * After creation of the PD in the privileged call to HH_alloc_pd()\r
- * through VIP's checkings, this function deals with binding of allocated\r
- * PD to pre-allocated user-level context.\r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_alloc_pd_done(hca_hndl, hhul_pd, hh_pd, pd_ul_resources_p) \\r
- (hca_hndl)->if_ops->HHULIF_alloc_pd_done(hca_hndl, hhul_pd, hh_pd, pd_ul_resources_p)\r
-\r
-/************************************************************************\r
- * Function: HHUL_free_pd_prep\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * pd (IN) - The PD to free user level resources for\r
- * undo_flag (IN) - if TRUE, undo the previous free_pd_prep,\r
- * and restore the PD\r
- * \r
- * \r
- * Arguments: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_PD_HNDL - Unknown PD\r
- * HH_EBUSY - when prepping (undo_flag = FALSE), indicates that PD\r
- * still has allocated udav's\r
- * \r
- * Description:\r
- * \r
- * This function prepares the user level resources allocated during\r
- * HHUL_alloc_pd_prep() for freeing, checking if there are still UDAVs allocated to this PD.\r
- * It must be called before calling the kernel level HH_free_pd().\r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_free_pd_prep(hca_hndl, pd, undo_flag) \\r
- (hca_hndl)->if_ops->HHULIF_free_pd_prep(hca_hndl, pd, undo_flag)\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_free_pd_done\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * pd (IN) - The PD to free user level resources for\r
- * \r
- * \r
- * Arguments: HH_OK,\r
- * HH_EINVAL - Invalid parameters (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown not in "HH_OPENED" state\r
- * HH_EINVAL_PD_HNDL - Unknown PD\r
- * \r
- * Description:\r
- * \r
- * This function frees the user level resources allocated during\r
- * HHUL_alloc_pd_prep(). It must be called after succesfully calling the\r
- * kernel level HH_free_pd() (or when HH_alloc_pd() fails).\r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_free_pd_done(hca_hndl, pd) \\r
- (hca_hndl)->if_ops->HHULIF_free_pd_done(hca_hndl, pd)\r
-\r
-\r
-/************************************************************************\r
- * Set the if_ops tbl with dummy functions returning HH_ENOSYS.\r
- * This is convenient for initializing tables prior\r
- * setting them with partial real implementation.\r
- *\r
- * This way, the general HH_if_ops_t table structure can be extended,\r
- * requiring just recompilation.\r
- ************************************************************************/\r
-extern void HHUL_ifops_tbl_set_enosys(HHUL_if_ops_t* tbl);\r
-\r
-\r
-/************************************************************************\r
- * Function: HHUL_alloc_pd_avs_prep\r
- * \r
- * \r
- * Arguments: hca_hndl (IN) - User level handle of the HH device context\r
- * max_num_avs - desired max number of AVs to be available for this PD\r
- * pd_flags - currently, if is a PD for a SQP or not.\r
- * hhul_qp_p (OUT) - Returned user-level handle for this QP\r
- * pd_ul_resources_p (OUT) - Pointer to allocated resources\r
- * context (of size pd_ul_resources_sz)\r
- * \r
- * Returns: HH_OK,\r
- * HH_EINVAL - Invalid parameters\r
- * (NULL pointer, invalid L-Key, etc.)\r
- * HH_EINVAL_HCA_HNDL - Given HCA is unknown or not\r
- * in "HH_OPENED" state\r
- * HH_EAGAIN - No available resources to complete \r
- * this operation\r
- * \r
- * Description:\r
- * \r
- * Before creating the PD in a privileged call user level resources must\r
- * be allocated. This function deals with the allocation of the required\r
- * user level resources based on given parameters.\r
- *\r
- * If the caller desires to use the default maximum number of AVs for this PD,\r
- * max_num_avs should be set to EVAPI_DEFAULT_AVS_PER_PD.\r
- * \r
- * The resources context is returned in the pd_ul_resources_p and should\r
- * be given to kernel level call. Freeing of these resources is done\r
- * using the function HHUL_free_pd_done().\r
- * \r
- ************************************************************************/\r
-\r
-#define HHUL_alloc_pd_avs_prep(\\r
- hca_hndl,max_num_avs, pd_flags, hhul_pd_p, pd_ul_resources_p) \\r
- (hca_hndl)->if_ops->HHULIF_alloc_pd_avs_prep(hca_hndl, max_num_avs, pd_flags,hhul_pd_p, pd_ul_resources_p)\r
-\r
-\r
-/************************************************************************\r
- * Some common struct's to be used by lower level drivers\r
- */\r
-\r
-\r
-/* Send Request Descriptor */\r
-struct HHUL_sr_wqe_st {\r
- struct HHUL_sr_wqe_st *next; /* for WQEs list */\r
- struct HHUL_sr_wqe_st *ul_wqe_p; /* For passing from kernel to user */\r
-\r
- VAPI_wr_id_t id;\r
-\r
- VAPI_wr_opcode_t opcode;\r
- VAPI_comp_type_t comp_type;\r
-\r
- VAPI_imm_data_t imm_data;\r
- MT_bool fence;\r
- MT_bool av_valid; /* TRUE is following AV is valid */\r
- VAPI_ud_av_t av;\r
- VAPI_qp_num_t remote_qp;\r
- VAPI_qkey_t remote_qkey;\r
- VAPI_ethertype_t ethertype;\r
-\r
- MT_bool set_se;\r
- VAPI_virt_addr_t remote_addr;\r
-\r
-\r
- VAPI_rkey_t r_key;\r
- u_int64_t operand1; /* for atomic */\r
- u_int64_t operand2; /* for atomic */\r
-\r
- u_int32_t sg_lst_len;\r
-\r
- /* TBD - Add AckReg - Data Seg - If Gent - */\r
-\r
- /* TBD - Add support for reliable datagram (RD) */\r
- u_int32_t sg_total_byte_len;\r
-\r
- VAPI_sg_lst_entry_t sg_lst_p[1];\r
-\r
- /* here comes the data ...\r
- * if (sg_lst_len > 0)\r
- * MALLOC(sizeof(HH_sr_wqe_t)+[sg_lst_len-1]*sizeof(VAPI_sg_lst_entry_t))\r
- */\r
-\r
-}; /* HHUL_sr_wqe_t */;\r
-\r
-\r
-/* Receive Request WQE */ /* TBD - move to HH */\r
-struct HHUL_rr_wqe_st {\r
- struct HHUL_rr_wqe_st* next; /* Next wqe in receive queue */\r
- struct HHUL_rr_wqe_st* prev; /* Previous wqe in receive queue */\r
-\r
- VAPI_wr_id_t id; /* ID provided by the user */\r
-\r
- VAPI_comp_type_t comp_type; /* Mellanox Specific\r
- * {VAPI_SIGNALED, VAPI_UNSIGNALED} */\r
- u_int32_t total_len; /* Current s/g list length -\r
- * need to calculate it */\r
- u_int32_t sg_lst_len;\r
- VAPI_sg_lst_entry_t sg_lst_p[1]; /* TBD is it ok to define this way */\r
-\r
- /* here comes the data ...\r
- * if (sg_lst_len > 0)\r
- * MALLOC(sizeof(HHUL_rr_wqe_t)+[sg_lst_len-1]*sizeof(VAPI_sg_lst_entry_t))\r
- */\r
-} /* HHUL_rr_wqe_t */;\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-typedef struct {\r
- MT_virt_addr_t addr;\r
- MT_virt_addr_t len;\r
- VAPI_lkey_t lkey;\r
-} HHUL_sg_lst_entry_t;\r
-\r
-\r
-\r
-/* Receive Request WQE */ \r
-typedef struct HH_rr_wqe_st {\r
- VAPI_wr_id_t id; /* ID provided by the user */\r
-\r
- MT_virt_addr_t next; /* next wqe in struct */\r
-\r
- VAPI_comp_type_t comp_type; /* Mellanox Specific {VAPI_SIGNALED, VAPI_UNSIGNALED} */\r
- u_int32_t total_len; /* Current s/g list length - need to calculate it */\r
-\r
- u_int32_t sg_lst_len;\r
- HHUL_sg_lst_entry_t sg_lst_p[1]; /* TBD is this ok to define it this way */\r
-\r
- /* here comes the data ...\r
- * malloc(sizeof(GHQPC_rr_wqe_t)+[sg_lst_len-1]*sizeof(VAPI_sg_lst_entry_t)) \r
- */\r
-} HHUL_rr_wqe_t;\r
-\r
-\r
-#if 0\r
-/* TBD - probably obsolete. see HH_sr_wqe_t in hhul_common.h */\r
-/* Send Request Descriptor */\r
-typedef struct HHUL_sr_desc_st \r
-{\r
- HH_hca_hndl_t hh_hca_hndl; /* Handle to HCA */\r
- \r
- VAPI_sr_desc_t vapi_sr_desc; /* VAPI Send Request Descriptor */\r
- \r
- VAPI_av_t vapi_av;\r
-\r
- HHUL_sg_lst_entry_t *hh_sg_lst;\r
- \r
- /* TBD - Add AckReg - Data Seg - If Gent - */\r
-\r
- /* TBD - Add support for reliable datagram (RD) */\r
-\r
-} HH_sr_desc_t;\r
-#endif\r
-\r
-\r
-\r
-struct HHUL_hca_obj {\r
- HH_hca_hndl_t hca_hndl;\r
-\r
- HHUL_qp_obj_st *qp_head;\r
- HHUL_cq_obj_st *cq_head;\r
- \r
- /* TBD - Add support for address vector image */\r
- /* TBD - Add support for RDD */\r
- \r
-} HHUL_hca_obj_t;\r
-\r
-\r
-\r
-#endif /* H_HHUL_OBJ_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-HH_ret_t HHUL_destroy_qp(HHUL_hca_hndl_t hca_hndl, VAPI_qp_num_t qp_num)\r
-{\r
- return HH_OK;\r
-}\r
-\r
-\r
-\r
-HH_ret_t HHUL_get_qp_state(HHUL_hca_hndl_t hca_hndl, VAPI_qp_num_t qp_num, VAPI_qp_state_t *qp_state_p)\r
-{\r
- *qp_state_p = VAPI_RESET;\r
- return HH_OK; \r
-}\r
-\r
-\r
-HH_ret_t HHUL_create_cq(HHUL_hca_hndl_t hca_hndl, HH_cq_num_t cq_num, MT_virt_addr_t cq_buff, MT_virt_addr_t cq_size)\r
-{\r
- return HH_OK;\r
-}\r
-\r
-\r
-HH_ret_t HHUL_destroy_cq(HHUL_hca_hndl_t hca_hndl, HH_cq_num_t cq_num)\r
-{\r
- return HH_OK;\r
-}\r
-\r
-\r
-\r
-/* TBD - Complete Memory Windows Registration */\r
-/* HHUL_bind_memory_region */\r
-\r
-\r
-\r
-HH_ret_t HHUL_post_send_wr(HHUL_hca_hndl_t hca_hndl, VAPI_sr_desc_t *vapi_sr_desc_p, VAPI_ud_av_t *vapi_av_p) /* TBD - EEC */\r
-{\r
- return HH_OK;\r
-}\r
-\r
-\r
-HH_ret_t HHUL_post_receive_wr(HH_hca_hndl_t hca_hndl, VAPI_rr_desc_t *vapi_rr_desc_p)\r
-{\r
- return HH_OK;\r
-}\r
-\r
-\r
-\r
-HH_ret_t HHUL_poll_for_completion(HHUL_hca_hndl_t hca_hndl, HH_cq_num_t cq_num,\r
- VAPI_wc_desc_t *VAPI_comp_desc_p)\r
-{\r
- return HH_OK;\r
-}\r
-\r
-\r
-\r
-\r
-HH_ret_t HHUL_req_comp_notify(HH_hca_hndl_t hca_hndl, HH_cq_num_t cq_num, VAPI_cq_notif_type_t cq_not_type)\r
-{\r
- return HH_OK;\r
-}\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id:$\r
- */\r
-\r
-\r
-static HH_ret_t enosys_cleanup_user_level(\r
- HHUL_hca_hndl_t hhul_hndl\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_alloc_pd_prep(\r
- HHUL_hca_hndl_t hca_hndl,\r
- HHUL_pd_hndl_t* hhul_pd_p,\r
- void* pd_ul_resources_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_alloc_pd_done(\r
- HHUL_hca_hndl_t hca_hndl,\r
- HHUL_pd_hndl_t hhul_pd,\r
- HH_pd_hndl_t hh_pd,\r
- void* pd_ul_resources_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_free_pd_done(\r
- HHUL_hca_hndl_t hca_hndl,\r
- HHUL_pd_hndl_t hhul_pd\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_alloc_mw(\r
- HHUL_hca_hndl_t hhul_hndl,\r
- IB_rkey_t initial_rkey,\r
- HHUL_mw_hndl_t* mw_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_bind_mw(\r
- HHUL_hca_hndl_t hhul_hndl,\r
- HHUL_mw_hndl_t mw,\r
- HHUL_mw_bind_t* bind_prop_p,\r
- IB_rkey_t* bind_rkey_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_free_mw(\r
- HHUL_hca_hndl_t hhul_hndl,\r
- HHUL_mw_hndl_t mw\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_create_ud_av(\r
- HHUL_hca_hndl_t hca_hndl,\r
- HHUL_pd_hndl_t pd, \r
- VAPI_ud_av_t* av_p,\r
- HHUL_ud_av_hndl_t* ah_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_modify_ud_av(\r
- HHUL_hca_hndl_t hca_hndl,\r
- HHUL_ud_av_hndl_t ah,\r
- VAPI_ud_av_t* av_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_query_ud_av(\r
- HHUL_hca_hndl_t hca_hndl,\r
- HHUL_ud_av_hndl_t ah,\r
- VAPI_ud_av_t* av_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_destroy_ud_av(\r
- HHUL_hca_hndl_t hca_hndl,\r
- HHUL_ud_av_hndl_t ah\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_create_cq_prep(\r
- HHUL_hca_hndl_t hca_hndl,\r
- VAPI_cqe_num_t num_o_cqes,\r
- HHUL_cq_hndl_t* hhul_cq_p,\r
- VAPI_cqe_num_t* num_o_cqes_p,\r
- void* cq_ul_resources_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_create_cq_done(\r
- HHUL_hca_hndl_t hca_hndl,\r
- HHUL_cq_hndl_t hhul_cq,\r
- HH_cq_hndl_t hh_cq,\r
- void* cq_ul_resources_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_resize_cq_prep(\r
- HHUL_hca_hndl_t hca_hndl,\r
- HHUL_cq_hndl_t cq,\r
- VAPI_cqe_num_t num_o_cqes,\r
- VAPI_cqe_num_t* num_o_cqes_p,\r
- void* cq_ul_resources_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_resize_cq_done(\r
- HHUL_hca_hndl_t hca_hndl,\r
- HHUL_cq_hndl_t cq,\r
- void* cq_ul_resources_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_poll4cqe(\r
- HHUL_hca_hndl_t hca_hndl,\r
- HHUL_cq_hndl_t cq,\r
- VAPI_wc_desc_t* cqe_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_peek_cq(\r
- HHUL_hca_hndl_t hca_hndl,\r
- HHUL_cq_hndl_t cq,\r
- VAPI_cqe_num_t cqe_num\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_req_comp_notif(\r
- HHUL_hca_hndl_t hca_hndl,\r
- HHUL_cq_hndl_t cq,\r
- VAPI_cq_notif_type_t notif_type\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_req_ncomp_notif(\r
- HHUL_hca_hndl_t hca_hndl,\r
- HHUL_cq_hndl_t cq,\r
- VAPI_cqe_num_t cqe_num\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_destroy_cq_done(\r
- HHUL_hca_hndl_t hca_hndl,\r
- HHUL_cq_hndl_t cq\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_create_qp_prep(\r
- HHUL_hca_hndl_t hca_hndl,\r
- HHUL_qp_init_attr_t* qp_init_attr_p,\r
- HHUL_qp_hndl_t* qp_hndl_p,\r
- VAPI_qp_cap_t* qp_cap_out_p,\r
- void* qp_ul_resources_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_special_qp_prep(\r
- HHUL_hca_hndl_t hca_hndl,\r
- VAPI_special_qp_t qp_type,\r
- IB_port_t port,\r
- HHUL_qp_init_attr_t* qp_init_attr_p,\r
- HHUL_qp_hndl_t* qp_hndl_p,\r
- VAPI_qp_cap_t* qp_cap_out_p,\r
- void* qp_ul_resources_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_create_qp_done(\r
- HHUL_hca_hndl_t hca_hndl,\r
- HHUL_qp_hndl_t hhul_qp,\r
- IB_wqpn_t hh_qp,\r
- void* qp_ul_resources_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_post_send_req(\r
- HHUL_hca_hndl_t hca_hndl,\r
- HHUL_qp_hndl_t qp_hndl,\r
- VAPI_sr_desc_t* send_req_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_post_inline_send_req(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_qp_hndl_t qp_hndl,\r
- VAPI_sr_desc_t* send_req_p)\r
-{\r
- return HH_ENOSYS;\r
-}\r
- \r
-static HH_ret_t enosys_post_send_reqs(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_qp_hndl_t qp_hndl,\r
- u_int32_t num_of_requests,\r
- VAPI_sr_desc_t* send_req_array)\r
-{\r
- return HH_ENOSYS;\r
-}\r
- \r
-static HH_ret_t enosys_post_recv_req(\r
- HHUL_hca_hndl_t hca_hndl,\r
- HHUL_qp_hndl_t qp_hndl,\r
- VAPI_rr_desc_t* recv_req_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_post_recv_reqs(HHUL_hca_hndl_t hca_hndl,\r
- HHUL_qp_hndl_t qp_hndl,\r
- u_int32_t num_of_requests,\r
- VAPI_rr_desc_t* recv_req_array)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_destroy_qp_done(\r
- HHUL_hca_hndl_t hca_hndl,\r
- HHUL_qp_hndl_t qp_hndl\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-static HH_ret_t enosys_create_srq_prep( \r
- /*IN*/\r
- HHUL_hca_hndl_t hca, \r
- HHUL_pd_hndl_t pd,\r
- u_int32_t max_outs,\r
- u_int32_t max_sentries,\r
- /*OUT*/\r
- HHUL_srq_hndl_t *srq_hndl_p,\r
- u_int32_t *actual_max_outs_p,\r
- u_int32_t *actual_max_sentries_p,\r
- void /*THH_srq_ul_resources_t*/ *srq_ul_resources_p)\r
-{\r
- return HH_ENOSYS;\r
-}\r
- \r
-\r
-static HH_ret_t enosys_create_srq_done( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_srq_hndl_t hhul_srq, \r
- HH_srq_hndl_t hh_srq, \r
- void/*THH_srq_ul_resources_t*/ *srq_ul_resources_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-\r
-static HH_ret_t enosys_destroy_srq_done( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_qp_hndl_t hhul_srq \r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-\r
-static HH_ret_t enosys_post_srq(\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_srq_hndl_t hhul_srq, \r
- /*IN*/ u_int32_t num_of_requests,\r
- /*IN*/ VAPI_rr_desc_t *recv_req_array,\r
- /*OUT*/ u_int32_t *posted_requests_p\r
-)\r
-{\r
- return HH_ENOSYS;\r
-}\r
-\r
-\r
-static void enosys_init(HHUL_if_ops_t* p)\r
-{\r
- p->HHULIF_cleanup_user_level = &enosys_cleanup_user_level;\r
- p->HHULIF_alloc_pd_prep = &enosys_alloc_pd_prep;\r
- p->HHULIF_alloc_pd_done = &enosys_alloc_pd_done;\r
- p->HHULIF_free_pd_done = &enosys_free_pd_done;\r
- p->HHULIF_alloc_mw = &enosys_alloc_mw;\r
- p->HHULIF_bind_mw = &enosys_bind_mw;\r
- p->HHULIF_free_mw = &enosys_free_mw;\r
- p->HHULIF_create_ud_av = &enosys_create_ud_av;\r
- p->HHULIF_modify_ud_av = &enosys_modify_ud_av;\r
- p->HHULIF_query_ud_av = &enosys_query_ud_av;\r
- p->HHULIF_destroy_ud_av = &enosys_destroy_ud_av;\r
- p->HHULIF_create_cq_prep = &enosys_create_cq_prep;\r
- p->HHULIF_create_cq_done = &enosys_create_cq_done;\r
- p->HHULIF_resize_cq_prep = &enosys_resize_cq_prep;\r
- p->HHULIF_resize_cq_done = &enosys_resize_cq_done;\r
- p->HHULIF_poll4cqe = &enosys_poll4cqe;\r
- p->HHULIF_peek_cq = &enosys_peek_cq;\r
- p->HHULIF_req_comp_notif = &enosys_req_comp_notif;\r
- p->HHULIF_req_ncomp_notif = &enosys_req_ncomp_notif;\r
- p->HHULIF_destroy_cq_done = &enosys_destroy_cq_done;\r
- p->HHULIF_create_qp_prep = &enosys_create_qp_prep;\r
- p->HHULIF_special_qp_prep = &enosys_special_qp_prep;\r
- p->HHULIF_create_qp_done = &enosys_create_qp_done;\r
- p->HHULIF_post_send_req = &enosys_post_send_req;\r
- p->HHULIF_post_inline_send_req = &enosys_post_inline_send_req;\r
- p->HHULIF_post_send_reqs = &enosys_post_send_reqs;\r
- p->HHULIF_post_recv_req = &enosys_post_recv_req;\r
- p->HHULIF_post_recv_reqs = &enosys_post_recv_reqs;\r
- p->HHULIF_destroy_qp_done = &enosys_destroy_qp_done;\r
- p->HHULIF_create_srq_prep = &enosys_create_srq_prep; \r
- p->HHULIF_create_srq_done = &enosys_create_srq_done; \r
- p->HHULIF_destroy_srq_done = &enosys_destroy_srq_done; \r
- p->HHULIF_post_srq = &enosys_post_srq; \r
-} /* enosys_init */\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id:$\r
- */\r
-\r
-\r
-static HH_ret_t invalid_open_hca(\r
- HH_hca_hndl_t hca_hndl,\r
- EVAPI_hca_profile_t *profile_p,\r
- EVAPI_hca_profile_t *sugg_profile_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_close_hca(\r
- HH_hca_hndl_t hca_hndl\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_alloc_ul_resources(\r
- HH_hca_hndl_t hca_hndl,\r
- MOSAL_protection_ctx_t user_protection_context,\r
- void* hca_ul_resources_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_free_ul_resources(\r
- HH_hca_hndl_t hca_hndl,\r
- void* hca_ul_resources_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_query_hca(\r
- HH_hca_hndl_t hca_hndl,\r
- VAPI_hca_cap_t* hca_cap_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_modify_hca(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- VAPI_hca_attr_t* hca_attr_p,\r
- VAPI_hca_attr_mask_t* hca_attr_mask_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_query_port_prop(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- VAPI_hca_port_t* hca_port_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_get_pkey_tbl(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- u_int16_t tbl_len_in,\r
- u_int16_t* tbl_len_out,\r
- IB_pkey_t* pkey_tbl_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_get_gid_tbl(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- u_int16_t tbl_len_in,\r
- u_int16_t* tbl_len_out,\r
- IB_gid_t* pkey_tbl_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_get_lid(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port,\r
- IB_lid_t* lid_p,\r
- u_int8_t* lmc_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_alloc_pd(\r
- HH_hca_hndl_t hca_hndl, \r
- MOSAL_protection_ctx_t prot_ctx, \r
- void * pd_ul_resources_p, \r
- HH_pd_hndl_t *pd_num_p\r
-) \r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_free_pd(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_pd_hndl_t pd\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_alloc_rdd(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_rdd_hndl_t* rdd_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_free_rdd(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_rdd_hndl_t rdd\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_create_priv_ud_av(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_pd_hndl_t pd,\r
- VAPI_ud_av_t* av_p,\r
- HH_ud_av_hndl_t* ah_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_modify_priv_ud_av(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_ud_av_hndl_t ah,\r
- VAPI_ud_av_t* av_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_query_priv_ud_av(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_ud_av_hndl_t ah,\r
- VAPI_ud_av_t* av_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_destroy_priv_ud_av(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_ud_av_hndl_t ah\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_register_mr(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_mr_t* mr_props_p,\r
- VAPI_lkey_t* lkey_p,\r
- IB_rkey_t* rkey_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_reregister_mr(\r
- HH_hca_hndl_t hca_hndl,\r
- VAPI_lkey_t lkey,\r
- VAPI_mr_change_t change_mask,\r
- HH_mr_t* mr_props_p,\r
- VAPI_lkey_t* lkey_p,\r
- IB_rkey_t* rkey_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_register_smr(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_smr_t* smr_props_p,\r
- VAPI_lkey_t* lkey_p,\r
- IB_rkey_t* rkey_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_deregister_mr(\r
- HH_hca_hndl_t hca_hndl,\r
- VAPI_lkey_t lkey\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_query_mr(\r
- HH_hca_hndl_t hca_hndl,\r
- VAPI_lkey_t lkey,\r
- HH_mr_info_t* mr_info_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_alloc_mw(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_pd_hndl_t pd,\r
- IB_rkey_t* initial_rkey_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_free_mw(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_rkey_t initial_rkey\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_create_cq(\r
- HH_hca_hndl_t hca_hndl,\r
- MOSAL_protection_ctx_t user_protection_context,\r
- void* cq_ul_resources_p,\r
- HH_cq_hndl_t* cq\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_resize_cq(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_cq_hndl_t cq,\r
- void* cq_ul_resources_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_query_cq(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_cq_hndl_t cq,\r
- VAPI_cqe_num_t* num_o_cqes_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_destroy_cq(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_cq_hndl_t cq\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_create_qp(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_qp_init_attr_t* init_attr_p,\r
- void* qp_ul_resources_p,\r
- IB_wqpn_t* qpn_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_get_special_qp(\r
- HH_hca_hndl_t hca_hndl,\r
- VAPI_special_qp_t qp_type,\r
- IB_port_t port,\r
- HH_qp_init_attr_t* init_attr_p,\r
- void* qp_ul_resources_p,\r
- IB_wqpn_t* sqp_hndl_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_modify_qp(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_wqpn_t qp_num,\r
- VAPI_qp_state_t cur_qp_state,\r
- VAPI_qp_attr_t* qp_attr_p,\r
- VAPI_qp_attr_mask_t* qp_attr_mask_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_query_qp(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_wqpn_t qp_num,\r
- VAPI_qp_attr_t* qp_attr_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_destroy_qp(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_wqpn_t qp_num\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_create_eec(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_rdd_hndl_t rdd,\r
- IB_eecn_t* eecn_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_modify_eec(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_eecn_t eecn,\r
- VAPI_qp_state_t cur_ee_state,\r
- VAPI_qp_attr_t* ee_attr_p,\r
- VAPI_qp_attr_mask_t* ee_attr_mask_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_query_eec(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_eecn_t eecn,\r
- VAPI_qp_attr_t* ee_attr_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_destroy_eec(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_eecn_t eecn\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_set_async_eventh(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_async_eventh_t handler,\r
- void* private_data\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_set_comp_eventh(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_comp_eventh_t handler,\r
- void* private_data\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_attach_to_multicast(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_wqpn_t qpn,\r
- IB_gid_t dgid\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-static HH_ret_t invalid_detach_from_multicast(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_wqpn_t qpn,\r
- IB_gid_t dgid\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-\r
-static HH_ret_t invalid_process_local_mad(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- IB_lid_t slid,\r
- EVAPI_proc_mad_opt_t proc_mad_opts,\r
- void* mad_in_p,\r
- void* mad_out_p\r
-)\r
-{\r
- return HH_HCA_STATUS_INVALID;\r
-}\r
-\r
-\r
-static void invalid_init(HH_if_ops_t* p)\r
-{\r
- p->HHIF_open_hca = &invalid_open_hca;\r
- p->HHIF_close_hca = &invalid_close_hca;\r
- p->HHIF_alloc_ul_resources = &invalid_alloc_ul_resources;\r
- p->HHIF_free_ul_resources = &invalid_free_ul_resources;\r
- p->HHIF_query_hca = &invalid_query_hca;\r
- p->HHIF_modify_hca = &invalid_modify_hca;\r
- p->HHIF_query_port_prop = &invalid_query_port_prop;\r
- p->HHIF_get_pkey_tbl = &invalid_get_pkey_tbl;\r
- p->HHIF_get_gid_tbl = &invalid_get_gid_tbl;\r
- p->HHIF_get_lid = &invalid_get_lid;\r
- p->HHIF_alloc_pd = &invalid_alloc_pd;\r
- p->HHIF_free_pd = &invalid_free_pd;\r
- p->HHIF_alloc_rdd = &invalid_alloc_rdd;\r
- p->HHIF_free_rdd = &invalid_free_rdd;\r
- p->HHIF_create_priv_ud_av = &invalid_create_priv_ud_av;\r
- p->HHIF_modify_priv_ud_av = &invalid_modify_priv_ud_av;\r
- p->HHIF_query_priv_ud_av = &invalid_query_priv_ud_av;\r
- p->HHIF_destroy_priv_ud_av = &invalid_destroy_priv_ud_av;\r
- p->HHIF_register_mr = &invalid_register_mr;\r
- p->HHIF_reregister_mr = &invalid_reregister_mr;\r
- p->HHIF_register_smr = &invalid_register_smr;\r
- p->HHIF_deregister_mr = &invalid_deregister_mr;\r
- p->HHIF_query_mr = &invalid_query_mr;\r
- p->HHIF_alloc_mw = &invalid_alloc_mw;\r
- p->HHIF_free_mw = &invalid_free_mw;\r
- p->HHIF_create_cq = &invalid_create_cq;\r
- p->HHIF_resize_cq = &invalid_resize_cq;\r
- p->HHIF_query_cq = &invalid_query_cq;\r
- p->HHIF_destroy_cq = &invalid_destroy_cq;\r
- p->HHIF_create_qp = &invalid_create_qp;\r
- p->HHIF_get_special_qp = &invalid_get_special_qp;\r
- p->HHIF_modify_qp = &invalid_modify_qp;\r
- p->HHIF_query_qp = &invalid_query_qp;\r
- p->HHIF_destroy_qp = &invalid_destroy_qp;\r
- p->HHIF_create_eec = &invalid_create_eec;\r
- p->HHIF_modify_eec = &invalid_modify_eec;\r
- p->HHIF_query_eec = &invalid_query_eec;\r
- p->HHIF_destroy_eec = &invalid_destroy_eec;\r
- p->HHIF_set_async_eventh = &invalid_set_async_eventh;\r
- p->HHIF_set_comp_eventh = &invalid_set_comp_eventh;\r
- p->HHIF_attach_to_multicast = &invalid_attach_to_multicast;\r
- p->HHIF_detach_from_multicast = &invalid_detach_from_multicast;\r
- p->HHIF_process_local_mad = &invalid_process_local_mad;\r
-} /* invalid_init */\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
- }; \r
- u_int16_t payload_size = 16; /*In bytes this must be the same as the buf size*/\r
-\r
- /* init parameters the rest will be updated by the build function */\r
-\r
- /* LRH */\r
- lrh_st.VL = 0x7;\r
- lrh_st.LVer = 0;\r
- lrh_st.SL = RC_SL;\r
- lrh_st.DLID = RC_SLID;\r
- lrh_st.SLID = RC_DLID; \r
-\r
- /* BTH */\r
- bth_st.SE = 0;\r
- bth_st.M = 0;\r
- bth_st.TVer = 0;\r
- bth_st.P_KEY = RC_PKEY;\r
- bth_st.DestQP= RC_SRC_QP_NUM;\r
- bth_st.A = 0;\r
- bth_st.PSN = RC_RQ_START_PSN; \r
-\r
- /* DETH */\r
- deth_st.Q_Key = 0x11111111;\r
- deth_st.reserved1 = 0x88;\r
- deth_st.SrcQP = 0x222222; \r
-\r
- /* AETH */\r
- aeth_st.Syndrome = 0xFF; /* 8 bit field */\r
- aeth_st.MSN = 0xFFFFFF; /* 24 bit field */\r
-\r
-\r
- opcode = RC_SEND_FIRST_OP; /* RC_ACKNOWLEDGE_OP; one of the cases */\r
-\r
- LNH = IBA_LOCAL; /* only IBA is supported in the lib so don't change it*/\r
-/***********************************************/ \r
- for (num_pkt = 1; num_pkt <= NUM_PKT + 1 ; num_pkt++) {\r
-\r
- switch (opcode) {\r
- \r
- case RC_SEND_FIRST_OP:\r
- ret = MPGA_fast_rc_send_first(&lrh_st, grh_st_p, &bth_st, LNH, \r
- payload_size, &header_size, &header_buf_p);\r
- CHECK_RESULT(ret); \r
- break; \r
- case RC_SEND_MIDDLE_OP:\r
- ret = MPGA_fast_rc_send_middle(&lrh_st, grh_st_p, &bth_st, LNH, \r
- payload_size, &header_size, &header_buf_p);\r
- CHECK_RESULT(ret);\r
- break;\r
- case RC_SEND_LAST_OP: \r
- bth_st.A = 1;\r
- ret = MPGA_fast_rc_send_last(&lrh_st, grh_st_p, &bth_st, LNH, \r
- payload_size, &header_size, &header_buf_p);\r
- CHECK_RESULT(ret);\r
- break;\r
- case RC_SEND_LAST_W_IM_OP: \r
- return(HH_ENOSYS); break;\r
- case RC_SEND_ONLY_OP:\r
- bth_st.A = 1; \r
- ret = MPGA_fast_rc_send_only(&lrh_st, grh_st_p, &bth_st, LNH, \r
- payload_size, &header_size, &header_buf_p);\r
- CHECK_RESULT(ret);\r
- break;\r
- case RC_ACKNOWLEDGE_OP: \r
- ret = MPGA_fast_rc_acknowledge(&lrh_st, grh_st_p, &bth_st, &aeth_st, \r
- LNH, &header_size, &header_buf_p);\r
- CHECK_RESULT(ret);\r
- break;\r
-\r
- case UD_SEND_ONLY_OP:\r
- ret=MPGA_fast_ud_send_only(&lrh_st, &bth_st, &deth_st, payload_size, \r
- &header_size, &header_buf_p);\r
- CHECK_RESULT(ret); \r
- break; \r
-\r
- default:\r
- printf("\n*** ERROR dont have such case %d ***\n",opcode);\r
- return(HH_ERR);\r
- break;\r
- }\r
- /*End of the buid part update for the next packet if needed*/\r
-\r
- bth_st.PSN++; \r
- if (opcode == RC_SEND_FIRST_OP) opcode = RC_SEND_MIDDLE_OP;\r
- else if (num_pkt == (NUM_PKT - 1)) opcode = RC_SEND_LAST_OP;\r
- else opcode = RC_SEND_ONLY_OP;\r
-\r
- /***********************************************************/\r
-\r
- MPGA_print_pkt((u_int8_t*)header_buf_p,header_size - 4);\r
-\r
-/***********************************************/\r
-\r
- /* Packet for analyzer sim the packet from eyals buffer*/\r
-\r
- packet_p = (u_int8_t*) malloc(sizeof(u_int8_t) * (header_size + payload_size + 4));\r
- memset(packet_p , 0, (header_size + payload_size + 4));\r
- memcpy((u_int8_t*)packet_p + 4, header_buf_p, header_size);\r
- memcpy(((u_int8_t*)packet_p + header_size + 4), payload_buf_p, payload_size);\r
-/***********************************************/\r
-\r
- GHGA_analyze((GHH_dev_t*)dev->device, packet_p, &packet_size);\r
-\r
-\r
-\r
- MPGA_print_pkt((u_int8_t*)packet_p,(header_size + payload_size + 4)); /* Printing the wanted header/Packet*/\r
-\r
-\r
- free(header_buf_p);\r
- free(packet_p); \r
- }\r
- return EXIT_SUCCESS;\r
-}\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_CMD_TYPES_H\r
-#define H_CMD_TYPES_H\r
-\r
-#include <mtl_types.h>\r
-#include <tavor_if_defs.h>\r
-#include <thh.h>\r
-\r
-\r
-typedef MT_size_t THH_mpt_index_t; /* ?? */\r
-typedef u_int16_t THH_mcg_hash_t; /* !!! to be defined in THH_mcgm !!! */\r
-\r
-/* matan: SQD event req is passed to HCA on opcode modifier field.\r
- however, THH_cmd_MODIFY_QPEE() has no input argument selecting \r
- sqd_event = 0/1. in order not to change the existing API, we define \r
- the flag below & mask it off on entry of THH_cmd_MODIFY_QPEE(). if \r
- (cmd == RTS2SQD) its value is used as sqd_event parameter.*/\r
-#define THH_CMD_SQD_EVENT_REQ 0x80000000\r
-\r
-/* QP/EE transitions */\r
-enum {\r
- QPEE_TRANS_RST2INIT = TAVOR_IF_CMD_RST2INIT_QPEE,\r
- QPEE_TRANS_INIT2INIT = TAVOR_IF_CMD_INIT2INIT_QPEE,\r
- QPEE_TRANS_INIT2RTR = TAVOR_IF_CMD_INIT2RTR_QPEE,\r
- QPEE_TRANS_RTR2RTS = TAVOR_IF_CMD_RTR2RTS_QPEE,\r
- QPEE_TRANS_RTS2RTS = TAVOR_IF_CMD_RTS2RTS_QPEE,\r
- QPEE_TRANS_SQERR2RTS = TAVOR_IF_CMD_SQERR2RTS_QPEE,\r
- QPEE_TRANS_2ERR = TAVOR_IF_CMD_2ERR_QPEE,\r
- QPEE_TRANS_RTS2SQD = TAVOR_IF_CMD_RTS2SQD_QPEE,\r
- QPEE_TRANS_RTS2SQD_WITH_EVENT = TAVOR_IF_CMD_RTS2SQD_QPEE | THH_CMD_SQD_EVENT_REQ,\r
- QPEE_TRANS_SQD2RTS = TAVOR_IF_CMD_SQD2RTS_QPEE,\r
- QPEE_TRANS_ERR2RST = TAVOR_IF_CMD_ERR2RST_QPEE\r
-};\r
-\r
-typedef u_int32_t THH_qpee_transition_t;\r
-\r
-\r
-enum {\r
- THH_CMD_STAT_OK = TAVOR_IF_CMD_STAT_OK, /* command completed successfully */\r
- THH_CMD_STAT_INTERNAL_ERR = TAVOR_IF_CMD_STAT_INTERNAL_ERR, /* Internal error (such as a bus error) occurred while processing command */\r
- THH_CMD_STAT_BAD_OP = TAVOR_IF_CMD_STAT_BAD_OP, /* Operation/command not supported or opcode modifier not supported */\r
- THH_CMD_STAT_BAD_PARAM = TAVOR_IF_CMD_STAT_BAD_PARAM, /* Parameter not supported or parameter out of range */\r
- THH_CMD_STAT_BAD_SYS_STATE = TAVOR_IF_CMD_STAT_BAD_SYS_STATE, /* System not enabled or bad system state */\r
- THH_CMD_STAT_BAD_RESOURCE = TAVOR_IF_CMD_STAT_BAD_RESOURCE, /* Attempt to access reserved or unallocaterd resource */\r
- THH_CMD_STAT_RESOURCE_BUSY = TAVOR_IF_CMD_STAT_RESOURCE_BUSY, /* Requested resource is currently executing a command, or is otherwise busy */\r
- THH_CMD_STAT_DDR_MEM_ERR = TAVOR_IF_CMD_STAT_DDR_MEM_ERR, /* memory error */\r
- THH_CMD_STAT_EXCEED_LIM = TAVOR_IF_CMD_STAT_EXCEED_LIM, /* Required capability exceeds device limits */\r
- THH_CMD_STAT_BAD_RES_STATE = TAVOR_IF_CMD_STAT_BAD_RES_STATE, /* Resource is not in the appropriate state or ownership */\r
- THH_CMD_STAT_BAD_INDEX = TAVOR_IF_CMD_STAT_BAD_INDEX, /* Index out of range */\r
- THH_CMD_STAT_BAD_QPEE_STATE = TAVOR_IF_CMD_STAT_BAD_QPEE_STATE, /* Attempt to modify a QP/EE which is not in the presumed state */\r
- THH_CMD_STAT_BAD_SEG_PARAM = TAVOR_IF_CMD_STAT_BAD_SEG_PARAM, /* Bad segment parameters (Address/Size) */\r
- THH_CMD_STAT_REG_BOUND = TAVOR_IF_CMD_STAT_REG_BOUND, /* Memory Region has Memory Windows bound to */\r
- THH_CMD_STAT_BAD_PKT = TAVOR_IF_CMD_STAT_BAD_PKT, /* Bad management packet (silently discarded) */\r
- THH_CMD_STAT_BAD_SIZE = TAVOR_IF_CMD_STAT_BAD_SIZE, /* More outstanding CQEs in CQ than new CQ size */\r
-\r
- /* driver added statuses */\r
- THH_CMD_STAT_EAGAIN = 0x0100, /* No (software) resources to enqueue given command - retry later*/\r
- THH_CMD_STAT_EABORT = 0x0101, /* Command aborted (due to change in cmdif state) */\r
- THH_CMD_STAT_ETIMEOUT = 0X0102, /* command not completed after timeout */\r
- THH_CMD_STAT_EFATAL = 0x0103, /* unexpected error - fatal */\r
- THH_CMD_STAT_EBADARG = 0x0104, /* bad argument */\r
- THH_CMD_STAT_EINTR = 0X0105 /* process received signal */\r
-};\r
-\r
-typedef u_int32_t THH_cmd_status_t;\r
-\r
-\r
-#define THH_CMD_STAT_OK_STR "TAVOR_IF_CMD_STAT_OK - command completed successfully"\r
-#define THH_CMD_STAT_INTERNAL_ERR_STR "TAVOR_IF_CMD_STAT_INTERNAL_ERR = Internal error (such as a bus error) occurred while processing command"\r
-#define THH_CMD_STAT_BAD_OP_STR "TAVOR_IF_CMD_STAT_BAD_OP - Operation/command not supported or opcode modifier not supported"\r
-#define THH_CMD_STAT_BAD_PARAM_STR "TAVOR_IF_CMD_STAT_BAD_PARAM - Parameter not supported or parameter out of range"\r
-#define THH_CMD_STAT_BAD_SYS_STATE_STR "TAVOR_IF_CMD_STAT_BAD_SYS_STATE - System not enabled or bad system state"\r
-#define THH_CMD_STAT_BAD_RESOURCE_STR "TAVOR_IF_CMD_STAT_BAD_RESOURCE - Attempt to access reserved or unallocaterd resource"\r
-#define THH_CMD_STAT_RESOURCE_BUSY_STR "TAVOR_IF_CMD_STAT_RESOURCE_BUSY - Requested resource is currently executing a command, or is otherwise busy"\r
-#define THH_CMD_STAT_DDR_MEM_ERR_STR "TAVOR_IF_CMD_STAT_DDR_MEM_ERR - memory error"\r
-#define THH_CMD_STAT_EXCEED_LIM_STR "TAVOR_IF_CMD_STAT_EXCEED_LIM - Required capability exceeds device limits"\r
-#define THH_CMD_STAT_BAD_RES_STATE_STR "TAVOR_IF_CMD_STAT_BAD_RES_STATE - Resource is not in the appropriate state or ownership"\r
-#define THH_CMD_STAT_BAD_INDEX_STR "TAVOR_IF_CMD_STAT_BAD_INDEX - Index out of range"\r
-#define THH_CMD_STAT_BAD_QPEE_STATE_STR "TAVOR_IF_CMD_STAT_BAD_QPEE_STATE - Attempt to modify a QP/EE which is not in the presumed state"\r
-#define THH_CMD_STAT_BAD_SEG_PARAM_STR "TAVOR_IF_CMD_STAT_BAD_SEG_PARAM - Bad segment parameters (Address/Size)"\r
-#define THH_CMD_STAT_REG_BOUND_STR "TAVOR_IF_CMD_STAT_REG_BOUND - Memory Region has Memory Windows bound to"\r
-#define THH_CMD_STAT_BAD_PKT_STR "TAVOR_IF_CMD_STAT_BAD_PKT - Bad management packet (silently discarded)"\r
-#define THH_CMD_STAT_BAD_SIZE_STR "THH_CMD_STAT_BAD_SIZE - More outstanding CQEs in CQ than new CQ size"\r
-#define THH_CMD_STAT_EAGAIN_STR "0x0100 - No (software) resources to enqueue given command - retry later"\r
-#define THH_CMD_STAT_EABORT_STR "0x0101 - Command aborted (due to change in cmdif state)"\r
-#define THH_CMD_STAT_ETIMEOUT_STR "0X0102 - command not completed after timeout"\r
-#define THH_CMD_STAT_EFATAL_STR "0x0103 - unexpected error - fatal"\r
-#define THH_CMD_STAT_EBADARG_STR "0x0104 - bad argument"\r
-#define THH_CMD_STAT_EINTR_STR "0x0105 - process received signal"\r
-\r
-\r
-enum {\r
- DDR_STAT_OK = 0,\r
- DDR_STAT_CAL_1_ERR = 1,\r
- DDR_STAT_CAL_2_ERR = 2\r
-};\r
-typedef u_int32_t THH_ddr_cal_status_t;\r
-\r
-enum {\r
- DIM_DI_NONE = 0,\r
- DIM_DI_PARITY = 1,\r
- DIM_DI_ECC = 2\r
-};\r
-typedef u_int32_t THH_dim_integrity_t;\r
-\r
-enum {\r
- DDR_NO_AUTO=0,\r
- DDR_AUTO_PRECHARGE_PER_TRANSLATION=1,\r
- DDR_AUTO_PRECHARGE_PER_64BIT=2\r
-};\r
-typedef u_int32_t THH_dim_apm_t;\r
-\r
-enum {\r
- DIM_STAT_ENABLED = 0,\r
- DIM_STAT_DISABLED = 1\r
-};\r
-typedef u_int32_t THH_dim_status_t;\r
-\r
-typedef struct THH_dim_info_t {\r
- u_int32_t dimmsize; /* Size of DIMM in units of 2^20 Bytes. */\r
- /* This value is valid only when DIMMStatus is DIM_STAT_OPERATIONAL. */\r
- THH_dim_integrity_t di; /* Data Integrity Configuration */\r
- u_int8_t dimmslot; /* Slot number in which the Logical DIMM is located. */\r
- /*;Two logical DIMMs may be on same module and therefore on same slot.\;This value is only valid when DIMMStatus is not 1. */\r
- THH_dim_status_t dimmstatus; /* When it is 1-255 the Logical DIMM in question is disabled*/\r
- /* 0 - DIMM is Operational \;1 - No DIMM detected */\r
- /* 2 - DIMM max freq is smaller than DMU freq\;3- DIMM min freq is greater than DMU freq\;4 - DIMM CAS Latency does not match the other DIMMs\;5 - DIMM CAS Latency is not supported.\;6 - DIMM chip width does not match the other DIMMs. (x4/x8/x16)\;6 - DIMM chip width is not supported\;7 - DIMM buffered/unbuffered does not match the other DIMMs\;8 - DIMM does not support 8 byte bursts\;9 - DIMM does not have 4 banks\;10 - 255 Other DIMM Errors */\r
- u_int64_t vendor_id; /* JDEC Manufacturer ID (64 bits) */\r
-}\r
-THH_dim_info_t;\r
-\r
-\r
-enum {\r
- THH_OWNER_SW = 0,\r
- THH_OWNER_HW = 1\r
-};\r
-typedef u_int32_t THH_owner_t;\r
-\r
-typedef struct {\r
- u_int64_t qpc_base_addr; /* QPC Base Address. Table must be aligned on its size */\r
- u_int8_t log_num_of_qp; /* Log base 2 of number of supported QPs */\r
- u_int64_t eec_base_addr; /* EEC Base Address. Table must be aligned on its size */\r
- u_int64_t srqc_base_addr; /* SRQC Base Address. Table must be aligned on its size */\r
- u_int8_t log_num_of_srq; /* Log base 2 of number of supported SRQs */\r
- u_int8_t log_num_of_ee; /* Log base 2 of number of supported EEs. */\r
- u_int64_t cqc_base_addr; /* CQC Base Address. Table must be aligned on its size */\r
- u_int8_t log_num_of_cq; /* Log base 2 of number of supported CQs. */\r
- u_int64_t eqpc_base_addr; /* Extended QPC Base Address. Table has same number of entries as QPC table. Table must be aligned to entry size. */\r
- u_int64_t eeec_base_addr; /* Extended EEC Base Address. Table has same number of entries as EEC table. Table must be aligned to entry size. */\r
- u_int64_t eqc_base_addr; /* EQC Base Address. */\r
- u_int8_t log_num_eq; /* Log base 2 of number of supported EQs. Must be 6 in MT23108 */\r
- u_int64_t rdb_base_addr; /* Base address of table that holds remote read and remote atomic requests. Table must be aligned to RDB entry size (32 bytes). Table size is implicitly defined when QPs/EEs are configured with indexes into this table. */\r
-}\r
-THH_contexts_prms_t;\r
-\r
-typedef struct { /* Protected UD-AV table parameters */\r
- u_int32_t l_key; /* L_Key used to access TPT */\r
- u_int32_t pd; /* PD used by TPT for matching against PD of region entry being accessed. */\r
- MT_bool xlation_en; /* When cleared, address is physical address and no translation will be done. When set, address is virtual. TPT will be accessed in both cases for address decoding purposes. */\r
-}\r
-THH_ud_av_tbl_prms_t;\r
-\r
-typedef struct {\r
- u_int64_t mc_base_addr; /* Base Address of the Multicast Table. The base address must be aligned to the entry size. */\r
- u_int16_t log_mc_table_entry_sz; /* Log2 of the Size of multicast group member (MGM) entry. Must be greater than 5 (to allow CTRL and GID sections). That implies the number of QPs per MC table entry. */\r
- u_int32_t mc_table_hash_sz; /* Number of entries in multicast DGID hash table (must be power of 2).\r
- INIT_HCA - the required number of entries\r
- QUERY_HCA - the actual number of entries assigned by firmware (will be less than or equal to the amount required in INIT_HCA) */\r
- u_int8_t log_mc_table_sz; /* Log2 of the overall number of MC entries in the MCG table (includes both hash and auxiliary tables) */\r
- u_int8_t mc_hash_fn; /* Multicast hash function\;0 - Default hash function\;other - reserved */\r
-}\r
-THH_mcast_prms_t;\r
-\r
-typedef struct {\r
- u_int64_t mpt_base_adr; /* MPT - Memory Protection Table base physical address. Entry size is 64 bytes. Table must be aligned to its size. */\r
- u_int8_t log_mpt_sz; /* Log (base 2) of the number of region/windows entries in the MPT table. */\r
- u_int8_t pfto; /* Page Fault RNR Timeout - The field returned in RNR Naks generated when a page fault is detected. It has no effect when on-demand-paging is not used. */\r
- u_int8_t mtt_version; /* Version of MTT page walk. Must be zero */\r
- u_int64_t mtt_base_addr; /* MTT - Memory Translation table base physical address. Table must be aligned to its size. */\r
- u_int8_t mtt_segment_size; /* The size of MTT segment is 64*2^MTT_Segment_Size bytes */\r
-}\r
-THH_tpt_prms_t;\r
-\r
-typedef struct {\r
- u_int64_t uar_base_addr; /* UAR Base Address (QUERY_HCA only) */\r
- u_int8_t uar_page_sz; /* This field defines the size of each UAR page. Size of UAR Page is 4KB*2^UAR_Page_Size */\r
- u_int64_t uar_scratch_base_addr; /* Base address of UAR scratchpad. Number of entries in table is UAR BAR size divided by UAR Page Size. Table must be aligned to entry size. */\r
-}\r
-THH_uar_prms_t;\r
-\r
-typedef struct {\r
- u_int32_t tbd; /* To Be Defined */\r
-}\r
-THH_sched_arb_t;\r
-\r
-typedef struct {\r
- u_int8_t hca_core_clock; /* Internal Clock Period (in units of 1/16 ns) (QUERY_HCA only) */\r
- u_int16_t router_qp; /* Upper 16 bit to be used as a QP number for router mode. Low order 8 bits are taken from the TClass field of the incoming packet.\;Valid only if RE bit is set */\r
- MT_bool re; /* Router Mode Enable\;If this bit is set, entire packet (including all headers and ICRC) will be considered as a data payload and will be scattered to memory as specified in the descriptor that is posted on the QP matching the TClass field of packet. */\r
- MT_bool udp; /* UD Port Check Enable\;0 - Port field in Address Vector is ignored\;1 - HCA will check the port field in AV entry (fetched for UD descriptor) against the Port of the UD QP executing the descriptor. */\r
- MT_bool he; /* host is big endian - Used for Atomic Operations */\r
- MT_bool ud; /* enable UD address vector protection (privileged UDAVs). 0 = disabled; 1 = enabled */\r
- THH_contexts_prms_t qpc_eec_cqc_eqc_rdb_parameters;\r
- THH_ud_av_tbl_prms_t udavtable_memory_parameters; /* Memory Access Parameters for UD Address Vector\r
-Table. Used for QPs/EEc that are configured to use protected Address Vectors. */\r
- THH_mcast_prms_t multicast_parameters;\r
- THH_tpt_prms_t tpt_parameters;\r
- THH_uar_prms_t uar_parameters; /* UAR Parameters */\r
-}\r
-THH_hca_props_t;\r
-\r
-\r
-enum {\r
- EQ_STATE_RSRV1 = 0,\r
- EQ_STATE_ARMED = 1,\r
- EQ_STATE_ALWAYS_ARMED = 2,\r
- EQ_STATE_FIRED = 3\r
-};\r
-typedef u_int32_t THH_eq_state_t;\r
-\r
-enum {\r
- EQ_STATUS_OK = 0,\r
- EQ_STATUS_OVERFLOW = 9,\r
- EQ_STATUS_WRITE_FAILURE = 10\r
-};\r
-typedef u_int32_t THH_eq_status_t;\r
-\r
-typedef struct {\r
- THH_eq_state_t st; /* Event delivery state machine\;01 - Armed\;11 - Fired\;10,00 - Reserved */\r
- MT_bool oi; /* Overrun detection ignore */\r
- MT_bool tr; /* Translation Required. If set - EQ access undergo address translation. */\r
- THH_owner_t owner; /* SW/HW ownership */\r
- THH_eq_status_t status; /* EQ status:\;0000 - OK\;1001 - EQ overflow\;1010 - EQ write failure */\r
- u_int64_t start_address; /* Start Address of Event Queue. Must be aligned on 32-byte boundary */\r
- u_int32_t usr_page;\r
- u_int8_t log_eq_size; /* Log2 of the amount of entries in the EQ */\r
- u_int8_t intr; /* Interupt (message) to be generated to report event to INT layer.\;0000iiii - specifies GPIO pin to be asserted\;1jjjjjjj - specificies type of interrupt message to be generated (total 128 different messages supported). */\r
- u_int32_t lost_count; /* Number of events lost due to EQ overrun */\r
- u_int32_t lkey; /* Memory key (L-Key) to be used to access EQ */\r
- u_int32_t pd; /* Protection Domain */\r
- u_int32_t consumer_indx; /* Contains next entry to be read upon poll for completion. Must be initalized to '0 while opening EQ */\r
- u_int32_t producer_indx; /* Contains next entry in EQ to be written by the HCA. Must be initialized to '1 while opening EQ. */\r
-}\r
-THH_eqc_t;\r
-\r
-enum {\r
- CQ_STATE_DISARMED = 0x0,\r
- CQ_STATE_ARMED = 0x1,\r
- CQ_STATE_ARMED_SOLICITED = 0x4,\r
- CQ_STATE_FIRED = 0xA\r
-};\r
-typedef u_int32_t THH_cq_state_t;\r
-\r
-enum {\r
- CQ_STATUS_OK = 0,\r
- CQ_STATUS_OVERFLOW = 9,\r
- CQ_STATUS_WRITE_FAILURE = 10\r
-};\r
-typedef u_int32_t THH_cq_status_t;\r
-\r
-typedef struct {\r
- THH_cq_state_t st; /* Event delivery state machine (Regular Events)\;0 - Disarmed\;1 - Armed\;Armed_Solicited=4\;0xA - Fired\;other - Reserved */\r
- MT_bool oi; /* Ignore overrun of this CQ if this bit is set */\r
- MT_bool tr; /* Translation Required - if set, accesses to CQ will undergo address translation. */\r
- THH_cq_status_t status; /* CQ status\;0000 - OK\;1001 - CQ overflow\;1010 - CQ write failure */\r
- u_int64_t start_address; /* Start address of CQ. Must be aligned on CQE size (32 bytes) */\r
- u_int32_t usr_page; /* UAR page this CQ can be accessed through (ringinig CQ doorbells) */\r
- u_int8_t log_cq_size; /* amount of entries in CQ 2^Log_CQ_size */\r
- THH_eqn_t e_eqn; /* Event Queue this CQ reports errors to (e.g. CQ overflow) */\r
- THH_eqn_t c_eqn; /* Event Queue this CQ reports completion events to */\r
- u_int32_t pd; /* Protection Domain */\r
- u_int32_t l_key; /* Memory key (L_Key) to be used to access CQ */\r
- u_int32_t last_notified_indx; /* Maintained by HW, not to be altered by SW */\r
- u_int32_t solicit_producer_indx; /* Maintained by HW, not to be altered by SW. points to last CQE reported for message with S-bit set */\r
- u_int32_t consumer_indx; /* Contains index to the next entry to be read upon poll for completion. The first completion after passing ownership of CQ from software to hardware will be reported to value passed in this field. */\r
- u_int32_t producer_indx; /* Maintained by HW, not to be altered by SW. Points to the next entry to be written to by Hardware. CQ overrun is reported if Producer_indx + 1 equals to Consumer_indx. */\r
- u_int32_t cqn; /* CQ number. Least significant bits are constrained by the position of this CQ in CQC table */\r
-}\r
-THH_cqc_t;\r
-\r
-enum {\r
- PM_STATE_ARMED = 0,\r
- PM_STATE_REARM = 1,\r
- PM_STATE_MIGRATED = 3\r
-};\r
-typedef u_int32_t THH_pm_state_t;\r
-\r
-enum {\r
- THH_ST_RC = 0,\r
- THH_ST_UC = 1,\r
- THH_ST_RD = 2,\r
- THH_ST_UD = 3,\r
- THH_ST_MLX = 7\r
-};\r
-typedef u_int32_t THH_service_type_t;\r
-\r
-typedef struct {\r
- u_int8_t pkey_index; /* PKey table index */\r
- IB_port_t port_number; /* Specific port associated with this QP/EE.\;0 - Port 1\;1 - Port 2 */\r
- IB_lid_t rlid; /* Remte (Destination) LID */\r
- u_int8_t my_lid_path_bits; /* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */\r
- MT_bool g; /* Global address enable - if set, GRH will be formed for packet header */\r
- u_int8_t rnr_retry; /* RNR retry count */\r
- u_int8_t hop_limit; /* IPv6 hop limit */\r
- u_int8_t max_stat_rate; /* Maximum static rate control. \;0 - 4X injection rate\;1 - 1X injection rate\;other - reserved\; */\r
- /* removed - u_int8_t MSG;*/ /* Message size (valid for UD AV only), size is 256*2^MSG bytes */\r
- u_int8_t mgid_index; /* Index to port GID table */\r
- u_int8_t ack_timeout; /* Locak ACK timeout */\r
- u_int32_t flow_label; /* IPv6 flow label */\r
- u_int8_t tclass; /* IPv6 TClass */\r
- IB_sl_t sl; /* InfiniBand Service Level (SL) */\r
- IB_gid_t rgid; /* Remote GID */\r
-}\r
-THH_address_path_t;\r
-\r
-typedef struct {\r
- u_int8_t ver; /* Version of QPC format. Must be zero for MT23108 */\r
- /* MT_bool te; */ /* Address translation enable. If cleared - no address translation will be performed for all memory accesses (data buffers and descriptors) associated with this QP. Present in all transports, invalid (reserved) in EE comnext */\r
- /* u_int8_t ce; Cache Mode. Must be set to '1 for proper HCA operation */\r
- MT_bool de; /* Send/Receive Descriptor Event enable - if set, events can be generated upon descriptors' completion on send/receive queue (controlled by E bit in WQE). Invalid in EE context */\r
- THH_pm_state_t pm_state; /* Path migration state (Migrated, Armed or Rearm)\;11-Migrated\;00-Armed\;01-Rearm */\r
- THH_service_type_t st; /* Service type (invalid in EE context):\;000-Reliable Connection\;001-Unreliable Connection\;010-Reliable Datagram\;011-Unreliable Datagram\;111-MLX transport (raw bits injection). Used fro management QPs and RAW */\r
- VAPI_qp_state_t state; /* For QUERY_QPEE */\r
- MT_bool sq_draining; /* query only - when (qp_state == VAPI_SQD) indicates whether sq is in drain process (TRUE), or drained.*/\r
- u_int8_t sched_queue; /* Schedule queue to be used for WQE scheduling to execution. Detrmines QOS for this QP. */\r
- u_int8_t msg_max; /* Max message size allowed on the QP. Maximum message size is two in the power of 2^msg_Max */\r
- IB_mtu_t mtu; /* MTU of the QP. Must be the same for both paths (primery and laternative). Encoding is per IB spec. Not valid (reserved) in EE context */\r
- u_int32_t usr_page; /* Index (offset) of user page allocated for this QP (see "non_privileged Access to the HCA Hardware"). Not valid (reserved) in EE context. */\r
- u_int32_t local_qpn_een; /* Local QO number Lower bits determine position of this record in QPC table, and - thus - constrained */\r
- u_int32_t remote_qpn_een; /* Remote QP/EE number */\r
- THH_address_path_t primary_address_path; /* see Table 6, "Address path format" on page 27. */\r
- THH_address_path_t alternative_address_path; /* see Table 6, "Address Path Format, on page 27 */\r
- u_int32_t rdd; /* Reliable Datagram Domain */\r
- u_int32_t pd; /* QP protection domain. Not valid (reserved) in EE context. */\r
- u_int32_t wqe_base_adr; /* Bits 63:32 of WQE address for both SQ and RQ. \;Reserved for EE context. */\r
- u_int32_t wqe_lkey; /* memory key (L-Key) to be used to access WQEs. Not valid (reserved) in EE context. */\r
- MT_bool ssc; /* If set - all send WQEs generate CQEs. If celared - only send WQEs with C bit set generate completion. Not valid (reserved) in EE context. */\r
- MT_bool sic; /* If zero - Ignore end to end credits on send queue. Not valid (reserved) in EE context. */\r
- MT_bool sae; /* If set - Atomic operations enabled on send queue. Not valid (reserved) in EE context. */\r
- MT_bool swe; /* If set - RDMA - write enabled on send queue. Not valid (reserved) in EE context. */\r
- MT_bool sre; /* If set - RDMA - read enabled on send queue. Not valid (reserved) in EE context. */\r
- u_int8_t retry_count; /* Maximum retry count */\r
- u_int8_t sra_max; /* Maximum number of outstanding RDMA-read/Atomic operations allowed in the send queue. Maximum number is 2^SRA_Max. Not valid (reserved) in EE context. */\r
- u_int8_t flight_lim; /* Number of outstanding (in-flight) messages on the wire allowed for this send queue. \;Number of outstanding messages is 2^Flight_Lim. \;Must be 0 for EE context. */\r
- u_int8_t ack_req_freq; /* ACK required frequency. ACK required bit will be set in every 2^AckReqFreq packets at least. Not valid (reserved) in EE context. */\r
- u_int32_t next_send_psn; /* Next PSN to be sent */\r
- u_int32_t cqn_snd; /* CQ number completions from this queue to be reported to. Not valid (reserved) in EE context. */\r
- u_int64_t next_snd_wqe; /* Pointer and properties of next WQE on send queue. The format is same as next segment (first 8 bytes) in the WQE. Not valid (reserved) in EE context. */\r
- MT_bool rsc; /* If set - all receive WQEs generate CQEs. If celared - only receive WQEs with C bit set generate completion. Not valid (reserved) in EE context. */\r
- MT_bool ric; /* Invalid Credits. If this bit is set, place "Invalid Credits" to ACKs sent from this queue. Not valid (reserved) in EE context. */\r
- MT_bool rae; /* If set - Atomic operations enabled. on receive queue. Not valid (reserved) in EE context. */\r
- MT_bool rwe; /* If set - RDMA - write enabled on receive queue. Not valid (reserved) in EE context. */\r
- MT_bool rre; /* If set - RDMA - read enabled on receive queue. Not valid (reserved) in EE context. */\r
- u_int8_t rra_max; /* Maximum number of outstanding RDMA-read/Atomic operations allowed on receive queue is 2^RRA_Max. \;Must be 0 for EE context. */\r
- u_int32_t next_rcv_psn; /* Next (expected) PSN on receive */\r
- u_int8_t min_rnr_nak; /* Minimum RNR NAK timer value (TTTTT field encoding). Not valid (reserved) in EE context. */\r
- u_int32_t ra_buff_indx; /* Index to outstanding read/atomic buffer. */\r
- u_int32_t cqn_rcv; /* CQ number completions from receive queue to be reported to. Not valid (reserved) in EE context. */\r
- u_int64_t next_rcv_wqe; /* Pointer and properties of next WQE on the receive queue. Ths format is same as next segment (first 8 bytes) in the WQE Not valid (reserved) in EE context. */\r
- u_int32_t q_key; /* Q_Key to be validated against received datagrams and sent if MSB of Q_Key specified in the WQE is set. Not valid (reserved) in EE context. */\r
- u_int32_t srqn; /* Specifies the SRQ number from which the QP dequeues receive descriptors. Valid only if srq bit is set. Not valid (reserved) in EE context. */\r
- MT_bool srq; /* If set, this queue is fed by descriptors from SRQ specified in the srqn field. Not valid (reserved) in EE context. */\r
-}\r
-THH_qpee_context_t;\r
-\r
-typedef struct THH_srq_context_st {\r
- u_int32_t pd; /* SRQ protection domain */\r
- u_int32_t uar; /* UAR index for doorbells of this SRQ */\r
- u_int32_t l_key; /* memory key (L-Key) to be used to access WQEs */\r
- u_int32_t wqe_addr_h; /* Bits 63:32 of WQE address for SRQ */\r
- u_int32_t next_wqe_addr_l; /* Bits 31:0 of next WQE address (valid only on QUERY/HW2SW) */\r
- u_int32_t ds; /* Descriptor size for SRQ (divided by 16) */\r
- u_int16_t wqe_cnt; /* WQE count on SRQ */\r
- u_int8_t state; /* SRQ state (QUERY)- 0xF=SW-own 0x0=HW-own 0x1=SRQ-error */\r
-} THH_srq_context_t;\r
-\r
-typedef struct {\r
- u_int8_t ver; /* Version. Must be zero for InfiniHost */\r
- MT_bool r_w; /* Defines whether this entry is Region (TRUE) or Window (FALSE) */\r
- MT_bool pa; /* Physical address. If set, no virtual-to-physical address translation will be performed for this region */\r
- MT_bool lr; /* If set - local read access enabled */\r
- MT_bool lw; /* If set - local write access enabled */\r
- MT_bool rr; /* If set - Remote read access enabled. */\r
- MT_bool rw; /* If set - remote write access enabled */\r
- MT_bool a; /* If set - Remote Atomic access is enabled */\r
- MT_bool eb; /* If set - Bind is enabled. Valid for region entry only. */\r
- MT_bool pw; /* If set, all writes to this region are posted writes */\r
- MT_bool m_io; /* If set - memory command is used on the uplink bus, if cleared - IO. If IO configured - PW bit must be cleared. */\r
- u_int8_t status; /* 0 valid window/region\;1 valid unbound window */\r
- u_int8_t page_size; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes. */\r
- u_int32_t mem_key; /* The memory Key. This field is compared to key used to access the region/window. Lower-order bits are restricted (index to the table). */\r
- u_int32_t pd; /* Protection Domain */\r
- u_int64_t start_address; /* Start Address - Virtual Address where this region/window starts */\r
- u_int64_t reg_wnd_len; /* Region/Window Length */\r
- u_int32_t lkey; /* LKey used for accessing the MTT (for bound windows) */\r
- u_int32_t win_cnt; /* Number of windows bounded to this region. Valid for regions only. */\r
- u_int32_t win_cnt_limit; /* The number of windows (limit) that can be bounded to this region. If bind operation is attempted while Win_cnt_limit, the operation will be aborted, CQE with error will be generated and QP will transfer to error state. Zero means no limit. */\r
- u_int64_t mtt_seg_adr; /* Base (first) address of the MTT segment, aligned on segment_size boundary */\r
-}\r
-THH_mpt_entry_t;\r
-\r
-typedef struct {\r
- u_int64_t ptag; /* physical tag (full address). Low order bits are masked according to page size*/\r
- MT_bool p; /* Present bit. If set, page entry is valid. If cleared, access to this page will generate 'non-present page access fault'. */\r
-}\r
-THH_mtt_entry_t;\r
-\r
-typedef struct THH_port_init_props_st{ /* !!! This is going to be changed for updated INIT_IB !!! */\r
- MT_bool e; /* Port Physical Link Enable */\r
- u_int8_t vl_cap; /* Maximum VLs supported on the port, excluding VL15 */\r
- IB_link_width_t port_width_cap; /* IB Port Width */\r
- IB_mtu_t mtu_cap; /* Maximum MTU Supported */\r
- u_int16_t max_gid; /* Maximum number of GIDs for the port */\r
- u_int16_t max_pkey; /* Maximum pkeys for the port */\r
- MT_bool g0; /* ADDED FOR NEW INIT_IB */\r
- IB_guid_t guid0; /* ADDED FOR NEW INIT_IB */\r
-}\r
-THH_port_init_props_t;\r
-\r
-typedef struct {\r
- MT_bool rqk; /* reset QKey Violation counter */\r
- u_int32_t capability_mask; /* PortInfo Capability Mask */\r
-} THH_set_ib_props_t;\r
-\r
-#if 0\r
-typedef struct { /* To be used for MODIFY_HCA */\r
-\r
-} THH_port_props_t;\r
-#endif\r
-\r
-typedef struct {\r
- u_int8_t log_max_qp; /* Log2 of the Maximum number of QPs supported */\r
- u_int8_t log2_rsvd_qps; /* Log2 of the number of QPs reserved for firmware use */\r
- u_int8_t log_max_qp_sz; /* Log2 of the maximum WQEs allowed on the RQ or the SQ */\r
- u_int8_t log_max_srqs; /* Log2 of the Maximum number of SRQs supported */\r
- u_int8_t log2_rsvd_srqs; /* Log2 of the number of SRQs reserved for firmware use */\r
- u_int8_t log_max_srq_sz; /* Log2 of the maximum WQEs allowed on the SRQ */\r
- u_int8_t log_max_ee; /* Log2 of the Maximum number of EE contexts supported */\r
- u_int8_t log2_rsvd_ees; /* Log2 of the number of EECs reserved for firmware use */\r
- u_int8_t log_max_cq; /* Log2 of the Maximum number of CQs supported */\r
- u_int8_t log2_rsvd_cqs; /* Log2 of the number of CQs reserved for firmware use */\r
- u_int8_t log_max_cq_sz; /* Log2 of the Maximum CQEs allowed in a CQ */\r
- u_int8_t log_max_eq; /* Log2 of the Maximum number of EQs */\r
- u_int8_t num_rsvd_eqs; /* The number of EQs reserved for firmware use */\r
- u_int8_t log_max_mpts; /* Log2 of the Maximum number of MPT entries (the number of Regions/Windows) */\r
- u_int8_t log_max_mtt_seg; /* Log2 of the Maximum number of MTT segments */\r
- u_int8_t log2_rsvd_mrws; /* Log2 of the number of MPTs reserved for firmware use */\r
- u_int8_t log_max_mrw_sz; /* Log2 of the Maximum Size of Memory Region/Window */\r
- u_int8_t log2_rsvd_mtts; /* Log2 of the number of MTT segments reserved for firmware use */\r
- u_int8_t log_max_av; /* Log2 of the Maximum number of Address Vectors */\r
- u_int8_t log_max_ra_res_qp; /* Log2 of the Maximum number of outstanding RDMA read/Atomic per QP as a responder */\r
- u_int8_t log_max_ra_req_qp; /* Log2 of the maximum number of outstanding RDMA read/Atomic per QP as a requester */\r
- u_int8_t log_max_ra_res_global; /* Log2 of the maximum number of RDMA read/atomic operations the HCA responder can support globally. That implies the RDB table size. */\r
- u_int8_t local_ca_ack_delay; /* The Local CA ACK Delay. This is the value recommended to be returned in Query HCA verb.\r
- The delay value in microseconds is computed using 4.096us * 2^(Local_CA_ACK_Delay). */\r
- u_int8_t log_max_gid; /* Log2 of the maximum number of GIDs per port */\r
- u_int8_t log_max_pkey; /* Log2 of the max PKey Table Size (per IB port) */\r
- u_int8_t num_ports; /* Number of IB ports */\r
- IB_link_width_t max_port_width; /* IB Port Width */\r
- IB_mtu_t max_mtu; /* Maximum MTU Supported */\r
- u_int8_t max_vl; /* Maximum number of VLs per IB port excluding VL15 */\r
- MT_bool rc; /* RC Transport supported */\r
- MT_bool uc; /* UC Transport Supported */\r
- MT_bool ud; /* UD Transport Supported */\r
- MT_bool rd; /* RD Transport Supported */\r
- MT_bool raw_ipv6; /* Raw IPv6 Transport Supported */\r
- MT_bool raw_ether; /* Raw Ethertype Transport Supported */\r
- MT_bool srq; /* SRQ is supported */\r
- MT_bool pkv; /* PKey Violation Counter Supported */\r
- MT_bool qkv; /* QKey Violation Coutner Supported */\r
- MT_bool mw; /* Memory windows supported */\r
- MT_bool apm; /* Automatic Path Migration Supported */\r
- MT_bool atm; /* Atomic operations supported (atomicity is guaranteed between QPs on this HCA) */\r
- MT_bool rm; /* Raw Multicast Supported */\r
- MT_bool avp; /* Address Vector Port checking supported */\r
- MT_bool udm; /* UD Multicast supported */\r
- MT_bool pg; /* Paging on demand supported */\r
- MT_bool r; /* Router mode supported */\r
- u_int8_t log_pg_sz; /* Log2 of system page size */\r
- u_int8_t uar_sz; /* UAR Area Size = 1MB * 2^max_uar_sz */\r
- u_int8_t num_rsvd_uars; /* The number of UARs reserved for firmware use */\r
- u_int16_t max_desc_sz; /* Max descriptor size */\r
- u_int8_t max_sg; /* Maximum S/G list elements in a WQE */\r
- u_int8_t log_max_mcg; /* Log2 of the maximum number of multicast groups */\r
- u_int8_t log_max_qp_mcg; /* Log2 of the maximum number of QPs per multicast group */\r
- /*MT_bool mce; / * Multicast support for extended QP list. - removed */\r
- u_int8_t log_max_rdds; /* Log2 of the maximum number of RDDs */\r
- u_int8_t num_rsvd_rdds; /* The number of RDDs reserved for firmware use */\r
- u_int8_t log_max_pd; /* Log2 of the maximum number of PDs */\r
- u_int8_t num_rsvd_pds; /* The number of PDs reserved for firmware use */\r
- u_int16_t qpc_entry_sz; /* QPC Entry Size for the device\;For Tavor entry size is 256 bytes */\r
- u_int16_t eec_entry_sz; /* EEC Entry Size for the device\;For Tavor entry size is 256 bytes */\r
- u_int16_t eqpc_entry_sz; /* Extended QPC entry size for the device\;For Tavor entry size is 32 bytes */\r
- u_int16_t eeec_entry_sz; /* Extended EEC entry size for the device\;For Tavor entry size is 32 bytes */\r
- u_int16_t cqc_entry_sz; /* CQC entry size for the device\;For Tavor entry size is 64 bytes */\r
- u_int16_t eqc_entry_sz; /* EQ context entry size for the device\;For Tavor entry size is 64 bytes */\r
- u_int16_t srq_entry_sz; /* SRQ entry size for the device\;For Tavor entry size is 32 bytes */\r
- u_int16_t uar_scratch_entry_sz; /* UAR Scratchpad Entry Size\;For Tavor entry size is 32 bytes */\r
-}\r
-THH_dev_lim_t;\r
-\r
-typedef struct {\r
- u_int16_t fw_rev_major; /* Firmware Revision - Major */\r
- u_int16_t fw_rev_minor; /* Firmware Revision - Minor */\r
- u_int16_t fw_rev_subminor; /* Firmware Sub-minor version (Patch level). */\r
- u_int16_t cmd_interface_rev; /* Command Interface Interpreter Revision ID */\r
- u_int8_t log_max_outstanding_cmd; /* Log2 of the maximum number of commands the HCR can support simultaneously */\r
- u_int64_t fw_base_addr; /* Physical Address of Firmware Area in DDR Memory */\r
- u_int64_t fw_end_addr; /* End of firmware address in DDR memory */\r
- u_int64_t error_buf_start; /* Read Only buffer for catastrofic error reports (phys addr) */\r
- u_int32_t error_buf_size; /* size of catastrophic error report buffer in words */\r
-}\r
-THH_fw_props_t;\r
-\r
-typedef struct {\r
- u_int32_t vendor_id; /* Adapter vendor ID */\r
- u_int32_t device_id; /* Adapter Device ID */\r
- u_int32_t revision_id; /* Adapter Revision ID */\r
- u_int8_t intapin; /* Interrupt Signal ID of HCA device pin that is connected to the INTA trace in the HCA board.\r
- 0..39 and 63 are valid values. 255 means INTA trace in board is not connected to the HCA device.\r
- All other values are reserved */\r
-}\r
-THH_adapter_props_t;\r
-\r
-typedef struct {\r
- u_int64_t ddr_start_adr; /* DDR memory start address */\r
- u_int64_t ddr_end_adr; /* DDR memory end address (excluding DDR memory reserved for firmware) */\r
- MT_bool dh; /* When Set DDR is Hidden and cannot be accessed from PCI bus */\r
- THH_dim_integrity_t di;\r
- THH_dim_apm_t ap;\r
- THH_dim_info_t dimm0;\r
- THH_dim_info_t dimm1;\r
- THH_dim_info_t dimm2;\r
- THH_dim_info_t dimm3;\r
-}\r
-THH_ddr_props_t;\r
-\r
-\r
-typedef struct {\r
- u_int32_t next_gid_index;\r
- IB_gid_t mgid; /* Group's GID */\r
- u_int32_t valid_qps; /* number of QPs in given group (size of qps array) */\r
- IB_wqpn_t *qps; /* QPs array with valid_qps QPN entries */\r
-}\r
-THH_mcg_entry_t;\r
-\r
-#endif /* H_CMD_TYPES_H */\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include <cmdif_priv.h>\r
-#include <cmdif.h>\r
-#include <tddrmm.h>\r
-#include <mosal.h>\r
-#include <MT23108.h>\r
-#ifdef VXWORKS_OS\r
-#include "Osa_Context.h"\r
-#include "Dump.h"\r
-#endif\r
-\r
-\r
-/*================ macro definitions ===============================================*/\r
-#ifdef THH_CMD_TIME_TRACK\r
-extern u_int64_t THH_eventp_last_cmdif_interrupt;\r
-#endif\r
-\r
-#define PRM_RSC_DELTA 32\r
-#define MAX_CMD_OBJS 32 /* max number of objects allowed to be created */\r
-#define CMD_ETIME_EVENTS 1000000 /* max execution time is fixed when we're using events */\r
-#define MAX_ITER_ON_EINTR 10\r
-#define MAX_UC_FOR_GO 100 /* time in microsec to do busy wait on go bit */\r
-#define MAX_UC_SLEEP_FOR_GO 300000000 /* time in microsec to do busy wait on go bit */\r
-#define SHORT_UC_DELAY_FOR_GO 10 /* time in microsec to do busy wait on go bit after first time */\r
-\r
-#ifdef IN\r
- #undef IN\r
-#endif\r
-#define IN\r
-\r
-#ifdef OUT\r
- #undef OUT\r
-#endif\r
-#define OUT\r
-\r
-#define HCR_DW_BYTE_OFFSET(field) (MT_BYTE_OFFSET(tavorprm_hca_command_register_st,field) & (~3))\r
-#define HCR_DW_BIT_OFFSET(field) (MT_BIT_OFFSET(tavorprm_hca_command_register_st,field) - HCR_DW_BYTE_OFFSET(field) * 8)\r
-#define HCR_BIT_SIZE(field) MT_BIT_SIZE(tavorprm_hca_command_register_st,field)\r
-\r
-\r
-#define PREP_TOKEN_DW(token_dw, val) MT_INSERT32((token_dw),(val),HCR_DW_BIT_OFFSET(token),MT_BIT_SIZE(tavorprm_hca_command_register_st,token)); \\r
- token_dw = MOSAL_cpu_to_be32(token_dw);\r
-\r
-\r
-\r
-#define DEFAULT_TOKEN 0x1234 /* default token value to use when there can be no outstanding commands */\r
-#define FREE_LIST_EOL ((u_int32_t)(-1))\r
-\r
-#define NEW_EQE_FORMAT\r
-\r
-\r
-\r
-#ifdef VXWORKS_OS\r
-extern int Osa_TraceMe();\r
-#endif\r
-\r
-\r
-/*================ static variables definitions ====================================*/\r
-\r
-\r
-\r
-/*================ static functions prototypes =====================================*/\r
-static THH_cmd_status_t sys_en_hca(struct cmd_if_context_st *entry);\r
-static THH_cmd_status_t main_cmd_flow(struct cmd_if_context_st *entry, command_fields_t *cmd_prms);\r
-static MT_bool cmdif_is_free(struct cmd_if_context_st *entry);\r
-static void cleanup_cmdobj(struct cmd_if_context_st *entry);\r
-static inline void write_command_dw(u_int32_t *dst_buf, u_int8_t go,\r
- u_int8_t use_event, u_int8_t op_mod, u_int16_t opcode);\r
-static inline THH_cmd_status_t cmd_if_status(struct cmd_if_context_st *entry);\r
-static inline void set_mailbox(u_int32_t *dst_buf, MT_phys_addr_t mbx_pa);\r
-static inline void ptr_to_mailbox_ptr(MT_phys_addr_t ptr, addr_64bit_t *mbx_pmtr);\r
-static inline void cvt_be32_to_cpu(void *buf, u_int32_t size);\r
-static inline void cvt_cpu_to_be32(void *buf, u_int32_t size);\r
-static void *memcpy_to_tavor(void *dst, const void *src, MT_size_t size);\r
-static void *memcpy_from_tavor(void *dst, const void *src, MT_size_t size);\r
-static inline u_int64_t d32_to_s64(u_int32_t hi, u_int32_t lo);\r
-static THH_cmd_status_t cmd_flow_events(struct cmd_if_context_st *entry, command_fields_t *cmd_prms);\r
-static THH_cmd_status_t cmd_flow_no_events(struct cmd_if_context_st *entry, command_fields_t *cmd_prms);\r
-/* ===> parse functions <=== */\r
-static void parse_HCR(u_int32_t *result_hcr_image_p, priv_hcr_t *hcr);\r
-#ifdef NEW_EQE_FORMAT\r
-static void parse_new_HCR(u_int32_t *result_hcr_image_p, priv_hcr_t *hcr);\r
-#endif\r
-static void edit_hcr(struct cmd_if_context_st *entry, command_fields_t *cmd_prms, u_int16_t token, cmd_ctx_t *ctx_p, int event);\r
-static void extract_hcr(command_fields_t *cmd_prms, priv_hcr_t *hcr);\r
-\r
-static void print_outs_commands(ctx_obj_t *ctxo_p);\r
-static void track_exec_cmds(struct cmd_if_context_st *entry, cmd_ctx_t *ctx_p);\r
-static void print_track_arr(struct cmd_if_context_st *entry);\r
-\r
-/* ===> pool handling <=== */\r
-static HH_ret_t alloc_cmd_contexts(struct cmd_if_context_st *entry, u_int32_t num, MT_bool in_at_ddr, MT_bool out_at_ddr);\r
-static HH_ret_t de_alloc_cmd_contexts(struct cmd_if_context_st *entry);\r
-static HH_ret_t acq_cmd_ctx(struct cmd_if_context_st *entry, cmd_ctx_t **ctx_pp);\r
-static void rel_cmd_ctx(struct cmd_if_context_st *entry, cmd_ctx_t *ctx_p);\r
-static HH_ret_t re_alloc_resources(struct cmd_if_context_st *entry, MT_bool in_at_ddr, MT_bool out_at_ddr);\r
-\r
-static int log2(u_int64_t arg);\r
-\r
-\r
-/* ===> print functions <=== */\r
-//static void print_hcr_dump(struct cmd_if_context_st *entry, u_int32_t cmd);\r
-//static void print_hcr_fileds(u_int32_t *buf, u_int32_t cmd);\r
-\r
-/********************************** UTILS *********************************/\r
-static void cmd_hexdump( void *buf, int size, const char * dump_title )\r
-{\r
- int i, j, maxlines, bytes_left, this_line;\r
- char linebuf[200], tempout[20];\r
- u_int8_t *iterator;\r
-\r
- \r
- iterator = (u_int8_t *)buf;\r
- bytes_left = size;\r
- if (size <= 0) {\r
- return;\r
- }\r
-\r
- MTL_ERROR1("%s, starting at addr 0x%p, size=%d:\n",\r
- dump_title, buf, size);\r
- \r
-\r
- maxlines = (size / 16) + ((size % 16) ? 1 : 0);\r
-\r
- for (i = 0; i < maxlines; i++) {\r
- memset(linebuf, 0, sizeof(linebuf));\r
- this_line = (bytes_left > 16 ? 16 : bytes_left);\r
-\r
- for (j = 0; j < this_line; j++) {\r
- if ((j % 4) == 0) {\r
- strcat(linebuf," ");\r
- }\r
- sprintf(tempout, "%02x", *iterator);\r
- iterator++; bytes_left--;\r
- strcat(linebuf,tempout);\r
- }\r
- MTL_ERROR1("%s\n", linebuf);\r
- }\r
- MTL_ERROR1("%s END\n", dump_title);\r
-}\r
-\r
-static void dump_cmd_err_info(cmd_ctx_t *ctx_p, command_fields_t *cmd_prms) \r
-{\r
- MTL_ERROR1("CMD ERROR DUMP. opcode=0x%x, opc_mod = 0x%x, exec_time_micro=%u\n",\r
- (u_int32_t)cmd_prms->opcode, cmd_prms->opcode_modifier, cmd_prms->exec_time_micro);\r
- cmd_hexdump((void *) ctx_p->hcr_buf,HCR_SIZE*sizeof(u_int32_t), "HCR dump"); \r
- if ((cmd_prms->in_trans == TRANS_MAILBOX) && (cmd_prms->in_param_size > 0)) {\r
- cmd_hexdump((void *) ctx_p->in_prm.prm_alloc_va,cmd_prms->in_param_size, "IN MAILBOX dump"); \r
- }\r
- if ((cmd_prms->out_trans == TRANS_MAILBOX) && (cmd_prms->out_param_size > 0)) {\r
- cmd_hexdump((void *) ctx_p->out_prm.prm_alloc_va,cmd_prms->out_param_size, "OUT MAILBOX dump"); \r
- }\r
-}\r
-\r
-/* ==== inline functions ===============*/\r
-\r
-static HH_ret_t inline get_ctx_by_idx(struct cmd_if_context_st *entry, u_int16_t idx, cmd_ctx_t **ctx_pp)\r
-{\r
- if ( (idx<entry->ctx_obj.num) && (entry->ctx_obj.ctx_arr[idx].ref_cnt>0) ) {\r
- *ctx_pp = &entry->ctx_obj.ctx_arr[idx];\r
- return HH_OK;\r
- }\r
- return HH_EAGAIN;\r
-}\r
-\r
-static THH_eqn_t inline eqn_set(struct cmd_if_context_st *entry, THH_eqn_t new_eqn)\r
-{\r
- THH_eqn_t old_eqn;\r
-\r
- MOSAL_spinlock_dpc_lock(&entry->eqn_spl);\r
- old_eqn = entry->eqn;\r
- entry->eqn = new_eqn;\r
- MOSAL_spinlock_unlock(&entry->eqn_spl);\r
- return old_eqn;\r
-}\r
-\r
-\r
-/*\r
- * write_command_dw\r
- */\r
-static inline void write_command_dw(u_int32_t *dst_buf, u_int8_t go,\r
- u_int8_t use_event, u_int8_t op_mod, u_int16_t opcode)\r
-{\r
- u_int32_t cmd=0;\r
-\r
- MT_INSERT32(cmd,opcode,HCR_DW_BIT_OFFSET(opcode),HCR_BIT_SIZE(opcode));\r
- MT_INSERT32(cmd,op_mod,HCR_DW_BIT_OFFSET(opcode_modifier),HCR_BIT_SIZE(opcode_modifier));\r
- MT_INSERT32(cmd,use_event,HCR_DW_BIT_OFFSET(e),HCR_BIT_SIZE(e));\r
- MT_INSERT32(cmd,go,HCR_DW_BIT_OFFSET(go),HCR_BIT_SIZE(go));\r
- MT_INSERT32(cmd,0,HCR_DW_BIT_OFFSET(status),HCR_BIT_SIZE(status)); /* status */\r
- *dst_buf = MOSAL_cpu_to_be32(cmd);\r
-}\r
-\r
-\r
-/*\r
- * ptr_to_mailbox_ptr\r
- */\r
-static inline void ptr_to_mailbox_ptr(MT_phys_addr_t ptr, addr_64bit_t *mbx_pmtr)\r
-{\r
- if ( sizeof(ptr) == 4 ) {\r
- MTL_DEBUG4("pointer is 32 bit\n");\r
- mbx_pmtr->addr_h = 0;\r
- mbx_pmtr->addr_l = (u_int32_t)ptr;\r
- }\r
- else if ( sizeof(ptr) == 8 ) {\r
- MTL_DEBUG4("pointer is 64 bit\n");\r
- mbx_pmtr->addr_h = (u_int32_t)(((u_int64_t)ptr)>>32);\r
- mbx_pmtr->addr_l = (u_int32_t)ptr;\r
- }\r
- else {\r
- MTL_ERROR1("bad address pointer size: %d\n",(int)sizeof(ptr));\r
- }\r
- mbx_pmtr->addr_h = MOSAL_cpu_to_be32(mbx_pmtr->addr_h);\r
- mbx_pmtr->addr_l = MOSAL_cpu_to_be32(mbx_pmtr->addr_l);\r
-}\r
-\r
-/*================ global functions definitions ====================================*/\r
-\r
-/*\r
- * THH_cmd_create\r
- */\r
-HH_ret_t THH_cmd_create(THH_hob_t hob, u_int32_t hw_ver, MT_phys_addr_t cr_base, MT_phys_addr_t uar0_base, THH_cmd_t *cmd_if_p,\r
- MT_bool inf_timeout, u_int32_t num_cmds_outs)\r
-{\r
- struct cmd_if_context_st *entry;\r
- HH_ret_t rc;\r
- u_int64_t cps;\r
-\r
- FUNC_IN;\r
-\r
- /* allocate memory for cmdif object */\r
- entry = TMALLOC(struct cmd_if_context_st);\r
- if ( !entry ) {\r
- MTL_ERROR1(MT_FLFMT("%s: failed to allocate memory for cmdif object"), __func__);\r
- MT_RETURN(HH_EAGAIN);\r
- }\r
- memset(entry, 0, sizeof(struct cmd_if_context_st));\r
-\r
- /* check if we should post commands UAR0 */\r
- if ( uar0_base == (MT_phys_addr_t) MAKE_ULONGLONG(0xFFFFFFFFFFFFFFFF) ) {\r
- entry->post_to_uar0 = FALSE;\r
- }\r
- else {\r
- entry->post_to_uar0 = TRUE;\r
- MTL_ERROR1(MT_FLFMT("%s: posting to uar0"), __func__);\r
- }\r
-\r
- entry->hob = hob;\r
- entry->hcr_virt_base = (void *)MOSAL_io_remap(cr_base + TAVOR_HCR_OFFSET_FROM_CR_BASE,\r
- sizeof(struct tavorprm_hca_command_register_st)/8);\r
-\r
- /* map hcr to kernel space */\r
- if ( !entry->hcr_virt_base ) {\r
- MTL_ERROR1(MT_FLFMT("%s: MOSAL_io_remap() failed. pa="PHYS_ADDR_FMT", size=" SIZE_T_FMT), __func__,\r
- cr_base + TAVOR_HCR_OFFSET_FROM_CR_BASE, sizeof(struct tavorprm_hca_command_register_st)/8);\r
- cleanup_cmdobj(entry);\r
- MT_RETURN(HH_EAGAIN);\r
- }\r
-\r
- /* if we're going to post to uar0 we need to map 8 bytes from UAR0 to kernel space */\r
- if ( entry->post_to_uar0 ) {\r
- entry->uar0_virt_base = (void *)MOSAL_io_remap(uar0_base, 8);\r
- if ( !entry->uar0_virt_base ) {\r
- cleanup_cmdobj(entry);\r
- MT_RETURN(HH_EAGAIN);\r
- }\r
- }\r
-\r
- entry->sys_enabled = FALSE;\r
- entry->ddrmm = THH_DDRMM_INVALID_HANDLE;\r
- entry->eqn = THH_INVALID_EQN;\r
-\r
- entry->inf_timeout = inf_timeout;\r
- entry->req_num_cmds_outs = num_cmds_outs;\r
-\r
- entry->tokens_shift = 0;\r
- entry->tokens_counter = 0;\r
- entry->tokens_idx_mask = (1<<entry->tokens_shift)-1;\r
-\r
- cps = MOSAL_get_counts_per_sec();\r
- if ( cps & MAKE_ULONGLONG(0xffffffff00000000) ) {\r
- MTL_ERROR1(MT_FLFMT("%s: *** delay time calculation for go bit will not be accurate !!!"), __func__);\r
- }\r
- entry->counts_busy_wait_for_go = (u_int64_t)(((u_int32_t)cps)/1000000) * MAX_UC_FOR_GO;\r
- entry->counts_sleep_wait_for_go = (u_int64_t)(((u_int32_t)cps)/1000000) * MAX_UC_SLEEP_FOR_GO;\r
- entry->short_wait_for_go = (u_int64_t)(((u_int32_t)cps)/1000000) * SHORT_UC_DELAY_FOR_GO;\r
-\r
- entry->in_at_ddr = FALSE;\r
- entry->out_at_ddr = FALSE;\r
- rc = alloc_cmd_contexts(entry, 1, entry->in_at_ddr, entry->in_at_ddr);\r
- if ( rc != HH_OK ) {\r
- MTL_ERROR1(MT_FLFMT("failed to allocate command contexts"));\r
- cleanup_cmdobj(entry);\r
- MT_RETURN(HH_EAGAIN);\r
- }\r
-\r
- entry->track_arr = TNMALLOC(u_int16_t, 256);\r
- if ( !entry->track_arr ) {\r
- cleanup_cmdobj(entry);\r
- MT_RETURN(HH_EAGAIN);\r
- }\r
- memset(entry->track_arr, 0, sizeof(u_int16_t)*256);\r
-\r
- MOSAL_mutex_init(&entry->sys_en_mtx);\r
- MOSAL_sem_init(&entry->no_events_sem, 1);\r
- MOSAL_mutex_init(&entry->hcr_mtx);\r
-\r
- MOSAL_sem_init(&entry->use_events_sem, 0);\r
- MOSAL_sem_init(&entry->fw_outs_sem, 0);\r
-\r
- MOSAL_spinlock_init(&entry->close_spl);\r
- entry->close_action = FALSE;\r
- MOSAL_syncobj_init(&entry->fatal_list);\r
-\r
- MOSAL_spinlock_init(&entry->eqn_spl);\r
-\r
- MOSAL_spinlock_init(&entry->ctr_spl);\r
- entry->events_in_pipe = 0;\r
- entry->poll_in_pipe = 0;\r
- \r
- *cmd_if_p = (THH_cmd_t)entry;\r
-\r
- MT_RETURN(HH_OK);\r
-}\r
-\r
-\r
-\r
-/*\r
- * THH_cmd_destroy\r
- */\r
-HH_ret_t THH_cmd_destroy(THH_cmd_t cmd_if)\r
-{\r
- struct cmd_if_context_st *entry = (struct cmd_if_context_st *)cmd_if;\r
-\r
- FUNC_IN;\r
-\r
-\r
- MOSAL_mutex_free(&entry->sys_en_mtx);\r
- MOSAL_sem_free(&entry->no_events_sem);\r
- MOSAL_sem_free(&entry->use_events_sem);\r
- MOSAL_sem_free(&entry->fw_outs_sem);\r
- MOSAL_syncobj_free(&entry->fatal_list);\r
- \r
- cleanup_cmdobj(entry);\r
-\r
- MT_RETURN(HH_OK);\r
-}\r
-\r
-\r
-/*\r
- * THH_cmd_set_fw_props\r
- */\r
-THH_cmd_status_t THH_cmd_set_fw_props(THH_cmd_t cmd_if, THH_fw_props_t *fw_props)\r
-{\r
- struct cmd_if_context_st *entry = (struct cmd_if_context_st *)cmd_if;\r
- unsigned int i;\r
-\r
- FUNC_IN;\r
- if ( entry->query_fw_done==FALSE ) {\r
- entry->queried_max_outstanding = 1<<fw_props->log_max_outstanding_cmd;\r
- if ( entry->req_num_cmds_outs <= entry->queried_max_outstanding ) {\r
- entry->max_outstanding = entry->req_num_cmds_outs;\r
- }\r
- else {\r
- entry->max_outstanding = entry->queried_max_outstanding;\r
- }\r
-\r
- entry->sw_num_rsc = 1<<ceil_log2((1<<ceil_log2(entry->max_outstanding)) + PRM_RSC_DELTA);\r
- MTL_DEBUG1(MT_FLFMT("%s: fw=%d, delta=%d, used=%d"), __func__,\r
- entry->queried_max_outstanding, PRM_RSC_DELTA, entry->sw_num_rsc);\r
-\r
- if ( re_alloc_resources(entry, entry->in_at_ddr, entry->out_at_ddr) != HH_OK ) {\r
- MTL_ERROR1(MT_FLFMT("%s: re_alloc_resources failed"), __func__);\r
- MT_RETURN(THH_CMD_STAT_EAGAIN);\r
- }\r
-\r
- for ( i=0; i<entry->max_outstanding; ++i ) {\r
- MOSAL_sem_rel(&entry->fw_outs_sem);\r
- }\r
- /* the following line is not an error but just to make sure the line is printed */\r
- MTL_DEBUG1(MT_FLFMT("%s: queried_max_outstanding=%d, max_outstanding=%d"), __func__,\r
- entry->queried_max_outstanding, entry->max_outstanding);\r
- memcpy(&entry->fw_props,fw_props,sizeof(THH_fw_props_t));\r
-/*** warning C4242: '=' : conversion from 'int' to 'u_int8_t', possible loss of data ***/\r
- entry->tokens_shift = (u_int8_t)log2(entry->sw_num_rsc);\r
- entry->tokens_idx_mask = (1<<entry->tokens_shift)-1;\r
- entry->query_fw_done = TRUE;\r
- }\r
- MT_RETURN(THH_CMD_STAT_OK);\r
-}\r
-\r
-\r
-\r
-\r
-\r
-/*\r
- * THH_cmd_set_eq\r
- */\r
-HH_ret_t THH_cmd_set_eq(THH_cmd_t cmd_if)\r
-{\r
- struct cmd_if_context_st *entry = (struct cmd_if_context_st *)cmd_if;\r
- int i;\r
- THH_eqn_t old_eqn;\r
- unsigned long ctr;\r
-\r
- FUNC_IN;\r
- old_eqn = eqn_set(entry, 0);\r
- if ( old_eqn != THH_INVALID_EQN ) {\r
- /* eqn already set. clr_eq before setting a new one */\r
- MT_RETURN(HH_OK);\r
- }\r
-\r
- /* make sure there are no commands that passed the if in main_cmd_flow\r
- before we changed state tp prevent deadlock when we acquire the semaphore */\r
- do {\r
- MOSAL_spinlock_lock(&entry->ctr_spl);\r
- ctr = entry->poll_in_pipe;\r
- MOSAL_spinlock_unlock(&entry->ctr_spl);\r
- if ( ctr == 0 ) break;\r
- MOSAL_delay_execution(20000);\r
- \r
- } while ( 1 );\r
-\r
- MOSAL_sem_acq_ui(&entry->no_events_sem);\r
-\r
- for ( i=0; i<(int)entry->sw_num_rsc; ++i ) {\r
- MTL_DEBUG2(MT_FLFMT("increase sem level"));\r
- MOSAL_sem_rel(&entry->use_events_sem);\r
- }\r
-\r
- MT_RETURN(HH_OK);\r
-}\r
-\r
-\r
-/*\r
- * THH_cmd_clr_eq\r
- */\r
-HH_ret_t THH_cmd_clr_eq(THH_cmd_t cmd_if)\r
-{\r
- struct cmd_if_context_st *entry = (struct cmd_if_context_st *)cmd_if;\r
- int i;\r
- THH_eqn_t old_eqn;\r
- unsigned long ctr;\r
-\r
- FUNC_IN;\r
- MTL_DEBUG1(MT_FLFMT("%s: called"), __func__);\r
-\r
- old_eqn = eqn_set(entry, THH_INVALID_EQN);\r
- if ( old_eqn == THH_INVALID_EQN ) {\r
- MTL_DEBUG1(MT_FLFMT("%s: returning"), __func__);\r
- MT_RETURN(HH_OK); /* already cleared */\r
- }\r
-\r
- /* make sure there are no commands that passed the if in main_cmd_flow\r
- before we changed state tp prevent deadlock when we acquire the semaphore */\r
- do {\r
- MOSAL_spinlock_lock(&entry->ctr_spl);\r
- ctr = entry->events_in_pipe;\r
- MOSAL_spinlock_unlock(&entry->ctr_spl);\r
- if ( ctr == 0 ) break;\r
- MOSAL_delay_execution(20000);\r
- \r
- } while ( 1 );\r
-\r
- /* acquire semaphore to the full depth to avoid to others to acquire it */\r
- for ( i=0; i<(int)entry->sw_num_rsc; ++i ) {\r
- MOSAL_sem_acq_ui(&entry->use_events_sem);\r
- MTL_DEBUG1(MT_FLFMT("%s: acquired %d"), __func__, i);\r
- }\r
-\r
- MOSAL_sem_rel(&entry->no_events_sem);\r
- MTL_DEBUG1(MT_FLFMT("%s: returning"), __func__);\r
- MT_RETURN(HH_OK);\r
-}\r
-\r
-\r
-\r
-/*\r
- * THH_cmd_eventh\r
- */\r
-void THH_cmd_eventh(THH_cmd_t cmd_if, u_int32_t *result_hcr_image_p)\r
-{\r
- struct cmd_if_context_st *entry = (struct cmd_if_context_st *)cmd_if;\r
- priv_hcr_t hcr;\r
- cmd_ctx_t *ctx_p;\r
-\r
- FUNC_IN;\r
- MOSAL_sem_rel(&entry->fw_outs_sem);\r
- parse_new_HCR(result_hcr_image_p, &hcr);\r
-\r
-#ifdef THH_CMD_TIME_TRACK\r
- MTL_ERROR1("CMD_TIME:END: cmd=UNKNOWN token=0x%X time=["U64_FMT"]\n",\r
- hcr.token, THH_eventp_last_cmdif_interrupt);\r
-#endif \r
-\r
- MOSAL_spinlock_dpc_lock(&entry->ctx_obj.spl);\r
- if ( (get_ctx_by_idx(entry, hcr.token&entry->tokens_idx_mask, &ctx_p)!=HH_OK) ||\r
- (hcr.token!=ctx_p->token)\r
- ) {\r
- MOSAL_spinlock_unlock(&entry->ctx_obj.spl);\r
- MTL_ERROR1(MT_FLFMT("%s: could not find context by token. token=0x%04x"), __func__, hcr.token);\r
- THH_hob_fatal_error(entry->hob, THH_FATAL_TOKEN, VAPI_EV_SYNDROME_NONE);\r
- MT_RETV;\r
- }\r
- ctx_p->hcr = hcr;\r
-\r
-/* fix for vapi_status console cmd */ \r
-#if !defined(VXWORKS_OS)\r
- MOSAL_syncobj_signal(&ctx_p->syncobj);\r
- MOSAL_spinlock_unlock(&entry->ctx_obj.spl);\r
-#else \r
- MOSAL_spinlock_unlock(&entry->ctx_obj.spl);\r
- MOSAL_syncobj_signal(&ctx_p->syncobj); \r
-#endif \r
-\r
- MT_RETV;\r
-}\r
-\r
-\r
-/*\r
- * THH_cmd_asign_ddrmm\r
- */\r
-HH_ret_t THH_cmd_assign_ddrmm(THH_cmd_t cmd_if, THH_ddrmm_t ddrmm)\r
-{\r
- struct cmd_if_context_st *entry = (struct cmd_if_context_st *)cmd_if;\r
- MT_bool in_at_ddr, out_at_ddr;\r
-\r
- FUNC_IN;\r
-\r
- MOSAL_mutex_acq_ui(&entry->sys_en_mtx);\r
- if ( entry->ddrmm != THH_DDRMM_INVALID_HANDLE ) {\r
- /* ddrmm already assigned */\r
- MOSAL_mutex_rel(&entry->sys_en_mtx);\r
- MT_RETURN(HH_EBUSY);\r
- }\r
- /* ddrmm was not assigned - assign it */\r
- entry->ddrmm = ddrmm;\r
- if ( entry->sys_enabled ) {\r
-#ifdef EQS_CMD_IN_DDR\r
- out_at_ddr = TRUE;\r
-#else\r
- out_at_ddr = FALSE;\r
-#endif\r
-#ifdef IN_PRMS_AT_DDR\r
- in_at_ddr = TRUE;\r
-#else\r
- in_at_ddr = FALSE;\r
-#endif\r
-\r
- if ( (in_at_ddr!=entry->in_at_ddr) || (out_at_ddr!=entry->out_at_ddr) ) {\r
- if ( re_alloc_resources(entry, in_at_ddr, out_at_ddr) != HH_OK ) {\r
- MOSAL_mutex_rel(&entry->sys_en_mtx);\r
- MT_RETURN(HH_EAGAIN);\r
- }\r
- else {\r
- entry->in_at_ddr = in_at_ddr;\r
- entry->out_at_ddr = out_at_ddr;\r
- }\r
- }\r
-\r
- }\r
-\r
- MOSAL_mutex_rel(&entry->sys_en_mtx);\r
-\r
- MT_RETURN(HH_OK);\r
-}\r
-\r
-\r
-/*\r
- * THH_cmd_revoke_ddrmm\r
- */\r
-HH_ret_t THH_cmd_revoke_ddrmm(THH_cmd_t cmd_if)\r
-{\r
- struct cmd_if_context_st *entry = (struct cmd_if_context_st *)cmd_if;\r
- HH_ret_t rc;\r
-\r
- FUNC_IN;\r
- MTL_DEBUG1(MT_FLFMT("%s called"), __func__);\r
- MOSAL_sem_acq_ui(&entry->no_events_sem);\r
- entry->in_at_ddr = FALSE;\r
- entry->out_at_ddr = FALSE;\r
- rc = re_alloc_resources(entry, entry->in_at_ddr, entry->out_at_ddr);\r
- if ( rc != HH_OK ) {\r
- MOSAL_sem_rel(&entry->no_events_sem);\r
- MTL_ERROR1(MT_FLFMT("%s: re_alloc_resources failed - %s"), __func__, HH_strerror(rc));\r
- MT_RETURN(rc);\r
- }\r
- entry->ddrmm = THH_DDRMM_INVALID_HANDLE;\r
-\r
- MOSAL_sem_rel(&entry->no_events_sem);\r
- MT_RETURN(HH_OK);\r
-}\r
-\r
-\r
-\r
-/*\r
- * THH_cmd_SYS_EN\r
- */\r
-THH_cmd_status_t THH_cmd_SYS_EN(IN THH_cmd_t cmd_if)\r
-{\r
- command_fields_t cmd_prms = {0};\r
- THH_cmd_status_t rc;\r
-\r
- FUNC_IN;\r
- cmd_prms.opcode = TAVOR_IF_CMD_SYS_EN;\r
- cmd_prms.in_trans = TRANS_NA;\r
- cmd_prms.out_trans = TRANS_NA;\r
- rc = cmd_invoke(cmd_if, &cmd_prms);\r
- if ( rc != THH_CMD_STAT_OK ) {\r
- MTL_ERROR1("%s\n", str_THH_cmd_status_t(rc));\r
- }\r
- MT_RETURN(rc);\r
-}\r
-\r
-\r
-\r
-/*\r
- * str_THH_cmd_status_t\r
- */\r
-const char *str_THH_cmd_status_t(THH_cmd_status_t status)\r
-{\r
- switch ( status ) {\r
- case THH_CMD_STAT_OK:\r
- return THH_CMD_STAT_OK_STR;\r
-\r
- case THH_CMD_STAT_INTERNAL_ERR:\r
- return THH_CMD_STAT_INTERNAL_ERR_STR;\r
-\r
- case THH_CMD_STAT_BAD_OP:\r
- return THH_CMD_STAT_BAD_OP_STR;\r
-\r
- case THH_CMD_STAT_BAD_PARAM:\r
- return THH_CMD_STAT_BAD_PARAM_STR;\r
-\r
- case THH_CMD_STAT_BAD_SYS_STATE:\r
- return THH_CMD_STAT_BAD_SYS_STATE_STR;\r
-\r
- case THH_CMD_STAT_BAD_RESOURCE:\r
- return THH_CMD_STAT_BAD_RESOURCE_STR;\r
-\r
- case THH_CMD_STAT_RESOURCE_BUSY:\r
- return THH_CMD_STAT_RESOURCE_BUSY_STR;\r
-\r
- case THH_CMD_STAT_DDR_MEM_ERR:\r
- return THH_CMD_STAT_DDR_MEM_ERR_STR;\r
-\r
- case THH_CMD_STAT_EXCEED_LIM:\r
- return THH_CMD_STAT_EXCEED_LIM_STR;\r
-\r
- case THH_CMD_STAT_BAD_RES_STATE:\r
- return THH_CMD_STAT_BAD_RES_STATE_STR;\r
-\r
- case THH_CMD_STAT_BAD_INDEX:\r
- return THH_CMD_STAT_BAD_INDEX_STR;\r
-\r
- case THH_CMD_STAT_BAD_QPEE_STATE:\r
- return THH_CMD_STAT_BAD_QPEE_STATE_STR;\r
-\r
- case THH_CMD_STAT_BAD_SEG_PARAM:\r
- return THH_CMD_STAT_BAD_SEG_PARAM_STR;\r
-\r
- case THH_CMD_STAT_REG_BOUND:\r
- return THH_CMD_STAT_REG_BOUND_STR;\r
-\r
- case THH_CMD_STAT_BAD_PKT:\r
- return THH_CMD_STAT_BAD_PKT_STR;\r
-\r
- case THH_CMD_STAT_EAGAIN:\r
- return THH_CMD_STAT_EAGAIN_STR;\r
-\r
- case THH_CMD_STAT_EABORT:\r
- return THH_CMD_STAT_EABORT_STR;\r
-\r
- case THH_CMD_STAT_ETIMEOUT:\r
- return THH_CMD_STAT_ETIMEOUT_STR;\r
-\r
- case THH_CMD_STAT_EFATAL:\r
- return THH_CMD_STAT_EFATAL_STR;\r
-\r
- case THH_CMD_STAT_EBADARG:\r
- return THH_CMD_STAT_EBADARG_STR;\r
-\r
- case THH_CMD_STAT_EINTR:\r
- return THH_CMD_STAT_EINTR_STR;\r
-\r
- case THH_CMD_STAT_BAD_SIZE:\r
- return THH_CMD_STAT_BAD_SIZE_STR;\r
-\r
- default:\r
- return "unrecognized status";\r
- }\r
-}\r
-\r
-\r
-const char *cmd_str(tavor_if_cmd_t opcode)\r
-{\r
- switch ( opcode ) {\r
- case TAVOR_IF_CMD_SYS_EN:\r
- return "TAVOR_IF_CMD_SYS_EN";\r
- case TAVOR_IF_CMD_SYS_DIS:\r
- return "TAVOR_IF_CMD_SYS_DIS";\r
- case TAVOR_IF_CMD_QUERY_DEV_LIM:\r
- return "TAVOR_IF_CMD_QUERY_DEV_LIM";\r
- case TAVOR_IF_CMD_QUERY_FW:\r
- return "TAVOR_IF_CMD_QUERY_FW";\r
- case TAVOR_IF_CMD_QUERY_DDR:\r
- return "TAVOR_IF_CMD_QUERY_DDR";\r
- case TAVOR_IF_CMD_QUERY_ADAPTER:\r
- return "TAVOR_IF_CMD_QUERY_ADAPTER";\r
- case TAVOR_IF_CMD_INIT_HCA:\r
- return "TAVOR_IF_CMD_INIT_HCA";\r
- case TAVOR_IF_CMD_CLOSE_HCA:\r
- return "TAVOR_IF_CMD_CLOSE_HCA";\r
- case TAVOR_IF_CMD_INIT_IB:\r
- return "TAVOR_IF_CMD_INIT_IB";\r
- case TAVOR_IF_CMD_CLOSE_IB:\r
- return "TAVOR_IF_CMD_CLOSE_IB";\r
- case TAVOR_IF_CMD_QUERY_HCA:\r
- return "TAVOR_IF_CMD_QUERY_HCA";\r
- case TAVOR_IF_CMD_SET_IB:\r
- return "TAVOR_IF_CMD_SET_IB";\r
- case TAVOR_IF_CMD_SW2HW_MPT:\r
- return "TAVOR_IF_CMD_SW2HW_MPT";\r
- case TAVOR_IF_CMD_QUERY_MPT:\r
- return "TAVOR_IF_CMD_QUERY_MPT";\r
- case TAVOR_IF_CMD_HW2SW_MPT:\r
- return "TAVOR_IF_CMD_HW2SW_MPT";\r
- case TAVOR_IF_CMD_READ_MTT:\r
- return "TAVOR_IF_CMD_READ_MTT";\r
- case TAVOR_IF_CMD_WRITE_MTT:\r
- return "TAVOR_IF_CMD_WRITE_MTT";\r
- case TAVOR_IF_CMD_MAP_EQ:\r
- return "TAVOR_IF_CMD_MAP_EQ";\r
- case TAVOR_IF_CMD_SW2HW_EQ:\r
- return "TAVOR_IF_CMD_SW2HW_EQ";\r
- case TAVOR_IF_CMD_HW2SW_EQ:\r
- return "TAVOR_IF_CMD_HW2SW_EQ";\r
- case TAVOR_IF_CMD_QUERY_EQ:\r
- return "TAVOR_IF_CMD_QUERY_EQ";\r
- case TAVOR_IF_CMD_SW2HW_CQ:\r
- return "TAVOR_IF_CMD_SW2HW_CQ";\r
- case TAVOR_IF_CMD_HW2SW_CQ:\r
- return "TAVOR_IF_CMD_HW2SW_CQ";\r
- case TAVOR_IF_CMD_QUERY_CQ:\r
- return "TAVOR_IF_CMD_QUERY_CQ";\r
- case TAVOR_IF_CMD_RST2INIT_QPEE:\r
- return "TAVOR_IF_CMD_RST2INIT_QPEE";\r
- case TAVOR_IF_CMD_INIT2RTR_QPEE:\r
- return "TAVOR_IF_CMD_INIT2RTR_QPEE";\r
- case TAVOR_IF_CMD_RTR2RTS_QPEE:\r
- return "TAVOR_IF_CMD_RTR2RTS_QPEE";\r
- case TAVOR_IF_CMD_RTS2RTS_QPEE:\r
- return "TAVOR_IF_CMD_RTS2RTS_QPEE";\r
- case TAVOR_IF_CMD_SQERR2RTS_QPEE:\r
- return "TAVOR_IF_CMD_SQERR2RTS_QPEE";\r
- case TAVOR_IF_CMD_2ERR_QPEE:\r
- return "TAVOR_IF_CMD_2ERR_QPEE";\r
- case TAVOR_IF_CMD_RTS2SQD_QPEE:\r
- return "TAVOR_IF_CMD_RTS2SQD_QPEE";\r
- case TAVOR_IF_CMD_SQD2RTS_QPEE:\r
- return "TAVOR_IF_CMD_SQD2RTS_QPEE";\r
- case TAVOR_IF_CMD_ERR2RST_QPEE:\r
- return "TAVOR_IF_CMD_ERR2RST_QPEE";\r
- case TAVOR_IF_CMD_QUERY_QPEE:\r
- return "TAVOR_IF_CMD_QUERY_QPEE";\r
- case TAVOR_IF_CMD_CONF_SPECIAL_QP:\r
- return "TAVOR_IF_CMD_CONF_SPECIAL_QP";\r
- case TAVOR_IF_CMD_MAD_IFC:\r
- return "TAVOR_IF_CMD_MAD_IFC";\r
- case TAVOR_IF_CMD_READ_MGM:\r
- return "TAVOR_IF_CMD_READ_MGM";\r
- case TAVOR_IF_CMD_WRITE_MGM:\r
- return "TAVOR_IF_CMD_WRITE_MGM";\r
- case TAVOR_IF_CMD_MGID_HASH:\r
- return "TAVOR_IF_CMD_MGID_HASH";\r
- case TAVOR_IF_CMD_CONF_NTU:\r
- return "TAVOR_IF_CMD_CONF_NTU";\r
- case TAVOR_IF_CMD_QUERY_NTU:\r
- return "TAVOR_IF_CMD_QUERY_NTU";\r
- case TAVOR_IF_CMD_RESIZE_CQ:\r
- return "TAVOR_IF_CMD_RESIZE_CQ";\r
- case TAVOR_IF_CMD_SUSPEND_QPEE:\r
- return "TAVOR_IF_CMD_SUSPEND_QPEE";\r
- case TAVOR_IF_CMD_UNSUSPEND_QPEE:\r
- return "TAVOR_IF_CMD_UNSUSPEND_QPEE";\r
- case TAVOR_IF_CMD_SW2HW_SRQ:\r
- return "TAVOR_IF_CMD_SW2HW_SRQ";\r
- case TAVOR_IF_CMD_HW2SW_SRQ:\r
- return "TAVOR_IF_CMD_HW2SW_SRQ";\r
- case TAVOR_IF_CMD_QUERY_SRQ:\r
- return "TAVOR_IF_CMD_QUERY_SRQ";\r
- case TAVOR_IF_CMD_SYNC_TPT:\r
- return "TAVOR_IF_CMD_SYNC_TPT";\r
- break;\r
- case TAVOR_IF_CMD_QUERY_DEBUG_MSG:\r
- return "TAVOR_IF_CMD_QUERY_DEBUG_MSG";\r
- break;\r
- case TAVOR_IF_CMD_SET_DEBUG_MSG:\r
- return "TAVOR_IF_CMD_SET_DEBUG_MSG";\r
- break;\r
- case TAVOR_IF_CMD_DIAG_RPRT:\r
- return "TAVOR_IF_CMD_DIAG_RPRT";\r
- break;\r
- case TAVOR_IF_CMD_NOP:\r
- return "TAVOR_IF_CMD_NOP";\r
- break;\r
- case TAVOR_IF_CMD_MOD_STAT_CFG:\r
- return "TAVOR_IF_CMD_MOD_STAT_CFG";\r
- break;\r
- case TAVOR_IF_CMD_ACCESS_DDR:\r
- return "TAVOR_IF_CMD_ACCESS_DDR";\r
- break;\r
- case TAVOR_IF_CMD_MODIFY_MPT:\r
- return "TAVOR_IF_CMD_MODIFY_MPT";\r
- break;\r
- case TAVOR_IF_CMD_SQD2SQD_QPEE:\r
- return "TAVOR_IF_CMD_SQD2SQD_QPEE";\r
- break;\r
- case TAVOR_IF_CMD_INIT2INIT_QPEE:\r
- return "TAVOR_IF_CMD_INIT2INIT_QPEE";\r
- break;\r
- default:\r
- return "[UNKNOWN_COMMAND]";\r
- }\r
-}\r
-\r
-\r
-/*================ static functions definitions ====================================*/\r
-\r
-\r
-/*\r
- * cmd_invoke\r
- */\r
-THH_cmd_status_t cmd_invoke(THH_cmd_t cmd_if, command_fields_t *cmd_prms)\r
-{\r
- struct cmd_if_context_st *entry = (struct cmd_if_context_st *)cmd_if;\r
- THH_cmd_status_t rc;\r
-\r
- FUNC_IN;\r
-\r
- if ( entry->have_fatal && ((cmd_prms->input_modifier==0) || (cmd_prms->opcode!=TAVOR_IF_CMD_CLOSE_HCA)) ) {\r
- MT_RETURN(THH_CMD_STAT_EFATAL);\r
- }\r
-\r
- if ( !entry->sys_enabled ) {\r
- /* sys not enabled - we only allow sys enable cmd */\r
- if ( cmd_prms->opcode != TAVOR_IF_CMD_SYS_EN ) {\r
- MT_RETURN(THH_CMD_STAT_EAGAIN);\r
- }\r
- else {\r
- rc = sys_en_hca(entry);\r
- MT_RETURN(rc);\r
- }\r
- }\r
- else {\r
- /* system enabled */\r
- if ( cmd_prms->opcode == TAVOR_IF_CMD_SYS_EN ) {\r
- /* we don't allow re-invoking sys enable */\r
- MT_RETURN(THH_CMD_STAT_BAD_SYS_STATE);\r
- }\r
- else {\r
- rc = main_cmd_flow(entry, cmd_prms);\r
- if ( rc != THH_CMD_STAT_OK ) {\r
- MTL_ERROR1(MT_FLFMT("Failed command 0x%X (%s): status=0x%X (%s)\n"), \r
- cmd_prms->opcode, cmd_str(cmd_prms->opcode),rc,str_THH_cmd_status_t(rc));\r
- }\r
- MT_RETURN(rc);\r
- }\r
- }\r
-}\r
-\r
-\r
-/*\r
- * sys_en_hca\r
- */\r
-static THH_cmd_status_t sys_en_hca(struct cmd_if_context_st *entry)\r
-{\r
- u_int32_t token = 0, i, dw6;\r
- THH_cmd_status_t rc;\r
-\r
- FUNC_IN;\r
- MOSAL_mutex_acq_ui(&entry->sys_en_mtx);\r
- if ( entry->sys_enabled ) {\r
- MOSAL_mutex_rel(&entry->sys_en_mtx);\r
- MT_RETURN(THH_CMD_STAT_OK); /* already enabled */\r
- }\r
- if ( !cmdif_is_free(entry) ) {\r
- MOSAL_mutex_rel(&entry->sys_en_mtx);\r
- /* no need to call the hob at this early stage - just return THH_CMD_STAT_EFATAL */\r
- MT_RETURN(THH_CMD_STAT_EFATAL);\r
- }\r
-\r
- PREP_TOKEN_DW(token, DEFAULT_TOKEN);\r
-\r
- MOSAL_MMAP_IO_WRITE_DWORD((u_int8_t *)(entry->hcr_virt_base)+HCR_DW_BYTE_OFFSET(token), token);\r
-\r
- write_command_dw(&dw6, 1, 0, 0, TAVOR_IF_CMD_SYS_EN);\r
- MOSAL_MMAP_IO_WRITE_DWORD(((u_int32_t *)(entry->hcr_virt_base))+6, dw6);\r
- for ( i=0; i<(TAVOR_IF_CMD_ETIME_SYS_EN/10000); ++i ) {\r
- MOSAL_delay_execution(10000);\r
- if ( cmdif_is_free(entry) ) {\r
- MTL_TRACE1("command executed in %d mili seconds\n", i*10);\r
- break;\r
- }\r
- }\r
- if ( !cmdif_is_free(entry) ) {\r
- MOSAL_mutex_rel(&entry->sys_en_mtx);\r
- /* no need to call the hob at this early stage - just return THH_CMD_STAT_EFATAL */\r
- MT_RETURN(THH_CMD_STAT_ETIMEOUT);\r
- }\r
- rc = cmd_if_status(entry);\r
- if ( rc == THH_CMD_STAT_OK ) {\r
- entry->sys_enabled = TRUE;\r
- }\r
- MOSAL_mutex_rel(&entry->sys_en_mtx);\r
- MT_RETURN(rc);\r
-}\r
-\r
-\r
-/*\r
- * main_cmd_flow\r
- */\r
-static THH_cmd_status_t main_cmd_flow(struct cmd_if_context_st *entry, command_fields_t *cmd_prms)\r
-{\r
- THH_cmd_status_t rc;\r
-\r
- FUNC_IN;\r
- MOSAL_spinlock_lock(&entry->ctr_spl);\r
- if ( entry->eqn == THH_INVALID_EQN ) {\r
- /* events not enabled */\r
- entry->poll_in_pipe++;\r
- MOSAL_spinlock_unlock(&entry->ctr_spl);\r
- rc = cmd_flow_no_events(entry, cmd_prms);\r
- MOSAL_spinlock_lock(&entry->ctr_spl);\r
- entry->poll_in_pipe--;\r
- MOSAL_spinlock_unlock(&entry->ctr_spl);\r
- MT_RETURN(rc);\r
- }\r
- else {\r
- /* events are enabled */\r
- entry->events_in_pipe++;\r
- MOSAL_spinlock_unlock(&entry->ctr_spl);\r
- rc = cmd_flow_events(entry, cmd_prms);\r
- MOSAL_spinlock_lock(&entry->ctr_spl);\r
- entry->events_in_pipe--;\r
- MOSAL_spinlock_unlock(&entry->ctr_spl);\r
- MT_RETURN(rc);\r
- }\r
-}\r
-\r
-\r
-/*\r
- * cmdif_is_free\r
- */\r
-static MT_bool cmdif_is_free(struct cmd_if_context_st *entry)\r
-{\r
- u_int32_t val;\r
- volatile u_int32_t *offset = (volatile u_int32_t *)entry->hcr_virt_base, *ptr;\r
- MT_bool is_free;\r
-\r
- ptr = &offset[HCR_DW_BYTE_OFFSET(go)>>2];\r
- val = MOSAL_be32_to_cpu(MOSAL_MMAP_IO_READ_DWORD(ptr));\r
- is_free = !MT_EXTRACT32(val, HCR_DW_BIT_OFFSET(go), HCR_BIT_SIZE(go));\r
- return is_free;\r
-}\r
-\r
-\r
-/*\r
- * cleanup_cmdobj\r
- */\r
-static void cleanup_cmdobj(struct cmd_if_context_st *entry)\r
-{\r
- FUNC_IN;\r
- if ( entry->track_arr ) FREE(entry->track_arr);\r
- de_alloc_cmd_contexts(entry);\r
- if ( entry->hcr_virt_base ) MOSAL_io_unmap((MT_virt_addr_t)(entry->hcr_virt_base));\r
- if ( entry->uar0_virt_base) MOSAL_io_unmap((MT_virt_addr_t)(entry->uar0_virt_base));\r
- FREE(entry);\r
- MT_RETV;\r
-}\r
-\r
-\r
-\r
-\r
-\r
-/*\r
- * cmd_if_status\r
- */\r
-static inline THH_cmd_status_t cmd_if_status(struct cmd_if_context_st *entry)\r
-{\r
- u_int32_t *offset = (u_int32_t *)entry->hcr_virt_base;\r
- u_int32_t cmd;\r
-\r
- cmd = offset[HCR_DW_BYTE_OFFSET(status)>>2];\r
- cmd = MOSAL_be32_to_cpu(cmd);\r
- return (THH_cmd_status_t)MT_EXTRACT32(cmd, HCR_DW_BIT_OFFSET(status), HCR_BIT_SIZE(status));\r
-}\r
-\r
-\r
-/*\r
- * set_mailbox\r
- */\r
-static inline void set_mailbox(u_int32_t *dst_buf, MT_phys_addr_t mbx_pa)\r
-{\r
- addr_64bit_t addr;\r
-\r
- ptr_to_mailbox_ptr(mbx_pa, &addr);\r
- dst_buf[0] = addr.addr_h;\r
- dst_buf[1] = addr.addr_l;\r
-}\r
-\r
-\r
-/*\r
- * cvt_be32_to_cpu\r
- * size in bytes\r
- */\r
-static inline void cvt_be32_to_cpu(void *buf, u_int32_t size)\r
-{\r
- u_int32_t i, *p=(u_int32_t *)(buf);\r
- for ( i=0; i<(size>>2); ++i ) {\r
- *p = MOSAL_be32_to_cpu(*p);\r
- p++;\r
- }\r
-}\r
-\r
-\r
-/*\r
- * cvt_cpu_to_be32\r
- * size in bytes\r
- */\r
-static inline void cvt_cpu_to_be32(void *buf, u_int32_t size)\r
-{\r
- u_int32_t i, *p=(u_int32_t *)(buf);\r
- for ( i=0; i<(size>>2); ++i ) {\r
- *p = MOSAL_cpu_to_be32(*p);\r
- p++;\r
- }\r
-}\r
-\r
-\r
-/*\r
- * d32_to_s64\r
- */\r
-static inline u_int64_t d32_to_s64(u_int32_t hi, u_int32_t lo)\r
-{\r
- return(((u_int64_t)hi) << 32) | (u_int64_t)(lo);\r
-}\r
-\r
-\r
-/*\r
- *\r
- */\r
-#if 0\r
-static inline void prep_token_dw(u_int32_t *token_dw_p, u_int16_t val)\r
-{\r
- MT_INSERT32((*token_dw_p),(val),HCR_DW_BIT_OFFSET(token),MT_BIT_SIZE(tavorprm_hca_command_register_st,token));\r
- *token_dw_p = MOSAL_cpu_to_be32(*token_dw_p);\r
-}\r
-#endif\r
-\r
-/*\r
- * cmd_flow_events\r
- */\r
-static THH_cmd_status_t cmd_flow_events(struct cmd_if_context_st *entry, command_fields_t *cmd_prms)\r
-{\r
- THH_cmd_status_t ret=THH_CMD_STAT_EFATAL;\r
- int i;\r
-#ifdef MAX_DEBUG\r
- u_int64_t command_time; /* For sampling time command started */\r
-#endif\r
- u_int64_t start_time, busy_end_time, go_end_time;\r
- call_result_t rc;\r
- HH_ret_t rc1;\r
- cmd_ctx_t *ctx_p;\r
-\r
- FUNC_IN;\r
-\r
-\r
- MOSAL_sem_acq_ui(&entry->use_events_sem);\r
- if ( entry->have_fatal ) {\r
- ret = THH_CMD_STAT_EFATAL;\r
- goto ex_ues_rel;\r
- }\r
-\r
- MOSAL_sem_acq_ui(&entry->fw_outs_sem); /* released in THH_cmd_eventh */\r
- if ( entry->have_fatal ) {\r
- ret = THH_CMD_STAT_EFATAL;\r
- goto ex_fos_rel;\r
- }\r
-\r
-\r
- MOSAL_spinlock_dpc_lock(&entry->ctx_obj.spl);\r
- rc1 = acq_cmd_ctx(entry, &ctx_p);\r
- MOSAL_spinlock_unlock(&entry->ctx_obj.spl);\r
- if ( rc1 != HH_OK ) {\r
- MTL_ERROR1(MT_FLFMT("%s: failed to acquire context. this is fatal !!!"), __func__);\r
- THH_hob_fatal_error(entry->hob, THH_FATAL_NONE, VAPI_EV_SYNDROME_NONE);\r
- print_outs_commands(&entry->ctx_obj);\r
- print_track_arr(entry);\r
- ret = THH_CMD_STAT_EFATAL;\r
- goto ex_fos_rel;\r
- }\r
- MTL_DEBUG8(MT_FLFMT("token=0x%04x"), ctx_p->token);\r
- edit_hcr(entry, cmd_prms, ctx_p->token, ctx_p, 1);\r
-\r
- /* execute the command */\r
-#ifdef MAX_DEBUG\r
- command_time= MOSAL_get_time_counter();\r
-#endif\r
-\r
- MOSAL_syncobj_clear(&ctx_p->syncobj);\r
-\r
- MOSAL_mutex_acq_ui(&entry->hcr_mtx);\r
- if ( entry->have_fatal ) {\r
- ret = THH_CMD_STAT_EFATAL;\r
- goto ex_hm_rel;\r
-\r
- }\r
- if ( !entry->post_to_uar0 ) {\r
- /* check that the go bit is 0 */\r
- start_time = MOSAL_get_time_counter();\r
- busy_end_time = start_time + entry->counts_busy_wait_for_go;\r
- go_end_time = start_time + entry->counts_sleep_wait_for_go;\r
- while ( !cmdif_is_free(entry) ) {\r
- if ( MOSAL_get_time_counter() > busy_end_time ) {\r
- /* expired busy wait loop */\r
- if ( MOSAL_get_time_counter() > go_end_time ) {\r
- /* fatal condition detected */\r
-\r
- THH_hob_fatal_error(entry->hob, THH_FATAL_GOBIT, VAPI_EV_SYNDROME_NONE);\r
- MTL_ERROR1(MT_FLFMT("%s: go bit was not cleared for %d usec"), __func__, MAX_UC_SLEEP_FOR_GO);\r
- print_outs_commands(&entry->ctx_obj);\r
- print_track_arr(entry);\r
- ret = THH_CMD_STAT_EFATAL;\r
- goto ex_hm_rel;\r
- }\r
-\r
- /* we go to sleep for 1 os tick */\r
- MOSAL_usleep_ui(1000);\r
-\r
- /* in case of fatal state terminate the loop immediately */\r
- if ( entry->have_fatal ) {\r
- ret = THH_CMD_STAT_EFATAL;\r
- goto ex_hm_rel;\r
- }\r
-\r
- /* calculate short busy waits */\r
- busy_end_time = MOSAL_get_time_counter() + entry->short_wait_for_go;\r
- }\r
- }\r
- }\r
-\r
-\r
-#ifdef THH_CMD_TIME_TRACK\r
- MTL_ERROR1("CMD_TIME:START: cmd=%s token=0x%X time=["U64_FMT"]\n",\r
- cmd_str(cmd_prms->opcode), ctx_p->token, MOSAL_get_time_counter());\r
-#endif\r
- /* execute the command */\r
- if ( entry->post_to_uar0 ) {\r
- for ( i=0; i<4; ++i ) {\r
- MOSAL_MMAP_IO_WRITE_DWORD(((u_int32_t *)(entry->uar0_virt_base))+i, ctx_p->hcr_buf[i]);\r
- }\r
- for ( i=4; i<8; ++i ) {\r
- MOSAL_MMAP_IO_WRITE_DWORD(((u_int32_t *)(entry->uar0_virt_base))+i-4, ctx_p->hcr_buf[i]);\r
- }\r
- }\r
- else {\r
- for ( i=0; i<7; ++i ) {\r
- MOSAL_MMAP_IO_WRITE_DWORD(((u_int32_t *)(entry->hcr_virt_base))+i, ctx_p->hcr_buf[i]);\r
- }\r
- }\r
-\r
- track_exec_cmds(entry, ctx_p);\r
- MOSAL_mutex_rel(&entry->hcr_mtx);\r
-\r
- MTL_TRACE7(MT_FLFMT("using timeout %d usec (0 signifies inifinite !!!)"), entry->inf_timeout ? MOSAL_SYNC_TIMEOUT_INFINITE : cmd_prms->exec_time_micro);\r
- rc = MOSAL_syncobj_waiton_ui(&ctx_p->syncobj, entry->inf_timeout ? MOSAL_SYNC_TIMEOUT_INFINITE : cmd_prms->exec_time_micro);\r
- if ( entry->have_fatal ) {\r
- ret = THH_CMD_STAT_EFATAL;\r
- goto ex_ctx_rel;\r
- }\r
- switch ( rc ) {\r
- case MT_OK:\r
-\r
-#ifdef MAX_DEBUG\r
- { \r
- unsigned long counts_per_usec = ((unsigned long)MOSAL_get_counts_per_sec())/1000000;\r
- if (counts_per_usec == 0) counts_per_usec= 1;\r
- command_time= MOSAL_get_time_counter() - command_time;\r
- MTL_DEBUG4(MT_FLFMT("Command completed after approx. "U64_FMT" CPU clocks (~ %lu [usec])"),\r
- command_time,((unsigned long)command_time)/counts_per_usec); \r
- }\r
-#endif \r
- /* woke by event */\r
- break;\r
-\r
- case MT_ETIMEDOUT:\r
-#ifdef VXWORKS_OS\r
- Osa_TraceMe();\r
- Dump_Snapshot(); \r
-#endif\r
- break;\r
-\r
- default:\r
- MTL_ERROR1(MT_FLFMT("%s: unexpeted return code from MOSAL_syncobj_waiton: %s(%d)"),\r
- __func__, mtl_strerror_sym(rc), rc);\r
- } /* end of switch (rc) */\r
-\r
-\r
- if ( rc == MT_OK ) {\r
- ret = ctx_p->hcr.status;\r
- extract_hcr(cmd_prms, &ctx_p->hcr);\r
- }\r
- else {\r
- ret = rc==MT_ETIMEDOUT ? THH_CMD_STAT_ETIMEOUT : THH_CMD_STAT_EFATAL;\r
- /*\r
- I release this semaphore even though the event may eventually arrive and release this\r
- semaphore again but this is a fatal condition so it's ok\r
- */\r
- MOSAL_sem_rel(&entry->fw_outs_sem);\r
- dump_cmd_err_info(ctx_p, cmd_prms);\r
- THH_hob_fatal_error(entry->hob, THH_FATAL_CMD_TIMEOUT, VAPI_EV_SYNDROME_NONE);\r
- ret = THH_CMD_STAT_EFATAL;\r
- print_outs_commands(&entry->ctx_obj);\r
- print_track_arr(entry);\r
- goto ex_ctx_rel;\r
- }\r
-\r
-\r
-\r
- MOSAL_spinlock_dpc_lock(&entry->ctx_obj.spl);\r
- rel_cmd_ctx(entry, ctx_p);\r
- MOSAL_spinlock_unlock(&entry->ctx_obj.spl);\r
- MOSAL_sem_rel(&entry->use_events_sem);\r
-\r
- /* \r
- we moved this code from the if statement above because we shouldn't be holding a spinlock while\r
- we try to report errors (especially via something like printf)\r
- */\r
- \r
- if (MOSAL_EXPECT_FALSE(rc != MT_OK)) {\r
- MTL_ERROR1(MT_FLFMT("Command not completed after timeout: cmd=%s (0x%x), token=0x%04x, pid=%d, go=%d"),\r
- cmd_str(cmd_prms->opcode),cmd_prms->opcode, ctx_p->token, MOSAL_getpid(), \r
- cmdif_is_free(entry)==TRUE ? 0 : 1);\r
-\r
- } else {\r
- MTL_DEBUG8(MT_FLFMT("successful completion for token=0x%04x\n"), ctx_p->token);\r
- }\r
-\r
- /* check if we're in a fatal state */\r
- if ( entry->have_fatal ) { ret = THH_CMD_STAT_EFATAL; }\r
- goto ex_no_clean; /* normal function exit */\r
-\r
-\r
-ex_hm_rel:\r
- MOSAL_mutex_rel(&entry->hcr_mtx);\r
-ex_ctx_rel:\r
- MOSAL_spinlock_dpc_lock(&entry->ctx_obj.spl);\r
- rel_cmd_ctx(entry, ctx_p);\r
- MOSAL_spinlock_unlock(&entry->ctx_obj.spl);\r
-ex_fos_rel:\r
- MOSAL_sem_rel(&entry->fw_outs_sem);\r
-ex_ues_rel:\r
- MOSAL_sem_rel(&entry->use_events_sem);\r
-ex_no_clean:\r
- MT_RETURN(ret);\r
-}\r
-\r
-\r
-/*\r
- * cmd_flow_no_events\r
- */\r
-static THH_cmd_status_t cmd_flow_no_events(struct cmd_if_context_st *entry, command_fields_t *cmd_prms)\r
-{\r
- priv_hcr_t hcr;\r
- THH_cmd_status_t rc;\r
- u_int32_t i;\r
- HH_ret_t rc1;\r
- cmd_ctx_t *ctx_p;\r
-\r
- FUNC_IN;\r
-\r
- if ( entry->have_fatal && ((cmd_prms->input_modifier==0) || (cmd_prms->opcode!=TAVOR_IF_CMD_CLOSE_HCA)) ) {\r
- MT_RETURN(THH_CMD_STAT_EFATAL);\r
- }\r
-\r
- MOSAL_sem_acq_ui(&entry->no_events_sem);\r
- /* make sure go bit is cleared */\r
- if ( !cmdif_is_free(entry) ) {\r
- MTL_ERROR1(MT_FLFMT("%s: go bit is set"), __func__);\r
- MOSAL_sem_rel(&entry->no_events_sem);\r
- THH_hob_fatal_error(entry->hob, THH_FATAL_GOBIT, VAPI_EV_SYNDROME_NONE);\r
- MT_RETURN(THH_CMD_STAT_EFATAL);\r
- }\r
-\r
- MOSAL_spinlock_dpc_lock(&entry->ctx_obj.spl);\r
- rc1 = acq_cmd_ctx(entry, &ctx_p);\r
- MOSAL_spinlock_unlock(&entry->ctx_obj.spl);\r
- if ( rc1 != HH_OK ) {\r
- MOSAL_sem_rel(&entry->no_events_sem);\r
- MTL_ERROR1(MT_FLFMT("%s: acq_cmd_ctx failed"), __func__);\r
- MT_RETURN(THH_CMD_STAT_EFATAL); /* this is not EAGAIN since this thing must not happen */ \r
- }\r
-\r
- edit_hcr(entry, cmd_prms, DEFAULT_TOKEN, ctx_p, 0);\r
-\r
-\r
- /* execute the command */\r
- for ( i=0; i<7; ++i ) {\r
- MOSAL_MMAP_IO_WRITE_DWORD(((u_int32_t *)(entry->hcr_virt_base))+i, ctx_p->hcr_buf[i]);\r
- }\r
-\r
- if ( !entry->inf_timeout ) {\r
- i = cmd_prms->exec_time_micro/10000;\r
- }\r
- else {\r
- i = 0xffffffff; /* not matematically infinite but practically it's a long time */\r
- }\r
- if ( (cmd_prms->exec_time_micro>=LOOP_DELAY_TRESHOLD) || (entry->inf_timeout==TRUE) ) {\r
- for ( i=0; i<(cmd_prms->exec_time_micro/10000); ++i ) {\r
- MOSAL_usleep_ui(10000);\r
- if ( cmdif_is_free(entry) ) {\r
- if ( i>=1 ) {\r
- MTL_TRACE1("command executed in %d mili seconds\n", i*10);\r
- }\r
- else {\r
- MTL_TRACE1("command executed in less than 10 mili seconds\n");\r
- }\r
- break;\r
- }\r
- }\r
- }\r
- else {\r
- MOSAL_delay_execution(cmd_prms->exec_time_micro);\r
- }\r
-\r
-\r
- if ( !cmdif_is_free(entry) ) {\r
- MTL_TRACE1("command failed after %d msec\n", i*10);\r
- MOSAL_spinlock_dpc_lock(&entry->ctx_obj.spl);\r
- rel_cmd_ctx(entry, ctx_p);\r
- MOSAL_spinlock_unlock(&entry->ctx_obj.spl);\r
- MOSAL_sem_rel(&entry->no_events_sem);\r
- dump_cmd_err_info(ctx_p, cmd_prms);\r
- THH_hob_fatal_error(entry->hob, THH_FATAL_GOBIT, VAPI_EV_SYNDROME_NONE);\r
- MT_RETURN(THH_CMD_STAT_ETIMEOUT);\r
- }\r
-\r
- parse_HCR((u_int32_t*)entry->hcr_virt_base, &hcr);\r
- extract_hcr(cmd_prms, &hcr);\r
- MOSAL_spinlock_dpc_lock(&entry->ctx_obj.spl);\r
- rel_cmd_ctx(entry, ctx_p);\r
- MOSAL_spinlock_unlock(&entry->ctx_obj.spl);\r
-\r
-\r
- rc = cmd_if_status(entry);\r
- MOSAL_sem_rel(&entry->no_events_sem);\r
- MTL_DEBUG2("status=0x%08x\n", rc);\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * memcpy_to_tavor\r
- */\r
-static void *memcpy_to_tavor(void *dst, const void *src, MT_size_t size)\r
-{\r
- u_int32_t *dst32 = (u_int32_t *)dst;\r
- u_int32_t *src32 = (u_int32_t *)src;\r
- MT_size_t i;\r
-\r
- for ( i=0; i<(size>>2); ++i ) {\r
- dst32[i] = MOSAL_cpu_to_be32(src32[i]);\r
- }\r
- return dst;\r
-}\r
-\r
-\r
-/*\r
- * memcpy_from_tavor\r
- */\r
-static void *memcpy_from_tavor(void *dst, const void *src, MT_size_t size)\r
-{\r
- u_int32_t *dst32 = (u_int32_t *)dst;\r
- u_int32_t *src32 = (u_int32_t *)src;\r
- MT_size_t i;\r
-\r
- for ( i=0; i<(size>>2); ++i ) {\r
- dst32[i] = MOSAL_be32_to_cpu(src32[i]);\r
- }\r
- return dst;\r
-}\r
-\r
-/*====== parse input output mailbox structs ===============*/\r
-#if 0\r
-static void parse_QUERY_FW(void *buf, THH_fw_props_t *fw_props_p)\r
-{\r
- cvt_be32_to_cpu(buf, sizeof(struct tavorprm_query_fw_st)>>5);\r
- fw_props_p->fw_rev_major = MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_query_fw_st, fw_rev_major), MT_BIT_SIZE(tavorprm_query_fw_st, fw_rev_major));\r
- fw_props_p->fw_rev_minor = MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_query_fw_st, fw_rev_minor), MT_BIT_SIZE(tavorprm_query_fw_st, fw_rev_minor));\r
- fw_props_p->cmd_interface_rev = MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_query_fw_st, cmd_interface_rev), MT_BIT_SIZE(tavorprm_query_fw_st, cmd_interface_rev));\r
- fw_props_p->log_max_outstanding_cmd = MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_query_fw_st, log_max_outstanding_cmd), MT_BIT_SIZE(tavorprm_query_fw_st, log_max_outstanding_cmd));\r
- fw_props_p->fw_base_addr = d32_to_s64(MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_query_fw_st, fw_base_addr_h), MT_BIT_SIZE(tavorprm_query_fw_st, fw_base_addr_h)),\r
- MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_query_fw_st, fw_base_addr_l), MT_BIT_SIZE(tavorprm_query_fw_st, fw_base_addr_l)));\r
-\r
- fw_props_p->fw_end_addr = d32_to_s64(MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_query_fw_st, fw_end_addr_h), MT_BIT_SIZE(tavorprm_query_fw_st, fw_end_addr_h)),\r
- MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_query_fw_st, fw_end_addr_l), MT_BIT_SIZE(tavorprm_query_fw_st, fw_end_addr_l)));\r
-\r
-}\r
-#endif\r
-\r
-\r
-static void parse_HCR(u_int32_t *result_hcr_image_p, priv_hcr_t *hcr)\r
-{\r
- u_int32_t buf[sizeof(struct tavorprm_hca_command_register_st) >> 5];\r
-\r
- MOSAL_MMAP_IO_READ_BUF_DWORD(result_hcr_image_p,buf,sizeof(buf)>>2);\r
-\r
- cvt_be32_to_cpu(buf, sizeof(buf));\r
-\r
- /* in param */\r
- hcr->in_param[0] = MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_hca_command_register_st, in_param_h),\r
- MT_BIT_SIZE(tavorprm_hca_command_register_st, in_param_h));\r
- hcr->in_param[1] = MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_hca_command_register_st, in_param_l),\r
- MT_BIT_SIZE(tavorprm_hca_command_register_st, in_param_l));\r
-\r
- /* input modifier */\r
- hcr->input_modifier = MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_hca_command_register_st, input_modifier),\r
- MT_BIT_SIZE(tavorprm_hca_command_register_st, input_modifier));\r
-\r
- /* out param */\r
- hcr->out_param[0] = MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_hca_command_register_st, out_param_h),\r
- MT_BIT_SIZE(tavorprm_hca_command_register_st, out_param_h));\r
- hcr->out_param[1] = MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_hca_command_register_st, out_param_l),\r
- MT_BIT_SIZE(tavorprm_hca_command_register_st, out_param_l));\r
-\r
- /* token */\r
- hcr->token = MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_hca_command_register_st, token),\r
- MT_BIT_SIZE(tavorprm_hca_command_register_st, token));\r
-\r
- /* opcode */\r
- hcr->opcode = MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_hca_command_register_st, opcode),\r
- MT_BIT_SIZE(tavorprm_hca_command_register_st, opcode));\r
-\r
- /* opcode modifier */\r
- hcr->opcode_modifier = MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_hca_command_register_st, opcode_modifier),\r
- MT_BIT_SIZE(tavorprm_hca_command_register_st, opcode_modifier));\r
-\r
- /* e bit */\r
- hcr->e = MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_hca_command_register_st, e),\r
- MT_BIT_SIZE(tavorprm_hca_command_register_st, e));\r
-\r
- /* go bit */\r
- hcr->go = MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_hca_command_register_st, go),\r
- MT_BIT_SIZE(tavorprm_hca_command_register_st, go));\r
-\r
- /* status */\r
- hcr->status = MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_hca_command_register_st, status),\r
- MT_BIT_SIZE(tavorprm_hca_command_register_st, status));\r
-}\r
-\r
-#ifdef NEW_EQE_FORMAT\r
-static void parse_new_HCR(u_int32_t *result_hcr_image_p, priv_hcr_t *hcr)\r
-{\r
- u_int32_t buf[sizeof(struct tavorprm_hcr_completion_event_st) >> 5];\r
-\r
- /* we don't read the hardware so memcpy suffices */\r
- memcpy(buf, result_hcr_image_p, sizeof(buf));\r
-\r
- cvt_be32_to_cpu(buf, sizeof(buf));\r
-\r
- /* token */\r
- hcr->token = MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_hcr_completion_event_st, token),\r
- MT_BIT_SIZE(tavorprm_hcr_completion_event_st, token));\r
-\r
- /* status */\r
- hcr->status = MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_hcr_completion_event_st, status),\r
- MT_BIT_SIZE(tavorprm_hcr_completion_event_st, status));\r
-\r
- /* out param */\r
- hcr->out_param[0] = MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_hcr_completion_event_st, out_param_h),\r
- MT_BIT_SIZE(tavorprm_hcr_completion_event_st, out_param_h));\r
- hcr->out_param[1] = MT_EXTRACT_ARRAY32(buf, MT_BIT_OFFSET(tavorprm_hcr_completion_event_st, out_param_l),\r
- MT_BIT_SIZE(tavorprm_hcr_completion_event_st, out_param_l));\r
-}\r
-#endif\r
-\r
-\r
-/*\r
- * edit_hcr\r
- */\r
-static void edit_hcr(struct cmd_if_context_st *entry, command_fields_t *cmd_prms, u_int16_t token, cmd_ctx_t *ctx_p, int event)\r
-{\r
- u_int32_t _token = 0;\r
-\r
- switch ( cmd_prms->in_trans ) {\r
- case TRANS_NA:\r
- /* note! since these are zeroes I do not bother to deal with endianess */\r
- ctx_p->hcr_buf[0] = 0;\r
- ctx_p->hcr_buf[1] = 0;\r
- break;\r
- case TRANS_IMMEDIATE:\r
- {\r
- u_int32_t *caller_prms = (u_int32_t *)cmd_prms->in_param;\r
- ctx_p->hcr_buf[0] = MOSAL_cpu_to_be32(caller_prms[0]);\r
- ctx_p->hcr_buf[1] = MOSAL_cpu_to_be32(caller_prms[1]);\r
- }\r
- break;\r
- case TRANS_MAILBOX:\r
- /* convert the data pointed by in_prms from cpu to be */\r
- cmd_prms->in_param_va = (u_int8_t *)(ctx_p->in_prm.prm_base_va);\r
- memcpy_to_tavor((void *)ctx_p->in_prm.prm_base_va, cmd_prms->in_param, cmd_prms->in_param_size);\r
- set_mailbox(&ctx_p->hcr_buf[0], ctx_p->in_prm.prm_base_pa);\r
- break;\r
- }\r
-\r
- ctx_p->hcr_buf[2] = MOSAL_cpu_to_be32(cmd_prms->input_modifier);\r
-\r
- switch ( cmd_prms->out_trans ) {\r
- case TRANS_NA:\r
- /* note! since these are zeroes I do not bother to deal with endianess */\r
- ctx_p->hcr_buf[3] = 0; \r
- ctx_p->hcr_buf[4] = 0;\r
- break;\r
-\r
- case TRANS_IMMEDIATE:\r
- break;\r
- case TRANS_MAILBOX:\r
- cmd_prms->out_param_va = (u_int8_t *)ctx_p->out_prm.prm_base_va;\r
- set_mailbox(&ctx_p->hcr_buf[3], ctx_p->out_prm.prm_base_pa);\r
- break;\r
- }\r
-\r
- MT_INSERT32(_token, token, 16, 16);\r
- ctx_p->hcr_buf[5] = MOSAL_cpu_to_be32(_token);\r
-/*** warning C4242: 'function' : conversion from 'int' to 'u_int8_t', possible loss of data ***/\r
- write_command_dw(&ctx_p->hcr_buf[6], 1, (u_int8_t)event, cmd_prms->opcode_modifier, cmd_prms->opcode);\r
-}\r
-\r
-/*\r
- * extract_hcr\r
- */\r
-static void extract_hcr(command_fields_t *cmd_prms, priv_hcr_t *hcr)\r
-{\r
- switch ( cmd_prms->out_trans ) {\r
- case TRANS_NA:\r
- break;\r
- case TRANS_IMMEDIATE:\r
- {\r
- u_int32_t *caller_prms = (u_int32_t *)cmd_prms->out_param;\r
- caller_prms[0] = hcr->out_param[0];\r
- caller_prms[1] = hcr->out_param[1];\r
- }\r
- break;\r
- case TRANS_MAILBOX:\r
- MTL_DEBUG1("out is TRANS_MAILBOX\n");\r
- memcpy_from_tavor(cmd_prms->out_param, cmd_prms->out_param_va, cmd_prms->out_param_size);\r
- break;\r
- }\r
-}\r
-\r
-/*========== memory allocation functions ============================*/\r
-\r
-#if 0\r
-/*\r
- * print_hcr_dump\r
- */\r
-static void print_hcr_dump(struct cmd_if_context_st *entry, u_int32_t cmd)\r
-{\r
-#if 6 <= MAX_DEBUG\r
- u_int32_t i, hcr_size=PSEUDO_MT_BYTE_SIZE(tavorprm_hca_command_register_st);\r
- u_int8_t *hcr = (u_int8_t *)entry->hcr_virt_base;\r
-\r
- MTL_DEBUG6("hcr dump\n");\r
- for ( i=0; i<(hcr_size-4); ++i ) {\r
- MTL_DEBUG6("%02x\n", hcr[i]);\r
- }\r
- for ( i=0; i<4; ++i ) {\r
- MTL_DEBUG6("%02x\n", ((u_int8_t *)(&cmd))[i]);\r
- }\r
-#endif\r
-}\r
-\r
-\r
-/*\r
- * print_hcr_fileds\r
- */\r
-static void print_hcr_fileds(u_int32_t *buf, u_int32_t cmd)\r
-{\r
- u_int32_t i, hcr_size=PSEUDO_MT_BYTE_SIZE(tavorprm_hca_command_register_st);\r
- u_int32_t *hcr32 = buf;\r
- u_int32_t dst32[PSEUDO_MT_BYTE_SIZE(tavorprm_hca_command_register_st)>>2];\r
- u_int64_t in_prm, out_prm;\r
- u_int32_t in_mod;\r
- u_int16_t token, opcode, op_mod;\r
- u_int8_t e, go, status;\r
-\r
- for ( i=0; i<((hcr_size>>2)-1); ++i ) {\r
- dst32[i] = MOSAL_be32_to_cpu(hcr32[i]);\r
- }\r
- dst32[i] = MOSAL_be32_to_cpu(cmd);\r
-\r
- in_prm = ((u_int64_t)dst32[0]<<32) + dst32[1];\r
- in_mod = dst32[2];\r
- out_prm = ((u_int64_t)dst32[3]<<32) + dst32[4];\r
- token = MT_EXTRACT32(dst32[5], 16, 16);\r
- opcode = MT_EXTRACT32(dst32[6], 0, 12);\r
- op_mod = MT_EXTRACT32(dst32[6], 12, 4);\r
- e = MT_EXTRACT32(dst32[6], 22, 1);\r
- go = MT_EXTRACT32(dst32[6], 23, 1);\r
- status = MT_EXTRACT32(dst32[6], 24, 8);\r
-\r
- MTL_DEBUG5("hcr fields values\n");\r
- MTL_DEBUG5("in_param = "U64_FMT"\n", in_prm);\r
- MTL_DEBUG5("input_modifier = %x\n", in_mod);\r
- MTL_DEBUG5("out_param = "U64_FMT"\n", out_prm);\r
- MTL_DEBUG5("token = %x\n", token);\r
- MTL_DEBUG5("opcode = %x\n", opcode);\r
- MTL_DEBUG5("opcode modifier = %x\n", op_mod);\r
- MTL_DEBUG5("e = %d\n", e);\r
- MTL_DEBUG5("go = %d\n", go);\r
- MTL_DEBUG5("status = %x\n", status);\r
-}\r
-#endif\r
-\r
-/*\r
- * log2()\r
- */\r
-static int log2(u_int64_t arg)\r
-{\r
- int i;\r
- u_int64_t tmp;\r
-\r
- if ( arg == 0 ) {\r
-#ifndef __DARWIN__\r
- return INT_MIN; /* log2(0) = -infinity */\r
-#else\r
- return -1; /* 0.5 = 0 => log2(0) = -1 */\r
-#endif\r
- }\r
-\r
- tmp = 1;\r
- i = 0;\r
- while ( tmp < arg ) {\r
- tmp = tmp << 1;\r
- ++i;\r
- }\r
-\r
- return i;\r
-}\r
-\r
-\r
-\r
-/*\r
- * alloc_prm_ctx\r
- */\r
-static HH_ret_t alloc_prm_ctx(struct cmd_if_context_st *entry,\r
- prms_buf_t *prm_p,\r
- MT_size_t buf_sz,\r
- MT_bool in_ddr)\r
-{\r
- MT_phys_addr_t pa;\r
- MT_size_t alloc_sz;\r
- MT_virt_addr_t alloc_va, va;\r
- HH_ret_t rc;\r
- call_result_t mrc;\r
-\r
- if ( in_ddr ) {\r
- /* params put in ddr */\r
- alloc_sz = buf_sz;\r
- rc = THH_ddrmm_alloc(entry->ddrmm, alloc_sz, PRM_ALIGN_SHIFT, &pa);\r
- if ( rc != HH_OK ) {\r
- MTL_ERROR1(MT_FLFMT("%s: failed to allocate "SIZE_T_FMT" bytes in ddr"), __func__, alloc_sz);\r
- return rc;\r
- }\r
- va = MOSAL_io_remap(pa, alloc_sz);\r
- if ( !va ) {\r
- rc = THH_ddrmm_free(entry->ddrmm, pa, alloc_sz);\r
- if ( rc != HH_OK ) MTL_ERROR1(MT_FLFMT("%s: THH_ddrmm_free failed. pa=" PHYS_ADDR_FMT ", size=" SIZE_T_FMT), __func__, pa, alloc_sz);\r
- return HH_EAGAIN;\r
- }\r
- alloc_va = va;\r
- prm_p->in_ddr = TRUE;\r
- }\r
- else {\r
- /* params put in main memory */\r
- alloc_sz = buf_sz + (1<<PRM_ALIGN_SHIFT) - 1;\r
- alloc_va = (MT_virt_addr_t)MOSAL_pci_phys_alloc_consistent(alloc_sz, PRM_ALIGN_SHIFT);\r
- if ( !alloc_va ) {\r
- return HH_EAGAIN;\r
- }\r
- va = MT_UP_ALIGNX_VIRT(alloc_va, PRM_ALIGN_SHIFT);\r
- mrc = MOSAL_virt_to_phys(MOSAL_get_kernel_prot_ctx(), va, &pa);\r
- if ( mrc != MT_OK ) {\r
- MOSAL_pci_phys_free_consistent((void *)(MT_ulong_ptr_t)alloc_va, alloc_sz);\r
- return HH_ERR;\r
- }\r
- prm_p->in_ddr = FALSE;\r
- }\r
-\r
- prm_p->prm_alloc_va = alloc_va;\r
- prm_p->prm_base_va = va;\r
- prm_p->prm_base_pa = pa;\r
- prm_p->prm_buf_sz = alloc_sz;\r
- prm_p->allocated = 1;\r
-\r
- return HH_OK;\r
-}\r
-\r
-\r
-/*\r
- * de_alloc_prm_ctx\r
- */\r
-static HH_ret_t de_alloc_prm_ctx(struct cmd_if_context_st *entry,\r
- prms_buf_t *prms_p)\r
-{\r
- if ( prms_p->in_ddr ) {\r
- MOSAL_io_unmap(prms_p->prm_base_va);\r
- return THH_ddrmm_free(entry->ddrmm, prms_p->prm_base_pa, prms_p->prm_buf_sz);\r
- }\r
- else {\r
- MOSAL_pci_phys_free_consistent((void *)(MT_ulong_ptr_t)(prms_p->prm_alloc_va), prms_p->prm_buf_sz);\r
- return HH_OK;\r
- }\r
-}\r
-\r
-/*\r
- * alloc_cmd_contexts\r
- */\r
-static HH_ret_t alloc_cmd_contexts(struct cmd_if_context_st *entry, u_int32_t num, MT_bool in_at_ddr, MT_bool out_at_ddr)\r
-{\r
- cmd_ctx_t *ctx_p;\r
- HH_ret_t rc;\r
- u_int32_t i, j;\r
- \r
- ctx_p = TNMALLOC(cmd_ctx_t, num);\r
- if ( !ctx_p ) {\r
- MTL_ERROR1(MT_FLFMT("%s: failed to allocated "SIZE_T_FMT" bytes"), __func__, sizeof(cmd_ctx_t)*num);\r
- return HH_EAGAIN;\r
- }\r
- memset(ctx_p, 0, sizeof(cmd_ctx_t)*num);\r
- entry->ctx_obj.ctx_arr = ctx_p;\r
- entry->ctx_obj.num = num;\r
-\r
- for ( i=0; i<num; ++i ) {\r
-\r
- rc = alloc_prm_ctx(entry, &ctx_p[i].in_prm, MAX_IN_PRM_SIZE, in_at_ddr);\r
- if ( rc != HH_OK ) {\r
- MTL_ERROR1(MT_FLFMT("%s: alloc_prm_ctx failed"), __func__);\r
- for ( j=0; j<i; ++j ) {\r
- de_alloc_prm_ctx(entry, &entry->ctx_obj.ctx_arr[j].in_prm);\r
- de_alloc_prm_ctx(entry, &entry->ctx_obj.ctx_arr[j].out_prm);\r
- }\r
- return rc;\r
- }\r
-\r
- rc = alloc_prm_ctx(entry, &ctx_p[i].out_prm, MAX_OUT_PRM_SIZE, out_at_ddr);\r
- if ( rc != HH_OK ) {\r
- MTL_ERROR1(MT_FLFMT("%s: alloc_prm_ctx failed"), __func__);\r
- for ( j=0; j<i; ++j ) {\r
- de_alloc_prm_ctx(entry, &entry->ctx_obj.ctx_arr[j].in_prm);\r
- de_alloc_prm_ctx(entry, &entry->ctx_obj.ctx_arr[j].out_prm);\r
- }\r
- de_alloc_prm_ctx(entry, &entry->ctx_obj.ctx_arr[i].in_prm);\r
- return rc;\r
- }\r
-\r
- entry->ctx_obj.ctx_arr[i].ref_cnt = 0;\r
- entry->ctx_obj.ctx_arr[i].next_free_idx = i+1;\r
- entry->ctx_obj.ctx_arr[i].entry_idx = i;\r
-\r
- entry->ctx_obj.ctx_arr[i].token = 0;\r
- MOSAL_syncobj_init(&entry->ctx_obj.ctx_arr[i].syncobj);\r
- }\r
-\r
- entry->ctx_obj.ctx_arr[num-1].next_free_idx = FREE_LIST_EOL;\r
- entry->ctx_obj.free_list_head = 0;\r
-\r
- MOSAL_spinlock_init(&entry->ctx_obj.spl);\r
- return HH_OK;\r
-}\r
-\r
-\r
-/*\r
- * de_alloc_cmd_contexts\r
- */\r
-static HH_ret_t de_alloc_cmd_contexts(struct cmd_if_context_st *entry)\r
-{\r
- HH_ret_t rc, rcx=HH_OK;\r
- u_int32_t i;\r
-\r
- for ( i=0; i<entry->ctx_obj.num; ++i ) {\r
- if ( entry->ctx_obj.ctx_arr[i].in_prm.allocated ) {\r
- rc = de_alloc_prm_ctx(entry, &entry->ctx_obj.ctx_arr[i].in_prm);\r
- if ( rc != HH_OK ) {\r
- MTL_ERROR1(MT_FLFMT("%s: de_alloc_prm_ctx failed - %s"), __func__, HH_strerror(rc));\r
- rcx = HH_ERR;\r
- }\r
- }\r
-\r
- if ( entry->ctx_obj.ctx_arr[i].out_prm.allocated ) {\r
- rc = de_alloc_prm_ctx(entry, &entry->ctx_obj.ctx_arr[i].out_prm);\r
- if ( rc != HH_OK ) {\r
- MTL_ERROR1(MT_FLFMT("%s: de_alloc_prm_ctx failed - %s"), __func__, HH_strerror(rc));\r
- rcx = HH_ERR;\r
- }\r
- }\r
- }\r
- if ( entry->ctx_obj.ctx_arr ) {\r
- FREE(entry->ctx_obj.ctx_arr);\r
- entry->ctx_obj.ctx_arr = NULL;\r
- }\r
- return rcx;\r
-}\r
-\r
-static HH_ret_t acq_cmd_ctx(struct cmd_if_context_st *entry, cmd_ctx_t **ctx_pp)\r
-{\r
- u_int32_t last_head;\r
-\r
- if ( !entry->ctx_obj.ctx_arr ) {\r
- MTL_ERROR1(MT_FLFMT("%s: no resources were allocated"), __func__);\r
- return HH_EAGAIN;\r
- }\r
-\r
- if ( entry->ctx_obj.free_list_head != FREE_LIST_EOL ) {\r
- last_head = entry->ctx_obj.free_list_head;\r
- entry->ctx_obj.free_list_head = entry->ctx_obj.ctx_arr[last_head].next_free_idx;\r
- *ctx_pp = &entry->ctx_obj.ctx_arr[last_head];\r
- entry->ctx_obj.ctx_arr[last_head].token = (entry->tokens_counter<<entry->tokens_shift) | last_head;\r
- entry->tokens_counter++;\r
- entry->ctx_obj.ctx_arr[last_head].ref_cnt = 1;\r
- return HH_OK;\r
- }\r
-\r
- return HH_EAGAIN;\r
-}\r
-\r
-\r
-static void rel_cmd_ctx(struct cmd_if_context_st *entry, cmd_ctx_t *ctx_p)\r
-{\r
- u_int32_t entry_idx = ctx_p->entry_idx;\r
- u_int32_t old_head = entry->ctx_obj.free_list_head;\r
- entry->ctx_obj.free_list_head = entry_idx;\r
- ctx_p->next_free_idx = old_head;\r
- ctx_p->ref_cnt = 0;\r
-}\r
-\r
-\r
-\r
-static HH_ret_t re_alloc_resources(struct cmd_if_context_st *entry, MT_bool in_at_ddr, MT_bool out_at_ddr)\r
-{\r
- HH_ret_t rc;\r
-\r
- rc = de_alloc_cmd_contexts(entry);\r
- if ( rc != HH_OK ) {\r
- MTL_ERROR1(MT_FLFMT("%s: de_alloc_cmd_contexts failed - %s"), __func__, HH_strerror(rc));\r
- return rc;\r
- }\r
-\r
- rc = alloc_cmd_contexts(entry, entry->sw_num_rsc, in_at_ddr, out_at_ddr);\r
- if ( rc != HH_OK ) {\r
- MTL_ERROR1(MT_FLFMT("%s: alloc_cmd_contexts failed - %s"), __func__, HH_strerror(rc));\r
- return rc;\r
- }\r
-\r
- return HH_OK;\r
-}\r
-\r
-THH_cmd_status_t THH_cmd_notify_fatal(THH_cmd_t cmd_if, THH_fatal_err_t fatal_err)\r
-{\r
- struct cmd_if_context_st *entry = (struct cmd_if_context_st *)cmd_if;\r
- int i;\r
-\r
- FUNC_IN;\r
- MTL_DEBUG2("%s: cmd_if = %p\n", __func__, (void *) cmd_if);\r
- /* Don't need spinlock here. The value is set to TRUE and stays there until\r
- * cmdif is destroyed.\r
- */\r
- entry->have_fatal = TRUE;\r
-\r
- /* wake all processes waiting for completion of commands */\r
- MTL_DEBUG2(MT_FLFMT("%s: waking waiting processes"), __func__);\r
- MOSAL_spinlock_dpc_lock(&entry->ctx_obj.spl);\r
- for ( i=0; i<(int)entry->ctx_obj.num; ++i ) {\r
- MOSAL_syncobj_signal(&entry->ctx_obj.ctx_arr[i].syncobj);\r
- }\r
- MOSAL_spinlock_unlock(&entry->ctx_obj.spl);\r
- MTL_DEBUG2(MT_FLFMT("%s: woke waiting processes"), __func__);\r
-\r
-\r
- MT_RETURN(THH_CMD_STAT_OK);\r
-}\r
-\r
-THH_cmd_status_t THH_cmd_handle_fatal(THH_cmd_t cmd_if)\r
-{\r
- struct cmd_if_context_st *entry = (struct cmd_if_context_st *)cmd_if;\r
-\r
- FUNC_IN;\r
- MTL_DEBUG1(MT_FLFMT("%s: called"), __func__);\r
- /* Don't need spinlock here. */\r
- if (entry->have_fatal != TRUE) {\r
- MT_RETURN(THH_CMD_STAT_BAD_RES_STATE); /* only callable from within fatal state */\r
- }\r
- THH_cmd_clr_eq(cmd_if);\r
- MTL_DEBUG1(MT_FLFMT("%s: returning"), __func__);\r
- MT_RETURN(THH_CMD_STAT_OK);\r
-}\r
-\r
-\r
-\r
-\r
-/*\r
- * print_outs_commands\r
- */\r
-static void print_outs_commands(ctx_obj_t *ctxo_p)\r
-{\r
- u_int32_t i;\r
-\r
- MOSAL_spinlock_dpc_lock(&ctxo_p->spl);\r
- MTL_ERROR1(MT_FLFMT("list of outstanding tokens:"));\r
- for ( i=0; i<ctxo_p->num; ++i ) {\r
- if ( ctxo_p->ctx_arr[i].ref_cnt > 0 ) {\r
- MTL_ERROR1(MT_FLFMT("outstanding i=%d, token=0x%04x"), i, ctxo_p->ctx_arr[i].token);\r
- }\r
- }\r
-\r
- MOSAL_spinlock_unlock(&ctxo_p->spl);\r
-}\r
-\r
-\r
-static void track_exec_cmds(struct cmd_if_context_st *entry, cmd_ctx_t *ctx_p)\r
-{\r
- u_int16_t token=ctx_p->token;\r
- int idx = token & entry->tokens_idx_mask;\r
- entry->track_arr[idx] = token;\r
-}\r
-\r
-\r
-\r
-static void print_track_arr(struct cmd_if_context_st *entry)\r
-{\r
- int num=(1<<entry->tokens_shift), i, shift=entry->tokens_shift;\r
-\r
- for (i=0; i<num; ++i) {\r
- MTL_ERROR1(MT_FLFMT("%s: idx=%d, token=0x%04x, counter=%d"), __func__, i, entry->track_arr[i], entry->track_arr[i]>>shift);\r
- }\r
-}\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef __cmdif_h\r
-#define __cmdif_h\r
-\r
-#include <mtl_types.h>\r
-#include <hh.h>\r
-#include <cmd_types.h>\r
-#include <tavor_if_defs.h>\r
-\r
-/* #define SIMULATE_HALT_HCA 1 */\r
-\r
-#define THH_CMDIF_INVALID_HANDLE 0xFFFFFFFF\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_cmd_create\r
- *\r
- * Description: Create a THH_cmd object\r
- *\r
- * Parameters:\r
- * hw_ver(IN) hardware version\r
- * cr_base(IN) physical address of the cr-space\r
- * uar0_base(IN) base address of uar0 for posting commands\r
- * cmd_if_p(OUT) handle to create THH_cmd_t object\r
- * inf_timeout(IN) when TRUE the cmdif will wait infinitely for the completion of a command\r
- * num_cmds_outs(IN) number of commands in the air requested by the user (the real\r
- * value may be less depending on the value returned by FW)\r
- *\r
- * Returns:\r
- *\r
- *****************************************************************************/\r
-HH_ret_t THH_cmd_create(THH_hob_t hob, u_int32_t hw_ver, MT_phys_addr_t cr_base, MT_phys_addr_t uar0_base, THH_cmd_t *cmd_if_p,\r
- MT_bool inf_timeout, u_int32_t num_cmds_outs);\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_cmd_destroy\r
- *\r
- * Description: Destroy the THH_cmd object\r
- *\r
- * Parameters:\r
- * cmd_if(IN) handle of the THH_cmd_t object\r
- *\r
- * Returns:\r
- *\r
- *****************************************************************************/\r
-HH_ret_t THH_cmd_destroy(THH_cmd_t cmd_if);\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_cmd_set_fw_props\r
- *\r
- * Description: set params set by QUERY_FW command\r
- *\r
- * Parameters:\r
- * cmd_if(IN) handle of the THH_cmd_t object\r
- * fw_props_p(IN) pointer to queried fw props\r
- *\r
- * Returns:\r
- *\r
- *****************************************************************************/\r
-THH_cmd_status_t THH_cmd_set_fw_props(THH_cmd_t cmd_if, THH_fw_props_t *fw_props);\r
-\r
-/******************************************************************************\r
- * Function: THH_cmd_set_eq\r
- *\r
- * Description: Enable the command interfcae object to work with events\r
- *\r
- * Parameters:\r
- * cmd_if(IN) handle of the THH_cmd_t object\r
- *\r
- * Returns:\r
- *\r
- *****************************************************************************/\r
-HH_ret_t THH_cmd_set_eq(THH_cmd_t cmd_if);\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_cmd_clr_eq\r
- *\r
- * Description: inform the object to stop reporting completions to the EQ\r
- *\r
- * Parameters:\r
- * cmd_if(IN) handle of the THH_cmd_t object\r
- *\r
- * Returns:\r
- *\r
- *****************************************************************************/\r
-HH_ret_t THH_cmd_clr_eq(THH_cmd_t cmd_if);\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_cmd_eventh\r
- *\r
- * Description: This function is called whenever a command was completed (when\r
- * working with events)\r
- *\r
- * Parameters:\r
- * cmd_if(IN) handle of the THH_cmd_t object\r
- * result_hcr_image_p(IN) - the (big-endian) HCR image of the command completion EQE\r
- *\r
- * Returns:\r
- *\r
- *****************************************************************************/\r
-void THH_cmd_eventh(THH_cmd_t cmd_if, u_int32_t *result_hcr_image_p);\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_cmd_assign_ddrmm\r
- *\r
- * Description: Assign memory manager to be used by this object for allocating\r
- * memory frm DDR\r
- *\r
- * Parameters:\r
- * cmd_if(IN) handle of the THH_cmd_t object\r
- * ddrmm(IN) handle of assigned ddr memory manager\r
- *\r
- * Returns:\r
- *\r
- *****************************************************************************/\r
-HH_ret_t THH_cmd_assign_ddrmm(THH_cmd_t cmd_if, THH_ddrmm_t ddrmm);\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_cmd_revoke_ddrmm\r
- *\r
- * Description: revoke the associated memory manager\r
- *\r
- * Parameters:\r
- * cmd_if(IN) handle of the THH_cmd_t object\r
- *\r
- * Returns:\r
- *\r
- *****************************************************************************/\r
-HH_ret_t THH_cmd_revoke_ddrmm(THH_cmd_t cmd_if);\r
-\r
-\r
-/*****************************************************************************\r
-* *\r
-* COMMAND FUNCTIONS *\r
-* *\r
-******************************************************************************/\r
-\r
-/* System commands */\r
-THH_cmd_status_t THH_cmd_SYS_EN(IN THH_cmd_t cmd_if);\r
-THH_cmd_status_t THH_cmd_SYS_DIS(IN THH_cmd_t cmd_if);\r
-\r
-/* General queries */\r
-THH_cmd_status_t THH_cmd_QUERY_DEV_LIM(IN THH_cmd_t cmd_if, OUT THH_dev_lim_t *dev_lim);\r
-THH_cmd_status_t THH_cmd_QUERY_FW(IN THH_cmd_t cmd_if, OUT THH_fw_props_t *fw_props);\r
-THH_cmd_status_t THH_cmd_QUERY_DDR(IN THH_cmd_t cmd_if, OUT THH_ddr_props_t *ddr_props);\r
-THH_cmd_status_t THH_cmd_QUERY_ADAPTER(IN THH_cmd_t cmd_if, OUT THH_adapter_props_t *adapter_props);\r
-\r
-/* HCA initialization and maintenance commands */\r
-THH_cmd_status_t THH_cmd_INIT_HCA(IN THH_cmd_t cmd_if, IN THH_hca_props_t *hca_props);\r
-THH_cmd_status_t THH_cmd_INIT_IB(IN THH_cmd_t cmd_if, IN IB_port_t port,\r
- IN THH_port_init_props_t *port_init_props);\r
-THH_cmd_status_t THH_cmd_QUERY_HCA(IN THH_cmd_t cmd_if, OUT THH_hca_props_t *hca_props);\r
-THH_cmd_status_t THH_cmd_SET_IB(IN THH_cmd_t cmd_if, IN IB_port_t port,\r
- IN THH_set_ib_props_t *port_props);\r
-THH_cmd_status_t THH_cmd_CLOSE_IB(IN THH_cmd_t cmd_if, IN IB_port_t port);\r
-#ifdef SIMULATE_HALT_HCA\r
-THH_cmd_status_t THH_cmd_CLOSE_HCA(IN THH_cmd_t cmd_if);\r
-#else\r
-THH_cmd_status_t THH_cmd_CLOSE_HCA(IN THH_cmd_t cmd_if, MT_bool do_halt);\r
-#endif\r
-/* TPT commands */\r
-THH_cmd_status_t THH_cmd_SW2HW_MPT(IN THH_cmd_t cmd_if, IN THH_mpt_index_t mpt_index,\r
- IN THH_mpt_entry_t *mpt_entry);\r
-THH_cmd_status_t THH_cmd_MODIFY_MPT(IN THH_cmd_t cmd_if, IN THH_mpt_index_t mpt_index,\r
- IN THH_mpt_entry_t *mpt_entry, MT_bool modify_entire_entry);\r
-THH_cmd_status_t THH_cmd_QUERY_MPT(IN THH_cmd_t cmd_if, IN THH_mpt_index_t mpt_index,\r
- OUT THH_mpt_entry_t *mpt_entry);\r
-THH_cmd_status_t THH_cmd_HW2SW_MPT(IN THH_cmd_t cmd_if, IN THH_mpt_index_t mpt_index,\r
- OUT THH_mpt_entry_t *mpt_entry);\r
-THH_cmd_status_t THH_cmd_READ_MTT(IN THH_cmd_t cmd_if, IN u_int64_t mtt_pa, IN MT_size_t num_elems,\r
- OUT THH_mtt_entry_t *mtt_entry);\r
-THH_cmd_status_t THH_cmd_WRITE_MTT(IN THH_cmd_t cmd_if, IN u_int64_t mtt_pa, IN MT_size_t num_elems,\r
- IN THH_mtt_entry_t *mtt_entry);\r
-THH_cmd_status_t THH_cmd_SYNC_TPT(IN THH_cmd_t cmd_if);\r
-\r
-/* EQ commands */\r
-THH_cmd_status_t THH_cmd_MAP_EQ(IN THH_cmd_t cmd_if, IN THH_eqn_t eqn, IN u_int64_t event_mask);\r
-THH_cmd_status_t THH_cmd_SW2HW_EQ(IN THH_cmd_t cmd_if, IN THH_eqn_t eqn, IN THH_eqc_t *eq_context);\r
-THH_cmd_status_t THH_cmd_HW2SW_EQ(IN THH_cmd_t cmd_if, IN THH_eqn_t eqn, OUT THH_eqc_t *eq_context);\r
-THH_cmd_status_t THH_cmd_QUERY_EQ(IN THH_cmd_t cmd_if, IN THH_eqn_t eqn, OUT THH_eqc_t *eq_context);\r
-\r
-\r
-/* CQ commands */\r
-THH_cmd_status_t THH_cmd_SW2HW_CQ(IN THH_cmd_t cmd_if, IN HH_cq_hndl_t cqn,\r
- IN THH_cqc_t *cq_context);\r
-THH_cmd_status_t THH_cmd_HW2SW_CQ(IN THH_cmd_t cmd_if, IN HH_cq_hndl_t cqn,\r
- OUT THH_cqc_t *cq_context);\r
-THH_cmd_status_t THH_cmd_QUERY_CQ(IN THH_cmd_t cmd_if, IN HH_cq_hndl_t cqn,\r
- IN THH_cqc_t *cq_context);\r
-THH_cmd_status_t THH_cmd_RESIZE_CQ(THH_cmd_t cmd_if, HH_cq_hndl_t cqn, \r
- u_int64_t start_address, u_int32_t l_key, u_int8_t log_cq_size,\r
- u_int32_t *new_producer_index_p);\r
-/* if given new_producer_index_p==NULL then opcode_modifier=1 (fixed resize CQ - FM issue #17002) */\r
-\r
-/* QP/EE commands */\r
-THH_cmd_status_t THH_cmd_MODIFY_QP(IN THH_cmd_t cmd_if, IN IB_wqpn_t qpn,\r
- IN THH_qpee_transition_t trans,\r
- IN THH_qpee_context_t *qp_context,\r
- IN u_int32_t optparammask);\r
-THH_cmd_status_t THH_cmd_MODIFY_EE(IN THH_cmd_t cmd_if, IN IB_eecn_t eecn,\r
- IN THH_qpee_transition_t trans,\r
- IN THH_qpee_context_t *ee_context,\r
- IN u_int32_t optparammask);\r
-THH_cmd_status_t THH_cmd_QUERY_QP(IN THH_cmd_t cmd_if, IN IB_wqpn_t qpn,\r
- OUT THH_qpee_context_t *qp_context);\r
-THH_cmd_status_t THH_cmd_QUERY_EE(IN THH_cmd_t cmd_if, IN IB_eecn_t eecn,\r
- OUT THH_qpee_context_t *ee_context);\r
-#if defined(MT_SUSPEND_QP)\r
-THH_cmd_status_t THH_cmd_SUSPEND_QP(THH_cmd_t cmd_if, u_int32_t qpn, MT_bool suspend_flag);\r
-#endif\r
-\r
-/* Special QP commands */\r
-THH_cmd_status_t THH_cmd_CONF_SPECIAL_QP(IN THH_cmd_t cmd_if, IN VAPI_special_qp_t qp_type,\r
- IN IB_wqpn_t base_qpn);\r
-THH_cmd_status_t THH_cmd_MAD_IFC(IN THH_cmd_t cmd_if, \r
- IN MT_bool mkey_validate, \r
- IN IB_lid_t slid, /* SLID is ignored if mkey_validate is false */\r
- IN IB_port_t port,\r
- IN void *mad_in, \r
- OUT void *mad_out);\r
-\r
-/* SRQ commands */\r
-\r
-THH_cmd_status_t THH_cmd_SW2HW_SRQ(IN THH_cmd_t cmd_if,\r
- IN u_int32_t srqn, /* SRQ number/index */\r
- IN THH_srq_context_t *srqc_p);/* SRQ context */\r
-\r
-THH_cmd_status_t THH_cmd_HW2SW_SRQ(IN THH_cmd_t cmd_if,\r
- IN u_int32_t srqn, /* SRQ number/index */\r
- OUT THH_srq_context_t *srqc_p);/* SRQ context (NULL for no output)*/\r
-\r
-THH_cmd_status_t THH_cmd_QUERY_SRQ(IN THH_cmd_t cmd_if,\r
- IN u_int32_t srqn, /* SRQ number/index */\r
- OUT THH_srq_context_t *srqc_p);/* SRQ context */\r
-\r
-/* Multicast groups commands */\r
-THH_cmd_status_t THH_cmd_READ_MGM(IN THH_cmd_t cmd_if, IN u_int32_t mcg_index,\r
- IN MT_size_t max_qp_per_mcg, OUT THH_mcg_entry_t *mcg_entry);\r
-THH_cmd_status_t THH_cmd_WRITE_MGM(IN THH_cmd_t cmd_if, IN u_int32_t mcg_index,\r
- IN MT_size_t max_qp_per_mcg, IN THH_mcg_entry_t *mcg_entry);\r
-THH_cmd_status_t THH_cmd_MGID_HASH(IN THH_cmd_t cmd_if, IN IB_gid_t mgid, OUT THH_mcg_hash_t *hash_val);\r
-\r
-/* fatal error notification */\r
-THH_cmd_status_t THH_cmd_notify_fatal(IN THH_cmd_t cmd_if, IN THH_fatal_err_t fatal_err);\r
-THH_cmd_status_t THH_cmd_handle_fatal(IN THH_cmd_t cmd_if);\r
-\r
-const char *str_THH_cmd_status_t(THH_cmd_status_t status);\r
-const char *cmd_str(tavor_if_cmd_t opcode);\r
-\r
-#endif /* __cmdif_h */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef __cmdif_priv_h\r
-#define __cmdif_priv_h\r
-\r
-#include <mtl_types.h>\r
-#include <mosal.h>\r
-#include <MT23108.h>\r
-#include <cmd_types.h>\r
-#include <thh.h>\r
-#include <thh_hob.h>\r
-\r
-#define PSEUDO_MT_BYTE_SIZE(x) (sizeof(struct x) >> 3)\r
-\r
-\r
-typedef struct {\r
- u_int32_t in_param[2]; /* Input Parameter: 64 bit parameter or 64 bit pointer to input mailbox (see command description) */\r
- u_int32_t input_modifier;/* Input Parameter Modifier */\r
- u_int32_t out_param[2]; /* Output Parameter: 64 bit parameter or 64 bit pointer to output mailbox (see command description) */\r
- u_int16_t token; /* Software assigned token to the command, to uniquely identify it. The token is returned to the software in the EQE reported. */\r
- u_int16_t opcode; /* Command opcode */\r
- u_int8_t opcode_modifier;/* Opcode Modifier, see specific description for each command. */\r
- u_int8_t e; /* Event Request\;0 - Don't report event (software will poll the G bit)\;1 - Report event to EQ when the command completes */\r
- u_int8_t go; /* Go (0=Software ownership for the HCR, 1=Hardware ownership for the HCR)\;Software can write to the HCR only if Go bit is cleared.\;Software must set the Go bit to trigger the HW to execute the command. Software must not write to this register value other than 1 for the Go bit. */\r
- u_int8_t status; /* Command execution status report. Valid only if command interface in under SW ownership (Go bit is cleared)\;0 - command completed without error. If different than zero, command execution completed with error. Syndrom encoding is depended on command executed and is defined for each command */\r
-}\r
-priv_hcr_t;\r
-\r
-typedef struct {\r
- MOSAL_syncobj_t *syncobj_p; /* pointer to synchronization object */\r
- u_int16_t token_val; /* the value of the token */\r
- priv_hcr_t hcr;\r
- MT_bool in_use; /* free if 0, otherwise used */\r
- MT_bool signalled;\r
-}\r
-wait_context_t;\r
-\r
-\r
-typedef enum {\r
- TRANS_NA,\r
- TRANS_IMMEDIATE,\r
- TRANS_MAILBOX\r
-}\r
-trans_type_t;\r
-\r
-typedef struct {\r
- u_int8_t *in_param; /* holds the virtually contigious buffer of the parameter block passed */\r
- u_int8_t *in_param_va; /* used internaly to hold the address of the allocated physical contigious buffer\r
- - no need to initialize by the wrapper */ \r
- u_int32_t in_param_size;\r
- trans_type_t in_trans;\r
-\r
- u_int32_t input_modifier;\r
-\r
- u_int8_t *out_param; /* holds the virtually contigious buffer of the parameter block passed */\r
- u_int8_t *out_param_va; /* used internaly to hold the address of the allocated physical contigious buffer\r
- - no need to initialize by the wrapper */ \r
- u_int32_t out_param_size;\r
- trans_type_t out_trans;\r
-\r
- tavor_if_cmd_t opcode;\r
- u_int8_t opcode_modifier;\r
-\r
- u_int32_t exec_time_micro;\r
-}\r
-command_fields_t;\r
-\r
-\r
-typedef struct {\r
- MT_virt_addr_t wide_pool; /* pointer to base address of the pool, which is not aligned */\r
- MT_virt_addr_t pool; /* pointer to start address of the pool - this address is aligned */\r
- MT_phys_addr_t pool_pa; /* physical address of the pool */\r
- u_int32_t num_bufs; /* number of buffers in the pool */\r
- MT_size_t buf_size; /* size of a buffer in the pool */\r
- void **buf_ptrs; /* array holding pointers to the buffers in the pool */\r
-}\r
-pool_control_t;\r
-\r
-#define TOKEN_VALUES_BASE (1+0) /* the '1' must be there to ensure the value of UNALLOCATED_TOKEN is valid */\r
-#define UNALLOCATED_TOKEN 0\r
-#define MAX_IN_PRM_SIZE 0x400 /* is this the right value ?? */\r
-#define MAX_OUT_PRM_SIZE 0x400 /* is this the right value ?? */\r
-#define LOOP_DELAY_TRESHOLD 10000 /* beyond 10 msec we make the deay in loop */\r
-\r
-/*================ type definitions ================================================*/\r
-\r
-typedef struct {\r
- MT_virt_addr_t prm_base_va; /* base virtual address of params buffer */\r
- MT_phys_addr_t prm_base_pa; /* base physical address of params buffer */\r
- MT_size_t prm_buf_sz; /* size of allocated buffer used for params */ \r
- MT_virt_addr_t prm_alloc_va; /* pointer to allocated buffer. useful when params\r
- are in main memory and due to alignment requirements\r
- prm_base_va may be higher then the allocated buffer\r
- pointer */\r
- MT_bool in_ddr; /* TRUE if prms are in ddr */\r
- int allocated; /* set to 1 when the object has been allocated to aid in cleanup */\r
-}\r
-prms_buf_t;\r
-\r
-#define HCR_SIZE 8\r
-/* type which contains all the resources used to execute a command */\r
-typedef struct {\r
- u_int16_t token; /* the value used in the token field */\r
- MOSAL_syncobj_t syncobj; /* pointer to synchronization object */\r
- prms_buf_t in_prm;\r
- prms_buf_t out_prm;\r
- u_int32_t ref_cnt; /* 0=entry not in use >0 in use */\r
- priv_hcr_t hcr; /* used to pass command results from event handler to the process */\r
- u_int32_t next_free_idx; /* indes of the next free element in the array */\r
- u_int32_t entry_idx; /* index of this entry in the array */\r
- u_int32_t hcr_buf[HCR_SIZE]; /* this buffer contains the image to be written to uar0 */\r
-} \r
-cmd_ctx_t;\r
-\r
-\r
-typedef struct {\r
- cmd_ctx_t *ctx_arr; /* pointer to an array of command contexts */\r
- u_int32_t num; /* number of aloocated contexts */\r
- MOSAL_spinlock_t spl; /* spinlock to protect the data */\r
- u_int32_t free_list_head;\r
-}\r
-ctx_obj_t;\r
-\r
-\r
-struct cmd_if_context_st {\r
- THH_hob_t hob;\r
- void *hcr_virt_base; /* virtual address base of the HCR */\r
- void *uar0_virt_base; /* virtual address base of the HCR */\r
- MT_bool sys_enabled; /* true if THH_CMD_SYS_EN has been executed successfully */\r
- volatile THH_eqn_t eqn; /* eqn used by this interface */\r
- MOSAL_spinlock_t eqn_spl;\r
- MOSAL_mutex_t sys_en_mtx; /* mutex used during execution of SYS_EN */\r
- MOSAL_semaphore_t no_events_sem; /* semaphore used during execution when EQN is not yet set */\r
- MOSAL_mutex_t hcr_mtx; /* mutex used to protect the hcr */\r
- MOSAL_semaphore_t use_events_sem; /* semaphore used while executing commands when EQN is set */\r
- MOSAL_semaphore_t fw_outs_sem;\r
-\r
- u_int32_t max_outstanding; /* max number of outstanding commands possible */\r
- u_int32_t queried_max_outstanding; /* max number of outstanding commands supported by FW */\r
- u_int32_t req_num_cmds_outs; /* requested number of outstanding commands */\r
-\r
- THH_ddrmm_t ddrmm; /* handle to ddr memory manager */\r
- pool_control_t in_prm_pool; /* used for managing memory for in params */\r
- MT_phys_addr_t phys_mem_addr; /* physical address allocated */\r
- MT_offset_t phys_mem_size; /* size of allocated physical memory */\r
-\r
- pool_control_t out_prm_pool; /* used for managing memory for out params */\r
-\r
- MT_phys_addr_t ddr_prms_buf; /* physical address in ddr to be used with input mailboxes */\r
-\r
- u_int8_t tokens_shift;\r
- u_int16_t tokens_idx_mask;\r
- u_int16_t tokens_counter;\r
-\r
- MT_bool inf_timeout; /* when TRUE cmdif will wait inifinitely for the completion of a command */\r
-\r
- MT_bool in_at_ddr, out_at_ddr; /* where are input and output params located */\r
-\r
- unsigned int sw_num_rsc; /* number pf software resources */\r
-\r
- ctx_obj_t ctx_obj; /* object that contains resources needed for executing commands */\r
- MT_bool query_fw_done; /* set to TRUE after the first time calling query FW and allocating resources */\r
- THH_fw_props_t fw_props; /* valid when query_fw_done is TRUE (after QUERY_FW) */\r
- u_int64_t counts_busy_wait_for_go; /* number of cpu clocks to busy wait for the go bit */\r
- u_int64_t short_wait_for_go; /* short busy wait for go */\r
- u_int64_t counts_sleep_wait_for_go; /* number of cpu clocks to wait for the go bit by suspending */\r
-\r
-#ifdef GO_MT_BIT_TIME_DEBUG\r
- u_int32_t go_wait_counts[sizeof(count_levels)/sizeof(u_int32_t)+1];\r
-#endif\r
- volatile MT_bool have_fatal; /* set if a fatal error has occurred */\r
- MOSAL_spinlock_t close_spl;\r
- MT_bool close_action;\r
- MOSAL_syncobj_t fatal_list; /* list of processes waiting untill HCA is closed */\r
-\r
- MT_bool post_to_uar0; /* when true cmds with events are posted like doorbels */\r
-\r
- MOSAL_spinlock_t ctr_spl;\r
- unsigned long events_in_pipe;\r
- unsigned long poll_in_pipe;\r
-\r
- u_int16_t *track_arr;\r
-};\r
-\r
-typedef struct {\r
- u_int32_t addr_h;\r
- u_int32_t addr_l;\r
-}\r
-addr_64bit_t;\r
-\r
-#define PRM_ALIGN_SHIFT 4 /* alignment required in params buffers */\r
-\r
-\r
-\r
-THH_cmd_status_t cmd_invoke(THH_cmd_t cmd_if, command_fields_t *cmd_prms);\r
-THH_cmd_status_t allocate_prm_resources(THH_cmd_t cmd_if, THH_fw_props_t *fw_props, MT_bool ddr);\r
-MT_bool valid_handle(THH_cmd_t cmd_if);\r
-void va_pa_mapping_helper(THH_cmd_t cmd_if, MT_virt_addr_t va, MT_phys_addr_t pa);\r
-\r
-\r
-/*================ external definitions ============================================*/\r
-#ifdef DEBUG_MEM_OV\r
-extern MT_phys_addr_t cmdif_dbg_ddr; /* address in ddr used for out params in debug mode */\r
-#endif\r
-\r
-#endif /* __cmdif_priv_h */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
- #include <cmdif.h>\r
- #include <cmd_types.h>\r
- #include <cmdif_priv.h>\r
- #include <sm_mad.h>\r
-\r
-/* T.D.(matan): change the method of reporting SQ_DRAINING state to a more cosisntent one.*/\r
-#define THH_CMD_QP_DRAINING_FLAG 0x80\r
-\r
-/* For the READ_MTT and WRITE_MTT, the mailbox contains a 16-byte preamble */\r
-#define MTT_CMD_PA_PREAMBLE_SIZE (16)\r
-\r
-#define EX_FLD(dst, a, st, fld) dst->fld = MT_EXTRACT_ARRAY32(a, MT_BIT_OFFSET(st, fld), MT_BIT_SIZE(st, fld))\r
-#define INS_FLD(src, a, st, fld) MT_INSERT_ARRAY32(a, src->fld, MT_BIT_OFFSET(st, fld), MT_BIT_SIZE(st, fld))\r
-\r
-#define EX_BOOL_FLD(dst, a, st, fld) dst->fld = ((MT_EXTRACT_ARRAY32(a, MT_BIT_OFFSET(st, fld), MT_BIT_SIZE(st, fld))==0) ? FALSE : TRUE)\r
-#define INS_BOOL_FLD(src, a, st, fld) MT_INSERT_ARRAY32(a, ((src->fld==FALSE)?0:1), MT_BIT_OFFSET(st, fld), MT_BIT_SIZE(st, fld))\r
-\r
-#define QP_EX_FLD(dst, a, st, fld) dst->fld = MT_EXTRACT_ARRAY32(a, MT_BIT_OFFSET(st, qpc_eec_data.fld), MT_BIT_SIZE(st, qpc_eec_data.fld))\r
-#define QP_INS_FLD(src, a, st, fld) MT_INSERT_ARRAY32(a, src->fld, MT_BIT_OFFSET(st, qpc_eec_data.fld), MT_BIT_SIZE(st, qpc_eec_data.fld))\r
-\r
-#define QP_EX_BOOL_FLD(dst, a, st, fld) dst->fld = ((MT_EXTRACT_ARRAY32(a, MT_BIT_OFFSET(st, qpc_eec_data.fld), MT_BIT_SIZE(st, qpc_eec_data.fld))==0) ? FALSE : TRUE)\r
-#define QP_INS_BOOL_FLD(src, a, st, fld) MT_INSERT_ARRAY32(a, ((src->fld==FALSE)?0:1), MT_BIT_OFFSET(st, qpc_eec_data.fld), MT_BIT_SIZE(st, qpc_eec_data.fld))\r
-\r
-#define EX_FLD64(dst, a, st, fld) dst->fld = (MT_EXTRACT_ARRAY32(a, MT_BIT_OFFSET(st, fld##_l), MT_BIT_SIZE(st, fld##_l)) | \\r
- (u_int64_t)(MT_EXTRACT_ARRAY32(a, MT_BIT_OFFSET(st, fld##_h), MT_BIT_SIZE(st, fld##_h))) << 32) \r
-\r
-#define INS_FLD64(src, a, st, fld) MT_INSERT_ARRAY32(a, (u_int32_t)src->fld, MT_BIT_OFFSET(st, fld##_l), MT_BIT_SIZE(st, fld##_l)) ; \\r
- MT_INSERT_ARRAY32(a, (u_int32_t)((src->fld) >> 32), MT_BIT_OFFSET(st, fld##_h), MT_BIT_SIZE(st, fld##_h))\r
-\r
-#define INS_FLD64_SH(src, a, st, fld) MT_INSERT_ARRAY32(a, (u_int32_t)((src->fld) >> (MT_BIT_OFFSET(st, fld##_l) & MASK32(5))), MT_BIT_OFFSET(st, fld##_l), MT_BIT_SIZE(st, fld##_l)) ; \\r
- MT_INSERT_ARRAY32(a, (u_int32_t)((src->fld) >> 32), MT_BIT_OFFSET(st, fld##_h), MT_BIT_SIZE(st, fld##_h))\r
-\r
-#define EX_FLD64_SH(dst, a, st, fld) dst->fld = ((MT_EXTRACT_ARRAY32(a, MT_BIT_OFFSET(st, fld##_l), MT_BIT_SIZE(st, fld##_l))) << ((MT_BIT_OFFSET(st, fld##_l)& MASK32(5))) | \\r
- (u_int64_t)(MT_EXTRACT_ARRAY32(a, MT_BIT_OFFSET(st, fld##_h), MT_BIT_SIZE(st, fld##_h))) << 32) \r
-\r
-#define QP_EX_FLD64(dst, a, st, fld) dst->fld = (MT_EXTRACT_ARRAY32(a, MT_BIT_OFFSET(st, qpc_eec_data.fld##_1), MT_BIT_SIZE(st, qpc_eec_data.fld##_1)) | \\r
- (u_int64_t)(MT_EXTRACT_ARRAY32(a, MT_BIT_OFFSET(st, qpc_eec_data.fld##_0), MT_BIT_SIZE(st, qpc_eec_data.fld##_0))) << 32) \r
-\r
-#define QP_INS_FLD64(src, a, st, fld) MT_INSERT_ARRAY32(a, (u_int32_t)src->fld, MT_BIT_OFFSET(st, qpc_eec_data.fld##_1), MT_BIT_SIZE(st, qpc_eec_data.fld##_1)) ; \\r
- MT_INSERT_ARRAY32(a, (u_int32_t)((src->fld) >> 32), MT_BIT_OFFSET(st, qpc_eec_data.fld##_0), MT_BIT_SIZE(st, qpc_eec_data.fld##_0))\r
-\r
-#define THH_CMDS_WRAP_DEBUG_LEVEL 4\r
-#define CMDS_DBG MTL_DEBUG4\r
-\r
-#if defined(MAX_DEBUG) && THH_CMDS_WRAP_DEBUG_LEVEL <= MAX_DEBUG\r
-#define THH_CMD_PRINT_DEV_LIMS(a) THH_cmd_print_dev_lims(a)\r
-#define THH_CMD_PRINT_HCA_PROPS(a) THH_cmd_print_hca_props(a)\r
-#define THH_CMD_PRINT_INIT_IB(a, b) THH_cmd_print_init_ib(a, b)\r
-#define THH_CMD_PRINT_QUERY_ADAPTER(a) THH_cmd_print_query_adapter(a)\r
-#define THH_CMD_PRINT_QUERY_DDR(a) THH_cmd_print_query_ddr(a)\r
-#define THH_CMD_PRINT_QUERY_FW(a) THH_cmd_print_query_fw(a)\r
-#define THH_CMD_PRINT_CQ_CONTEXT(a) THH_cmd_print_cq_context(a)\r
-#define THH_CMD_PRINT_QP_CONTEXT(a) THH_cmd_print_qp_context(a)\r
-#define THH_CMD_PRINT_EQ_CONTEXT(a) THH_cmd_print_eq_context(a)\r
-#define THH_CMD_PRINT_MPT_ENTRY(a) THH_cmd_print_mpt_entry(a)\r
-#define THH_CMD_PRINT_MTT_ENTRIES(a,b) THH_cmd_print_mtt_entries(a,b)\r
-#define THH_CMD_PRINT_MGM_ENTRY(a) THH_cmd_print_mgm_entry(a)\r
-#define THH_CMD_MAILBOX_PRINT(a,b,c) THH_cmd_mailbox_print(a,b,c)\r
-#else\r
-#define THH_CMD_PRINT_DEV_LIMS(a) \r
-#define THH_CMD_PRINT_HCA_PROPS(a) \r
-#define THH_CMD_PRINT_INIT_IB(a, b) \r
-#define THH_CMD_PRINT_QUERY_ADAPTER(a) \r
-#define THH_CMD_PRINT_QUERY_DDR(a) \r
-#define THH_CMD_PRINT_QUERY_FW(a) \r
-#define THH_CMD_PRINT_CQ_CONTEXT(a)\r
-#define THH_CMD_PRINT_QP_CONTEXT(a)\r
-#define THH_CMD_PRINT_EQ_CONTEXT(a)\r
-#define THH_CMD_PRINT_MPT_ENTRY(a)\r
-#define THH_CMD_PRINT_MTT_ENTRIES(a,b)\r
-#define THH_CMD_MAILBOX_PRINT(a,b,c) \r
-#define THH_CMD_PRINT_MGM_ENTRY(a)\r
-#endif\r
-\r
-/***************************************************** */\r
-/************** CMD INTERFACE UTILITIES ************* */\r
-/***************************************************** */\r
-static MT_bool THH_tavor_qpstate_2_vapi_qpstate(tavor_if_qp_state_t tavor_qp_state,\r
- VAPI_qp_state_t * vapi_qp_state)\r
-{\r
- switch(tavor_qp_state) {\r
- case TAVOR_IF_QP_STATE_RESET:\r
- *vapi_qp_state = VAPI_RESET;\r
- break;\r
-\r
- case TAVOR_IF_QP_STATE_INIT:\r
- *vapi_qp_state = VAPI_INIT;\r
- break;\r
-\r
- case TAVOR_IF_QP_STATE_RTR:\r
- *vapi_qp_state = VAPI_RTR;\r
- break;\r
-\r
- case TAVOR_IF_QP_STATE_RTS:\r
- *vapi_qp_state = VAPI_RTS;\r
- break;\r
-\r
- case TAVOR_IF_QP_STATE_SQER:\r
- *vapi_qp_state = VAPI_SQE;\r
- break;\r
-\r
- /* T.D.(matan): change this.*/\r
- case TAVOR_IF_QP_STATE_DRAINING:\r
- *vapi_qp_state = (VAPI_qp_state_t)(VAPI_SQD | THH_CMD_QP_DRAINING_FLAG);\r
- break;\r
- case TAVOR_IF_QP_STATE_SQD:\r
- *vapi_qp_state = VAPI_SQD;\r
- break;\r
-\r
- case TAVOR_IF_QP_STATE_ERR:\r
- *vapi_qp_state = VAPI_ERR;\r
- break;\r
- default:\r
- return FALSE;\r
- }\r
- return TRUE;\r
-}\r
-static MT_bool THH_vapi_qpstate_2_tavor_qpstate(VAPI_qp_state_t vapi_qp_state,\r
- tavor_if_qp_state_t *tavor_qp_state)\r
-{\r
- switch(vapi_qp_state) {\r
- case VAPI_RESET:\r
- *tavor_qp_state = TAVOR_IF_QP_STATE_RESET;\r
- break;\r
-\r
- case VAPI_INIT:\r
- *tavor_qp_state = TAVOR_IF_QP_STATE_INIT;\r
- break;\r
-\r
- case VAPI_RTR:\r
- *tavor_qp_state = TAVOR_IF_QP_STATE_RTR;\r
- break;\r
-\r
- case VAPI_RTS:\r
- *tavor_qp_state = TAVOR_IF_QP_STATE_RTS;\r
- break;\r
-\r
- case VAPI_SQE:\r
- *tavor_qp_state = TAVOR_IF_QP_STATE_SQER;\r
- break;\r
-\r
- case VAPI_SQD:\r
- *tavor_qp_state = TAVOR_IF_QP_STATE_SQD;\r
- break;\r
-\r
- case VAPI_ERR:\r
- *tavor_qp_state = TAVOR_IF_QP_STATE_ERR;\r
- break;\r
- default:\r
- return FALSE;\r
- }\r
- return TRUE;\r
-}\r
- \r
-\r
-/***************************************************** */\r
-/********** CMD INTERFACE PRINT UTILITIES **************/\r
-/***************************************************** */\r
-\r
-//--------------------------------------------------------------------------------------------------\r
-#if defined(MAX_DEBUG) && THH_CMDS_WRAP_DEBUG_LEVEL <= MAX_DEBUG\r
-\r
-static void THH_cmd_mailbox_print( void *mailbox, int size, const char * func )\r
-{\r
- int i, j, maxlines, bytes_left, this_line;\r
- char linebuf[200], tempout[20];\r
- u_int8_t *iterator;\r
-\r
- if (mailbox == NULL) return;\r
- \r
- iterator = (u_int8_t *)mailbox;\r
- bytes_left = size;\r
- return;\r
- MTL_DEBUG4("MailboxPrint from function %s, starting at addr 0x%p, size=%d:\n",\r
- func, mailbox, size);\r
- \r
- if (size <= 0) {\r
- return;\r
- }\r
-\r
- maxlines = (size / 16) + ((size % 16) ? 1 : 0);\r
-\r
- for (i = 0; i < maxlines; i++) {\r
- memset(linebuf, 0, sizeof(linebuf));\r
- this_line = (bytes_left > 16 ? 16 : bytes_left);\r
-\r
- for (j = 0; j < this_line; j++) {\r
- if ((j % 4) == 0) {\r
- strcat(linebuf," ");\r
- }\r
- sprintf(tempout, "%02x", *iterator);\r
- iterator++; bytes_left--;\r
- strcat(linebuf,tempout);\r
- }\r
- MTL_DEBUG4("%s\n", linebuf);\r
- }\r
- MTL_DEBUG3("MailboxPrint END\n");\r
-}\r
-\r
-\r
-/*\r
- * print_mtt_entries\r
- */\r
-static void THH_cmd_print_mtt_entries(u_int32_t elts_this_loop, void *inprm)\r
-{\r
- u_int32_t *p=(u_int32_t *)((u_int8_t *)inprm+MTT_CMD_PA_PREAMBLE_SIZE), i, \r
- *pp = (u_int32_t *)inprm;\r
- u_int64_t tag;\r
- int present;\r
- return;\r
- MTL_DEBUG1("mtt_pa = "U64_FMT"\n", (((u_int64_t)(*pp))<<32)+*(pp+1));\r
- for ( i=0; i<elts_this_loop; ++i ) {\r
- tag = ((((u_int64_t)(*p))<<32) + (*(p+1))) & MAKE_LONGLONG(0xfffffffffffff000);\r
- present = (*(p+1)) & 1;\r
- p+=2;\r
- MTL_DEBUG1("MTT entry: "U64_FMT", %s\n", tag, present ? "present" : "non present");\r
- }\r
-}\r
-\r
-void THH_cmd_print_hca_props(THH_hca_props_t *hca_props)\r
-{\r
- CMDS_DBG("HCA PROPS DUMP (THH_hca_props_t structure)\n");\r
-\r
- CMDS_DBG("hca_core_click = %d\n", hca_props->hca_core_clock);\r
-\r
- CMDS_DBG( "he (host endian) = %s\n", hca_props->he ? "Big Endian" : "Little Endian");\r
-\r
- CMDS_DBG( "re (Router Mode Enable) = %s\n", hca_props->re ? "TRUE" : "FALSE");\r
-\r
- CMDS_DBG( "router_qp = %s\n", hca_props->router_qp ? "TRUE" : "FALSE");\r
-\r
- CMDS_DBG( "ud (UD address vector protection) = %s\n", hca_props->ud ? "TRUE" : "FALSE");\r
- \r
- CMDS_DBG( "udp (UDP port check enabled) = %s\n", hca_props->udp ? "TRUE" : "FALSE");\r
- \r
- /* multicast parameters */\r
- CMDS_DBG( "\nmulticast_parameters.log_mc_table_entry_sz = %d\n", hca_props->multicast_parameters.log_mc_table_entry_sz);\r
- CMDS_DBG( "multicast_parameters.log_mc_table_sz = %d\n", hca_props->multicast_parameters.log_mc_table_sz);\r
- CMDS_DBG( "multicast_parameters.mc_base_addr = "U64_FMT"\n", hca_props->multicast_parameters.mc_base_addr);\r
- CMDS_DBG( "multicast_parameters.mc_hash_fn = %d\n", hca_props->multicast_parameters.mc_hash_fn);\r
- CMDS_DBG( "multicast_parameters.mc_table_hash_sz = %d\n", hca_props->multicast_parameters.mc_table_hash_sz);\r
-\r
- /* QP,EEC, EQC, RDB, CQC parameters */\r
- CMDS_DBG( "\nqpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr = "U64_FMT"\n", hca_props->qpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr);\r
- CMDS_DBG( "qpc_eec_cqc_eqc_rdb_parameters.eec_base_addr = "U64_FMT"\n", hca_props->qpc_eec_cqc_eqc_rdb_parameters.eec_base_addr);\r
- CMDS_DBG( "qpc_eec_cqc_eqc_rdb_parameters.eeec_base_addr = "U64_FMT"\n", hca_props->qpc_eec_cqc_eqc_rdb_parameters.eeec_base_addr);\r
- CMDS_DBG( "qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr = "U64_FMT"\n", hca_props->qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr);\r
- CMDS_DBG( "qpc_eec_cqc_eqc_rdb_parameters.eqpc_base_addr = "U64_FMT"\n", hca_props->qpc_eec_cqc_eqc_rdb_parameters.eqpc_base_addr);\r
- CMDS_DBG( "qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr = "U64_FMT"\n", hca_props->qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr);\r
- CMDS_DBG( "qpc_eec_cqc_eqc_rdb_parameters.rdb_base_addr = "U64_FMT"\n", hca_props->qpc_eec_cqc_eqc_rdb_parameters.rdb_base_addr);\r
- CMDS_DBG( "qpc_eec_cqc_eqc_rdb_parameters.log_num_eq = %d\n", hca_props->qpc_eec_cqc_eqc_rdb_parameters.log_num_eq);\r
- CMDS_DBG( "qpc_eec_cqc_eqc_rdb_parameters.log_num_of_cq = %d\n", hca_props->qpc_eec_cqc_eqc_rdb_parameters.log_num_of_cq);\r
- CMDS_DBG( "qpc_eec_cqc_eqc_rdb_parameters.log_num_of_ee = %d\n", hca_props->qpc_eec_cqc_eqc_rdb_parameters.log_num_of_ee);\r
- CMDS_DBG( "qpc_eec_cqc_eqc_rdb_parameters.log_num_of_qp = %d\n", hca_props->qpc_eec_cqc_eqc_rdb_parameters.log_num_of_qp);\r
-\r
- /* TPT parameters */\r
- CMDS_DBG( "\ntpt_parameters.mpt_base_adr = "U64_FMT"\n", hca_props->tpt_parameters.mpt_base_adr);\r
- CMDS_DBG( "tpt_parameters.mtt_base_adr = "U64_FMT"\n", hca_props->tpt_parameters.mtt_base_addr);\r
- CMDS_DBG( "tpt_parameters.log_mpt_sz = %d\n", hca_props->tpt_parameters.log_mpt_sz);\r
- CMDS_DBG( "tpt_parameters.mtt_segment_size = %d\n", hca_props->tpt_parameters.mtt_segment_size);\r
- CMDS_DBG( "tpt_parameters.mtt_version = %d\n", hca_props->tpt_parameters.mtt_version);\r
- CMDS_DBG( "tpt_parameters.pfto = %d\n", hca_props->tpt_parameters.pfto);\r
-\r
- /* UAR parameters */\r
- CMDS_DBG( "\nuar_parameters.uar_base_addr = "U64_FMT"\n", hca_props->uar_parameters.uar_base_addr);\r
- CMDS_DBG( "uar_parameters.uar_scratch_base_addr = "U64_FMT"\n", hca_props->uar_parameters.uar_scratch_base_addr);\r
- CMDS_DBG( "uar_parameters.uar_page_sz = %d\n", hca_props->uar_parameters.uar_page_sz);\r
-\r
- /* UDAV parameters */\r
- CMDS_DBG( "\nudavtable_memory_parameters.l_key = 0x%x\n", hca_props->udavtable_memory_parameters.l_key);\r
- CMDS_DBG( "udavtable_memory_parameters.pd = %d\n", hca_props->udavtable_memory_parameters.pd);\r
- CMDS_DBG( "udavtable_memory_parameters.xlation_en = %s\n", hca_props->udavtable_memory_parameters.xlation_en ? "TRUE" : "FALSE");\r
-}\r
-\r
-void THH_cmd_print_dev_lims(THH_dev_lim_t *dev_lim)\r
-{\r
- CMDS_DBG("QUERY DEV LIMS DUMP (THH_dev_lim_t structure)\n");\r
-\r
- CMDS_DBG( "dev_lim->apm (Automatic Path Migration) = %s\n", dev_lim->apm ? "TRUE" : "FALSE");\r
- CMDS_DBG( "dev_lim->atm (Atomic Operations) = %s\n", dev_lim->atm ? "TRUE" : "FALSE");\r
- CMDS_DBG( "dev_lim->avp (Address Vector port checking) = %s\n", dev_lim->avp ? "TRUE" : "FALSE");\r
- CMDS_DBG( "dev_lim->udm (UD Multicast support) = %s\n", dev_lim->udm ? "TRUE" : "FALSE");\r
- CMDS_DBG( "dev_lim->mw (Memory Windows) = %s\n", dev_lim->mw ? "TRUE" : "FALSE");\r
- CMDS_DBG( "dev_lim->pg (Paging on-demand) = %s\n", dev_lim->pg ? "TRUE" : "FALSE");\r
- CMDS_DBG( "dev_lim->pkv (PKey Violation Counter) = %s\n", dev_lim->pkv ? "TRUE" : "FALSE");\r
- CMDS_DBG( "dev_lim->pkv (PKey Violation Counter) = %s\n", dev_lim->pkv ? "TRUE" : "FALSE");\r
- CMDS_DBG( "dev_lim->qkv (QKey Violation Counter) = %s\n", dev_lim->qkv ? "TRUE" : "FALSE");\r
- CMDS_DBG( "dev_lim->r (Router Mode) = %s\n", dev_lim->r ? "TRUE" : "FALSE");\r
- CMDS_DBG( "dev_lim->raw_ether (Raw Ethernet mode) = %s\n", dev_lim->raw_ether ? "TRUE" : "FALSE");\r
- CMDS_DBG( "dev_lim->raw_ipv6 (Raw IpV6 mode) = %s\n", dev_lim->raw_ipv6 ? "TRUE" : "FALSE");\r
- CMDS_DBG( "dev_lim->rc (RC Transport) = %s\n", dev_lim->rc ? "TRUE" : "FALSE");\r
- CMDS_DBG( "dev_lim->rd (RD Transport) = %s\n", dev_lim->rd ? "TRUE" : "FALSE");\r
- CMDS_DBG( "dev_lim->uc (UC Transport) = %s\n", dev_lim->uc ? "TRUE" : "FALSE");\r
- CMDS_DBG( "dev_lim->ud (UD Transport) = %s\n", dev_lim->ud ? "TRUE" : "FALSE");\r
- CMDS_DBG( "dev_lim->rm (Raw Multicast) = %s\n", dev_lim->rm ? "TRUE" : "FALSE");\r
- /* multicast parameters */\r
- CMDS_DBG( "dev_lim->cqc_entry_sz = %d\n",dev_lim->cqc_entry_sz);\r
- CMDS_DBG( "dev_lim->eec_entry_sz = %d\n",dev_lim->eec_entry_sz);\r
- CMDS_DBG( "dev_lim->eeec_entry_sz = %d\n",dev_lim->eeec_entry_sz);\r
- CMDS_DBG( "dev_lim->eqc_entry_sz = %d\n",dev_lim->eqc_entry_sz);\r
- CMDS_DBG( "dev_lim->eqpc_entry_sz = %d\n",dev_lim->eqpc_entry_sz);\r
- CMDS_DBG( "dev_lim->log_max_cq_sz = %d\n",dev_lim->log_max_cq_sz);\r
- CMDS_DBG( "dev_lim->qpc_entry_sz = %d\n",dev_lim->qpc_entry_sz);\r
- CMDS_DBG( "dev_lim->max_uar_sz = %d\n",dev_lim->uar_sz);\r
- CMDS_DBG( "dev_lim->uar_scratch_entry_sz = %d\n",dev_lim->uar_scratch_entry_sz);\r
- CMDS_DBG( "dev_lim->log_max_av = %d\n",dev_lim->log_max_av);\r
- CMDS_DBG( "dev_lim->log_max_cq = %d\n",dev_lim->log_max_cq);\r
- CMDS_DBG( "dev_lim->log_max_cq_sz = %d\n",dev_lim->log_max_cq_sz);\r
- CMDS_DBG( "dev_lim->log_max_ee = %d\n",dev_lim->log_max_ee);\r
- CMDS_DBG( "dev_lim->log_max_eq = %d\n",dev_lim->log_max_eq);\r
- CMDS_DBG( "dev_lim->log_max_gid = %d\n",dev_lim->log_max_gid);\r
- CMDS_DBG( "dev_lim->log_max_mcg = %d\n",dev_lim->log_max_mcg);\r
- CMDS_DBG( "dev_lim->log_max_mpts = %d\n",dev_lim->log_max_mpts);\r
- CMDS_DBG( "dev_lim->log_max_mtt_seg = %d\n",dev_lim->log_max_mtt_seg);\r
- CMDS_DBG( "dev_lim->log_max_mrw_sz = %d\n",dev_lim->log_max_mrw_sz);\r
- CMDS_DBG( "dev_lim->log_max_pd = %d\n",dev_lim->log_max_pd);\r
- CMDS_DBG( "dev_lim->log_max_pkey = %d\n",dev_lim->log_max_pkey);\r
- CMDS_DBG( "dev_lim->log_max_qp = %d\n",dev_lim->log_max_qp);\r
- CMDS_DBG( "dev_lim->log_max_qp_mcg = %d\n",dev_lim->log_max_qp_mcg);\r
- CMDS_DBG( "dev_lim->log_max_qp_sz = %d\n",dev_lim->log_max_qp_sz);\r
- CMDS_DBG( "dev_lim->log_max_ra_req_qp = %d\n",dev_lim->log_max_ra_req_qp);\r
- CMDS_DBG( "dev_lim->log_max_ra_res_qp = %d\n",dev_lim->log_max_ra_res_qp);\r
- CMDS_DBG( "dev_lim->log_max_ra_res_global = %d\n",dev_lim->log_max_ra_res_global);\r
- CMDS_DBG( "dev_lim->log_max_rdds = %d\n",dev_lim->log_max_rdds);\r
- CMDS_DBG( "dev_lim->log_pg_sz = %d\n",dev_lim->log_pg_sz);\r
- CMDS_DBG( "dev_lim->max_desc_sz = %d\n",dev_lim->max_desc_sz);\r
- CMDS_DBG( "dev_lim->max_mtu = %d\n",dev_lim->max_mtu);\r
- CMDS_DBG( "dev_lim->max_port_width = %d\n",dev_lim->max_port_width);\r
- CMDS_DBG( "dev_lim->max_sg = %d\n",dev_lim->max_sg);\r
- CMDS_DBG( "dev_lim->max_vl = %d\n",dev_lim->max_vl);\r
- CMDS_DBG( "dev_lim->num_ports = %d\n",dev_lim->num_ports);\r
- CMDS_DBG( "dev_lim->log2_rsvd_qps = %d\n",dev_lim->log2_rsvd_qps);\r
- CMDS_DBG( "dev_lim->log2_rsvd_ees = %d\n",dev_lim->log2_rsvd_ees);\r
- CMDS_DBG( "dev_lim->log2_rsvd_cqs = %d\n",dev_lim->log2_rsvd_cqs);\r
- CMDS_DBG( "dev_lim->num_rsvd_eqs = %d\n",dev_lim->num_rsvd_eqs);\r
- CMDS_DBG( "dev_lim->log2_rsvd_mrws = %d\n",dev_lim->log2_rsvd_mrws);\r
- CMDS_DBG( "dev_lim->log2_rsvd_mtts = %d\n",dev_lim->log2_rsvd_mtts);\r
- CMDS_DBG( "dev_lim->num_rsvd_uars = %d\n",dev_lim->num_rsvd_uars);\r
- CMDS_DBG( "dev_lim->num_rsvd_rdds = %d\n",dev_lim->num_rsvd_rdds);\r
- CMDS_DBG( "dev_lim->num_rsvd_pds = %d\n",dev_lim->num_rsvd_pds);\r
- CMDS_DBG( "dev_lim->local_ca_ack_delay = %d\n",dev_lim->local_ca_ack_delay);\r
-}\r
-\r
-void THH_cmd_print_query_fw(THH_fw_props_t *fw_props)\r
-{\r
- CMDS_DBG("QUERY FW DUMP (THH_fw_props_t structure)\n");\r
- CMDS_DBG( "fw_props->cmd_interface_rev = 0x%x\n", fw_props->cmd_interface_rev);\r
- CMDS_DBG( "fw_props->fw_rev_major = 0x%x\n", fw_props->fw_rev_major);\r
- CMDS_DBG( "fw_props->fw_rev_minor = 0x%x\n", fw_props->fw_rev_minor);\r
- CMDS_DBG( "fw_props->fw_rev_subminor = 0x%x\n", fw_props->fw_rev_subminor);\r
- CMDS_DBG( "fw_props->fw_base_addr = "U64_FMT"\n", fw_props->fw_base_addr);\r
- CMDS_DBG( "fw_props->fw_end_addr = "U64_FMT"\n", fw_props->fw_end_addr);\r
- CMDS_DBG( "fw_props->error_buf_start = "U64_FMT"\n", fw_props->error_buf_start);\r
- CMDS_DBG( "fw_props->error_buf_size = %d\n", fw_props->error_buf_size);\r
-}\r
-\r
-void THH_cmd_print_query_adapter( THH_adapter_props_t *adapter_props)\r
-{\r
- CMDS_DBG("QUERY ADAPTER DUMP (THH_adapter_props_t structure)\n");\r
- CMDS_DBG( "adapter_props->device_id = %d\n", adapter_props->device_id);\r
- CMDS_DBG( "adapter_props->intapin = %d\n", adapter_props->intapin);\r
- CMDS_DBG( "adapter_props->revision_id = %d\n", adapter_props->revision_id);\r
- CMDS_DBG( "adapter_props->vendor_id = %d\n", adapter_props->vendor_id);\r
-}\r
-\r
-void THH_cmd_print_query_ddr( THH_ddr_props_t *ddr_props)\r
-{\r
- CMDS_DBG("QUERY DDR DUMP (THH_ddr_props_t structure)\n");\r
- CMDS_DBG( "ddr_props->ddr_start_adr = "U64_FMT"\n", ddr_props->ddr_start_adr);\r
- CMDS_DBG( "ddr_props->ddr_end_adr = "U64_FMT"\n", ddr_props->ddr_end_adr);\r
- CMDS_DBG( "\nddr_props->dimm0.di = %d\n", ddr_props->dimm0.di);\r
- CMDS_DBG( "ddr_props->dimm0.dimmsize = %d\n", ddr_props->dimm0.dimmsize);\r
- CMDS_DBG( "ddr_props->dimm0.dimmstatus = %d\n", ddr_props->dimm0.dimmstatus);\r
- CMDS_DBG( "ddr_props->dimm0.vendor_id = "U64_FMT"\n", ddr_props->dimm0.vendor_id);\r
- CMDS_DBG( "\nddr_props->dimm1.di = %d\n", ddr_props->dimm1.di);\r
- CMDS_DBG( "ddr_props->dimm1.dimmsize = %d\n", ddr_props->dimm1.dimmsize);\r
- CMDS_DBG( "ddr_props->dimm1.dimmstatus = %d\n", ddr_props->dimm1.dimmstatus);\r
- CMDS_DBG( "ddr_props->dimm1.vendor_id = "U64_FMT"\n", ddr_props->dimm1.vendor_id);\r
- CMDS_DBG( "\nddr_props->dimm2.di = %d\n", ddr_props->dimm2.di);\r
- CMDS_DBG( "ddr_props->dimm2.dimmsize = %d\n", ddr_props->dimm2.dimmsize);\r
- CMDS_DBG( "ddr_props->dimm2.dimmstatus = %d\n", ddr_props->dimm2.dimmstatus);\r
- CMDS_DBG( "ddr_props->dimm2.vendor_id = "U64_FMT"\n", ddr_props->dimm2.vendor_id);\r
- CMDS_DBG( "\nddr_props->dimm3.di = %d\n", ddr_props->dimm3.di);\r
- CMDS_DBG( "ddr_props->dimm3.dimmsize = %d\n", ddr_props->dimm3.dimmsize);\r
- CMDS_DBG( "ddr_props->dimm3.dimmstatus = %d\n", ddr_props->dimm3.dimmstatus);\r
- CMDS_DBG( "ddr_props->dimm3.vendor_id = "U64_FMT"\n", ddr_props->dimm3.vendor_id);\r
- CMDS_DBG( "ddr_props->dh = %s\n", (ddr_props->dh ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "ddr_props->ap = %d\n", ddr_props->ap);\r
- CMDS_DBG( "ddr_props->di = %d\n", ddr_props->di);\r
-}\r
-\r
-void THH_cmd_print_init_ib(IB_port_t port, THH_port_init_props_t *port_init_props)\r
-{\r
- CMDS_DBG("INIT_IB DUMP (THH_port_init_props_t structure) for port %d\n", port);\r
- CMDS_DBG( "port_init_props->max_gid = %d\n", port_init_props->max_gid);\r
- CMDS_DBG( "port_init_props->max_pkey = %d\n", port_init_props->max_pkey);\r
- CMDS_DBG( "port_init_props->mtu_cap = 0x%x\n", port_init_props->mtu_cap);\r
- CMDS_DBG( "port_init_props->port_width_cap = 0x%x\n", port_init_props->port_width_cap);\r
- CMDS_DBG( "port_init_props->vl_cap = 0x%x\n", port_init_props->vl_cap);\r
- CMDS_DBG( "port_init_props->g0 = %s\n", port_init_props->g0 ? "TRUE" : "FALSE");\r
- CMDS_DBG( "port_init_props->guid0 = 0x%2x%2x%2x%2x%2x%2x%2x%2x",\r
- port_init_props->guid0[0], port_init_props->guid0[1], port_init_props->guid0[2], \r
- port_init_props->guid0[3], port_init_props->guid0[4], port_init_props->guid0[5], \r
- port_init_props->guid0[6], port_init_props->guid0[7] );\r
-}\r
-\r
-void THH_cmd_print_cq_context(THH_cqc_t *cqc)\r
-{\r
- return;\r
- CMDS_DBG("CQ CONTEXT DUMP (THH_cqc_t structure)\n");\r
- CMDS_DBG( "cqc->st = 0x%x\n", cqc->st);\r
- CMDS_DBG( "cqc->oi (overrun ignore) = %s\n", cqc->oi ? "TRUE" : "FALSE");\r
- CMDS_DBG( "cqc->tr (translation required) = %s\n", cqc->tr ? "TRUE" : "FALSE");\r
- CMDS_DBG( "cqc->status = 0x%x\n", cqc->status);\r
- CMDS_DBG( "cqc->start_address = "U64_FMT"\n", cqc->start_address);\r
- CMDS_DBG( "cqc->usr_page = 0x%X\n", cqc->usr_page);\r
- CMDS_DBG( "cqc->log_cq_size = %d\n", cqc->log_cq_size);\r
- CMDS_DBG( "cqc->c_eqn = 0x%X\n", cqc->c_eqn);\r
- CMDS_DBG( "cqc->e_eqn = 0x%X\n", cqc->e_eqn);\r
- CMDS_DBG( "cqc->pd = 0x%X\n", cqc->pd);\r
- CMDS_DBG( "cqc->l_key = 0x%X\n", cqc->l_key);\r
- CMDS_DBG( "cqc->last_notified_indx = 0x%X\n", cqc->last_notified_indx);\r
- CMDS_DBG( "cqc->solicit_producer_indx = 0x%X\n", cqc->solicit_producer_indx);\r
- CMDS_DBG( "cqc->consumer_indx = 0x%X\n", cqc->consumer_indx);\r
- CMDS_DBG( "cqc->producer_indx = 0x%X\n", cqc->producer_indx);\r
- CMDS_DBG( "cqc->cqn = 0x%X\n", cqc->cqn);\r
-}\r
-void THH_cmd_print_qp_context(THH_qpee_context_t *qpc)\r
-{\r
- return;\r
- CMDS_DBG("QPEE CONTEXT DUMP (THH_qpee_context_t structure)\n");\r
- CMDS_DBG( "QPC ver = 0x%x\n", qpc->ver);\r
- // 'te' field has been removed:\r
- //CMDS_DBG( "QPC Address Translation Enabled = %s\n", (qpc->te ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "QPC Descriptor Event Enabled = %s\n", (qpc->de ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "QPC Path Migration State = 0x%x\n", qpc->pm_state);\r
- CMDS_DBG( "QPC Service Type = 0x%x\n", qpc->st);\r
- CMDS_DBG( "QPC VAPI-encoded State = %d\n", qpc->state);\r
- CMDS_DBG( "QPC Sched Queue = %d\n", qpc->sched_queue);\r
- CMDS_DBG( "QPC msg_max = %d\n", qpc->msg_max);\r
- CMDS_DBG( "QPC MTU (encoded) = %d\n", qpc->mtu);\r
- CMDS_DBG( "QPC usr_page = 0x%x\n", qpc->usr_page);\r
- CMDS_DBG( "QPC local_qpn_een = 0x%x\n", qpc->local_qpn_een);\r
- CMDS_DBG( "QPC remote_qpn_een = 0x%x\n", qpc->remote_qpn_een);\r
- CMDS_DBG( "QPC pd = 0x%x\n", qpc->pd);\r
- CMDS_DBG( "QPC wqe_base_adr = 0x%x\n", qpc->wqe_base_adr);\r
- CMDS_DBG( "QPC wqe_lkey = 0x%x\n", qpc->wqe_lkey);\r
- CMDS_DBG( "QPC ssc = %s\n", (qpc->ssc ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "QPC sic = %s\n", (qpc->sic ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "QPC sae = %s\n", (qpc->sae ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "QPC swe = %s\n", (qpc->swe ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "QPC sre = %s\n", (qpc->sre ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "QPC retry_count = 0x%x\n", qpc->retry_count);\r
- CMDS_DBG( "QPC sra_max = 0x%x\n", qpc->sra_max);\r
- CMDS_DBG( "QPC flight_lim = 0x%x\n", qpc->flight_lim);\r
- CMDS_DBG( "QPC ack_req_freq = 0x%x\n", qpc->ack_req_freq);\r
- CMDS_DBG( "QPC next_send_psn = 0x%x\n", qpc->next_send_psn);\r
- CMDS_DBG( "QPC cqn_snd = 0x%x\n", qpc->cqn_snd);\r
- CMDS_DBG( "QPC next_snd_wqe = "U64_FMT"\n", qpc->next_snd_wqe);\r
- CMDS_DBG( "QPC rsc = %s\n", (qpc->rsc ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "QPC ric = %s\n", (qpc->ric ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "QPC rae = %s\n", (qpc->rae ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "QPC rwe = %s\n", (qpc->rwe ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "QPC rre = %s\n", (qpc->rre ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "QPC rra_max = 0x%x\n", qpc->rra_max);\r
- CMDS_DBG( "QPC next_rcv_psn = 0x%x\n", qpc->next_rcv_psn);\r
- CMDS_DBG( "QPC min_rnr_nak = 0x%x\n", qpc->min_rnr_nak);\r
- CMDS_DBG( "QPC ra_buff_indx = 0x%x\n", qpc->ra_buff_indx);\r
- CMDS_DBG( "QPC cqn_rcv = 0x%x\n", qpc->cqn_rcv);\r
- CMDS_DBG( "QPC next_rcv_wqe = "U64_FMT"\n", qpc->next_rcv_wqe);\r
- CMDS_DBG( "QPC q_key = 0x%x\n", qpc->q_key);\r
- CMDS_DBG( "QPC srqn = 0x%x\n", qpc->srqn);\r
- CMDS_DBG( "QPC srq = %s\n", (qpc->srq ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "QPC primary.ack_timeout = %d\n" , qpc->primary_address_path.ack_timeout);\r
- CMDS_DBG( "QPC primary.max_stat_rate = %d\n" , qpc->primary_address_path.max_stat_rate);\r
-}\r
-void THH_cmd_print_eq_context(THH_eqc_t *eqc)\r
-{\r
- return;\r
- CMDS_DBG("EQ CONTEXT DUMP (THH_eqc_t structure)\n");\r
- CMDS_DBG( "eqc->st = 0x%x\n", eqc->st);\r
- CMDS_DBG( "eqc->oi (overrun ignore) = %s\n", eqc->oi ? "TRUE" : "FALSE");\r
- CMDS_DBG( "eqc->tr (translation required) = %s\n", eqc->tr ? "TRUE" : "FALSE");\r
- CMDS_DBG( "eqc->owner = %s\n", (eqc->owner == THH_OWNER_SW ? "THH_OWNER_SW" : "THH_OWNER_HW"));\r
- CMDS_DBG( "eqc->status = 0x%x\n", eqc->status);\r
- CMDS_DBG( "eqc->start_address = "U64_FMT"\n", eqc->start_address);\r
- CMDS_DBG( "eqc->usr_page = 0x%x\n", eqc->usr_page);\r
- CMDS_DBG( "eqc->log_eq_size = %d\n", eqc->log_eq_size);\r
- CMDS_DBG( "eqc->intr = 0x%x\n", eqc->intr);\r
- CMDS_DBG( "eqc->lost_count = 0x%x\n", eqc->lost_count);\r
- CMDS_DBG( "eqc->l_key = 0x%X\n", eqc->lkey);\r
- CMDS_DBG( "eqc->pd = 0x%X\n", eqc->pd);\r
- CMDS_DBG( "eqc->consumer_indx = 0x%X\n", eqc->consumer_indx);\r
- CMDS_DBG( "eqc->producer_indx = 0x%X\n", eqc->producer_indx);\r
-}\r
-void THH_cmd_print_mpt_entry(THH_mpt_entry_t *mpt)\r
-{\r
- CMDS_DBG("MPT ENTRY DUMP (THH_mpt_entry_t structure)\n");\r
- CMDS_DBG( "MPT entry type = %s\n", (mpt->r_w ? "REGION" : "WINDOW"));\r
- CMDS_DBG( "MPT physical addr flag = %s\n", (mpt->pa ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "MPT Local read access = %s\n", (mpt->lr ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "MPT Local write access = %s\n", (mpt->lw ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "MPT Remote read access = %s\n", (mpt->rr ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "MPT Remote write access = %s\n", (mpt->rw ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "MPT Atomic access = %s\n", (mpt->a ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "MPT Atomic access = %s\n", (mpt->a ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "MPT All writes posted = %s\n", (mpt->pw ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "MPT m_io = %s\n", (mpt->m_io ? "TRUE" : "FALSE"));\r
- CMDS_DBG( "MPT Status = 0x%x\n", mpt->status);\r
- CMDS_DBG( "MPT Page size = %d (Actual size is [4K]*2^Page_size)\n", mpt->page_size);\r
- CMDS_DBG( "MPT mem key = 0x%x\n", mpt->mem_key);\r
- CMDS_DBG( "MPT pd = 0x%x\n", mpt->pd);\r
- CMDS_DBG( "MPT start_address = "U64_FMT"\n", mpt->start_address);\r
- CMDS_DBG( "MPT length = "U64_FMT"\n", mpt->reg_wnd_len);\r
- CMDS_DBG( "MPT lkey = 0x%x\n", mpt->lkey);\r
- CMDS_DBG( "MPT win_cnt = 0x%x\n", mpt->win_cnt);\r
- CMDS_DBG( "MPT win_cnt_limit = 0x%x\n", mpt->win_cnt_limit);\r
- CMDS_DBG( "MPT MTT seg addr = "U64_FMT"\n", mpt->mtt_seg_adr);\r
-}\r
-\r
-void THH_cmd_print_mgm_entry(THH_mcg_entry_t *mgm)\r
-{\r
- IB_wqpn_t *qp_iterator;\r
- u_int32_t i;\r
-\r
- CMDS_DBG("MGM ENTRY DUMP (THH_mcg_entry_t structure)\n");\r
- CMDS_DBG( "MGM next_gid_index = 0x%x\n", mgm->next_gid_index);\r
- CMDS_DBG("MGM GID = %d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d \n",\r
- mgm->mgid[0], mgm->mgid[1], mgm->mgid[2], mgm->mgid[3]\r
- , mgm->mgid[4], mgm->mgid[5], mgm->mgid[6], mgm->mgid[7]\r
- , mgm->mgid[8], mgm->mgid[9], mgm->mgid[10], mgm->mgid[10]\r
- , mgm->mgid[12], mgm->mgid[13], mgm->mgid[14], mgm->mgid[15]);\r
- CMDS_DBG( "MGM valid_qps = %d \n", mgm->valid_qps);\r
- for (qp_iterator = mgm->qps, i = 0; i < mgm->valid_qps; i++, qp_iterator++) {\r
- CMDS_DBG( "MGM qps[%d] = 0x%x\n", i, *qp_iterator);\r
- }\r
-}\r
-\r
-#else\r
-\r
-void THH_cmd_print_hca_props(THH_hca_props_t *hca_props) {}\r
-void THH_cmd_print_dev_lims(THH_dev_lim_t *dev_lim) {}\r
-void THH_cmd_print_query_fw(THH_fw_props_t *fw_props) {}\r
-void THH_cmd_print_query_adapter( THH_adapter_props_t *adapter_props) {}\r
-void THH_cmd_print_query_ddr( THH_ddr_props_t *ddr_props) {}\r
-void THH_cmd_print_init_ib(IB_port_t port, THH_port_init_props_t *port_init_props) {}\r
-void THH_cmd_print_cq_context(THH_cqc_t *cqc) {}\r
-void THH_cmd_print_qp_context(THH_qpee_context_t *qpc) {}\r
-void THH_cmd_print_eq_context(THH_eqc_t *eqc) {}\r
-void THH_cmd_print_mpt_entry(THH_mpt_entry_t *mpt) {}\r
-void THH_cmd_print_mgm_entry(THH_mcg_entry_t *mgm) {}\r
-\r
-#endif /* #if THH_CMDS_WRAP_DEBUG_LEVEL */\r
-/***************************************************** */\r
-/************* END of PRINT UTILITIES **************** */\r
-/***************************************************** */\r
-\r
-\r
-/*\r
- * THH_cmd_QUERY_DEV_LIM\r
- */ \r
-THH_cmd_status_t THH_cmd_QUERY_DEV_LIM(THH_cmd_t cmd_if, THH_dev_lim_t *dev_lim)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t *outprm;\r
- THH_cmd_status_t rc; \r
- u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_query_dev_lim_st);\r
-\r
- FUNC_IN;\r
- outprm = TNMALLOC(u_int8_t, buf_size);\r
- if ( !outprm ) {\r
- MT_RETURN(THH_CMD_STAT_EAGAIN);\r
- }\r
- memset(outprm, 0, buf_size);\r
-\r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = 0;\r
- cmd_desc.out_param = outprm;\r
- cmd_desc.out_param_size = buf_size;\r
- cmd_desc.out_trans = TRANS_MAILBOX;\r
- cmd_desc.opcode = TAVOR_IF_CMD_QUERY_DEV_LIM;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_QUERY_DEV_LIM;\r
- \r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- if ( rc != THH_CMD_STAT_OK ) {\r
- FREE(outprm);\r
- MT_RETURN(rc);\r
- }\r
-\r
- if ( dev_lim ) {\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_max_qp);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log2_rsvd_qps);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_max_qp_sz);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_max_srqs);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log2_rsvd_srqs);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_max_srq_sz);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_max_ee);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log2_rsvd_ees);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_max_cq);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log2_rsvd_cqs);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_max_cq_sz);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_max_eq);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, num_rsvd_eqs);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_max_mpts);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_max_mtt_seg);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log2_rsvd_mrws);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_max_mrw_sz);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log2_rsvd_mtts);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_max_av);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_max_ra_res_qp);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_max_ra_req_qp);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_max_ra_res_global);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, num_ports);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, max_vl);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, max_port_width);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, max_mtu);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, local_ca_ack_delay);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_max_gid);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_max_pkey);\r
-\r
- EX_BOOL_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, rc);\r
- EX_BOOL_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, uc);\r
- EX_BOOL_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, ud);\r
- EX_BOOL_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, rd);\r
- EX_BOOL_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, raw_ipv6);\r
- EX_BOOL_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, raw_ether);\r
- EX_BOOL_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, srq);\r
- EX_BOOL_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, pkv);\r
- EX_BOOL_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, qkv);\r
- EX_BOOL_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, mw);\r
- EX_BOOL_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, apm);\r
- EX_BOOL_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, atm);\r
- EX_BOOL_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, rm);\r
- EX_BOOL_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, avp);\r
- EX_BOOL_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, udm);\r
- EX_BOOL_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, pg);\r
- EX_BOOL_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, r);\r
- \r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_pg_sz);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, uar_sz);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, num_rsvd_uars);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, max_desc_sz);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, max_sg);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_max_mcg);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_max_qp_mcg);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_max_rdds);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, num_rsvd_rdds);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, log_max_pd);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, num_rsvd_pds);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, qpc_entry_sz);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, eec_entry_sz);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, eqpc_entry_sz);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, eeec_entry_sz);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, cqc_entry_sz);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, eqc_entry_sz);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, srq_entry_sz);\r
- EX_FLD(dev_lim, outprm, tavorprm_query_dev_lim_st, uar_scratch_entry_sz);\r
- THH_CMD_PRINT_DEV_LIMS(dev_lim);\r
- }\r
-\r
- FREE(outprm);\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_QUERY_FW\r
- */ \r
-THH_cmd_status_t THH_cmd_QUERY_FW(THH_cmd_t cmd_if, THH_fw_props_t *fw_props)\r
-{\r
- command_fields_t cmd_desc;\r
- //u_int8_t outprm[PSEUDO_MT_BYTE_SIZE(tavorprm_query_fw_st)];\r
- u_int8_t *outprm;\r
- THH_cmd_status_t rc;\r
- u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_query_fw_st);\r
-\r
- FUNC_IN;\r
- outprm = TNMALLOC(u_int8_t, buf_size);\r
- if ( !outprm ) {\r
- MT_RETURN(THH_CMD_STAT_EAGAIN);\r
- }\r
- memset(outprm, 0, buf_size);\r
- \r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = 0;\r
- cmd_desc.out_param = outprm;\r
- cmd_desc.out_param_size = buf_size;\r
- cmd_desc.out_trans = TRANS_MAILBOX;\r
- cmd_desc.opcode = TAVOR_IF_CMD_QUERY_FW;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_QUERY_FW;\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- if ( rc != THH_CMD_STAT_OK ) {\r
- FREE(outprm);\r
- MT_RETURN(rc);\r
- }\r
-\r
- EX_FLD(fw_props, outprm, tavorprm_query_fw_st, fw_rev_major);\r
- EX_FLD(fw_props, outprm, tavorprm_query_fw_st, fw_rev_minor);\r
- EX_FLD(fw_props, outprm, tavorprm_query_fw_st, fw_rev_subminor);\r
- EX_FLD(fw_props, outprm, tavorprm_query_fw_st, cmd_interface_rev);\r
- EX_FLD(fw_props, outprm, tavorprm_query_fw_st, log_max_outstanding_cmd);\r
- EX_FLD64(fw_props, outprm, tavorprm_query_fw_st, fw_base_addr);\r
- EX_FLD64(fw_props, outprm, tavorprm_query_fw_st, fw_end_addr);\r
- EX_FLD64(fw_props, outprm, tavorprm_query_fw_st, error_buf_start);\r
- EX_FLD(fw_props, outprm, tavorprm_query_fw_st, error_buf_size);\r
- FREE(outprm);\r
-\r
- THH_cmd_set_fw_props(cmd_if, fw_props);\r
-\r
- THH_CMD_PRINT_QUERY_FW(fw_props);\r
- \r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_QUERY_DDR\r
- */ \r
-THH_cmd_status_t THH_cmd_QUERY_DDR(THH_cmd_t cmd_if, THH_ddr_props_t *ddr_props)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t *outprm;\r
- THH_cmd_status_t rc;\r
- u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_query_ddr_st);\r
-\r
- FUNC_IN;\r
- outprm = TNMALLOC(u_int8_t, buf_size);\r
- if ( !outprm ) {\r
- MT_RETURN(THH_CMD_STAT_EAGAIN);\r
- }\r
- memset(outprm, 0, buf_size);\r
- \r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = 0;\r
- cmd_desc.out_param = outprm;\r
- cmd_desc.out_param_size = buf_size;\r
- cmd_desc.out_trans = TRANS_MAILBOX;\r
- cmd_desc.opcode = TAVOR_IF_CMD_QUERY_DDR;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_QUERY_DDR;\r
- \r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- if ( rc != THH_CMD_STAT_OK ) {\r
- FREE(outprm);\r
- MT_RETURN(rc);\r
- }\r
-\r
- if ( ddr_props ) {\r
- EX_FLD64(ddr_props, outprm, tavorprm_query_ddr_st, ddr_start_adr);\r
- EX_FLD64(ddr_props, outprm, tavorprm_query_ddr_st, ddr_end_adr);\r
-\r
- EX_BOOL_FLD(ddr_props, outprm, tavorprm_query_ddr_st, dh);\r
- EX_FLD(ddr_props, outprm, tavorprm_query_ddr_st, di);\r
- EX_FLD(ddr_props, outprm, tavorprm_query_ddr_st, ap);\r
-\r
- /* TBD handle dimm structs here */\r
- EX_FLD(ddr_props, outprm, tavorprm_query_ddr_st, dimm0.dimmsize);\r
- EX_FLD(ddr_props, outprm, tavorprm_query_ddr_st, dimm0.dimmstatus);\r
- EX_FLD64(ddr_props, outprm, tavorprm_query_ddr_st, dimm0.vendor_id);\r
-\r
- EX_FLD(ddr_props, outprm, tavorprm_query_ddr_st, dimm1.dimmsize);\r
- EX_FLD(ddr_props, outprm, tavorprm_query_ddr_st, dimm1.dimmstatus);\r
- EX_FLD64(ddr_props, outprm, tavorprm_query_ddr_st, dimm1.vendor_id);\r
-\r
- EX_FLD(ddr_props, outprm, tavorprm_query_ddr_st, dimm2.dimmsize);\r
- EX_FLD(ddr_props, outprm, tavorprm_query_ddr_st, dimm2.dimmstatus);\r
- EX_FLD64(ddr_props, outprm, tavorprm_query_ddr_st, dimm2.vendor_id);\r
-\r
- EX_FLD(ddr_props, outprm, tavorprm_query_ddr_st, dimm3.dimmsize);\r
- EX_FLD(ddr_props, outprm, tavorprm_query_ddr_st, dimm3.dimmstatus);\r
- EX_FLD64(ddr_props, outprm, tavorprm_query_ddr_st, dimm3.vendor_id);\r
-\r
- THH_CMD_PRINT_QUERY_DDR(ddr_props);\r
- }\r
- FREE(outprm);\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_QUERY_ADAPTER\r
- */ \r
-THH_cmd_status_t THH_cmd_QUERY_ADAPTER(THH_cmd_t cmd_if, THH_adapter_props_t *adapter_props)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t *outprm;\r
- THH_cmd_status_t rc;\r
- u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_query_adapter_st);\r
-\r
- FUNC_IN;\r
- outprm = TNMALLOC(u_int8_t, buf_size);\r
- if (outprm == NULL) {\r
- MT_RETURN(THH_CMD_STAT_EAGAIN);\r
- }\r
- memset(outprm, 0, buf_size);\r
- \r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = 0;\r
- cmd_desc.out_param = outprm;\r
- cmd_desc.out_param_size = buf_size;\r
- cmd_desc.out_trans = TRANS_MAILBOX;\r
- cmd_desc.opcode = TAVOR_IF_CMD_QUERY_ADAPTER;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_QUERY_ADAPTER;\r
- \r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- if ( rc != THH_CMD_STAT_OK ) {\r
- FREE(outprm);\r
- MT_RETURN(rc);\r
- }\r
-\r
- if ( adapter_props ) {\r
- EX_FLD(adapter_props, outprm, tavorprm_query_adapter_st, vendor_id);\r
- EX_FLD(adapter_props, outprm, tavorprm_query_adapter_st, device_id);\r
- EX_FLD(adapter_props, outprm, tavorprm_query_adapter_st, revision_id);\r
- EX_FLD(adapter_props, outprm, tavorprm_query_adapter_st, intapin);\r
-\r
- THH_CMD_PRINT_QUERY_ADAPTER(adapter_props);\r
- }\r
- FREE(outprm);\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_INIT_HCA\r
- */ \r
-\r
-THH_cmd_status_t THH_cmd_INIT_HCA(THH_cmd_t cmd_if, THH_hca_props_t *hca_props)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t *inprm;\r
- THH_cmd_status_t rc;\r
- u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_init_hca_st);\r
- u_int64_t rdb_base_addr_save;\r
-\r
- FUNC_IN;\r
- if (hca_props == NULL) {MT_RETURN(THH_CMD_STAT_EBADARG); }\r
- inprm = TNMALLOC(u_int8_t, buf_size);\r
- if ( !inprm ) {\r
- MT_RETURN(THH_CMD_STAT_EAGAIN);\r
- }\r
- memset(inprm, 0, buf_size);\r
- THH_CMD_PRINT_HCA_PROPS(hca_props);\r
-\r
- cmd_desc.in_param = inprm;\r
- cmd_desc.in_param_size = buf_size;\r
- cmd_desc.in_trans = TRANS_MAILBOX;\r
- cmd_desc.input_modifier = 0;\r
- cmd_desc.out_param = 0;\r
- cmd_desc.out_param_size = 0;\r
- cmd_desc.out_trans = TRANS_NA;\r
- cmd_desc.opcode = TAVOR_IF_CMD_INIT_HCA;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = hca_props->qpc_eec_cqc_eqc_rdb_parameters.log_num_of_qp > 18 ?\r
- 2*(TAVOR_IF_CMD_ETIME_INIT_HCA) : TAVOR_IF_CMD_ETIME_INIT_HCA;\r
-\r
- INS_FLD(hca_props, inprm, tavorprm_init_hca_st, router_qp);\r
- INS_BOOL_FLD(hca_props, inprm, tavorprm_init_hca_st, re);\r
- INS_BOOL_FLD(hca_props, inprm, tavorprm_init_hca_st, udp);\r
- INS_BOOL_FLD(hca_props, inprm, tavorprm_init_hca_st, he);\r
- INS_BOOL_FLD(hca_props, inprm, tavorprm_init_hca_st, ud);\r
-\r
- INS_FLD64_SH(hca_props, inprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr);\r
- INS_FLD(hca_props, inprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.log_num_of_qp);\r
- INS_FLD64_SH(hca_props, inprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.srqc_base_addr);\r
- INS_FLD(hca_props, inprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.log_num_of_srq);\r
- INS_FLD64_SH(hca_props, inprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.eec_base_addr);\r
- INS_FLD(hca_props, inprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.log_num_of_ee);\r
- INS_FLD64_SH(hca_props, inprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr);\r
- INS_FLD(hca_props, inprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.log_num_of_cq);\r
- INS_FLD64(hca_props, inprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.eqpc_base_addr);\r
- INS_FLD64(hca_props, inprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.eeec_base_addr);\r
- INS_FLD64_SH(hca_props, inprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr);\r
- INS_FLD(hca_props, inprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.log_num_eq);\r
-\r
- /* zero out low order 32 bits of rdb base addr for passing to Tavor */\r
- rdb_base_addr_save = hca_props->qpc_eec_cqc_eqc_rdb_parameters.rdb_base_addr;\r
- hca_props->qpc_eec_cqc_eqc_rdb_parameters.rdb_base_addr &= MAKE_ULONGLONG(0xFFFFFFFF00000000);\r
- INS_FLD64(hca_props, inprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.rdb_base_addr);\r
- /*restore original RDB base address */\r
- hca_props->qpc_eec_cqc_eqc_rdb_parameters.rdb_base_addr =rdb_base_addr_save;\r
-\r
- INS_FLD(hca_props, inprm, tavorprm_init_hca_st, udavtable_memory_parameters.l_key);\r
- INS_FLD(hca_props, inprm, tavorprm_init_hca_st, udavtable_memory_parameters.pd);\r
- INS_BOOL_FLD(hca_props, inprm, tavorprm_init_hca_st, udavtable_memory_parameters.xlation_en);\r
- \r
- INS_FLD64(hca_props, inprm, tavorprm_init_hca_st, multicast_parameters.mc_base_addr);\r
- INS_FLD(hca_props, inprm, tavorprm_init_hca_st, multicast_parameters.log_mc_table_entry_sz);\r
- INS_FLD(hca_props, inprm, tavorprm_init_hca_st, multicast_parameters.log_mc_table_sz);\r
- INS_FLD(hca_props, inprm, tavorprm_init_hca_st, multicast_parameters.mc_table_hash_sz);\r
- INS_FLD(hca_props, inprm, tavorprm_init_hca_st, multicast_parameters.mc_hash_fn);\r
- \r
- INS_FLD64(hca_props, inprm, tavorprm_init_hca_st, tpt_parameters.mpt_base_adr);\r
- INS_FLD(hca_props, inprm, tavorprm_init_hca_st, tpt_parameters.log_mpt_sz);\r
- INS_FLD(hca_props, inprm, tavorprm_init_hca_st, tpt_parameters.pfto);\r
- INS_FLD(hca_props, inprm, tavorprm_init_hca_st, tpt_parameters.mtt_segment_size);\r
- INS_FLD(hca_props, inprm, tavorprm_init_hca_st, tpt_parameters.mtt_version);\r
- INS_FLD64(hca_props, inprm, tavorprm_init_hca_st, tpt_parameters.mtt_base_addr);\r
- \r
- INS_FLD64(hca_props, inprm, tavorprm_init_hca_st, uar_parameters.uar_base_addr);\r
- INS_FLD(hca_props, inprm, tavorprm_init_hca_st, uar_parameters.uar_page_sz);\r
- INS_FLD64(hca_props, inprm, tavorprm_init_hca_st, uar_parameters.uar_scratch_base_addr);\r
- THH_CMD_MAILBOX_PRINT(inprm, buf_size, __func__);\r
- \r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- FREE(inprm);\r
- MT_RETURN(rc);\r
-}\r
-\r
-\r
-/*\r
- * THH_cmd_CLOSE_HCA\r
- */ \r
-#ifdef SIMULATE_HALT_HCA\r
-THH_cmd_status_t THH_cmd_CLOSE_HCA(THH_cmd_t cmd_if)\r
-#else\r
-THH_cmd_status_t THH_cmd_CLOSE_HCA(THH_cmd_t cmd_if, MT_bool do_halt)\r
-#endif\r
-{\r
- command_fields_t cmd_desc;\r
- THH_cmd_status_t rc;\r
-\r
- FUNC_IN;\r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = 0;\r
- cmd_desc.out_param = 0;\r
- cmd_desc.out_param_size = 0;\r
- cmd_desc.out_trans = TRANS_NA;\r
- cmd_desc.opcode = TAVOR_IF_CMD_CLOSE_HCA;\r
-#ifdef SIMULATE_HALT_HCA\r
- cmd_desc.opcode_modifier = 0;\r
-#else\r
- cmd_desc.opcode_modifier = (do_halt == FALSE ? 0 : 1);\r
-#endif\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_CLOSE_HCA;\r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- MT_RETURN(rc);\r
-}\r
-\r
-\r
-/*\r
- * THH_cmd_INIT_IB\r
- */ \r
-THH_cmd_status_t THH_cmd_INIT_IB(THH_cmd_t cmd_if, IB_port_t port,\r
- THH_port_init_props_t *port_init_props)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t *inprm;\r
- THH_cmd_status_t rc;\r
- u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_init_ib_st);\r
- u_int32_t temp_u32;\r
-\r
- FUNC_IN;\r
- if (port_init_props == NULL) {MT_RETURN(THH_CMD_STAT_EBADARG); }\r
- \r
- inprm = TNMALLOC(u_int8_t, buf_size);\r
- if ( !inprm ) {\r
- MT_RETURN(THH_CMD_STAT_EAGAIN);\r
- }\r
- memset(inprm, 0, buf_size);\r
- THH_CMD_PRINT_INIT_IB(port, port_init_props);\r
- cmd_desc.in_param = inprm;\r
- cmd_desc.in_param_size = buf_size;\r
- cmd_desc.in_trans = TRANS_MAILBOX;\r
- cmd_desc.input_modifier = port;\r
- cmd_desc.out_param = 0;\r
- cmd_desc.out_param_size = 0;\r
- cmd_desc.out_trans = TRANS_NA;\r
- cmd_desc.opcode = TAVOR_IF_CMD_INIT_IB;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_INIT_IB;\r
-\r
- INS_FLD(port_init_props, inprm, tavorprm_init_ib_st, vl_cap);\r
- INS_FLD(port_init_props, inprm, tavorprm_init_ib_st, port_width_cap);\r
- INS_FLD(port_init_props, inprm, tavorprm_init_ib_st, mtu_cap);\r
- INS_FLD(port_init_props, inprm, tavorprm_init_ib_st, max_gid);\r
- INS_FLD(port_init_props, inprm, tavorprm_init_ib_st, max_pkey);\r
-\r
- INS_BOOL_FLD(port_init_props, inprm, tavorprm_init_ib_st, g0);\r
-\r
- /* We get GUID0 in BIG_ENDIAN format. It needs to be split up into Host-endian format before passing to cmd_invoke */\r
- /* Note that need to memcpy each 4 bytes to a temporary u_int32_t variable, since there is no guarantee */\r
- /* that the GUID is 4-byte aligned (it is an array of unsigned chars) */\r
- memcpy(&temp_u32, &(port_init_props->guid0[0]), sizeof(u_int32_t));\r
- MT_INSERT_ARRAY32(inprm, MOSAL_be32_to_cpu(temp_u32), \r
- MT_BIT_OFFSET(tavorprm_init_ib_st, guid0_h), MT_BIT_SIZE(tavorprm_init_ib_st, guid0_h));\r
-\r
- memcpy(&temp_u32, &(port_init_props->guid0[4]), sizeof(u_int32_t));\r
- MT_INSERT_ARRAY32(inprm, MOSAL_be32_to_cpu(temp_u32), \r
- MT_BIT_OFFSET(tavorprm_init_ib_st, guid0_l), MT_BIT_SIZE(tavorprm_init_ib_st, guid0_l));\r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- FREE(inprm);\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_CLOSE_IB\r
- */ \r
-THH_cmd_status_t THH_cmd_SYS_DIS(THH_cmd_t cmd_if)\r
-{\r
- command_fields_t cmd_desc;\r
- THH_cmd_status_t rc;\r
-\r
- FUNC_IN;\r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = 0;\r
- cmd_desc.out_param = 0;\r
- cmd_desc.out_param_size = 0;\r
- cmd_desc.out_trans = TRANS_NA;\r
- cmd_desc.opcode = TAVOR_IF_CMD_SYS_DIS;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_SYS_DIS;\r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- MT_RETURN(rc);\r
-}\r
-\r
-\r
-\r
-/*\r
- * THH_cmd_CLOSE_IB\r
- */ \r
-THH_cmd_status_t THH_cmd_CLOSE_IB(THH_cmd_t cmd_if, IB_port_t port)\r
-{\r
- command_fields_t cmd_desc;\r
- THH_cmd_status_t rc;\r
-\r
- FUNC_IN;\r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = port;\r
- cmd_desc.out_param = 0;\r
- cmd_desc.out_param_size = 0;\r
- cmd_desc.out_trans = TRANS_NA;\r
- cmd_desc.opcode = TAVOR_IF_CMD_CLOSE_IB;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_CLOSE_IB;\r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_QUERY_HCA\r
- */ \r
-\r
-THH_cmd_status_t THH_cmd_QUERY_HCA(THH_cmd_t cmd_if, THH_hca_props_t *hca_props)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t *outprm;\r
- THH_cmd_status_t rc;\r
- u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_init_hca_st);\r
-\r
- FUNC_IN;\r
- outprm = TNMALLOC(u_int8_t, buf_size);\r
- if ( !outprm ) {\r
- MT_RETURN(THH_CMD_STAT_EAGAIN);\r
- }\r
- memset(outprm, 0, buf_size);\r
-\r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = 0;\r
- cmd_desc.out_param = outprm;\r
- cmd_desc.out_param_size = buf_size;\r
- cmd_desc.out_trans = TRANS_MAILBOX;\r
- cmd_desc.opcode = TAVOR_IF_CMD_QUERY_HCA;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_QUERY_HCA;\r
- \r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- if ( rc != THH_CMD_STAT_OK ) {\r
- FREE(outprm);\r
- MT_RETURN(rc);\r
- }\r
-\r
- if ( hca_props ) {\r
- EX_FLD(hca_props, outprm, tavorprm_init_hca_st, hca_core_clock);\r
- EX_FLD(hca_props, outprm, tavorprm_init_hca_st, router_qp);\r
- EX_BOOL_FLD(hca_props, outprm, tavorprm_init_hca_st, re);\r
- EX_BOOL_FLD(hca_props, outprm, tavorprm_init_hca_st, udp);\r
- EX_BOOL_FLD(hca_props, outprm, tavorprm_init_hca_st, he);\r
- EX_BOOL_FLD(hca_props, outprm, tavorprm_init_hca_st, ud);\r
-\r
- EX_FLD64_SH(hca_props, outprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr);\r
- EX_FLD(hca_props, outprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.log_num_of_qp);\r
- EX_FLD64_SH(hca_props, outprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.srqc_base_addr);\r
- EX_FLD(hca_props, outprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.log_num_of_srq);\r
- EX_FLD64_SH(hca_props, outprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.eec_base_addr);\r
- EX_FLD(hca_props, outprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.log_num_of_ee);\r
- EX_FLD64_SH(hca_props, outprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr);\r
- EX_FLD(hca_props, outprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.log_num_of_cq);\r
- EX_FLD64(hca_props, outprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.eqpc_base_addr);\r
- EX_FLD64(hca_props, outprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.eeec_base_addr);\r
- EX_FLD64_SH(hca_props, outprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr);\r
- EX_FLD(hca_props, outprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.log_num_eq);\r
- EX_FLD64(hca_props, outprm, tavorprm_init_hca_st, qpc_eec_cqc_eqc_rdb_parameters.rdb_base_addr);\r
-\r
- EX_FLD(hca_props, outprm, tavorprm_init_hca_st, udavtable_memory_parameters.l_key);\r
- EX_FLD(hca_props, outprm, tavorprm_init_hca_st, udavtable_memory_parameters.pd);\r
- EX_BOOL_FLD(hca_props, outprm, tavorprm_init_hca_st, udavtable_memory_parameters.xlation_en);\r
-\r
- EX_FLD64(hca_props, outprm, tavorprm_init_hca_st, multicast_parameters.mc_base_addr);\r
- EX_FLD(hca_props, outprm, tavorprm_init_hca_st, multicast_parameters.log_mc_table_entry_sz);\r
- EX_FLD(hca_props, outprm, tavorprm_init_hca_st, multicast_parameters.log_mc_table_sz);\r
- EX_FLD(hca_props, outprm, tavorprm_init_hca_st, multicast_parameters.mc_table_hash_sz);\r
- EX_FLD(hca_props, outprm, tavorprm_init_hca_st, multicast_parameters.mc_hash_fn);\r
-\r
- EX_FLD64(hca_props, outprm, tavorprm_init_hca_st, tpt_parameters.mpt_base_adr);\r
- EX_FLD(hca_props, outprm, tavorprm_init_hca_st, tpt_parameters.log_mpt_sz);\r
- EX_FLD(hca_props, outprm, tavorprm_init_hca_st, tpt_parameters.pfto);\r
- EX_FLD(hca_props, outprm, tavorprm_init_hca_st, tpt_parameters.mtt_segment_size);\r
- EX_FLD(hca_props, outprm, tavorprm_init_hca_st, tpt_parameters.mtt_version);\r
- EX_FLD64(hca_props, outprm, tavorprm_init_hca_st, tpt_parameters.mtt_base_addr);\r
-\r
- EX_FLD64(hca_props, outprm, tavorprm_init_hca_st, uar_parameters.uar_base_addr);\r
- EX_FLD(hca_props, outprm, tavorprm_init_hca_st, uar_parameters.uar_page_sz);\r
- EX_FLD64(hca_props, outprm, tavorprm_init_hca_st, uar_parameters.uar_scratch_base_addr);\r
- THH_CMD_MAILBOX_PRINT(outprm, buf_size, __func__);\r
-\r
- THH_CMD_PRINT_HCA_PROPS(hca_props);\r
- }\r
- \r
- FREE(outprm);\r
- MT_RETURN(rc);\r
-}\r
-\r
-\r
-/*\r
- * THH_cmd_SET_IB\r
- */ \r
-THH_cmd_status_t THH_cmd_SET_IB(THH_cmd_t cmd_if, IB_port_t port,\r
- THH_set_ib_props_t *port_init_props)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t inprm[PSEUDO_MT_BYTE_SIZE(tavorprm_set_ib_st)];\r
- THH_cmd_status_t rc;\r
- u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_set_ib_st);\r
-\r
- FUNC_IN;\r
- if (port_init_props == NULL) {MT_RETURN(THH_CMD_STAT_EBADARG);}\r
- memset(inprm, 0, buf_size);\r
-\r
- cmd_desc.in_param = inprm;\r
- cmd_desc.in_param_size = buf_size;\r
- cmd_desc.in_trans = TRANS_MAILBOX;\r
- cmd_desc.input_modifier = port;\r
- cmd_desc.out_param = 0;\r
- cmd_desc.out_param_size = 0;\r
- cmd_desc.out_trans = TRANS_NA;\r
- cmd_desc.opcode = TAVOR_IF_CMD_SET_IB;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_SET_IB;\r
-\r
- INS_BOOL_FLD(port_init_props, inprm, tavorprm_set_ib_st, rqk);\r
- INS_FLD(port_init_props, inprm, tavorprm_set_ib_st, capability_mask);\r
- \r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_SW2HW_MPT\r
- */ \r
-THH_cmd_status_t THH_cmd_SW2HW_MPT(THH_cmd_t cmd_if, THH_mpt_index_t mpt_index,\r
- THH_mpt_entry_t *mpt_entry)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t inprm[PSEUDO_MT_BYTE_SIZE(tavorprm_mpt_st)];\r
- THH_cmd_status_t rc;\r
- MT_size_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_mpt_st);\r
-\r
- FUNC_IN;\r
- MTL_DEBUG4("THH_cmd_SW2HW_MPT: mpt_index = "SIZE_T_FMT", buf_size = "SIZE_T_FMT"\n", mpt_index, buf_size); \r
- if (mpt_entry == NULL) {MT_RETURN(THH_CMD_STAT_EBADARG); }\r
- THH_CMD_PRINT_MPT_ENTRY(mpt_entry);\r
-\r
- memset(inprm, 0, buf_size);\r
- \r
- cmd_desc.in_param = inprm;\r
- cmd_desc.in_param_size = (u_int32_t)buf_size;\r
- cmd_desc.in_trans = TRANS_MAILBOX;\r
- cmd_desc.input_modifier = (u_int32_t)mpt_index;\r
- cmd_desc.out_param = 0;\r
- cmd_desc.out_param_size = 0;\r
- cmd_desc.out_trans = TRANS_NA;\r
- cmd_desc.opcode = TAVOR_IF_CMD_SW2HW_MPT;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_SW2HW_MPT;\r
-\r
- INS_FLD(mpt_entry, inprm, tavorprm_mpt_st, ver);\r
- \r
- INS_BOOL_FLD(mpt_entry, inprm, tavorprm_mpt_st, r_w);\r
- INS_BOOL_FLD(mpt_entry, inprm, tavorprm_mpt_st, pa);\r
- INS_BOOL_FLD(mpt_entry, inprm, tavorprm_mpt_st, lr);\r
- INS_BOOL_FLD(mpt_entry, inprm, tavorprm_mpt_st, lw);\r
- INS_BOOL_FLD(mpt_entry, inprm, tavorprm_mpt_st, rr);\r
- INS_BOOL_FLD(mpt_entry, inprm, tavorprm_mpt_st, rw);\r
- INS_BOOL_FLD(mpt_entry, inprm, tavorprm_mpt_st, a);\r
- INS_BOOL_FLD(mpt_entry, inprm, tavorprm_mpt_st, eb);\r
- INS_BOOL_FLD(mpt_entry, inprm, tavorprm_mpt_st, m_io);\r
- \r
- INS_FLD(mpt_entry, inprm, tavorprm_mpt_st, status);\r
- INS_FLD(mpt_entry, inprm, tavorprm_mpt_st, page_size);\r
- INS_FLD(mpt_entry, inprm, tavorprm_mpt_st, mem_key);\r
- INS_FLD(mpt_entry, inprm, tavorprm_mpt_st, pd);\r
- INS_FLD64(mpt_entry, inprm, tavorprm_mpt_st, start_address);\r
- INS_FLD64(mpt_entry, inprm, tavorprm_mpt_st, reg_wnd_len);\r
- INS_FLD(mpt_entry, inprm, tavorprm_mpt_st, lkey);\r
- INS_FLD(mpt_entry, inprm, tavorprm_mpt_st, win_cnt);\r
- INS_FLD(mpt_entry, inprm, tavorprm_mpt_st, win_cnt_limit);\r
- INS_FLD64_SH(mpt_entry, inprm, tavorprm_mpt_st, mtt_seg_adr);\r
-\r
- THH_CMD_MAILBOX_PRINT(inprm, (int)buf_size, __func__);\r
-#if 1\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
-#else\r
- MTL_DEBUG4("THH_cmd_SW2HW_MPT: SKIPPING cmd_invoke !!!!!!!!!\n");\r
- rc = THH_CMD_STAT_OK;\r
-#endif\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_SW2HW_MPT\r
- */ \r
-THH_cmd_status_t THH_cmd_MODIFY_MPT(THH_cmd_t cmd_if, THH_mpt_index_t mpt_index,\r
- THH_mpt_entry_t *mpt_entry, MT_bool modify_entire_entry)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t inprm[PSEUDO_MT_BYTE_SIZE(tavorprm_mpt_st)];\r
- THH_cmd_status_t rc;\r
- MT_size_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_mpt_st);\r
-\r
- FUNC_IN;\r
- MTL_DEBUG4("THH_cmd_MODIFY_MPT: mpt_index = "SIZE_T_FMT", (in_param)buf_size = "SIZE_T_FMT"\n", \r
- mpt_index, buf_size); \r
- MTL_DEBUG4("%s: mpt_entry->reg_wnd_len="U64_FMT" mpt_entry->mtt_seg_adr="U64_FMT, \r
- __func__,mpt_entry->reg_wnd_len, mpt_entry->mtt_seg_adr);\r
- if (mpt_entry == NULL) {MT_RETURN(THH_CMD_STAT_EBADARG); }\r
- THH_CMD_PRINT_MPT_ENTRY(mpt_entry);\r
-\r
- memset(inprm, 0, buf_size);\r
- \r
- cmd_desc.in_param = inprm;\r
- cmd_desc.in_param_size = (u_int32_t)buf_size;\r
- cmd_desc.in_trans = TRANS_MAILBOX;\r
- cmd_desc.input_modifier = (u_int32_t)mpt_index;\r
- cmd_desc.out_param = 0;\r
- cmd_desc.out_param_size = 0;\r
- cmd_desc.out_trans = TRANS_NA;\r
- cmd_desc.opcode = TAVOR_IF_CMD_MODIFY_MPT ;\r
- cmd_desc.opcode_modifier = (modify_entire_entry == TRUE) ? 0x5 : 0x3;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_CLASS_B;\r
-\r
- INS_FLD(mpt_entry, inprm, tavorprm_mpt_st, ver);\r
- \r
- INS_BOOL_FLD(mpt_entry, inprm, tavorprm_mpt_st, r_w);\r
- INS_BOOL_FLD(mpt_entry, inprm, tavorprm_mpt_st, pa);\r
- INS_BOOL_FLD(mpt_entry, inprm, tavorprm_mpt_st, lr);\r
- INS_BOOL_FLD(mpt_entry, inprm, tavorprm_mpt_st, lw);\r
- INS_BOOL_FLD(mpt_entry, inprm, tavorprm_mpt_st, rr);\r
- INS_BOOL_FLD(mpt_entry, inprm, tavorprm_mpt_st, rw);\r
- INS_BOOL_FLD(mpt_entry, inprm, tavorprm_mpt_st, a);\r
- INS_BOOL_FLD(mpt_entry, inprm, tavorprm_mpt_st, eb);\r
- INS_BOOL_FLD(mpt_entry, inprm, tavorprm_mpt_st, m_io);\r
- \r
- INS_FLD(mpt_entry, inprm, tavorprm_mpt_st, status);\r
- INS_FLD(mpt_entry, inprm, tavorprm_mpt_st, page_size);\r
- INS_FLD(mpt_entry, inprm, tavorprm_mpt_st, mem_key);\r
- INS_FLD(mpt_entry, inprm, tavorprm_mpt_st, pd);\r
- INS_FLD64(mpt_entry, inprm, tavorprm_mpt_st, start_address);\r
- INS_FLD64(mpt_entry, inprm, tavorprm_mpt_st, reg_wnd_len);\r
- INS_FLD(mpt_entry, inprm, tavorprm_mpt_st, lkey);\r
- INS_FLD(mpt_entry, inprm, tavorprm_mpt_st, win_cnt);\r
- INS_FLD(mpt_entry, inprm, tavorprm_mpt_st, win_cnt_limit);\r
- INS_FLD64_SH(mpt_entry, inprm, tavorprm_mpt_st, mtt_seg_adr);\r
-\r
- THH_CMD_MAILBOX_PRINT(inprm, (int)buf_size, __func__);\r
-#if 1\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
-#else\r
- MTL_DEBUG4("%s: SKIPPING cmd_invoke !!!!!!!!!\n", __func__);\r
- rc = THH_CMD_STAT_OK;\r
-#endif\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_QUERY_MPT\r
- */ \r
-THH_cmd_status_t THH_cmd_QUERY_MPT(THH_cmd_t cmd_if, THH_mpt_index_t mpt_index,\r
- THH_mpt_entry_t *mpt_entry)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t outprm[PSEUDO_MT_BYTE_SIZE(tavorprm_mpt_st)];\r
- THH_cmd_status_t rc;\r
- u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_mpt_st);\r
-\r
- FUNC_IN;\r
- memset(outprm, 0, buf_size);\r
-\r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = (u_int32_t)mpt_index;\r
- cmd_desc.out_param = outprm;\r
- cmd_desc.out_param_size = buf_size;\r
- cmd_desc.out_trans = TRANS_MAILBOX;\r
- cmd_desc.opcode = TAVOR_IF_CMD_QUERY_MPT;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_QUERY_MPT;\r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- if ( rc != THH_CMD_STAT_OK ) {\r
- MT_RETURN(rc);\r
- }\r
- \r
- if ( mpt_entry ) {\r
- EX_FLD(mpt_entry, outprm, tavorprm_mpt_st, ver);\r
- EX_BOOL_FLD(mpt_entry, outprm, tavorprm_mpt_st, r_w);\r
- EX_BOOL_FLD(mpt_entry, outprm, tavorprm_mpt_st, pa);\r
- EX_BOOL_FLD(mpt_entry, outprm, tavorprm_mpt_st, lr);\r
- EX_BOOL_FLD(mpt_entry, outprm, tavorprm_mpt_st, lw);\r
- EX_BOOL_FLD(mpt_entry, outprm, tavorprm_mpt_st, rr);\r
- EX_BOOL_FLD(mpt_entry, outprm, tavorprm_mpt_st, rw);\r
- EX_BOOL_FLD(mpt_entry, outprm, tavorprm_mpt_st, a);\r
- EX_BOOL_FLD(mpt_entry, outprm, tavorprm_mpt_st, eb);\r
- EX_BOOL_FLD(mpt_entry, outprm, tavorprm_mpt_st, m_io);\r
-\r
- EX_FLD(mpt_entry, outprm, tavorprm_mpt_st, status);\r
- EX_FLD(mpt_entry, outprm, tavorprm_mpt_st, page_size);\r
- EX_FLD(mpt_entry, outprm, tavorprm_mpt_st, mem_key);\r
- EX_FLD(mpt_entry, outprm, tavorprm_mpt_st, pd);\r
- EX_FLD64(mpt_entry, outprm, tavorprm_mpt_st, start_address);\r
- EX_FLD64(mpt_entry, outprm, tavorprm_mpt_st, reg_wnd_len);\r
- EX_FLD(mpt_entry, outprm, tavorprm_mpt_st, lkey);\r
- EX_FLD(mpt_entry, outprm, tavorprm_mpt_st, win_cnt);\r
- EX_FLD(mpt_entry, outprm, tavorprm_mpt_st, win_cnt_limit);\r
- EX_FLD64_SH(mpt_entry, outprm, tavorprm_mpt_st, mtt_seg_adr);\r
- }\r
-\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_HW2SW_MPT\r
- */ \r
-THH_cmd_status_t THH_cmd_HW2SW_MPT(THH_cmd_t cmd_if, THH_mpt_index_t mpt_index,\r
- THH_mpt_entry_t *mpt_entry)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t outprm[PSEUDO_MT_BYTE_SIZE(tavorprm_mpt_st)];\r
- THH_cmd_status_t rc;\r
- u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_mpt_st);\r
-\r
- FUNC_IN;\r
- memset(outprm, 0, buf_size);\r
-\r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = (u_int32_t)mpt_index;\r
- cmd_desc.out_param = outprm;\r
- cmd_desc.out_param_size = buf_size;\r
- cmd_desc.out_trans = TRANS_MAILBOX;\r
- cmd_desc.opcode = TAVOR_IF_CMD_HW2SW_MPT;\r
- /* when output is not necessary putting 1 in opcode modifier\r
- will case the command execute faster */\r
- cmd_desc.opcode_modifier = mpt_entry ? 0 : 1;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_HW2SW_MPT;\r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- if ( rc != THH_CMD_STAT_OK ) {\r
- MT_RETURN(rc);\r
- }\r
- \r
- if ( mpt_entry ) {\r
- EX_FLD(mpt_entry, outprm, tavorprm_mpt_st, ver);\r
-\r
- EX_BOOL_FLD(mpt_entry, outprm, tavorprm_mpt_st, r_w);\r
- EX_BOOL_FLD(mpt_entry, outprm, tavorprm_mpt_st, pa);\r
- EX_BOOL_FLD(mpt_entry, outprm, tavorprm_mpt_st, lr);\r
- EX_BOOL_FLD(mpt_entry, outprm, tavorprm_mpt_st, lw);\r
- EX_BOOL_FLD(mpt_entry, outprm, tavorprm_mpt_st, rr);\r
- EX_BOOL_FLD(mpt_entry, outprm, tavorprm_mpt_st, rw);\r
- EX_BOOL_FLD(mpt_entry, outprm, tavorprm_mpt_st, a);\r
- EX_BOOL_FLD(mpt_entry, outprm, tavorprm_mpt_st, eb);\r
- EX_BOOL_FLD(mpt_entry, outprm, tavorprm_mpt_st, m_io);\r
- \r
- EX_FLD(mpt_entry, outprm, tavorprm_mpt_st, status);\r
- EX_FLD(mpt_entry, outprm, tavorprm_mpt_st, page_size);\r
- EX_FLD(mpt_entry, outprm, tavorprm_mpt_st, mem_key);\r
- EX_FLD(mpt_entry, outprm, tavorprm_mpt_st, pd);\r
- EX_FLD64(mpt_entry, outprm, tavorprm_mpt_st, start_address);\r
- EX_FLD64(mpt_entry, outprm, tavorprm_mpt_st, reg_wnd_len);\r
- EX_FLD(mpt_entry, outprm, tavorprm_mpt_st, lkey);\r
- EX_FLD(mpt_entry, outprm, tavorprm_mpt_st, win_cnt);\r
- EX_FLD(mpt_entry, outprm, tavorprm_mpt_st, win_cnt_limit);\r
- EX_FLD64_SH(mpt_entry, outprm, tavorprm_mpt_st, mtt_seg_adr);\r
- }\r
-\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_READ_MTT\r
- */ \r
-THH_cmd_status_t THH_cmd_READ_MTT(THH_cmd_t cmd_if, u_int64_t mtt_pa, MT_size_t num_elems,\r
- THH_mtt_entry_t *mtt_entry)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t *outprm, *iterator;\r
- int i, local_num_elts, elts_this_loop, max_elts_per_buffer;\r
- u_int32_t buf_size;\r
- u_int32_t mtt_pa_transfer[2];\r
- THH_cmd_status_t rc = THH_CMD_STAT_OK;\r
- MT_bool buf_align_adjust = TRUE;\r
- \r
- /* TBD: need to: a. limit number of entries in the mailbox */\r
- /* b. for performance, if the initial addr is odd, */\r
- /* do a loop of a single element, then do the rest */\r
-\r
-\r
- FUNC_IN;\r
- if (!num_elems) {\r
- MT_RETURN(THH_CMD_STAT_BAD_PARAM);\r
- }\r
-\r
- outprm = TNMALLOC(u_int8_t, MAX_OUT_PRM_SIZE);\r
- if ( !outprm ) {\r
- MT_RETURN(THH_CMD_STAT_EAGAIN);\r
- }\r
- memset(outprm, 0, MAX_OUT_PRM_SIZE);\r
-\r
- local_num_elts = (int)num_elems;\r
- max_elts_per_buffer = (MAX_OUT_PRM_SIZE - MTT_CMD_PA_PREAMBLE_SIZE) / ( PSEUDO_MT_BYTE_SIZE(tavorprm_mtt_st));\r
-\r
- while(local_num_elts > 0) {\r
-\r
- elts_this_loop = (local_num_elts > max_elts_per_buffer ? max_elts_per_buffer : local_num_elts);\r
-\r
- /* if the mtt_pa address is odd (3 LSBs ignored), and we need to use multiple commands */\r
- /* and we are also reading an odd number of elements, then decrease the elements in this loop */\r
- /* by one so that on the next go-around, the reading will start at an even mtt_pa address */\r
- /* If necessary, the adjustment needs to be performed only once */\r
- if ((buf_align_adjust) && (local_num_elts > max_elts_per_buffer) && ((mtt_pa>>3)& 0x1) && (!(elts_this_loop & 0x1))) {\r
- elts_this_loop--;\r
- buf_align_adjust = FALSE;\r
- }\r
-\r
- buf_size = elts_this_loop*PSEUDO_MT_BYTE_SIZE(tavorprm_mtt_st);\r
- memset(outprm, 0, buf_size);\r
- \r
- iterator = outprm;\r
-\r
- /* The command interface expects the mtt_pa format to be the HIGH order word first, */\r
- /* then the low-order word. The command interface adjusts endianness within words */\r
-\r
- mtt_pa_transfer[0]= (u_int32_t)(mtt_pa >> 32); /* MS-DWORD */\r
- mtt_pa_transfer[1]= (u_int32_t)(mtt_pa & 0xFFFFFFFF); /* LS-DWORD */ \r
- \r
- cmd_desc.in_param = (u_int8_t *)&(mtt_pa_transfer[0]);\r
- cmd_desc.in_param_size = sizeof(mtt_pa_transfer);\r
- cmd_desc.in_trans = TRANS_IMMEDIATE;\r
- cmd_desc.input_modifier = elts_this_loop;\r
- cmd_desc.out_param = outprm;\r
- cmd_desc.out_param_size = buf_size;\r
- cmd_desc.out_trans = TRANS_MAILBOX;\r
- cmd_desc.opcode = TAVOR_IF_CMD_READ_MTT;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_READ_MTT;\r
- \r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- if ( rc != THH_CMD_STAT_OK ) {\r
- FREE(outprm);\r
- MT_RETURN(rc);\r
- }\r
- \r
- if ( mtt_entry ) {\r
- for (i = 0; i < elts_this_loop; i++, mtt_entry++, iterator += PSEUDO_MT_BYTE_SIZE(tavorprm_mtt_st) ) {\r
- EX_FLD64_SH(mtt_entry, iterator, tavorprm_mtt_st, ptag);\r
- EX_BOOL_FLD(mtt_entry, iterator, tavorprm_mtt_st, p);\r
- }\r
- }\r
- \r
- if (rc != THH_CMD_STAT_OK) {\r
- FREE(outprm);\r
- MT_RETURN(rc);\r
- }\r
- /* update loop parameters */\r
- mtt_pa += elts_this_loop * PSEUDO_MT_BYTE_SIZE(tavorprm_mtt_st); /* incr target pointer */\r
- local_num_elts -= elts_this_loop;\r
- }\r
- FREE(outprm);\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_WRITE_MTT\r
- */ \r
-THH_cmd_status_t THH_cmd_WRITE_MTT(THH_cmd_t cmd_if, u_int64_t mtt_pa, MT_size_t num_elems,\r
- THH_mtt_entry_t *mtt_entry)\r
-{\r
-#if 1\r
- command_fields_t cmd_desc;\r
- u_int8_t *inprm, *iterator;\r
- int i, local_num_elts, elts_this_loop, max_elts_per_buffer;\r
- u_int32_t buf_size;\r
- THH_cmd_status_t rc = THH_CMD_STAT_OK;\r
- MT_bool buf_align_adjust = TRUE;\r
-\r
- /* TBD: need to: a. limit number of entries in the mailbox */\r
- /* b. for performance, if the initial addr is odd, */\r
- /* do one loop of an odd number of elements, then do the rest */\r
-\r
- FUNC_IN;\r
- if ( !STACK_OK ) MT_RETURN(THH_CMD_STAT_EFATAL);\r
- if (!num_elems) {\r
- MT_RETURN(THH_CMD_STAT_BAD_PARAM);\r
- }\r
-\r
- inprm = (u_int8_t*)MALLOC(MAX_IN_PRM_SIZE);\r
- if ( !inprm ) {\r
- MT_RETURN(THH_CMD_STAT_EAGAIN);\r
- }\r
- local_num_elts = (u_int32_t)num_elems;\r
- max_elts_per_buffer = (MAX_IN_PRM_SIZE - MTT_CMD_PA_PREAMBLE_SIZE) / ( PSEUDO_MT_BYTE_SIZE(tavorprm_mtt_st));\r
-\r
- MTL_DEBUG4("THH_cmd_WRITE_MTT: local_num_elts = %d, max_elts_per_buffer = %d\n",local_num_elts, max_elts_per_buffer);\r
- while(local_num_elts > 0) {\r
-\r
- elts_this_loop = (local_num_elts > max_elts_per_buffer ? max_elts_per_buffer : local_num_elts);\r
-\r
- /* if the mtt_pa address is odd (3 LSBs ignored), and we need to use multiple commands */\r
- /* and we are also writing an odd number of elements, then decrease the elements in this loop */\r
- /* by one so that on the next go-around, the writing will start at an even mtt_pa address */\r
- /* If necessary, the adjustment needs to be performed only once */\r
- if ((buf_align_adjust) && (local_num_elts > max_elts_per_buffer) && ((mtt_pa>>3)& 0x1) && (!(elts_this_loop & 0x1))) {\r
- elts_this_loop--;\r
- buf_align_adjust = FALSE;\r
- }\r
- if (elts_this_loop <= 0) {\r
- break;\r
- }\r
-\r
- buf_size = elts_this_loop*PSEUDO_MT_BYTE_SIZE(tavorprm_mtt_st) + MTT_CMD_PA_PREAMBLE_SIZE;\r
- memset(inprm, 0, buf_size);\r
- iterator = inprm;\r
- \r
- MTL_DEBUG4("THH_cmd_WRITE_MTT: elts_this_loop = %d, buf_size = %d, buf_align_adjust = %d\n",elts_this_loop, buf_size, buf_align_adjust);\r
- \r
- cmd_desc.in_param = inprm;\r
- cmd_desc.in_param_size = buf_size;\r
- cmd_desc.in_trans = TRANS_MAILBOX;\r
- cmd_desc.input_modifier = elts_this_loop;\r
- cmd_desc.out_param = 0;\r
- cmd_desc.out_param_size = 0;\r
- cmd_desc.out_trans = TRANS_NA;\r
- cmd_desc.opcode = TAVOR_IF_CMD_WRITE_MTT;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_WRITE_MTT;\r
- \r
- /* copy */\r
- ((u_int32_t*)iterator)[0]= (u_int32_t)(mtt_pa >> 32); /* MS-DWORD */\r
- ((u_int32_t*)iterator)[1]= (u_int32_t)(mtt_pa & 0xFFFFFFFF); /* LS-DWORD */ \r
-\r
- iterator += MTT_CMD_PA_PREAMBLE_SIZE;\r
- \r
- for (i = 0; i < elts_this_loop; i++, mtt_entry++, iterator += PSEUDO_MT_BYTE_SIZE(tavorprm_mtt_st) ) {\r
- INS_FLD64_SH(mtt_entry, iterator, tavorprm_mtt_st, ptag);\r
- INS_BOOL_FLD(mtt_entry, iterator, tavorprm_mtt_st, p);\r
- }\r
- \r
-\r
- THH_CMD_MAILBOX_PRINT(inprm, buf_size, __func__);\r
- THH_CMD_PRINT_MTT_ENTRIES(elts_this_loop, inprm);\r
-#if 1\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- if (rc != THH_CMD_STAT_OK) {\r
- FREE(inprm);\r
- MT_RETURN(rc);\r
- }\r
-#else\r
- MTL_DEBUG4("THH_cmd_WRITE_MTT: SKIPPING cmd_invoke\n");\r
- rc = THH_CMD_STAT_INTERNAL_ERR;\r
-#endif\r
- /* update loop parameters */\r
- mtt_pa += elts_this_loop * PSEUDO_MT_BYTE_SIZE(tavorprm_mtt_st); /* incr target pointer */\r
- local_num_elts -= elts_this_loop;\r
- }\r
- FREE(inprm);\r
- MT_RETURN(rc);\r
-#else\r
- FREE(inprm);\r
- MT_RETURN(THH_CMD_STAT_INTERNAL_ERR);\r
-#endif \r
-}\r
-\r
-\r
-THH_cmd_status_t THH_cmd_SYNC_TPT(THH_cmd_t cmd_if)\r
-{\r
- command_fields_t cmd_prms = {0};\r
- THH_cmd_status_t rc;\r
-\r
- FUNC_IN;\r
- cmd_prms.opcode = TAVOR_IF_CMD_SYNC_TPT;\r
- cmd_prms.in_trans = TRANS_NA;\r
- cmd_prms.out_trans = TRANS_NA;\r
- cmd_prms.exec_time_micro = TAVOR_IF_CMD_ETIME_SYNC_TPT;\r
- rc = cmd_invoke(cmd_if, &cmd_prms);\r
- if ( rc != THH_CMD_STAT_OK ) {\r
- MTL_ERROR1(MT_FLFMT("THH_cmd_SYNC_TPT failed: %s\n"), str_THH_cmd_status_t(rc));\r
- }\r
- MT_RETURN(rc);\r
-}\r
-\r
-\r
-/*\r
- * THH_cmd_MAP_EQ\r
- */ \r
-THH_cmd_status_t THH_cmd_MAP_EQ(THH_cmd_t cmd_if, THH_eqn_t eqn, u_int64_t event_mask)\r
-{\r
- command_fields_t cmd_desc;\r
- THH_cmd_status_t rc;\r
- u_int32_t event_mask_transfer[2];\r
-\r
- FUNC_IN;\r
-\r
-\r
- /* The command interface expects the event_mask format to be the HIGH order word first, */\r
- /* then the low-order word. The command interface adjusts endianness within words */\r
-\r
- event_mask_transfer[0]= (u_int32_t)(event_mask >> 32); /* MS-DWORD */\r
- event_mask_transfer[1]= (u_int32_t)(event_mask & 0xFFFFFFFF); /* LS-DWORD */ \r
-\r
- MTL_DEBUG4("THH_cmd_MAP_EQ: eqn = 0x%x, event_mask = "U64_FMT"\n", eqn, event_mask);\r
- MTL_DEBUG4("THH_cmd_MAP_EQ: event_mask_transfer [0] = 0x%x, event_mask_transfer [1] = 0x%x\n",\r
- event_mask_transfer[0], event_mask_transfer[1]);\r
-\r
- cmd_desc.in_param = (u_int8_t *)&(event_mask_transfer[0]);\r
- cmd_desc.in_param_size = sizeof(event_mask_transfer);\r
- cmd_desc.in_trans = TRANS_IMMEDIATE;\r
- cmd_desc.input_modifier = eqn;\r
- cmd_desc.out_param = 0;\r
- cmd_desc.out_param_size = 0;\r
- cmd_desc.out_trans = TRANS_NA;\r
- cmd_desc.opcode = TAVOR_IF_CMD_MAP_EQ;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_MAP_EQ;\r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_SW2HW_EQ\r
- */ \r
-THH_cmd_status_t THH_cmd_SW2HW_EQ(THH_cmd_t cmd_if, THH_eqn_t eqn, THH_eqc_t *eq_context)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t inprm[PSEUDO_MT_BYTE_SIZE(tavorprm_eqc_st)];\r
- THH_cmd_status_t rc;\r
- u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_eqc_st);\r
-\r
- FUNC_IN;\r
- if (eq_context == NULL) {MT_RETURN(THH_CMD_STAT_EBADARG); }\r
- memset(inprm, 0, buf_size);\r
-\r
- THH_CMD_PRINT_EQ_CONTEXT(eq_context);\r
-\r
- cmd_desc.in_param = inprm;\r
- cmd_desc.in_param_size = buf_size;\r
- cmd_desc.in_trans = TRANS_MAILBOX;\r
- cmd_desc.input_modifier = eqn;\r
- cmd_desc.out_param = 0;\r
- cmd_desc.out_param_size = 0;\r
- cmd_desc.out_trans = TRANS_NA;\r
- cmd_desc.opcode = TAVOR_IF_CMD_SW2HW_EQ;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_SW2HW_EQ;\r
-\r
- INS_FLD(eq_context, inprm, tavorprm_eqc_st, st);\r
-\r
- INS_BOOL_FLD(eq_context, inprm, tavorprm_eqc_st, oi);\r
- INS_BOOL_FLD(eq_context, inprm, tavorprm_eqc_st, tr);\r
-\r
- INS_FLD(eq_context, inprm, tavorprm_eqc_st, owner);\r
- INS_FLD(eq_context, inprm, tavorprm_eqc_st, status);\r
- INS_FLD64(eq_context, inprm, tavorprm_eqc_st, start_address);\r
- INS_FLD(eq_context, inprm, tavorprm_eqc_st, usr_page);\r
- INS_FLD(eq_context, inprm, tavorprm_eqc_st, log_eq_size);\r
- INS_FLD(eq_context, inprm, tavorprm_eqc_st, pd);\r
- INS_FLD(eq_context, inprm, tavorprm_eqc_st, intr);\r
- INS_FLD(eq_context, inprm, tavorprm_eqc_st, lost_count);\r
- INS_FLD(eq_context, inprm, tavorprm_eqc_st, lkey);\r
- INS_FLD(eq_context, inprm, tavorprm_eqc_st, consumer_indx);\r
- INS_FLD(eq_context, inprm, tavorprm_eqc_st, producer_indx);\r
- THH_CMD_MAILBOX_PRINT(inprm, buf_size, __func__);\r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_HW2SW_EQ\r
- */ \r
-THH_cmd_status_t THH_cmd_HW2SW_EQ(THH_cmd_t cmd_if, THH_eqn_t eqn, THH_eqc_t *eq_context)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t outprm[PSEUDO_MT_BYTE_SIZE(tavorprm_mpt_st)];\r
- THH_cmd_status_t rc;\r
- u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_mpt_st);\r
-\r
- FUNC_IN;\r
- memset(outprm, 0, buf_size);\r
-\r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = eqn;\r
- cmd_desc.out_param = outprm;\r
- cmd_desc.out_param_size = buf_size;\r
- cmd_desc.out_trans = TRANS_MAILBOX;\r
- cmd_desc.opcode = TAVOR_IF_CMD_HW2SW_EQ;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_HW2SW_EQ;\r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- if ( rc != THH_CMD_STAT_OK ) {\r
- MT_RETURN(rc);\r
- }\r
- \r
- if ( eq_context ) {\r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, st);\r
- EX_BOOL_FLD(eq_context, outprm, tavorprm_eqc_st, oi);\r
- EX_BOOL_FLD(eq_context, outprm, tavorprm_eqc_st, tr);\r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, owner);\r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, status);\r
- EX_FLD64(eq_context, outprm, tavorprm_eqc_st, start_address);\r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, usr_page);\r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, log_eq_size);\r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, pd);\r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, intr);\r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, lost_count);\r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, lkey);\r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, consumer_indx);\r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, producer_indx);\r
- }\r
-\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_QUERY_EQ\r
- */ \r
-THH_cmd_status_t THH_cmd_QUERY_EQ(THH_cmd_t cmd_if, THH_eqn_t eqn, THH_eqc_t *eq_context)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t outprm[PSEUDO_MT_BYTE_SIZE(tavorprm_eqc_st)];\r
- THH_cmd_status_t rc;\r
- u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_eqc_st);\r
-\r
- FUNC_IN;\r
- memset(outprm, 0, buf_size);\r
-\r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = eqn;\r
- cmd_desc.out_param = outprm;\r
- cmd_desc.out_param_size = buf_size;\r
- cmd_desc.out_trans = TRANS_MAILBOX;\r
- cmd_desc.opcode = TAVOR_IF_CMD_HW2SW_EQ;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_HW2SW_EQ;\r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- if ( rc != THH_CMD_STAT_OK ) {\r
- MT_RETURN(rc);\r
- }\r
- \r
- if ( eq_context ) {\r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, st);\r
-\r
- EX_BOOL_FLD(eq_context, outprm, tavorprm_eqc_st, oi);\r
- EX_BOOL_FLD(eq_context, outprm, tavorprm_eqc_st, tr);\r
- \r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, owner);\r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, status);\r
- EX_FLD64(eq_context, outprm, tavorprm_eqc_st, start_address);\r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, usr_page);\r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, log_eq_size);\r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, pd);\r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, intr);\r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, lost_count);\r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, lkey);\r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, consumer_indx);\r
- EX_FLD(eq_context, outprm, tavorprm_eqc_st, producer_indx);\r
- }\r
-\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_SW2HW_EQ\r
- */ \r
-THH_cmd_status_t THH_cmd_SW2HW_CQ(THH_cmd_t cmd_if, HH_cq_hndl_t cqn, THH_cqc_t *cq_context)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t inprm[PSEUDO_MT_BYTE_SIZE(tavorprm_completion_queue_context_st)];\r
- THH_cmd_status_t rc;\r
- u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_completion_queue_context_st);\r
-\r
- FUNC_IN;\r
- if (cq_context == NULL) {MT_RETURN(THH_CMD_STAT_EBADARG); }\r
- memset(inprm, 0, buf_size);\r
-\r
- THH_CMD_PRINT_CQ_CONTEXT(cq_context);\r
-\r
- cmd_desc.in_param = inprm;\r
- cmd_desc.in_param_size = buf_size;\r
- cmd_desc.in_trans = TRANS_MAILBOX;\r
- cmd_desc.input_modifier = cqn;\r
- cmd_desc.out_param = 0;\r
- cmd_desc.out_param_size = 0;\r
- cmd_desc.out_trans = TRANS_NA;\r
- cmd_desc.opcode = TAVOR_IF_CMD_SW2HW_CQ;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_SW2HW_CQ;\r
-\r
- INS_FLD(cq_context, inprm, tavorprm_completion_queue_context_st, st);\r
-\r
- INS_BOOL_FLD(cq_context, inprm, tavorprm_completion_queue_context_st, oi);\r
- INS_BOOL_FLD(cq_context, inprm, tavorprm_completion_queue_context_st, tr);\r
- \r
- INS_FLD(cq_context, inprm, tavorprm_completion_queue_context_st, status);\r
- INS_FLD64(cq_context, inprm, tavorprm_completion_queue_context_st, start_address);\r
- INS_FLD(cq_context, inprm, tavorprm_completion_queue_context_st, usr_page);\r
- INS_FLD(cq_context, inprm, tavorprm_completion_queue_context_st, log_cq_size);\r
- INS_FLD(cq_context, inprm, tavorprm_completion_queue_context_st, e_eqn);\r
- INS_FLD(cq_context, inprm, tavorprm_completion_queue_context_st, c_eqn);\r
- INS_FLD(cq_context, inprm, tavorprm_completion_queue_context_st, pd);\r
- INS_FLD(cq_context, inprm, tavorprm_completion_queue_context_st, l_key);\r
- INS_FLD(cq_context, inprm, tavorprm_completion_queue_context_st, last_notified_indx);\r
- INS_FLD(cq_context, inprm, tavorprm_completion_queue_context_st, solicit_producer_indx);\r
- INS_FLD(cq_context, inprm, tavorprm_completion_queue_context_st, consumer_indx);\r
- INS_FLD(cq_context, inprm, tavorprm_completion_queue_context_st, producer_indx);\r
- INS_FLD(cq_context, inprm, tavorprm_completion_queue_context_st, cqn);\r
- THH_CMD_MAILBOX_PRINT(inprm, buf_size, __func__);\r
-#if 1\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
-#else\r
- MTL_DEBUG4("THH_cmd_SW2HW_CG: SKIPPING cmd_invoke !!!!!!!!!\n");\r
- rc = THH_CMD_STAT_OK;\r
-#endif\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_HW2SW_EQ\r
- */ \r
-THH_cmd_status_t THH_cmd_HW2SW_CQ(THH_cmd_t cmd_if, HH_cq_hndl_t cqn, THH_cqc_t *cq_context)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t outprm[PSEUDO_MT_BYTE_SIZE(tavorprm_completion_queue_context_st)];\r
- THH_cmd_status_t rc;\r
- u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_completion_queue_context_st);\r
-\r
- FUNC_IN;\r
- MTL_DEBUG4("THH_cmd_HW2SW_CQ: cqn = 0x%x, cq_context = 0x%p\n", cqn, cq_context);\r
- memset(outprm, 0, buf_size);\r
-\r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = cqn;\r
- cmd_desc.out_param = outprm;\r
- cmd_desc.out_param_size = buf_size;\r
- cmd_desc.out_trans = TRANS_MAILBOX;\r
- cmd_desc.opcode = TAVOR_IF_CMD_HW2SW_CQ;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_HW2SW_CQ;\r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- if ( rc != THH_CMD_STAT_OK ) {\r
- MT_RETURN(rc);\r
- }\r
- \r
-\r
- if ( cq_context ) {\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, st);\r
- \r
- EX_BOOL_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, oi);\r
- EX_BOOL_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, tr);\r
- \r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, status);\r
- EX_FLD64(cq_context, outprm, tavorprm_completion_queue_context_st, start_address);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, usr_page);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, log_cq_size);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, e_eqn);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, c_eqn);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, pd);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, l_key);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, last_notified_indx);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, solicit_producer_indx);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, consumer_indx);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, producer_indx);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, cqn);\r
- THH_CMD_PRINT_CQ_CONTEXT(cq_context);\r
- }\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_QUERY_CQ\r
- */ \r
-THH_cmd_status_t THH_cmd_QUERY_CQ(THH_cmd_t cmd_if, HH_cq_hndl_t cqn, THH_cqc_t *cq_context)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t outprm[PSEUDO_MT_BYTE_SIZE(tavorprm_completion_queue_context_st)];\r
- THH_cmd_status_t rc;\r
- u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_completion_queue_context_st);\r
-\r
- FUNC_IN;\r
- memset(outprm, 0, buf_size);\r
-\r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = cqn;\r
- cmd_desc.out_param = outprm;\r
- cmd_desc.out_param_size = buf_size;\r
- cmd_desc.out_trans = TRANS_MAILBOX;\r
- cmd_desc.opcode = TAVOR_IF_CMD_QUERY_CQ;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_QUERY_CQ;\r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- if ( rc != THH_CMD_STAT_OK ) {\r
- MT_RETURN(rc);\r
- }\r
- \r
- if ( cq_context ) {\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, st);\r
- \r
- EX_BOOL_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, oi);\r
- EX_BOOL_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, tr);\r
- \r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, status);\r
- EX_FLD64(cq_context, outprm, tavorprm_completion_queue_context_st, start_address);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, usr_page);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, log_cq_size);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, e_eqn);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, c_eqn);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, pd);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, l_key);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, last_notified_indx);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, solicit_producer_indx);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, consumer_indx);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, producer_indx);\r
- EX_FLD(cq_context, outprm, tavorprm_completion_queue_context_st, cqn);\r
- THH_CMD_PRINT_CQ_CONTEXT(cq_context);\r
- }\r
-\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_RESIZE_CQ\r
- */ \r
-THH_cmd_status_t THH_cmd_RESIZE_CQ(THH_cmd_t cmd_if, HH_cq_hndl_t cqn, \r
- u_int64_t start_address, u_int32_t l_key, u_int8_t log_cq_size,\r
- u_int32_t *new_producer_index_p)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int32_t inprm[PSEUDO_MT_BYTE_SIZE(tavorprm_resize_cq_st)];\r
- THH_cmd_status_t rc;\r
- const u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_resize_cq_st);\r
- u_int32_t out_param_tmp[2];\r
-\r
- FUNC_IN;\r
- memset(inprm, 0, buf_size);\r
-\r
- cmd_desc.in_param = (u_int8_t*)inprm;\r
- cmd_desc.in_param_size = buf_size;\r
- cmd_desc.in_trans = TRANS_MAILBOX;\r
- cmd_desc.input_modifier = cqn;\r
- cmd_desc.out_trans = TRANS_IMMEDIATE;\r
- cmd_desc.out_param = (u_int8_t*)out_param_tmp;\r
- cmd_desc.opcode = TAVOR_IF_CMD_RESIZE_CQ;\r
- cmd_desc.opcode_modifier = new_producer_index_p ? 0 /* legacy mode */: \r
- 1 /* fixed resize: new_pi= old_pi % new_size */;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_RESIZE_CQ;\r
-\r
- memset(inprm,0,buf_size);\r
- inprm[MT_BYTE_OFFSET(tavorprm_resize_cq_st, start_addr_h) >> 2]= (u_int32_t)(start_address >> 32);\r
- inprm[MT_BYTE_OFFSET(tavorprm_resize_cq_st, start_addr_l) >> 2]= (u_int32_t)(start_address & 0xFFFFFFFF);\r
- inprm[MT_BYTE_OFFSET(tavorprm_resize_cq_st, l_key) >> 2]= l_key;\r
- MT_INSERT_ARRAY32(inprm, log_cq_size , \r
- MT_BIT_OFFSET(tavorprm_resize_cq_st, log_cq_size), MT_BIT_SIZE(tavorprm_resize_cq_st, log_cq_size)) ;\r
- //MTL_ERROR1(MT_FLFMT("RESIZE_CQ: mailbox[0-3]= 0x%X 0x%X 0x%X 0x%X"),inprm[0],inprm[1],inprm[2],inprm[3]);\r
- THH_CMD_MAILBOX_PRINT(inprm, buf_size, __func__);\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- if (new_producer_index_p) *new_producer_index_p= out_param_tmp[0]; /* new producer index is in out_param_h */\r
- MT_RETURN(rc);\r
-}\r
-\r
-\r
-/*\r
- * GET_QP_CMD_EXEC_TIME -- returns QP command exec time in microseconds\r
- */ \r
-static u_int32_t get_qp_cmd_exec_time(THH_qpee_transition_t trans)\r
-{\r
- switch(trans) {\r
- case QPEE_TRANS_RST2INIT:\r
- return TAVOR_IF_CMD_ETIME_RST2INIT_QPEE;\r
- case QPEE_TRANS_INIT2INIT:\r
- return TAVOR_IF_CMD_ETIME_INIT2INIT_QPEE;\r
- case QPEE_TRANS_INIT2RTR:\r
- return TAVOR_IF_CMD_ETIME_INIT2RTR_QPEE;\r
- case QPEE_TRANS_RTR2RTS:\r
- return TAVOR_IF_CMD_ETIME_RTR2RTS_QPEE;\r
- case QPEE_TRANS_RTS2RTS:\r
- return TAVOR_IF_CMD_ETIME_RTS2RTS_QPEE;\r
- case QPEE_TRANS_SQERR2RTS:\r
- return TAVOR_IF_CMD_ETIME_SQERR2RTS_QPEE;\r
- case QPEE_TRANS_SQD2RTS:\r
- return TAVOR_IF_CMD_ETIME_SQD2RTS_QPEE;\r
- case QPEE_TRANS_2ERR:\r
- return TAVOR_IF_CMD_ETIME_2ERR_QPEE;\r
- case QPEE_TRANS_RTS2SQD:\r
- return TAVOR_IF_CMD_ETIME_RTS2SQD;\r
- case QPEE_TRANS_ERR2RST:\r
- return TAVOR_IF_CMD_ETIME_ERR2RST_QPEE;\r
- default:\r
- MTL_ERROR1(MT_FLFMT("no such qp transition exists \n")); \r
- return 0;\r
- }\r
-}\r
-/*\r
- * THH_cmd_MODIFY_QPEE \r
- * is_ee: 0 = QP, 1 = EE\r
- */ \r
-static THH_cmd_status_t THH_cmd_MODIFY_QPEE( THH_cmd_t cmd_if, MT_bool is_ee, u_int32_t qpn, THH_qpee_transition_t trans,\r
- THH_qpee_context_t *qp_context,u_int32_t optparammask)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t *inprm = NULL;\r
- THH_cmd_status_t rc;\r
- u_int32_t buf_size, sqd_event_req;\r
- u_int32_t temp_u32;\r
- tavor_if_qp_state_t tavor_if_qp_state;\r
-\r
- FUNC_IN;\r
- \r
- /* we save the value of sqd_event bit in xaction field & clr it to receive a normal xaction value. */\r
- sqd_event_req = trans & THH_CMD_SQD_EVENT_REQ;\r
- trans &= ~THH_CMD_SQD_EVENT_REQ; \r
- \r
- CMDS_DBG("%s: TRANSACTION val = 0x%x\n", __func__, trans);\r
-\r
- /* see which transition was requested */\r
- switch(trans) {\r
- /* have input mailbox only */\r
- case QPEE_TRANS_RST2INIT:\r
- case QPEE_TRANS_INIT2INIT:\r
- case QPEE_TRANS_INIT2RTR:\r
- case QPEE_TRANS_RTR2RTS:\r
- case QPEE_TRANS_RTS2RTS:\r
- case QPEE_TRANS_SQERR2RTS:\r
- case QPEE_TRANS_SQD2RTS:\r
- if (qp_context == NULL) {MT_RETURN(THH_CMD_STAT_EBADARG); }\r
- \r
- inprm = (u_int8_t *)MALLOC(PSEUDO_MT_BYTE_SIZE(tavorprm_qp_ee_state_transitions_st));\r
- if (inprm == NULL) {\r
- MT_RETURN(THH_CMD_STAT_EAGAIN);\r
- }\r
- \r
- buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_qp_ee_state_transitions_st);\r
- memset(inprm, 0, buf_size);\r
-\r
- cmd_desc.in_param = inprm;\r
- cmd_desc.in_param_size = buf_size;\r
- cmd_desc.in_trans = TRANS_MAILBOX;\r
- cmd_desc.input_modifier = qpn | (is_ee ? 0x1000000 : 0);\r
- cmd_desc.out_param = 0;\r
- cmd_desc.out_param_size = 0;\r
- cmd_desc.out_trans = TRANS_NA;\r
- cmd_desc.opcode = (tavor_if_cmd_t)trans;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = get_qp_cmd_exec_time(trans);\r
-\r
- THH_CMD_PRINT_QP_CONTEXT(qp_context);\r
-\r
- /* translate VAPI qp state to Tavor qp state, and fail if not valid*/\r
- if (!THH_vapi_qpstate_2_tavor_qpstate(qp_context->state, &tavor_if_qp_state)) {\r
- CMDS_DBG("%s: VAPI QP state (0x%x) is not valid\n", __func__, qp_context->state);\r
- rc = THH_CMD_STAT_EFATAL;\r
- goto retn;\r
- }\r
-\r
- MT_INSERT_ARRAY32(inprm, optparammask, MT_BIT_OFFSET(tavorprm_qp_ee_state_transitions_st, opt_param_mask), \r
- MT_BIT_SIZE(tavorprm_qp_ee_state_transitions_st, opt_param_mask));\r
-\r
- // 'te' field has been removed.\r
- //QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, te);\r
- QP_INS_BOOL_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, de);\r
-\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st,pm_state);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, st);\r
-\r
- MT_INSERT_ARRAY32(inprm, tavor_if_qp_state, MT_BIT_OFFSET(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.state), \r
- MT_BIT_SIZE(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.state));\r
- \r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, sched_queue);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, msg_max);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, mtu);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, usr_page);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, local_qpn_een);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, remote_qpn_een);\r
-\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.pkey_index);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.port_number);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.rlid);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.my_lid_path_bits);\r
- \r
- QP_INS_BOOL_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.g);\r
- \r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.rnr_retry);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.hop_limit);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.max_stat_rate);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.mgid_index);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.ack_timeout);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.flow_label);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.tclass);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.sl);\r
-\r
- memcpy(&temp_u32, &(qp_context->primary_address_path.rgid[0]), sizeof(u_int32_t));\r
- MT_INSERT_ARRAY32(inprm, MOSAL_be32_to_cpu(temp_u32), \r
- MT_BIT_OFFSET(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.primary_address_path.rgid_127_96),\r
- MT_BIT_SIZE(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.primary_address_path.rgid_127_96));\r
- \r
- memcpy(&temp_u32, &(qp_context->primary_address_path.rgid[4]), sizeof(u_int32_t));\r
- MT_INSERT_ARRAY32(inprm, MOSAL_be32_to_cpu(temp_u32), \r
- MT_BIT_OFFSET(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.primary_address_path.rgid_95_64),\r
- MT_BIT_SIZE(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.primary_address_path.rgid_95_64));\r
-\r
- memcpy(&temp_u32, &(qp_context->primary_address_path.rgid[8]), sizeof(u_int32_t));\r
- MT_INSERT_ARRAY32(inprm, MOSAL_be32_to_cpu(temp_u32), \r
- MT_BIT_OFFSET(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.primary_address_path.rgid_63_32),\r
- MT_BIT_SIZE(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.primary_address_path.rgid_63_32));\r
-\r
- memcpy(&temp_u32, &(qp_context->primary_address_path.rgid[12]), sizeof(u_int32_t));\r
- MT_INSERT_ARRAY32(inprm, MOSAL_be32_to_cpu(temp_u32), \r
- MT_BIT_OFFSET(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.primary_address_path.rgid_31_0),\r
- MT_BIT_SIZE(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.primary_address_path.rgid_31_0));\r
-\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.pkey_index);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.port_number);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.rlid);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.my_lid_path_bits);\r
- \r
- QP_INS_BOOL_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.g);\r
-\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.rnr_retry);\r
-\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.hop_limit);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.max_stat_rate);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.mgid_index);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.ack_timeout);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.flow_label);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.tclass);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.sl);\r
-\r
- memcpy(&temp_u32, &(qp_context->alternative_address_path.rgid[0]), sizeof(u_int32_t));\r
- MT_INSERT_ARRAY32(inprm, MOSAL_be32_to_cpu(temp_u32), \r
- MT_BIT_OFFSET(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.alternative_address_path.rgid_127_96),\r
- MT_BIT_SIZE(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.alternative_address_path.rgid_127_96));\r
- \r
- memcpy(&temp_u32, &(qp_context->alternative_address_path.rgid[4]), sizeof(u_int32_t));\r
- MT_INSERT_ARRAY32(inprm, MOSAL_be32_to_cpu(temp_u32), \r
- MT_BIT_OFFSET(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.alternative_address_path.rgid_95_64),\r
- MT_BIT_SIZE(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.alternative_address_path.rgid_95_64));\r
-\r
- memcpy(&temp_u32, &(qp_context->alternative_address_path.rgid[8]), sizeof(u_int32_t));\r
- MT_INSERT_ARRAY32(inprm, MOSAL_be32_to_cpu(temp_u32), \r
- MT_BIT_OFFSET(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.alternative_address_path.rgid_63_32),\r
- MT_BIT_SIZE(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.alternative_address_path.rgid_63_32));\r
-\r
- memcpy(&temp_u32, &(qp_context->alternative_address_path.rgid[12]), sizeof(u_int32_t));\r
- MT_INSERT_ARRAY32(inprm, MOSAL_be32_to_cpu(temp_u32), \r
- MT_BIT_OFFSET(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.alternative_address_path.rgid_31_0),\r
- MT_BIT_SIZE(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.alternative_address_path.rgid_31_0));\r
-\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, rdd);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, pd);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, wqe_base_adr);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, wqe_lkey);\r
- \r
- QP_INS_BOOL_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, ssc);\r
- QP_INS_BOOL_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, sic);\r
- QP_INS_BOOL_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, sae);\r
- QP_INS_BOOL_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, swe);\r
- QP_INS_BOOL_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, sre);\r
- \r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, retry_count);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, sra_max);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, flight_lim);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, ack_req_freq);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, next_send_psn);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, cqn_snd);\r
- QP_INS_FLD64(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, next_snd_wqe);\r
- \r
- QP_INS_BOOL_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, rsc);\r
- QP_INS_BOOL_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, ric);\r
- QP_INS_BOOL_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, rae);\r
- QP_INS_BOOL_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, rwe);\r
- QP_INS_BOOL_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, rre);\r
- \r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, rra_max);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, next_rcv_psn);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, min_rnr_nak);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, ra_buff_indx);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, cqn_rcv);\r
- QP_INS_FLD64(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, next_rcv_wqe);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, q_key);\r
- QP_INS_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, srqn);\r
- \r
- QP_INS_BOOL_FLD(qp_context, inprm, tavorprm_qp_ee_state_transitions_st, srq);\r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- goto retn;\r
-\r
- /* No mailboxes, and no immed data */\r
- case QPEE_TRANS_2ERR:\r
- case QPEE_TRANS_RTS2SQD:\r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = qpn | ( (sqd_event_req && (trans == QPEE_TRANS_RTS2SQD)) ? TAVOR_IF_SQD_EVENT_FLAG:0 );\r
- cmd_desc.input_modifier |= (is_ee ? 0x1000000 : 0);\r
- cmd_desc.out_param = 0;\r
- cmd_desc.out_param_size = 0;\r
- cmd_desc.out_trans = TRANS_NA;\r
- cmd_desc.opcode = (tavor_if_cmd_t)trans;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = get_qp_cmd_exec_time(trans);\r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- goto retn;\r
-\r
- /* output mailbox only */\r
- /* matan: this is now the ANY2RST xition. */\r
- case QPEE_TRANS_ERR2RST:\r
-\r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = qpn | (is_ee ? 0x1000000 : 0);\r
- cmd_desc.out_param = 0; /* not using outbox */\r
- cmd_desc.out_param_size = 0; /* not using outbox */\r
- cmd_desc.out_trans = TRANS_MAILBOX;\r
- cmd_desc.opcode = (tavor_if_cmd_t)trans;\r
- /* matan: ANY2RST is always called with (opcode_modifier |= 2), meaning no need \r
- to move into ERR before RST. Also, set LSB so that no outbox will be generated */\r
- cmd_desc.opcode_modifier = 3 ; /* bits 0 and 1 set */\r
- cmd_desc.exec_time_micro = get_qp_cmd_exec_time(trans);\r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- goto retn;\r
- default:\r
- MTL_ERROR1("%s: BAD TRANSACTION val = 0x%x\n", __func__, trans);\r
- CMDS_DBG("%s: BAD TRANSACTION val = 0x%x\n", __func__, trans);\r
- MT_RETURN(THH_CMD_STAT_EBADARG);\r
- }\r
- MT_RETURN(THH_CMD_STAT_EFATAL); // ??? BAD_ARG ??\r
-\r
-retn:\r
- if (inprm != NULL) {\r
- FREE(inprm);\r
- }\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_MODIFY_QP \r
- */ \r
-THH_cmd_status_t THH_cmd_MODIFY_QP(THH_cmd_t cmd_if, IB_wqpn_t qpn,\r
- THH_qpee_transition_t trans,\r
- THH_qpee_context_t *qp_context,\r
- u_int32_t optparammask)\r
-{\r
- CMDS_DBG("%s: TRANSACTION val = 0x%x\n", __func__, trans);\r
- return (THH_cmd_MODIFY_QPEE(cmd_if,0,qpn,trans,qp_context,optparammask));\r
-}\r
-\r
-/*\r
- * THH_cmd_MODIFY_EE \r
- */ \r
-THH_cmd_status_t THH_cmd_MODIFY_EE(THH_cmd_t cmd_if, IB_eecn_t eecn,\r
- THH_qpee_transition_t trans,\r
- THH_qpee_context_t *ee_context,\r
- u_int32_t optparammask)\r
-{\r
- return (THH_cmd_MODIFY_QPEE(cmd_if,1,eecn,trans,ee_context,optparammask));\r
-}\r
-\r
-\r
-/*\r
- * THH_cmd_QUERY_QPEE \r
- */ \r
-#ifdef VXWORKS_OS\r
-static void THH_cmd_QUERY_QPEE_fill(THH_qpee_context_t *qp_context,u_int8_t *outprm)\r
-{\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, rdd);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, pd);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, wqe_base_adr);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, wqe_lkey);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, ssc);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, sic);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, sae);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, swe);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, sre);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, retry_count);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, sra_max);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, flight_lim);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, ack_req_freq);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, next_send_psn);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, cqn_snd);\r
- QP_EX_FLD64(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, next_snd_wqe);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, rsc);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, ric);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, rae);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, rwe);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, rre);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, rra_max);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, next_rcv_psn);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, min_rnr_nak);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, ra_buff_indx);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, cqn_rcv);\r
- QP_EX_FLD64(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, next_rcv_wqe);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, q_key);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, srqn);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, srq);\r
- /* THH_CMD_PRINT_QP_CONTEXT(qp_context); */\r
-}\r
-#endif\r
-static THH_cmd_status_t THH_cmd_QUERY_QPEE( THH_cmd_t cmd_if, MT_bool is_ee, u_int32_t qpn,\r
- THH_qpee_context_t *qp_context)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t *outprm;\r
- THH_cmd_status_t rc;\r
- u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_qp_ee_state_transitions_st);\r
- u_int32_t temp_u32;\r
- tavor_if_qp_state_t tavor_if_qp_state;\r
- \r
- FUNC_IN;\r
- outprm = TNMALLOC(u_int8_t, buf_size);\r
- if ( !outprm ) {\r
- MT_RETURN(THH_CMD_STAT_EAGAIN);\r
- }\r
- memset(outprm, 0, buf_size);\r
-\r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = qpn;\r
- cmd_desc.out_param = outprm;\r
- cmd_desc.out_param_size = buf_size;\r
- cmd_desc.out_trans = TRANS_MAILBOX;\r
- cmd_desc.opcode = TAVOR_IF_CMD_QUERY_QPEE;\r
- cmd_desc.opcode_modifier = is_ee ? 1 : 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_QUERY_QPEE;\r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- if ( rc != THH_CMD_STAT_OK ) {\r
- FREE(outprm);\r
- MT_RETURN(rc);\r
- }\r
-\r
- if ( qp_context ) {\r
- // 'te' field has been removed.\r
- //QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, te);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, de);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, pm_state);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, st);\r
-\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, sched_queue);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, msg_max);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, mtu);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, usr_page);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, local_qpn_een);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, remote_qpn_een);\r
-\r
- tavor_if_qp_state = (tavor_if_qp_state_t) \r
- MT_EXTRACT_ARRAY32(outprm, MT_BIT_OFFSET(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.state), \r
- MT_BIT_SIZE(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.state));\r
- if(!THH_tavor_qpstate_2_vapi_qpstate(tavor_if_qp_state, &(qp_context->state))){\r
- CMDS_DBG("%s: TAVOR QP state (0x%x) is not valid\n", __func__, tavor_if_qp_state);\r
- FREE(outprm);\r
- return THH_CMD_STAT_EFATAL;\r
- }\r
- \r
- /*T.D.(matan): change along with the rest of SQ_DRAINING improvements.*/\r
- qp_context->sq_draining = (qp_context->state & THH_CMD_QP_DRAINING_FLAG) ? TRUE:FALSE;\r
- qp_context->state = (VAPI_qp_state_t) (qp_context->state & ~(THH_CMD_QP_DRAINING_FLAG));\r
-\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.pkey_index);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.port_number);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.rlid);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.my_lid_path_bits);\r
-\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.g);\r
-\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.rnr_retry);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.hop_limit);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.max_stat_rate);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.mgid_index);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.ack_timeout);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.flow_label);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.tclass);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, primary_address_path.sl);\r
-\r
- /* extract RGID. Note that get the RGID from the command object as 4 double-words, each in CPU-endianness. */\r
- /* Need to take them one at a time, and convert each to big-endian before storing in the output RGID array */\r
- /* Note that need to memcpy each 4 bytes to a temporary u_int32_t variable, since there is no guarantee */\r
- /* that the RGID is 4-byte aligned (it is an array of unsigned chars) */\r
- temp_u32 = MOSAL_cpu_to_be32(MT_EXTRACT_ARRAY32(outprm, \r
- MT_BIT_OFFSET(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.primary_address_path.rgid_127_96),\r
- MT_BIT_SIZE(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.primary_address_path.rgid_127_96)));\r
- memcpy(&(qp_context->primary_address_path.rgid[0]), &temp_u32, sizeof(u_int32_t));\r
-\r
- temp_u32 = MOSAL_cpu_to_be32(MT_EXTRACT_ARRAY32(outprm, \r
- MT_BIT_OFFSET(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.primary_address_path.rgid_95_64),\r
- MT_BIT_SIZE(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.primary_address_path.rgid_95_64)));\r
- memcpy(&(qp_context->primary_address_path.rgid[4]), &temp_u32, sizeof(u_int32_t));\r
-\r
- temp_u32 = MOSAL_cpu_to_be32(MT_EXTRACT_ARRAY32(outprm, \r
- MT_BIT_OFFSET(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.primary_address_path.rgid_63_32),\r
- MT_BIT_SIZE(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.primary_address_path.rgid_63_32)));\r
- memcpy(&(qp_context->primary_address_path.rgid[8]), &temp_u32, sizeof(u_int32_t));\r
-\r
- temp_u32 = MOSAL_cpu_to_be32(MT_EXTRACT_ARRAY32(outprm, \r
- MT_BIT_OFFSET(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.primary_address_path.rgid_31_0),\r
- MT_BIT_SIZE(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.primary_address_path.rgid_31_0)));\r
- memcpy(&(qp_context->primary_address_path.rgid[12]), &temp_u32, sizeof(u_int32_t));\r
-\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.pkey_index);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.port_number);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.rlid);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.my_lid_path_bits);\r
- \r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.g);\r
- \r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.rnr_retry);\r
-\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.hop_limit);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.max_stat_rate);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.mgid_index);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.ack_timeout);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.flow_label);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.tclass);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, alternative_address_path.sl);\r
-\r
- /* extract RGID. Note that get the RGID from the command object as 4 double-words, each in CPU-endianness. */\r
- /* Need to take them one at a time, and convert each to big-endian before storing in the output RGID array */\r
- /* Note that need to memcpy each 4 bytes to a temporary u_int32_t variable, since there is no guarantee */\r
- /* that the RGID is 4-byte aligned (it is an array of unsigned chars) */\r
- temp_u32 = MOSAL_cpu_to_be32(MT_EXTRACT_ARRAY32(outprm, \r
- MT_BIT_OFFSET(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.alternative_address_path.rgid_127_96),\r
- MT_BIT_SIZE(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.alternative_address_path.rgid_127_96)));\r
- memcpy(&(qp_context->alternative_address_path.rgid[0]), &temp_u32, sizeof(u_int32_t));\r
-\r
- temp_u32 = MOSAL_cpu_to_be32(MT_EXTRACT_ARRAY32(outprm, \r
- MT_BIT_OFFSET(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.alternative_address_path.rgid_95_64),\r
- MT_BIT_SIZE(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.alternative_address_path.rgid_95_64)));\r
- memcpy(&(qp_context->alternative_address_path.rgid[4]), &temp_u32, sizeof(u_int32_t));\r
-\r
- temp_u32 = MOSAL_cpu_to_be32(MT_EXTRACT_ARRAY32(outprm, \r
- MT_BIT_OFFSET(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.alternative_address_path.rgid_63_32),\r
- MT_BIT_SIZE(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.alternative_address_path.rgid_63_32)));\r
- memcpy(&(qp_context->alternative_address_path.rgid[8]), &temp_u32, sizeof(u_int32_t));\r
-\r
- temp_u32 = MOSAL_cpu_to_be32(MT_EXTRACT_ARRAY32(outprm, \r
- MT_BIT_OFFSET(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.alternative_address_path.rgid_31_0),\r
- MT_BIT_SIZE(tavorprm_qp_ee_state_transitions_st, qpc_eec_data.alternative_address_path.rgid_31_0)));\r
- memcpy(&(qp_context->alternative_address_path.rgid[12]), &temp_u32, sizeof(u_int32_t));\r
-\r
- /* TBD: ???? following code beak Vapi in Vxworks.\r
- * If compile without inline code, then it work.\r
- * It look like compiler error with optimization\r
- */ \r
-#ifndef VXWORKS_OS \r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, rdd);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, pd);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, wqe_base_adr);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, wqe_lkey);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, ssc);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, sic);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, sae);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, swe);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, sre);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, retry_count);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, sra_max);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, flight_lim);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, ack_req_freq);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, next_send_psn);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, cqn_snd);\r
- QP_EX_FLD64(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, next_snd_wqe);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, rsc);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, ric);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, rae);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, rwe);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, rre);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, rra_max);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, next_rcv_psn);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, min_rnr_nak);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, ra_buff_indx);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, cqn_rcv);\r
- QP_EX_FLD64(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, next_rcv_wqe);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, q_key);\r
- QP_EX_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, srqn);\r
- QP_EX_BOOL_FLD(qp_context, outprm, tavorprm_qp_ee_state_transitions_st, srq);\r
- /* THH_CMD_PRINT_QP_CONTEXT(qp_context); */\r
- }\r
-\r
-#else\r
- THH_cmd_QUERY_QPEE_fill(qp_context,outprm);\r
-#endif \r
-\r
- FREE(outprm);\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_QUERY_QP \r
- */ \r
-THH_cmd_status_t THH_cmd_QUERY_QP(THH_cmd_t cmd_if, IB_wqpn_t qpn,\r
- THH_qpee_context_t *qp_context)\r
-{\r
- return (THH_cmd_QUERY_QPEE(cmd_if,0,qpn,qp_context));\r
-}\r
-/*\r
- * THH_cmd_QUERY_EE \r
- */ \r
-THH_cmd_status_t THH_cmd_QUERY_EE(THH_cmd_t cmd_if, IB_eecn_t eecn,\r
- THH_qpee_context_t *ee_context)\r
-{\r
- return (THH_cmd_QUERY_QPEE(cmd_if,1,eecn,ee_context));\r
-}\r
-\r
-/*\r
- * THH_cmd_CONF_SPECIAL_QP \r
- */ \r
-THH_cmd_status_t THH_cmd_CONF_SPECIAL_QP(THH_cmd_t cmd_if, VAPI_special_qp_t qp_type,\r
- IB_wqpn_t base_qpn)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t op_modifier;\r
- THH_cmd_status_t rc;\r
-\r
- FUNC_IN;\r
- MTL_DEBUG4("%s: ENTERING \n", __func__);\r
- switch(qp_type) {\r
- case VAPI_SMI_QP:\r
- op_modifier = 0;\r
- break;\r
- case VAPI_GSI_QP:\r
- op_modifier = 1;\r
- break;\r
- case VAPI_RAW_IPV6_QP:\r
- op_modifier = 2;\r
- break;\r
- case VAPI_RAW_ETY_QP:\r
- op_modifier = 3;\r
- break;\r
- default:\r
- MT_RETURN (THH_CMD_STAT_EBADARG);\r
- }\r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = base_qpn;\r
- cmd_desc.out_param = 0;\r
- cmd_desc.out_param_size = 0;\r
- cmd_desc.out_trans = TRANS_NA;\r
- cmd_desc.opcode = TAVOR_IF_CMD_CONF_SPECIAL_QP;\r
- cmd_desc.opcode_modifier = op_modifier;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_CONF_SPECIAL_QP;\r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_MAD_IFC \r
- */ \r
-THH_cmd_status_t THH_cmd_MAD_IFC(THH_cmd_t cmd_if, \r
- MT_bool mkey_validate, \r
- IB_lid_t slid, /* SLID is ignored if mkey_validate is false */\r
- IB_port_t port,\r
- void *mad_in, \r
- void *mad_out)\r
-{\r
- struct cmd_if_context_st *cmdif_p = (struct cmd_if_context_st *)cmd_if;\r
- command_fields_t cmd_desc;\r
- THH_cmd_status_t rc;\r
- u_int32_t i, *int32_inbuf, *int32_outbuf, *orig_inbuf = NULL, *int32_temp_inbuf = NULL;\r
- \r
- /* support NULL mad_out */\r
- static u_int32_t dummy_mad_out[256/sizeof(u_int32_t)]; /* STATIC ! (not on stack) */\r
- \r
-\r
- FUNC_IN;\r
- if (mad_in == NULL) return THH_CMD_STAT_EBADARG;\r
- int32_temp_inbuf = (u_int32_t*)MALLOC(256);\r
- if (int32_temp_inbuf == NULL) {\r
- MT_RETURN(THH_CMD_STAT_EAGAIN);\r
- }\r
- int32_inbuf = (u_int32_t *) mad_in;\r
- int32_outbuf = (u_int32_t *) (mad_out == NULL ? dummy_mad_out : mad_out);\r
- orig_inbuf = int32_temp_inbuf;\r
-\r
- cmd_desc.in_param = (u_int8_t *) int32_temp_inbuf;\r
- cmd_desc.in_param_size = 256;\r
- cmd_desc.in_trans = TRANS_MAILBOX;\r
- cmd_desc.input_modifier = (port & 3);\r
- /* For Mkey validation the MAD's source LID is required (upper 16 bits of input mod.) */\r
- if ((mkey_validate) &&\r
- (THH_FW_VER_VALUE(cmdif_p->fw_props.fw_rev_major,\r
- cmdif_p->fw_props.fw_rev_minor,\r
- cmdif_p->fw_props.fw_rev_subminor) > THH_FW_VER_VALUE(1,0x17,0) ) ) {\r
- /* SLID for MAD_IFC is supported only after 1.17.0000 */\r
- cmd_desc.input_modifier |= ( ((u_int32_t)slid) << 16 );\r
- }\r
- cmd_desc.out_param = (u_int8_t*)int32_outbuf;\r
- cmd_desc.out_param_size = 256;\r
- cmd_desc.out_trans = TRANS_MAILBOX;\r
- cmd_desc.opcode = TAVOR_IF_CMD_MAD_IFC;\r
- cmd_desc.opcode_modifier = mkey_validate ? 0 : 1;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_MAD_IFC;\r
- \r
- /* reverse endianness to CPU endian, since MAD frames are all BE*/\r
- for (i = 0; i < 256/(sizeof(u_int32_t)); i++) {\r
- *int32_temp_inbuf = MOSAL_be32_to_cpu(*int32_inbuf);\r
- int32_inbuf++;\r
- int32_temp_inbuf++;\r
- }\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- /* reverse endianness to big endian, since information is gotten cpu-endian*/\r
- for (i = 0; i < 256/(sizeof(u_int32_t)); i++) {\r
- *int32_outbuf = MOSAL_cpu_to_be32(*int32_outbuf);\r
- int32_outbuf++;\r
- }\r
- FREE(orig_inbuf);\r
- THH_CMD_MAILBOX_PRINT(mad_out, 256, __func__);\r
- MT_RETURN(rc);\r
-}\r
-\r
-\r
-THH_cmd_status_t THH_cmd_SW2HW_SRQ(THH_cmd_t cmd_if,\r
- u_int32_t srqn, /* SRQ number/index */\r
- THH_srq_context_t *srqc_p) /* SRQ context */\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t inprm[PSEUDO_MT_BYTE_SIZE(tavorprm_srq_context_st)];\r
- THH_cmd_status_t rc;\r
- const u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_srq_context_st);\r
-\r
- FUNC_IN;\r
- if (srqc_p == NULL) {MT_RETURN(THH_CMD_STAT_EBADARG); }\r
- memset(inprm, 0, buf_size);\r
- INS_FLD(srqc_p, inprm, tavorprm_srq_context_st, pd);\r
- INS_FLD(srqc_p, inprm, tavorprm_srq_context_st, uar);\r
- INS_FLD(srqc_p, inprm, tavorprm_srq_context_st, l_key);\r
- INS_FLD(srqc_p, inprm, tavorprm_srq_context_st, wqe_addr_h);\r
- INS_FLD(srqc_p, inprm, tavorprm_srq_context_st, next_wqe_addr_l);\r
- INS_FLD(srqc_p, inprm, tavorprm_srq_context_st, ds);\r
-\r
- cmd_desc.in_param = inprm;\r
- cmd_desc.in_param_size = buf_size;\r
- cmd_desc.in_trans = TRANS_MAILBOX;\r
- cmd_desc.input_modifier = srqn;\r
- cmd_desc.out_param = 0;\r
- cmd_desc.out_param_size = 0;\r
- cmd_desc.out_trans = TRANS_NA;\r
- cmd_desc.opcode = TAVOR_IF_CMD_SW2HW_SRQ;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_CLASS_C;\r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- MT_RETURN(rc);\r
-}\r
-\r
-THH_cmd_status_t THH_cmd_HW2SW_SRQ(THH_cmd_t cmd_if,\r
- u_int32_t srqn, /* SRQ number/index */\r
- THH_srq_context_t *srqc_p) /* SRQ context */\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t outprm[PSEUDO_MT_BYTE_SIZE(tavorprm_srq_context_st)];\r
- THH_cmd_status_t rc;\r
- const u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_srq_context_st);\r
-\r
- FUNC_IN;\r
- memset(outprm, 0, buf_size);\r
-\r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = srqn;\r
- cmd_desc.out_param = srqc_p != NULL ? outprm : 0;\r
- cmd_desc.out_param_size = srqc_p != NULL ? buf_size : 0;\r
- cmd_desc.out_trans = TRANS_MAILBOX;\r
- cmd_desc.opcode = TAVOR_IF_CMD_HW2SW_SRQ;\r
- cmd_desc.opcode_modifier = srqc_p != NULL ? 1 : 0; /* No need for output if no *srqc_p */\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_CLASS_C;\r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- \r
- if (srqc_p != NULL) {\r
- EX_FLD(srqc_p, outprm, tavorprm_srq_context_st, pd);\r
- EX_FLD(srqc_p, outprm, tavorprm_srq_context_st, uar);\r
- EX_FLD(srqc_p, outprm, tavorprm_srq_context_st, l_key);\r
- EX_FLD(srqc_p, outprm, tavorprm_srq_context_st, wqe_addr_h);\r
- EX_FLD(srqc_p, outprm, tavorprm_srq_context_st, next_wqe_addr_l);\r
- EX_FLD(srqc_p, outprm, tavorprm_srq_context_st, ds);\r
- EX_FLD(srqc_p, outprm, tavorprm_srq_context_st, wqe_cnt);\r
- EX_FLD(srqc_p, outprm, tavorprm_srq_context_st, state);\r
- }\r
- MT_RETURN(rc);\r
-}\r
-\r
-THH_cmd_status_t THH_cmd_QUERY_SRQ(THH_cmd_t cmd_if,\r
- u_int32_t srqn, /* SRQ number/index */\r
- THH_srq_context_t *srqc_p) /* SRQ context */\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t outprm[PSEUDO_MT_BYTE_SIZE(tavorprm_srq_context_st)];\r
- THH_cmd_status_t rc;\r
- const u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_srq_context_st);\r
-\r
- FUNC_IN;\r
- if (srqc_p == NULL) {MT_RETURN(THH_CMD_STAT_EBADARG); }\r
- memset(outprm, 0, buf_size);\r
-\r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = srqn;\r
- cmd_desc.out_param = outprm;\r
- cmd_desc.out_param_size = buf_size;\r
- cmd_desc.out_trans = TRANS_MAILBOX;\r
- cmd_desc.opcode = TAVOR_IF_CMD_QUERY_SRQ;\r
- cmd_desc.opcode_modifier = 0; \r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_CLASS_C;\r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- \r
- if (srqc_p != NULL){\r
- EX_FLD(srqc_p, outprm, tavorprm_srq_context_st, pd);\r
- EX_FLD(srqc_p, outprm, tavorprm_srq_context_st, uar);\r
- EX_FLD(srqc_p, outprm, tavorprm_srq_context_st, l_key);\r
- EX_FLD(srqc_p, outprm, tavorprm_srq_context_st, wqe_addr_h);\r
- EX_FLD(srqc_p, outprm, tavorprm_srq_context_st, next_wqe_addr_l);\r
- EX_FLD(srqc_p, outprm, tavorprm_srq_context_st, ds);\r
- EX_FLD(srqc_p, outprm, tavorprm_srq_context_st, wqe_cnt);\r
- EX_FLD(srqc_p, outprm, tavorprm_srq_context_st, state);\r
- }\r
- MT_RETURN(rc);\r
-}\r
-\r
-\r
-/*\r
- * THH_cmd_READ_MGM \r
- */ \r
-THH_cmd_status_t THH_cmd_READ_MGM(THH_cmd_t cmd_if, u_int32_t mcg_index,\r
- MT_size_t max_qp_per_mcg, THH_mcg_entry_t *mcg_entry)\r
-{\r
- // need to add qps_per_mcg_entry field\r
- command_fields_t cmd_desc;\r
- u_int8_t *outprm;\r
- THH_cmd_status_t rc;\r
- IB_wqpn_t /**qp_buf,*/ *qp_iterator;\r
- u_int32_t buf_size, i, num_active_qps_found, temp_u32;\r
- u_int8_t valid;\r
-\r
- FUNC_IN;\r
-\r
- /* the default mcg_entry structure contains space for 8 qps per mcg */\r
- /* If HCA is configured for more than 8 qps per group, space for the extra qp entries */\r
- /* must be allocated as well */\r
- buf_size = (u_int32_t)(PSEUDO_MT_BYTE_SIZE(tavorprm_mgm_entry_st) + \r
- ((max_qp_per_mcg - 8)*PSEUDO_MT_BYTE_SIZE(tavorprm_mgmqp_st)));\r
-\r
- outprm = (u_int8_t*)MALLOC(buf_size);\r
- if ( !outprm ) {\r
- MT_RETURN(THH_CMD_STAT_EAGAIN);\r
- }\r
-\r
- memset(outprm, 0, buf_size);\r
-\r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = mcg_index;\r
- cmd_desc.out_param = outprm;\r
- cmd_desc.out_param_size = buf_size;\r
- cmd_desc.out_trans = TRANS_MAILBOX;\r
- cmd_desc.opcode = TAVOR_IF_CMD_READ_MGM;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_READ_MGM;\r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- if ( rc != THH_CMD_STAT_OK ) {\r
- goto invoke_err;\r
- }\r
- \r
- if ( mcg_entry ) {\r
- /* allocate memory for the multicast QPs IB_wqpn_t */\r
- //qp_buf = (IB_wqpn_t *)MALLOC(sizeof(IB_wqpn_t) * max_qp_per_mcg); \r
- //if ( !qp_buf ) {\r
- // rc = THH_CMD_STAT_EAGAIN;\r
- //goto malloc_err;\r
- //}\r
- //memset(qp_buf, 0, sizeof(IB_wqpn_t) * max_qp_per_mcg);\r
-\r
- /* get fixed portion of reply */\r
- EX_FLD(mcg_entry, outprm, tavorprm_mgm_entry_st, next_gid_index);\r
-\r
- /* extract MGID. Note that get the MGID from the command object as 4 double-words, each in CPU-endianness. */\r
- /* Need to take them one at a time, and convert each to big-endian before storing in the output MGID array */\r
- /* Note that need to memcpy each 4 bytes to a temporary u_int32_t variable, since there is no guarantee */\r
- /* that the MGID is 4-byte aligned (it is an array of unsigned chars) */\r
- temp_u32 = MOSAL_cpu_to_be32(MT_EXTRACT_ARRAY32(outprm, \r
- MT_BIT_OFFSET(tavorprm_mgm_entry_st, mgid_128_96),\r
- MT_BIT_SIZE(tavorprm_mgm_entry_st, mgid_128_96)));\r
- memcpy(&(mcg_entry->mgid[0]), &temp_u32, sizeof(u_int32_t));\r
-\r
- temp_u32 = MOSAL_cpu_to_be32(MT_EXTRACT_ARRAY32(outprm, \r
- MT_BIT_OFFSET(tavorprm_mgm_entry_st, mgid_95_64),\r
- MT_BIT_SIZE(tavorprm_mgm_entry_st, mgid_95_64)));\r
- memcpy(&(mcg_entry->mgid[4]), &temp_u32, sizeof(u_int32_t));\r
-\r
- temp_u32 = MOSAL_cpu_to_be32(MT_EXTRACT_ARRAY32(outprm, \r
- MT_BIT_OFFSET(tavorprm_mgm_entry_st, mgid_63_32),\r
- MT_BIT_SIZE(tavorprm_mgm_entry_st, mgid_63_32)));\r
- memcpy(&(mcg_entry->mgid[8]), &temp_u32, sizeof(u_int32_t));\r
-\r
- temp_u32 = MOSAL_cpu_to_be32(MT_EXTRACT_ARRAY32(outprm, \r
- MT_BIT_OFFSET(tavorprm_mgm_entry_st, mgid_31_0),\r
- MT_BIT_SIZE(tavorprm_mgm_entry_st, mgid_31_0)));\r
- memcpy(&(mcg_entry->mgid[12]), &temp_u32, sizeof(u_int32_t));\r
-\r
- /* Now, extract the QP entries in the group */\r
- for (i = 0, num_active_qps_found = 0, qp_iterator = mcg_entry->qps/*qp_buf*/; i < max_qp_per_mcg; i++ ) {\r
- /* extract VALID bit for each QP. If valid is set, extract the QP number and insert in */\r
- /* the QP array returned */\r
- valid = (u_int8_t)(MT_EXTRACT_ARRAY32(outprm, \r
- (MT_BIT_OFFSET(tavorprm_mgm_entry_st, mgmqp_0.qi) + i*(MT_BIT_SIZE(tavorprm_mgm_entry_st, mgmqp_0))),\r
- MT_BIT_SIZE(tavorprm_mgm_entry_st, mgmqp_0.qi) ));\r
- if (valid) {\r
- /* NULL protection .. */\r
- if (mcg_entry->qps) {\r
- *((u_int32_t *) qp_iterator) = MT_EXTRACT_ARRAY32(outprm, \r
- (MT_BIT_OFFSET(tavorprm_mgm_entry_st, mgmqp_0.qpn_i) + i*(MT_BIT_SIZE(tavorprm_mgm_entry_st, mgmqp_0))),\r
- MT_BIT_SIZE(tavorprm_mgm_entry_st, mgmqp_0.qpn_i) );\r
- qp_iterator++;\r
- }\r
- num_active_qps_found++;\r
- }\r
- }\r
- mcg_entry->valid_qps = num_active_qps_found;\r
- /* If valid QPs found, return the allocated QP number buffer and number found. Otherwise */\r
- /* return 0 QPs and delete the buffer */\r
- //if (num_active_qps_found) {\r
- // mcg_entry->qps = qp_buf;\r
- //} else {\r
- // mcg_entry->qps = NULL;\r
- // FREE(qp_buf);\r
- //}\r
- }\r
-\r
-invoke_err:\r
- FREE(outprm);\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_WRITE_MGM \r
- */ \r
-THH_cmd_status_t THH_cmd_WRITE_MGM(THH_cmd_t cmd_if, u_int32_t mcg_index,\r
- MT_size_t max_qp_per_mcg, THH_mcg_entry_t *mcg_entry)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t inprm[PSEUDO_MT_BYTE_SIZE(tavorprm_mgm_entry_st)];\r
- THH_cmd_status_t rc;\r
- u_int32_t buf_size = PSEUDO_MT_BYTE_SIZE(tavorprm_mgm_entry_st);\r
- IB_wqpn_t *qp_iterator;\r
- u_int32_t i, temp_u32;\r
-\r
- FUNC_IN;\r
- \r
- CMDS_DBG("THH_cmd_WRITE_MGM: index=%u, max_qp_per_mcg = "SIZE_T_FMT"\n", mcg_index, max_qp_per_mcg);\r
- if (mcg_entry == NULL) {MT_RETURN(THH_CMD_STAT_EBADARG); }\r
- THH_CMD_PRINT_MGM_ENTRY(mcg_entry);\r
- memset(inprm, 0, buf_size);\r
-\r
- cmd_desc.in_param = inprm;\r
- cmd_desc.in_param_size = buf_size;\r
- cmd_desc.in_trans = TRANS_MAILBOX;\r
- cmd_desc.input_modifier = mcg_index;\r
- cmd_desc.out_param = 0;\r
- cmd_desc.out_param_size = 0;\r
- cmd_desc.out_trans = TRANS_NA;\r
- cmd_desc.opcode = TAVOR_IF_CMD_WRITE_MGM;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_WRITE_MGM;\r
-\r
- /* get fixed portion of reply */\r
- INS_FLD(mcg_entry, inprm, tavorprm_mgm_entry_st, next_gid_index);\r
-\r
- /* insert MGID. Note that get the MGID from the command object as 4 double-words, each in CPU-endianness. */\r
- /* Need to take them one at a time, and convert each to big-endian before storing in the output MGID array */\r
- memcpy(&temp_u32, &(mcg_entry->mgid[0]), sizeof(u_int32_t));\r
- MT_INSERT_ARRAY32(inprm, MOSAL_be32_to_cpu(temp_u32), \r
- MT_BIT_OFFSET(tavorprm_mgm_entry_st, mgid_128_96),\r
- MT_BIT_SIZE(tavorprm_mgm_entry_st, mgid_128_96));\r
- \r
- memcpy(&temp_u32, &(mcg_entry->mgid[4]), sizeof(u_int32_t));\r
- MT_INSERT_ARRAY32(inprm, MOSAL_be32_to_cpu(temp_u32), \r
- MT_BIT_OFFSET(tavorprm_mgm_entry_st, mgid_95_64),\r
- MT_BIT_SIZE(tavorprm_mgm_entry_st, mgid_95_64));\r
- \r
- memcpy(&temp_u32, &(mcg_entry->mgid[8]), sizeof(u_int32_t));\r
- MT_INSERT_ARRAY32(inprm, MOSAL_be32_to_cpu(temp_u32), \r
- MT_BIT_OFFSET(tavorprm_mgm_entry_st, mgid_63_32),\r
- MT_BIT_SIZE(tavorprm_mgm_entry_st, mgid_63_32));\r
-\r
- memcpy(&temp_u32, &(mcg_entry->mgid[12]), sizeof(u_int32_t));\r
- MT_INSERT_ARRAY32(inprm, MOSAL_be32_to_cpu(temp_u32), \r
- MT_BIT_OFFSET(tavorprm_mgm_entry_st, mgid_31_0),\r
- MT_BIT_SIZE(tavorprm_mgm_entry_st, mgid_31_0));\r
-\r
- /* Now, insert the QP entries in the group */\r
- for (i = 0, qp_iterator = mcg_entry->qps; i < max_qp_per_mcg; i++, qp_iterator++ ) {\r
- /* Insert valid entries. First, insert a VALID bit = 1 for each valid QP number, then insert */\r
- /* the QP number itself. If there are no more valid entries, insert only a VALID bit = 0 for each */\r
- /* invalid entry, up to the maximum allowed QPs */\r
- if (i < mcg_entry->valid_qps) {\r
- MT_INSERT_ARRAY32(inprm, 1, \r
- (MT_BIT_OFFSET(tavorprm_mgm_entry_st, mgmqp_0.qi) + i*(MT_BIT_SIZE(tavorprm_mgm_entry_st, mgmqp_0))),\r
- MT_BIT_SIZE(tavorprm_mgm_entry_st, mgmqp_0.qi) );\r
- MT_INSERT_ARRAY32(inprm, *((u_int32_t *) qp_iterator) , \r
- (MT_BIT_OFFSET(tavorprm_mgm_entry_st, mgmqp_0.qpn_i) + i*(MT_BIT_SIZE(tavorprm_mgm_entry_st, mgmqp_0))),\r
- MT_BIT_SIZE(tavorprm_mgm_entry_st, mgmqp_0.qpn_i) );\r
- } else {\r
- MT_INSERT_ARRAY32(inprm, 0, \r
- (MT_BIT_OFFSET(tavorprm_mgm_entry_st, mgmqp_0.qi) + i*(MT_BIT_SIZE(tavorprm_mgm_entry_st, mgmqp_0))),\r
- MT_BIT_SIZE(tavorprm_mgm_entry_st, mgmqp_0.qi) );\r
- }\r
- }\r
- THH_CMD_MAILBOX_PRINT(inprm, buf_size, __func__); \r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- MT_RETURN(rc);\r
-}\r
-\r
-/*\r
- * THH_cmd_HASH \r
- */ \r
-THH_cmd_status_t THH_cmd_MGID_HASH(THH_cmd_t cmd_if, IB_gid_t mgid, THH_mcg_hash_t *hash_val)\r
-{\r
- command_fields_t cmd_desc;\r
- u_int8_t inprm[16];\r
- THH_cmd_status_t rc;\r
- u_int32_t out_param[2], temp_u32;\r
- \r
- FUNC_IN;\r
- memset(inprm, 0, 16);\r
- memset(out_param, 0, sizeof(out_param));\r
-\r
- cmd_desc.in_param = inprm;\r
- cmd_desc.in_param_size = sizeof(IB_gid_t);\r
- cmd_desc.in_trans = TRANS_MAILBOX;\r
- cmd_desc.input_modifier = 0;\r
- cmd_desc.out_param = (u_int8_t *)&(out_param[0]);\r
- cmd_desc.out_param_size = sizeof(out_param);\r
- cmd_desc.out_trans = TRANS_IMMEDIATE;\r
- cmd_desc.opcode = TAVOR_IF_CMD_MGID_HASH;\r
- cmd_desc.opcode_modifier = 0;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_MGID_HASH;\r
-\r
- /* insert GID into mailbox, 1 double-word at a time. Modify byte ordering within doubl-words */\r
- /* to cpu-endian, so that lower layers will properly process the GID */\r
- memcpy(&temp_u32, &(mgid[0]), sizeof(u_int32_t));\r
- MT_INSERT_ARRAY32(inprm, MOSAL_be32_to_cpu(temp_u32),0,32);\r
- memcpy(&temp_u32, &(mgid[4]), sizeof(u_int32_t));\r
- MT_INSERT_ARRAY32(inprm, MOSAL_be32_to_cpu(temp_u32),32,32);\r
- memcpy(&temp_u32, &(mgid[8]), sizeof(u_int32_t));\r
- MT_INSERT_ARRAY32(inprm, MOSAL_be32_to_cpu(temp_u32),64,32); \r
- memcpy(&temp_u32, &(mgid[12]), sizeof(u_int32_t));\r
- MT_INSERT_ARRAY32(inprm, MOSAL_be32_to_cpu(temp_u32),96,32); \r
-\r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
-\r
- /* Note that output result is directly inserted into hash_val parameter, in cpu-endian order */\r
- /* Only the first of the two output double-words needs to be copied. */\r
- CMDS_DBG( "THH_cmd_MGID_HASH: out_param[0] = 0x%x; out_param[1] = 0x%x\n", \r
- out_param[0], out_param[1]);\r
-\r
- *hash_val = (THH_mcg_hash_t)MT_EXTRACT32(out_param[1],0,16);\r
- MT_RETURN(rc);\r
-}\r
-\r
-#if defined(MT_SUSPEND_QP)\r
-THH_cmd_status_t THH_cmd_SUSPEND_QP(THH_cmd_t cmd_if, u_int32_t qpn, MT_bool suspend_flag)\r
-{\r
- command_fields_t cmd_desc;\r
- THH_cmd_status_t rc;\r
- FUNC_IN;\r
- \r
- MTL_DEBUG2(MT_FLFMT("%s: qpn = 0x%x, suspend_flag = %s"), \r
- __func__, qpn, ((suspend_flag==TRUE) ? "TRUE" : "FALSE" ));\r
- cmd_desc.in_param = 0;\r
- cmd_desc.in_param_size = 0;\r
- cmd_desc.in_trans = TRANS_NA;\r
- cmd_desc.input_modifier = qpn & 0xFFFFFF;\r
- //cmd_desc.input_modifier |= (is_ee ? 0x1000000 : 0);\r
- cmd_desc.out_param = 0;\r
- cmd_desc.out_param_size = 0;\r
- cmd_desc.out_trans = TRANS_NA;\r
- cmd_desc.opcode = (suspend_flag == TRUE) ? TAVOR_IF_CMD_SUSPEND_QPEE : TAVOR_IF_CMD_UNSUSPEND_QPEE;\r
- cmd_desc.opcode_modifier = 1;\r
- cmd_desc.exec_time_micro = TAVOR_IF_CMD_ETIME_CLASS_C;\r
- \r
- rc = cmd_invoke(cmd_if, &cmd_desc);\r
- MTL_DEBUG2(MT_FLFMT("%s: qpn = 0x%x, command returned 0x%x"), __func__,qpn, rc);\r
- MT_RETURN(rc);\r
-}\r
-#endif\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include <tddrmm.h>\r
-#include <mtl_common.h>\r
-#include <tlog2.h>\r
-#include <extbuddy.h>\r
-#include <mosal.h>\r
-\r
-\r
-#define ELSE_ACQ_ERROR(f) else { MTL_ERROR1("%s MOSAL_mutex_acq failed\n", f); }\r
-#define logIfErr(f) \\r
- if (rc != HH_OK) { MTL_ERROR1("%s: rc=%s\n", f, HH_strerror_sym(rc)); }\r
-\r
-\r
-typedef struct THH_ddrmm_st\r
-{\r
- MT_phys_addr_t mem_base;\r
- MT_size_t mem_sz;\r
- Extbuddy_hndl xb;\r
- MOSAL_mutex_t mtx; /* protect xb */\r
-} DDRMM_t;\r
-\r
-\r
-/************************************************************************/\r
-/************************************************************************/\r
-/* private functions */\r
-\r
-/************************************************************************/\r
-static int well_alligned(MT_phys_addr_t mem_base, MT_size_t mem_sz)\r
-{\r
- unsigned int lg2sz = ceil_log2(mem_sz);\r
- MT_phys_addr_t mask = (1ul << lg2sz) - 1;\r
- MT_phys_addr_t residue = mem_base & mask;\r
- return (residue == 0);\r
-} /* well_alligned */\r
-\r
-\r
-/************************************************************************/\r
-static void lookup_sort(\r
- MT_size_t n,\r
- const MT_size_t* sizes,\r
- MT_size_t* lut\r
-)\r
-{\r
- unsigned int i, i1, j;\r
- for (i = 0; i != n; lut[i] = i, ++i); /* identity init */\r
- for (i = 0, i1 = 1; i1 != n; i = i1++) /* small n, so Bubble sort O(n^2) */\r
- {\r
- MT_size_t luiMax = i;\r
- MT_size_t iMax = sizes[ lut[i] ];\r
- for (j = i1; j != n; ++j)\r
- {\r
- MT_size_t v = sizes[ lut[j] ];\r
- if (iMax < v)\r
- {\r
- iMax = v;\r
- luiMax = j;\r
- }\r
- }\r
- j = (unsigned int)lut[i]; lut[i] = lut[luiMax]; lut[luiMax] = j; /* swap */\r
- }\r
-} /* lookup_sort */\r
-\r
-\r
-/************************************************************************/\r
-/************************************************************************/\r
-/* interface functions */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_ddrmm_create(\r
- MT_phys_addr_t mem_base, /* IN */\r
- MT_size_t mem_sz, /* IN */\r
- THH_ddrmm_t* ddrmm_p /* OUT */\r
-)\r
-{\r
- HH_ret_t rc = HH_OK;\r
- Extbuddy_hndl xb = NULL;\r
- DDRMM_t* mm = NULL;\r
-\r
- MTL_TRACE1("{THH_ddrmm_create: base="U64_FMT", sz="SIZE_T_FMT"\n", \r
- (u_int64_t)mem_base, mem_sz);\r
- if (!well_alligned(mem_base, mem_sz))\r
- {\r
- rc = HH_EINVAL;\r
- }\r
- else\r
- {\r
- xb = extbuddy_create((u_int32_t) mem_sz, 0);\r
- mm = (xb ? TMALLOC(DDRMM_t) : NULL);\r
- }\r
- if (mm == NULL)\r
- {\r
- rc = HH_EAGAIN;\r
- }\r
- else\r
- {\r
- mm->mem_base = mem_base;\r
- mm->mem_sz = mem_sz;\r
- mm->xb = xb;\r
- MOSAL_mutex_init(&mm->mtx);\r
- *ddrmm_p = mm;\r
- }\r
- MTL_TRACE1("}THH_ddrmm_create: ddrmm=%p\n", *ddrmm_p);\r
-// logIfErr("THH_ddrmm_create")\r
- return rc;\r
-} /* THH_ddrmm_create */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_ddrmm_destroy(THH_ddrmm_t ddrmm)\r
-{\r
- HH_ret_t rc = HH_OK;\r
- MTL_TRACE1("{THH_ddrmm_destroy: ddrmm=%p\n", ddrmm);\r
- extbuddy_destroy(ddrmm->xb);\r
- MOSAL_mutex_free(&ddrmm->mtx); \r
- FREE(ddrmm);\r
- MTL_TRACE1("}THH_ddrmm_destroy\n");\r
- logIfErr("THH_ddrmm_destroy")\r
- return rc;\r
-} /* THH_ddrmm_destroy */\r
-\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_ddrmm_reserve (\r
- THH_ddrmm_t ddrmm, /* IN */\r
- MT_phys_addr_t addr, /* IN */\r
- MT_size_t size /* IN */\r
-)\r
-{\r
- MT_bool ok = FALSE;\r
- HH_ret_t rc;\r
- \r
- MTL_TRACE1("{THH_ddrmm_reserve: ddrmm=%p, addr="U64_FMT", size="SIZE_T_FMT"\n",\r
- ddrmm, (u_int64_t)addr, size);\r
- MOSAL_mutex_acq_ui(&ddrmm->mtx);\r
- MTL_DEBUG4(MT_FLFMT("rel="U64_FMT", size="SIZE_T_FMT""), \r
- (u_int64_t)(addr - ddrmm->mem_base), size);\r
- ok = extbuddy_reserve(ddrmm->xb, (u_int32_t)(addr - ddrmm->mem_base), (u_int32_t)size);\r
- MOSAL_mutex_rel(&ddrmm->mtx);\r
- rc = (ok ? HH_OK : HH_EINVAL);\r
- MTL_TRACE1("}THH_ddrmm_reserve\n");\r
- logIfErr("THH_ddrmm_reserve")\r
- return rc;\r
-} /* THH_ddrmm_reserve */\r
-\r
-\r
-/************************************************************************/\r
-/* Note: For chunks in the array of size THH_DDRMM_INVALID_SZ, no allocation is made */\r
-HH_ret_t THH_ddrmm_alloc_sz_aligned(\r
- THH_ddrmm_t ddrmm, /* IN */\r
- MT_size_t num_o_chunks, /* IN */\r
- MT_size_t* chunks_log2_sizes, /* IN */\r
- MT_phys_addr_t* chunks_addrs /* OUT */\r
-)\r
-{\r
- HH_ret_t rc = HH_EAGAIN;\r
- MT_size_t* slut; /* Sorted Look-Up Table - (:politely incorrect:) */\r
-\r
- MTL_TRACE1("{THH_ddrmm_alloc_sz_aligned: ddrmm=%p, n="SIZE_T_FMT"\n", \r
- ddrmm, num_o_chunks);\r
- slut = TNMALLOC(MT_size_t, num_o_chunks); /* small, so not VMALLOC */\r
- if (slut)\r
- {\r
- MT_size_t i;\r
- rc = HH_OK;\r
- lookup_sort(num_o_chunks, chunks_log2_sizes, slut);\r
- for (i = 0; (i != num_o_chunks) && (rc == HH_OK); ++i)\r
- {\r
- MT_size_t si = slut[i];\r
- u_int8_t log2sz = (u_int8_t)chunks_log2_sizes[si];\r
- if (log2sz != (u_int8_t)THH_DDRMM_INVALID_SZ) {\r
- rc = THH_ddrmm_alloc(ddrmm, (MT_size_t)1 << log2sz, log2sz, &chunks_addrs[si]);\r
- } else {\r
- chunks_addrs[si]= THH_DDRMM_INVALID_PHYS_ADDR;\r
- /* No allocation if given log size is zero (workaround struct design in ddr_alloc_size_vec)*/\r
- }\r
- }\r
- if (rc != HH_OK)\r
- { /* Backwards. Note that we avoid (MT_size_t)-1 > 0 */\r
- while (i-- > 0)\r
- { /* Now i >= 0 */\r
- MT_size_t si = slut[i];\r
- u_int8_t log2sz = (u_int8_t)chunks_log2_sizes[si];\r
- if (log2sz != (u_int8_t)THH_DDRMM_INVALID_SZ) \r
- THH_ddrmm_free(ddrmm, chunks_addrs[si], (MT_size_t)1 << log2sz);\r
- }\r
- }\r
- FREE(slut);\r
- }\r
- MTL_TRACE1("}THH_ddrmm_alloc_sz_aligned\n");\r
- logIfErr("THH_ddrmm_alloc_sz_aligned")\r
- return rc;\r
-} /* THH_ddrmm_alloc_sz_aligned */\r
-\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_ddrmm_alloc(\r
- THH_ddrmm_t ddrmm, /* IN */\r
- MT_size_t size, /* IN */\r
- u_int8_t align_shift, /* IN */\r
- MT_phys_addr_t* buf_p /* OUT */\r
-)\r
-{\r
- HH_ret_t rc = HH_EINVAL;\r
- /* internally (extbuddy) we need power-2 size */\r
- MT_size_t log2sz = ceil_log2(size);\r
- MTL_TRACE1("{THH_ddrmm_alloc: ddrmm=%p, sz="SIZE_T_FMT", lg2=%d, shift=%d\n", \r
- ddrmm, size, (u_int32_t)log2sz, align_shift);\r
- if (log2sz >= align_shift)\r
- {\r
- u_int32_t p = EXTBUDDY_NULL;\r
- MOSAL_mutex_acq_ui(&ddrmm->mtx);\r
- p = extbuddy_alloc(ddrmm->xb, (u_int8_t)log2sz);\r
- MOSAL_mutex_rel(&ddrmm->mtx);\r
- MTL_DEBUG7(MT_FLFMT("log2sz="SIZE_T_FMT", p=0x%x"), log2sz, p);\r
- rc = HH_EAGAIN;\r
- if (p != EXTBUDDY_NULL)\r
- {\r
- *buf_p = ddrmm->mem_base + p;\r
- rc = HH_OK;\r
- }\r
- }\r
- MTL_TRACE1("}THH_ddrmm_alloc: buf="U64_FMT"\n", (u_int64_t)*buf_p);\r
- if ( rc != HH_OK ) {\r
- if (rc == HH_EAGAIN) {\r
- MTL_DEBUG1("%s: rc=%s\n",__func__, HH_strerror_sym(rc));\r
- } else {\r
- MTL_ERROR1("%s: rc=%s\n",__func__, HH_strerror_sym(rc));\r
- }\r
- }\r
- return rc;\r
-} /* THH_ddrmm_alloc */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_ddrmm_alloc_bound(\r
- THH_ddrmm_t ddrmm, /* IN */\r
- MT_size_t size, /* IN */\r
- u_int8_t align_shift, /* IN */\r
- MT_phys_addr_t area_start, /* IN */\r
- MT_phys_addr_t area_size, /* IN */\r
- MT_phys_addr_t* buf_p /* OUT */\r
-)\r
-{\r
- HH_ret_t rc = HH_EINVAL;\r
- /* internally (extbuddy) we need power-2 size */\r
- MT_size_t log2sz = ceil_log2(size);\r
- MTL_TRACE1("{THH_ddrmm_alloc_bound: ddrmm=%p, sz="SIZE_T_FMT", shift=%d, "\r
- "area:{start="U64_FMT", size="U64_FMT"\n", \r
- ddrmm, size, align_shift, (u_int64_t)area_start, (u_int64_t)area_size);\r
- if (log2sz >= align_shift)\r
- {\r
- u_int32_t p = EXTBUDDY_NULL;\r
- MOSAL_mutex_acq_ui(&ddrmm->mtx);\r
- p = extbuddy_alloc_bound(ddrmm->xb, (u_int8_t)log2sz, (u_int32_t)area_start, (u_int32_t)area_size);\r
- MOSAL_mutex_rel(&ddrmm->mtx);\r
- rc = HH_EAGAIN;\r
- if (p != EXTBUDDY_NULL)\r
- {\r
- *buf_p = ddrmm->mem_base + p;\r
- rc = HH_OK;\r
- }\r
- }\r
- MTL_TRACE1("}THH_ddrmm_alloc_bound: buf="U64_FMT"\n", (u_int64_t)*buf_p);\r
- logIfErr("THH_ddrmm_alloc_bound")\r
- return rc;\r
-} /* THH_ddrmm_alloc_bound */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_ddrmm_free(\r
- THH_ddrmm_t ddrmm, /* IN */\r
- MT_phys_addr_t buf, /* IN */\r
- MT_size_t size /* IN */\r
-)\r
-{\r
- HH_ret_t rc = HH_OK; \r
- MT_size_t log2sz = ceil_log2(size);\r
- MTL_TRACE1("{THH_ddrmm_free: ddrmm=%p, buf="U64_FMT", sz="SIZE_T_FMT"\n",\r
- ddrmm, (u_int64_t)buf, size);\r
- MOSAL_mutex_acq_ui(&ddrmm->mtx);\r
- extbuddy_free(ddrmm->xb, (u_int32_t)(buf - ddrmm->mem_base), (u_int8_t)log2sz);\r
- MOSAL_mutex_rel(&ddrmm->mtx);\r
- MTL_TRACE1("}THH_ddrmm_free\n");\r
- logIfErr("THH_ddrmm_free")\r
- return rc;\r
-} /* THH_ddrmm_free */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_ddrmm_query(\r
- THH_ddrmm_t ddrmm, /* IN */\r
- u_int8_t align_shift, /* IN */\r
- VAPI_size_t* total_mem, /* OUT */\r
- VAPI_size_t* free_mem, /* OUT */\r
- VAPI_size_t* largest_chunk, /* OUT */\r
- VAPI_phy_addr_t* largest_free_addr_p /* OUT */\r
-)\r
-{\r
- HH_ret_t rc = HH_OK;\r
- int log2_sz;\r
- MTL_TRACE1("{THH_ddrmm_query: ddrmm=%p, shift=%d\n", ddrmm, align_shift);\r
- *total_mem = ddrmm->mem_sz;\r
- *free_mem = extbuddy_total_available(ddrmm->xb);\r
- log2_sz = extbuddy_log2_max_available(ddrmm->xb);\r
- *largest_chunk = 0;\r
- *largest_free_addr_p = ddrmm->mem_base + ddrmm->mem_sz; /* like null */\r
- if (log2_sz >= align_shift)\r
- {\r
- u_int32_t p;\r
- *largest_chunk = (VAPI_size_t)1 << log2_sz;\r
-/*** warning C4242: 'function' : conversion from 'int' to 'u_int8_t', possible loss of data ***/\r
- extbuddy_query_chunks(ddrmm->xb, (u_int8_t)log2_sz, 1, &p);\r
- *largest_free_addr_p = ddrmm->mem_base + p;\r
- }\r
- MTL_TRACE1("}THH_ddrmm_query: total="U64_FMT", free="U64_FMT", lc="U64_FMT", p="U64_FMT"\n",\r
- *total_mem, *free_mem, \r
- *largest_chunk, (VAPI_phy_addr_t)*largest_free_addr_p);\r
- logIfErr("THH_ddrmm_query")\r
- return rc;\r
-} /* THH_ddrmm_query */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#if !defined(_TDDRM__H)\r
-#define _TDDRM__H\r
-\r
-#include <mtl_common.h>\r
-#include <vapi_types.h>\r
-#include <mosal.h>\r
-#include <hh.h>\r
-#include <thh.h>\r
-\r
-\r
-#define THH_DDRMM_INVALID_HANDLE ((THH_ddrmm_t)0)\r
-#define THH_DDRMM_INVALID_SZ ((MT_size_t)-1)\r
-#define THH_DDRMM_INVALID_PHYS_ADDR ((MT_phys_addr_t)-1)\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_ddrmm_create\r
- *\r
- * Arguments:\r
- * mem_base - Physical address base for DDR memory\r
- * mem_sz - Size in bytes of DDR memory 1\r
- * ddrmm_p - Created object handle\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameter\r
- * HH_EAGAIN - Not enough resources for creating this object\r
- *\r
- * Description:\r
- * Create DDR memory management object context.\r
- */\r
-extern HH_ret_t THH_ddrmm_create(\r
- MT_phys_addr_t mem_base, /* IN */\r
- MT_size_t mem_sz, /* IN */\r
- THH_ddrmm_t* ddrmm_p /* OUT */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_ddrmm_destroy\r
- *\r
- * Arguments:\r
- * ddrmm - The handle of the object to destroy\r
- *\r
- * Returns:\r
- * HH_OK HH_EINVAL - No such object\r
- *\r
- * Description:\r
- * Free given object resources.\r
- */\r
-extern HH_ret_t THH_ddrmm_destroy(THH_ddrmm_t ddrmm /* IN */);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_ddrmm_reserve\r
- *\r
- * Arguments:\r
- * ddrmm\r
- * addr - Physical address of reserved area\r
- * size - Byte size of the reserved area\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters (Given area is beyond DDR memory space)\r
- * or called after some allocation done.\r
- *\r
- * Description:\r
- * Can be used only before any THH_ddrmm_alloc...() calls.\r
- * Some areas in the attached DDR memory are reserved and may not be\r
- * allocated by HCA driver or an application (e.g. firmware reserved\r
- * areas). This function allows the HCA driver to explicitly define a\r
- * memory space to exclude of the THH_ddrmm dynamic allocation.\r
- */\r
-extern HH_ret_t THH_ddrmm_reserve (\r
- THH_ddrmm_t ddrmm, /* IN */\r
- MT_phys_addr_t addr, /* IN */\r
- MT_size_t size /* IN */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_ddrmm_alloc_sz_aligned\r
- *\r
- * Arguments:\r
- * ddrmm - THH_ddrmm context\r
- * num_o_chunks - The number of chunks to allocate (size of arrays below)\r
- * chunks_sizes - An array of num_o_chunks sizes (log2) array.\r
- * One for each chunk.\r
- * chunks_addrs - An array of num_o_chunks addresses allocated\r
- * for the chunks based on given size/alignment\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters (NULL...)\r
- * HH_EAGAIN - No resources available to match all chunks requirements\r
- *\r
- * Description:\r
- * HCA resources which are allocated during HCA initialization are all\r
- * required to be size aligned (context tables etc.). By providing all\r
- * those memory requirement at once this function allows the THH_ddrmm\r
- * to efficiently allocate the attached DDR memory resources under the\r
- * alignment constrains.\r
- */\r
-extern HH_ret_t THH_ddrmm_alloc_sz_aligned(\r
- THH_ddrmm_t ddrmm, /* IN */\r
- MT_size_t num_o_chunks, /* IN */\r
- MT_size_t* chunks_log2_sizes, /* IN */\r
- MT_phys_addr_t* chunks_addrs /* OUT */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_ddrmm_alloc\r
- *\r
- * Arguments:\r
- * ddrmm - The object handle\r
- * size - Size in bytes of memory chunk required\r
- * align_shift - Alignment shift of chunk (log2 of alignment value)\r
- * buf_p - The returned allocated buffer physical address\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalud object handle\r
- * HH_EAGAIN - Not enough resources for required allocation\r
- *\r
- * Description:\r
- * Allocate a physically contiguous memory chunk in DDR memory which\r
- * follows requirement of size and alignment.\r
- */\r
-extern HH_ret_t THH_ddrmm_alloc(\r
- THH_ddrmm_t ddrmm, /* IN */\r
- MT_size_t size, /* IN */\r
- u_int8_t align_shift, /* IN */\r
- MT_phys_addr_t* buf_p /* OUT */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_ddrmm_alloc_bound\r
- *\r
- * Arguments:\r
- * ddrmm - The object handle\r
- * size - Size in bytes of memory chunk required\r
- * align_shift - Alignment shift of chunk (log2 of alignment value)\r
- * area_start - Start of area where allocation is restricted to.\r
- * area_size - Size of area where allocation is restricted to.\r
- * buf_p - The returned allocated buffer physical address\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalud object handle\r
- * HH_EAGAIN - Not enough resources for required allocation\r
- *\r
- * Description:\r
- * Allocate a physically contiguous memory chunk in DDR memory which\r
- * follows requirement of size and alignment.\r
- */\r
-extern HH_ret_t THH_ddrmm_alloc_bound(\r
- THH_ddrmm_t ddrmm, /* IN */\r
- MT_size_t size, /* IN */\r
- u_int8_t align_shift, /* IN */\r
- MT_phys_addr_t area_start, /* IN */\r
- MT_phys_addr_t area_size, /* IN */\r
- MT_phys_addr_t* buf_p /* OUT */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_ddrmm_free\r
- *\r
- * Arguments:\r
- * ddrmm - The object handle\r
- * buf - Exact address of buffer as given in allocation\r
- * size - Original size (in bytes)of buffer as given in allocation\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Given handle in unknown or given address is not\r
- * an address returned by THH_ddrmm_alloc\r
- * (or THH_ddrmm_alloc_sz_aligned)\r
- *\r
- * Description:\r
- * Free a memory chunk allocated by THH_ddrmm_alloc.\r
- */\r
-extern HH_ret_t THH_ddrmm_free(\r
- THH_ddrmm_t ddrmm, /* IN */\r
- MT_phys_addr_t buf, /* IN */\r
- MT_size_t size /* IN */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_ddrmm_query\r
- *\r
- * Arguments:\r
- * ddrmm - The object handle\r
- * align_shift - Alignment requirements for returned largest_chunk\r
- * total_mem - Total byte count of memory managed by this object\r
- * free_mem - Total byte count of free memory\r
- * largest_chunk - Largest chunk possible to allocate with given\r
- * align_shift requirements\r
- * largest_free_addr_p - Address of the refered largest chunk\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid handle\r
- *\r
- * Description:\r
- * Query ddrmm object for allocation capabilities with given alignment\r
- * contrains (use 0 if alignment is not needed). This is useful in case\r
- * one wishes to get a hint from the object on the amount to request.\r
- */\r
-extern HH_ret_t THH_ddrmm_query(\r
- THH_ddrmm_t ddrmm, /* IN */\r
- u_int8_t align_shift, /* IN */\r
- VAPI_size_t* total_mem, /* OUT */\r
- VAPI_size_t* free_mem, /* OUT */\r
- VAPI_size_t* largest_chunk, /* OUT */\r
- VAPI_phy_addr_t* largest_free_addr_p /* OUT */\r
-);\r
-\r
-\r
-#endif /* _TDDRM__H */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#include <cmdif.h>\r
-#include <mosal.h>\r
-#include <eventp_priv.h>\r
-#include <uar.h>\r
-#include <thh_hob.h>\r
-#include <vapi_common.h>\r
-\r
-#include <cr_types.h>\r
-#include <MT23108.h>\r
-\r
-//#define MTPERF\r
-#include <mtperf.h>\r
-\r
-#ifdef THH_CMD_TIME_TRACK\r
-u_int64_t THH_eventp_last_cmdif_interrupt;\r
-#endif\r
-\r
-/*================ macro definitions ===============================================*/\r
-\r
-/*================ type definitions ================================================*/\r
-\r
-\r
-typedef struct eq_entry_st {\r
- u_int8_t event_type;\r
- tavor_if_port_event_subtype_t event_sub_type;\r
- u_int32_t event_data[6]; /* Delivers auxiliary data to handle event. - 24 bytes */\r
-}eq_entry_t;\r
-\r
-\r
-/*================ global variables definitions ====================================*/\r
-\r
-MTPERF_NEW_SEGMENT(interupt_segment,100000);\r
-MTPERF_NEW_SEGMENT(inter2dpc_segment,100000);\r
-MTPERF_NEW_SEGMENT(dpc_segment,100000);\r
-MTPERF_NEW_SEGMENT(part_of_DPC_segment,100000);\r
-\r
-/*================ static functions prototypes =====================================*/\r
-\r
-inline static MT_bool read_eq_entry(u_int32_t *buff_p,\r
- EQ_type_t eq_type,\r
- eq_entry_t *eqe_p);\r
-\r
-\r
-\r
-inline static HH_ret_t move_eqe_to_hw(EQP_eq_entry_t *eqe_p, \r
- u_int32_t *eqe_buff_p); /* pointer to start of EQE buffer */\r
-\r
-static void handle_eqe_ib_events(EQP_eq_entry_t *eqe_p,\r
- eq_entry_t *eq_data_p);\r
-/*================ global functions definitions ====================================*/\r
-\r
-\r
-\r
-/************************************************************************\r
- * Function: thh_intr_handler\r
- * \r
- \r
- Arguments:\r
- eventp - handler to eventp object\r
- isr_ctx1 & isr_ctx2 - ignored\r
- \r
- \r
- Description:\r
- \r
- Clear_INT(); // De-assert INT pin (write to Clr_INT register) \r
- ECR = Read_ECR(); // read ECR register \r
- foreach (EQN set in ECR) { \r
- Schedule_EQ_handler(EQN); // schedule appropriate handler \r
- Clear_ECR; // Clear ECR bits that were taken care of \r
- }\r
- \r
- \r
- \r
-************************************************************************/\r
-\r
-\r
-BOOLEAN thh_intr_handler(MT_ulong_ptr_t eventp_dpc, void* isr_ctx1, void* isr_ctx2)\r
-{\r
- THH_eventp_t eventp = (THH_eventp_t)eventp_dpc;\r
- u_int32_t ecr[2]; /* 0 - low 1- high */\r
- int i,j, eq_num;\r
- EQP_eq_entry_t *event_entry;\r
-\r
-\r
- /* start measurements */\r
-\r
- //MTPERF_TIME_START(interupt_segment);\r
- \r
- /* De-assert INT pin (write to Clr_INT register) */\r
- MOSAL_MMAP_IO_WRITE_DWORD(eventp->intr_clr_reg, eventp->intr_clr_mask);\r
-\r
- /*MTL_DEBUG1("%s: ECR register=0x%08x\n", __func__, eventp->ecr_h_base );*/\r
-\r
- /* read ECR register */\r
- ecr[0] = MOSAL_be32_to_cpu(MOSAL_MMAP_IO_READ_DWORD(eventp->ecr_l_base));\r
-#if EQP_ECR_USED>1\r
- ecr[1] = MOSAL_be32_to_cpu(MOSAL_MMAP_IO_READ_DWORD(eventp->ecr_h_base));\r
- MTL_ERROR1("%s: READ ECR HIGH\n", __func__);\r
-#endif\r
- \r
- /* No need to check anything of all bits are zero */\r
- if (ecr[0] == 0) {\r
- return FALSE;\r
- }\r
- if (ecr[0] == 0xffffffff) {\r
- /* master abort */\r
- /* verify that it indeed master abort by reading ECR high too */\r
- ecr[1] = MOSAL_be32_to_cpu(MOSAL_MMAP_IO_READ_DWORD(eventp->ecr_h_base));\r
- if (ecr[1] == 0xffffffff) {\r
- /* notify hob for fatal error - must be done from DPC level */\r
- MTL_ERROR1("%s: THH_FATAL_MASTER_ABORT: on ECR[0 & 1] \n", __func__);\r
- if (eventp->have_fatal) {\r
- /* no need to do anything since we already in fatal state */\r
- MTL_ERROR1("%s: THH_FATAL_MASTER_ABORT recieved when we are in FATAL state - NOP \n", __func__);\r
- }\r
- else { /* a new fatal error */\r
- eventp->have_fatal = TRUE;\r
- eventp->fatal_type = THH_FATAL_MASTER_ABORT;\r
- MOSAL_DPC_schedule(&(eventp->fatal_error_dpc)); /* schedule DPC to notify hob on master abort */\r
- }\r
- return TRUE;\r
- }\r
- MTL_ERROR1("%s: THH_FATAL_MASTER_ABORT: on ECR[0] only - ignoring \n", __func__);\r
- }\r
- \r
- /* work on both words */\r
- for(i=0; i<EQP_ECR_USED; i++) { /* foreach dword */\r
- for(j=0; j<eventp->max_eq_num_used; j++) { /* foreach bit */\r
- if((ecr[i] & BITS32(j,1))) { /* if the j-th bit is set */\r
- eq_num = (i << 5) + j;\r
- event_entry = &(eventp->eq_table[eq_num]);\r
- MOSAL_spinlock_irq_lock(&(event_entry->state_lock));\r
- if (IS_EQ_VALID_P(event_entry)) {\r
-#if !defined(VXWORKS_OS) /* can not use printf in isr */\r
- MTL_DEBUG1("%s: ECR_LOW=0x%08x ECR_HIGH=not read, eq_num = %d \n", __func__, ecr[0], eq_num);\r
-#endif \r
- /* check if this is catastrophic error */\r
- if (eq_num == EQP_CATAS_ERR_EQN) {\r
- MTL_ERROR1("%s: THH_FATAL_ERROR recieved on EQP_CATAS_ERR_EQN (%d) \n", \r
- __func__, EQP_CATAS_ERR_EQN);\r
- if (eventp->have_fatal) {\r
- /* no need to do anything since we already in fatal state */\r
- MTL_ERROR1("%s: THH_FATAL_ERROR recieved when we are in FATAL state - NOP \n", __func__);\r
- }\r
- else { /* a new fatal error */\r
- eventp->have_fatal = TRUE;\r
- eventp->fatal_type = THH_FATAL_EVENT;\r
- MOSAL_DPC_schedule(&(eventp->fatal_error_dpc)); /* schedule DPC to notify hob on fatal error */\r
- }\r
- } \r
- else {\r
- if (MOSAL_DPC_schedule(&event_entry->polling_dpc)){ /* schedule DPC to poll EQ */\r
- #if !defined(DPC_IS_DIRECT_CALL)\r
- MOSAL_atomic_inc32(&event_entry->dpc_cntr);\r
- #else\r
- event_entry->dpc_cntr++; /* Monitor number of outstanding DPCs */\r
- #endif \r
-#ifdef THH_CMD_TIME_TRACK\r
- if (eq_num == EQP_CMD_IF_EQN) {\r
- THH_eventp_last_cmdif_interrupt= MOSAL_get_time_counter();\r
- }\r
-#endif\r
- }\r
- }\r
- } \r
- else {\r
- if (eventp->have_fatal) {\r
- MTL_DEBUG1("%s: in fatal state: got event to EQ=%d but it is not setup; eq state=%d\n", __func__, \r
- i*32 + j, event_entry->res_state);\r
- }\r
- else {\r
- MTL_ERROR1("%s: Internal error: got event to EQ=%d but it is not setup; eq state=%d\n", __func__, \r
- i*32 + j, event_entry->res_state);\r
- }\r
- \r
- }\r
- MOSAL_spinlock_unlock(&(event_entry->state_lock));\r
- \r
- /* clear ecr bits that were taken care of - already in big-endian */\r
- if (event_entry->clr_ecr_addr) {\r
- MOSAL_MMAP_IO_WRITE_DWORD(event_entry->clr_ecr_addr, event_entry->clr_ecr_mask); \r
- }\r
- else {\r
- MTL_ERROR1(MT_FLFMT("event_entry->clr_ecr_addr=null\n"));\r
- }\r
-\r
- if (eq_num == EQP_CATAS_ERR_EQN) {\r
- goto end_intr; \r
- }\r
- } /* the j-th bit is set */\r
- } /* foreach bit */\r
- } /* foreach dword */\r
- \r
-end_intr:\r
- return TRUE;\r
-} /* thh_intr_handler() */\r
-\r
-/* inline functions must be placed BEFORE their call */\r
-/************************************************************************************************/\r
-inline static MT_bool read_eq_entry(u_int32_t *eqe_buff_p,\r
- EQ_type_t eq_type,\r
- eq_entry_t *eqe_p)\r
-{\r
- u_int32_t tmp_eq_data[8] = {0,0,0,0,0,0,0,0}; /* entry size is 32 bytes */\r
- unsigned int i;\r
-\r
-\r
- MTL_DEBUG1("%s: eqe_buff= %x %x %x %x %x %x %x %x \n", __func__, *eqe_buff_p,\r
- *(eqe_buff_p+1), *(eqe_buff_p+2), *(eqe_buff_p+3),*(eqe_buff_p+4),\r
- *(eqe_buff_p+5), *(eqe_buff_p+6), *(eqe_buff_p+7));\r
- /* first extract the owner & event_type only*/\r
- \r
-#ifdef EQS_CMD_IN_DDR\r
- tmp_eq_data[EQE_OWNER_OFFSET] = MOSAL_be32_to_cpu(MOSAL_MMAP_IO_READ_DWORD((eqe_buff_p+EQE_OWNER_OFFSET)));\r
- /* owner */\r
- if ( EQE_SW_OWNER != MT_EXTRACT_ARRAY32(tmp_eq_data, MT_BIT_OFFSET(tavorprm_event_queue_entry_st, owner),\r
- MT_BIT_SIZE(tavorprm_event_queue_entry_st, owner))) {\r
- MTL_DEBUG1("%s: EQE_HW_OWNER\n", __func__);\r
- return FALSE;\r
- }\r
-#else\r
- /* if EQE not in SW ownership - end of EQEs to handle */\r
- if ((((u_int8_t*)eqe_buff_p)[EQE_OWNER_BYTE_OFFSET] & EQE_HW_OWNER) != EQE_SW_OWNER) {\r
- MTL_DEBUG1("%s: EQE_HW_OWNER\n", __func__);\r
- return FALSE;\r
- }\r
-#endif \r
-\r
- /* event_type & event_sub_type */\r
-#ifdef EQS_CMD_IN_DDR\r
- tmp_eq_data[EQE_EVENT_TYPE_OFFSET] = MOSAL_be32_to_cpu(MOSAL_MMAP_IO_READ_DWORD((eqe_buff_p+EQE_EVENT_TYPE_OFFSET)));\r
-#else\r
- tmp_eq_data[EQE_EVENT_TYPE_OFFSET] = MOSAL_be32_to_cpu(*(eqe_buff_p+EQE_EVENT_TYPE_OFFSET));\r
-#endif\r
- eqe_p->event_type = MT_EXTRACT_ARRAY32(tmp_eq_data, MT_BIT_OFFSET(tavorprm_event_queue_entry_st, event_type),\r
- MT_BIT_SIZE(tavorprm_event_queue_entry_st, event_type));\r
-\r
- eqe_p->event_sub_type = (tavor_if_port_event_subtype_t)\r
- MT_EXTRACT_ARRAY32(tmp_eq_data, MT_BIT_OFFSET(tavorprm_event_queue_entry_st, event_sub_type),\r
- MT_BIT_SIZE(tavorprm_event_queue_entry_st, event_sub_type));\r
-\r
- /* extract of data will be done according to the event type */\r
- \r
- if(eq_type != EQP_CMD_IF_EVENT) {\r
- for(i=EQE_DATA_OFFSET; i< EQE_OWNER_OFFSET; i++) {\r
-#ifdef EQS_CMD_IN_DDR\r
- eqe_p->event_data[i-EQE_DATA_OFFSET] = MOSAL_be32_to_cpu(MOSAL_MMAP_IO_READ_DWORD((eqe_buff_p + i)));\r
-#else\r
- eqe_p->event_data[i-EQE_DATA_OFFSET] = MOSAL_be32_to_cpu(*(eqe_buff_p + i));\r
-#endif\r
- }\r
- }\r
- else { /* need to leave as big-endien for the cmd_if callback */\r
-#ifdef EQS_CMD_IN_DDR\r
- MOSAL_MMAP_IO_READ_BUF_DWORD(eqe_buff_p+EQE_DATA_OFFSET,eqe_p->event_data,EQE_DATA_BYTE_SIZE/4);\r
-#else\r
- memcpy(eqe_p->event_data, eqe_buff_p+EQE_DATA_OFFSET, EQE_DATA_BYTE_SIZE);\r
-#endif\r
- }\r
- FUNC_OUT;\r
- return TRUE;\r
-}\r
-\r
-/************************************************************************************************/\r
-\r
-inline static HH_ret_t move_eqe_to_hw(EQP_eq_entry_t *eqe_p, \r
- u_int32_t *eqe_buff_p) /* pointer to start of EQE buffer */\r
-{\r
-\r
- HH_ret_t ret = HH_OK;\r
-\r
- /* move EQE to HW ownership */\r
- \r
-#ifdef EQS_CMD_IN_DDR\r
- MOSAL_MMAP_IO_WRITE_DWORD((eqe_buff_p+EQE_OWNER_OFFSET), 0xffffffff);\r
-#else\r
- *(eqe_buff_p+EQE_OWNER_OFFSET) = 0xffffffff; /* no need for cpu to be32 sine all is ff */\r
-#endif\r
-\r
- /* update consumer index the FW take care to the cyclic buffer update */\r
- ret = THH_uar_eq_cmd(eqe_p->eventp_p->kar, TAVOR_IF_UAR_EQ_INC_CI, eqe_p->eqn, 0);\r
- if(ret != HH_OK) {\r
- MTL_ERROR1("%s: Internal error: THH_uar_eq_cmd failed ret=%d.\n", __func__,ret);\r
- }\r
- MT_RETURN( ret);\r
-}\r
-\r
-\r
-/************************************************************************\r
- * Function: eq_polling_dpc\r
- * \r
- \r
- Arguments:\r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL -Invalid parameters \r
- \r
- Description: \r
- \r
- lock spinlock of EQ\r
- clear ECR of this EQ\r
- While (EQE[Consumer_indx].Owner == SW) { \r
- consume_entry - call EQ handler; // remove entry from the queue \r
- EQE[Consumer_indx++].Owner = HW; // mark entry to the Hardware ownership for next time around \r
- consumer_indx &= MASK; // wrap around index \r
- } \r
- update_consumer_index(EQ,consumer_indx); // update consumer index in HCA via UAR \r
- subscribe_for_event(EQ); // subscribe for event for next time\r
- unlock EQ spinlock\r
- \r
-************************************************************************/\r
-\r
-void eq_polling_dpc(DPC_CONTEXT_t *dpc_obj_p)\r
-{\r
- EQP_eq_entry_t *eqe_p = (EQP_eq_entry_t *)dpc_obj_p->func_ctx; /* EQ context entry (not the EQE) */ \r
- u_int32_t cons_indx;\r
- eq_entry_t eqe;\r
- u_int32_t *eqe_buff_p;\r
- void* cyc_buff;\r
- HH_ret_t ret;\r
-\r
- \r
- //MTPERF_TIME_END(inter2dpc_segment);\r
- //MTPERF_TIME_START(dpc_segment);\r
-\r
- FUNC_IN;\r
-\r
-\r
- if (eqe_p->eventp_p->have_fatal){\r
- goto dpc_done1;\r
- }\r
- \r
-#if !defined(DPC_IS_DIRECT_CALL) && !defined(IMPROVE_EVENT_HANDLING)\r
- // the following fragment is unnecessary, because THH_eventp_teardown_eq() will wait for all DPCs to exit.\r
- /* In Darwin, the DPC is a direct function call, so this is guaranteed to be\r
- * checked already */\r
- MOSAL_spinlock_irq_lock(&eqe_p->state_lock);\r
- if (!IS_EQ_VALID_P(eqe_p)) { /* Make sure the EQ is still in use (was not torn down) */\r
- MOSAL_spinlock_unlock(&eqe_p->state_lock);\r
- MTL_ERROR1(MT_FLFMT("DPC invoked for an EQ not in use.\n"));\r
- goto dpc_done1;\r
- }\r
- MOSAL_spinlock_unlock(&eqe_p->state_lock);\r
-#endif\r
- \r
- \r
- /* CLEAR ECR bit of this EQ since it might be set again between ISR & DPC */\r
- /* moved to comment since any write to the Tavor registers harm the performance */\r
- /* MOSAL_MMAP_IO_WRITE_DWORD(eqe_p->clr_ecr_addr, eqe_p->clr_ecr_mask); */\r
-\r
- cyc_buff = eqe_p->eq_buff;\r
- /* EQEs polling loop */\r
-/* need to protect only in case simultanuous DPC can be called at the same time \r
- currently will be set only for windows */\r
-#if defined( SIMULTANUOUS_DPC ) && !defined( DPC_IS_DIRECT_CALL )\r
- MOSAL_spinlock_dpc_lock(&eqe_p->dpc_lock); /* protect consumer index access */\r
-#endif\r
-\r
- for(cons_indx = eqe_p->cons_indx;/* break done inside the loop*/ ;\r
- cons_indx = (cons_indx == (eqe_p->eq_buff_entry_num - 1)) ? 0 : cons_indx+1) {\r
-\r
- MTL_DEBUG1("%s: cons_indx=%d cyc_buff=%p\n", __func__,cons_indx, cyc_buff);\r
- eqe_buff_p = ((u_int32_t*)cyc_buff) + EQE_DWORD_SIZE*cons_indx ; /* TK: can improve with << of EQE logsize later */\r
- /* read the EQE and change to machine endianess */\r
- if (read_eq_entry(eqe_buff_p, eqe_p->eq_type, &eqe) == FALSE){\r
- MTL_DEBUG1("%s: entry not in SW ownership, cons_indx=%d cyc_buff=%p\n", __func__,cons_indx, cyc_buff);\r
- break; /* no more EQEs to poll */\r
- }\r
-\r
- /* if we are here then we have EQE in SW ownership */\r
-\r
- /* first return EQE to HW ownership and update consumer index */\r
- if((ret = move_eqe_to_hw(eqe_p, eqe_buff_p)) != HH_OK) {\r
- MTL_ERROR1("%s: failed moving EQE to HW \n", __func__);\r
- goto dpc_done2;\r
- }\r
- /* TK: maybe this should be moved before the move to hw?? \r
- now check that we don't have overrun */\r
-\r
- if(eqe.event_type == TAVOR_IF_EV_TYPE_OVERRUN) {\r
- MTL_ERROR1("%s: EQ OVERRUN eqn=%d\n", __func__, eqe_p->eqn);\r
- /* need to notify the hob for the fatal error */\r
- eqe_p->eventp_p->have_fatal = TRUE;\r
- THH_hob_fatal_error(eqe_p->eventp_p->hob, THH_FATAL_EQ_OVF, VAPI_CATAS_ERR_EQ_OVERFLOW);\r
- goto dpc_done2;\r
- }\r
- \r
- MTL_DEBUG1("%s: EQ type =%d\n", __func__, eqe_p->eq_type);\r
- switch (eqe_p->eq_type) {\r
- /* handle CMD_IF EQ */\r
- case EQP_CMD_IF_EVENT:\r
- if(eqe.event_type != TAVOR_IF_EV_TYPE_CMD_IF_COMP) {\r
- MTL_ERROR1("%s: Internal error: wrong EQ type to CMD_IF EQ. EQ type =%d\n", __func__, \r
- eqe.event_type);\r
- }\r
- else {\r
- /* notify cmd_if module */\r
- THH_cmd_eventh(eqe_p->eventp_p->cmd_if, (u_int32_t*)eqe.event_data);\r
- }\r
- break;\r
- /* IB events */\r
- case EQP_IB_EVENT:\r
- handle_eqe_ib_events(eqe_p,&eqe);\r
- break;\r
- \r
- /* Completion Events */ \r
- case EQP_CQ_COMP_EVENT: \r
- /* sanity check */\r
- if(eqe.event_type != TAVOR_IF_EV_TYPE_CQ_COMP) {\r
- MTL_ERROR1("%s: Internal error: wrong EQ type to COMPLETION EVENTS EQ. EQ type =%d\n", __func__,\r
- eqe.event_type);\r
- }\r
- else {\r
- u_int32_t cqnum=0;\r
- cqnum = MT_EXTRACT_ARRAY32(eqe.event_data, MT_BIT_OFFSET(tavorprm_completion_event_st, cqn),\r
- MT_BIT_SIZE(tavorprm_completion_event_st, cqn));\r
- MTL_DEBUG2("%s: Got completion event on CQN=%d. Going to DIS-ARM CQ\n", __func__,cqnum);\r
- /* disarm CQ */\r
- ret = THH_uar_eq_cmd(eqe_p->eventp_p->kar, TAVOR_IF_UAR_EQ_DISARM_CQ, eqe_p->eqn, cqnum);\r
-\r
- /* call handler */\r
- \r
- eqe_p->handler.comp_event_h(eqe_p->eventp_p->hh_hca_hndl, (HH_cq_hndl_t)cqnum, \r
- eqe_p->priv_context);\r
- }\r
- break;\r
-\r
- case EQP_CATAS_ERR_EVENT:\r
- MTL_ERROR1("%s: Internal error: got to EQP_CATAS_ERR_EVENT in regular DPC \n", __func__);\r
- goto dpc_done2;\r
- break;\r
- case EQP_MLX_EVENT:\r
- break;\r
- }\r
- } /* polling EQE for loop */\r
-\r
- /* re-arm EQ for all EQs */\r
- ret = THH_uar_eq_cmd(eqe_p->eventp_p->kar, TAVOR_IF_UAR_EQ_INT_ARM, eqe_p->eqn, 0);\r
- if(ret != HH_OK) {\r
- MTL_ERROR1("%s: Internal error: THH_uar_eq_cmd failed ret=%d.\n", __func__,ret);\r
- }\r
-\r
- /* update consumer index of EQ */\r
- eqe_p->cons_indx = cons_indx;\r
-\r
-dpc_done2:\r
-#if defined( SIMULTANUOUS_DPC ) && !defined( DPC_IS_DIRECT_CALL )\r
- MOSAL_spinlock_unlock(&eqe_p->dpc_lock);\r
-#endif\r
-\r
-dpc_done1:\r
-#if defined(DPC_IS_DIRECT_CALL)\r
- /* In darwin, this spinlock is locked all throughout the intr_handler which\r
- * directly calls this function */\r
- eqe_p->dpc_cntr--; /* signal DPC done (for cleanup) */\r
-#else \r
- MOSAL_atomic_dec32(&eqe_p->dpc_cntr);\r
-#endif \r
-\r
- FUNC_OUT;\r
-\r
-#ifdef MTPERF\r
- if (eqe_p->eq_type == EQP_CQ_COMP_EVENT) {\r
- /*MTPERF_TIME_END(dpc_segment)*/;\r
- }\r
-#endif\r
-}\r
-\r
-/************************************************************************************************/\r
-\r
-\r
-static inline VAPI_event_record_type_t tavor2vapi_qp_error_type(u_int8_t event_type, MT_bool is_qp)\r
-{\r
- \r
- VAPI_event_record_type_t vapi_event_type;\r
- switch(event_type) {\r
- case TAVOR_IF_EV_TYPE_PATH_MIG: \r
- vapi_event_type = is_qp ? VAPI_QP_PATH_MIGRATED : VAPI_EEC_PATH_MIGRATED;\r
- break;\r
- case TAVOR_IF_EV_TYPE_SEND_Q_DRAINED: \r
- vapi_event_type = VAPI_SEND_QUEUE_DRAINED;\r
- break;\r
- case TAVOR_IF_EV_TYPE_PATH_MIG_FAIL: \r
- vapi_event_type = VAPI_PATH_MIG_REQ_ERROR;\r
- break;\r
- case TAVOR_IF_EV_TYPE_COMM_EST:\r
- vapi_event_type = is_qp ? VAPI_QP_COMM_ESTABLISHED : VAPI_EEC_COMM_ESTABLISHED;\r
- break;\r
- case TAVOR_IF_EV_TYPE_LOCAL_WQ_CATAS_ERR:\r
- vapi_event_type = is_qp ? VAPI_LOCAL_WQ_CATASTROPHIC_ERROR : VAPI_LOCAL_EEC_CATASTROPHIC_ERROR;\r
- break;\r
- case TAVOR_IF_EV_TYPE_LOCAL_WQ_INVALID_REQ_ERR: \r
- vapi_event_type = VAPI_LOCAL_WQ_INV_REQUEST_ERROR;\r
- break;\r
- case TAVOR_IF_EV_TYPE_LOCAL_WQ_ACCESS_VIOL_ERR: \r
- vapi_event_type = VAPI_LOCAL_WQ_ACCESS_VIOL_ERROR;\r
- break;\r
- case TAVOR_IF_EV_TYPE_SRQ_QP_LAST_WQE_REACHED:\r
- vapi_event_type = VAPI_RECEIVE_QUEUE_DRAINED;\r
- break;\r
- case TAVOR_IF_EV_TYPE_LOCAL_SRQ_CATAS_ERR:\r
- vapi_event_type = VAPI_SRQ_CATASTROPHIC_ERROR;\r
- break;\r
- \r
- default:\r
- MTL_ERROR1("%s: Unknown event type = %d\n", __func__,event_type);\r
- vapi_event_type = VAPI_LOCAL_CATASTROPHIC_ERROR;\r
- }\r
- return vapi_event_type;\r
-}\r
- \r
-\r
- \r
-/************************************************************************************************/\r
-static void handle_eqe_ib_events(EQP_eq_entry_t *eqe_p,\r
- eq_entry_t *eq_data_p)\r
-{\r
- HH_event_record_t event_record;\r
- u_int8_t syndrome=0;\r
- VAPI_event_syndrome_t vapi_syndrome = VAPI_EV_SYNDROME_NONE;\r
- event_record.syndrome = VAPI_EV_SYNDROME_NONE;\r
-\r
- FUNC_IN;\r
- switch(eq_data_p->event_type) {\r
-#if 0 /* TK: currently not supported by Tavor */\r
- case TAVOR_IF_EV_TYPE_LOCAL_EE_CATAS_ERR: \r
-#endif\r
- /* QP/EEC errors */\r
- case TAVOR_IF_EV_TYPE_PATH_MIG_FAIL: \r
- case TAVOR_IF_EV_TYPE_PATH_MIG: \r
- case TAVOR_IF_EV_TYPE_COMM_EST:\r
- case TAVOR_IF_EV_TYPE_LOCAL_WQ_CATAS_ERR:\r
- case TAVOR_IF_EV_TYPE_LOCAL_WQ_INVALID_REQ_ERR:\r
- case TAVOR_IF_EV_TYPE_LOCAL_WQ_ACCESS_VIOL_ERR:\r
- case TAVOR_IF_EV_TYPE_SEND_Q_DRAINED: \r
- case TAVOR_IF_EV_TYPE_SRQ_QP_LAST_WQE_REACHED: /* this is QP event */\r
- {\r
- u_int32_t qpn=0;\r
- u_int32_t is_qp=1;\r
-\r
- qpn = MT_EXTRACT_ARRAY32(eq_data_p->event_data, MT_BIT_OFFSET(tavorprm_qp_ee_event_st, qpn_een),\r
- MT_BIT_SIZE(tavorprm_qp_ee_event_st, qpn_een));\r
- \r
- is_qp = !(MT_EXTRACT_ARRAY32(eq_data_p->event_data, MT_BIT_OFFSET(tavorprm_qp_ee_event_st, e_q),\r
- MT_BIT_SIZE(tavorprm_qp_ee_event_st, e_q)));\r
-\r
- if (is_qp) {\r
- event_record.event_modifier.qpn = qpn;\r
- /* need to translate to VAPI_event_record_type_t */ \r
-/*** warning C4242: 'function' : conversion from 'u_int32_t' to 'MT_bool', possible loss of data ***/\r
- event_record.etype = tavor2vapi_qp_error_type(eq_data_p->event_type,(MT_bool)is_qp);\r
- }\r
- else { /* EEC is not supported now */\r
- MTL_ERROR1("%s: Internal error: is_eq = 0 but EEC not supported. eqn=%d\n", __func__,\r
- eqe_p->eqn);\r
- }\r
- break;\r
- }\r
- \r
- case TAVOR_IF_EV_TYPE_LOCAL_SRQ_CATAS_ERR:\r
- {\r
- event_record.event_modifier.srq= \r
- MT_EXTRACT_ARRAY32(eq_data_p->event_data, \r
- MT_BIT_OFFSET(tavorprm_qp_ee_event_st, qpn_een),\r
- MT_BIT_SIZE(tavorprm_qp_ee_event_st, qpn_een));\r
- event_record.etype = tavor2vapi_qp_error_type(eq_data_p->event_type,FALSE);\r
- break;\r
- }\r
-\r
- /* IB - affiliated errors CQ */\r
- case TAVOR_IF_EV_TYPE_CQ_ERR: \r
- {\r
- u_int32_t cqnum=0;\r
- \r
- cqnum = MT_EXTRACT_ARRAY32(eq_data_p->event_data, MT_BIT_OFFSET(tavorprm_completion_queue_error_st, cqn),\r
- MT_BIT_SIZE(tavorprm_completion_queue_error_st, cqn));\r
- syndrome = MT_EXTRACT_ARRAY32(eq_data_p->event_data, MT_BIT_OFFSET(tavorprm_completion_queue_error_st, syndrome),\r
- MT_BIT_SIZE(tavorprm_completion_queue_error_st, syndrome));\r
- event_record.etype = VAPI_CQ_ERROR;\r
- event_record.event_modifier.cq = cqnum;\r
- event_record.syndrome = (syndrome == TAVOR_IF_CQ_OVERRUN) ? VAPI_CQ_ERR_OVERRUN : \r
- ((syndrome == TAVOR_IF_CQ_ACCSS_VIOL_ERR) ? VAPI_CQ_ERR_ACCESS_VIOL : \r
- VAPI_EV_SYNDROME_NONE);\r
- MTL_ERROR1("%s: CQ error on CQ number= %d syndrome is %s (%d)\n", __func__,cqnum,\r
- VAPI_event_syndrome_sym(event_record.syndrome), event_record.syndrome);\r
- break;\r
- }\r
- /* Unaffiliated errors */\r
- case TAVOR_IF_EV_TYPE_LOCAL_CATAS_ERR:\r
- {\r
- MTL_ERROR1("%s: CATASTROPHIC ERROR - should not be in this EQ: \n", __func__);\r
- MTL_ERROR1("CATASTROPHIC ERROR: data: %x %x %x %x %x %x \n", *(eq_data_p->event_data),\r
- *(eq_data_p->event_data+1), *(eq_data_p->event_data+2), *(eq_data_p->event_data+3),\r
- *(eq_data_p->event_data+4), *(eq_data_p->event_data+5));\r
- break; \r
- }\r
- case TAVOR_IF_EV_TYPE_PORT_ERR: \r
- { \r
- IB_port_t port;\r
- port = MT_EXTRACT_ARRAY32(eq_data_p->event_data,MT_BIT_OFFSET(tavorprm_port_state_change_st, p),\r
- MT_BIT_SIZE(tavorprm_port_state_change_st, p));\r
-\r
- if (eq_data_p->event_sub_type == TAVOR_IF_SUB_EV_PORT_DOWN) {\r
- event_record.etype = VAPI_PORT_ERROR;\r
- }\r
- else if (eq_data_p->event_sub_type == TAVOR_IF_SUB_EV_PORT_UP) {\r
- event_record.etype = VAPI_PORT_ACTIVE;\r
- }\r
- else {\r
- MTL_ERROR1("%s: Wrong sub-type for Port event on port=%d sub_type=%d\n", __func__,port,eq_data_p->event_sub_type);\r
- }\r
-\r
- event_record.event_modifier.port = port;\r
- MTL_DEBUG1("%s: Port change event on port=%d sub_type=%d\n", __func__,port,eq_data_p->event_sub_type);\r
- break;\r
- }\r
- default:\r
- MTL_ERROR1("%s: Unsupported event type = %d\n", __func__,eq_data_p->event_type);\r
- /* in case of catastrophic error - no call to upper layer but notify HOB to handle */\r
- MTL_ERROR1("CATASTROPHIC ERROR: data: %x %x %x %x %x %x \n", *(eq_data_p->event_data),\r
- *(eq_data_p->event_data+1), *(eq_data_p->event_data+2), *(eq_data_p->event_data+3),\r
- *(eq_data_p->event_data+4), *(eq_data_p->event_data+5));\r
-\r
- THH_hob_fatal_error(eqe_p->eventp_p->hob, THH_FATAL_EVENT, vapi_syndrome);\r
- /**** !!!! FUNCTION returns HERE !!!! */\r
- FUNC_OUT;\r
- return;\r
- } /* switch(eq_data_p->event_type) */\r
- \r
- /* call the event callback */\r
- eqe_p->handler.ib_comp_event_h(eqe_p->eventp_p->hh_hca_hndl, &event_record, eqe_p->priv_context);\r
-\r
- FUNC_OUT;\r
- \r
-}\r
-\r
-\r
-/************************************************************************************************/\r
- \r
-void fatal_error_dpc(DPC_CONTEXT_t *dpc_obj_p)\r
-{\r
- VAPI_event_syndrome_t syndrome;\r
- \r
- THH_eventp_t eventp = (THH_eventp_t)dpc_obj_p->func_ctx; /* eventp of this hob */ \r
- FUNC_IN;\r
-\r
- if (eventp->fatal_type == THH_FATAL_MASTER_ABORT) {\r
- syndrome = VAPI_CATAS_ERR_MASTER_ABORT;\r
- MTL_DEBUG1("%s: VAPI_CATAS_ERR_MASTER_ABORT\n", __func__);\r
- }\r
- else {\r
- syndrome = VAPI_CATAS_ERR_GENERAL;\r
- MTL_DEBUG1("%s: VAPI_CATAS_ERR_GENERAL\n", __func__);\r
- }\r
-\r
- THH_hob_fatal_error(eventp->hob, eventp->fatal_type, syndrome);\r
- \r
- FUNC_OUT;\r
-}\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#include <mosal.h>\r
-#include <MT23108.h>\r
-#include <eventp_priv.h>\r
-#include <tavor_if_defs.h>\r
-#include <cmdif.h>\r
-#include <thh_hob.h>\r
-#include <uar.h>\r
-#include <tlog2.h>\r
-#include <tmrwm.h>\r
-//#define MTPERF\r
-#include <mtperf.h>\r
-\r
-#ifdef EQS_CMD_IN_DDR\r
-#include <tddrmm.h>\r
-#endif\r
-\r
-\r
-/*================ macro definitions ===============================================*/\r
-\r
-\r
-/*** error C4296: '<' : expression is always false ***/\r
-#define NOT_VALID_EQ_NUM(eq_num) ((eq_num) >= EQP_MAX_EQS)\r
-\r
-\r
-/*================ type definitions ================================================*/\r
-\r
-#define PHYS_EQ_MAX_SIZE 0x2000\r
-\r
-/*================ global variables definitions ====================================*/\r
-\r
-\r
-MTPERF_EXTERN_SEGMENT(interupt_segment); \r
-MTPERF_EXTERN_SEGMENT(dpc_segment);\r
-MTPERF_EXTERN_SEGMENT(inter2dpc_segment);\r
-MTPERF_EXTERN_SEGMENT(part_of_DPC_segment);\r
-\r
-\r
-/*================ static functions prototypes =====================================*/\r
-\r
-#ifdef MAX_DEBUG\r
-static char * const eq_type_str(EQ_type_t eq_type)\r
-{\r
- switch ( eq_type ) {\r
- case EQP_CQ_COMP_EVENT:\r
- return "EQP_CQ_COMP_EVENT";\r
- case EQP_IB_EVENT:\r
- return "EQP_IB_EVENT";\r
- case EQP_CMD_IF_EVENT:\r
- return "EQP_CMD_IF_EVENT";\r
- case EQP_MLX_EVENT:\r
- return "EQP_MLX_EVENT";\r
- case EQP_CATAS_ERR_EVENT:\r
- return "EQP_CATAS_ERR_EVENT";\r
- default:\r
- return "***UNKNOWNN***";\r
- }\r
-}\r
-#endif\r
-\r
-#ifdef __WIN__\r
-#ifndef MAX_DEBUG\r
-static char * const eq_type_str(EQ_type_t eq_type) { return NULL; }\r
-#endif\r
-#endif\r
-\r
-static THH_eqn_t insert_new_eq(THH_eventp_t eventp,\r
- void* eventh, \r
- void *priv_context, \r
- MT_size_t max_outs_eqe, \r
- EQ_type_t eq_type);\r
-\r
-static HH_ret_t map_eq(THH_eventp_t eventp,\r
- THH_eqn_t eqn,\r
- THH_eventp_mtmask_t tavor_mask);\r
-\r
-static void remove_eq(THH_eventp_t eventp,\r
- THH_eqn_t eqn);\r
-\r
-\r
-static HH_ret_t prepare_intr_resources(THH_eventp_t eventp);\r
-\r
-static HH_ret_t remove_intr_resources(THH_eventp_t eventp);\r
-\r
-static HH_ret_t add_catast_err_eq(THH_eventp_t eventp);\r
-\r
-/*================ external functions definitions ====================================*/\r
-\r
-\r
-\r
-extern void eq_polling_dpc(DPC_CONTEXT_t *func_ctx);\r
-\r
-extern void fatal_error_dpc(DPC_CONTEXT_t *func_ctx);\r
-\r
-extern BOOLEAN thh_intr_handler(MT_ulong_ptr_t eventp, void* isr_ctx1, void* isr_ctx2);\r
-\r
-\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_eventp_create\r
- * \r
- \r
- Arguments:\r
- version_p - Version information \r
- event_res_p - See 7.2.1 THH_eventp_res_t - Event processing resources on page 63 \r
- cmd_if - Command interface object to use for EQ setup commands \r
- kar - KAR object to use for EQ doorbells \r
- eventp_p - Returned object handle \r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL -Invalid parameters \r
- HH_EAGAIN -Not enough resources to create object \r
- HH_ERR - internal error\r
- \r
- Description: \r
- Create THH_eventp object context. No EQs are set up until an event consumer registers \r
- using one of the functions below. \r
- \r
- \r
-************************************************************************/\r
- \r
-HH_ret_t THH_eventp_create ( /*IN */ THH_hob_t hob,\r
- /*IN */ THH_eventp_res_t *event_res_p, \r
- /*IN */ THH_uar_t kar, \r
- /*OUT*/ THH_eventp_t *eventp_p )\r
-{\r
-\r
- THH_eventp_t new_eventp_p = NULL;\r
- u_int32_t i;\r
- HH_ret_t ret;\r
-\r
- FUNC_IN;\r
- \r
- \r
- /* allocation of object structure */\r
- new_eventp_p = (THH_eventp_t)VMALLOC(sizeof(THH_eventp_internal_t));\r
- if (!new_eventp_p) {\r
- MTL_ERROR4("%s: Cannot allocate EVENTP object.\n", __func__);\r
- MT_RETURN(HH_EAGAIN);\r
- }\r
- \r
- memset(new_eventp_p,0,sizeof(THH_eventp_internal_t));\r
- MOSAL_mutex_init(&new_eventp_p->mtx);\r
- for (i= 0; i < EQP_MAX_EQS; i++) {\r
- SET_EQ_FREE(new_eventp_p,i);\r
- new_eventp_p->eq_table[i].eq_buff_entry_num= 0;\r
- new_eventp_p->eq_table[i].alloc_mem_addr_p= 0;\r
- if (MOSAL_spinlock_init(&(new_eventp_p->eq_table[i].state_lock)) != MT_OK){\r
- MTL_ERROR4("%s: Failed to initializing spinlocks.\n", __func__);\r
- ret= HH_ERR;\r
- goto err_free_mem;\r
- } \r
-#ifdef SIMULTANUOUS_DPC\r
-#ifdef IMPROVE_EVENT_HANDLING\r
- new_eventp_p->eq_table[i].dpc_lock = 0;\r
-#else\r
- if (MOSAL_spinlock_init(&(new_eventp_p->eq_table[i].dpc_lock)) != MT_OK){\r
- MTL_ERROR4("%s: Failed to initializing dpc_lock.\n", __func__);\r
- ret= HH_ERR;\r
- goto err_free_mem;\r
- } \r
-#endif \r
-#endif \r
- \r
- }\r
-\r
- /* filling eventp structure */\r
- memcpy(&new_eventp_p->event_resources, event_res_p, sizeof(THH_eventp_res_t));\r
- new_eventp_p->max_eq_num_used = EQP_MIN_EQ_NUM;\r
- new_eventp_p->fatal_type = THH_FATAL_NONE;\r
- new_eventp_p->have_fatal = FALSE;\r
- new_eventp_p->hob = hob;\r
- if (THH_hob_get_cmd_if (hob, &new_eventp_p->cmd_if) != HH_OK){\r
- MTL_ERROR4("%s: Cannot get cmd_if object handle.\n", __func__);\r
- ret = HH_ERR;\r
- goto err_free_mem;\r
- }\r
- new_eventp_p->kar = kar; \r
- if ((ret = THH_uar_get_index(new_eventp_p->kar, &new_eventp_p->kar_index)) != HH_OK){ /* the KAR */\r
- MTL_ERROR4("%s: Failed to THH_uar_get_index. ret=%d.\n", __func__,ret);\r
- ret = HH_ERR;\r
- goto err_free_mem;\r
- }\r
- if (THH_hob_get_ver_info(hob, &new_eventp_p->version) != HH_OK){\r
- MTL_ERROR4("%s: Cannot get version.\n", __func__);\r
- ret = HH_ERR;\r
- goto err_free_mem;\r
- }\r
- if (THH_hob_get_mrwm(hob, &new_eventp_p->mrwm_internal) != HH_OK){\r
- MTL_ERROR4("%s: Cannot get mrwm_internal.\n", __func__);\r
- ret = HH_ERR;\r
- goto err_free_mem;\r
- }\r
-#ifdef EQS_CMD_IN_DDR\r
- if (THH_hob_get_ddrmm(hob, &new_eventp_p->ddrmm) != HH_OK){\r
- MTL_ERROR4("%s: Cannot get ddrmm.\n", __func__);\r
- ret = HH_ERR;\r
- goto err_free_mem;\r
- }\r
-#endif\r
- if (THH_hob_get_hca_hndl(hob, &new_eventp_p->hh_hca_hndl) != HH_OK){\r
- MTL_ERROR4("%s: Cannot get HH_HCA_hndl.\n", __func__);\r
- ret = HH_ERR;\r
- goto err_free_mem;\r
- }\r
-\r
- new_eventp_p->ctx_internal = MOSAL_get_kernel_prot_ctx();\r
-\r
- /* init DPC of master abort & catastrophic error*/\r
- MOSAL_DPC_init(&new_eventp_p->fatal_error_dpc, fatal_error_dpc, (MT_ulong_ptr_t)new_eventp_p, \r
- MOSAL_SINGLE_CTX);\r
-\r
- MTL_TRACE4("%s: SUCCESS to MOSAL_DPC_init the master_abort_dpc. \n", __func__);\r
-\r
- if (prepare_intr_resources(new_eventp_p) != HH_OK){\r
- MTL_ERROR4("%s: Cannot set interrupt resources.\n", __func__);\r
- ret = HH_ERR;\r
- goto err_free_mem;\r
- }\r
-\r
- /* initialize value of CLR_ECR for all EQs */\r
- for ( i=EQP_MIN_EQ_NUM; i<EQP_MAX_EQS; ++i ) {\r
- if (i < 32) {\r
- new_eventp_p->eq_table[i].clr_ecr_addr = new_eventp_p->clr_ecr_l_base;\r
- }\r
- else {\r
- new_eventp_p->eq_table[i].clr_ecr_addr = new_eventp_p->clr_ecr_h_base;\r
- }\r
- new_eventp_p->eq_table[i].clr_ecr_mask = MOSAL_cpu_to_be32(1 << (i % 32));\r
- }\r
-\r
- /* setup the catastrophic error EQ - must be a separete EQ initialzed at the begining */\r
- add_catast_err_eq(new_eventp_p);\r
-\r
- *eventp_p = new_eventp_p;\r
- MT_RETURN(HH_OK);\r
-\r
-\r
- /* error handling cleanup */\r
-err_free_mem:\r
- VFREE(new_eventp_p);\r
- MT_RETURN(ret);\r
-\r
-}\r
-\r
-/************************************************************************\r
- * Function: THH_eventp_destroy\r
- * \r
- \r
- Arguments:\r
- eventp -The THH_eventp object to destroy \r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL -Invalid event object handle \r
- \r
- Description: \r
- Destroy object context. If any EQs are still set they are torn-down when this \r
- function is called Those EQs should generate an HCA catastrophic error ((i.e.callbacks \r
- for IB compliant, proprietary and debug events are invoked) since this call implies \r
- abnormal HCA closure (in a normal HCA closure all EQs should be torn-down before a \r
- call to this function). \r
- \r
- \r
- ************************************************************************/\r
-\r
-HH_ret_t THH_eventp_destroy( /*IN */ THH_eventp_t eventp)\r
-{\r
- THH_eqn_t eqn;\r
-\r
- FUNC_IN;\r
- \r
- if (eventp == NULL) {\r
- MTL_ERROR4("%s: eventp is NULL.\n", __func__);\r
- MT_RETURN( HH_EINVAL);\r
- }\r
-\r
- //MTPERF_REPORT_PRINTF(interupt_segment);\r
- //MTPERF_REPORT_PRINTF(inter2dpc_segment);\r
- //MTPERF_REPORT_PRINTF(dpc_segment);\r
- //MTPERF_REPORT_PRINTF(part_of_DPC_segment);\r
- \r
- \r
- /* Teardown any EQ still up */\r
- for (eqn=0; eqn<EQP_MAX_EQS; eqn++) {\r
- THH_eventp_teardown_eq(eventp, eqn);\r
- } /*for loop */\r
- \r
- MOSAL_mutex_acq_ui(&eventp->mtx);\r
- remove_intr_resources(eventp);\r
- MOSAL_mutex_rel(&eventp->mtx);\r
- MOSAL_mutex_free(&eventp->mtx);\r
- VFREE(eventp);\r
- MT_RETURN( HH_OK);\r
- \r
-\r
-}\r
-/************************************************************************\r
- * Function: THH_eventp_setup_comp_eq\r
- * \r
- Arguments:\r
- eventp -The THH_eventp object handle \r
- eventh -The callback handle for events over this EQ \r
- priv_context -Private context to be used in callback invocation \r
- max_outs_eqe -Maximum outstanding EQEs in EQ created \r
- eqn_p -Allocated EQ index \r
- \r
- Returns:\r
- HH_OK\r
- HH_EINVAL -Invalid handle \r
- HH_EAGAIN -Not enough resources available (e.g.EQC,mem- ory,etc.). \r
- \r
- Description: \r
- Set up an EQ for completion events and register given handler as a callback for \r
- such events. \r
- Note that the created EQ is not mapped to any event at this stage since completion \r
- events are mapped using the CQC set up on CQ creation.\r
- \r
- \r
- ************************************************************************/\r
-\r
- \r
-HH_ret_t THH_eventp_setup_comp_eq(/*IN */ THH_eventp_t eventp, \r
- /*IN */ HH_comp_eventh_t eventh, \r
- /*IN */ void *priv_context, \r
- /*IN */ MT_size_t max_outs_eqe, \r
- /*OUT*/ THH_eqn_t *eqn_p )\r
-\r
-{\r
- THH_eqn_t new_eq;\r
- \r
- FUNC_IN;\r
-\r
- if (eventp == NULL || eventh == NULL || max_outs_eqe == 0) {\r
- MTL_ERROR4("%s: NULL parameter. eventp=%p, eventh=%p, max_outs_eqe=%d\n", __func__,\r
- eventp, eventh, (u_int32_t)max_outs_eqe);\r
- MT_RETURN(HH_EINVAL);\r
- }\r
- if (MOSAL_mutex_acq(&eventp->mtx, TRUE) != MT_OK){\r
-\r
- MTL_ERROR4("%s: MOSAL_mutex_acq failed\n", __func__);\r
- MT_RETURN(HH_EINTR);\r
- }\r
- new_eq = insert_new_eq(eventp, (void*)eventh, priv_context, max_outs_eqe, \r
- EQP_CQ_COMP_EVENT);\r
- \r
- if (new_eq == EQP_MAX_EQS) { /* All EQs are occupied */\r
- MTL_ERROR4("%s: Fail in adding new EQ.\n", __func__);\r
- MOSAL_mutex_rel(&eventp->mtx);\r
- MT_RETURN( HH_EAGAIN);\r
- }\r
- MTL_DEBUG1("%s success: eqn=%d\n", __func__, new_eq);\r
-\r
- *eqn_p = new_eq;\r
- MOSAL_mutex_rel(&eventp->mtx);\r
-\r
- MT_RETURN( HH_OK);\r
-}\r
-\r
-/************************************************************************\r
- * Function: \r
- * \r
- Arguments:\r
- eventp -The THH_eventp object handle \r
- eventh -The callback handle for events over this EQ \r
- priv_context -Private context to be used in callback invocation \r
- max_outs_eqe -Maximum outstanding EQEs in EQ created \r
- eqn_p -Allocated EQ index \r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL -Invalid handle \r
- HH_EAGAIN -Not enough resources available (e.g.EQC,mem- ory,etc.). \r
- HH_ERR - Internal error\r
- \r
- Description: \r
- Set up an EQ and map events given in mask to it. Events over new EQ are reported to \r
- given handler. \r
- \r
- \r
- ************************************************************************/\r
-\r
-HH_ret_t THH_eventp_setup_ib_eq(/*IN */ THH_eventp_t eventp, \r
- /*IN */ HH_async_eventh_t eventh, \r
- /*IN */ void *priv_context, \r
- /*IN */ MT_size_t max_outs_eqe, \r
- /*OUT*/ THH_eqn_t *eqn_p )\r
-\r
-{\r
- THH_eqn_t new_eq;\r
- THH_eventp_mtmask_t tavor_mask=0;\r
-\r
- FUNC_IN;\r
-\r
- if (eventp == NULL || eventh == NULL || max_outs_eqe == 0) {\r
- MTL_ERROR4("%s: NULL parameter. eventp=%p, eventh=%p, max_outs_eqe=%d\n", __func__,\r
- eventp, eventh, (u_int32_t)max_outs_eqe);\r
- MT_RETURN( HH_EINVAL);\r
- }\r
- \r
- if (MOSAL_mutex_acq(&eventp->mtx, TRUE) != MT_OK){\r
-\r
- MTL_ERROR4("%s: MOSAL_mutex_acq failed\n", __func__);\r
- MT_RETURN(HH_EINTR);\r
- }\r
- \r
- new_eq = insert_new_eq(eventp, (void*)eventh, priv_context, max_outs_eqe, \r
- EQP_IB_EVENT);\r
- \r
- if (new_eq == EQP_MAX_EQS) { /* All EQs are occupied */\r
- MTL_ERROR4("%s: Fail in adding new EQ.\n", __func__);\r
- MOSAL_mutex_rel(&eventp->mtx);\r
- MT_RETURN( HH_EAGAIN);\r
- }\r
-\r
- /* map the EQ to events */\r
- /* prepare mask for all IB events */\r
- TAVOR_IF_EV_MASK_SET(tavor_mask,TAVOR_IF_EV_MASK_PATH_MIG);\r
- TAVOR_IF_EV_MASK_SET(tavor_mask,TAVOR_IF_EV_MASK_COMM_EST);\r
- TAVOR_IF_EV_MASK_SET(tavor_mask,TAVOR_IF_EV_MASK_SEND_Q_DRAINED);\r
- TAVOR_IF_EV_MASK_SET(tavor_mask,TAVOR_IF_EV_MASK_CQ_ERR);\r
- TAVOR_IF_EV_MASK_SET(tavor_mask,TAVOR_IF_EV_MASK_LOCAL_WQ_CATAS_ERR);\r
- TAVOR_IF_EV_MASK_SET(tavor_mask,TAVOR_IF_EV_MASK_LOCAL_EE_CATAS_ERR);\r
- TAVOR_IF_EV_MASK_SET(tavor_mask,TAVOR_IF_EV_MASK_PATH_MIG_FAIL );\r
- TAVOR_IF_EV_MASK_SET(tavor_mask,TAVOR_IF_EV_MASK_PORT_ERR);\r
- TAVOR_IF_EV_MASK_SET(tavor_mask,TAVOR_IF_EV_MASK_LOCAL_WQ_INVALID_REQ_ERR);\r
- TAVOR_IF_EV_MASK_SET(tavor_mask,TAVOR_IF_EV_MASK_LOCAL_WQ_ACCESS_VIOL_ERR);\r
- if (eventp->event_resources.is_srq_enable) {\r
- TAVOR_IF_EV_MASK_SET(tavor_mask,TAVOR_IF_EV_MASK_LOCAL_SRQ_CATAS_ERR);\r
- TAVOR_IF_EV_MASK_SET(tavor_mask,TAVOR_IF_EV_MASK_SRQ_QP_LAST_WQE_REACHED);\r
- }\r
-\r
- if (map_eq(eventp, new_eq, tavor_mask) != HH_OK){\r
- MTL_ERROR4("%s: Failed to map EQ.\n", __func__);\r
- MOSAL_mutex_rel(&eventp->mtx);\r
- MT_RETURN( HH_ERR);\r
- }\r
- MTL_DEBUG1("%s: Succeeded to map EQ=%d. mask="U64_FMT"\n", __func__, new_eq, (u_int64_t)tavor_mask);\r
- *eqn_p = new_eq;\r
-\r
- MOSAL_mutex_rel(&eventp->mtx);\r
- \r
- MT_RETURN( HH_OK);\r
-}\r
-\r
-\r
-\r
-/************************************************************************\r
- * Function: \r
- * \r
- Arguments:\r
- eventp -The THH_eventp object handle \r
- \r
- Arguments:\r
- HH_OK \r
- HH_EINVAL -Invalid handle \r
- HH_EAGAIN -Not enough resources available (e.g.EQC,mem- ory,etc.). \r
- EE_ERR - internal error\r
- \r
- Description: \r
- This function setup an EQ and maps command interface events to it. It also takes \r
- care of notifying the THH_cmd associated with it (as de ned on the THH_eventp creation)of \r
- this EQ availability using the THH_cmd_set_eq() (see page 38)function.This causes the THH_cmd \r
- to set event generation to given EQ for all commands dispatched after this noti cation. The \r
- THH_eventp automatically sets noti cation of events from this EQ to the THH_cmd_eventh() \r
- (see page 39)callback of associated THH_cmd. The function should be invoked by the THH_hob \r
- in order to cause the THH_cmd associated with this eventp to execute commands using events. \r
- \r
- \r
- ************************************************************************/\r
-\r
-HH_ret_t THH_eventp_setup_cmd_eq ( /*IN */ THH_eventp_t eventp,\r
- /*IN */ MT_size_t max_outs_eqe)\r
-\r
-{\r
- \r
- THH_eqn_t new_eq;\r
- THH_eventp_mtmask_t tavor_mask = 0;\r
- HH_ret_t ret;\r
- \r
- \r
- FUNC_IN;\r
- \r
- \r
- if (eventp == NULL || max_outs_eqe == 0) {\r
- MTL_ERROR4("%s: NULL parameter. eventp=%p, max_outs_eqe=%d\n", __func__,\r
- eventp, (u_int32_t)max_outs_eqe);\r
- MT_RETURN( HH_EINVAL);\r
- }\r
- \r
- if (MOSAL_mutex_acq(&eventp->mtx, TRUE) != MT_OK){\r
- MTL_ERROR4("%s: MOSAL_mutex_acq failed\n", __func__);\r
- MT_RETURN(HH_EINTR);\r
- }\r
- \r
- new_eq = insert_new_eq(eventp, NULL, NULL, max_outs_eqe, EQP_CMD_IF_EVENT);\r
- \r
- if (new_eq == EQP_MAX_EQS) { /* All EQs are occupied */\r
- MTL_ERROR4("%s: Fail in adding new EQ.\n", __func__);\r
- MOSAL_mutex_rel(&eventp->mtx);\r
- MT_RETURN( HH_EAGAIN);\r
- }\r
- \r
- /* map the EQ to events */\r
- TAVOR_IF_EV_MASK_SET(tavor_mask, TAVOR_IF_EV_MASK_CMD_IF_COMP);\r
- if (map_eq(eventp,new_eq,tavor_mask) != HH_OK){\r
- MTL_ERROR4("%s: Failed to map EQ.\n", __func__);\r
- MOSAL_mutex_rel(&eventp->mtx);\r
- MT_RETURN( HH_ERR);\r
- }\r
-#if 1\r
- if ((ret = THH_cmd_set_eq(eventp->cmd_if)) != HH_OK){\r
- MTL_ERROR4("%s: Failed to THH_cmd_set_eq. ret=%d\n", __func__, ret);\r
- MOSAL_mutex_rel(&eventp->mtx);\r
- MT_RETURN( HH_ERR);\r
- }\r
-#else\r
- ret=HH_OK;\r
-#endif\r
- MOSAL_mutex_rel(&eventp->mtx);\r
-\r
- MTL_DEBUG1("%s success: eqn=%d\n", __func__, new_eq);\r
- \r
- MT_RETURN( HH_OK);\r
-}\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_eventp_setup_mt_eq\r
- * \r
- Arguments:\r
- eventp -The THH_eventp object handle \r
- event_mask -Flags combination of events to map to this EQ \r
- eventh -The callback handle for events over this EQ \r
- priv_context -Private context to be used in callback invocation \r
- max_outs_eqe -Maximum outstanding EQEs in EQ created eqn_p -Allocated EQ index \r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL -Invalid handle \r
- HH_EAGAIN -Not enough resources available (e.g.EQC,mem- ory,etc.). \r
- HH_ERR - internal error\r
- \r
- Description: \r
- Set up an EQ for reporting events beyond IB-spec.(debug events and others). All events \r
- given in the event_mask are mapped to the new EQ. \r
- \r
- \r
- \r
- ************************************************************************/\r
-\r
-HH_ret_t THH_eventp_setup_mt_eq(/*IN */ THH_eventp_t eventp, \r
- /*IN */ THH_eventp_mtmask_t event_mask, \r
- /*IN */ THH_mlx_eventh_t eventh, \r
- /*IN */ void *priv_context, \r
- /*IN */ MT_size_t max_outs_eqe, \r
- /*OUT*/ THH_eqn_t *eqn_p)\r
-\r
-{\r
- THH_eqn_t new_eq;\r
- \r
- FUNC_IN;\r
-\r
- if (eventp == NULL || eventh == NULL || max_outs_eqe == 0 || event_mask == 0) {\r
- MTL_ERROR4("%s: NULL parameter. eventp=%p, eventh=%p, max_outs_eqe=%d, event_mask="U64_FMT"\n", __func__,\r
- eventp, eventh, (u_int32_t)max_outs_eqe, (u_int64_t)event_mask);\r
- MT_RETURN( HH_EINVAL);\r
- }\r
- \r
- if (MOSAL_mutex_acq(&eventp->mtx, TRUE) != MT_OK){\r
- MTL_ERROR4("%s: MOSAL_mutex_acq failed\n", __func__);\r
- MT_RETURN(HH_EINTR);\r
- }\r
-\r
- new_eq = insert_new_eq(eventp, (void*)eventh, priv_context, max_outs_eqe, EQP_MLX_EVENT);\r
-\r
- if (new_eq == EQP_MAX_EQS) { /* All EQs are occupied */\r
- MTL_ERROR4("%s: Fail in adding new EQ.\n", __func__);\r
- MOSAL_mutex_rel(&eventp->mtx);\r
- MT_RETURN( HH_EAGAIN);\r
- }\r
- \r
- /* map the EQ to events */\r
- if (map_eq(eventp,new_eq,event_mask) != HH_OK){\r
- MTL_ERROR4("%s: Failed to map EQ.\n", __func__);\r
- MOSAL_mutex_rel(&eventp->mtx);\r
- MT_RETURN( HH_ERR);\r
- }\r
-\r
- *eqn_p = new_eq;\r
- MOSAL_mutex_rel(&eventp->mtx);\r
-\r
-\r
- MT_RETURN( HH_OK);\r
-}\r
-\r
-\r
-/************************************************************************\r
- * Function: \r
- * \r
- Arguments:\r
- eventp \r
- eq -The EQ to replace handler for \r
- eventh -The new handler \r
- priv_context -Private context to be used with handler\r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL \r
- HH_ENORSC -Given EQ is not set up \r
- \r
- Description: \r
- Replace the callback function of an EQ previously set up. This may be used \r
- in order to change the handler without loosing events.It retains the EQ and \r
- just replaces the callback function.All EQEs polled after a return from this \r
- function will be reported to the new handler.\r
- \r
- ************************************************************************/\r
-\r
-HH_ret_t THH_eventp_replace_handler(/*IN */ THH_eventp_t eventp, \r
- /*IN */ THH_eqn_t eqn, \r
- /*IN */ THH_eventp_handler_t eventh, \r
- /*IN */ void *priv_context)\r
-\r
-{\r
- HH_ret_t ret=HH_OK;\r
- \r
- FUNC_IN;\r
-\r
- if (eventp == NULL || NOT_VALID_EQ_NUM(eqn)){\r
- MTL_ERROR4("%s: Invalid parameter. eventp=%p, eq_num=%d\n", __func__,\r
- eventp, (u_int32_t)eqn);\r
- MT_RETURN( HH_EINVAL);\r
- }\r
-\r
- MOSAL_spinlock_irq_lock(&(eventp->eq_table[eqn].state_lock));\r
- \r
- if (!IS_EQ_VALID(eventp,eqn)){\r
- MOSAL_spinlock_unlock(&(eventp->eq_table[eqn].state_lock));\r
- MTL_ERROR4("%s: EQ %d is not in use.\n", __func__, (u_int32_t)eqn);\r
- MT_RETURN( HH_EINVAL);\r
- }\r
-\r
- switch (eventp->eq_table[eqn].eq_type)\r
- {\r
- case EQP_CQ_COMP_EVENT:\r
- if(eventh.comp_event_h == NULL) {\r
- MTL_ERROR4("%s: Invalid event handler is NULL\n", __func__);\r
- ret = HH_EINVAL;\r
- }\r
- else {\r
- eventp->eq_table[eqn].handler.comp_event_h= eventh.comp_event_h;\r
- }\r
- break;\r
- case EQP_IB_EVENT:\r
- if(eventh.ib_comp_event_h == NULL) {\r
- MTL_ERROR4("%s: Invalid event handler is NULL\n", __func__);\r
- ret = HH_EINVAL;\r
- }\r
- else {\r
- eventp->eq_table[eqn].handler.ib_comp_event_h= eventh.ib_comp_event_h;\r
- }\r
- break;\r
- case EQP_CMD_IF_EVENT: /* no event handler in this case */\r
- break;\r
- case EQP_MLX_EVENT:\r
- if(eventh.mlx_event_h == NULL) {\r
- MTL_ERROR4("%s: Invalid event handler is NULL\n", __func__);\r
- ret = HH_EINVAL;\r
- }\r
- else {\r
- eventp->eq_table[eqn].handler.mlx_event_h= eventh.mlx_event_h;\r
- }\r
- break;\r
- case EQP_CATAS_ERR_EVENT:\r
- MTL_ERROR4("%s: Internal error: EQP_CATAS_ERR_EVENT should not get any handle\n", __func__);\r
- break;\r
- default:\r
- MTL_ERROR4("%s: Internal error: invalid event type.\n", __func__);\r
- ret= HH_ERR;\r
- }\r
- eventp->eq_table[eqn].priv_context = priv_context;\r
- MOSAL_spinlock_unlock(&(eventp->eq_table[eqn].state_lock));\r
-\r
- MT_RETURN(ret);\r
-}\r
-\r
-/************************************************************************\r
- * Function: \r
- * \r
- Arguments:\r
- eventp -The THH_eventp object handle \r
- eqn -The EQ to teardown \r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL -Invalid handles (e.g.no such EQ set up) \r
- \r
- Description: \r
- This function tear down an EQ set up by one of the previous functions. Given eqn \r
- which EQ to tear down. This teardown includes cleaning of any context relating to \r
- the callback associated with it. \r
- \r
- \r
- ************************************************************************/\r
-\r
-HH_ret_t THH_eventp_teardown_eq(/*IN */ THH_eventp_t eventp, \r
- /*IN */ THH_eqn_t eqn )\r
-\r
-{\r
- THH_cmd_status_t cmd_ret;\r
- HH_ret_t ret;\r
- unsigned long i=0;\r
- \r
- FUNC_IN;\r
-\r
- if (eventp == NULL || NOT_VALID_EQ_NUM(eqn)){\r
- MTL_ERROR4("%s: Invalid parameter. eventp=%p, eq_num=%d\n", __func__,\r
- eventp, (u_int32_t)eqn);\r
- MT_RETURN( HH_EINVAL);\r
- }\r
-\r
- \r
- if (MOSAL_mutex_acq(&eventp->mtx, TRUE) != MT_OK){\r
- MTL_ERROR4("%s: MOSAL_mutex_acq failed\n", __func__);\r
- MT_RETURN(HH_EINTR);\r
- }\r
-\r
- MOSAL_spinlock_irq_lock(&(eventp->eq_table[eqn].state_lock));\r
- if (!IS_EQ_VALID(eventp,eqn)) { /* Given EQN is not in use ? */\r
- MOSAL_spinlock_unlock(&(eventp->eq_table[eqn].state_lock)); \r
- if (eventp->max_eq_num_used == eqn) { /* the highest EQ is removed */\r
- eventp->max_eq_num_used--;\r
- }\r
- MOSAL_mutex_rel(&(eventp->mtx));\r
- return HH_EINVAL;\r
- }\r
- SET_EQ_CLEANUP(eventp,eqn); /* Mark EQ while in the cleanup stage (disable DPC sched. from ISR) */\r
- MOSAL_spinlock_unlock(&(eventp->eq_table[eqn].state_lock)); \r
- \r
- /* Wait for all outstanding DPCs */\r
- while (eventp->eq_table[eqn].dpc_cntr)\r
- {\r
- /* this must be done for Linux only since there is no preemption in Linux */\r
- /* (DPC/tasklet cannot run while this context hold the CPU) */\r
-#ifdef __LINUX__\r
- schedule();\r
-#endif\r
- i++;\r
- if (i==0xffffffff) {\r
- MTL_DEBUG4("%s: dpc_cntr was not zero after %lu iterations for eq_num=%d, dpc_cntr=%d\n",\r
- __func__, i, eqn, eventp->eq_table[eqn].dpc_cntr);\r
- i=0;\r
- //break;\r
- }\r
- }\r
- \r
- /* for CMD_IF event need to notify the cmd_if object */\r
- if (eventp->eq_table[eqn].eq_type == EQP_CMD_IF_EVENT){\r
- if ((ret = THH_cmd_clr_eq(eventp->cmd_if)) != HH_OK){\r
- MTL_ERROR4("%s: Failed to THH_cmd_clr_eq. ret=%d\n", __func__, ret);\r
- }\r
- }\r
-\r
- /* unmap events of EQ by putting special EQ number */\r
- /* in case of fatal error - do not call CMD_IF */\r
- if (eventp->have_fatal == FALSE) {\r
- if ((cmd_ret = THH_cmd_MAP_EQ(eventp->cmd_if, TAVOR_IF_UNMAP_QP_BIT, eventp->eq_table[eqn].events_mask))\r
- != THH_CMD_STAT_OK){\r
- MTL_ERROR4("%s: Failed to unmap EQ events. CMD_IF error:%d.\n", __func__,cmd_ret);\r
- }\r
- }\r
- remove_eq(eventp,eqn);\r
- \r
- MOSAL_mutex_rel(&(eventp->mtx));\r
- MT_RETURN( HH_OK);\r
-\r
-}\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_eventp_notify_fatal\r
- * \r
- Arguments:\r
- eventp -The THH_eventp object handle\r
- fatal_err - the error code of the fatal error \r
- \r
- Return:\r
- HH_OK \r
- HH_EINVAL -Invalid handle \r
- \r
- Description: \r
- This function is invoked by THH_hob_fatal_error to notify eventp when a fatal error\r
- has occurred.\r
- \r
- ************************************************************************/\r
-\r
-HH_ret_t THH_eventp_notify_fatal ( /*IN */ THH_eventp_t eventp,\r
- /*IN */ THH_fatal_err_t fatal_err)\r
-{\r
- \r
- FUNC_IN;\r
- \r
- if (eventp == NULL ) {\r
- MTL_ERROR4("%s: NULL parameter. eventp=%p\n",__func__,eventp);\r
- MT_RETURN( HH_EINVAL);\r
- }\r
-\r
- eventp->have_fatal = TRUE;\r
- MT_RETURN(HH_OK);\r
-}\r
-\r
-/************************************************************************\r
- * Function: THH_eventp_handle_fatal\r
- * \r
- Arguments:\r
- eventp -The THH_eventp object handle\r
- \r
- Return:\r
- HH_OK \r
- HH_EINVAL -Invalid handle \r
- \r
- Description: \r
- This function is invoked by THH_hob_fatal_error t\r
- \r
- \r
- \r
- o handle the fatal error\r
- has occurred.\r
- \r
- ************************************************************************/\r
-\r
-HH_ret_t THH_eventp_handle_fatal ( /*IN */ THH_eventp_t eventp)\r
-{\r
- \r
- FUNC_IN;\r
- \r
- if (eventp == NULL ) {\r
- MTL_ERROR4("%s: NULL parameter. eventp=%p\n", __func__, eventp);\r
- MT_RETURN( HH_EINVAL);\r
- }\r
-\r
- MT_RETURN(HH_OK);\r
-}\r
-\r
-\r
-/********************* STATIC FUNCTIONS ************************************************/\r
-\r
-/* This function must be invoked with eventp's mutex locked */\r
-static THH_eqn_t insert_new_eq(THH_eventp_t eventp,\r
- void* eventh, \r
- void *priv_context, \r
- MT_size_t max_outs_eqe, \r
- EQ_type_t eq_type)\r
-{\r
- unsigned int new_eq=EQP_MAX_EQS+1;\r
- EQP_eq_entry_t *new_entry;\r
- THH_internal_mr_t params;\r
- THH_eqc_t eq_context;\r
- MT_size_t entries_num;\r
- THH_cmd_status_t cmd_ret;\r
- HH_ret_t ret=HH_OK;\r
- MT_bool virtual_eq = TRUE;\r
- VAPI_size_t alloc_mem_bytes_size;\r
- call_result_t rc;\r
-\r
- \r
- FUNC_IN;\r
- /* TK NOTE: this will not work if we have more then one EQ from the same type\r
- In this case we will need to change this huristic */\r
- switch (eq_type) {\r
- case EQP_CATAS_ERR_EVENT:\r
- new_eq = EQP_CATAS_ERR_EQN;\r
- break;\r
- case EQP_CQ_COMP_EVENT:\r
- new_eq = EQP_CQ_COMP_EQN;\r
- break;\r
- case EQP_IB_EVENT:\r
- new_eq = EQP_ASYNCH_EQN;\r
- break;\r
- case EQP_CMD_IF_EVENT:\r
- new_eq = EQP_CMD_IF_EQN;\r
- break;\r
- case EQP_MLX_EVENT: /* currently not supported */\r
- break;\r
- default:\r
- MTL_ERROR4("%s: Internal error: invalid event queue type.\n", __func__);\r
- return EQP_MAX_EQS;\r
- }\r
-\r
- MTL_DEBUG3("%s:eq_type=%s; eq_num=%d \n", __func__, eq_type_str(eq_type), new_eq);\r
- \r
- if (new_eq != EQP_MAX_EQS+1) { /* one of the above types */\r
- SET_EQ_INIT(eventp,new_eq); /* reserve EQ while initializing */\r
- }\r
- else { /* Not one of the above types */\r
- /* TK: this code is not realy working now since no other types of EQs are exposed */\r
- for (new_eq= EQP_MIN_EQ_NUM; new_eq < EQP_MAX_EQS; new_eq++) {/* Find free EQ */\r
- /* reserve EQ while initializing */\r
- MOSAL_spinlock_irq_lock(&(eventp->eq_table[new_eq].state_lock));\r
- if (IS_EQ_FREE(eventp,new_eq)) { /* find free entry */\r
- SET_EQ_INIT(eventp,new_eq); /* reserve EQ while initializing */\r
- if (new_eq+1 > eventp->max_eq_num_used) {\r
- eventp->max_eq_num_used=new_eq+1; /* should be done under spinlock since the intr handler use this */\r
- }\r
- MOSAL_spinlock_unlock(&(eventp->eq_table[new_eq].state_lock));\r
- break;\r
- }\r
- MOSAL_spinlock_unlock(&(eventp->eq_table[new_eq].state_lock));\r
- }\r
- }\r
- \r
- /* no free EQ */\r
- if (new_eq == EQP_MAX_EQS) {\r
- MTL_ERROR4("%s: All EQs are busy.\n", __func__);\r
- MT_RETURN( EQP_MAX_EQS);\r
- }\r
- \r
- MTL_DEBUG3("%s: in params: max_outs_eqe = "SIZE_T_FMT", eq_type=%s; got EQ num = %d\n", \r
- __func__, max_outs_eqe, eq_type_str(eq_type), new_eq);\r
- new_entry = &(eventp->eq_table[new_eq]);\r
- /* number of outs_eqes must be power of 2 */\r
- entries_num = THH_CYCLIC_BUFF_SIZE(max_outs_eqe); /* already take care for the empty entry in cyclic buff */\r
- \r
-#ifdef EQS_CMD_IN_DDR\r
- /* when EQEs in DDR we can get the alignment we need */\r
- alloc_mem_bytes_size = entries_num*EQ_ENTRY_SIZE;\r
- virtual_eq=FALSE;\r
- ret = THH_ddrmm_alloc(eventp->ddrmm, alloc_mem_bytes_size, floor_log2(EQ_ENTRY_SIZE), \r
- &new_entry->alloc_mem_addr_p);\r
- if ( ret != HH_OK ) {\r
- MTL_ERROR4("%s: failed to allocate ddr memory\n", __func__);\r
- goto err_free_eq;\r
- }\r
- new_entry->eq_buff = (void*)MOSAL_io_remap(new_entry->alloc_mem_addr_p, alloc_mem_bytes_size); \r
- if ( !new_entry->eq_buff ) {\r
- goto err_free_alloc;\r
- }\r
- memset((void*)new_entry->eq_buff,0xff,alloc_mem_bytes_size);\r
-#else\r
- /* EQS are in main memory */\r
- /* need to add 1 for the alignment */\r
- alloc_mem_bytes_size = (entries_num+1)*EQ_ENTRY_SIZE;\r
- /* if this is a small EQ then work with physically contiguous memory */\r
- if (alloc_mem_bytes_size <= PHYS_EQ_MAX_SIZE) {\r
-/*** warning C4242: 'function' : conversion from 'VAPI_size_t' to 'MT_size_t', possible loss of data ***/\r
- new_entry->alloc_mem_addr_p = (MT_virt_addr_t)MOSAL_pci_phys_alloc_consistent((MT_size_t)alloc_mem_bytes_size, floor_log2(EQ_ENTRY_SIZE));\r
- if (new_entry->alloc_mem_addr_p != 0) {\r
- virtual_eq=FALSE;\r
- MTL_TRACE5("%s: EQ %d is going to be with physical memory. \n", __func__,new_eq);\r
- }\r
- }\r
-\r
- if (virtual_eq) {\r
-/*** warning C4242: 'function' : conversion from 'VAPI_size_t' to 'const size_t', possible loss of data ***/\r
- new_entry->alloc_mem_addr_p = (MT_virt_addr_t)MOSAL_pci_virt_alloc_consistent((size_t)alloc_mem_bytes_size, floor_log2(EQ_ENTRY_SIZE));\r
- if (!new_entry->alloc_mem_addr_p) {\r
- MTL_ERROR4("%s: Cannot allocate EQE buffer.\n", __func__);\r
- goto err_free_eq;\r
- }\r
- }\r
- \r
- /* EQEs cyclic buffer should be aligned to entry size */\r
- new_entry->eq_buff = (void *)MT_UP_ALIGNX_VIRT(new_entry->alloc_mem_addr_p, floor_log2(EQ_ENTRY_SIZE)); \r
-/*** warning C4242: 'function' : conversion from 'VAPI_size_t' to 'size_t', possible loss of data ***/\r
- memset((void*)new_entry->alloc_mem_addr_p,0xff,(size_t)alloc_mem_bytes_size);\r
-#endif\r
-\r
-\r
- MTL_DEBUG3("%s: real entries_num = "SIZE_T_FMT", table size= "SIZE_T_FMT"\n", __func__, entries_num,(entries_num * EQ_ENTRY_SIZE) );\r
- new_entry->pd = THH_RESERVED_PD;\r
- new_entry->priv_context = priv_context;\r
- new_entry->dpc_cntr= 0;\r
- new_entry->eventp_p = eventp;\r
- new_entry->virtual_eq = virtual_eq;\r
- new_entry->eq_type = eq_type;\r
- new_entry->eqn = new_eq;\r
- new_entry->cons_indx= 0;\r
- switch (eq_type)\r
- {\r
- case EQP_CQ_COMP_EVENT:\r
- new_entry->handler.comp_event_h = (HH_comp_eventh_t)eventh;\r
- break;\r
- case EQP_IB_EVENT:\r
- new_entry->handler.ib_comp_event_h = (HH_async_eventh_t)eventh;\r
- break;\r
- case EQP_CMD_IF_EVENT: /* no event handler in this case */\r
- break;\r
- case EQP_MLX_EVENT:\r
- new_entry->handler.mlx_event_h = (THH_mlx_eventh_t)eventh;\r
- break;\r
- case EQP_CATAS_ERR_EVENT:\r
- new_entry->handler.mlx_event_h = NULL; /* no handler for catast error */\r
- break;\r
- default:\r
- MTL_ERROR4("%s: Internal error: invalid event queue type.\n", __func__);\r
- goto err_free_mem;\r
- }\r
- \r
- if (virtual_eq) {\r
- /* registering memory region for this buffer */\r
- memset(¶ms, 0, sizeof(params));\r
- params.start = (IB_virt_addr_t)(MT_virt_addr_t)(new_entry->eq_buff);\r
- params.size = (VAPI_size_t)entries_num * EQ_ENTRY_SIZE;\r
- params.pd = THH_RESERVED_PD;\r
- params.vm_ctx = MOSAL_get_kernel_prot_ctx(); //eventp->ctx_internal;\r
- params.force_memkey = FALSE;\r
-\r
- MTL_DEBUG4("%s: registering mem region. start addr="U64_FMT", size="U64_FMT"\n", __func__,\r
- params.start, params.size);\r
- if((ret = THH_mrwm_register_internal(eventp->mrwm_internal, ¶ms, &new_entry->mem_lkey)) != HH_OK){\r
- MTL_ERROR4("%s: Failed to register EQ buffer in memory. ret=%d\n", __func__, ret);\r
- goto err_free_mem;\r
- }\r
- MTL_TRACE4("%s: SUCCESS to register EQ buffer in memory. \n", __func__);\r
- }\r
- else {\r
- new_entry->mem_lkey = 0;\r
- }\r
- \r
- /* prepare EQ for HW ownership */\r
- memset(&eq_context,0,sizeof(THH_eqc_t));\r
- eq_context.st = EQ_STATE_ARMED;\r
-\r
- if (eq_type == EQP_CATAS_ERR_EVENT) {\r
- eq_context.oi = TRUE; /* Overrun detection ignore */\r
- }\r
- else {\r
- eq_context.oi = FALSE; /* Overrun detection ignore */\r
- }\r
- \r
- eq_context.tr = virtual_eq; /* Translation Required. If set - EQ access undergo address translation. */\r
- eq_context.owner = THH_OWNER_HW; /* SW/HW ownership */\r
- eq_context.status = EQ_STATUS_OK; /* EQ status:\;0000 - OK\;1001 - EQ overflow\;1010 - EQ write failure */\r
- if (virtual_eq) {\r
- eq_context.start_address = (u_int64_t)(MT_virt_addr_t)new_entry->eq_buff; /* Start Address of Event Queue. Must be aligned on 32-byte boundary */\r
- }\r
- else {\r
-#ifdef EQS_CMD_IN_DDR\r
- eq_context.start_address = (u_int64_t)(new_entry->alloc_mem_addr_p);\r
-#else \r
- MT_phys_addr_t pa;\r
-\r
- rc = MOSAL_virt_to_phys(MOSAL_get_kernel_prot_ctx(), (MT_virt_addr_t)new_entry->eq_buff, &pa);\r
- if ( rc != MT_OK ) {\r
- MTL_ERROR4(MT_FLFMT("%s: failed va=%p"), __func__, new_entry->eq_buff);\r
- goto err_unreg_mem;\r
- }\r
- else {\r
- eq_context.start_address = (u_int64_t)pa;\r
- }\r
-#endif \r
- }\r
- \r
- if ((ret = THH_uar_get_index(eventp->kar, &eq_context.usr_page)) != HH_OK){ /* the KAR */\r
- MTL_ERROR4("%s: Failed to THH_uar_get_index. ret=%d.\n", __func__,ret);\r
- goto err_unreg_mem;\r
- }\r
- eq_context.log_eq_size = floor_log2(entries_num); /* Log2 of the amount of entries in the EQ */\r
- eq_context.intr = eventp->event_resources.intr_clr_bit; /* Interrupt (message) to be generated to report event to INT layer.\r
- \;0000iiii - specifies GPIO pin to be asserted\r
- \;1jjjjjjj - specificies type of interrupt message to be generated (total 128 different messages supported). */\r
- eq_context.lkey = new_entry->mem_lkey; /* Memory key (L-Key) to be used to access EQ */\r
- eq_context.consumer_indx = 0; /* Contains next entry to be read upon poll for completion. Must be initialized to '0 while opening EQ */\r
- eq_context.producer_indx = 0; /* Contains next entry in EQ to be written by the HCA. Must be initialized to '1 while opening EQ. */\r
- eq_context.pd = THH_RESERVED_PD; // TK - need to add to structure\r
- \r
- if ((cmd_ret = THH_cmd_SW2HW_EQ(eventp->cmd_if, new_eq, &eq_context)) != THH_CMD_STAT_OK){\r
- MTL_ERROR4("%s: Failed to move EQ to HW ownership. CMD_IF error:%d.\n", __func__,cmd_ret);\r
- goto err_unreg_mem;\r
- }\r
- \r
- MTL_TRACE4("%s: SUCCESS to THH_cmd_SW2HW_EQ EQ=%d. \n", __func__,new_eq);\r
- /* init DPC of this EQ */\r
- if (eq_type != EQP_CATAS_ERR_EVENT) {\r
- MOSAL_DPC_init(&new_entry->polling_dpc, eq_polling_dpc, (MT_ulong_ptr_t)new_entry, MOSAL_SINGLE_CTX);\r
- }\r
- /* each eq use only one word (high or low) of the clr_ecr_reg \r
- decide on this if EQ number is bigger then 32. \r
- also prepare the mask to be used when polling the EQ in the DPC */\r
- \r
- MTL_TRACE4("%s: SUCCESS to MOSAL_DPC_init. \n", __func__);\r
- if (new_eq < 32) {\r
- new_entry->clr_ecr_addr = eventp->clr_ecr_l_base;\r
- }\r
- else {\r
- new_entry->clr_ecr_addr = eventp->clr_ecr_h_base;\r
- }\r
- new_entry->clr_ecr_mask = MOSAL_cpu_to_be32(1 << (new_eq % 32));\r
-\r
- /* this must be done last since this is the indication that the entry is valid */\r
- new_entry->alloc_mem_bytes_size = alloc_mem_bytes_size;\r
- new_entry->eq_buff_entry_num = entries_num;\r
- SET_EQ_VALID(eventp,new_eq);\r
-\r
- MT_RETURN( (THH_eqn_t)new_eq);\r
-\r
- /* error handling */\r
-err_unreg_mem:\r
- if (virtual_eq) {\r
- if ((ret = THH_mrwm_deregister_mr(eventp->mrwm_internal, new_entry->mem_lkey)) != HH_OK){\r
- MTL_ERROR4("%s: Failed to deregister memory region. ret=%d\n", __func__,ret);\r
- }\r
- }\r
-err_free_mem: \r
-#ifdef EQS_CMD_IN_DDR\r
- MOSAL_io_unmap((MT_virt_addr_t)new_entry->eq_buff);\r
-err_free_alloc:\r
- ret = THH_ddrmm_free(eventp->ddrmm, new_entry->alloc_mem_addr_p, alloc_mem_bytes_size);\r
- if ( ret != HH_OK ) {\r
- MTL_ERROR4("%s: failed to THH_ddrmm_free\n", __func__);\r
- }\r
-#else \r
- if (virtual_eq) {\r
- MOSAL_pci_virt_free_consistent((void *)new_entry->alloc_mem_addr_p, alloc_mem_bytes_size);\r
- }\r
- else {\r
-/*** warning C4242: 'function' : conversion from 'VAPI_size_t' to 'MT_size_t', possible loss of data ***/\r
- MOSAL_pci_phys_free_consistent((void *)(MT_ulong_ptr_t)new_entry->alloc_mem_addr_p, (MT_size_t)alloc_mem_bytes_size);\r
- }\r
-#endif\r
-err_free_eq:\r
- SET_EQ_FREE(eventp,new_eq); /* return EQ to free-pool */\r
- MT_RETURN(EQP_MAX_EQS);\r
-} /* insert_new_eq */\r
- \r
-\r
-/************************************************************************/\r
-\r
-\r
-static HH_ret_t map_eq(THH_eventp_t eventp,\r
- THH_eqn_t eqn,\r
- THH_eventp_mtmask_t tavor_mask)\r
-{\r
- THH_cmd_status_t cmd_ret;\r
-\r
- \r
- FUNC_IN;\r
- /* save mask for later unmapping when EQ is teared down */\r
- eventp->eq_table[eqn].events_mask = tavor_mask;\r
- MTL_TRACE4("%s: EQ=%d mask="U64_FMT" \n", __func__, eqn, (u_int64_t)tavor_mask);\r
-\r
- if ((cmd_ret = THH_cmd_MAP_EQ(eventp->cmd_if, eqn, tavor_mask))!= THH_CMD_STAT_OK){\r
- MTL_ERROR4("%s: Failed to map EQ events. CMD_IF error:%d EQN=%d.\n", __func__,cmd_ret,eqn);\r
- /* due to this error need to remove EQ */\r
- remove_eq(eventp, eqn);\r
- MT_RETURN( HH_ERR);\r
- }\r
- MTL_TRACE4("%s: SUCCESS to THH_cmd_MAP_EQ. EQ=%d mask="U64_FMT" \n", __func__, eqn, (u_int64_t)tavor_mask);\r
- MT_RETURN( HH_OK);\r
-}\r
-\r
-\r
-/************************************************************************/\r
-\r
-\r
-static void remove_eq(THH_eventp_t eventp,\r
- THH_eqn_t eqn)\r
-{\r
- THH_cmd_status_t cmd_ret;\r
- THH_eqc_t eq_context;\r
- VAPI_size_t buf_sz;\r
-#ifdef EQS_CMD_IN_DDR\r
- MT_phys_addr_t buf_addr;\r
-#else\r
- void* buf_addr;\r
-#endif\r
- MT_bool virt_buf;\r
- HH_ret_t ret;\r
-\r
- \r
- FUNC_IN;\r
- \r
- /* clear EQC (in SW ownership) */\r
- memset(&eq_context,0,sizeof(THH_eqc_t));\r
- \r
- /* in case of fatal error - do not call CMD_IF */\r
- if (eventp->have_fatal == FALSE) {\r
- if ((cmd_ret = THH_cmd_HW2SW_EQ(eventp->cmd_if, eqn, &eq_context)) != THH_CMD_STAT_OK){\r
- MTL_ERROR4("%s: Failed to move EQ to SW ownership. CMD_IF error:%d.\n", __func__,cmd_ret);\r
- /* TK - maybe we need to exit in this case */\r
- }\r
- }\r
- /* unregister MR of buffer and free the eq_buff */\r
- if (eventp->eq_table[eqn].virtual_eq) {\r
- ret = THH_mrwm_deregister_mr(eventp->mrwm_internal, eventp->eq_table[eqn].mem_lkey);\r
- if (ret != HH_OK){ \r
- MTL_ERROR4("%s: Failed to deregister memory region. ret=%d\n", __func__,ret);\r
- }\r
- }\r
- MOSAL_spinlock_irq_lock(&(eventp->eq_table[eqn].state_lock));\r
- virt_buf= eventp->eq_table[eqn].virtual_eq;\r
-#ifdef EQS_CMD_IN_DDR\r
- buf_addr= eventp->eq_table[eqn].alloc_mem_addr_p;\r
-#else\r
- buf_addr= (void*)eventp->eq_table[eqn].alloc_mem_addr_p;\r
-#endif\r
- buf_sz= eventp->eq_table[eqn].alloc_mem_bytes_size;\r
-\r
- eventp->eq_table[eqn].alloc_mem_addr_p= 0;\r
- eventp->eq_table[eqn].eq_buff_entry_num = 0; \r
- eventp->eq_table[eqn].alloc_mem_bytes_size = 0;\r
- SET_EQ_FREE(eventp,eqn);\r
- MOSAL_spinlock_unlock(&(eventp->eq_table[eqn].state_lock)); \r
-\r
- /* Free buffer */\r
- \r
-#ifdef EQS_CMD_IN_DDR\r
- MOSAL_io_unmap((MT_virt_addr_t)eventp->eq_table[eqn].eq_buff);\r
- ret = THH_ddrmm_free(eventp->ddrmm, buf_addr, buf_sz);\r
- if ( ret != HH_OK ) {\r
- MTL_ERROR4("%s: failed to THH_ddrmm_free\n", __func__);\r
- }\r
-#else \r
- if (virt_buf) {\r
- MOSAL_pci_virt_free_consistent(buf_addr, buf_sz);\r
- }\r
- else {\r
-/*** warning C4242: 'function' : conversion from 'VAPI_size_t' to 'MT_size_t', possible loss of data ***/\r
- MOSAL_pci_phys_free_consistent(buf_addr, (MT_size_t)buf_sz);\r
- }\r
-#endif\r
- \r
- FUNC_OUT;\r
- return;\r
-}\r
-\r
-\r
-/************************************************************************************************/\r
-\r
-HH_ret_t prepare_intr_resources(THH_eventp_t eventp)\r
-{\r
- call_result_t msl_ret;\r
-\r
- MT_phys_addr_t cr_base = eventp->event_resources.cr_base;\r
- \r
- FUNC_IN;\r
- /* map both ecr & clr_ecr registers (4 words) */\r
- // TK: need to use the structure and do separate io remap for each register\r
- if ((eventp->ecr_h_base = MOSAL_io_remap(cr_base+TAVOR_ECR_H_OFFSET_FROM_CR_BASE, 4*sizeof(u_int32_t))) \r
- == 0){\r
- MTL_ERROR1("%s: Failed to MOSAL_io_remap for ECR\n", __func__);\r
- MT_RETURN( HH_ERR);\r
- }\r
- eventp->ecr_l_base = eventp->ecr_h_base + 4;\r
- eventp->clr_ecr_h_base = eventp->ecr_h_base + 8;\r
- eventp->clr_ecr_l_base = eventp->ecr_h_base + 12;\r
-\r
-\r
- MTL_DEBUG1("%s: ECR register="VIRT_ADDR_FMT"\n", __func__, eventp->ecr_h_base );\r
-\r
- \r
- /* if interrupt bit < 32: we use the low word and otherwise the high word of the clr_int register */\r
- if ((eventp->intr_clr_reg = MOSAL_io_remap(cr_base + (eventp->event_resources.intr_clr_bit<32 ? \r
- TAVOR_CLR_INT_L_OFFSET_FROM_CR_BASE : TAVOR_CLR_INT_H_OFFSET_FROM_CR_BASE),\r
- sizeof(u_int32_t))) == 0)\r
- {\r
- MTL_ERROR1("%s: Failed to MOSAL_io_remap for INTR_CLR_REG\n", __func__);\r
- MT_RETURN( HH_ERR);\r
- }\r
- eventp->intr_clr_mask = MOSAL_be32_to_cpu(1 << (eventp->event_resources.intr_clr_bit % 32));\r
- \r
- //MTL_DEBUG1("%s: TAVOR IRQ=%d\n", __func__, eventp->event_resources.irq);\r
- if ((msl_ret = MOSAL_ISR_set(&eventp->isr_obj, thh_intr_handler, eventp->event_resources.irq,\r
- "InfiniHost", (MT_ulong_ptr_t)eventp)) != MT_OK){\r
- MTL_ERROR1("%s: Failed to MOSAL_ISR_set MOSAL ret=%d\n", __func__, msl_ret);\r
- MT_RETURN( HH_ERR);\r
- }\r
- MT_RETURN( HH_OK);\r
-}\r
-\r
-\r
-/*\r
-***********************************************************************************************/\r
-\r
-HH_ret_t remove_intr_resources(THH_eventp_t eventp)\r
-{\r
- call_result_t msl_ret;\r
-\r
-\r
- FUNC_IN;\r
- MOSAL_io_unmap(eventp->ecr_h_base);\r
- MOSAL_io_unmap(eventp->intr_clr_reg);\r
-\r
- if ((msl_ret = MOSAL_ISR_unset(&eventp->isr_obj)) != MT_OK){\r
- MTL_ERROR1("%s: Failed to MOSAL_ISR_unset MOSAL ret=%d\n", __func__, msl_ret);\r
- MT_RETURN( HH_ERR);\r
- }\r
- MT_RETURN( HH_OK);\r
-}\r
-\r
-/************************************************************************************************/\r
-\r
-\r
-static HH_ret_t add_catast_err_eq(THH_eventp_t eventp)\r
-{\r
- THH_eventp_mtmask_t tavor_mask=0;\r
- \r
- FUNC_IN;\r
- \r
- if (MOSAL_mutex_acq(&eventp->mtx, TRUE) != MT_OK){\r
-\r
- MTL_ERROR4("%s: MOSAL_mutex_acq failed\n", __func__);\r
- MT_RETURN(HH_EINTR);\r
- }\r
- \r
- if (insert_new_eq(eventp, (void*)NULL, NULL, 4, EQP_CATAS_ERR_EVENT) == EQP_MAX_EQS) {\r
- MTL_ERROR4("%s: Failed to add the catastrophic event EQ.\n", __func__);\r
- MT_RETURN (HH_ERR);\r
- }\r
-\r
- TAVOR_IF_EV_MASK_SET(tavor_mask, TAVOR_IF_EV_MASK_LOCAL_CATAS_ERR);\r
-\r
- if (map_eq(eventp, EQP_CATAS_ERR_EQN, tavor_mask) != HH_OK){\r
- MTL_ERROR4("%s: Failed to map catastrophic error EQ.\n", __func__);\r
- MOSAL_mutex_rel(&eventp->mtx);\r
- MT_RETURN( HH_ERR);\r
- }\r
- MOSAL_mutex_rel(&eventp->mtx);\r
- MTL_DEBUG1("%s: Succeeded to map EQ=%d. mask="U64_FMT"\n", __func__, \r
- EQP_CATAS_ERR_EQN, (u_int64_t)tavor_mask);\r
- MT_RETURN(HH_OK);\r
-\r
-}\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_EVENTP_H\r
-#define H_EVENTP_H\r
-\r
-#include <mtl_common.h>\r
-#include <tavor_if_defs.h>\r
-#include <vapi_types.h>\r
-#include <hh.h>\r
-#include <thh.h>\r
-\r
-\r
-typedef struct THH_eventp_res_st{\r
- MT_phys_addr_t cr_base; /* physical address of the CR-space */\r
- u_int8_t intr_clr_bit; /* Bit number to clear using the interrupt clear register */\r
- MOSAL_IRQ_ID_t irq; /* IRQ line to hook interrupt handler to */\r
- MT_bool is_srq_enable; /* Is SRQ supported in this FW */\r
-} THH_eventp_res_t;\r
-\r
-\r
-\r
-/* Mask bits from tavor_if_eventt_mask_enum_t in tavor_if_defs.h */\r
-typedef tavor_if_eventt_mask_t THH_eventp_mtmask_t;\r
-\r
-#define TAVOR_IF_EV_MASK_CLR_ALL(mask) ((mask)=0)\r
-#define TAVOR_IF_EV_MASK_SET(mask,attr) ((mask)=((mask)|(attr)))\r
-#define TAVOR_IF_EV_MASK_CLR(mask,attr) ((mask)=((mask)&(~(attr))))\r
-#define TAVOR_IF_EV_IS_SET(mask,attr) (((mask)&(attr))!=0)\r
-\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_eventp_create\r
- * \r
- \r
- Arguments:\r
- version_p - Version information \r
- event_res_p - See 7.2.1 THH_eventp_res_t - Event processing resources on page 63 \r
- cmd_if - Command interface object to use for EQ setup commands \r
- kar - KAR object to use for EQ doorbells \r
- eventp_p - Returned object handle \r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL -Invalid parameters \r
- HH_EAGAIN -Not enough resources to create object \r
- \r
- Description: \r
- Create THH_eventp object context. No EQs are set up until an event consumer registers \r
- using one of the functions below. \r
- \r
- \r
- ************************************************************************/\r
- \r
-extern HH_ret_t THH_eventp_create ( /*IN */ THH_hob_t hob,\r
- /*IN */ THH_eventp_res_t *event_res_p, \r
- /*IN */ THH_uar_t kar, \r
- /*OUT*/ THH_eventp_t *eventp_p );\r
-\r
-/************************************************************************\r
- * Function: THH_eventp_destroy\r
- * \r
- \r
- Arguments:\r
- eventp -The THH_eventp object to destroy \r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL -Invalid event object handle \r
- HH_ERR - internal error\r
- \r
- Description: \r
- Destroy object context. If any EQs are still set they are torn-down when this \r
- function is called Those EQs should generate an HCA catastrophic error ((i.e.callbacks \r
- for IB compliant, proprietary and debug events are invoked) since this call implies \r
- abnormal HCA closure (in a normal HCA closure all EQs should be torn-down before a \r
- call to this function). \r
- \r
- \r
- ************************************************************************/\r
-\r
-extern HH_ret_t THH_eventp_destroy( /*IN */ THH_eventp_t eventp );\r
-\r
-/************************************************************************\r
- * Function: THH_eventp_setup_comp_eq\r
- * \r
- Arguments:\r
- eventp -The THH_eventp object handle \r
- eventh -The callback handle for events over this EQ \r
- priv_context -Private context to be used in callback invocation \r
- max_outs_eqe -Maximum outstanding EQEs in EQ created \r
- eqn_p -Allocated EQ index \r
- \r
- Returns:\r
- HH_OK\r
- HH_EINVAL -Invalid handle \r
- HH_EAGAIN -Not enough resources available (e.g.EQC,mem- ory,etc.).\r
- HH_ERR - internal error\r
- \r
- Description: \r
- Set up an EQ for completion events and register given handler as a callback for such events. \r
- Note that the created EQ is not mapped to any event at this stage since completion events are \r
- mapped using the CQC set up on CQ creation.\r
- \r
- \r
- ************************************************************************/\r
-\r
- \r
-extern HH_ret_t THH_eventp_setup_comp_eq(/*IN */ THH_eventp_t eventp, \r
- /*IN */ HH_comp_eventh_t eventh, \r
- /*IN */ void *priv_context, \r
- /*IN */ MT_size_t max_outs_eqe, \r
- /*OUT*/ THH_eqn_t *eqn_p );\r
-\r
-\r
-/************************************************************************\r
- * Function: \r
- * \r
- Arguments:\r
- eventp -The THH_eventp object handle \r
- event_mask -Flags combination of events to map to this EQ \r
- eventh -The callback handle for events over this EQ \r
- priv_context -Private context to be used in callback invocation \r
- max_outs_eqe -Maximum outstanding EQEs in EQ created \r
- eqn_p -Allocated EQ index \r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL -Invalid handle \r
- HH_EAGAIN -Not enough resources available (e.g.EQC,mem- ory,etc.). \r
- HH_ERR - internal error\r
- \r
- Description: \r
- Set up an EQ and map events given in mask to it. Events over new EQ are reported to \r
- given handler. \r
- \r
- \r
- ************************************************************************/\r
-\r
-extern HH_ret_t THH_eventp_setup_ib_eq(/*IN */ THH_eventp_t eventp, \r
- /*IN */ HH_async_eventh_t eventh, \r
- /*IN */ void *priv_context, \r
- /*IN */ MT_size_t max_outs_eqe, \r
- /*OUT*/ THH_eqn_t *eqn_p );\r
-\r
-\r
-/************************************************************************\r
- * Function: \r
- * \r
- Arguments:\r
- eventp -The THH_eventp object handle \r
- max_outs_eqe -Maximum outstanding EQEs in EQ created \r
- \r
- \r
- Return::\r
- HH_OK \r
- HH_EINVAL -Invalid handle \r
- HH_EAGAIN -Not enough resources available (e.g.EQC,mem- ory,etc.). \r
- HH_ERR - internal error\r
- \r
- Description: \r
- This function setup an EQ and maps command interface events to it. It also takes \r
- care of notifying the THH_cmd associated with it (as de ned on the THH_eventp creation)of \r
- this EQ availability using the THH_cmd_set_eq() (see page 38)function.This causes the THH_cmd \r
- to set event generation to given EQ for all commands dispatched after this noti cation. The \r
- THH_eventp automatically sets noti cation of events from this EQ to the THH_cmd_eventh() \r
- (see page 39)callback of assoicated THH_cmd. The function should be invoked by the THH_hob \r
- in order to cause the THH_cmd associated with this eventp to execute commands using events. \r
- \r
- \r
- ************************************************************************/\r
-\r
-extern HH_ret_t THH_eventp_setup_cmd_eq ( /*IN */ THH_eventp_t eventp,\r
- /*IN */ MT_size_t max_outs_eqe);\r
-\r
-/************************************************************************\r
- * Function: \r
- * \r
- Arguments:\r
- eventp -The THH_eventp object handle \r
- event_mask -Flags combination of events to map to this EQ \r
- eventh -The callback handle for events over this EQ \r
- priv_context -Private context to be used in callback invocation \r
- max_outs_eqe -Maximum outstanding EQEs in EQ created eqn_p -Allocated EQ index \r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL -Invalid handle \r
- HH_EAGAIN -Not enough resources available (e.g.EQC,mem- ory,etc.). \r
- HH_ERR - internal error\r
- \r
- Description: \r
- Set up an EQ for reporting events beyond IB-spec.(debug events and others). All events \r
- given in the event_mask are mapped to the new EQ. \r
- \r
- \r
- \r
- ************************************************************************/\r
-\r
-extern HH_ret_t THH_eventp_setup_mt_eq(/*IN */ THH_eventp_t eventp, \r
- /*IN */ THH_eventp_mtmask_t event_mask, \r
- /*IN */ THH_mlx_eventh_t eventh, \r
- /*IN */ void *priv_context, \r
- /*IN */ MT_size_t max_outs_eqe, \r
- /*OUT*/ THH_eqn_t *eqn_p);\r
-\r
-\r
-/************************************************************************\r
- * Function: \r
- * \r
- Arguments:\r
- eventp \r
- eq -The EQ to replace handler for \r
- eventh -The new handler \r
- priv_context -Private context to be used with handler\r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL \r
- HH_ENORSC -Given EQ is not set up \r
- HH_ERR - internal error\r
- \r
- Description: \r
- Replace the callback function of an EQ previously set up. This may be used \r
- in order to change the handler without loosing events.It retains the EQ and \r
- just replaces the callback function.All EQEs polled after a return from this \r
- function will be repored to the new handler.\r
- \r
- ************************************************************************/\r
-\r
-extern HH_ret_t THH_eventp_replace_handler(/*IN */ THH_eventp_t eventp, \r
- /*IN */ THH_eqn_t eq, \r
- /*IN */ THH_eventp_handler_t eventh, \r
- /*IN */ void *priv_context);\r
-\r
-/************************************************************************\r
- * Function: \r
- * \r
- Arguments:\r
- eventp -The THH_eventp object handle \r
- eqn -The EQ to teardown \r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL -Invalid handles (e.g.no such EQ set up) \r
- HH_ERR - internal error\r
- \r
- Description: \r
- This function tear down an EQ set up by one of the previous functions. Given eqn denes \r
- which EQ to tear down. This teardown includes cleaning of any context relating to \r
- the callback associated with it. \r
- \r
- \r
- ************************************************************************/\r
-\r
-extern HH_ret_t THH_eventp_teardown_eq(/*IN */ THH_eventp_t eventp, \r
- /*IN */ THH_eqn_t eqn );\r
-\r
-\r
-extern HH_ret_t THH_eventp_notify_fatal ( /*IN */ THH_eventp_t eventp,\r
- /*IN */ THH_fatal_err_t fatal_err);\r
-\r
-extern HH_ret_t THH_eventp_handle_fatal ( /*IN */ THH_eventp_t eventp);\r
-#endif /* H_EVENTP_H */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#ifndef H_EVENTP_PRIV_H\r
-#define H_EVENTP_PRIV_H\r
-\r
-\r
-\r
-#include <mosal.h>\r
-#include <eventp.h>\r
-#include <mtl_common.h>\r
-#include <vapi_types.h>\r
-#include <hh.h>\r
-#include <thh.h>\r
-\r
-/*================ macro definitions ===============================================*/\r
-#define EQP_MAX_EQS 32 /* this if for now since we only use 3 EQs and its save us reading two ECR registers */\r
-#define EQP_ECR_USED 1 /* should be changed to 2 when > 32 EQs are used */\r
-#define EQP_CATAS_ERR_EQN 4 /* this is reserved only for catastrophic error notification */\r
-#define EQP_CMD_IF_EQN 1 /* this is reserved only for command interface */\r
-#define EQP_CQ_COMP_EQN 0 /* this is reserved only for CQ completion events */\r
-#define EQP_ASYNCH_EQN 3 /* this is reserved only for asynch events */\r
-#define EQE_HW_OWNER 0x80\r
-#define EQP_MIN_EQ_NUM (EQP_CATAS_ERR_EQN+1) /* make sure we start only after reserved EQs */\r
-#define EQE_SW_OWNER 0x00\r
-#define EQE_OWNER_BYTE_OFFSET 31\r
-\r
-#define EQE_DATA_BYTE_SIZE (MT_BYTE_SIZE(tavorprm_event_queue_entry_st, event_data)) /* in bytes */\r
-#define EQE_OWNER_OFFSET (MT_BIT_OFFSET(tavorprm_event_queue_entry_st, owner) /32 ) /* in DWORDS relay on owner field to be first in DWORD*/\r
-#define EQE_EVENT_TYPE_OFFSET (MT_BIT_OFFSET(tavorprm_event_queue_entry_st, event_type) /32 ) /* in DWORDS relay on owner field to be first in DWORD*/\r
-#define EQE_DATA_OFFSET (MT_BIT_OFFSET(tavorprm_event_queue_entry_st, event_data) /32 ) /* in DWORDS relay on owner field to be first in DWORD*/\r
-#define EQE_DWORD_SIZE (sizeof(struct tavorprm_event_queue_entry_st)/32) /* in DWORDS */\r
-#define EQ_ENTRY_SIZE (sizeof(struct tavorprm_event_queue_entry_st) / 8) /* in bytes */\r
-\r
-\r
-/* Values to put in eq_buff_entry_num to mark entry state. If not one of those - entry is valid */\r
-#define SET_EQ_INIT(eventp,eq_num) (eventp->eq_table[eq_num].res_state= EQP_EQ_INIT)\r
-#define SET_EQ_VALID(eventp,eq_num) (eventp->eq_table[eq_num].res_state= EQP_EQ_VALID)\r
-#define SET_EQ_CLEANUP(eventp,eq_num) (eventp->eq_table[eq_num].res_state= EQP_EQ_CLEANUP)\r
-#define SET_EQ_FREE(eventp,eq_num) (eventp->eq_table[eq_num].res_state= EQP_EQ_FREE)\r
-/* Macros to test if entry is invalid/free */\r
-#define IS_EQ_FREE(eventp,eq_num) (eventp->eq_table[eq_num].res_state == EQP_EQ_FREE)\r
-#define IS_EQ_VALID(eventp,eq_num) (eventp->eq_table[eq_num].res_state == EQP_EQ_VALID)\r
-#define IS_EQ_VALID_P(eq_p) (eq_p->res_state == EQP_EQ_VALID)\r
-\r
-\r
-/*================ type definitions ================================================*/\r
-\r
-typedef enum {\r
- EQP_CQ_COMP_EVENT,\r
- EQP_IB_EVENT,\r
- EQP_CMD_IF_EVENT,\r
- EQP_MLX_EVENT,\r
- EQP_CATAS_ERR_EVENT\r
-}EQ_type_t;\r
-\r
-/* States of the EQ resources (for EQs pool management) */\r
-typedef enum {\r
- EQP_EQ_FREE,\r
- EQP_EQ_INIT,\r
- EQP_EQ_VALID,\r
- EQP_EQ_CLEANUP\r
-}EQ_resource_state_t;\r
-\r
-/* entry saved for each EQ */\r
-typedef struct EQP_eq_entry_st {\r
- EQ_resource_state_t res_state; /* EQ resource (entry) state */\r
-#ifdef EQS_CMD_IN_DDR\r
- MT_phys_addr_t alloc_mem_addr_p; /* need to save the allocated pointer for free at destroy */\r
-#else\r
- MT_virt_addr_t alloc_mem_addr_p; /* need to save the allocated pointer for free at destroy */\r
-#endif \r
- VAPI_size_t alloc_mem_bytes_size;\r
- void* eq_buff;\r
- VAPI_size_t eq_buff_entry_num; /* if ==0 entry is invalid */\r
- VAPI_pd_hndl_t pd;\r
- VAPI_lkey_t mem_lkey;\r
- void *priv_context;\r
- THH_eventp_mtmask_t events_mask;\r
- EQ_type_t eq_type;\r
- THH_eqn_t eqn; /* eq number - needed by DPC */\r
- THH_eventp_handler_t handler;\r
- THH_eventp_t eventp_p;\r
- MOSAL_DPC_t polling_dpc;\r
- volatile u_int32_t dpc_cntr; /* Outstanding DPCs counter (possible values:0,1,2)*/\r
- u_int32_t cons_indx;\r
- MT_virt_addr_t clr_ecr_addr;\r
- u_int32_t clr_ecr_mask;\r
- MT_bool virtual_eq;\r
-#ifdef IMPROVE_EVENT_HANDLING\r
- volatile u_int32_t dpc_lock;\r
-#else\r
- MOSAL_spinlock_t dpc_lock; /* ensure that only one DPC is running - WINDOWS allows \r
- more than one DPC to run at the same time */\r
-#endif \r
- MOSAL_spinlock_t state_lock; /* protect on the eq state - \r
- must be used for every access to this entry */\r
-}EQP_eq_entry_t;\r
-\r
-\r
-/* The main EVENT processor structure */\r
-typedef struct THH_eventp_st {\r
- THH_hob_t hob;\r
- THH_ver_info_t version; \r
- THH_eventp_res_t event_resources; \r
- THH_cmd_t cmd_if; \r
- THH_uar_t kar; \r
- THH_uar_index_t kar_index;\r
- THH_mrwm_t mrwm_internal;\r
- THH_ddrmm_t ddrmm;\r
- EQP_eq_entry_t eq_table[EQP_MAX_EQS]; /* static table of eqs */\r
- MOSAL_mutex_t mtx; /* used internally */\r
- MOSAL_protection_ctx_t ctx_internal;\r
- MOSAL_ISR_t isr_obj;\r
- HH_hca_hndl_t hh_hca_hndl;\r
- volatile MT_virt_addr_t ecr_h_base;\r
- volatile MT_virt_addr_t ecr_l_base;\r
- volatile MT_virt_addr_t clr_ecr_h_base;\r
- volatile MT_virt_addr_t clr_ecr_l_base;\r
- volatile MT_virt_addr_t intr_clr_reg; /* can be the high or the low but not both */\r
- u_int32_t intr_clr_mask;\r
- volatile u_int8_t max_eq_num_used;\r
- volatile MT_bool have_fatal;\r
- volatile THH_fatal_err_t fatal_type; /* need to distingush between master abort and catast error */\r
- MOSAL_DPC_t fatal_error_dpc;\r
-}THH_eventp_internal_t;\r
-\r
-\r
-/*================ external functions ================================================*/\r
-\r
-\r
-\r
-#endif /* H_EVENTP_PRIV_H */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include <mosal.h>\r
-#include <MT23108.h>\r
-#include <mcgm.h>\r
-#include <cmdif.h>\r
-#include <epool.h>\r
-#include <thh_hob.h>\r
-#include <vip_hashp.h>\r
-#include <vapi_common.h>\r
-\r
-/*================ macro definitions ===============================================*/\r
-\r
-//#define EPOOL_ENTRY_SIZE 8 /* the minimum needed for the Epool */\r
-\r
-/*================ type definitions ================================================*/\r
-typedef VIP_hashp_p_t mcg_status_hash_t;\r
-typedef enum\r
-{\r
- MGHT =0, AMGM=1\r
-} mcg_tbl_kind_t;\r
-typedef enum\r
-{\r
- INSERT =0, REMOVE=1\r
-} mcg_op_t;\r
-\r
-\r
-\r
-/* The main MCG-manager structure */\r
-typedef struct THH_mcgm_st\r
-{\r
- THH_hob_t hob; \r
- THH_ver_info_t version;\r
- VAPI_size_t mght_total_entries;\r
- VAPI_size_t mght_hash_bins; /* actually, it requires 16 bit!! */\r
- u_int16_t max_qp_per_mcg; \r
- MOSAL_mutex_t mtx; /* used internally */\r
- THH_cmd_t cmd_if_h;\r
- EPool_t free_list; /* the free list of the non-hash part of the MCG table */\r
- mcg_status_hash_t my_hash;\r
- //u_int32_t amgm_idx;\r
- //u_int32_t mght_idx;\r
-}THH_mcgm_props_t;\r
-\r
-/* multicast groups status hash tabel*/\r
-struct mcg_status_entry\r
-{\r
- IB_gid_t mgid; /* Group's GID */\r
- u_int16_t num_valid_qps;\r
- u_int32_t idx; //absolute idx !!! (AMGM + MGHT)\r
- u_int32_t prev_idx; //absolute idx !!! (AMGM + MGHT)\r
-};\r
-\r
-/*================ global variables definitions ====================================*/\r
-static const EPool_meta_t free_list_meta =\r
-{\r
- 2*sizeof(unsigned long), \r
- 0, /* unsigned long 'prev' index */\r
- sizeof(unsigned long) \r
-};\r
-\r
-\r
-/*================ static functions prototypes =====================================*/\r
-\r
-static HH_ret_t THMCG_get_status_entry(IB_gid_t gid,\r
- mcg_status_hash_t* hash_p,\r
- mcg_status_entry_t* mcg_p);\r
-static HH_ret_t THMCG_update_status_entry(mcg_status_hash_t* hash_p,mcg_status_entry_t* entry_p,MT_bool new_e);\r
-static HH_ret_t THMCG_remove_status_entry(mcg_status_hash_t* hash_p,mcg_status_entry_t* entry_p);\r
-\r
-static inline HH_ret_t read_alloc_mgm(THH_mcgm_t mcgm, THH_mcg_entry_t* entry,u_int32_t idx);\r
-\r
-static HH_ret_t THMCG_reduce_MGHT(THH_mcgm_t mcgm, u_int32_t idx,THH_mcg_entry_t* fw_tmp_entry);\r
-\r
-static HH_ret_t THMCG_find_last_index(THH_mcgm_t mcgm, THH_mcg_hash_t fw_hash_val,\r
- u_int32_t* last, THH_mcg_entry_t* last_entry);\r
-static inline void print_fw_entry(THH_mcg_entry_t* entry);\r
-static inline void print_status_entry(mcg_status_entry_t* my_entry);\r
-\r
-/*================ global functions definitions ====================================*/\r
-\r
-/************************************************************************\r
- * Function: THH_mcgm_create\r
- * \r
- Arguments:\r
- hob - THH_hob this object is included in \r
- mght_total_entries - Number of entries in the MGHT \r
- mght_hash_bins - Number of bins in the hash table \r
- max_qp_per_mcg - Max number of QPs per Multicast Group \r
- mcgm_p - Allocated THH_mcgm_t object \r
- Returns:\r
- HH_OK \r
- HH_EINVAL \r
- HH_EAGAIN\r
- \r
- Description: Create THH_mcgm_t instance. \r
- \r
- implementation saving the values:\r
- 1.Total number of entries in the MGHT. \r
- 2.Size of the hash table part (i.e.number of bins). \r
- 3.THH_cmd object to use (taken from the THH_hob using THH_hob_get_cmd_if()). \r
- 4.Version information (taken using THH_hob_get_ver_info(). \r
- 5.Free MGHT entries pool management data structure.\r
-\r
-\r
- ************************************************************************/\r
-\r
-extern HH_ret_t THH_mcgm_create(/*IN */ THH_hob_t hob, \r
- /*IN */ VAPI_size_t mght_total_entries, \r
- /*IN */ VAPI_size_t mght_hash_bins, \r
- /*IN */ u_int16_t max_qp_per_mcg, \r
- /*OUT*/ THH_mcgm_t *mcgm_p )\r
-{\r
- THH_mcgm_t new_mcgm_p = NULL;\r
- unsigned long amgm_table_size;\r
- VIP_common_ret_t ret=VIP_OK;\r
- HH_ret_t hh_ret = HH_OK;\r
-\r
- FUNC_IN;\r
-\r
-\r
- MTL_DEBUG1("%s: starting...\n", __func__);\r
- /* allocation of object structure */\r
- new_mcgm_p = (THH_mcgm_t)MALLOC(sizeof(THH_mcgm_props_t));\r
- if (!new_mcgm_p)\r
- {\r
- MTL_ERROR4("%s: Cannot allocate MGM object.\n", __func__);\r
- MT_RETURN(HH_EAGAIN);\r
- }\r
- MTL_DEBUG1("after allocating new_mcgm_p\n"); \r
- memset(new_mcgm_p,0,sizeof(THH_mcgm_props_t));\r
-\r
- //check arguments\r
- MTL_DEBUG1("hash bins:"U64_FMT", total entries:"U64_FMT"\n",mght_hash_bins,mght_total_entries);\r
- if ((mght_hash_bins > mght_total_entries) || (mght_total_entries <= 0) || (mght_hash_bins <= 0))\r
- {\r
-\r
- MTL_ERROR4("%s: bad initial values!\n", __func__);\r
- FREE(new_mcgm_p);\r
- MT_RETURN(HH_EINVAL);\r
- }\r
-\r
-\r
- MOSAL_mutex_init(&new_mcgm_p->mtx);\r
- \r
- amgm_table_size = (unsigned long)(mght_total_entries - mght_hash_bins);\r
- MTL_DEBUG1("total: "U64_FMT", hashbins: "U64_FMT" \n",\r
- mght_total_entries,mght_hash_bins);\r
-\r
- new_mcgm_p->free_list.entries = (void*)(MT_ulong_ptr_t)VMALLOC(sizeof(unsigned long)* 2 *amgm_table_size); \r
- if (!new_mcgm_p->free_list.entries)\r
- {\r
- MTL_ERROR4("%s: Cannot allocate AMGM table.\n", __func__);\r
- FREE(new_mcgm_p);\r
- MT_RETURN(HH_EAGAIN);\r
- }\r
- MTL_DEBUG1("after allocating free_list.entries\n" ); \r
-\r
- memset(new_mcgm_p->free_list.entries,0,sizeof(unsigned long)* 2 *amgm_table_size);\r
- /* init the epool */\r
- new_mcgm_p->free_list.size = amgm_table_size;\r
- new_mcgm_p->free_list.meta = &free_list_meta;\r
- epool_init(&(new_mcgm_p->free_list));\r
-\r
-\r
-\r
- /*filling mcgm structure */\r
- new_mcgm_p->hob = hob;\r
- new_mcgm_p->mght_total_entries = mght_total_entries;\r
- new_mcgm_p->mght_hash_bins = mght_hash_bins;\r
- new_mcgm_p->max_qp_per_mcg = max_qp_per_mcg;\r
- MTL_DEBUG1("max qp per mgm entry: %d\n",new_mcgm_p->max_qp_per_mcg);\r
-\r
- hh_ret = THH_hob_get_cmd_if (hob, &new_mcgm_p->cmd_if_h);\r
- if (hh_ret != HH_OK) {\r
- MTL_ERROR4("%s: Cannot get cmd_if object handle.\n", __func__);\r
- goto clean;\r
- }\r
- hh_ret = THH_hob_get_ver_info(hob, &new_mcgm_p->version);\r
- if (hh_ret != HH_OK) {\r
- MTL_ERROR4("%s: Cannot get version.\n", __func__);\r
- goto clean;\r
- }\r
- /*init local hash table */\r
- ret = VIP_hashp_create_maxsize((u_int32_t)mght_total_entries,(u_int32_t)mght_total_entries,&(new_mcgm_p->my_hash));\r
- if (ret != VIP_OK)\r
- {\r
- MTL_ERROR4("%s: Cannot allocate multicast status hash.\n", __func__);\r
- hh_ret = HH_EAGAIN;\r
- goto clean;\r
- }\r
- MTL_DEBUG1("after creating hash table\n"); \r
- VIP_hashp_may_grow(new_mcgm_p->my_hash,FALSE); /* fix hash table size */\r
- //new_mcgm_p->amgm_idx = 0;\r
- //new_mcgm_p->mght_idx = 0;\r
-\r
- /* succeeded to create object - return params: */\r
- *mcgm_p = new_mcgm_p;\r
- \r
- MT_RETURN(HH_OK);\r
-\r
- clean:\r
- VFREE(new_mcgm_p->free_list.entries);\r
- FREE(new_mcgm_p);\r
- MT_RETURN(hh_ret);\r
-}\r
-\r
-/************************************************************************\r
- * Function: THMCG_remove_status_entry\r
- * \r
- Arguments:\r
- hash_p - pointer to status hash \r
- entry_p - pointer to entry that should be removed \r
- \r
- Returns:\r
- HH_OK \r
- HH_ERR - an error has occured\r
- \r
- Description: \r
- removes enty from status hash \r
- \r
- ************************************************************************/\r
-\r
-static void THMCG_destroy_remove_status_entry( VIP_hash_key_t key,VIP_hashp_value_t hash_val, void * priv_data)\r
-{\r
-\r
-\r
- FUNC_IN;\r
-\r
- if (hash_val != 0) {\r
- FREE(hash_val);\r
- }\r
- return;\r
-}\r
-/************************************************************************\r
- * Function: THH_mcgm_destroy\r
- * \r
- Arguments:\r
- mcgm - THH_mcgm to destroy \r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL \r
- \r
- Description: \r
- Free THH_mcgm context resources. \r
- ************************************************************************/\r
-\r
-extern HH_ret_t THH_mcgm_destroy( /*IN */ THH_mcgm_t mcgm )\r
-{\r
- VIP_common_ret_t ret = VIP_OK;\r
-\r
- FUNC_IN;\r
-\r
- THMCG_CHECK_NULL(mcgm,done);\r
- \r
- MOSAL_mutex_acq_ui(&mcgm->mtx);\r
- epool_cleanup(&(mcgm->free_list));\r
-\r
- /* first free the epool */\r
- VFREE(mcgm->free_list.entries);\r
-\r
- /*destroy my_hash. Need to de-allocate 'malloced' entries */\r
- ret = VIP_hashp_destroy(mcgm->my_hash,&THMCG_destroy_remove_status_entry,0);\r
- if (ret != VIP_OK)\r
- {\r
- MTL_ERROR4("%s: Cannot destroy multicast status hash.\n", __func__);\r
- }\r
-\r
-done: \r
- MOSAL_mutex_rel(&mcgm->mtx);\r
- MOSAL_mutex_free(&mcgm->mtx);\r
- FREE(mcgm);\r
- MT_RETURN(ret);\r
-\r
-}\r
-\r
-/************************************************************************\r
- Function: THH_mcgm_attach_qp\r
- \r
- Arguments:\r
- mcgm \r
- qpn -QP number of QP to attach \r
- mgid -GID of a multicast group to attach to\r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL \r
- HH_EAGAIN - No more MGHT entries. \r
- HH_2BIG_MCG_SIZE - Number of QPs attached to multicast groups exceeded") \\r
- HH_ERR - an error has ocuured\r
- \r
- Description: \r
- Attach given QP to multicast with given DGID. Add new group if this is the first QP in MCG.\r
- ************************************************************************/\r
-extern HH_ret_t THH_mcgm_attach_qp(/*IN */ THH_mcgm_t mcgm, \r
- /*IN */ IB_wqpn_t qpn, \r
- /*IN */ IB_gid_t mgid )\r
-{\r
- THH_mcg_entry_t fw_tmp_entry;\r
- THH_cmd_status_t c_status;\r
- mcg_status_entry_t my_entry;\r
- HH_ret_t ret,s_ret = HH_OK;\r
- THH_mcg_hash_t fw_hash_val;\r
- u_int32_t new_idx,i;\r
- MT_bool new_e = TRUE;\r
- MT_bool is_empty=TRUE;\r
- \r
- FUNC_IN;\r
-\r
- ret=HH_EINVAL;\r
- THMCG_CHECK_NULL(mcgm,fin);\r
- ret=HH_OK;\r
-\r
- MOSAL_mutex_acq_ui(&mcgm->mtx);\r
-\r
- MTL_DEBUG1("got gid:%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.\n",mgid[0],mgid[1],\r
- mgid[2],mgid[3],mgid[4],mgid[5],mgid[6],mgid[7],\r
- mgid[8],mgid[9],mgid[10],mgid[11],mgid[12],mgid[13],\r
- mgid[14],mgid[15]); \r
-\r
- memset(&my_entry,0,sizeof(mcg_status_entry_t));\r
- s_ret = THMCG_get_status_entry(mgid,&(mcgm->my_hash),&my_entry);\r
- switch (s_ret) {\r
- \r
- case HH_NO_MCG:\r
- MTL_DEBUG1(MT_FLFMT("gid doesn't have a multicast group yet \n"));\r
- \r
- //get hash idx from fw\r
- c_status = THH_cmd_MGID_HASH(mcgm->cmd_if_h,mgid,&fw_hash_val);\r
- ret= HH_ERR;\r
- THMCG_CHECK_CMDIF_ERR(c_status,fin," THH_cmd_HASH failed\n");\r
- ret= HH_OK;\r
- \r
- MTL_DEBUG1("returned hash val:0x%x \n",fw_hash_val);\r
- if (fw_hash_val >= mcgm->mght_hash_bins)\r
- {\r
- MTL_ERROR1("ERROR:got invalid hash idx for new gid\n");\r
- ret=HH_ERR;\r
- goto fin;\r
- }\r
- \r
- //read the entry where the new gid supposed to be- is it empty?\r
- ret= read_alloc_mgm(mcgm,&fw_tmp_entry,fw_hash_val);\r
- if (ret!= HH_OK) {\r
- goto fin;\r
- }\r
- \r
- for (i=0; i< 16; i++) {\r
- if (fw_tmp_entry.mgid[i] != 0) {\r
- is_empty= FALSE;\r
- break;\r
- }\r
- }\r
- if (!is_empty) /* if the hash isn't empty*/\r
- { \r
- /* put the gid in amgm */\r
- u_int32_t last=0;\r
- //mcgm->amgm_idx++; \r
- MTL_DEBUG1("original hash idx is taken. before find last gid\n");\r
- if (fw_tmp_entry.next_gid_index > 0) {\r
-/*** warning C4242: 'function' : conversion from 'u_int32_t' to 'THH_mcg_hash_t', possible loss of data ***/\r
- ret=THMCG_find_last_index(mcgm,(THH_mcg_hash_t)fw_tmp_entry.next_gid_index,&last,&fw_tmp_entry);\r
- THMCG_CHECK_HH_ERR(ret,clean,"THMCG_find_last_index failed");\r
- }\r
- \r
- //get free idx\r
- new_idx = (u_int32_t)epool_alloc(&mcgm->free_list);\r
- if (new_idx == EPOOL_NULL)\r
- {\r
- ret = HH_EAGAIN;\r
- THMCG_CHECK_HH_ERR(ret,clean,"THH_mcgm_attach_qp: $$ No free entries in MCGM table.\n");\r
- }\r
- \r
- MTL_DEBUG1("after allocating new idx: 0x%x in AMGM\n",new_idx);\r
- new_idx+=(u_int32_t)mcgm->mght_hash_bins; //abs idx in MGHT+AMGM\r
- \r
- //update the last entry\r
- fw_tmp_entry.next_gid_index = new_idx;\r
- c_status = THH_cmd_WRITE_MGM(mcgm->cmd_if_h,last,mcgm->max_qp_per_mcg,&fw_tmp_entry);\r
- ret= HH_ERR;\r
- THMCG_CHECK_CMDIF_ERR(c_status,clean," THH_cmd_WRITE_MGM failed\n");\r
- ret= HH_OK;\r
- my_entry.prev_idx = last;\r
- \r
- }else{\r
- //mcgm->mght_idx++; \r
- new_idx = (u_int32_t)fw_hash_val;\r
- my_entry.prev_idx = 0xffffffff;\r
- MTL_DEBUG1("using fw hash idx \n");\r
- }\r
-\r
- //either in MGHT or AMGM - insert new GID entry\r
- my_entry.idx = new_idx;\r
- my_entry.num_valid_qps = 1;\r
- memcpy(my_entry.mgid,mgid,sizeof(IB_gid_t)); \r
- \r
- fw_tmp_entry.next_gid_index=0;\r
- fw_tmp_entry.valid_qps=0;\r
- memset(fw_tmp_entry.qps, 0, sizeof(IB_wqpn_t) * mcgm->max_qp_per_mcg); \r
- memcpy(fw_tmp_entry.mgid,mgid,sizeof(IB_gid_t)); \r
- \r
- break;\r
- \r
- case HH_OK:\r
- MTL_DEBUG1("$$$ gid already exists in hash table\n");\r
- \r
- //read the entry\r
- ret=read_alloc_mgm(mcgm,&fw_tmp_entry,my_entry.idx);\r
- if (ret!= HH_OK) {\r
- goto fin;\r
- }\r
- if (fw_tmp_entry.valid_qps != my_entry.num_valid_qps) {\r
- MTL_ERROR1(MT_FLFMT("mismatch hw (%d)/sw (%d) MCG entry \n"),fw_tmp_entry.valid_qps,my_entry.num_valid_qps);\r
- ret= HH_ERR;\r
- goto clean;\r
- }\r
- \r
- //check if the qp already exists in the gid\r
- for (i=0; i<fw_tmp_entry.valid_qps; i++)\r
- {\r
- if (fw_tmp_entry.qps[i] == qpn)\r
- {\r
- MTL_DEBUG1("qpn already exists in the requested gid\n");\r
- ret=HH_OK; \r
- goto clean;\r
- }\r
- }\r
- \r
- if (my_entry.num_valid_qps == mcgm->max_qp_per_mcg){\r
- ret=HH_2BIG_MCG_SIZE;\r
- MTL_ERROR1("exceeded mcgroup's max qps amount\n");\r
- goto clean;\r
- }\r
- \r
- my_entry.num_valid_qps ++;\r
- new_e = FALSE;\r
- break;\r
- \r
- default: MTL_ERROR1(MT_FLFMT("MCG_get_status_entry failed")); \r
- goto fin; \r
- }\r
- fw_tmp_entry.qps[fw_tmp_entry.valid_qps] = qpn;\r
- fw_tmp_entry.valid_qps ++;\r
- \r
- MTL_DEBUG1("writing new mcg entry to idx: 0x%x\n",my_entry.idx);\r
- c_status = THH_cmd_WRITE_MGM(mcgm->cmd_if_h,my_entry.idx,mcgm->max_qp_per_mcg,&fw_tmp_entry);\r
- ret=HH_ERR;\r
- THMCG_CHECK_CMDIF_ERR(c_status,clean," THH_cmd_WRITE_MGM failed\n");\r
- ret=HH_OK;\r
-\r
- THMCG_update_status_entry(&mcgm->my_hash,&my_entry,new_e);\r
-\r
- //MTL_ERROR1("so far: amgm:%d mght:%d \n",mcgm->amgm_idx,mcgm->mght_idx);\r
- \r
-clean: \r
- if (fw_tmp_entry.qps) {\r
- FREE(fw_tmp_entry.qps);\r
- }\r
-fin: \r
- MOSAL_mutex_rel(&mcgm->mtx);\r
- MT_RETURN(ret);\r
-}\r
-\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_mcgm_detach_qp\r
- * \r
- Arguments:\r
- mcgm \r
- qpn - QP number of QP to attach \r
- mgid - GID of a multicast group to attach to \r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL - No such multicast group or given QP is not in given group \r
- HH_ERR - an error has occured\r
- \r
- Description: \r
- Detach given QP from multicast group with given GID. \r
- \r
- ************************************************************************/\r
-\r
-extern HH_ret_t THH_mcgm_detach_qp(/*IN */ THH_mcgm_t mcgm, \r
- /*IN */ IB_wqpn_t qpn, \r
- /*IN */ IB_gid_t mgid)\r
-{\r
- THH_mcg_entry_t fw_tmp_entry;\r
- THH_cmd_status_t c_status;\r
- mcg_status_entry_t my_entry;\r
- HH_ret_t ret = HH_OK;\r
- MT_bool qp_is_in = FALSE;\r
- u_int32_t i;\r
-\r
- FUNC_IN;\r
-\r
- ret=HH_ERR;\r
- THMCG_CHECK_NULL(mcgm,fin);\r
- ret=HH_OK;\r
-\r
- MOSAL_mutex_acq_ui(&mcgm->mtx);\r
-\r
- MTL_DEBUG1("got gid:%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.\n",mgid[0],mgid[1],\r
- mgid[2],mgid[3],mgid[4],mgid[5],mgid[6],mgid[7],\r
- mgid[8],mgid[9],mgid[10],mgid[11],mgid[12],mgid[13],\r
- mgid[14],mgid[15]); \r
- MTL_DEBUG1("got qpn: 0x%x \n",qpn);\r
-\r
- ret = THMCG_get_status_entry(mgid,&(mcgm->my_hash),&my_entry);\r
- if (ret != HH_OK) {\r
- if (ret == HH_NO_MCG) {\r
- ret= HH_EINVAL_MCG_GID;\r
- MTL_ERROR1("this gid doesn't have a multicast group\n");\r
- }else {\r
- MTL_ERROR1("MCG_get_status_entry failed");\r
- }\r
- goto fin;\r
- }\r
- print_status_entry(&my_entry);\r
-\r
- //read the entry\r
- MTL_DEBUG1("reading from idx: 0x%x \n",my_entry.idx);\r
- \r
- ret=read_alloc_mgm(mcgm,&fw_tmp_entry,my_entry.idx);\r
- if (ret!= HH_OK) {\r
- goto fin;\r
- }\r
- \r
- for (i=0; i< fw_tmp_entry.valid_qps; i++)\r
- {\r
- if (fw_tmp_entry.qps[i] == qpn)\r
- {\r
- qp_is_in = TRUE;\r
- break;\r
- }\r
- }\r
- //qp is not in group\r
- if (qp_is_in == FALSE)\r
- {\r
- MTL_ERROR1("qp doesn't belong to gid's multicast group\n");\r
- ret=HH_EINVAL_QP_NUM;\r
- goto clean;\r
- }\r
-\r
- MTL_DEBUG1("MCGM detach qp: qp & gid are valid \n");\r
- \r
- if (fw_tmp_entry.valid_qps > 1)\r
- {\r
- MTL_DEBUG1("no need to remove gid's mcg \n");\r
- for (i=0; i< fw_tmp_entry.valid_qps; i++)\r
- {\r
- //assuming qp exists max once in mcg group\r
- if (fw_tmp_entry.qps[i] == qpn)\r
- fw_tmp_entry.qps[i]=fw_tmp_entry.qps[fw_tmp_entry.valid_qps-1];\r
- }\r
- fw_tmp_entry.valid_qps--;\r
- \r
- c_status = THH_cmd_WRITE_MGM(mcgm->cmd_if_h,my_entry.idx,mcgm->max_qp_per_mcg,&fw_tmp_entry);\r
- ret=HH_ERR;\r
- THMCG_CHECK_CMDIF_ERR(c_status,clean," THH_cmd_WRITE_MGM failed\n");\r
- ret=HH_OK;\r
-\r
- //update my hash\r
- my_entry.num_valid_qps--;\r
- ret=THMCG_update_status_entry(&mcgm->my_hash,&my_entry,FALSE);\r
- THMCG_CHECK_HH_ERR(ret,clean," THMCG_update_status_entry failed\n");\r
- }else {\r
- MTL_DEBUG1("no more qp's - removing MGM entry\n");\r
- \r
- //MGHT\r
- if (my_entry.idx < mcgm->mght_hash_bins)\r
- {\r
- MTL_DEBUG1("reduced entry is in MGHT \n");\r
- \r
- if (fw_tmp_entry.next_gid_index > 0) {\r
- ret=THMCG_reduce_MGHT(mcgm,my_entry.idx/*the entry to remove*/,&fw_tmp_entry);\r
- THMCG_CHECK_HH_ERR(ret,clean," THMCG_reduce_MGHT failed\n");\r
- //mcgm->amgm_idx--; \r
- }else{\r
- /* write nullified entry */\r
- memset(fw_tmp_entry.mgid,0,sizeof(IB_gid_t)); \r
- c_status = THH_cmd_WRITE_MGM(mcgm->cmd_if_h,my_entry.idx,mcgm->max_qp_per_mcg,&fw_tmp_entry);\r
- ret=HH_ERR;\r
- THMCG_CHECK_CMDIF_ERR(c_status,clean," THH_cmd_WRITE_MGM failed\n");\r
- ret=HH_OK;\r
- //mcgm->mght_idx--; \r
- }\r
- }\r
- //AMGM\r
- else\r
- {\r
- THH_mcg_entry_t fw_prev_entry;\r
- u_int32_t next_idx = fw_tmp_entry.next_gid_index;\r
-\r
- MTL_DEBUG1("reduced entry is in AMGM \n");\r
- //mcgm->amgm_idx--; \r
- /*1.HW: update the prev */\r
- ret=read_alloc_mgm(mcgm,&fw_prev_entry,my_entry.prev_idx);\r
- if (ret!= HH_OK) {\r
- goto clean;\r
- }\r
- \r
- fw_prev_entry.next_gid_index = fw_tmp_entry.next_gid_index;\r
-\r
- MTL_DEBUG1("writing updated prev to AMGM \n");\r
- c_status = THH_cmd_WRITE_MGM(mcgm->cmd_if_h,my_entry.prev_idx,mcgm->max_qp_per_mcg,&fw_prev_entry);\r
- FREE(fw_prev_entry.qps);\r
- \r
- ret=HH_ERR;\r
- THMCG_CHECK_CMDIF_ERR(c_status,clean," THH_cmd_WRITE_MGM failed\n");\r
- ret=HH_OK;\r
- \r
-\r
- /* 2. read the gid of the next entry (if there's any)*/ \r
- if (next_idx> 0) {\r
- mcg_status_entry_t next_entry;\r
-\r
- c_status = THH_cmd_READ_MGM(mcgm->cmd_if_h,next_idx,mcgm->max_qp_per_mcg,&fw_tmp_entry);\r
- ret=HH_ERR;\r
- THMCG_CHECK_CMDIF_ERR(c_status,clean," THH_cmd_WRITE_MCG failed\n");\r
- ret=HH_OK;\r
- \r
- \r
- /* 2.1 update the prev field of the next in my DB*/\r
- ret=THMCG_get_status_entry(fw_tmp_entry.mgid,&mcgm->my_hash,&next_entry);\r
- THMCG_CHECK_HH_ERR(ret,clean," THMCG_get_status_entry failed\n"); \r
- \r
- next_entry.prev_idx = my_entry.prev_idx;\r
- \r
- ret=THMCG_update_status_entry(&mcgm->my_hash,&next_entry,FALSE);\r
- THMCG_CHECK_HH_ERR(ret,clean," THMCG_get_status_entry failed\n"); \r
- }\r
- \r
- epool_free(&mcgm->free_list,(unsigned long)((VAPI_size_t)my_entry.idx - mcgm->mght_hash_bins));\r
- \r
- }/* else - AMGM */\r
- \r
- /* remove the entry from my table */\r
- ret=THMCG_remove_status_entry(&mcgm->my_hash,&my_entry);\r
- THMCG_CHECK_HH_ERR(ret,clean," THMCG_remove_status_entry failed\n");\r
- \r
- }\r
- \r
- clean:\r
- if (fw_tmp_entry.qps) {\r
- FREE(fw_tmp_entry.qps);\r
- }\r
- fin:\r
- MOSAL_mutex_rel(&mcgm->mtx);\r
- MT_RETURN(ret);\r
-}\r
-\r
-\r
-\r
-/***** static definitions **********************************/\r
-\r
-/************************************************************************\r
- * Function: THMCG_find_last_index\r
- * \r
- Arguments:\r
- mcgm\r
- fw_hash_val - the MGHT idx to start with\r
- last- pointer to last index in chain\r
- last_entry - pointer to last fw entry that will be filled \r
- Returns:\r
- HH_OK \r
- HH_ERR - an error has occured\r
- \r
- Description: \r
- finds the last fw entry in a chain of the sam hash key\r
- ************************************************************************/\r
-static HH_ret_t THMCG_find_last_index(THH_mcgm_t mcgm, THH_mcg_hash_t start,\r
- u_int32_t* last, THH_mcg_entry_t* last_entry)\r
-{\r
-\r
- THH_cmd_status_t c_status;\r
- HH_ret_t ret = HH_EAGAIN;\r
- u_int32_t cur_idx=(u_int32_t)start;\r
-\r
- FUNC_IN;\r
-\r
- \r
- while (1)\r
- {\r
- MTL_DEBUG1("MCGM find last idx: reading from idx: 0x%x \n",cur_idx);\r
- memset(last_entry->qps, 0, sizeof(IB_wqpn_t) * mcgm->max_qp_per_mcg); \r
- c_status = THH_cmd_READ_MGM(mcgm->cmd_if_h,cur_idx,mcgm->max_qp_per_mcg,last_entry);\r
- ret=HH_ERR;\r
- THMCG_CHECK_CMDIF_ERR(c_status,fin," THH_cmd_READ_MGM failed\n");\r
- ret=HH_OK;\r
- print_fw_entry(last_entry);\r
- if (last_entry->next_gid_index==0) {\r
- *last=cur_idx;\r
- break;\r
- }\r
- cur_idx = last_entry->next_gid_index;\r
- }\r
- \r
- fin:\r
- MT_RETURN(ret); \r
-}\r
-\r
-/************************************************************************\r
- * Function: THMCG_update_status_entry\r
- * \r
- Arguments:\r
- hash_p - status hash table\r
- mcg_p - the status entry to be updated\r
- new_e - is it a new entry (add) or not (update)\r
- Returns:\r
- HH_OK \r
- HH_ERR - an error has occured\r
- \r
- Description: \r
- updates or addes status entry\r
- ************************************************************************/\r
-\r
-static HH_ret_t THMCG_update_status_entry(mcg_status_hash_t* hash_p,mcg_status_entry_t* entry_p,MT_bool new_e)\r
-{\r
-\r
- u_int32_t hash_key;\r
- VIP_common_ret_t hash_ret;\r
- VIP_hashp_value_t hash_val;\r
- mcg_status_entry_t* mgm_p;\r
- \r
- FUNC_IN;\r
-\r
- hash_key = GID_2_HASH_KEY(entry_p->mgid);\r
-\r
- if (!new_e)\r
- {\r
- hash_ret = VIP_hashp_erase(*hash_p, hash_key, &hash_val);\r
- if (hash_ret != VIP_OK)\r
- {\r
- MTL_ERROR1("failed VIP_hashp_erase: got %s \n",VAPI_strerror_sym(hash_ret));\r
- return HH_EINVAL;\r
- }\r
- mgm_p = (mcg_status_entry_t*)hash_val;\r
- }else {\r
- mgm_p = (mcg_status_entry_t*)MALLOC(sizeof(mcg_status_entry_t));\r
- if (mgm_p == NULL)\r
- {\r
- MT_RETURN(HH_EAGAIN);\r
- }\r
- }\r
- print_status_entry(entry_p);\r
-\r
- mgm_p->idx = entry_p->idx;\r
- mgm_p->prev_idx = entry_p->prev_idx;\r
- mgm_p->num_valid_qps = entry_p->num_valid_qps;\r
- memcpy(mgm_p->mgid,entry_p->mgid,sizeof(IB_gid_t)); \r
-\r
- hash_ret = VIP_hashp_insert(*hash_p, hash_key, (VIP_hashp_value_t)mgm_p);\r
- if (hash_ret != VIP_OK)\r
- {\r
- MTL_ERROR1(MT_FLFMT("failed VIP_hashp_insert\n"));\r
- if (new_e) FREE(mgm_p);\r
- return HH_ERR;\r
- }\r
-\r
-////////////////\r
-#if 0\r
- /* try to find mcg of this mcg */\r
- hash_ret = VIP_hashp_find(*hash_p, hash_key, &hash_val);\r
- if (hash_ret != VIP_OK)\r
- {\r
- MTL_ERROR1("failed VIP_hashp_insert\n");\r
- return HH_ERR;\r
- }\r
- print_status_entry((mcg_status_entry_t*)hash_val);\r
-#endif\r
-\r
-////////////////\r
-\r
-\r
- MT_RETURN( HH_OK);\r
-}\r
-\r
-/************************************************************************\r
- * Function: THMCG_get_status_entry\r
- * \r
- Arguments:\r
- gid - the status entry gid\r
- hash_p - status hash table\r
- mcg_p - the status entry that will be filled \r
- Returns:\r
- HH_OK \r
- HH_ERR - an error has occured\r
- \r
- Description: \r
- returns the entry which matches the gid \r
- ************************************************************************/\r
-\r
-static HH_ret_t THMCG_get_status_entry(IB_gid_t gid,\r
- mcg_status_hash_t* hash_p,\r
- mcg_status_entry_t* mcg_p)\r
-{\r
- VIP_common_ret_t v_ret = VIP_OK;\r
- HH_ret_t ret = HH_OK;\r
- u_int32_t hash_key;\r
- VIP_hashp_value_t hash_val;\r
-\r
- FUNC_IN;\r
-\r
- hash_key = GID_2_HASH_KEY(gid);\r
-\r
- MTL_DEBUG2("%s: GID key is: %u\n", __func__, hash_key);\r
-\r
- /* try to find mcg of this mcg */\r
- v_ret = VIP_hashp_find(*hash_p, hash_key, &hash_val);\r
-\r
- switch (v_ret)\r
- {\r
- case VIP_OK:\r
- MTL_DEBUG1("returning HH OK\n"); \r
- *mcg_p = *((mcg_status_entry_t*)hash_val);\r
- break;\r
- \r
- case VIP_EINVAL_HNDL:\r
- MTL_DEBUG1("returning HH NO MCG\n"); \r
- ret= HH_NO_MCG;\r
- break;\r
- \r
- default:\r
- ret=HH_EAGAIN;\r
- }\r
- \r
- return ret;\r
-}\r
-\r
-/************************************************************************\r
- * Function: THMCG_reduce_MGHT\r
- * \r
- Arguments:\r
- mcgm\r
- cur_idx - entry idx in FW table \r
- fw_entry_p - pointer to fw_hash_entry that reduced from MGHT \r
- \r
- Returns:\r
- HH_OK \r
- HH_ERR - an error has occured\r
- \r
- Description: \r
- removes entry from MGHT, moves its succ to the entry's place in MGHT and updates status hash \r
- \r
- ************************************************************************/\r
-\r
-static HH_ret_t THMCG_reduce_MGHT(THH_mcgm_t mcgm, u_int32_t cur_idx, THH_mcg_entry_t* fw_entry_p)\r
-{\r
- THH_mcg_entry_t fw_next_entry;\r
- THH_cmd_status_t c_status;\r
- mcg_status_entry_t my_entry;\r
- HH_ret_t ret = HH_OK;\r
- \r
- FUNC_IN;\r
-\r
- //read the next entry & write it instead the removed one\r
- ret=read_alloc_mgm(mcgm,&fw_next_entry,fw_entry_p->next_gid_index);\r
- if (ret!= HH_OK) {\r
- goto fin;\r
- }\r
-\r
- c_status = THH_cmd_WRITE_MGM(mcgm->cmd_if_h,cur_idx,mcgm->max_qp_per_mcg,&fw_next_entry);\r
- FREE(fw_next_entry.qps);\r
- \r
- ret=HH_ERR;\r
- THMCG_CHECK_CMDIF_ERR(c_status,fin," THH_cmd_WRITE_MGM failed\n");\r
- ret=HH_OK;\r
-\r
- //free the next idx in epool\r
- epool_free(&mcgm->free_list,(unsigned long)((VAPI_size_t)fw_entry_p->next_gid_index - mcgm->mght_hash_bins));\r
-\r
- //update the next's entry\r
- memcpy(my_entry.mgid,fw_next_entry.mgid,sizeof(IB_gid_t)); \r
- my_entry.idx = cur_idx;\r
-/*** warning C4242: '=' : conversion from 'u_int32_t' to 'u_int16_t', possible loss of data ***/\r
- my_entry.num_valid_qps = (u_int16_t)fw_next_entry.valid_qps;\r
- my_entry.prev_idx = 0xffffffff;\r
- ret=THMCG_update_status_entry(&mcgm->my_hash,&my_entry,FALSE);\r
- THMCG_CHECK_HH_ERR(ret,fin," THMCG_update_status_entry failed\n");\r
- print_status_entry(&my_entry);\r
- \r
-\r
- fin:\r
- MT_RETURN(ret);\r
-}\r
-\r
-/************************************************************************\r
- * Function: THMCG_remove_status_entry\r
- * \r
- Arguments:\r
- hash_p - pointer to status hash \r
- entry_p - pointer to entry that should be removed \r
- \r
- Returns:\r
- HH_OK \r
- HH_ERR - an error has occured\r
- \r
- Description: \r
- removes enty from status hash \r
- \r
- ************************************************************************/\r
-\r
-static HH_ret_t THMCG_remove_status_entry(mcg_status_hash_t* hash_p,mcg_status_entry_t* entry_p)\r
-{\r
-\r
- u_int32_t hash_key;\r
- VIP_common_ret_t hash_ret;\r
- VIP_hashp_value_t hash_val;\r
- HH_ret_t ret = HH_OK;\r
-\r
- FUNC_IN;\r
-\r
- hash_key = GID_2_HASH_KEY(entry_p->mgid);\r
-\r
- hash_ret = VIP_hashp_erase(*hash_p, hash_key, &hash_val);\r
- if (hash_ret != VIP_OK)\r
- {\r
- MTL_ERROR1("failed VIP_hashp_erase\n");\r
- ret= HH_ERR;\r
- }\r
- FREE(hash_val);\r
- MT_RETURN(ret);\r
-}\r
-\r
-static inline void print_fw_entry(THH_mcg_entry_t* entry)\r
-{\r
- u_int32_t i;\r
- MTL_DEBUG1("--- FW ENTRY ----\n");\r
-\r
- MTL_DEBUG1("gid:%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.\n",entry->mgid[0],entry->mgid[1],\r
- entry->mgid[2],entry->mgid[3],entry->mgid[4],entry->mgid[5],entry->mgid[6],entry->mgid[7],\r
- entry->mgid[8],entry->mgid[9],entry->mgid[10],entry->mgid[11],entry->mgid[12],entry->mgid[13],\r
- entry->mgid[14],entry->mgid[15]); \r
-\r
- MTL_DEBUG1("num of qps:0x%x \n",entry->valid_qps);\r
- if (entry->qps) {\r
- for (i=0; i< entry->valid_qps ; i++)\r
- {MTL_DEBUG1("qpn:0x%x ",entry->qps[i]);} \r
- }else {MTL_DEBUG1("-... no qps ...-\n");}\r
- MTL_DEBUG1("next gid idx:%d \n",entry->next_gid_index);\r
- MTL_DEBUG1("--------------\n");\r
-}\r
-\r
-static inline void print_status_entry(mcg_status_entry_t* my_entry)\r
-{\r
- MTL_DEBUG1("--- STATUS ENTRY --\n");\r
- MTL_DEBUG1("gid:%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.\n",my_entry->mgid[0],my_entry->mgid[1],\r
- my_entry->mgid[2],my_entry->mgid[3],my_entry->mgid[4],my_entry->mgid[5],my_entry->mgid[6],\r
- my_entry->mgid[7],my_entry->mgid[8],my_entry->mgid[9],my_entry->mgid[10],my_entry->mgid[11],\r
- my_entry->mgid[12],my_entry->mgid[13],my_entry->mgid[14],my_entry->mgid[15]); \r
-\r
- MTL_DEBUG1("\nnum of qps:0x%x\n",my_entry->num_valid_qps);\r
- MTL_DEBUG1("gid_idx:0x%x prev_idx:0x%x \n",my_entry->idx,my_entry->prev_idx);\r
- MTL_DEBUG1("------------------\n");\r
-}\r
-\r
-static inline HH_ret_t read_alloc_mgm(THH_mcgm_t mcgm, THH_mcg_entry_t* entry,u_int32_t idx)\r
-{\r
- THH_cmd_status_t c_status= THH_CMD_STAT_OK;\r
- entry->qps = TNMALLOC(IB_wqpn_t,mcgm->max_qp_per_mcg); \r
- if (entry->qps == NULL) { \r
- MTL_ERROR1(MT_FLFMT("Null pointer detected\n")); \r
- MT_RETURN(HH_EAGAIN); \r
- }\r
- memset(entry->qps, 0, sizeof(IB_wqpn_t) * mcgm->max_qp_per_mcg); \r
- c_status = THH_cmd_READ_MGM(mcgm->cmd_if_h,idx,mcgm->max_qp_per_mcg,entry); \r
- if (c_status != THH_CMD_STAT_OK) { \r
- FREE(entry->qps);\r
- entry->qps = NULL;\r
- MTL_ERROR1(MT_FLFMT("failed READ_MGM\n")); \r
- MT_RETURN(HH_ERR);\r
- }\r
- print_fw_entry(entry);\r
- MT_RETURN(HH_OK);\r
-}\r
-\r
-HH_ret_t THH_mcgm_get_num_mcgs(THH_mcgm_t mcgm, u_int32_t *num_mcgs_p)\r
-{\r
- THMCG_CHECK_NULL(mcgm,done);\r
- *num_mcgs_p = VIP_hashp_get_num_of_objects(mcgm->my_hash);\r
- MT_RETURN(HH_OK);\r
-\r
-done:\r
- MT_RETURN(HH_EINVAL);\r
-}\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#if !defined(H_MCGM_H)\r
-#define H_MCGM_H\r
-\r
-#include <mtl_common.h>\r
-#include <vapi_types.h>\r
-#include <hh.h>\r
-#include <thh.h>\r
-\r
-typedef struct mcg_status_entry mcg_status_entry_t;\r
-\r
-#define GID_2_HASH_KEY(gid) (*((u_int32_t *)gid) ^ *((u_int32_t *)gid+1) ^ *((u_int32_t *)gid+2) ^ *((u_int32_t *)gid+3))\r
-\r
-#define THMCG_CHECK_HH_ERR(res, lable,message) \\r
- if ((res) != HH_OK) { \\r
- MTL_ERROR1(MT_FLFMT(message)); \\r
- goto lable; \\r
- }\r
-\r
-#define THMCG_CHECK_CMDIF_ERR(res, lable,message) \\r
- if ((res) != THH_CMD_STAT_OK) { \\r
- MTL_ERROR1(MT_FLFMT(message)); \\r
- goto lable; \\r
- }\r
-\r
-#define THMCG_CHECK_NULL(p, lable) \\r
- if ((p) == NULL) { \\r
- MTL_ERROR1(MT_FLFMT("Null pointer detected\n")); \\r
- goto lable; \\r
- }\r
-\r
-\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_mcgm_create\r
- * \r
- Arguments:\r
- hob - THH_hob this object is included in \r
- mght_total_entries - Number of entries in the MGHT \r
- mght_hash_bins - Number of bins in the hash table \r
- max_qp_per_mcg - Max number of QPs per Multicast Group \r
- mcgm_p - Allocated THH_mcgm_t object \r
- Returns:\r
- HH_OK \r
- HH_EINVAL \r
- HH_EAGAIN\r
- \r
- Description: Create THH_mcgm_t instance. \r
- \r
- \r
- ************************************************************************/\r
- \r
-extern HH_ret_t THH_mcgm_create(/*IN */ THH_hob_t hob, \r
- /*IN */ VAPI_size_t mght_total_entries, \r
- /*IN */ VAPI_size_t mght_hash_bins, \r
- /*IN */ u_int16_t max_qp_per_mcg, \r
- /*OUT*/ THH_mcgm_t *mcgm_p );\r
-\r
-/************************************************************************\r
- * Function: THH_mcgm_destroy\r
- * \r
- Arguments:\r
- mcgm - THH_mcgm to destroy \r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL \r
- \r
- Description: \r
- Free THH_mcgm context resources. \r
- ************************************************************************/\r
-\r
-extern HH_ret_t THH_mcgm_destroy( /*IN */ THH_mcgm_t mcgm );\r
-\r
-/************************************************************************\r
- * Function: THH_mcgm_attach_qp\r
- * \r
- Arguments:\r
- mcgm \r
- qpn -QP number of QP to attach \r
- mgid -GID of a multicast group to attach to\r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL \r
- HH_EAGAIN - No more MGHT entries. \r
- HH_2BIG_MCG_SIZE - Number of QPs attached to multicast groups exceeded") \\r
- HH_ERR - an error has occured\r
- \r
- Description: \r
- Attach given QP to multicast with given DGID.\r
- \r
- ************************************************************************/\r
-\r
- \r
-extern HH_ret_t THH_mcgm_attach_qp(/*IN */ THH_mcgm_t mcgm, \r
- /*IN */ IB_wqpn_t qpn, \r
- /*IN */ IB_gid_t mgid );\r
-/************************************************************************\r
- * Function: THH_mcgm_detach_qp\r
- * \r
- Arguments:\r
- mcgm \r
- qpn - QP number of QP to attach \r
- mgid - GID of a multicast group to attach to \r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL - No such multicast group or given QP i not in given group \r
- HH_ERR - an error has occured\r
- \r
- \r
- Description: \r
- Detach given QP from multicast group with given GID. \r
- \r
- ************************************************************************/\r
-\r
-extern HH_ret_t THH_mcgm_detach_qp(/*IN */ THH_mcgm_t mcgm, \r
- /*IN */ IB_wqpn_t qpn, \r
- /*IN */ IB_gid_t mgid); \r
-\r
-/************************************************************************\r
- * Function: THMCG_get_num_mcgs\r
- * \r
- Arguments:\r
- mcgm \r
- num_mcgs_p - current number of multicast groups \r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL - invalid mcgm handle \r
- \r
- \r
- Description: \r
- \r
- ************************************************************************/\r
-extern HH_ret_t THH_mcgm_get_num_mcgs(THH_mcgm_t mcgm, u_int32_t *num_mcgs_p);\r
-\r
-#endif /* H_MCGM_H */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
- \r
-/* First to validate "tmrwm.h" is a legal header */\r
-#include <tmrwm.h>\r
-#if defined(USE_STD_MEMORY)\r
-# include <memory.h>\r
-#endif\r
-#include <mtl_common.h>\r
-#include <mosal.h>\r
-\r
-#include <cmdif.h>\r
-#include <epool.h>\r
-#include <thh_uldm.h>\r
-#include <thh.h>\r
-#include <tlog2.h>\r
-#include <tavor_if_defs.h>\r
-#include <vip_common.h>\r
-#include <vip_array.h>\r
-#include <vapi_common.h>\r
-\r
-#include "extbuddy.h"\r
-\r
-#include <mosal.h>\r
-#ifndef MTL_TRACK_ALLOC\r
-#define EXTBUDDY_ALLOC_MTT(index,log2_n_segs) \r
-#define EXTBUDDY_FREE_MTT(index,log2_n_segs) \r
-#else\r
-#define EXTBUDDY_ALLOC_MTT(index,log2_n_segs) \\r
- memtrack_alloc(MEMTRACK_MTT_SEG,(void *)(MT_virt_addr_t)index,(unsigned long)(1<<log2_n_segs),GFP_KERNEL,__FILE__,__LINE__)\r
-#define EXTBUDDY_FREE_MTT(index,log2_n_segs) memtrack_free(MEMTRACK_MTT_SEG,(void *)(MT_virt_addr_t)index,__FILE__,__LINE__)\r
-#endif\r
-\r
-enum { TAVOR_LOG_MPT_PG_SZ_SHIFT = 12 }; /* log2(4K) */\r
-#define LOG2_MTT_ENTRY_SZ 3\r
-\r
-#define IFFREE(p) if (p) { FREE(p); }\r
-#define logIfErr(f) \\r
- if (rc != HH_OK) { MTL_ERROR1("%s: rc=%s\n", f, HH_strerror_sym(rc)); }\r
-\r
-#define CURRENT_MEMKEY(mrwm,mpt_seg,mpt_index) \\r
- ( ((mrwm)->key_prefix[mpt_seg][mpt_index-(mrwm)->offset[mpt_seg]] << (mrwm)->props.log2_mpt_sz) | (mpt_index))\r
-\r
-/* macro for translating cmd_rc return codes for non-destroy procs */\r
-#define CMDRC2HH_ND(cmd_rc) ((cmd_rc == THH_CMD_STAT_OK) ? HH_OK : \\r
- (cmd_rc == THH_CMD_STAT_EINTR) ? HH_EINTR : HH_EFATAL)\r
- \r
-/* Reg_Segs_t phys_pages array allocation/free */\r
-\r
-#define SMART_MALLOC(size) THH_SMART_MALLOC(size)\r
-#define SMART_FREE(ptr,size) THH_SMART_FREE(ptr,size)\r
-\r
-/*** warning C4242: 'function' : conversion from 'VAPI_size_t' to 'const size_t', possible loss of data ***/\r
-#define ALLOC_PHYS_PAGES_ARRAY(reg_segs_p) \\r
- (reg_segs_p)->phys_pages= (VAPI_phy_addr_t*)SMART_MALLOC((size_t)(sizeof(VAPI_phy_addr_t)*(reg_segs_p)->n_pages))\r
-\r
-/* Free memory allocated in buf_lst_2_pages() into phys_pages of reg_segs */\r
-#define FREE_PHYS_PAGES_ARRAY(reg_segs_p) { \\r
- SMART_FREE((reg_segs_p)->phys_pages,sizeof(VAPI_phy_addr_t)*(reg_segs_p)->n_pages); \\r
- (reg_segs_p)->phys_pages= NULL; \\r
-}\r
-\r
-static u_int8_t native_page_shift;\r
-\r
-\r
-\r
-\r
-#define DHERE {MTL_DEBUG4(MT_FLFMT(""));}\r
-\r
-enum\r
-{\r
- /* These are the tunebale parameters */\r
- LOG2_MIN_SEG_SIZE = 3,\r
- /* LOG2_MAX_SEGS = 20, 1M limit [REMOVED! 2002/November/18] */\r
- MTT_WRITE_MAX = 64,\r
-\r
- /* Better be given explicitly on creation (by firmware), hard code for now */\r
- MTT_LOG_MTT_ENTRY_SIZE = 3\r
-\r
-};\r
-\r
-/*keeps all the data shared between shared mr's */\r
-typedef struct\r
-{\r
- VAPI_size_t size;\r
- u_int32_t seg_start; /* segment index - given by EPool */\r
- u_int8_t log2_segs;\r
- u_int8_t page_shift;\r
- u_int32_t ref_count; \r
- MOSAL_spinlock_t ref_lock; /* May be removed when atomic is available */\r
-} Shared_data_t;\r
-\r
-/* Since remote=local for {key,start,size}\r
- * we can do with less than the whole HH_mr_info_t.\r
- * On the other hand, we do need to save some internal data.\r
- */\r
-typedef struct\r
-{\r
- VAPI_lkey_t key;\r
- IB_virt_addr_t start;\r
- HH_pd_hndl_t pd;\r
- \r
- Shared_data_t* shared_p; \r
- MOSAL_iobuf_t iobuf; /* for internal regions only */\r
-\r
- /* the small fields, in the end */\r
- VAPI_mrw_acl_t acl;\r
- MOSAL_mutex_t modify_mtx;\r
-\r
-#if defined(MT_SUSPEND_QP)\r
- MT_bool is_suspended; /* cannot use mpt_entry field below, since mpt_entry\r
- * is set before iobuf_dereg when suspending\r
- */\r
- THH_mpt_entry_t *mpt_entry; /* saved at suspend, for unsuspend */\r
- MT_virt_addr_t va; /* saved at suspend, for unsuspend */\r
- MT_size_t size; /* saved at suspend, for unsuspend */\r
- MOSAL_prot_ctx_t prot_ctx; /* saved at suspend, for unsuspend */\r
-#endif\r
- \r
-} Mr_sw_t;\r
-\r
-typedef struct {\r
- u_int32_t seg_start; /* segment index - given by EPool */\r
- u_int8_t log2_segs;\r
- u_int8_t log2_page_sz;\r
- MT_virt_addr_t mtt_entries; /* Mapped MTT entries */\r
- MT_virt_addr_t mpt_entry; /* Mapped MPT entry */\r
- u_int32_t last_free_key; /* Last memory key that was explicitly freed \r
- * (for key wrap around detection) */\r
-} FMR_sw_info_t;\r
-\r
-\r
-typedef enum {\r
- MPT_int,\r
- MPT_ext,\r
- MPT_EOR, /* end of regions */\r
- MPT_win = MPT_EOR,\r
- MPT_N,\r
- MPT_reserved\r
-} mpt_segment_t;\r
-\r
-/* The MRWM main structure */\r
-typedef struct THH_mrwm_st\r
-{\r
- THH_hob_t hob;\r
- THH_mrwm_props_t props;\r
- u_int32_t usage_cnt[MPT_N]; /* current number of rgn_int,rgn_ext,win */\r
- VIP_array_p_t mpt[MPT_N]; /* MPT array for each of the entities */\r
- u_int8_t* is_fmr_bits;\r
- u_int32_t max_mpt[MPT_N];/* limit size of each mpt array */\r
- u_int32_t offset[MPT_N]; /* [MPT_int=0] = 0, [MPT_EOR] = #regions */\r
- u_int16_t *key_prefix[MPT_N]; /* persistant key prefix storage */\r
- MOSAL_spinlock_t key_prefix_lock;/* protect key_prefix updates (2be changed to atomic_inc)*/\r
- /* u_int8_t log2_seg_size; */\r
- Extbuddy_hndl xbuddy_tpt;\r
- u_int32_t surplus_segs; /* # segs we can give over 1/region */\r
- MOSAL_spinlock_t reserve_lock; /* protect MPT (usage_cnt) and MTT (surplus_segs) reservations*/\r
- MOSAL_mutex_t extbuddy_lock; /* protect extbuddy calls */\r
-\r
- /* convenient handle saving */\r
- THH_cmd_t cmd_if;\r
- THH_uldm_t uldm;\r
-} TMRWM_t;\r
-\r
-/* place holder for parameters during registartion */\r
-typedef struct\r
-{\r
- THH_mrwm_t mrwm;\r
- THH_mpt_entry_t mpt_entry;\r
- u_int32_t mpt_index; /* == lower_bits(mpt_entry.lkey) */\r
- VAPI_phy_addr_t* phys_pages;\r
- VAPI_size_t n_pages;\r
- u_int8_t log2_page_size;\r
- u_int32_t seg_start;\r
- u_int32_t key;\r
- VAPI_mrw_acl_t acl;\r
- MOSAL_iobuf_t iobuf; /* for internal regions */\r
-} Reg_Segs_t;\r
-\r
-\r
-/************************************************************************/\r
-/* private functions */\r
-\r
-\r
-static inline mpt_segment_t get_mpt_seg(THH_mrwm_t mrwm,u_int32_t mpt_index)\r
-{\r
- if (mpt_index < mrwm->offset[MPT_int]) { /* internal region */\r
- return MPT_reserved;\r
- } else if (mpt_index < mrwm->offset[MPT_ext]) {\r
- return MPT_int;\r
- } else if (mpt_index < mrwm->offset[MPT_win]) {\r
- return MPT_ext;\r
- } /* else... */\r
- return MPT_win;\r
-}\r
-\r
-/********** MPT entries and MTT segments reservations *************/\r
-\r
- \r
-/* reserve an MPT entry in given segment (to limit VIP_array's size) */\r
-static inline HH_ret_t reserve_mpt_entry(THH_mrwm_t mrwm, mpt_segment_t mpt_seg)\r
-{\r
- MOSAL_spinlock_lock(&mrwm->reserve_lock);\r
- if (mrwm->usage_cnt[mpt_seg] >= mrwm->max_mpt[mpt_seg]) {\r
- MOSAL_spinlock_unlock(&mrwm->reserve_lock);\r
- return HH_EAGAIN; /* reached limit for given segment */\r
- }\r
- MTL_DEBUG5(MT_FLFMT("%s: usage_cnt[%d]=%d -> %d"),__func__,\r
- mpt_seg,mrwm->usage_cnt[mpt_seg],mrwm->usage_cnt[mpt_seg]+1);\r
- mrwm->usage_cnt[mpt_seg]++;\r
- MOSAL_spinlock_unlock(&mrwm->reserve_lock);\r
- return HH_OK;\r
-}\r
-\r
-/* opposite of reserve_mpt */\r
-static inline void release_mpt_entry(THH_mrwm_t mrwm, mpt_segment_t mpt_seg)\r
-{\r
- MOSAL_spinlock_lock(&mrwm->reserve_lock);\r
-#ifdef MAX_DEBUG\r
- if (mrwm->usage_cnt[mpt_seg] == 0) {\r
- MTL_ERROR1(MT_FLFMT("%s: Invoked while usage_cnt==0"),__func__);\r
- }\r
-#endif\r
- MTL_DEBUG5(MT_FLFMT("%s: usage_cnt[%d]=%d -> %d"),__func__,\r
- mpt_seg,mrwm->usage_cnt[mpt_seg],mrwm->usage_cnt[mpt_seg]-1);\r
- mrwm->usage_cnt[mpt_seg]--;\r
- MOSAL_spinlock_unlock(&mrwm->reserve_lock);\r
-}\r
-\r
-/* reserve MTT segments (to assure allocation in "extbuddy" structure) */\r
-static inline HH_ret_t reserve_mtt_segs(THH_mrwm_t mrwm, u_int32_t surplus2reserve)\r
-{\r
- MOSAL_spinlock_lock(&mrwm->reserve_lock);\r
- if (surplus2reserve > mrwm->surplus_segs) {\r
- MTL_ERROR4(MT_FLFMT("%s: Cannot reserve %d MTT segments (%d dynamic MTT segments left)"),\r
- __func__,surplus2reserve,mrwm->surplus_segs);\r
- MOSAL_spinlock_unlock(&mrwm->reserve_lock);\r
- return HH_EAGAIN; /* reached limit */\r
- }\r
- MTL_DEBUG5(MT_FLFMT("%s: MTT segments %d -> %d"),__func__,\r
- mrwm->surplus_segs,mrwm->surplus_segs-surplus2reserve);\r
- mrwm->surplus_segs -= surplus2reserve;\r
- MOSAL_spinlock_unlock(&mrwm->reserve_lock);\r
- return HH_OK;\r
-}\r
-\r
-static inline void release_mtt_segs(THH_mrwm_t mrwm, u_int32_t surplus2reserve)\r
-{\r
- MOSAL_spinlock_lock(&mrwm->reserve_lock);\r
- MTL_DEBUG5(MT_FLFMT("%s: MTT segments %d -> %d"),__func__,\r
- mrwm->surplus_segs,mrwm->surplus_segs+surplus2reserve);\r
- mrwm->surplus_segs += surplus2reserve;\r
- MOSAL_spinlock_unlock(&mrwm->reserve_lock);\r
-}\r
-\r
-/************************************************************************/\r
-static HH_ret_t buf_lst_2_pages\r
-(\r
- const VAPI_phy_addr_t* phys_buf_lst,\r
- const VAPI_size_t* buf_sz_lst,\r
- MT_size_t n,\r
- IB_virt_addr_t start,\r
- VAPI_phy_addr_t iova_offset,\r
- Reg_Segs_t* reg_segs\r
-);\r
-\r
-\r
-static inline HH_ret_t tpt_buf_lst_2_pages(const HH_mr_t* mr, Reg_Segs_t* rs)\r
-{\r
- const HH_tpt_t* t = &mr->tpt;\r
- MTL_DEBUG4(MT_FLFMT("tpt_buf_lst_2_pages"));\r
- return buf_lst_2_pages(t->tpt.buf_lst.phys_buf_lst, t->tpt.buf_lst.buf_sz_lst,\r
- t->num_entries, \r
- mr->start, t->tpt.buf_lst.iova_offset,\r
- rs);\r
-} /* tpt_buf_lst_2_pages */\r
-\r
-/******************************************************/\r
-\r
-static void release_shared_mtts(THH_mrwm_t mrwm, Mr_sw_t *mrsw_p)\r
-{\r
- MOSAL_spinlock_lock(&mrsw_p->shared_p->ref_lock);\r
- if (mrsw_p->shared_p->ref_count > 1) {\r
- mrsw_p->shared_p->ref_count--; \r
- MOSAL_spinlock_unlock(&mrsw_p->shared_p->ref_lock);\r
- }else{ \r
- MOSAL_spinlock_unlock(&mrsw_p->shared_p->ref_lock);\r
- /* MTT segment 0 is reserved, so if seg_start is 0 it is a physical addressing region (no MTTs)*/\r
- if (mrsw_p->shared_p->seg_start != 0) { \r
- MOSAL_mutex_acq_ui(&mrwm->extbuddy_lock);\r
- extbuddy_free(mrwm->xbuddy_tpt, mrsw_p->shared_p->seg_start, mrsw_p->shared_p->log2_segs);\r
- EXTBUDDY_FREE_MTT(mrsw_p->shared_p->seg_start, mrsw_p->shared_p->log2_segs);\r
- MOSAL_mutex_rel(&mrwm->extbuddy_lock);\r
- release_mtt_segs(mrwm,(1 << mrsw_p->shared_p->log2_segs) - 1);\r
- }\r
- FREE(mrsw_p->shared_p); \r
- }\r
- mrsw_p->shared_p = NULL;\r
-}\r
-\r
-static HH_ret_t change_translation(Reg_Segs_t* rs_p,HH_mr_t* mr_props_p, Mr_sw_t *mrsw_p,\r
- u_int8_t *log2_segs_p)\r
-{\r
- HH_ret_t ret= HH_EAGAIN;\r
- u_int32_t n_segs_o = (1 << mrsw_p->shared_p->log2_segs); /* >= 1 !! */\r
- THH_mrwm_t mrwm = rs_p->mrwm;\r
- \r
- /*calc num of segs of new mr*/\r
- u_int8_t page_shift;\r
- u_int8_t log2_mtt_seg_sz = mrwm->props.log2_mtt_seg_sz;\r
- /* avoid explict u_int64_t division ! */\r
- u_int32_t n_segs;\r
- u_int8_t log2_segs;\r
- MT_size_t seg_comp;\r
- MOSAL_iobuf_props_t iobuf_props;\r
-\r
- FUNC_IN;\r
-\r
- switch (mr_props_p->tpt.tpt_type) {\r
- case HH_TPT_PAGE: \r
- /*calc num of segs of new mr*/\r
- page_shift = mr_props_p->tpt.tpt.page_lst.page_shift;\r
- rs_p->n_pages = ((mr_props_p->start+mr_props_p->size - 1)>> page_shift)-(mr_props_p->start>> page_shift)+ 1;\r
- /* avoid explict u_int64_t division ! */\r
- if (rs_p->n_pages != mr_props_p->tpt.num_entries) {\r
- MTL_ERROR1(MT_FLFMT("%s: Given "SIZE_T_DFMT" pages of %uKB is smaller than given region size ("U64_FMT" KB)"),\r
- __func__,mr_props_p->tpt.num_entries,(1<<(page_shift-10)),mr_props_p->size>>10);\r
- return HH_EINVAL;\r
- }\r
- rs_p->phys_pages = (VAPI_phy_addr_t*)mr_props_p->tpt.tpt.page_lst.phys_page_lst;\r
- rs_p->log2_page_size= mr_props_p->tpt.tpt.page_lst.page_shift;\r
- break; \r
- \r
- case HH_TPT_BUF: \r
- if ((mr_props_p->tpt.num_entries == 1) \r
- && (mr_props_p->tpt.tpt.buf_lst.phys_buf_lst[0] == mr_props_p->start))\r
- {\r
- /* no translation needed */\r
- rs_p->mpt_entry.pa = TRUE;\r
- rs_p->n_pages = 1;\r
- rs_p->seg_start= 0;\r
- rs_p->log2_page_size= 0;\r
- ret= HH_OK;\r
- }else {\r
- ret = tpt_buf_lst_2_pages(mr_props_p, rs_p);\r
- }\r
- if (ret != HH_OK) return ret;\r
- break;\r
- \r
- case HH_TPT_IOBUF:\r
- rs_p->iobuf= mr_props_p->tpt.tpt.iobuf;\r
- if (MOSAL_iobuf_get_props(rs_p->iobuf,&iobuf_props) != MT_OK) {\r
- MTL_ERROR4(MT_FLFMT("Failed MOSAL_iobuf_get_props."));\r
- return HH_EINVAL;\r
- }\r
- rs_p->n_pages= iobuf_props.nr_pages;\r
- rs_p->phys_pages= NULL;\r
-/*** warning C4242: '=' : conversion from 'MT_u_int_t' to 'u_int8_t', possible loss of data ***/\r
- rs_p->log2_page_size = (u_int8_t)iobuf_props.page_shift;\r
- break;\r
- \r
- default: \r
- MTL_ERROR2(MT_FLFMT("%s: Invalid tpt type (%d)\n"),__func__,mr_props_p->tpt.tpt_type); \r
- return HH_EINVAL;\r
- }\r
-/*** warning C4242: '=' : conversion from 'VAPI_size_t' to 'MT_size_t', possible loss of data ***/\r
- seg_comp= (u_int8_t)(rs_p->n_pages >> log2_mtt_seg_sz);\r
- seg_comp= ((seg_comp << log2_mtt_seg_sz) != rs_p->n_pages) ? seg_comp + 1 : seg_comp;\r
- /*check that n_segs will not overflow 32 bits */\r
- log2_segs = ceil_log2(seg_comp);\r
- if (log2_segs >= (8*sizeof(n_segs))) return HH_EINVAL_PARAM;\r
- n_segs = 1 << log2_segs;\r
-\r
- //MTL_DEBUG4(MT_FLFMT("start=0x%Lx, size=0x%Lx, shift=%d, ne=%d, np=%d"),(u_int64_t)start,\r
- // (u_int64_t)mr_props_p->size, page_shift,(int)mr_props_p->tpt.num_entries, (int)n_pages);\r
- \r
- MTL_DEBUG3(MT_FLFMT("log2 mtt sz=%d \n"),log2_mtt_seg_sz);\r
- MTL_DEBUG3(MT_FLFMT("n_segs_o=%d n_segs=%d \n"),n_segs_o,n_segs);\r
- \r
- if ( (n_segs != n_segs_o) || (mrsw_p->shared_p->ref_count > 1) || (rs_p->mpt_entry.pa)) {\r
- /* replace MTTs (or just free if new "translation" is physical with no translation) */\r
- u_int32_t seg_start = EXTBUDDY_NULL;\r
- /* we are not using spinlock on the ref_cnt on the above check to simplify code*/\r
- /* if we are "lucky" enough we may get here even we can keep use the same MTTs */\r
- /* (when 2 sharing regions did the change_translation simultaneously) */\r
- /* but... this is not a bug. Just an overkill (reallocating MTTs) */\r
- /* ("shared memory" regions are rarely reregistered) */\r
- release_shared_mtts(mrwm,mrsw_p);\r
-\r
- MTL_DEBUG1(MT_FLFMT("alloc new MTT's \n"));\r
- /* 2. alloc new MTT's */ \r
- if (!rs_p->mpt_entry.pa) { /* If translation needed */\r
- if (reserve_mtt_segs(mrwm, n_segs-1) != HH_OK) { /* surplus segments reservation */\r
- MTL_ERROR1(MT_FLFMT("Out of MTT segments"));\r
- return HH_EAGAIN;\r
- }\r
- if (MOSAL_mutex_acq(&mrwm->extbuddy_lock,TRUE) != MT_OK) {\r
- release_mtt_segs(mrwm,n_segs-1);\r
- return HH_EINTR;\r
- }\r
- seg_start = extbuddy_alloc(mrwm->xbuddy_tpt, log2_segs); \r
- if (seg_start != EXTBUDDY_NULL) {EXTBUDDY_ALLOC_MTT(seg_start,log2_segs);}\r
- MOSAL_mutex_rel(&mrwm->extbuddy_lock);\r
-\r
- if (seg_start != EXTBUDDY_NULL) {\r
- rs_p->seg_start = seg_start;\r
- rs_p->mpt_entry.mtt_seg_adr = mrwm->props.mtt_base |\r
- (seg_start << (log2_mtt_seg_sz+ MTT_LOG_MTT_ENTRY_SIZE));;\r
- }else{ /* reregister (translation) failed */\r
- MTL_ERROR1(MT_FLFMT("Failed allocating MTT segments (unexpected error !!)"));\r
- release_mtt_segs(mrwm,n_segs-1);\r
- return HH_EAGAIN;\r
- }\r
- }\r
- }else{ /* else, using the same MTT's of the original region */\r
- rs_p->seg_start= mrsw_p->shared_p->seg_start;\r
- rs_p->log2_page_size = mrsw_p->shared_p->page_shift;\r
- }\r
- \r
- *log2_segs_p= log2_segs;\r
- return HH_OK;\r
-}\r
-\r
-\r
-/************************************************************************/\r
-static void determine_ctx(\r
- THH_mrwm_t mrwm,\r
- THH_internal_mr_t* mr_props,\r
- MOSAL_protection_ctx_t* ctx_p\r
-)\r
-{\r
- HH_ret_t rc = THH_uldm_get_protection_ctx(mrwm->uldm, mr_props->pd, ctx_p);\r
- if (rc != HH_OK)\r
- {\r
-#ifndef __DARWIN__\r
- MTL_DEBUG4(MT_FLFMT("THH_uldm_get_protection_ctx failed, use ctx=0x%x"),\r
- mr_props->vm_ctx);\r
-#else\r
- MTL_DEBUG4(MT_FLFMT("THH_uldm_get_protection_ctx failed"));\r
-#endif\r
- *ctx_p = mr_props->vm_ctx;\r
- }\r
-} /* determine_ctx */\r
-\r
-\r
-\r
-/************************************************************************\r
- * Copies and check props into mrwm handle.\r
- * Here are the restrictions:\r
- * #-regions + #-windows <= #MPT-entries.\r
- * segment_size = 2^n >= 2^3 = 8\r
- * #-regions <= #-segments <= 1M = 2^20\r
- */\r
-static MT_bool check_props(const THH_mrwm_props_t* props, THH_mrwm_t mrwm)\r
-{\r
- MT_bool ok = FALSE;\r
- u_int8_t log2_mtt_sz = props->log2_mtt_sz;\r
- u_int32_t n_log_reserved_mtt_segs= props->log2_rsvd_mtt_segs + props->log2_mtt_seg_sz;\r
- u_int32_t tavor_num_reserved_mtts = (u_int32_t) (1ul << props->log2_rsvd_mtt_segs);\r
- u_int32_t tavor_num_reserved_mpts = (u_int32_t) (1ul << props->log2_rsvd_mpts);\r
- u_int32_t n_req_mpts = (u_int32_t)(tavor_num_reserved_mpts + props->max_mem_reg_internal + \r
- props->max_mem_reg + props->max_mem_win);\r
- \r
- MTL_DEBUG4(MT_FLFMT("base="U64_FMT", log2_mpt_sz=%d, log2_mtt_sz=%d, n_req_mpts=0x%x"),\r
- props->mtt_base, props->log2_mpt_sz, log2_mtt_sz, n_req_mpts);\r
- if ((n_req_mpts <= (1ul << props->log2_mpt_sz)) &&\r
- (log2_mtt_sz > n_log_reserved_mtt_segs) &&\r
- (log2_mtt_sz >= LOG2_MIN_SEG_SIZE)) /* funny check, but... */\r
- {\r
- u_int32_t n_segs;\r
- u_int32_t n_rgns= (u_int32_t)(props->max_mem_reg_internal + props->max_mem_reg);\r
- u_int8_t log2_n_segs = props->log2_mtt_sz - props->log2_mtt_seg_sz;\r
- mrwm->props = *props; /* But we may fix some values */\r
- MTL_DEBUG4(MT_FLFMT("log2_n_segs=%d, max=%d"), \r
- log2_n_segs, props->log2_max_mtt_segs);\r
- if (log2_n_segs > props->log2_max_mtt_segs)\r
- {\r
- /* Waste of MTT memory, but we cannot use more than 1M */\r
- mrwm->props.log2_mtt_sz = props->log2_mtt_seg_sz + \r
- props->log2_max_mtt_segs;\r
- log2_n_segs = props->log2_max_mtt_segs;\r
- MTL_DEBUG4(MT_FLFMT("Enlarge: log2_n_segs=%d"), log2_n_segs);\r
- }\r
- n_segs = (1ul << log2_n_segs);\r
- ok = (n_rgns <= n_segs);\r
- if (!ok)\r
- {\r
- MTL_ERROR1(MT_FLFMT("n_rgns=0x%x > n_segs=0x%x"), n_rgns, n_segs);\r
- return ok;\r
- }\r
- mrwm->surplus_segs = (n_segs - tavor_num_reserved_mtts) - n_rgns;\r
- }\r
- MTL_DEBUG4(MT_FLFMT("ok=%d"), ok);\r
- return ok;\r
-} /* check_props */\r
-\r
-\r
-/************************************************************************/\r
-static void mpt_entry_init(THH_mpt_entry_t* e)\r
-{\r
- memset(e, 0, sizeof(THH_mpt_entry_t));\r
- e->ver = 0;\r
- /* e->ce = 1; */\r
- e->lr = TRUE;\r
- e->pw = 0;\r
- e->m_io = TRUE;\r
- /* e->vl = 0; */\r
- /* e->owner = 0; */\r
- e->status = 0;\r
- e->win_cnt = 0;\r
- e->win_cnt_limit = 0; /* 0 means no limit */\r
-} /* mpt_entry_init */\r
-\r
-\r
-/************************************************************************/\r
-static void props2mpt_entry(const HH_mr_t* props, THH_mpt_entry_t* e)\r
-{\r
- VAPI_mrw_acl_t acl = props->acl;\r
-\r
- mpt_entry_init(e);\r
- e->lw = (acl & VAPI_EN_LOCAL_WRITE ? TRUE : FALSE);\r
- e->rr = (acl & VAPI_EN_REMOTE_READ ? TRUE : FALSE);\r
- e->rw = (acl & VAPI_EN_REMOTE_WRITE ? TRUE : FALSE);\r
- e->a = (acl & VAPI_EN_REMOTE_ATOM ? TRUE : FALSE);\r
- e->eb = (acl & VAPI_EN_MEMREG_BIND ? TRUE : FALSE);\r
- e->pd = props->pd;\r
- e->start_address = props->start;\r
- e->reg_wnd_len = props->size;\r
- e->pa = FALSE;\r
-} /* props2mpt_entry */\r
-\r
-/************************************************************************/\r
-static HH_ret_t smr_props2mpt_entry(THH_mrwm_t mrwm,const HH_smr_t* props, THH_mpt_entry_t* e)\r
-{\r
- VAPI_mrw_acl_t acl = props->acl;\r
- HH_mr_info_t orig_mr; \r
- HH_ret_t ret;\r
-\r
- mpt_entry_init(e);\r
- e->lw = (acl & VAPI_EN_LOCAL_WRITE ? TRUE : FALSE);\r
- e->rr = (acl & VAPI_EN_REMOTE_READ ? TRUE : FALSE);\r
- e->rw = (acl & VAPI_EN_REMOTE_WRITE ? TRUE : FALSE);\r
- e->a = (acl & VAPI_EN_REMOTE_ATOM ? TRUE : FALSE);\r
- e->eb = (acl & VAPI_EN_MEMREG_BIND ? TRUE : FALSE);\r
- e->pd = props->pd;\r
- e->start_address = props->start;\r
- \r
- /* size is not given, so we must query it according to lkey of the original mr*/\r
- ret = THH_mrwm_query_mr(mrwm,props->lkey,&orig_mr);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("failed quering the original mr \n");\r
- return ret;\r
- }\r
-\r
- MTL_DEBUG1("end SMR props2mpt \n");\r
- /*TBD: what about remote ?? */\r
- e->reg_wnd_len = orig_mr.local_size;\r
- return HH_OK;\r
-} /* props2mpt_entry */\r
-\r
-static void init_fmr_mpt_entry(THH_mpt_entry_t* mpt_entry_p, \r
- HH_pd_hndl_t pd, \r
- VAPI_mrw_acl_t acl,\r
- u_int32_t init_memkey,\r
- u_int8_t log2_page_sz,\r
- u_int64_t mtt_seg_adr)\r
-{\r
- memset(mpt_entry_p, 0, sizeof(THH_mpt_entry_t));\r
- mpt_entry_p->pd = pd;\r
- mpt_entry_p->lr = TRUE;\r
- mpt_entry_p->m_io = TRUE;\r
- mpt_entry_p->r_w = TRUE; /* Region */\r
- mpt_entry_p->pa = FALSE;\r
- mpt_entry_p->page_size = log2_page_sz - TAVOR_LOG_MPT_PG_SZ_SHIFT;\r
- mpt_entry_p->mem_key = init_memkey; /* Initial (invalid) key */\r
- mpt_entry_p->mtt_seg_adr = mtt_seg_adr;\r
- mpt_entry_p->lw = (acl & VAPI_EN_LOCAL_WRITE ? TRUE : FALSE);\r
- mpt_entry_p->rr = (acl & VAPI_EN_REMOTE_READ ? TRUE : FALSE);\r
- mpt_entry_p->rw = (acl & VAPI_EN_REMOTE_WRITE ? TRUE : FALSE);\r
- mpt_entry_p->a = (acl & VAPI_EN_REMOTE_ATOM ? TRUE : FALSE);\r
- mpt_entry_p->eb = FALSE; /* No memory bind allowed over FMRs */\r
- mpt_entry_p->reg_wnd_len= 0; /* prevent access via this MPT */\r
-}\r
-\r
-/************************************************************************/\r
-static void internal_props2mpt_entry(\r
- const THH_internal_mr_t* props,\r
- THH_mpt_entry_t* e\r
-)\r
-{\r
- mpt_entry_init(e);\r
- e->lw = TRUE;\r
- e->rr = FALSE;\r
- e->rw = FALSE;\r
- e->a = FALSE;\r
- e->eb = FALSE;\r
- e->pd = props->pd;\r
- e->start_address = props->start;\r
- e->reg_wnd_len = props->size;\r
-} /* internal_props2mpt_entry */\r
-\r
-\r
-/************************************************************************/\r
-inline static u_int32_t make_key(THH_mrwm_t mrwm, mpt_segment_t mpt_seg, u_int32_t mpt_index)\r
-{\r
- if ((mpt_index < mrwm->offset[mpt_seg]) || \r
- (mpt_index >= mrwm->offset[mpt_seg]+mrwm->max_mpt[mpt_seg])) {\r
- MTL_ERROR4(MT_FLFMT("%s: Given MPT index (0x%X) is not in given mpt segment"),__func__,\r
- mpt_index);\r
- return 0;\r
- }\r
- MOSAL_spinlock_dpc_lock(&mrwm->key_prefix_lock); /* TBD: change to atomic_inc */\r
- mrwm->key_prefix[mpt_seg][mpt_index-mrwm->offset[mpt_seg]]++;\r
- MOSAL_spinlock_unlock(&mrwm->key_prefix_lock);\r
- return CURRENT_MEMKEY(mrwm,mpt_seg,mpt_index);\r
-} /* make_key */\r
-\r
-\r
-/************************************************************************/\r
-/* Go thru the two synced arrays of buffers addresses and sizes.\r
- * For each get the alignment - that is lowest bit.\r
- * Return the total_size and the minimal lowest bit.\r
- * The latter is minimized with initial page_shift provided value.\r
- * Note that this lowest bit can be used to test native page alignment.\r
- */\r
-static u_int8_t buf_lst_2_page_shift\r
-(\r
- const VAPI_phy_addr_t* phys_buf_lst,\r
- const VAPI_size_t* buf_sz_lst,\r
- MT_size_t n,\r
- u_int8_t page_shift,\r
- VAPI_size_t* total_p\r
-)\r
-{\r
- MT_size_t bi;\r
- VAPI_phy_addr_t bs[2], *bs_begin = &bs[0], *bs_end = bs_begin + 2, *pbs;\r
- VAPI_size_t total_size = 0;\r
-\r
- MTL_DEBUG4(MT_FLFMT("n="SIZE_T_FMT", page_shift=%d"), n, page_shift);\r
- /* Find gcd of address+size that is a power of 2. \r
- * Actually minimizing lowest bit on.\r
- */\r
- for (bi = n; bi--; )\r
- { /* 'arraying' the address + size values, to allow for loop */\r
- bs[0] = phys_buf_lst[bi]; /* must be native page aligned */\r
- bs[1] = buf_sz_lst[bi];\r
- MTL_DEBUG4(MT_FLFMT("buf="U64_FMT", sz="U64_FMT), bs[0], bs[1]);\r
- total_size += buf_sz_lst[bi];\r
- for (pbs = bs_begin; pbs != bs_end; ++pbs)\r
- {\r
- VAPI_phy_addr_t u32 = *pbs;\r
- if (u32) \r
- {\r
- u_int8_t l = lowest_bit(u32);\r
- MTL_DEBUG4(MT_FLFMT("lowest_bit("U64_FMT")=%d"), u32, l);\r
- if (l < page_shift)\r
- {\r
- page_shift = l;\r
- }\r
- }\r
- }\r
- }\r
- *total_p = total_size;\r
- MTL_DEBUG4(MT_FLFMT("page_shift=%d"), page_shift);\r
- return page_shift;\r
-} /* buf_lst_2_page_shift */\r
-\r
-\r
-/************************************************************************/\r
-static HH_ret_t buf_lst_2_pages\r
-(\r
- const VAPI_phy_addr_t* phys_buf_lst,\r
- const VAPI_size_t* buf_sz_lst,\r
- MT_size_t n,\r
- IB_virt_addr_t start,\r
- VAPI_phy_addr_t iova_offset,\r
- Reg_Segs_t* reg_segs\r
-)\r
-{\r
- VAPI_size_t total_size;\r
- VAPI_phy_addr_t initial_pages_skip;\r
- VAPI_phy_addr_t* currp;\r
- VAPI_size_t page_size;\r
- MT_size_t bi;\r
- IB_virt_addr_t start_unoffset = start - iova_offset;\r
- u_int8_t page_shift = lowest_bit(start_unoffset);\r
- VAPI_size_t tmp;\r
- \r
- MTL_DEBUG4(MT_FLFMT("start="U64_FMT", offset="U64_FMT", unoffset="U64_FMT", shift=%d"),\r
- start, iova_offset, start_unoffset, page_shift);\r
- \r
- /* calc page shift */\r
- page_shift = buf_lst_2_page_shift(phys_buf_lst, buf_sz_lst, n, page_shift, \r
- &total_size);\r
- \r
- if (page_shift > TAVOR_IF_MAX_MPT_PAGE_SIZE) {\r
- MTL_ERROR1("page shift calculated :%d , due to MPT restrictions page shift wil be 32 \n",page_shift); \r
- page_shift = TAVOR_IF_MAX_MPT_PAGE_SIZE;\r
- }\r
- MTL_DEBUG4(MT_FLFMT("n="SIZE_T_DFMT", page_shift=%d"), n, page_shift);\r
- if (page_shift < native_page_shift)\r
- {\r
- MTL_ERROR1(MT_FLFMT("page shift below system page size"));\r
- return HH_EINVAL;\r
- }\r
- \r
- initial_pages_skip = /* page_size * (iova_offset/page_size) */\r
- iova_offset & ~(((VAPI_phy_addr_t)1 << page_shift) - 1);\r
- MTL_DEBUG4(MT_FLFMT("total_size="U64_FMT", initial_pages_skip="U64_FMT),total_size, initial_pages_skip);\r
- \r
- total_size -= initial_pages_skip;\r
- reg_segs->n_pages = total_size >> page_shift;\r
- reg_segs->log2_page_size = page_shift;\r
- MTL_DEBUG4(MT_FLFMT("total_size="U64_FMT", page_shift=%d, n_pages="SIZE_T_DFMT),\r
- total_size, page_shift, reg_segs->n_pages);\r
- tmp= sizeof(VAPI_phy_addr_t)*reg_segs->n_pages;\r
- if (tmp > ((MT_phys_addr_t) MAKE_ULONGLONG(0xFFFFFFFFFFFFFFFF))) {\r
- MTL_ERROR1(MT_FLFMT("total bufs size exceeds max size available on this machine"));\r
- return HH_EINVAL;\r
- }\r
-/*** warning C4242: 'function' : conversion from 'VAPI_size_t' to 'const size_t', possible loss of data ***/\r
- ALLOC_PHYS_PAGES_ARRAY(reg_segs);\r
- if (reg_segs->phys_pages == NULL)\r
- {\r
- MTL_ERROR1(MT_FLFMT("alloc of "SIZE_T_DFMT" phys_pages failed"),reg_segs->n_pages);\r
- return HH_EAGAIN;\r
- }\r
- \r
- page_size = (VAPI_size_t)1<< page_shift;\r
- currp = reg_segs->phys_pages;\r
- MTL_DEBUG4(MT_FLFMT("page_size="U64_FMT", phys_buf_lst=%p, currp=%p"),page_size, phys_buf_lst, currp);\r
- for (bi = 0; bi != n; ++bi)\r
- {\r
- VAPI_phy_addr_t buf_page = phys_buf_lst[bi] + initial_pages_skip;\r
- VAPI_phy_addr_t buf_page_end = buf_page + buf_sz_lst[bi];\r
- initial_pages_skip = 0; /* skip only in 1st buffer */\r
- MTL_DEBUG4(MT_FLFMT("bi="SIZE_T_FMT", currp=%p, bp="U64_FMT", bp_end="U64_FMT), \r
- bi, currp, buf_page, buf_page_end);\r
- for ( ; buf_page != buf_page_end; buf_page += page_size, ++currp)\r
- {\r
- MTL_DEBUG4(MT_FLFMT("currp=%p, b="U64_FMT), currp, buf_page);\r
- *currp = buf_page;\r
- }\r
- }\r
- \r
- \r
- return HH_OK;\r
-} /* buf_lst_2_pages */\r
-\r
-\r
-\r
-\r
-/************************************************************************/\r
-/* For the sake of MicroCode(?) efficiency,\r
- * we ensure writing an even number of MTTs.\r
- */\r
-static HH_ret_t mtt_writes(\r
- THH_cmd_t cmd_if,\r
- VAPI_phy_addr_t* phys_page_lst,\r
- VAPI_phy_addr_t mtt_pa,\r
- VAPI_size_t n_pages\r
-)\r
-{\r
- static const MT_size_t MTT_WRITE_MAX_SIZE = \r
- MTT_WRITE_MAX * (1ul << MTT_LOG_MTT_ENTRY_SIZE);\r
- THH_mtt_entry_t *e0,*e_end;\r
- THH_cmd_status_t cmd_rc = THH_CMD_STAT_OK;\r
- VAPI_size_t n_entries = MTT_WRITE_MAX, n_w_entries;\r
-\r
- MTL_DEBUG4(MT_FLFMT("mtt_writes: mtt_pa="U64_FMT", n="U64_FMT), mtt_pa, n_pages);\r
- e0 = (THH_mtt_entry_t*)MALLOC((MTT_WRITE_MAX + 1) * sizeof(THH_mtt_entry_t));\r
- if (!e0) {\r
- MTL_ERROR1(MT_FLFMT("kmalloc of "SIZE_T_FMT" bytes failed"),\r
- (MTT_WRITE_MAX + 1) * sizeof(THH_mtt_entry_t));\r
- return HH_EAGAIN;\r
- }\r
-\r
- e_end = e0 + MTT_WRITE_MAX;\r
-\r
-\r
- while (n_pages)\r
- {\r
- THH_mtt_entry_t* e = e0;\r
- if (n_pages < MTT_WRITE_MAX)\r
- {\r
- n_entries = n_pages;\r
- e_end = e0 + n_pages;\r
- }\r
- for (; e != e_end; ++e)\r
- {\r
- e->ptag = *phys_page_lst++;\r
- e->p = TRUE;\r
- /* MTL_DEBUG4(MT_FLFMT("e=0x%p, e->ptag=0x%Lx"), e, e->ptag); */\r
- }\r
- /* dummy extra, to ensure even number of MTTs */\r
- e->ptag = 0;\r
- e->p = FALSE;\r
- n_w_entries = (n_entries + 1) & ~1ul; /* even upper bound */\r
- MTL_DEBUG4(MT_FLFMT("mtt_pa="U64_FMT", ne="U64_FMT), mtt_pa, n_w_entries);\r
-/*** warning C4242: 'function' : conversion from 'VAPI_size_t' to 'MT_size_t', possible loss of data ***/\r
- cmd_rc = THH_cmd_WRITE_MTT(cmd_if, mtt_pa, (MT_size_t)n_w_entries, e0);\r
- n_pages -= n_entries;\r
- MTL_DEBUG4(MT_FLFMT("cmd_rc=%d, n_pages="U64_FMT), cmd_rc, n_pages);\r
- if (cmd_rc != THH_CMD_STAT_OK)\r
- {\r
- n_pages = 0;\r
- }\r
- else if (n_pages) /* may save 64-bit addition */\r
- {\r
- mtt_pa += MTT_WRITE_MAX_SIZE;\r
- }\r
- } DHERE;\r
- if (cmd_rc != THH_CMD_STAT_OK) {\r
- MTL_ERROR1(MT_FLFMT("mtt writes failed got %d \n"),cmd_rc);\r
- }\r
- FREE(e0);\r
- return (CMDRC2HH_ND(cmd_rc));\r
-} /* mtt_writes */\r
-\r
-static HH_ret_t mtt_writes_iobuf(\r
- THH_cmd_t cmd_if,\r
- MOSAL_iobuf_t iobuf,\r
- VAPI_phy_addr_t mtt_pa,\r
- VAPI_size_t n_pages\r
-)\r
-{\r
- static const MT_size_t MTT_WRITE_MAX_SIZE = \r
- MTT_WRITE_MAX * (1ul << MTT_LOG_MTT_ENTRY_SIZE);\r
- THH_mtt_entry_t *e0,*e;\r
- THH_cmd_status_t cmd_rc = THH_CMD_STAT_OK;\r
- MT_size_t n_entries = MTT_WRITE_MAX, n_w_entries;\r
- MT_size_t n_entries_out, cur_entry;\r
- MOSAL_iobuf_iter_t iobuf_iter;\r
- MT_phys_addr_t *mt_pages_p;\r
- call_result_t mt_rc;\r
- HH_ret_t rc= HH_EAGAIN;\r
-\r
- MTL_DEBUG4(MT_FLFMT("mtt_writes_iobuf: mtt_pa="U64_FMT", n="U64_FMT", iobuf=0x%p, n_pages="U64_FMT),\r
- mtt_pa, n_pages,iobuf,n_pages);\r
-\r
- e0 = (THH_mtt_entry_t*)MALLOC((MTT_WRITE_MAX + 1) * sizeof(THH_mtt_entry_t));\r
- if (!e0) {\r
- MTL_ERROR2(MT_FLFMT("kmalloc of "SIZE_T_FMT" bytes failed"),\r
- (MTT_WRITE_MAX + 1) * sizeof(THH_mtt_entry_t));\r
- return HH_EAGAIN;\r
- }\r
- mt_pages_p= (MT_phys_addr_t*)MALLOC(MTT_WRITE_MAX * sizeof(MT_phys_addr_t)); /* for MOSAL_iobuf_get_tpt_seg */\r
- if (!mt_pages_p) {\r
- MTL_ERROR2(MT_FLFMT("kmalloc of "SIZE_T_FMT" bytes failed"),\r
- MTT_WRITE_MAX * sizeof(MT_phys_addr_t));\r
- goto fail_mt_pages;\r
- }\r
- (void)MOSAL_iobuf_iter_init(iobuf,&iobuf_iter);\r
-\r
- while (n_pages)\r
- {\r
- if (n_pages < MTT_WRITE_MAX) {\r
-/*** warning C4242: '=' : conversion from 'VAPI_size_t' to 'MT_size_t', possible loss of data ***/\r
- n_entries = (MT_size_t)n_pages;\r
- }\r
-\r
- MTL_DEBUG5(MT_FLFMT("%s: n_pages="U64_FMT" n_entries="SIZE_T_FMT" mtt_pa="U64_FMT),\r
- __func__, n_pages, n_entries, mtt_pa); \r
-\r
- /* get next segment of the page table */\r
- mt_rc= MOSAL_iobuf_get_tpt_seg(iobuf, &iobuf_iter, n_entries, &n_entries_out, mt_pages_p);\r
- if (mt_rc != MT_OK) {\r
- MTL_ERROR2(MT_FLFMT("Failed MOSAL_iobuf_get_tpt_seg (%s)"),mtl_strerror_sym(mt_rc));\r
- rc= HH_EFATAL;\r
- goto fail_get_tpt;\r
- }\r
- if (n_entries_out != n_entries) { /* sanity check */\r
- MTL_ERROR2(MT_FLFMT(\r
- "Number of pages returned from MOSAL_iobuf_get_tpt_seg ("SIZE_T_DFMT\r
- ") is different from expected ("SIZE_T_DFMT")"), n_entries_out, n_entries);\r
- rc= HH_EFATAL;\r
- goto fail_get_tpt;\r
- }\r
- for (e= e0, cur_entry= 0; cur_entry < n_entries; ++e, ++cur_entry) {\r
- e->ptag = mt_pages_p[cur_entry];\r
- e->p = TRUE;\r
- /* MTL_DEBUG4(MT_FLFMT("e=0x%p, e->ptag=0x%Lx"), e, e->ptag); */\r
- }\r
- /* dummy extra, to ensure even number of MTTs */\r
- e->ptag = 0;\r
- e->p = FALSE;\r
- n_w_entries = (n_entries + 1) & ~1ul; /* even upper bound */\r
- cmd_rc = THH_cmd_WRITE_MTT(cmd_if, mtt_pa, n_w_entries, e0);\r
- if (cmd_rc != THH_CMD_STAT_OK) {\r
- MTL_ERROR1(MT_FLFMT("THH_cmd_WRITE_MTT failed (err=%d)"),cmd_rc);\r
- rc= HH_EFATAL;\r
- goto fail_cmd;\r
- }\r
- n_pages -= n_entries;\r
- mtt_pa += MTT_WRITE_MAX_SIZE;\r
- }\r
- FREE(mt_pages_p);\r
- FREE(e0);\r
- MTL_DEBUG5(MT_FLFMT("mtt_writes_iobuf - DONE"));\r
- return HH_OK;\r
-\r
- fail_cmd:\r
- fail_get_tpt:\r
- FREE(mt_pages_p);\r
- fail_mt_pages:\r
- FREE(e0);\r
- return rc;\r
-} /* mtt_writes */\r
-\r
-\r
-\r
-/************************************************************************/\r
-static HH_ret_t register_pages(Reg_Segs_t* rs_p,mpt_segment_t mpt_seg,VAPI_mrw_type_t mr_type)\r
-{\r
- HH_ret_t rc = HH_EAGAIN;\r
- THH_mrwm_t mrwm = rs_p->mrwm;\r
- THH_mpt_entry_t* mpt_entry_p = &rs_p->mpt_entry;\r
- THH_cmd_status_t cmd_rc;\r
- u_int8_t log2_seg_sz = mrwm->props.log2_mtt_seg_sz;\r
- VAPI_phy_addr_t mtt_seg_adr;\r
-\r
- MTL_DEBUG4(MT_FLFMT("register_pages: seg_start=0x%x, log2_seg_sz=%u iobuf=0x%p n_pages="SIZE_T_DFMT), \r
- rs_p->seg_start, log2_seg_sz, rs_p->iobuf, rs_p->n_pages);\r
-\r
- mtt_seg_adr = mrwm->props.mtt_base |\r
- (rs_p->seg_start << (log2_seg_sz + MTT_LOG_MTT_ENTRY_SIZE));\r
- rs_p->key = make_key(mrwm, mpt_seg,rs_p->mpt_index);\r
-\r
- mpt_entry_p->r_w = TRUE;\r
- mpt_entry_p->page_size = rs_p->log2_page_size - TAVOR_LOG_MPT_PG_SZ_SHIFT;\r
- mpt_entry_p->mem_key = rs_p->key;\r
- mpt_entry_p->mtt_seg_adr = mtt_seg_adr;\r
-\r
- if ( (!mpt_entry_p->pa) &&\r
- ((mr_type == VAPI_MR) || (mr_type == VAPI_MPR)) )\r
- {\r
- if (rs_p->iobuf != NULL) { /* use MOSAL_iobuf to write MTT entries */\r
- rc= mtt_writes_iobuf(mrwm->cmd_if, rs_p->iobuf, mtt_seg_adr, rs_p->n_pages);\r
- } else { /* page tables is given in rs_p->phys_pages */\r
- rc= mtt_writes(mrwm->cmd_if, rs_p->phys_pages, mtt_seg_adr, rs_p->n_pages);\r
- }\r
- }\r
- else rc = HH_OK; /* no need to write mtt with SHARED (or no-translation) mr */\r
- \r
- if (rc == HH_OK)\r
- {\r
- cmd_rc = THH_cmd_SW2HW_MPT(mrwm->cmd_if, rs_p->mpt_index, &rs_p->mpt_entry);\r
- MTL_DEBUG4(MT_FLFMT("SW2HW_MPT: cmd_rc=%d"), cmd_rc);\r
- if (cmd_rc != THH_CMD_STAT_OK) {\r
- MTL_ERROR1(MT_FLFMT("register pages failed got %d \n"),cmd_rc);\r
- rc = (CMDRC2HH_ND(cmd_rc));\r
- }\r
- }\r
- return rc;\r
-} /* register_pages */\r
-\r
-\r
-/************************************************************************/\r
-static HH_ret_t save_sw_context(const Reg_Segs_t* rs_p, u_int8_t log2_segs, VAPI_mrw_type_t mr_type,\r
- Mr_sw_t* mrsw)\r
-{\r
- mrsw->key = rs_p->key;\r
- mrsw->start = rs_p->mpt_entry.start_address;\r
- mrsw->pd = rs_p->mpt_entry.pd;\r
- mrsw->acl = rs_p->acl;\r
- if (mr_type != VAPI_MSHAR) {\r
- mrsw->shared_p = (Shared_data_t*)MALLOC(sizeof(Shared_data_t));\r
- if (mrsw->shared_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("save_sw_ctxt: failed allocating memory \n"));\r
- return HH_EAGAIN; \r
- }\r
- mrsw->shared_p->size = rs_p->mpt_entry.reg_wnd_len;\r
- mrsw->shared_p->seg_start = rs_p->seg_start;\r
- mrsw->shared_p->log2_segs = log2_segs;\r
- mrsw->shared_p->page_shift = rs_p->log2_page_size;\r
- mrsw->shared_p->ref_count = 1;\r
- MOSAL_spinlock_init(&mrsw->shared_p->ref_lock);\r
- }else {\r
- MOSAL_spinlock_lock(&mrsw->shared_p->ref_lock);\r
- mrsw->shared_p->ref_count ++;\r
- MOSAL_spinlock_unlock(&mrsw->shared_p->ref_lock);\r
- }\r
- mrsw->iobuf = rs_p->iobuf;\r
- return HH_OK;\r
-} /* save_sw_context */\r
-\r
-\r
-static HH_ret_t init_fmr_context(THH_mrwm_t mrwm, \r
- FMR_sw_info_t* fmr_info_p,\r
- u_int32_t mpt_index, \r
- u_int32_t seg_start, \r
- u_int8_t log2_segs,\r
- u_int8_t log2_page_sz)\r
-{\r
- MT_phys_addr_t mtt_seg_adr= \r
- mrwm->props.mtt_base | (seg_start << (mrwm->props.log2_mtt_seg_sz + MTT_LOG_MTT_ENTRY_SIZE));\r
- MT_phys_addr_t mpt_entry_adr= mrwm->props.mpt_base | (mpt_index << TAVOR_IF_STRIDE_MPT_BIT);\r
-\r
- fmr_info_p->mtt_entries= MOSAL_io_remap(mtt_seg_adr,(MT_size_t)1 << (log2_segs + mrwm->props.log2_mtt_seg_sz + MTT_LOG_MTT_ENTRY_SIZE));\r
- if (fmr_info_p->mtt_entries == 0) {\r
- MTL_ERROR2(MT_FLFMT("%s: MOSAL_io_remap("PHYS_ADDR_FMT", 0x%x) failed"),\r
- __func__, mtt_seg_adr,\r
- 1 << (log2_segs + mrwm->props.log2_mtt_seg_sz + MTT_LOG_MTT_ENTRY_SIZE));\r
- return HH_EAGAIN;\r
- }\r
- \r
- fmr_info_p->mpt_entry= MOSAL_io_remap(mpt_entry_adr, TAVOR_IF_STRIDE_MPT);\r
- if (fmr_info_p->mpt_entry == 0) {\r
- MTL_ERROR2(MT_FLFMT("%s: MOSAL_io_remap("PHYS_ADDR_FMT", 0x%x) failed"), __func__, \r
- mpt_entry_adr, TAVOR_IF_STRIDE_MPT);\r
- MOSAL_io_unmap((MT_virt_addr_t)fmr_info_p->mtt_entries);\r
- return HH_EAGAIN;\r
- }\r
- \r
- fmr_info_p->last_free_key= CURRENT_MEMKEY(mrwm,MPT_ext,mpt_index);\r
- fmr_info_p->seg_start= seg_start;\r
- fmr_info_p->log2_segs= log2_segs;\r
- fmr_info_p->log2_page_sz= log2_page_sz;\r
-\r
- return HH_OK;\r
-}\r
-\r
-\r
-/************************************************************************/\r
-static HH_ret_t alloc_reg_pages(\r
- Reg_Segs_t* rs_p,\r
- mpt_segment_t tpt_group,\r
- VAPI_lkey_t* forced_key,\r
- Mr_sw_t** mrsw_pp\r
-)\r
-{\r
- HH_ret_t rc = HH_EAGAIN;\r
- VIP_common_ret_t vip_array_rc=VIP_EAGAIN;\r
- Mr_sw_t* mrsw_p= TMALLOC(Mr_sw_t);\r
- VIP_array_handle_t mpt_index= 0xFFFFFFFF;\r
- THH_mrwm_t mrwm = rs_p->mrwm;\r
- u_int32_t seg_start = EXTBUDDY_NULL;\r
- u_int8_t log2_mtt_seg_sz = mrwm->props.log2_mtt_seg_sz;\r
- /* avoid explict u_int64_t division ! */\r
- u_int32_t n_segs;\r
- MT_size_t seg_comp;\r
- u_int8_t log2_segs;\r
- \r
- if (mrsw_pp) {\r
- *mrsw_pp = NULL;\r
- }\r
-/*** warning C4242: '=' : conversion from 'VAPI_size_t' to 'MT_size_t', possible loss of data ***/\r
- seg_comp= (MT_size_t)(rs_p->n_pages >> log2_mtt_seg_sz);\r
- seg_comp= ((seg_comp << log2_mtt_seg_sz) != rs_p->n_pages) ? seg_comp + 1 : seg_comp;\r
- /*check that n_segs will not overflow 32 bits */\r
- log2_segs = ceil_log2(seg_comp);\r
- if (log2_segs >= (8*sizeof(n_segs))) return HH_EINVAL_PARAM;\r
- n_segs = 1 << log2_segs;\r
-\r
- MTL_DEBUG4(MT_FLFMT("%s: n_pages="SIZE_T_DFMT" n_segs=%u"), __func__,\r
- rs_p->n_pages, n_segs); \r
- \r
- if (!mrsw_p) {\r
- MTL_ERROR3(MT_FLFMT("%s: Failed allocating MR_sw_t for new memory region"),__func__);\r
- return HH_EAGAIN;\r
- }\r
- memset(mrsw_p,0,sizeof(Mr_sw_t));\r
- MTL_DEBUG4(MT_FLFMT("log2_mtt_seg_sz=%d"), log2_mtt_seg_sz);\r
- MTL_DEBUG4(MT_FLFMT("alloc_reg_pages: #pg="SIZE_T_FMT", #segs=0x%x, surp=0x%x, g=%d"),\r
- rs_p->n_pages, n_segs, mrwm->surplus_segs, tpt_group);\r
-\r
- if (reserve_mpt_entry(mrwm,tpt_group) != HH_OK) {\r
- MTL_ERROR4(MT_FLFMT("%s: Out of MPT entries"),__func__);\r
- goto failed_mpt_reserve;\r
- }\r
- \r
- if (!rs_p->mpt_entry.pa) {\r
- if ((rc= reserve_mtt_segs(mrwm,n_segs-1)) != HH_OK) {\r
- MTL_ERROR4(MT_FLFMT("%s: Out of MTT entries"),__func__);\r
- goto failed_mtt_reserve;\r
- }\r
- }\r
- \r
- if (forced_key) /* must be Internal! */\r
- {\r
- mpt_index= (*forced_key & MASK32(mrwm->props.log2_mpt_sz));\r
- if ((mpt_index >= mrwm->offset[MPT_int]) && \r
- (mpt_index < mrwm->offset[MPT_ext])) {\r
- vip_array_rc= \r
- VIP_array_insert2hndl(mrwm->mpt[tpt_group],mrsw_p,mpt_index-mrwm->offset[MPT_int]);\r
- } else {\r
- vip_array_rc= VIP_EINVAL_PARAM; /* given key is not available */\r
- }\r
- }\r
- else /* !forced_key */\r
- {\r
- vip_array_rc= VIP_array_insert(mrwm->mpt[tpt_group],mrsw_p,&mpt_index);\r
- mpt_index+= mrwm->offset[tpt_group];\r
- }\r
- \r
- if (vip_array_rc != VIP_OK) {\r
- MTL_ERROR3(MT_FLFMT("%s: Failed MPT entry allocation (%s)"),__func__,\r
- VAPI_strerror_sym(vip_array_rc));\r
- goto failed_vip_array;\r
- }\r
- \r
- \r
- if (!rs_p->mpt_entry.pa) {\r
- if (MOSAL_mutex_acq(&mrwm->extbuddy_lock, TRUE) != MT_OK) {\r
- rc= VIP_EINTR;\r
- goto failed_mutex;\r
- }\r
- seg_start = extbuddy_alloc(mrwm->xbuddy_tpt, log2_segs);\r
- if (seg_start != EXTBUDDY_NULL) {EXTBUDDY_ALLOC_MTT(seg_start,log2_segs);}\r
- MOSAL_mutex_rel(&mrwm->extbuddy_lock);\r
- if (seg_start == EXTBUDDY_NULL) {\r
- MTL_ERROR3(MT_FLFMT("%s: Failed allocation of %d MTT segment/s allocation"),__func__,\r
- log2_segs);\r
- rc= HH_EAGAIN;\r
- goto failed_extbuddy;\r
- }\r
- rs_p->seg_start = seg_start;\r
- }\r
- \r
- \r
- rs_p->mpt_index = mpt_index;\r
- /*in PMR, it acts the same, as long as it's not SHARED */\r
- rc = register_pages(rs_p,tpt_group,VAPI_MR); \r
- if (rc != HH_OK) {\r
- goto failed_register_pages;\r
- }\r
- \r
- /*saving the new MPT entry */\r
- /*in PMR, it acts the same, as long as it's not SHARED */\r
- rc = save_sw_context(rs_p, log2_segs,VAPI_MR,mrsw_p); \r
- if (rc != HH_OK) {\r
- MTL_ERROR1("failed save_sw_ctxt \n");\r
- goto failed_save_ctx;\r
- }\r
-\r
- if (mrsw_pp) {\r
- *mrsw_pp = mrsw_p;\r
- }\r
-\r
- return HH_OK;\r
-\r
- failed_save_ctx:\r
- THH_cmd_HW2SW_MPT(mrwm->cmd_if, mpt_index, NULL); /* reclaim MPT entry from HW */\r
- failed_register_pages:\r
- MOSAL_mutex_acq_ui(&mrwm->extbuddy_lock);\r
- extbuddy_free(mrwm->xbuddy_tpt, seg_start, log2_segs);\r
- EXTBUDDY_FREE_MTT(seg_start, log2_segs);\r
- MOSAL_mutex_rel(&mrwm->extbuddy_lock);\r
- failed_extbuddy:\r
- failed_mutex:\r
- VIP_array_erase(mrwm->mpt[tpt_group],mpt_index-mrwm->offset[tpt_group],NULL);\r
- failed_vip_array:\r
- if (!rs_p->mpt_entry.pa) {\r
- release_mtt_segs(mrwm,n_segs-1);\r
- }\r
- failed_mtt_reserve:\r
- release_mpt_entry(mrwm,tpt_group);\r
- failed_mpt_reserve:\r
- FREE(mrsw_p);\r
- return rc;\r
-} /* alloc_reg_pages */\r
-\r
-\r
-/************************************************************************/\r
-static void swinfo2mrinfo(const Mr_sw_t* swmr, HH_mr_info_t* hmr)\r
-{\r
- hmr->lkey = swmr->key;\r
- hmr->rkey = swmr->key;\r
- hmr->local_start = swmr->start;\r
- hmr->remote_start = swmr->start;\r
- hmr->local_size = swmr->shared_p->size;\r
- hmr->remote_size = swmr->shared_p->size;\r
- hmr->pd = swmr->pd;\r
- hmr->acl = swmr->acl;\r
-} /* swinfo2mrinfo */\r
-\r
-\r
-\r
-/************************************************************************/\r
-/* Handling THH_mrwm_register_internal(...) case \r
- * where physical buffers are given\r
- */\r
-static HH_ret_t bufs_register_internal(\r
- THH_internal_mr_t* mr_p,\r
- Reg_Segs_t* rs_p,\r
- VAPI_lkey_t* forced_key,\r
- Mr_sw_t** mrsw_pp\r
-)\r
-{\r
- HH_ret_t rc;\r
- MTL_DEBUG4(MT_FLFMT("bufs_register_internal"));\r
- rc = buf_lst_2_pages(mr_p->phys_buf_lst, mr_p->buf_sz_lst, (unsigned int)mr_p->num_bufs, \r
- mr_p->start, 0 /* no offset */,rs_p);\r
- MTL_DEBUG4(MT_FLFMT("rc=%d"), rc);\r
- if (rc == HH_OK)\r
- {\r
- rs_p->acl = VAPI_EN_LOCAL_WRITE;\r
- rc = alloc_reg_pages(rs_p, MPT_int, forced_key, mrsw_pp);\r
- }\r
- if (rs_p->phys_pages) FREE_PHYS_PAGES_ARRAY(rs_p);\r
- return rc;\r
-} /* bufs_register_internal */\r
-\r
-\r
-/************************************************************************/\r
-/* Handling THH_mrwm_register_internal(...) case \r
- * where physical buffers are not supplied and pages need to be locked\r
- */\r
-static HH_ret_t lock_register_internal(\r
- THH_internal_mr_t* mr_props_p,\r
- Reg_Segs_t* rs_p,\r
- VAPI_lkey_t* forced_key,\r
- Mr_sw_t **mrsw_pp\r
-)\r
-{\r
- MOSAL_iobuf_props_t iobuf_props;\r
- MOSAL_protection_ctx_t ctx;\r
- HH_ret_t rc = HH_ENOSYS;\r
- call_result_t mosal_rc;\r
-\r
- MTL_DEBUG4(MT_FLFMT("%s: start="U64_FMT" size="U64_FMT), __func__ ,\r
- mr_props_p->start, mr_props_p->size); \r
-\r
- /* Arrange for pages locking */\r
- determine_ctx(rs_p->mrwm, mr_props_p, &ctx);\r
-\r
-/*** warning C4242: 'function' : conversion from 'IB_virt_addr_t' to 'MT_virt_addr_t', possible loss of data ***/\r
-/*** warning C4242: 'function' : conversion from 'VAPI_size_t' to 'MT_size_t', possible loss of data ***/\r
- mosal_rc = MOSAL_iobuf_register((MT_virt_addr_t)mr_props_p->start, (MT_size_t)mr_props_p->size, ctx, \r
- MOSAL_PERM_READ | MOSAL_PERM_WRITE, &rs_p->iobuf, MOSAL_IOBUF_LNX_FLG_MARK_ALL_DONTCOPY);\r
- if (mosal_rc != MT_OK) {\r
- MTL_ERROR4(MT_FLFMT("MOSAL_iobuf_register: rc=%s"), mtl_strerror_sym(mosal_rc));\r
- return mosal_rc == MT_EAGAIN ? HH_EAGAIN : HH_EINVAL_VA;\r
- }\r
-\r
- if (MOSAL_iobuf_get_props(rs_p->iobuf,&iobuf_props) != MT_OK) {\r
- MTL_ERROR4(MT_FLFMT("Failed MOSAL_iobuf_get_props."));\r
- rc= HH_EINVAL;\r
- } else {\r
- rs_p->n_pages= iobuf_props.nr_pages;\r
-/*** warning C4242: '=' : conversion from 'MT_u_int_t' to 'u_int8_t', possible loss of data ***/\r
- rs_p->log2_page_size = (u_int8_t)iobuf_props.page_shift;\r
- rs_p->acl = VAPI_EN_LOCAL_WRITE;\r
- rc = alloc_reg_pages(rs_p, MPT_int, forced_key, mrsw_pp);\r
- }\r
-\r
- if ( rc != HH_OK ) {\r
- MOSAL_iobuf_deregister(rs_p->iobuf);\r
- rs_p->iobuf= NULL;\r
- }\r
-\r
- return rc;\r
-} /* lock_register_internal */\r
-\r
-\r
-/************************************************************************/\r
-static void internal_unlock(VIP_delay_unlock_t delay_unlock_obj, MOSAL_iobuf_t iobuf, MT_bool have_fatal)\r
-{\r
- MTL_DEBUG4(MT_FLFMT("%s: iobuf=0x%p have_fatal=%d"),__func__,iobuf,have_fatal);\r
- if ( iobuf ) {\r
- if (have_fatal) {\r
- VIP_delay_unlock_insert(delay_unlock_obj, iobuf);\r
- }\r
- else {\r
- MOSAL_iobuf_deregister(iobuf);\r
- }\r
- }\r
-} /* internal_unlock */\r
-\r
-\r
-\r
-/************************************************************************/\r
-/************************************************************************/\r
-/* interface functions */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_mrwm_create(\r
- THH_hob_t hob, /* IN */\r
- THH_mrwm_props_t* mrwm_props, /* IN */\r
- THH_mrwm_t* mrwm_p /* OUT */\r
-)\r
-{\r
- HH_ret_t rc = HH_EAGAIN;\r
- TMRWM_t* mrwm = TMALLOC(TMRWM_t);\r
- u_int32_t mtt_sz = 1ul << mrwm_props->log2_mtt_sz;\r
- int i;\r
- MT_bool ok = TRUE;\r
-\r
- MTL_TRACE1("{THH_mrwm_create: hob=%p\n", hob);\r
-\r
- if (mrwm) memset(mrwm,0,sizeof(TMRWM_t));\r
- ok = (mrwm && check_props(mrwm_props, mrwm) &&\r
- ((rc=THH_hob_get_cmd_if(hob, &mrwm->cmd_if)) == HH_OK) &&\r
- ((rc=THH_hob_get_uldm(hob, &mrwm->uldm)) == HH_OK));\r
-\r
- /* Key prefix arrays (for "persistant" storage) */\r
- if (ok) {rc = HH_EAGAIN;} /*reinitialize return code */\r
- ok= ok && ((mrwm->key_prefix[MPT_int]= \r
- TNVMALLOC(u_int16_t,mrwm->props.max_mem_reg_internal)) != NULL);\r
- ok= ok && ((mrwm->key_prefix[MPT_ext]= \r
- TNVMALLOC(u_int16_t,mrwm->props.max_mem_reg)) != NULL);\r
- ok= ok && ((mrwm->key_prefix[MPT_win]= \r
- TNVMALLOC(u_int16_t,mrwm->props.max_mem_win)) != NULL);\r
-\r
- /* we allocate mtt segmenst, each of 2^LOG2_SEG_SIZE entries */\r
- ok = ok && ((mrwm->xbuddy_tpt =\r
- extbuddy_create(mtt_sz >> mrwm->props.log2_mtt_seg_sz, 0)) != NULL);\r
- ok = ok && extbuddy_reserve(mrwm->xbuddy_tpt, 0, (1ul << mrwm->props.log2_rsvd_mtt_segs));\r
-\r
- ok = ok && \r
- ((rc= VIP_array_create_maxsize((u_int32_t)(mrwm->props.max_mem_reg_internal>>10),(u_int32_t)mrwm->props.max_mem_reg_internal,\r
- &mrwm->mpt[MPT_int])) == HH_OK);\r
- ok = ok && \r
- ((rc= VIP_array_create_maxsize((u_int32_t)(mrwm->props.max_mem_reg>>10),(u_int32_t)mrwm->props.max_mem_reg,\r
- &mrwm->mpt[MPT_ext])) == HH_OK);\r
- ok = ok && \r
- ((rc= VIP_array_create_maxsize((u_int32_t)(mrwm->props.max_mem_win>>10),(u_int32_t)mrwm->props.max_mem_win,\r
- &mrwm->mpt[MPT_win])) == HH_OK);\r
- \r
- if (ok) {\r
- mrwm->is_fmr_bits= TNMALLOC(u_int8_t,mrwm->props.max_mem_reg>>3);\r
- if (mrwm->is_fmr_bits == NULL) {\r
- rc = HH_EAGAIN;\r
- goto cleanup;\r
- }\r
- memset(mrwm->is_fmr_bits,0,sizeof(u_int8_t)*mrwm->props.max_mem_reg>>3);\r
- mrwm->hob = hob;\r
- /* divide MPT to 3 sections: 1) Internal region. 2) External region. 3) mem. windows. */\r
- mrwm->offset[MPT_int] = (1<<mrwm->props.log2_rsvd_mpts); \r
- mrwm->offset[MPT_ext] = (u_int32_t)(mrwm->offset[MPT_int]+mrwm_props->max_mem_reg_internal);\r
- mrwm->offset[MPT_win] = (u_int32_t)(mrwm->offset[MPT_ext]+mrwm_props->max_mem_reg);\r
- mrwm->max_mpt[MPT_int]= (u_int32_t)mrwm_props->max_mem_reg_internal;\r
- mrwm->max_mpt[MPT_ext]= (u_int32_t)mrwm_props->max_mem_reg;\r
- mrwm->max_mpt[MPT_win]= (u_int32_t)mrwm_props->max_mem_win;\r
- for (i= 0; i < MPT_N ; i++) {\r
- mrwm->usage_cnt[i]= 0;\r
- memset(mrwm->key_prefix[i],0,sizeof(u_int16_t)*mrwm->max_mpt[i]);\r
- }\r
- MOSAL_mutex_init(&mrwm->extbuddy_lock);\r
- MOSAL_spinlock_init(&mrwm->reserve_lock);\r
- MOSAL_spinlock_init(&mrwm->key_prefix_lock);\r
- *mrwm_p = mrwm;\r
- MTL_TRACE1("}THH_mrwm_create: mrwm=%p,rc=OK\n", *mrwm_p);\r
- return HH_OK;\r
- } \r
-\r
-cleanup:\r
- for (i= 0; i < MPT_N ; i++) {\r
- if (mrwm->mpt[i]) VIP_array_destroy(mrwm->mpt[i],NULL);\r
- if (mrwm->key_prefix[i]) VFREE(mrwm->key_prefix[i]);\r
- }\r
- if (mrwm->xbuddy_tpt) extbuddy_destroy(mrwm->xbuddy_tpt);\r
- IFFREE(mrwm);\r
- MTL_TRACE1("}THH_mrwm_create: mrwm=%p\n", *mrwm_p);\r
- logIfErr("THH_mrwm_create")\r
- return rc;\r
-} /* THH_mrwm_create */\r
-\r
-\r
-/************************************************************************/\r
-static void VIP_free_mw(void* p)\r
-{\r
- MTL_ERROR1(MT_FLFMT("found unreleased mw!!!!\n"));\r
-}\r
-\r
-\r
-HH_ret_t THH_mrwm_destroy(\r
- THH_mrwm_t mrwm, /* IN */\r
- MT_bool hca_failure /* IN */\r
-)\r
-{\r
- int i;\r
- VIP_common_ret_t ret=VIP_OK;\r
- VIP_array_handle_t hdl;\r
- VIP_array_obj_t obj;\r
-\r
- MTL_TRACE1("THH_mrwm_destroy{\n");\r
- for (i= 0; i < MPT_N ; i++) {\r
- if (i==MPT_int) {\r
- ret= VIP_array_get_first_handle(mrwm->mpt[i],&hdl,&obj);\r
- while (ret == VIP_OK) {\r
- MTL_ERROR1(MT_FLFMT("found unreleased internal mr!!!!\n"));\r
- if (!hca_failure)\r
- {\r
- THH_mrwm_deregister_mr(mrwm,((Mr_sw_t*)obj)->key);\r
- }else {\r
- internal_unlock(THH_hob_get_delay_unlock(mrwm->hob),((Mr_sw_t*)obj)->iobuf, TRUE);\r
- }\r
- ret= VIP_array_get_next_handle(mrwm->mpt[i],&hdl,&obj);\r
- }\r
- }\r
- \r
- if (i==MPT_ext) {\r
- ret= VIP_array_get_first_handle(mrwm->mpt[i],&hdl,&obj);\r
- while (ret == VIP_OK) {\r
- /* check if it's fmr or mr */\r
- u_int8_t offset_in_cell = hdl & 0x7;\r
- if ((mrwm->is_fmr_bits[hdl>>3] >> offset_in_cell) & 0x1) \r
- {\r
- MTL_ERROR1(MT_FLFMT("found unreleased fmr!!!!\n"));\r
- if (!hca_failure) {\r
- THH_mrwm_free_fmr(mrwm,((FMR_sw_info_t*)obj)->last_free_key);\r
- }\r
- \r
- }else \r
- {\r
- MTL_ERROR1(MT_FLFMT("found unreleased mr!!!!\n"));\r
- if (!hca_failure) {\r
- THH_mrwm_deregister_mr(mrwm,((Mr_sw_t*)obj)->key);\r
- }else{\r
- if (((Mr_sw_t*)obj)->shared_p->ref_count > 1) {\r
- \r
- ((Mr_sw_t*)obj)->shared_p->ref_count--;\r
- \r
- }else {\r
- /*free shared data structures */\r
- FREE(((Mr_sw_t*)obj)->shared_p);\r
- }\r
- }\r
- \r
- }\r
- ret= VIP_array_get_next_handle(mrwm->mpt[i],&hdl,&obj);\r
- }\r
- }\r
- \r
- if (i==MPT_win) {\r
- VIP_array_destroy(mrwm->mpt[i],VIP_free_mw); \r
- }else {\r
- VIP_array_destroy(mrwm->mpt[i],NULL);\r
- }\r
- VFREE(mrwm->key_prefix[i]);\r
- }\r
- FREE(mrwm->is_fmr_bits);\r
- MOSAL_mutex_free(&mrwm->extbuddy_lock);\r
- extbuddy_destroy(mrwm->xbuddy_tpt);\r
- FREE(mrwm);\r
-\r
- MTL_TRACE1("}THH_mrwm_destroy\n");\r
- return HH_OK;\r
-} /* THH_mrwm_destroy */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_mrwm_register_mr(\r
- THH_mrwm_t mrwm, /* IN */\r
- HH_mr_t* mr_props_p, /* IN */\r
- VAPI_lkey_t* lkey_p, /* OUT */\r
- IB_rkey_t* rkey_p /* OUT */\r
-)\r
-{\r
- HH_ret_t rc = HH_EINVAL;\r
- HH_tpt_t* tpt = &mr_props_p->tpt; /* just a shorthand */\r
- IB_virt_addr_t start = mr_props_p->start;\r
- u_int8_t page_shift;\r
- Reg_Segs_t reg_segs;\r
- MOSAL_iobuf_props_t iobuf_props;\r
-\r
- MTL_TRACE1("{THH_mrwm_register_mr: mrwm=%p\n", mrwm);\r
- reg_segs.mrwm = mrwm;\r
- reg_segs.acl = mr_props_p->acl;\r
- reg_segs.iobuf= NULL;\r
- props2mpt_entry(mr_props_p, ®_segs.mpt_entry);\r
- switch (tpt->tpt_type)\r
- {\r
- case HH_TPT_PAGE:\r
- page_shift = tpt->tpt.page_lst.page_shift;\r
- reg_segs.n_pages = ((start + mr_props_p->size - 1) >> page_shift) -\r
- (start >> page_shift) + 1;\r
- MTL_DEBUG4(MT_FLFMT("start="U64_FMT", size="U64_FMT", shift=%d, ne="\r
- SIZE_T_DFMT", np="SIZE_T_DFMT),\r
- (u_int64_t)start, (u_int64_t)mr_props_p->size, page_shift,\r
- tpt->num_entries, reg_segs.n_pages);\r
- if (tpt->num_entries != reg_segs.n_pages)\r
- {\r
- MTL_ERROR1(MT_FLFMT("mismatch: num_entries="SIZE_T_DFMT" != n_pages="SIZE_T_DFMT),\r
- tpt->num_entries, reg_segs.n_pages);\r
- }\r
- if (tpt->num_entries >= reg_segs.n_pages)\r
- {\r
- if (tpt->num_entries > reg_segs.n_pages)\r
- {\r
- MTL_ERROR1(MT_FLFMT("Warning: Extra tpt entries will be ignored"));\r
- }\r
- reg_segs.phys_pages = tpt->tpt.page_lst.phys_page_lst;\r
- reg_segs.log2_page_size = page_shift;\r
- rc = alloc_reg_pages(®_segs, MPT_ext, NULL, NULL);\r
- }\r
- break;\r
- \r
- case HH_TPT_BUF:\r
- if ((mr_props_p->tpt.num_entries == 1) \r
- && (mr_props_p->tpt.tpt.buf_lst.phys_buf_lst[0] == mr_props_p->start))\r
- {\r
- /* no translation needed */\r
- reg_segs.mpt_entry.pa = TRUE;\r
- reg_segs.n_pages = 1;\r
- reg_segs.seg_start= 0;\r
- reg_segs.phys_pages= NULL;\r
- reg_segs.log2_page_size = TAVOR_LOG_MPT_PG_SZ_SHIFT;\r
- rc= HH_OK;\r
- }else {\r
- rc = tpt_buf_lst_2_pages(mr_props_p, ®_segs);\r
- }\r
- if (rc == HH_OK)\r
- {\r
- rc = alloc_reg_pages(®_segs, MPT_ext, NULL, NULL);\r
- if (reg_segs.phys_pages != NULL) FREE_PHYS_PAGES_ARRAY(®_segs);\r
- }\r
- break;\r
- \r
- case HH_TPT_IOBUF:\r
- reg_segs.iobuf= tpt->tpt.iobuf;\r
- if (MOSAL_iobuf_get_props(reg_segs.iobuf,&iobuf_props) != MT_OK) {\r
- MTL_ERROR4(MT_FLFMT("Failed MOSAL_iobuf_get_props."));\r
- rc= HH_EINVAL;\r
- break;\r
- }\r
- reg_segs.n_pages= iobuf_props.nr_pages;\r
-/*** warning C4242: '=' : conversion from 'MT_u_int_t' to 'u_int8_t', possible loss of data ***/\r
- reg_segs.log2_page_size = (u_int8_t)iobuf_props.page_shift;\r
- rc = alloc_reg_pages(®_segs, MPT_ext, NULL, NULL);\r
- break;\r
- \r
- default:\r
- MTL_ERROR1(MT_FLFMT("bad tpt_type=%d"), tpt->tpt_type);\r
- }\r
- if (rc == HH_OK)\r
- {\r
- *lkey_p = reg_segs.key;\r
- *rkey_p = reg_segs.key;\r
- }\r
- MTL_TRACE1("}THH_mrwm_register_mr: lkey=0x%x\n", *lkey_p);\r
- logIfErr("THH_mrwm_register_mr")\r
- return rc;\r
-} /* THH_mrwm_register_mr */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_mrwm_register_internal(\r
- THH_mrwm_t mrwm, /* IN */\r
- THH_internal_mr_t* mr_props_p, /* IN */\r
- VAPI_lkey_t* lkey_p /* OUT */\r
-)\r
-{\r
- HH_ret_t rc = HH_EAGAIN;\r
- Reg_Segs_t reg_segs;\r
- VAPI_lkey_t* forced_key;\r
- Mr_sw_t* mrsw_p = NULL;\r
-\r
- MTL_TRACE1("{THH_mrwm_register_internal: mrwm=%p, force=%d, nbufs="SIZE_T_FMT"\n",\r
- mrwm, mr_props_p->force_memkey, mr_props_p->num_bufs);\r
- reg_segs.mrwm = mrwm;\r
- internal_props2mpt_entry(mr_props_p, ®_segs.mpt_entry);\r
- reg_segs.phys_pages = NULL;\r
- reg_segs.iobuf= NULL;\r
- forced_key = (mr_props_p->force_memkey ? &mr_props_p->memkey : NULL);\r
- if (mr_props_p->num_bufs != 0)\r
- { /* physical buffers supplied */ \r
- rc = bufs_register_internal(mr_props_p, ®_segs, forced_key, &mrsw_p);\r
- }\r
- else\r
- {\r
- rc = lock_register_internal(mr_props_p, ®_segs, forced_key, &mrsw_p);\r
- }\r
- if (rc == HH_OK)\r
- {\r
- MOSAL_mutex_init(&mrsw_p->modify_mtx);\r
- *lkey_p = reg_segs.key;\r
- }\r
- MTL_TRACE1("}THH_mrwm_register_internal: lkey=0x%x\n", *lkey_p);\r
- logIfErr("THH_mrwm_register_internal")\r
- return rc;\r
-} /* THH_mrwm_register_internal */\r
-\r
-/************************************************************************/\r
-static HH_ret_t modify_reg_pages(\r
- Reg_Segs_t* rs_p,\r
- Mr_sw_t* mrsw_p\r
-)\r
-{\r
- HH_ret_t rc = HH_EAGAIN;\r
- THH_mrwm_t mrwm = rs_p->mrwm;\r
- u_int32_t seg_start = EXTBUDDY_NULL;\r
- u_int8_t log2_mtt_seg_sz = mrwm->props.log2_mtt_seg_sz;\r
- /* avoid explict u_int64_t division ! */\r
- u_int32_t n_segs;\r
- VAPI_size_t seg_comp;\r
- u_int8_t log2_segs;\r
- VAPI_phy_addr_t mtt_seg_adr;\r
- THH_cmd_status_t cmd_rc;\r
- \r
- if (!mrsw_p) {\r
- MTL_ERROR3(MT_FLFMT("%s: current memory region object is NULL"),__func__);\r
- return HH_EINVAL;\r
- }\r
- \r
- seg_comp= rs_p->n_pages >> log2_mtt_seg_sz;\r
- seg_comp= ((seg_comp << log2_mtt_seg_sz) != rs_p->n_pages) ? seg_comp + 1 : seg_comp;\r
- /*check that n_segs will not overflow 32 bits */\r
- log2_segs = ceil_log2(seg_comp);\r
- if (log2_segs >= (8*sizeof(n_segs))) return HH_EINVAL_PARAM;\r
- n_segs = 1 << log2_segs;\r
-\r
- MTL_DEBUG4(MT_FLFMT("%s: n_pages="SIZE_T_DFMT" n_segs=%u"), __func__,\r
- rs_p->n_pages, n_segs); \r
- \r
- MTL_DEBUG4(MT_FLFMT("log2_mtt_seg_sz=%d"), log2_mtt_seg_sz);\r
- \r
- /* always need to allocate new MTT segments, since we may be using modify option 2, and in this\r
- * case, the current MTT segments continue to be active -- they may not be touched */\r
-\r
- if ((rc= reserve_mtt_segs(mrwm,n_segs-1)) != HH_OK) {\r
- MTL_ERROR4(MT_FLFMT("%s: Out of MTT entries"),__func__);\r
- return rc;\r
- }\r
- \r
- if (MOSAL_mutex_acq(&mrwm->extbuddy_lock, TRUE) != MT_OK) {\r
- rc= VIP_EINTR;\r
- goto failed_mutex;\r
- }\r
- seg_start = extbuddy_alloc(mrwm->xbuddy_tpt, log2_segs);\r
- if (seg_start != EXTBUDDY_NULL) {EXTBUDDY_ALLOC_MTT(seg_start,log2_segs);}\r
- MOSAL_mutex_rel(&mrwm->extbuddy_lock);\r
- if (seg_start == EXTBUDDY_NULL) {\r
- MTL_ERROR3(MT_FLFMT("%s: Failed allocation of %d MTT segment/s allocation"),__func__,\r
- log2_segs);\r
- rc= HH_EAGAIN;\r
- goto failed_extbuddy;\r
- }\r
- rs_p->seg_start = seg_start;\r
- \r
- mtt_seg_adr = mrwm->props.mtt_base |\r
- (rs_p->seg_start << (log2_mtt_seg_sz + MTT_LOG_MTT_ENTRY_SIZE));\r
- rc= mtt_writes_iobuf(mrwm->cmd_if, rs_p->iobuf, mtt_seg_adr, rs_p->n_pages);\r
- if (rc != HH_OK) {\r
- MTL_ERROR3(MT_FLFMT("%s: Failed mtt_writes_iobuf (%d: %s) of npages = "SIZE_T_DFMT ", seg addr="U64_FMT),\r
- __func__,rc, HH_strerror_sym(rc),rs_p->n_pages,mtt_seg_adr );\r
- goto failed_register_pages;\r
- }\r
- \r
- /* issue command to update the MPT entry in Tavor */\r
- rs_p->mpt_entry.mtt_seg_adr = mtt_seg_adr;\r
- cmd_rc = THH_cmd_MODIFY_MPT(mrwm->cmd_if, rs_p->mpt_index, &rs_p->mpt_entry, FALSE);\r
- MTL_DEBUG4(MT_FLFMT("THH_cmd_MODIFY_MPT: cmd_rc=%d"), cmd_rc);\r
- if (cmd_rc != THH_CMD_STAT_OK) {\r
- MTL_ERROR1(MT_FLFMT("THH_cmd_MODIFY_MPT failed (%d) \n"),cmd_rc);\r
- rc = (CMDRC2HH_ND(cmd_rc));\r
- goto failed_modify_mpt;\r
- }\r
-\r
- /* save new mpt info in sw context */\r
- MOSAL_spinlock_lock(&mrsw_p->shared_p->ref_lock);\r
- mrsw_p->shared_p->size = rs_p->mpt_entry.reg_wnd_len;\r
- mrsw_p->shared_p->seg_start = rs_p->seg_start;\r
- mrsw_p->shared_p->log2_segs = log2_segs;\r
- MOSAL_spinlock_unlock(&mrsw_p->shared_p->ref_lock);\r
-\r
- return HH_OK;\r
-\r
- failed_modify_mpt:\r
- failed_register_pages:\r
- MOSAL_mutex_acq_ui(&mrwm->extbuddy_lock);\r
- extbuddy_free(mrwm->xbuddy_tpt, seg_start, log2_segs);\r
- EXTBUDDY_FREE_MTT(seg_start, log2_segs);\r
- MOSAL_mutex_rel(&mrwm->extbuddy_lock);\r
- failed_extbuddy:\r
- failed_mutex:\r
- release_mtt_segs(mrwm,n_segs-1);\r
- return rc;\r
-} /* alloc_reg_pages */\r
-/************************************************************************/\r
-/* Handling THH_mrwm_modify_internal(...) case \r
- * where physical buffers are not supplied and pages need to be locked\r
- */\r
-static HH_ret_t lock_modify_internal(\r
- THH_internal_mr_t* mr_props_p,\r
- Reg_Segs_t* rs_p,\r
- Mr_sw_t *mrsw_p\r
-)\r
-{\r
- MOSAL_iobuf_props_t iobuf_props;\r
- HH_ret_t rc = HH_ENOSYS;\r
- call_result_t mosal_rc;\r
-\r
- MTL_DEBUG4(MT_FLFMT("%s: start="U64_FMT" size="U64_FMT), __func__ ,\r
- mr_props_p->start, mr_props_p->size); \r
-\r
- mosal_rc = MOSAL_iobuf_register((MT_virt_addr_t)mr_props_p->start, (MT_size_t)mr_props_p->size, mr_props_p->vm_ctx, \r
- MOSAL_PERM_READ | MOSAL_PERM_WRITE, &rs_p->iobuf, \r
- MOSAL_IOBUF_LNX_FLG_MARK_ALL_DONTCOPY);\r
- if (mosal_rc != MT_OK) {\r
- MTL_ERROR4(MT_FLFMT("MOSAL_iobuf_register: rc=%s"), mtl_strerror_sym(mosal_rc));\r
- return mosal_rc == MT_EAGAIN ? HH_EAGAIN : HH_EINVAL_VA;\r
- }\r
-\r
- if (MOSAL_iobuf_get_props(rs_p->iobuf,&iobuf_props) != MT_OK) {\r
- MTL_ERROR4(MT_FLFMT("Failed MOSAL_iobuf_get_props."));\r
- rc= HH_EINVAL;\r
- } else {\r
- rs_p->n_pages= iobuf_props.nr_pages;\r
- rs_p->log2_page_size = (u_int8_t)iobuf_props.page_shift;\r
- rs_p->acl = VAPI_EN_LOCAL_WRITE;\r
- rc = modify_reg_pages(rs_p, mrsw_p);\r
- }\r
-\r
- if ( rc != HH_OK ) {\r
- MOSAL_iobuf_deregister(rs_p->iobuf);\r
- rs_p->iobuf= NULL;\r
- } else {\r
- mrsw_p->iobuf = rs_p->iobuf;\r
- }\r
-\r
- return rc;\r
-} /* lock_modify_internal */\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_mrwm_modify_internal(\r
- THH_mrwm_t mrwm, /* IN */\r
- VAPI_lkey_t lkey, /* IN */\r
- THH_internal_mr_t* mr_props_p, /* IN */\r
- THH_mrwm_modify_flags_t flags /* IN */\r
-)\r
-{\r
- HH_ret_t rc = HH_OK;\r
- u_int32_t mpt_index = lkey & ((1ul << mrwm->props.log2_mpt_sz) - 1);\r
- VIP_common_ret_t vip_rc;\r
- Reg_Segs_t reg_segs;\r
- u_int8_t freed_log2_segs;\r
- u_int32_t freed_seg_start;\r
- mpt_segment_t mpt_seg;\r
- VIP_array_obj_t vip_array_obj;\r
- Mr_sw_t *mrsw_p;\r
- MOSAL_iobuf_t freed_iobuf; /* for internal regions */\r
-\r
-\r
- if (flags != THH_MRWM_MODIFY_FLAGS_TRANSLATION) {\r
- MTL_ERROR4(MT_FLFMT("%s: Invalid flags set (0x%X) for internal mr modify"),__func__,flags);\r
- return HH_ENOSYS;\r
- }\r
-\r
- mpt_seg= get_mpt_seg(mrwm,mpt_index);\r
- if (mpt_seg != MPT_int) {\r
- MTL_ERROR4(MT_FLFMT("%s: Invalid L-key (0x%X) for (internal) memory region"),__func__,lkey);\r
- return HH_EINVAL;\r
- }\r
-\r
- if (mr_props_p->num_bufs != 0) {\r
- MTL_ERROR4(MT_FLFMT("%s: Providing phys pages for internal mr modify. Currently not supported"),__func__);\r
- return HH_ENOSYS;\r
- }\r
- \r
- if (mr_props_p->force_memkey != FALSE) {\r
- MTL_ERROR4(MT_FLFMT("%s: Forcing memory key for internal mr modify."),__func__);\r
- return HH_EINVAL;\r
- }\r
-\r
- vip_rc= VIP_array_find_hold(mrwm->mpt[mpt_seg],mpt_index-mrwm->offset[mpt_seg],&vip_array_obj); \r
- if (vip_rc != VIP_OK) {\r
- MTL_ERROR4(MT_FLFMT("%s: Failed removing L-key (0x%X) for memory region (%s)"),__func__,\r
- lkey,VAPI_strerror_sym(vip_rc));\r
- return vip_rc == VIP_EINVAL_HNDL ? HH_EINVAL : HH_EBUSY;\r
- }\r
- mrsw_p= (Mr_sw_t*)vip_array_obj;\r
-\r
- /* Prevent another resize MR operation while this one is in progress */\r
- if (MOSAL_mutex_acq(&mrsw_p->modify_mtx, TRUE) != MT_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: Could not acquire mutex -- received signal. returning"), __func__);\r
- VIP_array_find_release(mrwm->mpt[mpt_seg],mpt_index-mrwm->offset[mpt_seg]);\r
- rc = HH_EINTR;\r
- }\r
-\r
- /* get pd and protection context of current mr */\r
- mr_props_p->pd = mrsw_p->pd;\r
- rc = THH_uldm_get_protection_ctx( mrwm->uldm, mr_props_p->pd, &mr_props_p->vm_ctx);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: Could not get protection context for internal mr modify."),__func__);\r
- goto done;\r
- }\r
-\r
- freed_iobuf = mrsw_p->iobuf;\r
- freed_log2_segs = mrsw_p->shared_p->log2_segs;\r
- freed_seg_start = mrsw_p->shared_p->seg_start;\r
-\r
- memset(®_segs,0,sizeof(Reg_Segs_t));\r
- reg_segs.mrwm = mrwm;\r
- reg_segs.phys_pages = NULL;\r
- reg_segs.iobuf= NULL;\r
- reg_segs.mpt_index = mpt_index;\r
- reg_segs.mpt_entry.reg_wnd_len = mr_props_p->size;\r
- rc = lock_modify_internal(mr_props_p,®_segs,mrsw_p);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: lock_modify_internal failed (%d: %s)"),__func__,\r
- rc, HH_strerror_sym(rc));\r
- goto done;\r
- }\r
- \r
- /* release previous iobuf */\r
- MOSAL_iobuf_deregister(freed_iobuf);\r
-\r
- /* release previous MTT entries */\r
- MOSAL_mutex_acq_ui(&mrwm->extbuddy_lock);\r
- extbuddy_free(mrwm->xbuddy_tpt, freed_seg_start, freed_log2_segs);\r
- EXTBUDDY_FREE_MTT(freed_seg_start, freed_log2_segs);\r
- MOSAL_mutex_rel(&mrwm->extbuddy_lock);\r
- release_mtt_segs(mrwm, (1 << freed_log2_segs) - 1);\r
-\r
-done:\r
- MOSAL_mutex_rel(&mrsw_p->modify_mtx);\r
- VIP_array_find_release(mrwm->mpt[mpt_seg],mpt_index-mrwm->offset[mpt_seg]);\r
- return rc;\r
-\r
-}\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_mrwm_register_smr(\r
- THH_mrwm_t mrwm, /* IN */\r
- HH_smr_t* smr_props_p, /* IN */\r
- VAPI_lkey_t* lkey_p, /* OUT */\r
- IB_rkey_t* rkey_p /* OUT */\r
-)\r
-{\r
- HH_ret_t rc = HH_EINVAL;\r
- Reg_Segs_t reg_segs;\r
- VIP_common_ret_t vip_rc;\r
- VIP_array_obj_t vip_obj;\r
- Mr_sw_t *mrsw_p,*shared_mr_p;\r
- VIP_array_handle_t mr_hndl;\r
- u_int32_t shared_index; /*index of region shared with*/\r
- \r
-\r
- MTL_TRACE1("{THH_mrwm_register_smr: mrwm=%p\n", mrwm);\r
- /* prepare inputs */\r
- shared_index = smr_props_p->lkey & ((1ul << mrwm->props.log2_mpt_sz) - 1);\r
- if ((shared_index < mrwm->offset[MPT_ext]) || (shared_index >= mrwm->offset[MPT_win])) {\r
- MTL_ERROR4(MT_FLFMT("%s: Got Lkey (0x%X) invalid for (ext.) memory region"),__func__,\r
- smr_props_p->lkey);\r
- return HH_EINVAL;\r
- }\r
- shared_index-= mrwm->offset[MPT_ext];\r
- /* Hold shared MR while sharing in progress (retain properties until this function done) */\r
- vip_rc= VIP_array_find_hold(mrwm->mpt[MPT_ext],shared_index,&vip_obj);\r
- if (vip_rc != VIP_OK) {\r
- MTL_ERROR4(MT_FLFMT("%s: Failed to find (ext.) region with Lkey=0x%X"),__func__,\r
- smr_props_p->lkey);\r
- return HH_EINVAL;\r
- }\r
- shared_mr_p= (Mr_sw_t*)vip_obj;\r
- rc = smr_props2mpt_entry(mrwm,smr_props_p,®_segs.mpt_entry);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1("failed smr_props2mpt_entry \n");\r
- goto failed_props2mpt;\r
- }\r
-\r
-\r
- mrsw_p= TMALLOC(Mr_sw_t);\r
- if (mrsw_p == NULL) {\r
- MTL_ERROR4(MT_FLFMT("%s: Failed allocation for MR SW context memory"),__func__);\r
- rc= HH_EAGAIN;\r
- goto failed_malloc;\r
- }\r
- memset(mrsw_p, 0, sizeof(Mr_sw_t));\r
-\r
- reg_segs.acl = smr_props_p->acl;\r
- reg_segs.iobuf= NULL;\r
- /*allocate new mpt idx */\r
- if (reserve_mpt_entry(mrwm,MPT_ext) != HH_OK) {\r
- MTL_ERROR4(MT_FLFMT("%s: No more free MPT entry for external regions"),__func__);\r
- rc= HH_EAGAIN;\r
- goto failed_reserve_mpt;\r
- }\r
- vip_rc= VIP_array_insert(mrwm->mpt[MPT_ext],mrsw_p,&mr_hndl);\r
- if (vip_rc != VIP_OK)\r
- {\r
- MTL_ERROR1("register_smr: ERROR: failed allocating new mpt idx \n"); \r
- rc= HH_EAGAIN;\r
- goto failed_array_insert;\r
- }\r
-\r
-\r
- reg_segs.mpt_index = mrwm->offset[MPT_ext] + mr_hndl; \r
- \r
-\r
- /*taking MTT seg start from the mr we're sharing with*/\r
- reg_segs.seg_start = shared_mr_p->shared_p->seg_start;\r
- reg_segs.log2_page_size = shared_mr_p->shared_p->page_shift;\r
- reg_segs.mrwm = mrwm;\r
-\r
-\r
- rc = register_pages(®_segs,MPT_ext,VAPI_MSHAR); \r
- if (rc != HH_OK) {\r
- MTL_ERROR1("register_smr: failed register_pages \n");\r
- goto failed_register;\r
- }\r
- \r
- /*pointing to the original allocated struct */\r
- mrsw_p->shared_p = shared_mr_p->shared_p;\r
- /*saving the new MPT entry ctx*/\r
- rc = save_sw_context(®_segs,0,VAPI_MSHAR,mrsw_p);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1("%s: unexpected error !!! failed save_sw_context \n",__func__);\r
- goto failed_save;\r
- }\r
- VIP_array_find_release(mrwm->mpt[MPT_ext],shared_index);\r
- \r
- *lkey_p = reg_segs.key;\r
- *rkey_p = reg_segs.key;\r
- return HH_OK;\r
-\r
- failed_save:\r
- THH_cmd_HW2SW_MPT(mrwm->cmd_if, reg_segs.mpt_index, NULL);\r
- failed_register:\r
- VIP_array_erase(mrwm->mpt[MPT_ext],mr_hndl,NULL);\r
- failed_array_insert:\r
- release_mpt_entry(mrwm,MPT_ext);\r
- failed_reserve_mpt:\r
- FREE(mrsw_p);\r
- failed_malloc:\r
- failed_props2mpt:\r
- VIP_array_find_release(mrwm->mpt[MPT_ext],shared_index);\r
- return rc;\r
-\r
-} /* THH_mrwm_register_smr */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_mrwm_reregister_mr(\r
- THH_mrwm_t mrwm, /* IN */\r
- VAPI_lkey_t lkey,\r
- VAPI_mr_change_t change_mask, /* IN */\r
- HH_mr_t* mr_props_p, /* IN */\r
- VAPI_lkey_t* lkey_p, /* OUT */\r
- IB_rkey_t* rkey_p /* OUT */\r
- )\r
-{\r
- HH_ret_t rc = HH_OK;\r
- u_int32_t mpt_index = lkey & ((1ul << mrwm->props.log2_mpt_sz) - 1);\r
- VIP_common_ret_t vip_rc;\r
- THH_cmd_status_t cmd_rc;\r
- Reg_Segs_t reg_segs;\r
- u_int8_t log2_segs;\r
- mpt_segment_t mpt_seg;\r
- VIP_array_obj_t vip_array_obj;\r
- Mr_sw_t *mrsw_p;\r
-\r
- memset(®_segs,0,sizeof(Reg_Segs_t));\r
- reg_segs.mrwm = mrwm;\r
- reg_segs.iobuf= NULL; /* external */\r
- reg_segs.mpt_index = mpt_index;\r
-\r
- mpt_seg= get_mpt_seg(mrwm,mpt_index);\r
- if (mpt_seg != MPT_ext) {\r
- MTL_ERROR4(MT_FLFMT("%s: Invalid L-key (0x%X) for (external) memory region"),__func__,lkey);\r
- return HH_EINVAL;\r
- }\r
- /* hide entry while changing translation (i.e. no other operation allowed - mostly sharing) */\r
- vip_rc= VIP_array_erase_prepare(mrwm->mpt[mpt_seg],mpt_index-mrwm->offset[mpt_seg],&vip_array_obj);\r
- if (vip_rc != VIP_OK) {\r
- MTL_ERROR4(MT_FLFMT("%s: Failed removing L-key (0x%X) for memory region (%s)"),__func__,\r
- lkey,VAPI_strerror_sym(vip_rc));\r
- return vip_rc == VIP_EINVAL_HNDL ? HH_EINVAL : HH_EBUSY;\r
- }\r
- mrsw_p= (Mr_sw_t*)vip_array_obj;\r
-\r
- MTL_DEBUG1(MT_FLFMT("before query orig mr \n"));\r
- /* query original mpt entry */\r
- cmd_rc = THH_cmd_HW2SW_MPT(mrwm->cmd_if, mpt_index,®_segs.mpt_entry);\r
- if (cmd_rc != THH_CMD_STAT_OK) {\r
- switch(cmd_rc) {\r
- case THH_CMD_STAT_REG_BOUND:\r
- MTL_ERROR1(MT_FLFMT("There are mw bounded to this region \n"));\r
- VIP_array_erase_undo(mrwm->mpt[MPT_ext],mpt_index - mrwm->offset[MPT_ext]);\r
- return HH_EBUSY;\r
- default:\r
- rc = HH_EFATAL;\r
- }\r
- goto failure_release;\r
- }\r
- rc = HH_OK;\r
- \r
- /* make new mem key */\r
- /*reg_segs.mpt_entry.mem_key = make_key(mrwm,mpt_seg,reg_segs.mpt_index);*/\r
- /* CHANGE: We retain the same memory key - some ULPs don't like that we replace the Rkey */\r
- \r
- /* fill changed attributes in sw mpt entry */\r
- if (change_mask & VAPI_MR_CHANGE_ACL) {\r
- reg_segs.mpt_entry.lw = (mr_props_p->acl & VAPI_EN_LOCAL_WRITE ? TRUE : FALSE);\r
- reg_segs.mpt_entry.rr = (mr_props_p->acl & VAPI_EN_REMOTE_READ ? TRUE : FALSE);\r
- reg_segs.mpt_entry.rw = (mr_props_p->acl & VAPI_EN_REMOTE_WRITE ? TRUE : FALSE);\r
- reg_segs.mpt_entry.a = (mr_props_p->acl & VAPI_EN_REMOTE_ATOM ? TRUE : FALSE);\r
- reg_segs.mpt_entry.eb = (mr_props_p->acl & VAPI_EN_MEMREG_BIND ? TRUE : FALSE);\r
- reg_segs.acl = mr_props_p->acl;\r
- } \r
-\r
- if (change_mask & VAPI_MR_CHANGE_PD) {\r
- reg_segs.mpt_entry.pd = mr_props_p->pd;\r
- }\r
-\r
- if (change_mask & VAPI_MR_CHANGE_TRANS) {\r
-\r
- MTL_DEBUG1(MT_FLFMT("changed translation \n"));\r
- rc = change_translation(®_segs,mr_props_p,mrsw_p,&log2_segs);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("change translation failed \n"));\r
- goto failure_release;\r
- }\r
- reg_segs.mpt_entry.page_size = reg_segs.log2_page_size - TAVOR_LOG_MPT_PG_SZ_SHIFT;\r
- reg_segs.mpt_entry.start_address = mr_props_p->start;\r
- reg_segs.mpt_entry.reg_wnd_len = mr_props_p->size;\r
- \r
- /* write the new MTT's */\r
- MTL_DEBUG3(MT_FLFMT("before mtt writes \n"));\r
- if (reg_segs.iobuf != NULL) {\r
- rc= mtt_writes_iobuf(mrwm->cmd_if, reg_segs.iobuf, reg_segs.mpt_entry.mtt_seg_adr, \r
- reg_segs.n_pages);\r
- } else {\r
- rc = mtt_writes(mrwm->cmd_if, reg_segs.phys_pages,reg_segs.mpt_entry.mtt_seg_adr,reg_segs.n_pages);\r
- }\r
- if (rc!= HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("mtt_writes(_iobuf) failed (%s)\n"),HH_strerror_sym(rc));\r
- goto failure_release;\r
- }\r
- MTL_DEBUG4(MT_FLFMT("mtt_writes: rc=%d"), rc);\r
- }\r
- \r
-\r
- /* write new MPT to HW */\r
- cmd_rc = THH_cmd_SW2HW_MPT(reg_segs.mrwm->cmd_if, reg_segs.mpt_index, ®_segs.mpt_entry);\r
- MTL_DEBUG4(MT_FLFMT("SW2HW_MPT: cmd_rc=%d"), cmd_rc);\r
- rc = (CMDRC2HH_ND(cmd_rc));\r
- if (rc != HH_OK) {\r
- goto failure_release;\r
- }\r
-\r
- /* save the new MPT locally */\r
- reg_segs.key = reg_segs.mpt_entry.mem_key;\r
- \r
- /* save the new attributes locally */\r
- mrsw_p->key = reg_segs.key;\r
-\r
- if (change_mask & VAPI_MR_CHANGE_ACL) {\r
- mrsw_p->acl = reg_segs.acl; \r
- } \r
-\r
- if (change_mask & VAPI_MR_CHANGE_PD) {\r
- mrsw_p->pd = reg_segs.mpt_entry.pd ;\r
- }\r
-\r
- if (change_mask & VAPI_MR_CHANGE_TRANS) {\r
- mrsw_p->start = reg_segs.mpt_entry.start_address;\r
- if (mrsw_p->shared_p == NULL) {\r
- mrsw_p->shared_p = (Shared_data_t*)MALLOC(sizeof(Shared_data_t));\r
- if (mrsw_p->shared_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("failed allocating memory \n"));\r
- rc=HH_EAGAIN; \r
- goto failure_release;\r
- }\r
- }\r
- mrsw_p->shared_p->size = reg_segs.mpt_entry.reg_wnd_len;\r
- mrsw_p->shared_p->seg_start = reg_segs.seg_start;\r
- mrsw_p->shared_p->log2_segs = log2_segs;\r
- mrsw_p->shared_p->page_shift = reg_segs.log2_page_size;\r
- mrsw_p->shared_p->ref_count = 1;\r
- MOSAL_spinlock_init(&mrsw_p->shared_p->ref_lock);\r
- if ((mr_props_p->tpt.tpt_type == HH_TPT_BUF) && (reg_segs.phys_pages != NULL)) \r
- FREE_PHYS_PAGES_ARRAY(®_segs);\r
- }\r
- \r
- VIP_array_erase_undo(mrwm->mpt[MPT_ext],mpt_index - mrwm->offset[MPT_ext]);\r
- *lkey_p = reg_segs.mpt_entry.mem_key;\r
- *rkey_p = reg_segs.mpt_entry.mem_key;\r
- logIfErr("THH_mrwm_reregister_mr")\r
- return rc;\r
-\r
- failure_release:\r
- /* Invalidate entry after failure - as requested by IB */\r
- if (mrsw_p->shared_p) { /* still has MTTs to release */\r
- release_shared_mtts(mrwm,mrsw_p);\r
- }\r
- if ((mr_props_p->tpt.tpt_type == HH_TPT_BUF) && (reg_segs.phys_pages != NULL)) \r
- FREE_PHYS_PAGES_ARRAY(®_segs);\r
- VIP_array_erase_done(mrwm->mpt[MPT_ext],mpt_index - mrwm->offset[MPT_ext],NULL);\r
- release_mpt_entry(mrwm,MPT_ext);\r
- FREE(mrsw_p);\r
- return rc;\r
-} /* THH_mrwm_reregister_mr */\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_mrwm_query_mr(\r
- THH_mrwm_t mrwm, /* IN */\r
- VAPI_lkey_t lkey, /* IN */\r
- HH_mr_info_t* mr_info_p /* OUT */\r
-)\r
-{\r
- VIP_common_ret_t vip_rc;\r
- u_int32_t mpt_index = lkey & ((1ul << mrwm->props.log2_mpt_sz) - 1);\r
- mpt_segment_t mpt_seg;\r
- VIP_array_obj_t vip_obj;\r
- Mr_sw_t *mrsw_p;\r
-\r
- mpt_seg= get_mpt_seg(mrwm,mpt_index);\r
- if ((mpt_seg != MPT_ext) && (mpt_seg != MPT_int)){\r
- MTL_ERROR4(MT_FLFMT("%s: Invalid L-key (0x%X) for memory region"),__func__,lkey);\r
- return HH_EINVAL;\r
- }\r
- vip_rc= VIP_array_find_hold(mrwm->mpt[mpt_seg],mpt_index-mrwm->offset[mpt_seg],&vip_obj);\r
- if (vip_rc != VIP_OK) {\r
- MTL_ERROR4(MT_FLFMT("%s: Failed finding a memory region with L-key 0x%X (%s)"),__func__,\r
- lkey,VAPI_strerror_sym(vip_rc));\r
- return (HH_ret_t)vip_rc;\r
- }\r
- mrsw_p= (Mr_sw_t*)vip_obj;\r
- swinfo2mrinfo(mrsw_p, mr_info_p);\r
- VIP_array_find_release(mrwm->mpt[mpt_seg],mpt_index-mrwm->offset[mpt_seg]);\r
- MTL_TRACE1("}THH_mrwm_query_mr\n");\r
- return HH_OK;\r
-} /* THH_mrwm_query_mr */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_mrwm_deregister_mr(\r
- THH_mrwm_t mrwm, /* IN */\r
- VAPI_lkey_t lkey /* IN */\r
-)\r
-{\r
- HH_ret_t rc = HH_EINVAL;\r
- VIP_common_ret_t vip_rc= VIP_EINVAL_PARAM;\r
- u_int32_t mpt_index = lkey & ((1ul << mrwm->props.log2_mpt_sz) - 1);\r
- MT_bool have_fatal = FALSE;\r
- VIP_array_obj_t vip_obj;\r
- Mr_sw_t *mrsw_p=NULL;\r
- THH_cmd_status_t cmd_rc = THH_CMD_STAT_OK;\r
- mpt_segment_t mpt_seg;\r
-\r
- MTL_TRACE1("{THH_mrwm_deregister_mr: mrwm=%p, lkey=0x%x, mi=0x%x\n",\r
- mrwm, lkey, mpt_index);\r
- mpt_seg= get_mpt_seg(mrwm,mpt_index);\r
- if ((mpt_seg != MPT_ext) && (mpt_seg != MPT_int)){\r
- MTL_ERROR4(MT_FLFMT("%s: Invalid L-key (0x%X) for memory region"),__func__,lkey);\r
- return HH_EINVAL;\r
- }\r
- vip_rc= VIP_array_erase_prepare(mrwm->mpt[mpt_seg],mpt_index-mrwm->offset[mpt_seg],&vip_obj);\r
- if (vip_rc != VIP_OK) {\r
- MTL_ERROR4(MT_FLFMT("%s: Failed removing L-key (0x%X) for memory region (%s)"),__func__,\r
- lkey,VAPI_strerror_sym(vip_rc));\r
- return (HH_ret_t)vip_rc;\r
- }\r
- mrsw_p= (Mr_sw_t*)vip_obj;\r
-\r
-#if defined(MT_SUSPEND_QP)\r
- if ((mpt_seg != MPT_int) || (mrsw_p->is_suspended == FALSE)) {\r
- /* if region IS suspended, is is already in SW ownership */\r
- cmd_rc = THH_cmd_HW2SW_MPT(mrwm->cmd_if, mpt_index, NULL);\r
- }\r
-#else\r
- cmd_rc = THH_cmd_HW2SW_MPT(mrwm->cmd_if, mpt_index, NULL);\r
-#endif\r
- /* for memory regions only, anything that is not a 'legal' return code is considered fatal.\r
- * In all problem cases, the unlocking of memory is deferred until THH_hob_destroy.\r
- */\r
- MTL_DEBUG4(MT_FLFMT("cmd_rc=%d=%s"), cmd_rc, str_THH_cmd_status_t(cmd_rc));\r
- switch(cmd_rc) {\r
- case THH_CMD_STAT_RESOURCE_BUSY:\r
- case THH_CMD_STAT_REG_BOUND:\r
- VIP_array_erase_undo(mrwm->mpt[mpt_seg],mpt_index-mrwm->offset[mpt_seg]);\r
- rc = HH_EBUSY;\r
- break;\r
- case THH_CMD_STAT_EINTR:\r
- VIP_array_erase_undo(mrwm->mpt[mpt_seg],mpt_index-mrwm->offset[mpt_seg]);\r
- rc = HH_EINTR;\r
- break;\r
- default: /* OK and all fatal errors*/\r
- {\r
- have_fatal = (cmd_rc != THH_CMD_STAT_OK) ? TRUE : FALSE;\r
- if (have_fatal && (cmd_rc != THH_CMD_STAT_EFATAL)) {\r
- MTL_ERROR1(MT_FLFMT("POSSIBLE FATAL ERROR:cmd_rc=%d=%s"), cmd_rc, str_THH_cmd_status_t(cmd_rc));\r
- }\r
- \r
- VIP_array_erase_done(mrwm->mpt[mpt_seg],mpt_index-mrwm->offset[mpt_seg],NULL);\r
- release_mpt_entry(mrwm,mpt_seg);\r
- if (mpt_index >= mrwm->offset[MPT_ext]) { \r
- /* return fatal for external mem region if had fatal */\r
- release_shared_mtts(mrwm,mrsw_p);\r
- rc = (have_fatal == TRUE) ? HH_EFATAL : HH_OK ;\r
- } else { /* internal region */\r
- /* return OK for internal mem region even if had fatal, because we are\r
- * handling deferred unlocking here.\r
- */\r
- internal_unlock(THH_hob_get_delay_unlock(mrwm->hob), mrsw_p->iobuf, have_fatal);\r
- release_shared_mtts(mrwm,mrsw_p);\r
- MOSAL_mutex_free(&mrsw_p->modify_mtx);\r
- rc = HH_OK;\r
- }\r
- FREE(mrsw_p);\r
- }\r
- }\r
- \r
- MTL_TRACE1("}THH_mrwm_deregister_mr, rc=%d\n", rc);\r
- if (rc != HH_EFATAL) {\r
- logIfErr("THH_mrwm_deregister_mr")\r
- }\r
- return rc;\r
-} /* THH_mrwm_deregister_mr */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_mrwm_alloc_mw(\r
- THH_mrwm_t mrwm, /* IN */\r
- HH_pd_hndl_t pd, /* IN */\r
- IB_rkey_t* initial_rkey_p /* OUT */\r
-)\r
-{\r
- HH_ret_t rc = HH_EAGAIN;\r
- VIP_array_handle_t win_hndl;\r
- VIP_common_ret_t vip_rc;\r
-\r
- MTL_TRACE1("{THH_mrwm_alloc_mw: mrwm=%p, pd=%d\n", mrwm, pd);\r
- if (reserve_mpt_entry(mrwm,MPT_win) != HH_OK) {\r
- MTL_ERROR4(MT_FLFMT("%s: No more free MPT entries for memory windows"),__func__);\r
- return HH_EAGAIN;\r
- }\r
- vip_rc= VIP_array_insert(mrwm->mpt[MPT_win],NULL,&win_hndl);\r
-\r
- if (vip_rc == VIP_OK)\r
- {\r
- THH_mpt_entry_t mpt_entry;\r
- THH_cmd_status_t cmd_rc;\r
- u_int32_t mpt_index = mrwm->offset[MPT_win] + win_hndl;\r
- \r
- mpt_entry_init(&mpt_entry);\r
- mpt_entry.pd = pd;\r
- mpt_entry.r_w = FALSE;\r
- mpt_entry.mem_key = CURRENT_MEMKEY(mrwm,MPT_win,mpt_index);\r
- cmd_rc = THH_cmd_SW2HW_MPT(mrwm->cmd_if, mpt_index, &mpt_entry);\r
- MTL_DEBUG4(MT_FLFMT("alloc_mw: cmd_rc=%d=%s"), \r
- cmd_rc, str_THH_cmd_status_t(cmd_rc));\r
- rc = (CMDRC2HH_ND(cmd_rc));\r
- *initial_rkey_p = mpt_entry.mem_key;\r
- }\r
- if ((rc != HH_OK) && (vip_rc == VIP_OK)) {\r
- VIP_array_erase(mrwm->mpt[MPT_win],win_hndl,NULL);\r
- release_mpt_entry(mrwm,MPT_win);\r
- }\r
- MTL_TRACE1("}THH_mrwm_alloc_mw: ley=0x%x\n", *initial_rkey_p);\r
- logIfErr("THH_mrwm_alloc_mw")\r
- return rc;\r
-} /* THH_mrwm_alloc_mw */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_mrwm_query_mw(\r
- THH_mrwm_t mrwm, /* IN */\r
- IB_rkey_t initial_rkey, /* IN */\r
- IB_rkey_t* current_rkey_p, /* OUT */\r
- HH_pd_hndl_t* pd_p /* OUT */\r
-)\r
-{\r
- HH_ret_t rc = HH_EINVAL;\r
- VIP_common_ret_t vip_rc;\r
- u_int32_t mpt_index= initial_rkey & MASK32(mrwm->props.log2_mpt_sz);\r
- u_int32_t win_index= mpt_index-mrwm->offset[MPT_win];\r
- VIP_array_obj_t win_obj; \r
- MTL_TRACE1("{THH_mrwm_query_mw: mrwm=%p, ini_key=0x%x\n", mrwm, initial_rkey);\r
- \r
- if (get_mpt_seg(mrwm,mpt_index) != MPT_win) {\r
- MTL_ERROR4(MT_FLFMT("%s: Invalid initial R-key for memory window (0x%X)"),__func__,\r
- initial_rkey);\r
- return HH_EINVAL_MW;\r
- }\r
- vip_rc= VIP_array_find_hold(mrwm->mpt[MPT_win],win_index,&win_obj);\r
- if (vip_rc != VIP_OK) {\r
- MTL_ERROR3(MT_FLFMT("%s: Invalid mem-window memkey (0x%X)"),__func__,initial_rkey);\r
- } else {\r
- THH_mpt_entry_t mpt_entry;\r
- THH_cmd_status_t cmd_rc;\r
- mpt_entry_init(&mpt_entry); /* not really needed */\r
- cmd_rc = THH_cmd_QUERY_MPT(mrwm->cmd_if, mpt_index, &mpt_entry);\r
- rc = (CMDRC2HH_ND(cmd_rc));\r
- if (cmd_rc == THH_CMD_STAT_OK)\r
- {\r
- *current_rkey_p = mpt_entry.mem_key;\r
- *pd_p = mpt_entry.pd;\r
- }\r
- }\r
- \r
- VIP_array_find_release(mrwm->mpt[MPT_win],win_index);\r
- MTL_TRACE1("}THH_mrwm_query_mw: cur_key=0x%x, pd=%d\n",\r
- *current_rkey_p, *current_rkey_p);\r
- logIfErr("THH_mrwm_query_mw")\r
- return rc;\r
-} /* THH_mrwm_query_mw */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_mrwm_free_mw(\r
- THH_mrwm_t mrwm, /* IN */\r
- IB_rkey_t initial_rkey /* IN */\r
-)\r
-{\r
- HH_ret_t rc = HH_EINVAL;\r
- VIP_common_ret_t vip_rc;\r
- VIP_array_obj_t win_obj;\r
- u_int32_t mpt_index= initial_rkey & MASK32(mrwm->props.log2_mpt_sz);\r
- u_int32_t win_index= mpt_index-mrwm->offset[MPT_win];\r
- MTL_TRACE1("{THH_mrwm_free_mw: mrwm=%p, ini_key=0x%x\n", mrwm, initial_rkey);\r
- \r
- if (get_mpt_seg(mrwm,mpt_index) != MPT_win) {\r
- MTL_ERROR4(MT_FLFMT("%s: Invalid initial R-key for memory window (0x%X)"),__func__,\r
- initial_rkey);\r
- return HH_EINVAL_MW;\r
- }\r
- vip_rc= VIP_array_erase_prepare(mrwm->mpt[MPT_win],win_index,&win_obj);\r
- if (vip_rc != VIP_OK) {\r
- MTL_ERROR3(MT_FLFMT("%s: Invalid mem-window memkey (0x%X)"),__func__,initial_rkey);\r
- } else {\r
- THH_mpt_entry_t mpt_entry;\r
- THH_cmd_status_t cmd_rc = THH_cmd_HW2SW_MPT(mrwm->cmd_if, mpt_index,\r
- &mpt_entry);\r
- switch(cmd_rc) {\r
- case THH_CMD_STAT_OK:\r
- rc = HH_OK;\r
- break;\r
- case THH_CMD_STAT_RESOURCE_BUSY:\r
- rc = HH_EBUSY;\r
- break;\r
- case THH_CMD_STAT_EINTR:\r
- rc = HH_EINTR;\r
- break;\r
- default:\r
- rc = HH_EFATAL;\r
- }\r
- if (cmd_rc == THH_CMD_STAT_OK)\r
- {\r
- mrwm->key_prefix[MPT_win][win_index] = /* sync key prefix for next allocation */\r
- (mpt_entry.mem_key >> mrwm->props.log2_mpt_sz) + 1;\r
- }\r
- if ((rc == HH_OK) || (rc == HH_EFATAL)) {\r
- VIP_array_erase_done(mrwm->mpt[MPT_win],win_index,NULL);\r
- release_mpt_entry(mrwm,MPT_win);\r
- } else {\r
- VIP_array_erase_undo(mrwm->mpt[MPT_win],win_index);\r
- }\r
- }\r
- MTL_TRACE1("}THH_mrwm_free_mw\n");\r
- if (rc != HH_EFATAL) {\r
- logIfErr("THH_mrwm_free_mw")\r
- }\r
- return rc;\r
-} /* THH_mrwm_free_mw */\r
-\r
-\r
-HH_ret_t THH_mrwm_alloc_fmr(THH_mrwm_t mrwm, /*IN*/\r
- HH_pd_hndl_t pd, /*IN*/\r
- VAPI_mrw_acl_t acl, /*IN*/\r
- MT_size_t max_pages, /*IN*/ \r
- u_int8_t log2_page_sz,/*IN*/\r
- VAPI_lkey_t* last_lkey_p) /*OUT*/\r
-{\r
- HH_ret_t rc = HH_EAGAIN;\r
- VIP_common_ret_t vip_rc;\r
- FMR_sw_info_t* new_fmr_p;\r
- VIP_array_handle_t fmr_hndl;\r
- u_int32_t seg_start = EXTBUDDY_NULL;\r
- u_int8_t log2_mtt_seg_sz = mrwm->props.log2_mtt_seg_sz;\r
- u_int32_t n_segs;\r
- u_int8_t log2_segs;\r
- THH_mpt_entry_t mpt_entry;\r
- THH_mpt_index_t mpt_index;\r
- THH_cmd_status_t cmd_rc;\r
- MT_size_t seg_comp = max_pages >> log2_mtt_seg_sz;\r
- \r
-\r
- /*compute n_segs: round it up to mtt seg size multiple */\r
- seg_comp= ((seg_comp << log2_mtt_seg_sz) != max_pages) ? seg_comp + 1 : seg_comp;\r
- /*check that n_segs will not overflow 32 bits */\r
- log2_segs = ceil_log2(seg_comp);\r
- if (log2_segs >= (8*sizeof(n_segs))) return HH_EINVAL_PARAM;\r
- n_segs = 1 << log2_segs;\r
-\r
-\r
- if (log2_page_sz < TAVOR_LOG_MPT_PG_SZ_SHIFT) {\r
- MTL_ERROR4(MT_FLFMT("Given log2_page_sz too small (%d)"),log2_page_sz);\r
- return HH_EINVAL_PARAM;\r
- }\r
-\r
- new_fmr_p= TMALLOC(FMR_sw_info_t);\r
- if (new_fmr_p == NULL) {\r
- MTL_ERROR4(MT_FLFMT("%s: Failed allocating memory for FMR context"),__func__);\r
- goto failed_malloc; /* HH_EAGAIN */\r
- }\r
-\r
- if (reserve_mpt_entry(mrwm,MPT_ext) != HH_OK) {\r
- MTL_ERROR4(MT_FLFMT("%s: No more free MPT entry for external regions"),__func__);\r
- goto failed_reserve_mpt;\r
- }\r
- vip_rc= VIP_array_insert(mrwm->mpt[MPT_ext],new_fmr_p,&fmr_hndl);\r
- if (vip_rc != VIP_OK) {\r
- MTL_ERROR1(MT_FLFMT("Failed allocating MPT entry for FMR (%s)"),VAPI_strerror_sym(vip_rc));\r
- rc= HH_EAGAIN;\r
- goto failed_array_insert;\r
- }\r
- \r
- /* set the fmr_bit in the array */\r
- {\r
- u_int8_t offset_in_cell = fmr_hndl & 0x7;\r
- mrwm->is_fmr_bits[fmr_hndl>>3]|= (((u_int8_t)1) << offset_in_cell);\r
- }\r
-\r
- /* we must ensure at least one segment for each region */\r
- if (reserve_mtt_segs(mrwm,n_segs-1) != HH_OK) {\r
- MTL_ERROR4(MT_FLFMT("Not enough available MTT segments for a new FMR of %d segments"),n_segs);\r
- rc= HH_EAGAIN;\r
- goto failed_out_of_mtt;\r
- }\r
- if (MOSAL_mutex_acq(&mrwm->extbuddy_lock, TRUE) != MT_OK) {\r
- rc= HH_EINTR; /* Operation interrupted */\r
- goto failed_mutex;\r
- }\r
- seg_start = extbuddy_alloc(mrwm->xbuddy_tpt, log2_segs);\r
- if (seg_start != EXTBUDDY_NULL) {EXTBUDDY_ALLOC_MTT(seg_start,log2_segs);}\r
- MOSAL_mutex_rel(&mrwm->extbuddy_lock);\r
- if (seg_start == EXTBUDDY_NULL) {\r
- MTL_ERROR1(MT_FLFMT("Failed allocating MTT segments for FMR"));\r
- rc= HH_EAGAIN;\r
- goto failed_extbd;\r
- }\r
-\r
- mpt_index = mrwm->offset[MPT_ext] + fmr_hndl;\r
- init_fmr_mpt_entry(&mpt_entry,pd,acl,make_key(mrwm, MPT_ext,(u_int32_t)mpt_index),log2_page_sz,\r
- mrwm->props.mtt_base | (seg_start << (mrwm->props.log2_mtt_seg_sz + MTT_LOG_MTT_ENTRY_SIZE)) );\r
- MTL_DEBUG4(MT_FLFMT("mtt_seg_adr="U64_FMT), mpt_entry.mtt_seg_adr);\r
-\r
- cmd_rc = THH_cmd_SW2HW_MPT(mrwm->cmd_if, mpt_index, &mpt_entry);\r
- if (cmd_rc != THH_CMD_STAT_OK) {\r
- MTL_ERROR1(MT_FLFMT("SW2HW_MPT failed - cmd_rc=%d"), cmd_rc);\r
- rc = (cmd_rc == THH_CMD_STAT_EINTR) ? HH_EINTR : HH_EFATAL; \r
- goto failed_sw2hw_mpt;\r
- }\r
- \r
- /*saving the new MPT entry */\r
- rc = init_fmr_context(mrwm,new_fmr_p ,(u_int32_t)mpt_index, seg_start, log2_segs, log2_page_sz); \r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("failed init_fmr_context() \n"));\r
- goto failed_sw_ctx;\r
- }\r
-\r
- *last_lkey_p = mpt_entry.mem_key;\r
- return rc;\r
-\r
- failed_sw_ctx:\r
- if (THH_cmd_HW2SW_MPT(mrwm->cmd_if, mpt_index, &mpt_entry) != THH_CMD_STAT_OK) rc= HH_EFATAL;\r
- failed_sw2hw_mpt:\r
- MOSAL_mutex_acq_ui(&mrwm->extbuddy_lock);\r
- extbuddy_free(mrwm->xbuddy_tpt, seg_start,log2_segs);\r
- EXTBUDDY_FREE_MTT(seg_start, log2_segs);\r
- MOSAL_mutex_rel(&mrwm->extbuddy_lock);\r
- failed_extbd:\r
- failed_mutex:\r
- release_mtt_segs(mrwm,n_segs - 1);\r
- failed_out_of_mtt:\r
- VIP_array_erase(mrwm->mpt[MPT_ext],fmr_hndl,NULL);\r
- failed_array_insert:\r
- release_mpt_entry(mrwm,MPT_ext);\r
- failed_reserve_mpt:\r
- FREE(new_fmr_p);\r
- failed_malloc:\r
- return rc;\r
-}\r
-\r
-HH_ret_t THH_mrwm_map_fmr(THH_mrwm_t mrwm, /*IN*/\r
- VAPI_lkey_t last_lkey, /*IN*/\r
- EVAPI_fmr_map_t* map_p, /*IN*/\r
- VAPI_lkey_t* lkey_p, /*OUT*/\r
- IB_rkey_t* rkey_p) /*OUT*/\r
-{\r
- u_int32_t mpt_index= last_lkey & MASK32(mrwm->props.log2_mpt_sz);\r
- u_int32_t fmr_hndl;\r
- VIP_array_obj_t vip_obj;\r
- FMR_sw_info_t* fmr_info_p;\r
- MT_size_t max_pages,real_num_of_pages,i;\r
- u_int32_t cur_memkey,new_memkey;\r
-#ifndef WRITE_QWORD_WORKAROUND\r
- volatile u_int64_t tmp_qword;\r
-#endif\r
- MT_virt_addr_t cur_mtt_p;\r
- VIP_common_ret_t vip_rc;\r
-\r
- /* Validity checks */\r
- \r
- if (get_mpt_seg(mrwm,mpt_index) != MPT_ext){\r
- MTL_ERROR3(MT_FLFMT("%s: Invalid FMR lkey (0x%X)"),__func__,last_lkey);\r
- return HH_EINVAL;\r
- }\r
- fmr_hndl= mpt_index-mrwm->offset[MPT_ext];\r
- vip_rc= VIP_array_find_hold(mrwm->mpt[MPT_ext],fmr_hndl,&vip_obj);\r
- if (vip_rc != VIP_OK) {\r
- MTL_ERROR2(MT_FLFMT("THH_mrmw_map_fmr invoked for invalid MPT (last_lkey=0x%X)"),last_lkey);\r
- return HH_EINVAL;\r
- }\r
- fmr_info_p= (FMR_sw_info_t*)vip_obj;\r
- cur_memkey= CURRENT_MEMKEY(mrwm,MPT_ext,mpt_index);\r
- if (last_lkey != cur_memkey) {\r
- VIP_array_find_release(mrwm->mpt[MPT_ext],fmr_hndl);\r
- MTL_ERROR2(MT_FLFMT("THH_mrmw_map_fmr invoked with last_lkey=0x%X while current lkey=0x%X"),\r
- last_lkey,cur_memkey);\r
- return HH_EINVAL;\r
- }\r
- \r
- max_pages= (MT_size_t)1<<(fmr_info_p->log2_segs + mrwm->props.log2_mtt_seg_sz); \r
- /* TBD: possible optimization for line above: save max_pages on FMR allocation in FMR_sw_info_t */\r
-/*** warning C4242: '=' : conversion from 'VAPI_virt_addr_t' to 'MT_size_t', possible loss of data ***/\r
- real_num_of_pages= (MT_size_t)(((map_p->start + map_p->size - 1) >> fmr_info_p->log2_page_sz) - /* end_page - start_page + 1 */\r
- (map_p->start >> fmr_info_p->log2_page_sz) + 1); \r
- if ((map_p->page_array_len > max_pages) || (real_num_of_pages != map_p->page_array_len)) {\r
- VIP_array_find_release(mrwm->mpt[MPT_ext],fmr_hndl);\r
- MTL_ERROR2(MT_FLFMT("%s: illegal number of pages for mapping FMR at MPT index 0x%X: start="U64_FMT\r
- " , size="U64_FMT" , log2_page_sz=%d, "\r
- "real_num_of_pages="SIZE_T_DFMT" , page_array_len="SIZE_T_DFMT" , max_pages="SIZE_T_DFMT), __func__,mpt_index,map_p->start, map_p->size,fmr_info_p->log2_page_sz, \r
- real_num_of_pages,map_p->page_array_len,max_pages);\r
- return HH_EINVAL;\r
- }\r
- \r
- /* Compute new memory key */\r
- MOSAL_spinlock_dpc_lock(&mrwm->key_prefix_lock);\r
- ++(mrwm->key_prefix[MPT_ext][fmr_hndl]);\r
- new_memkey= CURRENT_MEMKEY(mrwm,MPT_ext,mpt_index);\r
- if (new_memkey == fmr_info_p->last_free_key) {\r
- mrwm->key_prefix[MPT_ext][fmr_hndl]--; /* Restore previous key */\r
- MOSAL_spinlock_unlock(&mrwm->key_prefix_lock);\r
- VIP_array_find_release(mrwm->mpt[MPT_ext],fmr_hndl);\r
- MTL_DEBUG4(MT_FLFMT("Wrap around of memory key detected for MPT index %d (last_free_key=0x%X)"),\r
- mpt_index,new_memkey);\r
- return HH_EAGAIN; /* Retry after unmapping */\r
- }\r
- MOSAL_spinlock_unlock(&mrwm->key_prefix_lock);\r
-\r
- if (cur_memkey != fmr_info_p->last_free_key) { /* It's a "remap" - invalidate MPT before updating MTT andother MPT fields */\r
- MOSAL_MMAP_IO_WRITE_BYTE((fmr_info_p->mpt_entry + TAVOR_IF_MPT_HW_STATUS_OFFSET),0xf0);\r
- }\r
-\r
- for (i= 0, cur_mtt_p= fmr_info_p->mtt_entries; i < real_num_of_pages; i++) { /* Write MTT entries */\r
-#ifdef WRITE_QWORD_WORKAROUND\r
- MOSAL_MMAP_IO_WRITE_DWORD(cur_mtt_p,MOSAL_cpu_to_be32((u_int32_t)(map_p->page_array[i] >> 32)));\r
- MOSAL_MMAP_IO_WRITE_DWORD(cur_mtt_p+4,MOSAL_cpu_to_be32(((u_int32_t)(map_p->page_array[i] & 0xFFFFFFFF)) | 1);\r
-#else\r
- ((volatile u_int32_t*)&tmp_qword)[0]= \r
- MOSAL_cpu_to_be32((u_int32_t)(map_p->page_array[i] >> 32)); /* ptag_h */\r
- ((volatile u_int32_t*)&tmp_qword)[1]= \r
- MOSAL_cpu_to_be32(((u_int32_t)(map_p->page_array[i] & 0xFFFFF000)) | 1); /* ptag_l | p */\r
- MOSAL_MMAP_IO_WRITE_QWORD(cur_mtt_p, tmp_qword );\r
-#endif\r
- cur_mtt_p+= (1<<LOG2_MTT_ENTRY_SZ);\r
- }\r
-#ifdef WRITE_QWORD_WORKAROUND\r
- MOSAL_MMAP_IO_WRITE_DWORD((fmr_info_p->mpt_entry + TAVOR_IF_MPT_HW_START_ADDR_OFFSET),\r
- MOSAL_cpu_to_be32((u_int32_t)(map_p->start >> 32)));\r
- MOSAL_MMAP_IO_WRITE_DWORD((fmr_info_p->mpt_entry + TAVOR_IF_MPT_HW_START_ADDR_OFFSET + 4),\r
- MOSAL_cpu_to_be32((u_int32_t)(map_p->start & 0xFFFFFFFF)));\r
-#else\r
- ((volatile u_int32_t*)&tmp_qword)[0]= \r
- MOSAL_cpu_to_be32((u_int32_t)(map_p->start >> 32)); /* start_h */ \r
- ((volatile u_int32_t*)&tmp_qword)[1]= \r
- MOSAL_cpu_to_be32((u_int32_t)(map_p->start & 0xFFFFFFFF)); /* start_l */\r
- MOSAL_MMAP_IO_WRITE_QWORD((fmr_info_p->mpt_entry + TAVOR_IF_MPT_HW_START_ADDR_OFFSET),tmp_qword);\r
-#endif\r
- /* MemKey+Lkey update */\r
- MOSAL_MMAP_IO_WRITE_DWORD((fmr_info_p->mpt_entry + TAVOR_IF_MPT_HW_MEMKEY_OFFSET),MOSAL_cpu_to_be32(new_memkey));\r
- MOSAL_MMAP_IO_WRITE_DWORD((fmr_info_p->mpt_entry + TAVOR_IF_MPT_HW_LKEY_OFFSET),MOSAL_cpu_to_be32(new_memkey));\r
-\r
-#ifdef WRITE_QWORD_WORKAROUND\r
- MOSAL_MMAP_IO_WRITE_DWORD((fmr_info_p->mpt_entry + TAVOR_IF_MPT_HW_LEN_OFFSET),\r
- MOSAL_cpu_to_be32((u_int32_t)(map_p->size >> 32)));\r
- MOSAL_MMAP_IO_WRITE_DWORD((fmr_info_p->mpt_entry + TAVOR_IF_MPT_HW_LEN_OFFSET + 4),\r
- MOSAL_cpu_to_be32((u_int32_t)(map_p->size & 0xFFFFFFFF)));\r
-#else\r
- ((volatile u_int32_t*)&tmp_qword)[0]= \r
- MOSAL_cpu_to_be32((u_int32_t)(map_p->size >> 32)); /* length_h */ \r
- ((volatile u_int32_t*)&tmp_qword)[1]= \r
- MOSAL_cpu_to_be32((u_int32_t)(map_p->size & 0xFFFFFFFF)); /* length_l */\r
- MOSAL_MMAP_IO_WRITE_QWORD((fmr_info_p->mpt_entry + TAVOR_IF_MPT_HW_LEN_OFFSET),tmp_qword); /* length change makes MPT valid again */\r
-#endif\r
- /* revalidate this MPT */\r
- MOSAL_MMAP_IO_WRITE_BYTE((fmr_info_p->mpt_entry + TAVOR_IF_MPT_HW_STATUS_OFFSET),0);\r
-\r
- VIP_array_find_release(mrwm->mpt[MPT_ext],fmr_hndl);\r
- *lkey_p= new_memkey;\r
- *rkey_p= new_memkey;\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THH_mrwm_unmap_fmr(THH_mrwm_t mrwm, /*IN*/\r
- u_int32_t num_of_fmrs_to_unmap,/*IN*/\r
- VAPI_lkey_t* last_lkeys_array) /*IN*/\r
-{\r
- u_int32_t mpt_index,fmr_hndl;\r
- u_int32_t index_mask= MASK32(mrwm->props.log2_mpt_sz);\r
- VIP_array_obj_t vip_obj;\r
- FMR_sw_info_t* fmr_info_p;\r
- u_int32_t cur_memkey;\r
- u_int32_t i;\r
- THH_cmd_status_t cmd_rc;\r
- VIP_common_ret_t vip_rc;\r
-\r
- for (i= 0; i < num_of_fmrs_to_unmap; i++) {\r
- mpt_index= last_lkeys_array[i] & index_mask;\r
- if (get_mpt_seg(mrwm,mpt_index) != MPT_ext){\r
- MTL_ERROR3(MT_FLFMT("%s: Invalid FMR lkey (0x%X)"),__func__,last_lkeys_array[i]);\r
- continue;\r
- }\r
- fmr_hndl= mpt_index-mrwm->offset[MPT_ext];\r
- vip_rc= VIP_array_find_hold(mrwm->mpt[MPT_ext],fmr_hndl,&vip_obj);\r
- if (vip_rc != VIP_OK) {\r
- MTL_ERROR2(MT_FLFMT("THH_mrmw_map_fmr invoked for invalid MPT (last_lkey=0x%X)"),\r
- last_lkeys_array[i]);\r
- continue;\r
- }\r
- fmr_info_p= (FMR_sw_info_t*)vip_obj;\r
- cur_memkey= CURRENT_MEMKEY(mrwm,MPT_ext,mpt_index);\r
- if (last_lkeys_array[i] != cur_memkey) {\r
- VIP_array_find_release(mrwm->mpt[MPT_ext],fmr_hndl);\r
- MTL_ERROR2(MT_FLFMT("THH_mrmw_map_fmr invoked with last_lkey=0x%X while current lkey=0x%X"),\r
- last_lkeys_array[i],cur_memkey);\r
- continue; /* continue unmap for any region we can */\r
- }\r
- \r
- MOSAL_MMAP_IO_WRITE_BYTE((fmr_info_p->mpt_entry + TAVOR_IF_MPT_HW_STATUS_OFFSET),0xf0); /* invalidate mpt */\r
- fmr_info_p->last_free_key= cur_memkey;\r
- VIP_array_find_release(mrwm->mpt[MPT_ext],fmr_hndl);\r
- }\r
-\r
- cmd_rc = THH_cmd_SYNC_TPT(mrwm->cmd_if);\r
- if ((cmd_rc != THH_CMD_STAT_OK) && (cmd_rc != THH_CMD_STAT_EINTR)) {\r
- MTL_ERROR1(MT_FLFMT("Fatal error: Command SYNC_TPT failed"));\r
- }\r
- return (CMDRC2HH_ND(cmd_rc));\r
-}\r
-\r
-HH_ret_t THH_mrwm_free_fmr(THH_mrwm_t mrwm, /*IN*/\r
- VAPI_lkey_t last_lkey) /*IN*/\r
-\r
-{\r
- u_int32_t mpt_index= last_lkey & MASK32(mrwm->props.log2_mpt_sz);\r
- VIP_array_obj_t vip_obj;\r
- VIP_array_handle_t fmr_hndl;\r
- FMR_sw_info_t* fmr_info_p;\r
- THH_cmd_status_t stat;\r
- VIP_common_ret_t vip_rc;\r
-\r
- /* Validity checks */\r
- if (get_mpt_seg(mrwm,mpt_index) != MPT_ext){\r
- MTL_ERROR3(MT_FLFMT("%s: Invalid FMR lkey (0x%X)"),__func__,last_lkey);\r
- return HH_EINVAL;\r
- }\r
- fmr_hndl= mpt_index-mrwm->offset[MPT_ext];\r
- vip_rc= VIP_array_erase_prepare(mrwm->mpt[MPT_ext],fmr_hndl,&vip_obj);\r
- if (vip_rc != VIP_OK) {\r
- MTL_ERROR2(MT_FLFMT("THH_mrmw_map_fmr invoked for invalid MPT (last_lkey=0x%X)"),last_lkey);\r
- return HH_EINVAL;\r
- }\r
- fmr_info_p= (FMR_sw_info_t*)vip_obj;\r
- \r
- if (last_lkey != CURRENT_MEMKEY(mrwm,MPT_ext,mpt_index)) {\r
- VIP_array_erase_undo(mrwm->mpt[MPT_ext],fmr_hndl);\r
- MTL_ERROR2(MT_FLFMT("THH_mrwm_free_fmr invoked with last_lkey=0x%X while current lkey=0x%X"),\r
- last_lkey,CURRENT_MEMKEY(mrwm,MPT_ext,mpt_index));\r
- return HH_EINVAL;\r
- }\r
- \r
- MOSAL_MMAP_IO_WRITE_BYTE((fmr_info_p->mpt_entry + TAVOR_IF_MPT_HW_STATUS_OFFSET),0xf0); /* invalidate mpt */\r
-\r
- stat = THH_cmd_SYNC_TPT(mrwm->cmd_if);\r
- if ((stat != THH_CMD_STAT_OK) && (stat != THH_CMD_STAT_EINTR)) {\r
- MTL_ERROR1(MT_FLFMT("Fatal error: Command SYNC_TPT failed"));\r
- }\r
-\r
- /* MOSAL_io_unmap for MTTs+MPT */\r
- MOSAL_io_unmap(fmr_info_p->mpt_entry);\r
- MOSAL_io_unmap(fmr_info_p->mtt_entries);\r
- \r
- /* Return MTTs to extbuddy and MPT to epool */\r
- MOSAL_mutex_acq_ui(&mrwm->extbuddy_lock);\r
- if (!extbuddy_free(mrwm->xbuddy_tpt, fmr_info_p->seg_start,fmr_info_p->log2_segs)) {\r
- MTL_ERROR4(MT_FLFMT(\r
- "extbuddy_free failed for %d MTT segments from segment %d - resource leak !"),\r
- fmr_info_p->seg_start,fmr_info_p->log2_segs); /* continue anyway */\r
- }\r
- EXTBUDDY_FREE_MTT(fmr_info_p->seg_start,fmr_info_p->log2_segs);\r
- MOSAL_mutex_rel(&mrwm->extbuddy_lock);\r
- release_mtt_segs(mrwm,(1 << fmr_info_p->log2_segs) - 1);\r
- \r
- VIP_array_erase_done(mrwm->mpt[MPT_ext],fmr_hndl,NULL);\r
- /* zero the fmr_bit in the array */\r
- {\r
- u_int8_t offset_in_cell = fmr_hndl & 0x7;\r
- mrwm->is_fmr_bits[fmr_hndl>>3]&= ~(((u_int8_t)1) << offset_in_cell);\r
- }\r
- \r
- release_mpt_entry(mrwm,MPT_ext);\r
- FREE(fmr_info_p);\r
- return ((stat ==THH_CMD_STAT_OK) ? HH_OK : HH_EFATAL);\r
-}\r
-\r
-/************************************************************************/\r
-/* Assumed to be the first called in this module, single thread. */\r
-void THH_mrwm_init(void)\r
-{\r
- native_page_shift = MOSAL_SYS_PAGE_SHIFT;\r
- MTL_DEBUG4(MT_FLFMT("native_page: shift=%d"), native_page_shift);\r
-} /* THH_mrwm_init */\r
-\r
-\r
-HH_ret_t THH_mrwm_get_num_objs(THH_mrwm_t mrwm,u_int32_t *num_mr_int_p, \r
- u_int32_t *num_mr_ext_p,u_int32_t *num_mws_p )\r
-{\r
- /* check attributes */\r
- if ( mrwm == NULL || mrwm->mpt[MPT_int] == NULL ||\r
- mrwm->mpt[MPT_ext] == NULL || mrwm->mpt[MPT_win] == NULL) {\r
- return HH_EINVAL;\r
- }\r
- \r
- if (num_mr_int_p == NULL && num_mr_ext_p == NULL && num_mws_p == NULL) {\r
- return HH_EINVAL;\r
- }\r
-\r
- if (num_mr_int_p) {\r
- *num_mr_int_p = VIP_array_get_num_of_objects(mrwm->mpt[MPT_int]);\r
- }\r
- if (num_mr_ext_p) {\r
- *num_mr_ext_p = VIP_array_get_num_of_objects(mrwm->mpt[MPT_ext]);\r
- }\r
- if (num_mws_p) {\r
- *num_mws_p = VIP_array_get_num_of_objects(mrwm->mpt[MPT_win]);\r
- }\r
- return HH_OK;\r
-}\r
-\r
-#if defined(MT_SUSPEND_QP)\r
-HH_ret_t THH_mrwm_suspend_internal(\r
- THH_mrwm_t mrwm, /* IN */\r
- VAPI_lkey_t lkey, /* IN */\r
- MT_bool suspend_flag /* IN */\r
-)\r
-{\r
- VIP_common_ret_t vip_rc;\r
- u_int32_t mpt_index = lkey & ((1ul << mrwm->props.log2_mpt_sz) - 1);\r
- mpt_segment_t mpt_seg;\r
- VIP_array_obj_t vip_obj;\r
- Mr_sw_t *mrsw_p;\r
- THH_cmd_status_t cmd_st;\r
- MOSAL_iobuf_props_t iobuf_props = {0};\r
- call_result_t mosal_rc;\r
- HH_ret_t rc = HH_OK; \r
-\r
- MTL_TRACE1(MT_FLFMT("{%s: L_key=0x%x, suspend_flag=%s"),\r
- __func__, lkey, (suspend_flag==TRUE)?"TRUE":"FALSE");\r
-\r
- mpt_seg= get_mpt_seg(mrwm,mpt_index);\r
- if (mpt_seg != MPT_int){\r
- MTL_ERROR4(MT_FLFMT("%s: Invalid L-key (0x%X) for internal memory region"),__func__,lkey);\r
- return HH_EINVAL;\r
- }\r
-\r
- vip_rc= VIP_array_find_hold(mrwm->mpt[mpt_seg],mpt_index-mrwm->offset[mpt_seg],&vip_obj);\r
- if (vip_rc != VIP_OK) {\r
- MTL_ERROR4(MT_FLFMT("%s: Failed finding internal memory region with L-key 0x%X (%s)"),__func__,\r
- lkey,VAPI_strerror_sym(vip_rc));\r
- return (HH_ret_t)vip_rc;\r
- }\r
- mrsw_p= (Mr_sw_t*)vip_obj;\r
-\r
- if (suspend_flag == TRUE) {\r
- if (mrsw_p->is_suspended == TRUE) {\r
- MTL_DEBUG2(MT_FLFMT("%s: internal memory region with L-key 0x%x already suspended"),\r
- __func__,lkey);\r
- rc = HH_EAGAIN;\r
- goto suspend_hold;\r
- }\r
- if (mrsw_p->iobuf == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: suspending intl_reg with L-key 0x%X. IOBUF is NULL!!"),\r
- __func__,lkey);\r
- rc = HH_ERR;\r
- goto suspend_hold;\r
- }\r
-\r
- mrsw_p->mpt_entry = TMALLOC(THH_mpt_entry_t);\r
- if (mrsw_p->mpt_entry == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: Could not malloc mem for saving mpt_entry for internal reg L-key 0x%X"),\r
- __func__,lkey);\r
- rc = HH_EAGAIN;\r
- goto suspend_hold;\r
- }\r
- /* change MPT entry to SW ownership to disable it, and save the mpt entry for restoring later */\r
- cmd_st = THH_cmd_HW2SW_MPT(mrwm->cmd_if, mpt_index, mrsw_p->mpt_entry);\r
- if (cmd_st != THH_CMD_STAT_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: THH_cmd_HW2SW_MPT returned %d for internal reg L-key 0x%X"),\r
- __func__,cmd_st, lkey);\r
- rc = HH_ERR;\r
- goto suspend_malloc;\r
- }\r
- /* deregister the iobuf */\r
- MOSAL_iobuf_get_props(mrsw_p->iobuf, &iobuf_props);\r
- mrsw_p->prot_ctx = iobuf_props.prot_ctx;\r
- mrsw_p->va = iobuf_props.va;\r
- mrsw_p->size = iobuf_props.size;\r
-\r
- MOSAL_iobuf_deregister(mrsw_p->iobuf);\r
- mrsw_p->iobuf= NULL;\r
- mrsw_p->is_suspended = TRUE;\r
- } else {\r
- /* unsuspending */\r
- /* reregister the iobuf */\r
- if (mrsw_p->is_suspended == FALSE) {\r
- MTL_ERROR1(MT_FLFMT("%s: unsuspend request. internel region is not suspended"), __func__);\r
- rc = HH_ERR;\r
- goto unsuspend_hold;\r
- }\r
- mosal_rc = MOSAL_iobuf_register( mrsw_p->va, mrsw_p->size, mrsw_p->prot_ctx, \r
- MOSAL_PERM_READ | MOSAL_PERM_WRITE, &mrsw_p->iobuf, \r
- MOSAL_IOBUF_LNX_FLG_MARK_ALL_DONTCOPY);\r
- if (mosal_rc != MT_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: unsuspend. MOSAL_iobuf_register: rc=%s"), __func__, mtl_strerror_sym(mosal_rc));\r
- rc = (mosal_rc == MT_EAGAIN) ? HH_EAGAIN : HH_EINVAL_VA;\r
- goto unsuspend_hold;\r
- }\r
-\r
- /* get properties of the iobuf just obtained, to get n_pages. */\r
- mosal_rc = MOSAL_iobuf_get_props(mrsw_p->iobuf, &iobuf_props);\r
- if (mosal_rc != MT_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: unsuspend. MOSAL_iobuf_get_props: rc=%s"), __func__, mtl_strerror_sym(mosal_rc));\r
- rc = HH_ERR;\r
- goto unsuspend_iobuf;\r
- }\r
- \r
- /* write the MTT entry with the page translation table*/\r
- rc = mtt_writes_iobuf(mrwm->cmd_if, \r
- mrsw_p->iobuf, \r
- (VAPI_phy_addr_t)mrsw_p->mpt_entry->mtt_seg_adr,\r
- iobuf_props.nr_pages);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: unsuspend. mtt_writes_iobuf failed (%d: %s)"),__func__,\r
- rc,HH_strerror_sym(rc));\r
- goto unsuspend_iobuf;\r
- }\r
-\r
- /* re-activate the MPT entry */\r
- cmd_st = THH_cmd_SW2HW_MPT(mrwm->cmd_if, mpt_index, mrsw_p->mpt_entry);\r
- if (cmd_st != THH_CMD_STAT_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: THH_cmd_SW2HW_MPT returned %d for internal reg L-key 0x%X"),\r
- __func__,cmd_st, lkey);\r
- rc = HH_ERR;\r
- goto unsuspend_iobuf;\r
- }\r
-\r
- /* clean-up */\r
- FREE(mrsw_p->mpt_entry);\r
- mrsw_p->mpt_entry= NULL;\r
- mrsw_p->is_suspended = FALSE;\r
- }\r
- \r
- VIP_array_find_release(mrwm->mpt[mpt_seg],mpt_index-mrwm->offset[mpt_seg]);\r
- MTL_TRACE1("}THH_mrwm_suspend_mr\n");\r
- return HH_OK;\r
-\r
-suspend_malloc:\r
- FREE(mrsw_p->mpt_entry);\r
- mrsw_p->mpt_entry = NULL;\r
-\r
-suspend_hold:\r
- VIP_array_find_release(mrwm->mpt[mpt_seg],mpt_index-mrwm->offset[mpt_seg]);\r
- return rc;\r
-\r
-unsuspend_iobuf:\r
- MOSAL_iobuf_deregister(mrsw_p->iobuf);\r
- mrsw_p->iobuf= NULL;\r
-unsuspend_hold:\r
- VIP_array_find_release(mrwm->mpt[mpt_seg],mpt_index-mrwm->offset[mpt_seg]);\r
- return rc;\r
- \r
-\r
-} /* THH_mrwm_query_mr */\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#if !defined(_TMRW__H)\r
-#define _TMRW__H\r
-\r
-#include <mtl_common.h>\r
-#include <vapi_types.h>\r
-#include <mosal.h>\r
-#include <hh.h>\r
-#include <cmdif.h>\r
-#include <thh.h>\r
-#include <thh_hob.h> /* just for THH_hob_t decl */\r
-\r
-typedef u_int32_t THH_pdm_t;\r
-\r
-\r
-#define THH_MRWM_MODIFY_FLAGS_TRANSLATION 1 /* implies size change - only this one \r
- * needs to be supported for SRQ. For \r
- * the rest ENOSYS \r
- */\r
-#define THH_MRWM_MODIFY_FLAGS_START_ADDR (1<<1) /* If not set, start address is only \r
- * used to create the new iobuf, but \r
- * MPT.start is retained from original MR \r
- */\r
-#define THH_MRWM_MODIFY_FLAGS_ACL (1<<2)\r
-#define THH_MRWM_MODIFY_FLAGS_PD (1<<3)\r
-/* More: TBD */\r
-typedef u_int32_t THH_mrwm_modify_flags_t;\r
-\r
-\r
-typedef struct\r
-{\r
- u_int64_t mtt_base; /* Physical address of MTT */\r
- MT_phys_addr_t mpt_base; /* Physical address of MPT */\r
- u_int8_t log2_mpt_sz; /* Log2 of number of entries in MPT */\r
- u_int8_t log2_mtt_sz; /* Log2 of number of entries in the MTT */\r
- u_int8_t log2_mtt_seg_sz; /* Log2 of MTT segment size in entries */\r
- u_int8_t log2_max_mtt_segs; /* Log2 of maximum MTT segments possible */\r
- u_int8_t log2_rsvd_mpts; /* Log2 of number of MPTs reserved for firmware */\r
- u_int8_t log2_rsvd_mtt_segs; /* Log2 of number of MTT segments reserved for firmware */\r
- MT_size_t max_mem_reg; /* Max regions in MPT for external */\r
- MT_size_t max_mem_reg_internal; /* Max regions ... internal (WQEs & CQEs) */\r
- MT_size_t max_mem_win; /* Max memory windows in the MPT */\r
-} THH_mrwm_props_t;\r
-\r
-\r
-typedef struct\r
-{\r
- IB_virt_addr_t start; /* Region start address in user virtual space */\r
- VAPI_size_t size; /* Region size */\r
- HH_pd_hndl_t pd; /* PD to associate with requested region */\r
- MOSAL_protection_ctx_t vm_ctx; /* Virtual context of given virt. address */\r
- MT_bool force_memkey; /* Allocate region with given memory key */\r
- VAPI_lkey_t memkey; /* Requested memory key (valid iff force_memkey) */\r
-\r
- /* Optional supplied physical buffers. Similar to HH_tpt_t.buf_lst */\r
- MT_size_t num_bufs; /* != 0 iff physical buffers supplied */\r
- VAPI_phy_addr_t* phys_buf_lst; /* size = num_bufs */\r
- VAPI_size_t* buf_sz_lst; /* [num_bufs], corresponds to phys_buf_lst */\r
-} THH_internal_mr_t;\r
-\r
-/************************************************************************\r
- * Function: THH_mrwm_create\r
- *\r
- * Arguments:\r
- * hob\r
- * mrwm_props - Tables sizes and allocation partioning\r
- * mrwm_p - The allocated THH_mrwm object\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters (MPT size given is smaller than\r
- * total number of regions and windows, or NULL ptr.)\r
- * HH_EAGAIN - Not enough resources in order to allocate object\r
- *\r
- * Description:\r
- * This function creates the THH_mrwm_t object instance in order to\r
- * manage the MPT and MTT resources.\r
- */\r
-extern HH_ret_t THH_mrwm_create(\r
- THH_hob_t hob, /* IN */\r
- THH_mrwm_props_t* mrwm_props, /* IN */\r
- THH_mrwm_t* mrwm_p /* OUT */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_mrwm_destroy\r
- *\r
- * Arguments:\r
- * mrwm - Object to destroy\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Unknown object\r
- *\r
- * Description:\r
- * This function frees the THH_mrwm object resources.\r
- */\r
-extern HH_ret_t THH_mrwm_destroy(\r
- THH_mrwm_t mrwm, /* IN */\r
- MT_bool hca_failure /* IN */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_mrwm_register_mr\r
- *\r
- * Arguments:\r
- * mrwm\r
- * mr_props - Memory region properties\r
- * lkey_p - L-Key allocated for region (to be used as region handle)\r
- * rkey_p - R-Key allocated for region (valid for remote access)\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters (properties or pointers)\r
- * HH_EAGAIN - No free region resources available\r
- *\r
- * Description:\r
- * This function registers given memory region (virtual or physical -\r
- * based on given mr_props_p).\r
- */\r
-extern HH_ret_t THH_mrwm_register_mr(\r
- THH_mrwm_t mrwm, /* IN */\r
- HH_mr_t* mr_props_p, /* IN */\r
- VAPI_lkey_t* lkey_p, /* OUT */\r
- IB_rkey_t* rkey_p /* OUT */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_mrwm_register_internal\r
- *\r
- * Arguments:\r
- * mrwm\r
- * mr_props_p - Requested internal memory region propetries\r
- * memkey_p - Memory key to use in order to access this region\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- * HH_EAGAIN - No resources to allocate internal memory region\r
- *\r
- * Description:\r
- * For the WQEs and CQEs buffers internal memory registration is\r
- * required in order enable access of the InifinHost to those\r
- * buffers. This function performs a full memory registration operation\r
- * in addition to the registration operation as done for\r
- * THH_mrwm_register_mr(), i.e. it deals with locking the memory and\r
- * getting physical pages table (which is done by the VIP layers for\r
- * external memory registrations).\r
- */\r
-extern HH_ret_t THH_mrwm_register_internal(\r
- THH_mrwm_t mrwm, /* IN */\r
- THH_internal_mr_t* mr_props_p, /* IN */\r
- VAPI_lkey_t* memkey_p /* OUT */\r
-);\r
-\r
-/************************************************************************\r
- * Function: THH_mrwm_modify_internal\r
- *\r
- * Arguments:\r
- * mrwm\r
- * memkey_p - region's lkey\r
- * mr_props_p - Requested new internal memory region propetries\r
- * flags - indicate which properties in the mr_props structure\r
- * are valid (ie., are to be modified)\r
- * Currently, only THH_MRWM_MODIFY_FLAGS_TRANSLATION is supported.\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- * HH_EAGAIN - No resources to allocate internal memory region\r
- *\r
- * Description:\r
- * This function is currently used by SRQs, when modifying the size\r
- * of an SRQ. Size modification (i.e., number of outstanding WQEs)\r
- * is the only modification currently supported. The function must \r
- * pin the pages of the WQE buffer, create new MTT entries for the WQEs buffer,\r
- * update the data in the MPT entry for the region (MTT seg addr and length)\r
- * and issue the MODIFY_MPT command. If all goes well, the old iobuf is\r
- * deleted, as are the old MTT entries.\r
- */\r
-extern HH_ret_t THH_mrwm_modify_internal(\r
- THH_mrwm_t mrwm, /* IN */\r
- VAPI_lkey_t lkey, /* IN */\r
- THH_internal_mr_t* mr_props_p, /* IN */\r
- THH_mrwm_modify_flags_t flags /* IN */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_mrwm_reregister_mr\r
- *\r
- * Arguments:\r
- * mrwm\r
- * lkey\r
- * change_mask - Change request\r
- * mr_props_p - Updated memory region properties\r
- * lkey_p - \r
- * rkey_p - Returned R-key\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- * HH_EAGAIN - Not enough resources to complete operation\r
- *\r
- * Description:\r
- * (see HH-API s HH_reregister_mr)\r
- */\r
-extern HH_ret_t THH_mrwm_reregister_mr(\r
- THH_mrwm_t mrwm, /* IN */\r
- VAPI_lkey_t lkey,\r
- VAPI_mr_change_t change_mask, /* IN */\r
- HH_mr_t* mr_props_p, /* IN */\r
- VAPI_lkey_t* lkey_p, /* OUT */\r
- IB_rkey_t* rkey_p /* OUT */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_mrwm_register_smr\r
- *\r
- * Arguments:\r
- * mrwm\r
- * smr_props_p - Shared memory region properties\r
- * lkey_p - Returned L-key\r
- * rkey_p - Returned R-key\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters (properties or pointers)\r
- * HH_EAGAIN - No free region resources available\r
- *\r
- * Description:\r
- * This function uses the same physical pages (MTT) translation entries\r
- * for a new region (new MPT entry).\r
- */\r
-extern HH_ret_t THH_mrwm_register_smr(\r
- THH_mrwm_t mrwm, /* IN */\r
- HH_smr_t* smr_props_p, /* IN */\r
- VAPI_lkey_t* lkey_p, /* OUT */\r
- IB_rkey_t* rkey_p /* OUT */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_mrwm_query_mr\r
- *\r
- * Arguments:\r
- * mrwm\r
- * lkey - L-key of memory region as returned on registration\r
- * mr_info_p - Returned memory region information\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- *\r
- * Description:\r
- * This function returns properties of registered memory region using\r
- * region s L-key as a handle.\r
- */\r
-extern HH_ret_t THH_mrwm_query_mr(\r
- THH_mrwm_t mrwm, /* IN */\r
- VAPI_lkey_t lkey, /* IN */\r
- HH_mr_info_t* mr_info_p /* OUT */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_mrwm_deregister_mr\r
- *\r
- * Arguments:\r
- * mrwm\r
- * lkey - L-key of region to deregister\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Unknown region\r
- * HH_EBUSY - Given region is still bounded to memory windows\r
- *\r
- * Description:\r
- * This function frees given memory region resources (unless memory\r
- * windows are still bounded to it).\r
- */\r
-extern HH_ret_t THH_mrwm_deregister_mr(\r
- THH_mrwm_t mrwm, /* IN */\r
- VAPI_lkey_t lkey /* IN */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_mrwm_alloc_mw\r
- *\r
- * Arguments:\r
- * mrwm\r
- * pd - The protection domain of the allocated window\r
- * initial_rkey_p - R-Key to be used for first binding request\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters (unknown PD or NULL ptr.)\r
- * HH_EAGAIN - No available MPT resources\r
- *\r
- * Description:\r
- * Allocate MPT entry for a memory window.\r
- */\r
-extern HH_ret_t THH_mrwm_alloc_mw(\r
- THH_mrwm_t mrwm, /* IN */\r
- HH_pd_hndl_t pd, /* IN */\r
- IB_rkey_t* initial_rkey_p /* OUT */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_mrwm_query_mw\r
- *\r
- * Arguments:\r
- * mrwm\r
- * initial_rkey - R-Key received on window allocation\r
- * current_rkey_p - The current R-Key associated with this window\r
- * pd_p - The protection domain of this window\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters (unknown window or NULL ptr.)\r
- *\r
- * Description:\r
- * Return properties of given memory window (initial R-Key used as a handle).\r
- */\r
-extern HH_ret_t THH_mrwm_query_mw(\r
- THH_mrwm_t mrwm, /* IN */\r
- IB_rkey_t initial_rkey, /* IN */\r
- IB_rkey_t* current_rkey_p, /* OUT */\r
- HH_pd_hndl_t* pd_p /* OUT */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_mrwm_free_mw\r
- *\r
- * Arguments:\r
- * mrwm\r
- * initial_rkey - R-Key received on window allocation\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters (initial_rkey does not match\r
- * any memory window)\r
- *\r
- * Description:\r
- * Free the MPT resources associated with given memory window.\r
- */\r
-extern HH_ret_t THH_mrwm_free_mw(\r
- THH_mrwm_t mrwm, /* IN */\r
- IB_rkey_t initial_rkey /* IN */\r
-);\r
-\r
-\r
-\r
-/************************************************************************\r
- * Fast memory region\r
- ************************************************************************/\r
-\r
-HH_ret_t THH_mrwm_alloc_fmr(THH_mrwm_t mrwm, /*IN*/\r
- HH_pd_hndl_t pd, /*IN*/\r
- VAPI_mrw_acl_t acl, /*IN*/\r
- MT_size_t max_pages, /*IN*/ \r
- u_int8_t log2_page_sz,/*IN*/\r
- VAPI_lkey_t* last_lkey_p);/*OUT*/\r
-\r
-HH_ret_t THH_mrwm_map_fmr(THH_mrwm_t mrwm, /*IN*/\r
- VAPI_lkey_t last_lkey, /*IN*/\r
- EVAPI_fmr_map_t* map_p, /*IN*/\r
- VAPI_lkey_t* lkey_p, /*OUT*/\r
- IB_rkey_t* rkey_p); /*OUT*/\r
-\r
-HH_ret_t THH_mrwm_unmap_fmr(THH_mrwm_t mrwm, /*IN*/\r
- u_int32_t num_of_fmrs_to_unmap,/*IN*/\r
- VAPI_lkey_t* last_lkeys_array); /*IN*/\r
-\r
-HH_ret_t THH_mrwm_free_fmr(THH_mrwm_t mrwm, /*IN*/\r
- VAPI_lkey_t last_lkey); /*IN*/\r
-\r
-/* debug info */\r
-HH_ret_t THH_mrwm_get_num_objs(THH_mrwm_t mrwm,u_int32_t *num_mr_int_p, \r
- u_int32_t *num_mr_ext_p,u_int32_t *num_mws_p );\r
-\r
-\r
-#if defined(MT_SUSPEND_QP)\r
-HH_ret_t THH_mrwm_suspend_internal(\r
- THH_mrwm_t mrwm, /* IN */\r
- VAPI_lkey_t lkey, /* IN */\r
- MT_bool suspend_flag /* IN */\r
- );\r
-#endif\r
-#endif /* _TMRW__H */\r
-EXPORTS\r
- ; for OS only\r
- DllInitialize private\r
- DllUnload private\r
- ; for Windows Tavor Driver only\r
- THH_add_hca\r
- THH_rmv_hca\r
- ; ----- Thh_mod_obj.c -----\r
- THH_init_module\r
- THH_cleanup_module\r
- ; ----- Cmdif.c -----\r
- THH_cmd_create\r
- THH_cmd_destroy\r
- THH_cmd_set_eq\r
- THH_cmd_clr_eq\r
- THH_cmd_assign_ddrmm\r
- THH_cmd_revoke_ddrmm\r
- THH_cmd_eventh\r
- ; ----- Cmds_wrap.c -----\r
- THH_cmd_print_hca_props\r
- THH_cmd_print_dev_lims\r
- THH_cmd_print_query_fw\r
- THH_cmd_print_query_adapter\r
- THH_cmd_print_query_ddr\r
- THH_cmd_print_init_ib\r
- THH_cmd_print_cq_context\r
- THH_cmd_print_qp_context\r
- THH_cmd_print_eq_context\r
- THH_cmd_print_mpt_entry\r
- THH_cmd_print_mgm_entry\r
- ; ----- Eventp.c -----\r
- THH_eventp_create \r
- THH_eventp_destroy\r
- THH_eventp_setup_comp_eq\r
- THH_eventp_setup_ib_eq\r
- THH_eventp_setup_cmd_eq \r
- THH_eventp_setup_mt_eq\r
- THH_eventp_replace_handler\r
- THH_eventp_teardown_eq\r
- ; ----- Mcgm.c -----\r
- THH_mcgm_create\r
- THH_mcgm_destroy\r
- THH_mcgm_attach_qp\r
- THH_mcgm_detach_qp\r
- ; ----- Thh_hob.c -----\r
- THH_hob_query_port_prop\r
- THH_hob_alloc_ul_res\r
- THH_hob_free_ul_res\r
- THH_hob_alloc_pd\r
- THH_hob_free_pd\r
- THH_hob_alloc_rdd\r
- THH_hob_free_rdd\r
- THH_hob_create_ud_av\r
- THH_hob_modify_ud_av\r
- THH_hob_query_ud_av\r
- THH_hob_destroy_ud_av\r
- THH_hob_register_mr\r
- THH_hob_reregister_mr\r
- THH_hob_register_smr\r
- THH_hob_query_mr\r
- THH_hob_deregister_mr\r
- THH_hob_alloc_mw\r
- THH_hob_query_mw\r
- THH_hob_free_mw\r
- THH_hob_create_cq\r
- THH_hob_resize_cq\r
- THH_hob_query_cq\r
- THH_hob_destroy_cq\r
- THH_hob_create_qp\r
- THH_hob_get_special_qp\r
- THH_hob_modify_qp\r
- THH_hob_query_qp\r
- THH_hob_destroy_qp\r
- THH_hob_get_qp1_pkey\r
- THH_hob_get_sgid\r
- THH_hob_create_eec\r
- THH_hob_modify_eec\r
- THH_hob_query_eec\r
- THH_hob_destroy_eec\r
- THH_hob_attach_to_multicast\r
- THH_hob_detach_from_multicast\r
- THH_hob_close_hca\r
- THH_hob_open_hca\r
- THH_hob_destroy\r
- THH_hob_query\r
- THH_hob_modify\r
- THH_hob_get_pkey\r
- THH_hob_get_pkey_tbl\r
- THH_hob_set_comp_eventh\r
- THH_hob_set_async_eventh\r
- THH_hob_get_ver_info \r
- THH_hob_get_cmd_if \r
- THH_hob_get_uldm \r
- THH_hob_get_ddrmm \r
- THH_hob_get_mrwm \r
- THH_hob_get_qpm \r
- THH_hob_get_cqm \r
- THH_hob_get_eventp \r
- THH_hob_get_udavm_info \r
- THH_hob_get_hca_hndl \r
- THH_hob_alloc_ul_res\r
- THH_hob_free_ul_res\r
- THH_hob_alloc_pd\r
- THH_hob_free_pd\r
- THH_hob_alloc_rdd\r
- THH_hob_free_rdd\r
- THH_hob_create_ud_av\r
- THH_hob_modify_ud_av\r
- THH_hob_query_ud_av\r
- THH_hob_destroy_ud_av\r
- THH_hob_register_mr\r
- THH_hob_reregister_mr\r
- THH_hob_register_smr\r
- THH_hob_query_mr\r
- THH_hob_deregister_mr\r
- THH_hob_alloc_mw\r
- THH_hob_query_mw\r
- THH_hob_free_mw\r
- THH_hob_create_cq\r
- THH_hob_resize_cq\r
- THH_hob_query_cq\r
- THH_hob_destroy_cq\r
- THH_hob_create_qp\r
- THH_hob_get_special_qp\r
- THH_hob_modify_qp\r
- THH_hob_query_qp\r
- THH_hob_destroy_qp\r
- THH_hob_create_eec\r
- THH_hob_modify_eec\r
- THH_hob_query_eec\r
- THH_hob_destroy_eec\r
- THH_hob_attach_to_multicast\r
- THH_hob_detach_from_multicast\r
- THH_hob_get_num_ports\r
- ; ----- Thh_uldm.c -----\r
- THH_uldm_create\r
- THH_uldm_destroy\r
- THH_uldm_alloc_ul_res\r
- THH_uldm_free_ul_res\r
- THH_uldm_alloc_uar\r
- THH_uldm_free_uar\r
- THH_uldm_alloc_pd\r
- THH_uldm_free_pd\r
- THH_uldm_get_protection_ctx\r
- ; ----- Uar.c -----\r
- THH_uar_destroy\r
- THH_uar_get_index\r
- THH_uar_recvq_dbell\r
- THH_uar_cq_cmd\r
- THH_uar_eq_cmd\r
- THH_uar_blast\r
- ; ----- Udavm.c -----\r
- THH_udavm_create\r
- THH_udavm_destroy\r
- THH_udavm_get_memkey\r
- THH_udavm_create_av\r
- THH_udavm_modify_av\r
- THH_udavm_query_av\r
- THH_udavm_destroy_av\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include <hh.h>\r
-#include <thh.h>\r
-#include <thh_hob.h>\r
-#include <tavor_dev_defs.h>\r
-#include <thh_init.h>\r
-#include "thh_mod_obj.h"\r
-\r
-/* if non-zero, indicates legacy sqp initialization. May be modified by insmod parameter */\r
-static int thh_legacy_sqp = 0;\r
-static int av_in_host_mem = 0;\r
-static int infinite_cmd_timeout = 0; /* when 1 we use inifinite timeouts on commands completion */\r
-static int num_cmds_outs = 0; /* max number of outstanding commands */\r
-static int fatal_delay_halt = 0; /* when 1, HALT_HCA on fatal is delayed to just before the reset */\r
-static int async_eq_size = 0; /* size of async event queue */\r
-static int cmdif_use_uar0 = 0; /* when 1, cmdif posts commands to uar0 */\r
-static int ignore_subsystem_id = 0; /* when 1, we do not check the subsystem_vendor_id & subsystem_id */\r
-\r
-/*\r
- * Add a Tavor in device tables\r
- */\r
-HH_ret_t THH_add_hca(\r
- MT_size_t hca_num,\r
- card_hw_props_t *card_hw_props_p, \r
- HH_hca_hndl_t * hh_hca_hndl_p\r
- )\r
-{\r
- THH_module_flags_t mod_flags;\r
- THH_hw_props_t hw_props; \r
-\r
- /* fill HW params */\r
- hw_props.bus = card_hw_props_p->bus;\r
- hw_props.dev_func = card_hw_props_p->dev_func;\r
- hw_props.device_id = card_hw_props_p->device_id;\r
- hw_props.pci_vendor_id = card_hw_props_p->pci_vendor_id;\r
- hw_props.hw_ver = card_hw_props_p->hw_ver;\r
- hw_props.cr_base = card_hw_props_p->cr_base;\r
- hw_props.uar_base = card_hw_props_p->uar_base;\r
- hw_props.ddr_base = card_hw_props_p->ddr_base;\r
- hw_props.interrupt_props.irq = card_hw_props_p->interrupt_props.irq;\r
- hw_props.interrupt_props.intr_pin = card_hw_props_p->interrupt_props.intr_pin;\r
- \r
- /*initialize module flags structure */\r
- memset(&mod_flags, 0, sizeof(THH_module_flags_t));\r
- mod_flags.legacy_sqp = (thh_legacy_sqp == 0 ? FALSE : TRUE);\r
- mod_flags.av_in_host_mem = (av_in_host_mem == 0 ? FALSE : TRUE);\r
- mod_flags.inifinite_cmd_timeout = (infinite_cmd_timeout==1 ? TRUE : FALSE);\r
- mod_flags.fatal_delay_halt = (fatal_delay_halt==1 ? TRUE : FALSE);\r
- mod_flags.cmdif_post_uar0 = cmdif_use_uar0==1 ? TRUE : FALSE;\r
- \r
- if ( num_cmds_outs == 0 ) {\r
- mod_flags.num_cmds_outs = 0xffffffff;\r
- }\r
- else {\r
- mod_flags.num_cmds_outs = num_cmds_outs;\r
- }\r
- \r
- mod_flags.async_eq_size = async_eq_size;\r
- \r
- /* Create the Tavor HOB object */\r
- MTL_TRACE1("THH_init_hca: calling THH_hob_create: Tavor No %d\n", hca_num);\r
-\r
- return THH_hob_create(&hw_props, (u_int32_t)hca_num, &mod_flags, hh_hca_hndl_p);\r
-}\r
-\r
-\r
-/*\r
- * Remove a Tavor in device tables\r
- */\r
-HH_ret_t THH_rmv_hca(\r
- MT_size_t hca_num\r
- )\r
-{\r
- HH_hca_hndl_t *hh_list, hh_iterator;\r
- u_int32_t num_entries;\r
- HH_ret_t ret;\r
-\r
- /* get number of entries in the HCA registered devices table */\r
- HH_list_hcas(0, &num_entries, NULL);\r
- if (num_entries == 0) {\r
- /* no devices !! */\r
- MTL_TRACE1( "THH_rmv_hca: No HCAs registered\n");\r
- return (-1);\r
- }\r
- hh_list = (struct HH_hca_dev_st **)VMALLOC(num_entries * sizeof(HH_hca_hndl_t));\r
-\r
- /* get list of HH handles of all available devices */\r
- HH_list_hcas(num_entries, &num_entries, hh_list);\r
- if (num_entries < hca_num) {\r
- /* no our device !! */\r
- MTL_TRACE1( "THH_rmv_hca: No HCAs requested (%d)\n", hca_num);\r
- return (-1);\r
- }\r
-\r
- /* remove HCA */\r
- hh_iterator = hh_list[hca_num];\r
- if (hh_iterator->vendor_id == MT_MELLANOX_IEEE_VENDOR_ID &&\r
- hh_iterator->dev_id == MT23108_DEV_ID) {\r
- MTL_DEBUG3("THH_rmv_hca: removing the device %s\n", hh_iterator->dev_desc);\r
- ret = THH_hob_destroy(hh_iterator);\r
- if (ret == HH_OK) {\r
- MTL_DEBUG3("THH_rmv_hca: device removed successfully\n");\r
- } else {\r
- MTL_ERROR1("THH_rmv_hca: problems in removing device: THH_hob_destroy returned (%d)\n", ret);\r
- }\r
- }\r
-\r
- VFREE(hh_list);\r
- return ret;\r
-}\r
-\r
-int THH_init_module( THH_module_params_t *params_p)\r
-{\r
- HH_ret_t ret;\r
-\r
- MTL_TRACE('1', "%s: TAVOR device init_module() called\n", __func__);\r
-\r
- thh_legacy_sqp = params_p->thh_legacy_sqp;\r
- av_in_host_mem = params_p->av_in_host_mem;\r
- infinite_cmd_timeout = params_p->infinite_cmd_timeout; /* when 1 we use inifinite timeouts on commands completion */\r
- num_cmds_outs = params_p->num_cmds_outs; /* max number of outstanding commands */\r
- fatal_delay_halt = params_p->fatal_delay_halt;\r
- async_eq_size = params_p->async_eq_size;\r
- cmdif_use_uar0 = params_p->cmdif_use_uar0;\r
- ignore_subsystem_id = params_p->ignore_subsystem_id;\r
- \r
-\r
- ret = THH_init();\r
- if (ret != HH_OK) {\r
- MTL_ERROR('1', "init_module: THH_init failed (%d)\n", ret);\r
- return(-1);\r
- }\r
-\r
- MTL_TRACE('1', "THH: for all devices loaded\n");\r
- printk("<1>THH kernel module initialized successfully\n");\r
-\r
- return 0;\r
-}\r
-\r
-int THH_cleanup_module(void)\r
-{\r
- HH_ret_t ret;\r
- \r
- ret = THH_cleanup();\r
- if (ret != HH_OK) {\r
- MTL_ERROR('1', "cleanup_module: THH_cleanup failed (%d)\n", ret);\r
- return(0);\r
- }\r
- MTL_TRACE1("THH kernel module removed successfully\n");\r
- return 0;\r
-}\r
-\r
-#ifdef __KERNEL__\r
-\r
-\r
-/* ----- Kernel Space ----- */\r
-#ifndef MT_BUILD_LIB\r
-NTSTATUS \r
-DriverEntry(\r
- PDRIVER_OBJECT pi_pDriverObject,\r
- PUNICODE_STRING pi_pRegistryPath\r
- )\r
-{ /* DriverEntry */\r
-\r
- DbgPrint("\n***** THH_KL: DriverEntry()");\r
- return STATUS_SUCCESS;\r
-\r
-} /* DriverEntry */\r
-\r
-NTSTATUS DllInitialize(PUNICODE_STRING RegistryPath)\r
-{\r
- DbgPrint("\n***** THH_KL: DllInitialize()");\r
- return STATUS_SUCCESS;\r
-}\r
-\r
-NTSTATUS DllUnload()\r
-{\r
- DbgPrint("\n***** THH_KL DllUnload()");\r
- return STATUS_SUCCESS;\r
-}\r
-#endif\r
-#endif\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_THH_MOD_OBJ_H\r
-#define H_THH_MOD_OBJ_H\r
-\r
-#include <hh.h>\r
-\r
-typedef struct {\r
- int thh_legacy_sqp; /* if non-zero, indicates legacy sqp initialization */\r
- int av_in_host_mem; /* place AV ni the system memory */\r
- int infinite_cmd_timeout; /* when 1 we use inifinite timeouts on commands completion */\r
- int num_cmds_outs; /* max number of outstanding commands */\r
- int fatal_delay_halt; /* when 1, HALT_HCA on fatal is delayed to just before the reset */\r
- int async_eq_size; /* size of async event queue */\r
- int cmdif_use_uar0; /* when 1, cmdif posts commands to uar0 */\r
- int ignore_subsystem_id; /* when 1, we do not check the subsystem_vendor_id & subsystem_id */\r
-} THH_module_params_t;\r
-\r
-typedef struct {\r
- MOSAL_IRQ_ID_t irq;\r
- u_int8_t intr_pin;\r
-} card_intr_props_t;\r
-\r
-typedef struct {\r
- u_int8_t bus;\r
- u_int8_t dev_func;\r
- u_int16_t device_id;\r
- u_int16_t pci_vendor_id;\r
- u_int32_t hw_ver;\r
- MT_phys_addr_t cr_base;\r
- MT_phys_addr_t uar_base;\r
- MT_phys_addr_t ddr_base;\r
- card_intr_props_t interrupt_props;\r
-} card_hw_props_t;\r
-\r
-int THH_init_module( THH_module_params_t * params_p);\r
-int THH_cleanup_module(void);\r
-HH_ret_t THH_add_hca(\r
- MT_size_t hca_num,\r
- card_hw_props_t * hw_props_p, \r
- HH_hca_hndl_t * hh_hca_hndl_p\r
- );\r
- \r
-HH_ret_t THH_rmv_hca(\r
- MT_size_t hca_num\r
- );\r
-\r
-\r
-#endif\r
-EXPORTS\r
- ; for OS only\r
- DllInitialize private\r
- DllUnload private\r
- ; ----- Thhul_cqm.c -----\r
- THHUL_cqm_create\r
- THHUL_cqm_destroy \r
- THHUL_cqm_create_cq_prep\r
- THHUL_cqm_create_cq_done\r
- THHUL_cqm_destroy_cq_done\r
- THHUL_cqm_resize_cq_prep\r
- THHUL_cqm_resize_cq_done\r
- THHUL_cqm_cq_cleanup\r
- THHUL_cqm_poll4cqe\r
- THHUL_cqm_req_comp_notif\r
- ; ----- Thhul_hob.c -----\r
- THHUL_hob_create\r
- THHUL_hob_destroy\r
- THHUL_hob_query_version\r
- THHUL_hob_get_pdm\r
- THHUL_hob_get_cqm \r
- THHUL_hob_get_qpm \r
- THHUL_hob_get_uar \r
- THHUL_hob_get_mwm \r
- THHUL_hob_is_priv_ud_av\r
- ; ----- Thhul_mwm.c -----\r
- THHUL_mwm_create\r
- THHUL_mwm_destroy\r
- THHUL_mwm_alloc_mw\r
- THHUL_mwm_bind_mw\r
- THHUL_mwm_free_mw\r
- ; ----- Thhul_pdm.c -----\r
- THHUL_pdm_create \r
- THHUL_pdm_destroy \r
- THHUL_pdm_alloc_pd_prep \r
- THHUL_pdm_alloc_pd_done \r
- THHUL_pdm_free_pd_done \r
- THHUL_pdm_create_ud_av \r
- THHUL_pdm_modify_ud_av \r
- THHUL_pdm_query_ud_av \r
- THHUL_pdm_destroy_ud_av \r
-; THHUL_pdm_get_hh_pd\r
- THHUL_pdm_get_ud_av_memkey_sqp_ok\r
- ; ----- Thhul_qpm.c -----\r
- THHUL_qpm_create\r
- THHUL_qpm_destroy\r
- THHUL_qpm_create_qp_prep\r
- THHUL_qpm_special_qp_prep\r
- THHUL_qpm_create_qp_done\r
- THHUL_qpm_destroy_qp_done\r
- THHUL_qpm_modify_qp_done\r
- THHUL_qpm_post_send_req\r
- THHUL_qpm_post_recv_req\r
- THHUL_qpm_comp_ok\r
- THHUL_qpm_comp_err\r
- ; ----- Thhul_srqm.c -----\r
- THHUL_srqm_create_srq_prep\r
- THHUL_srqm_create_srq_done\r
- THHUL_srqm_destroy_srq_done\r
- THHUL_srqm_post_recv_reqs\r
\r
-/*\r
- This software is available to you under a choice of one of two\r
- licenses. You may choose to be licensed under the terms of the GNU\r
- General Public License (GPL) Version 2, available at\r
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD\r
- license, available in the LICENSE.TXT file accompanying this\r
- software. These details are also available at\r
- <http://openib.org/license.html>.\r
-\r
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- SOFTWARE.\r
-\r
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.\r
-*/\r
-\r
-#ifdef __KERNEL__\r
-\r
-#include "mtl_types.h"\r
-\r
-NTSTATUS \r
-DriverEntry(\r
- IN PDRIVER_OBJECT pi_pDriverObject,\r
- IN PUNICODE_STRING pi_pRegistryPath\r
- )\r
-{ /* DriverEntry */\r
-\r
- DbgPrint("\n***** THHUL_KL: DriverEntry()");\r
- return STATUS_SUCCESS;\r
-\r
-} /* DriverEntry */\r
-\r
-NTSTATUS DllInitialize(PUNICODE_STRING RegistryPath)\r
-{\r
- DbgPrint("\n***** THHUL_KL: DllInitialize()");\r
- return STATUS_SUCCESS;\r
-}\r
-\r
-NTSTATUS DllUnload()\r
-{\r
- DbgPrint("\n***** THHUL_KL: DllUnload()");\r
- return STATUS_SUCCESS;\r
-}\r
-#endif\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_THH_H\r
-#define H_THH_H\r
-\r
-#include "thh_common.h"\r
-\r
-#define THH_VMALLOC_THRESHOLD (2*MOSAL_SYS_PAGE_SIZE)\r
-\r
-#ifdef __LINUX__\r
-#define THH_SMART_MALLOC(size) ({ \\r
- void *p; \\r
- if ( (size) > THH_VMALLOC_THRESHOLD ) { \\r
- p = VMALLOC(size); \\r
- } \\r
- else { \\r
- p = MALLOC(size); \\r
- } \\r
- p; \\r
- })\r
-\r
-\r
-\r
-\r
-#define THH_SMART_FREE(ptr,size) do { \\r
- if ( (size) > THH_VMALLOC_THRESHOLD ) { \\r
- VFREE(ptr); \\r
- } \\r
- else { \\r
- FREE(ptr); \\r
- } \\r
- } \\r
- while(0)\r
-#else\r
-#define THH_SMART_MALLOC(size) VMALLOC(size)\r
-#define THH_SMART_FREE(ptr,size) VFREE(ptr)\r
-#endif \r
-\r
-#define THH_FW_VER_VALUE(major,minor,subminor) \\r
- ( (((u_int64_t)(major)) << 32) | (((u_int64_t)(minor)) << 16) | ((u_int64_t)(subminor)) )\r
-\r
-\r
-/* THH objects handles */\r
-typedef struct THH_hob_st *THH_hob_t;\r
-typedef MT_ulong_ptr_t THH_cmd_t; /* type to identify the cmdif object */\r
-typedef struct THH_eventp_st *THH_eventp_t;\r
-typedef struct THH_ddrmm_st *THH_ddrmm_t;\r
-typedef struct THH_uldm_st *THH_uldm_t;\r
-typedef struct THH_mrwm_st *THH_mrwm_t; \r
-typedef struct THH_cqm_st *THH_cqm_t;\r
-typedef struct THH_qpm_st *THH_qpm_t;\r
-typedef struct THH_srqm_st *THH_srqm_t;\r
-typedef struct THH_mcgm_st *THH_mcgm_t;\r
-typedef struct THH_sqp_demux_st *THH_sqp_demux_t;\r
-\r
-\r
-\r
-/* event's handlers types */\r
-typedef u_int8_t THH_event_type_t;\r
-typedef u_int8_t THH_event_subtype_t;\r
-typedef void (*THH_mlx_eventh_t)(HH_hca_hndl_t hh_hndl, \r
- THH_event_type_t event_type,\r
- THH_event_subtype_t event_subtype,\r
- void* event_data, \r
- void* private_data);\r
-\r
-typedef union {\r
- HH_comp_eventh_t comp_event_h;\r
- HH_async_eventh_t ib_comp_event_h;\r
- THH_mlx_eventh_t mlx_event_h;\r
-}THH_eventp_handler_t;\r
-\r
-/* structure for passing module flags or parameters from 'insmod' to THH_hob_create */\r
-typedef struct THH_module_flags_st {\r
- MT_bool legacy_sqp; /* TRUE if should perform INIT_IB in THH_hob_open_hca */\r
- MT_bool av_in_host_mem; /* TRUE if udav's should use host memory. */\r
- /* FALSE if udav's should use DDR SDRAM on Tavor */\r
- MT_bool inifinite_cmd_timeout; /* when TRUE cmdif will wait infinitely for the completion of a command */\r
- MT_bool fatal_delay_halt; /* when TRUE, HALT_HCA/disable on fatal error will be delayed to before the reset */\r
- u_int32_t num_cmds_outs; /* max number of outstanding commands that will be used by the driver\r
- The real value will not exceed tha value reported by fw */\r
- u_int32_t async_eq_size; /* The size of the async event queue (max # of outstanding async events) */\r
- MT_bool cmdif_post_uar0; /* when TRUE cmdif will post commands to uar0 */\r
-} THH_module_flags_t;\r
-\r
-/*\r
- * THH_hob_state_t tracks the status of an HCA -- is it OK, or has a fatal error occurred.\r
- * Actually, the states used in practice use the FATAL states as modifiers of the base states.\r
- * Thus, the states we may see in practice are:\r
- * THH_STATE_CREATING, THH_STATE_OPENING, THH_STATE_RUNNING, THH_STATE_CLOSING, THH_STATE_DESTROYING\r
- * and fatal modifiers on these states:\r
- * \r
- * THH_STATE_CREATING | THH_STATE_FATAL_HCA_HALTED\r
- * THH_STATE_OPENING | THH_STATE_FATAL_HCA_HALTED\r
- * \r
- * THH_STATE_RUNNING | THH_STATE_FATAL_START\r
- * THH_STATE_RUNNING | THH_STATE_FATAL_HCA_HALTED\r
- *\r
- * THH_STATE_CLOSING | THH_STATE_FATAL_HCA_HALTED\r
- * THH_STATE_DESTROYING | THH_STATE_FATAL_HCA_HALTED\r
- *\r
- * Note that in the RUNNING state, have two FATAL possibilities. When FATAL first occurs,\r
- * we enter the RUNNING/FATAL_START state, in which all commands and all calls to THH\r
- * (with very few exceptions) return FATAL. In addition, we attempt to halt the HCA.\r
- * After the halt-hca attempt returns, we enter the RUNNING/FATAL-HCA-HALTED state.\r
- * \r
- */\r
-enum {\r
- THH_STATE_NONE = 0,\r
- THH_STATE_CREATING = 0x1, \r
- THH_STATE_CLOSED = 0x2, \r
- THH_STATE_OPENING = 0x4, \r
- THH_STATE_RUNNING = 0x8, \r
- THH_STATE_CLOSING = 0x10, \r
- THH_STATE_DESTROYING= 0x20, \r
- THH_STATE_FATAL_START = 0x40, /* CATASTROPHIC EVENT has been reported */\r
- THH_STATE_FATAL_HCA_HALTED = 0x80 /* Failed HCA has been halted */\r
-};\r
-typedef u_int32_t THH_hob_state_t;\r
-\r
-#define THH_STATE_HAVE_ANY_FATAL (THH_STATE_FATAL_START | THH_STATE_FATAL_HCA_HALTED)\r
-\r
-/* Fatal event type enumeration, for passing to fatal event handlers */\r
-typedef enum {\r
- THH_FATAL_NONE, \r
- THH_FATAL_MASTER_ABORT, /* detected master abort */\r
- THH_FATAL_GOBIT, /* GO bit of HCR remains set (i.e., stuck) */\r
- THH_FATAL_CMD_TIMEOUT, /* timeout on a command execution */\r
- THH_FATAL_EQ_OVF, /* an EQ has overflowed */\r
- THH_FATAL_EVENT, /* firmware has generated a LOCAL CATASTROPHIC ERR event */\r
- THH_FATAL_CR, /* unexpected read from CR-space */\r
- THH_FATAL_TOKEN, /* invalid token on command completion */\r
- THH_FATAL_EXTERNAL, /* externally-generated artificial fatal via THH_hob_external_fatal */\r
- THH_FATAL_END /* indicates end of fatal error codes */\r
-} THH_fatal_err_t;\r
-\r
-#endif /* H_THH_H */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_THH_COMMON_H\r
-#define H_THH_COMMON_H\r
-\r
-\r
-#include <mtl_common.h>\r
-#include <vapi.h>\r
-#include <hh.h>\r
-#include <tlog2.h>\r
-\r
-/* resources reserved in driver */\r
-#define THH_NUM_RSVD_PD 2\r
-#define THH_NUM_RSVD_QP 8\r
-\r
-/* this macro ensure that total buff size is power of 2 and one extra entry for the cyclic buffer */\r
-#define THH_CYCLIC_BUFF_SIZE(entries) ((MT_size_t)1<<(floor_log2(entries)+1))\r
-\r
-typedef u_int32_t THH_eqn_t;\r
-#define THH_INVALID_EQN 0xFFFFFFFF\r
-\r
-typedef struct THH_udavm_st *THH_udavm_t; /* type to identify the udav object */\r
-typedef u_int32_t THH_uar_index_t;\r
-typedef struct THH_uar_st *THH_uar_t;\r
-\r
-\r
-#pragma warning( disable : 4201 )\r
-\r
-/* VERSION INFORMATION: used in order to retrieve major version numbers \r
- in order to deal with differences in different versions. */\r
-typedef struct THH_ver_info_st {\r
- u_int32_t hw_ver; /* HW version (stepping etc.)*/ \r
- u_int16_t fw_ver_major; /* Firmware major version */ \r
- u_int16_t fw_ver_minor; /* Firmware minor version */ \r
- u_int16_t fw_ver_subminor; /* Firmware Sub-minor version (Patch level). */\r
- u_int16_t cmd_if_ver; /* Command interface version */\r
-}THH_ver_info_t;\r
-\r
-typedef struct THH_hca_ul_resources_st {\r
- HH_hca_hndl_t hh_hca_hndl;\r
- THH_ver_info_t version;\r
- THH_uar_index_t uar_index;\r
- union\r
- {\r
- MT_virt_addr_t uar_map;\r
- void* __ptr64 resv0;\r
- };\r
- /* HCA capabilities to validate or use in THHUL */\r
- MT_bool priv_ud_av; /* Privileged UD AV are enforced ? */\r
- u_int32_t log2_mpt_size;\r
- char * __ptr64 av_ddr_base;\r
- char * __ptr64 av_host_base;\r
-\r
- u_int32_t max_qp_ous_wr; /* Maximum Number of oustanding WR on any WQ. */ \r
- u_int32_t max_srq_ous_wr; /* Maximum Number of oustanding WR on any WQ. */ \r
- u_int32_t max_num_sg_ent; /* Max num of scatter/gather entries for desc other than RD */\r
- u_int32_t max_num_sg_ent_srq; /* Max num of scatter/gather entries for SRQs */\r
- u_int32_t max_num_sg_ent_rd; /* Max num of scatter/gather entries for RD desc */\r
- u_int32_t max_num_ent_cq; /* Max num of supported entries per CQ */\r
-} THH_hca_ul_resources_t;\r
-\r
-typedef struct THH_pd_ul_resources_st {\r
- /* if user-level udavm_buf is used (i.e., non-zero), it should be malloc'ed\r
- * with size = (udavm_buf_sz + (1 udav entry size)), to allow the kernel level\r
- * to align the start of the udavm table to the entry size -- so some spare is\r
- * needed. Therefore, the udavm_buf_size value is the size of the actual udavm\r
- * table, not the size of the malloc'ed buffer.\r
- */\r
- union\r
- {\r
- MT_virt_addr_t udavm_buf; /* IN */\r
- void* __ptr64 resv0;\r
- };\r
- union\r
- {\r
- MT_size_t udavm_buf_sz; /* IN */\r
- void* __ptr64 resv1;\r
- };\r
- HH_pdm_pd_flags_t pd_flags; /* IN - if non-zero, is a PD for a special QP*/\r
- VAPI_lkey_t udavm_buf_memkey; /* OUT - set by THH_uldm */\r
-} THH_pd_ul_resources_t;\r
-\r
-typedef struct\r
-{\r
- union\r
- {\r
- MT_virt_addr_t cqe_buf; /* CQE buffer virtual addr. CQE size aligned */\r
- void* __ptr64 resv0;\r
- };\r
- union\r
- {\r
- MT_size_t cqe_buf_sz; /* Buffer size in bytes (mult of CQE size) */\r
- void* __ptr64 resv1;\r
- };\r
- THH_uar_index_t uar_index; /* Index of UAR used for this CQ. */\r
- u_int32_t new_producer_index; /* New producer index after "resize_cq" (OUT)*/\r
-} THH_cq_ul_resources_t;\r
-\r
-typedef struct \r
-{\r
- union\r
- {\r
- MT_virt_addr_t wqes_buf; /* WQEs buffer virtual address */\r
- void* __ptr64 resv0;\r
- };\r
- union\r
- {\r
- MT_size_t wqes_buf_sz; /* Buffer size in bytes */\r
- void* __ptr64 resv1;\r
- };\r
- THH_uar_index_t uar_index; /* index of UAR used for this QP */\r
- /* ER: Not used anywhere: MT_virt_addr_t uar_map; */ /* Address in user space of UAR */\r
-} THH_qp_ul_resources_t;\r
-\r
-typedef struct \r
-{\r
- union\r
- {\r
- MT_virt_addr_t wqes_buf; /* WQEs buffer virtual address */\r
- void* __ptr64 resv0;\r
- };\r
- union\r
- {\r
- MT_size_t wqes_buf_sz; /* Buffer size in bytes */\r
- void* __ptr64 resv1;\r
- };\r
- union\r
- {\r
- MT_size_t wqe_sz; /* WQE (descriptor) size in bytes */\r
- void* __ptr64 resv2;\r
- };\r
- THH_uar_index_t uar_index; /* index of UAR used for this QP */\r
-} THH_srq_ul_resources_t;\r
-\r
-#pragma warning( default : 4201 )\r
-#endif /* H_THH_COMMON_H */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "tcqm.h"\r
-#if defined(USE_STD_MEMORY)\r
-# include <memory.h>\r
-#endif\r
-#include <mtl_common.h>\r
-#include <epool.h>\r
-#include <tlog2.h>\r
-#include <cmdif.h>\r
-#include <thh_hob.h>\r
-#include <hh_common.h>\r
-#include <tmrwm.h>\r
-\r
-#include <cr_types.h>\r
-#include <MT23108_PRM.h>\r
-\r
-\r
-#define logIfErr(f) \\r
- if (rc != HH_OK) { MTL_ERROR1("%s: rc=%s\n", f, HH_strerror_sym(rc)); }\r
-\r
-/* macro for translating cmd_rc return codes for non-destroy procs */\r
-#define CMDRC2HH_ND(cmd_rc) ((cmd_rc == THH_CMD_STAT_OK) ? HH_OK : \\r
- (cmd_rc == THH_CMD_STAT_EINTR) ? HH_EINTR : HH_EFATAL)\r
-\r
-#define CMDRC2HH_BUSY(cmd_rc) ((cmd_rc == THH_CMD_STAT_OK) ? HH_OK : \\r
- (cmd_rc == THH_CMD_STAT_EINTR) ? HH_EINTR : \\r
- ((cmd_rc == THH_CMD_STAT_RESOURCE_BUSY) || \\r
- (cmd_rc == THH_CMD_STAT_REG_BOUND)) ? HH_EBUSY : HH_EFATAL)\r
- \r
-#define TCQM_CQN(cqm,cqc_index) \\r
- ( ( ((cqm)->entries[cqc_index].cqn_prefix) << (cqm)->log2_max_cq ) | (cqc_index) )\r
-\r
-enum\r
-{\r
- CQE_size = sizeof(struct tavorprm_completion_queue_entry_st)/8, /* 32 */\r
- CQE_size_log2 = 5,\r
- CQE_size_mask = (1ul << CQE_size_log2) - 1\r
-};\r
-\r
-typedef struct Completion_Queue_Context Completion_Queue_Context_t;\r
-\r
-typedef struct\r
-{\r
- unsigned long prev;\r
- unsigned long next;\r
-} _cq_free_offs_t;\r
-\r
-\r
-/* Completion Queue Context Manager - entry info */\r
-typedef struct CQCM_entry_s\r
-{\r
- /* THH_cq_props_t props; / * May be optimzed out, using CmdIf output */\r
- unsigned long n_cq; /* With buf_sz, may just recompute and save needed */\r
- VAPI_lkey_t lkey;\r
- MOSAL_protection_ctx_t user_protection_context; /*Save protection context to be used on resize*/\r
-#if defined(MT_SUSPEND_QP)\r
- MT_bool is_suspended;\r
-#endif\r
-} CQCM_entry_t;\r
-\r
-\r
-/* Completion Queue Context Manager - entry */\r
-typedef struct\r
-{\r
- union\r
- {\r
- CQCM_entry_t used;\r
- _cq_free_offs_t freelist;\r
- } u;\r
- unsigned char cqn_prefix:7; /* CQ number - avoid ghost CQ events (FM issue #15134) */\r
- unsigned char in_use :1;\r
-} CQCM_entry_ut;\r
-\r
-static const EPool_meta_t fl_meta =\r
- {\r
- sizeof(CQCM_entry_ut),\r
- (unsigned int)(MT_ulong_ptr_t)(&(((CQCM_entry_ut*)(0))->u.freelist.prev)),\r
- (unsigned int)(MT_ulong_ptr_t)(&(((CQCM_entry_ut*)(0))->u.freelist.next))\r
- };\r
-\r
-\r
-/* The main CQ-manager structure */\r
-typedef struct THH_cqm_st\r
-{\r
- THH_hob_t hob;\r
- u_int8_t log2_max_cq;\r
- u_int32_t max_cq;\r
- CQCM_entry_ut* entries;\r
- EPool_t flist;\r
-\r
- /* convenient handle saving */\r
- THH_cmd_t cmd_if;\r
- THH_mrwm_t mrwm_internal;\r
-\r
- MT_bool cq_resize_fixed; /* FW fix for FM issue #16966/#17002: comp. events during resize */\r
-} TCQM_t;\r
-\r
-\r
-/************************************************************************/\r
-/************************************************************************/\r
-/* private functions */\r
-/************************************************************************/\r
-\r
-#if MAX_TRACE >= 1\r
-static char* ulr_print(char* buf, const THH_cq_ul_resources_t* p)\r
-{\r
- sprintf(buf, "{CQulRes: buf="VIRT_ADDR_FMT", sz="SIZE_T_FMT", uar=%d}",\r
- p->cqe_buf, p->cqe_buf_sz, p->uar_index);\r
- return buf;\r
-} /* ulr_print */\r
-#endif\r
-\r
-\r
-/************************************************************************/\r
-static inline MT_bool in_use_cq(TCQM_t* cqm, HH_cq_hndl_t cq)\r
-{\r
- u_int32_t cqc_index= cq & MASK32(cqm->log2_max_cq);\r
- MT_bool in_use = (cqc_index < cqm->max_cq) && cqm->entries[cqc_index].in_use;\r
- if (!in_use) { MTL_ERROR2(MT_FLFMT("unused cq=0x%x"), cq); }\r
- return in_use;\r
-} /* in_use_cq */\r
-\r
-\r
-/************************************************************************/\r
-static HH_ret_t sw2hw_cq\r
-(\r
- THH_cmd_t cmd_if,\r
- THH_cq_ul_resources_t* user_prot_ctx_p,\r
- u_int32_t cqn, \r
- unsigned long n_cq_entries,\r
- VAPI_lkey_t lkey,\r
- THH_eqn_t comp_eqn,\r
- THH_eqn_t error_eqn\r
-)\r
-{\r
- THH_cqc_t cqc;\r
- THH_cmd_status_t cmd_rc;\r
-\r
- memset(&cqc, 0, sizeof(THH_cqc_t));\r
- cqc.st = 0; /* disarmed */\r
-#ifdef NO_CQ_CI_DBELL\r
- /* Use this option carefully - CQ overrun may cause unexpected behavior */\r
- /* It is recommended to set CQ size to be the total of max. outstanding */\r
- /* WQEs of all attached work queues. */\r
- cqc.oi = 1;/*CQ's consumer index update DBells are not used - must ignore CQ overrun*/\r
-#else\r
- cqc.oi = 0;/* Enforce CQ overrun detection based on consumer index doorbells updates*/\r
-#endif\r
- cqc.tr = 1;\r
- cqc.status = 0;\r
- cqc.start_address = user_prot_ctx_p->cqe_buf;\r
- cqc.usr_page = user_prot_ctx_p->uar_index;\r
- cqc.log_cq_size = floor_log2(n_cq_entries);\r
- cqc.e_eqn = error_eqn;\r
- cqc.c_eqn = comp_eqn;\r
- cqc.pd = THH_RESERVED_PD;\r
- cqc.l_key = lkey;\r
- cqc.cqn = cqn;\r
-\r
- cmd_rc = THH_cmd_SW2HW_CQ(cmd_if, cqn, &cqc);\r
- MTL_DEBUG4(MT_FLFMT("cmd_rc=%d=%s"), cmd_rc, str_THH_cmd_status_t(cmd_rc));\r
- return (CMDRC2HH_ND(cmd_rc));\r
-} /* sw2hw_cq */\r
-\r
-\r
-/************************************************************************/\r
-static HH_ret_t hw2sw_cq\r
-(\r
- THH_cmd_t cmd_if,\r
- u_int32_t cqn\r
-)\r
-{\r
- THH_cmd_status_t cmd_rc;\r
- cmd_rc = THH_cmd_HW2SW_CQ(cmd_if, cqn, NULL);\r
- return (CMDRC2HH_ND(cmd_rc));\r
-} /* hw2sw_cq */\r
-\r
-\r
-/************************************************************************/\r
-/************************************************************************/\r
-/* interface functions */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_cqm_create(\r
- THH_hob_t hob, /* IN */\r
- u_int8_t log2_max_cq, /* IN */\r
- u_int8_t log2_rsvd_cqs, /* IN */\r
- THH_cqm_t* cqm_p /* OUT */\r
-)\r
-{\r
- THH_cmd_t cmd_if;\r
- THH_ver_info_t version;\r
- HH_ret_t rc = THH_hob_get_cmd_if(hob, &cmd_if);\r
- TCQM_t* cqm = 0;\r
- CQCM_entry_ut* entries = 0;\r
- unsigned long ncq = 1ul << log2_max_cq;\r
- unsigned long tavor_num_reserved_cqs = 1ul << log2_rsvd_cqs;\r
- MTL_TRACE1("{THH_cqm_create: hob=%p, log2_max_cq=%d, rsvd_cqs=%lu\n", \r
- hob, log2_max_cq, tavor_num_reserved_cqs);\r
-\r
-#ifdef NO_CQ_CI_DBELL\r
- MTL_ERROR4(MT_FLFMT("WARNING: HCA driver is in CQ-Overrun-Ignore mode !"));\r
-#endif\r
- \r
- if (rc == HH_OK) {\r
- rc= THH_hob_get_ver_info(hob, &version);\r
- }\r
- if (rc == HH_OK)\r
- {\r
- cqm = TMALLOC(TCQM_t);\r
- entries = ((log2_max_cq < 24) && (ncq > tavor_num_reserved_cqs)\r
- ? TNVMALLOC(CQCM_entry_ut, ncq)\r
- : NULL);\r
- if (!(cqm && entries))\r
- {\r
- rc = HH_EAGAIN; MTL_ERROR2(MT_FLFMT(""));\r
- }\r
- else\r
- {\r
- HH_ret_t hob_rc;\r
- /* clearing is needed, but for the sake of consistency */\r
- memset(cqm, 0, sizeof(TCQM_t));\r
- memset(entries, 0, ncq * sizeof(CQCM_entry_ut));\r
- hob_rc = THH_hob_get_mrwm(hob, &cqm->mrwm_internal);\r
- if (hob_rc != HH_OK)\r
- {\r
- rc = HH_EAGAIN; MTL_ERROR2(MT_FLFMT(""));\r
- }\r
- }\r
- }\r
- if (rc == HH_OK)\r
- {\r
- cqm->hob = hob;\r
- cqm->cmd_if = cmd_if;\r
- cqm->log2_max_cq = log2_max_cq;\r
- cqm->max_cq = ncq;\r
- cqm->entries = entries;\r
- cqm->flist.entries = entries;\r
- cqm->flist.size = ncq;\r
- cqm->flist.meta = &fl_meta;\r
- epool_init(&cqm->flist);\r
- /* reserve is simpler than using an offset */\r
- epool_reserve(&cqm->flist, 0, tavor_num_reserved_cqs); \r
-\r
- cqm->cq_resize_fixed= (version.fw_ver_major >= 3);\r
- rc = HH_OK;\r
- *cqm_p = cqm;\r
- }\r
- else\r
- {\r
- if (entries) {VFREE(entries);}\r
- if (cqm) {FREE(cqm);}\r
- }\r
- MTL_TRACE1("}THH_cqm_create: cqm=%p\n", cqm);\r
- logIfErr("THH_cqm_create");\r
- return rc;\r
-} /* THH_cqm_create */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_cqm_destroy(\r
- THH_cqm_t cqm, /* IN */\r
- MT_bool hca_failure /* IN */\r
-)\r
-{\r
- HH_ret_t rc = HH_OK;\r
- MTL_TRACE1("{THH_cqm_destroy: cqm=%p, hca_failure=%d\n", cqm, hca_failure);\r
- if (!hca_failure)\r
- {\r
- CQCM_entry_ut* e = cqm->entries;\r
- CQCM_entry_ut* e_end = e + cqm->max_cq;\r
- THH_mrwm_t mrwm_internal = cqm->mrwm_internal;\r
- int any_busy = 0;\r
- for (; (e != e_end) && (rc == HH_OK); ++e)\r
- {\r
- if (e->in_use)\r
- {\r
- HH_ret_t mrrc = THH_mrwm_deregister_mr(mrwm_internal, e->u.used.lkey);\r
- switch (mrrc)\r
- {\r
- case HH_OK:\r
- break;\r
- case HH_EINVAL:\r
- rc = HH_EINVAL; MTL_ERROR2(MT_FLFMT(""));\r
- break;\r
- case HH_EBUSY:\r
- any_busy = 1; MTL_ERROR2(MT_FLFMT("")); /* Cannot happen! */\r
- break;\r
- default: MTL_ERROR2(MT_FLFMT(""));\r
- }\r
- }\r
- }\r
- if (any_busy) { rc = HH_EINVAL; } /* again... should not happen */\r
- }\r
- epool_cleanup(&cqm->flist);\r
- VFREE(cqm->entries);\r
- FREE(cqm);\r
- MTL_TRACE1("}THH_cqm_destroy\n");\r
- logIfErr("THH_cqm_destroy");\r
- return rc;\r
-} /* THH_cqm_destroy */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_cqm_create_cq(\r
- THH_cqm_t cqm, /* IN */\r
- MOSAL_protection_ctx_t user_protection_context, /* IN */\r
- THH_eqn_t comp_eqn, /* IN */\r
- THH_eqn_t error_eqn, /* IN */\r
- THH_cq_ul_resources_t* cq_ul_resources_p, /* IO */\r
- HH_cq_hndl_t* cq_p /* OUT */\r
-)\r
-{\r
- MT_virt_addr_t cqe_buf = cq_ul_resources_p->cqe_buf;\r
- MT_virt_addr_t unalligned_bits = cqe_buf & CQE_size_mask;\r
- MT_size_t buf_sz = cq_ul_resources_p->cqe_buf_sz;\r
- MT_size_t residue = buf_sz % CQE_size;\r
- HH_ret_t rc = ((unalligned_bits == 0) && (residue == 0)\r
- ? HH_OK : HH_EINVAL);\r
- u_int32_t new_cqn= 0xFFFFFFFF; /* Initialize to invalid CQN */\r
-#if MAX_TRACE >= 1\r
- char ulr_tbuf[256], *ulr_buf = &ulr_tbuf[0];\r
-#ifndef __DARWIN__\r
- MTL_TRACE1("{THH_cqm_create_cq: cqm=%p, ctx=0x%x, Ceqn=0x%x, Eeqn=0x%x\n"\r
- " %s\n", cqm, user_protection_context, comp_eqn, error_eqn,\r
- ulr_print(ulr_buf, cq_ul_resources_p));\r
-#else\r
- MTL_TRACE1("{THH_cqm_create_cq: cqm=%p, Ceqn=0x%x, Eeqn=0x%x\n"\r
- " %s\n", cqm, comp_eqn, error_eqn,\r
- ulr_print(ulr_buf, cq_ul_resources_p));\r
-#endif\r
-#endif\r
- if (rc == HH_OK)\r
- {\r
- VAPI_lkey_t lkey;\r
- HH_ret_t mr_rc = HH_ERR;\r
- unsigned long n_cq_entries = (unsigned long)(buf_sz / CQE_size);\r
- u_int32_t cqc_index = epool_alloc(&cqm->flist);\r
- rc = HH_ENOSYS; /* pessimistic */\r
- if (cqc_index != EPOOL_NULL)\r
- {\r
- THH_internal_mr_t mr_internal;\r
- memset(&cqm->entries[cqc_index], 0, sizeof(CQCM_entry_ut));\r
- memset(&mr_internal, 0, sizeof(mr_internal));\r
- mr_internal.start = cq_ul_resources_p->cqe_buf;\r
- mr_internal.size = buf_sz;\r
- mr_internal.pd = THH_RESERVED_PD;\r
- mr_internal.vm_ctx = user_protection_context;\r
- mr_internal.force_memkey = FALSE;\r
- mr_internal.memkey = (VAPI_lkey_t)0;\r
-\r
- mr_rc = THH_mrwm_register_internal(\r
- cqm->mrwm_internal, &mr_internal, &lkey);\r
- new_cqn= ( ++(cqm->entries[cqc_index].cqn_prefix) << cqm->log2_max_cq ) | cqc_index;\r
- rc = ((mr_rc == HH_OK)\r
- ? sw2hw_cq(cqm->cmd_if, cq_ul_resources_p, new_cqn, n_cq_entries,\r
- lkey, comp_eqn, error_eqn)\r
- : mr_rc);\r
- MTL_DEBUG4(MT_FLFMT("mr=%d=%s, rc=%d=%s"), \r
- mr_rc, HH_strerror_sym(mr_rc), rc, HH_strerror_sym(rc));\r
- }\r
-\r
- else {\r
- MTL_ERROR2(MT_FLFMT("CQ pool is drained.\n"));\r
- rc = HH_EAGAIN;\r
- }\r
-\r
- if (rc == HH_OK)\r
- {\r
- /* cqm->entries[cq].u.used.props = *cq_props_p; */\r
- cqm->entries[cqc_index].u.used.n_cq = n_cq_entries;\r
- cqm->entries[cqc_index].u.used.lkey = lkey;\r
- /* Save protection context for CQ-resize */\r
- cqm->entries[cqc_index].u.used.user_protection_context= user_protection_context;\r
- cqm->entries[cqc_index].in_use = 1;\r
-#if defined(MT_SUSPEND_QP)\r
- cqm->entries[cqc_index].u.used.is_suspended = FALSE;\r
-#endif\r
- *cq_p = new_cqn;\r
- }\r
- else /* clean */\r
- {\r
- MTL_ERROR2(MT_FLFMT("fail, now clean"));\r
- if (mr_rc == HH_OK)\r
- {\r
- (void)THH_mrwm_deregister_mr(cqm->mrwm_internal, lkey);\r
- }\r
- if (cqc_index != EPOOL_NULL)\r
- {\r
- epool_free(&cqm->flist, cqc_index);\r
- }\r
- }\r
- }\r
- MTL_TRACE1("}THH_cqm_create_cq, cq=0x%x\n", *cq_p);\r
- logIfErr("THH_cqm_create_cq");\r
- return rc;\r
-} /* THH_cqm_create_cq */\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_cqm_resize_cq(\r
- THH_cqm_t cqm, /* IN */\r
- HH_cq_hndl_t cq, /* IN */\r
- THH_cq_ul_resources_t* cq_ul_resources_p /* IO */\r
-)\r
-{\r
- MT_virt_addr_t cqe_buf = cq_ul_resources_p->cqe_buf;\r
- MT_virt_addr_t unalligned_bits = cqe_buf & CQE_size_mask;\r
- MT_size_t buf_sz = cq_ul_resources_p->cqe_buf_sz;\r
- MT_size_t residue = buf_sz % CQE_size;\r
- VAPI_lkey_t lkey;\r
- unsigned long n_cq_entries = (unsigned long)(buf_sz / CQE_size);\r
- CQCM_entry_ut* sw_cqc_p;\r
- THH_internal_mr_t mr_internal;\r
- THH_cmd_status_t cmd_rc;\r
- HH_ret_t rc;\r
- \r
- /* Validate parameters */\r
- if (!in_use_cq(cqm, cq)) {\r
- MTL_ERROR1(MT_FLFMT("Invalid CQ handle (0x%X)"),cq);\r
- return HH_EINVAL_CQ_HNDL;\r
- }\r
- sw_cqc_p = &cqm->entries[cq & MASK32(cqm->log2_max_cq)];\r
-\r
- if ((unalligned_bits != 0) || (residue != 0) || (buf_sz == 0)) {\r
- MTL_ERROR1(MT_FLFMT("%s: Invalid CQEs buffer (va="VIRT_ADDR_FMT" , size="SIZE_T_FMT")"),\r
- __func__,cqe_buf,buf_sz);\r
- return HH_EINVAL;\r
- }\r
-\r
- /* Register new CQEs buffer */\r
- memset(&mr_internal, 0, sizeof(mr_internal));\r
- mr_internal.start = cq_ul_resources_p->cqe_buf;\r
- mr_internal.size = buf_sz;\r
- mr_internal.pd = THH_RESERVED_PD;\r
- mr_internal.vm_ctx = sw_cqc_p->u.used.user_protection_context;\r
- mr_internal.force_memkey = FALSE;\r
- mr_internal.memkey = (VAPI_lkey_t)0;\r
-\r
- rc= THH_mrwm_register_internal(cqm->mrwm_internal, &mr_internal, &lkey);\r
- if (rc != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed registering new CQEs buffer (%s)"),\r
- __func__,HH_strerror_sym(rc));\r
- return rc;\r
- }\r
- \r
- cmd_rc= THH_cmd_RESIZE_CQ(cqm->cmd_if, cq, cqe_buf, lkey, floor_log2(n_cq_entries),\r
- cqm->cq_resize_fixed ? NULL : &cq_ul_resources_p->new_producer_index);\r
- if (cmd_rc != THH_CMD_STAT_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed command RESIZE_CQ (%s)"),\r
- __func__,str_THH_cmd_status_t(cmd_rc));\r
- switch (cmd_rc) {\r
- case THH_CMD_STAT_BAD_SIZE:\r
- rc= HH_E2BIG_CQE_NUM; /* Retry after polling some CQEs */\r
- break;\r
- case THH_CMD_STAT_BAD_RES_STATE: /* CQ in error state or does not exist anymore */\r
- case THH_CMD_STAT_BAD_INDEX: /* Wrong CQ number */\r
- rc= HH_EINVAL_CQ_HNDL; \r
- break;\r
- case THH_CMD_STAT_BAD_OP:\r
- rc= HH_ENOSYS; /* Probably old firmware */\r
- break;\r
- case THH_CMD_STAT_EINTR:\r
- rc = HH_EINTR;\r
- break;\r
- default:\r
- rc= HH_EFATAL; /* Unexpected error */\r
- break;\r
- }\r
- (void)THH_mrwm_deregister_mr(cqm->mrwm_internal, lkey); /* deregister new buffer */\r
- return rc;\r
- }\r
- \r
- rc= THH_mrwm_deregister_mr(cqm->mrwm_internal, sw_cqc_p->u.used.lkey);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: Failed deregistration of old CQEs buffer (%s) !!"),\r
- __func__,HH_strerror_sym(rc));\r
- /* Nothing we can do about old CQEs region but anyway nobody uses it for any other resource */\r
- }\r
- /* Save new parameters of the CQ */\r
- sw_cqc_p->u.used.n_cq = n_cq_entries;\r
- sw_cqc_p->u.used.lkey = lkey;\r
- \r
- return HH_OK;\r
-}\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_cqm_destroy_cq(\r
- THH_cqm_t cqm /* IN */,\r
- HH_cq_hndl_t cq /* IN */\r
-)\r
-{\r
- u_int32_t cqc_index= cq & MASK32(cqm->log2_max_cq);\r
- HH_ret_t rc = HH_EINVAL_CQ_HNDL;\r
- MTL_TRACE1("{THH_cqm_destroy_cq, cqm=%p, cq=0x%x\n", cqm, cq);\r
- if (in_use_cq(cqm, cq))\r
- {\r
- rc = hw2sw_cq(cqm->cmd_if, cq);\r
- if ((rc == HH_OK) || (rc == HH_EFATAL))\r
- {\r
- CQCM_entry_ut* e = &cqm->entries[cqc_index];\r
- THH_cmd_status_t mrrc = THH_mrwm_deregister_mr(cqm->mrwm_internal,\r
- e->u.used.lkey);\r
- if (mrrc != THH_CMD_STAT_OK)\r
- {\r
- MTL_ERROR1(MT_FLFMT("%s: Failed deregistration of CQEs buffer (%s) !!"),\r
- __func__,str_THH_cmd_status_t(mrrc));\r
- rc = CMDRC2HH_BUSY(mrrc);\r
- }\r
- else\r
- {\r
- /* If we are in a fatal error, return OK for destruction */\r
- if (rc == HH_EFATAL){\r
- MTL_DEBUG1(MT_FLFMT("%s: in fatal error"), __func__);\r
- rc = HH_OK;\r
- }\r
- e->in_use = 0;\r
- epool_free(&cqm->flist, cqc_index);\r
- }\r
- }\r
- }\r
- MTL_TRACE1("}THH_cqm_destroy_cq\n");\r
- logIfErr("THH_cqm_destroy_cq");\r
- return rc;\r
-} /* THH_cqm_destroy_cq */\r
-\r
-\r
-/************************************************************************/\r
-/* Note: we actually not validating that given 'cq' is indeed in use. */\r
-HH_ret_t THH_cqm_query_cq(\r
- THH_cqm_t cqm, /* IN */\r
- HH_cq_hndl_t cq, /* IN */\r
- VAPI_cqe_num_t* num_o_cqes_p /* IN */\r
-)\r
-{\r
- u_int32_t cqc_index= cq & MASK32(cqm->log2_max_cq);\r
- HH_ret_t rc = (in_use_cq(cqm, cq) ? HH_OK : HH_EINVAL_CQ_HNDL);\r
- MTL_TRACE1("{THH_cqm_query_cq: cqm=%p, cq=0x%x\n", cqm, cq);\r
- if (rc == HH_OK) rc= (TCQM_CQN(cqm,cqc_index) == cq) ? HH_OK : HH_EINVAL_CQ_HNDL;\r
- if (rc == HH_OK)\r
- {\r
- *num_o_cqes_p = cqm->entries[cqc_index].u.used.n_cq;\r
- }\r
- MTL_TRACE1("}THH_cqm_query_cq\n");\r
- logIfErr("THH_cqm_query_cq");\r
- return rc;\r
-} /* THH_cqm_query_cq */\r
-\r
-\r
-\r
-/************************************************************************/\r
-/* Assumed to be the first called in this module, single thread. */\r
-void THH_cqm_init(void)\r
-{\r
- MTL_TRACE1("THH_cqm_init\n");\r
-} /* THH_cqm_init */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_cqm_get_num_cqs(\r
- THH_cqm_t cqm, /* IN */\r
- u_int32_t *num_cqs_p /* OUT*/\r
-)\r
-{\r
- CQCM_entry_ut* e;\r
- CQCM_entry_ut* e_end;\r
- int num_alloc_cqs = 0;\r
-\r
- if (cqm == NULL) {\r
- return HH_EINVAL;\r
- }\r
-\r
- e = cqm->entries;\r
- e_end = e + cqm->max_cq;\r
- for (; (e != e_end) ; ++e){\r
- if (e->in_use){ num_alloc_cqs++; }\r
- }\r
- return HH_OK;\r
-} /* THH_cqm_destroy */\r
-\r
-#if defined(MT_SUSPEND_QP)\r
-HH_ret_t THH_cqm_suspend_cq(\r
- THH_cqm_t cqm, /* IN */\r
- HH_cq_hndl_t cq, /* IN */ \r
- MT_bool do_suspend /* IN */)\r
-{\r
- u_int32_t cqc_index= cq & MASK32(cqm->log2_max_cq);\r
- HH_ret_t rc = HH_EINVAL_CQ_HNDL;\r
- MTL_TRACE1("{THH_cqm_suspend_cq, cqm=%p, cq=0x%x, do_suspend=%s\n",\r
- cqm, cq,(do_suspend==FALSE)?"FALSE":"TRUE");\r
- if (in_use_cq(cqm, cq))\r
- {\r
- CQCM_entry_ut* e = &cqm->entries[cqc_index];\r
- MT_bool is_suspended = e->u.used.is_suspended;\r
- if (do_suspend == is_suspended) {\r
- /* cq suspension already in desired state */\r
- MTL_DEBUG2(MT_FLFMT("%s: CQ 0x%x already %s"),\r
- __func__,cq, (is_suspended == TRUE)?"suspended" : "unsuspended");\r
- return HH_OK;\r
- }\r
- rc = THH_mrwm_suspend_internal(cqm->mrwm_internal,e->u.used.lkey, do_suspend);\r
- if (rc != HH_OK)\r
- {\r
- MTL_ERROR1(MT_FLFMT("%s: Failed THH_mrwm_suspend_mr of CQEs buffer region(%d: %s) !!"),\r
- __func__,rc, HH_strerror_sym(rc));\r
- }\r
- else\r
- {\r
- MTL_DEBUG2(MT_FLFMT("%s: CQ 0x%x is %s"),\r
- __func__,cq, (do_suspend == TRUE)?"suspended" : "unsuspended");\r
- e->u.used.is_suspended = do_suspend;\r
- }\r
- }\r
- MTL_TRACE1("}THH_cqm_suspend_cq\n");\r
- logIfErr("THH_cqm_suspend_cq");\r
- return rc;\r
-} /* THH_cqm_suspend_cq */\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#if !defined(H_TCQM_H)\r
-#define H_TCQM_H\r
-\r
-#include <mtl_common.h>\r
-#include <vapi_types.h>\r
-#include <mosal.h>\r
-#include <hh.h>\r
-#include <thh.h>\r
-#include <thh_hob.h>\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_cqm_create\r
- * \r
- * Arguments:\r
- * hob - The THH_hob object in which this object will be included\r
- * log2_max_cq - (log2) Max. number of CQs (CQC table size)\r
- * cqm_p - The allocated CQM object\r
- * \r
- * Returns: \r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- * HH_EAGAIN - Not enough resources available\r
- * \r
- * Description: \r
- * This function creates the THH_cqm object.\r
- */\r
-extern HH_ret_t THH_cqm_create(\r
- THH_hob_t hob, /* IN */ \r
- u_int8_t log2_max_cq, /* IN */\r
- u_int8_t log2_rsvd_cqs, /* IN */\r
- THH_cqm_t* cqm_p /* OUT */\r
-);\r
-\r
-/************************************************************************\r
- * Function: THH_cqm_destroy\r
- * \r
- * Arguments:\r
- * cqm - The object to destroy\r
- * hca_failure - If TRUE object destruction is required \r
- * due to HCA (hardware) failure (e.g. surprise removal)\r
- * \r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid handle \r
- * \r
- * Description: \r
- * Free all CQM related resources.\r
- */\r
-extern HH_ret_t THH_cqm_destroy(\r
- THH_cqm_t cqm, /* IN */ \r
- MT_bool hca_failure /* IN */\r
-);\r
-\r
-/************************************************************************\r
- * Function: THH_cqm_create_cq\r
- * \r
- * Arguments:\r
- * cqm - CQM object context \r
- * user_protection_context - User context of given CQE buffer\r
- * comp_eqn - Completion Event Queue\r
- * error_eqn - Error Error Queue\r
- * cq_ul_resources_p buffers, requested and/or actually created.\r
- * cq_p - The allocated CQ handle (probably CQ index).\r
- * \r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- * HH_EAGAIN - Not enough resources available to complete operation\r
- * \r
- * Description:\r
- * Set up a CQ resource.\r
- */\r
-extern HH_ret_t THH_cqm_create_cq(\r
- THH_cqm_t cqm, /* IN */\r
- MOSAL_protection_ctx_t user_protection_context, /* IN */\r
- THH_eqn_t comp_eqn, /* IN */\r
- THH_eqn_t error_eqn, /* IN */\r
- THH_cq_ul_resources_t* cq_ul_resources_p, /* IO */\r
- HH_cq_hndl_t* cq_p /* OUT */\r
-);\r
-\r
-/************************************************************************\r
- * Function: THH_cqm_modify_cq\r
- * \r
- * Arguments:\r
- * cqm (IN) - CQM object context\r
- * cq (IN) - CQ to resize\r
- * cq_ul_resources_p (IO)- CQ resources allocated/defined in user space \r
- * and returned producer index\r
- * \r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- * HH_EAGAIN - Not enough resources available to complete operation\r
- * \r
- * Description:\r
- * Modify CQ by replacing the CQEs buffer. \r
- * Replace CQEs buffer with new buffer given is cq_ul_resources_p (new cqe_buf + buf_sz) \r
- * Return in cq_ul_resources_p the next prodcuer index (to start with in new buffer) \r
- */\r
-HH_ret_t THH_cqm_resize_cq(\r
- THH_cqm_t cqm, /* IN */\r
- HH_cq_hndl_t cq, /* IN */\r
- THH_cq_ul_resources_t* cq_ul_resources_p /* IO */\r
-);\r
-\r
-/************************************************************************\r
- * Function: THH_cqm_destroy_cq\r
- * Arguments:\r
- * cqm - The THH_cqm object handle\r
- * cq - The CQ to destroy\r
- * \r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid handles \r
- * \r
- * Description:\r
- * Free CQ resources.\r
- */\r
-extern HH_ret_t THH_cqm_destroy_cq(\r
- THH_cqm_t cqm /* IN */,\r
- HH_cq_hndl_t cq /* IN */\r
-);\r
-\r
-/************************************************************************\r
- * Function: THH_cqm_query_cq\r
- * \r
- * Arguments:\r
- * cqm - The THH_cqm object handle\r
- * cq - The CQ to query\r
- * num_o_cqes_p - Maximum outstanding CQEs for this CQ \r
- * \r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid handles\r
- * \r
- * Description:\r
- * Query CQ for number of outstanding CQEs limit.\r
- */\r
-extern HH_ret_t THH_cqm_query_cq(\r
- THH_cqm_t cqm, /* IN */\r
- HH_cq_hndl_t cq, /* IN */\r
- VAPI_cqe_num_t* num_o_cqes_p /* IN */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_cqm_get_num_cqs\r
- * \r
- * Arguments:\r
- * cqm - The THH_cqm object handle\r
- * num_cqs_p - number of CQs currently allocated \r
- * \r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid handles\r
- * \r
- * Description:\r
- */\r
-HH_ret_t THH_cqm_get_num_cqs(\r
- THH_cqm_t cqm, /* IN */\r
- u_int32_t *num_cqs_p /* OUT*/\r
-);\r
-\r
-#if defined(MT_SUSPEND_QP)\r
-/************************************************************************\r
- * Function: THH_cqm_suspend_cq\r
- * \r
- * Arguments:\r
- * cqm - The THH_cqm object handle\r
- * cq - CQ handle \r
- * do_suspend -- if TRUE, suspend (i.e., unpin the CQ's resources).\r
- * if FALSE, unsuspend (i.e., re-pin the CQs resources).\r
- * \r
- * \r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid handles\r
- * \r
- * Description:\r
- */\r
-HH_ret_t THH_cqm_suspend_cq(\r
- THH_cqm_t cqm, /* IN */\r
- HH_cq_hndl_t cq, /* IN */ \r
- MT_bool do_suspend /* IN */\r
-);\r
-#endif\r
-#endif /* H_TCQM_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_THH_DEFAULT_PROFILE_H\r
-#define H_THH_DEFAULT_PROFILE_H\r
-\r
-#include <thh_requested_profile.h>\r
-\r
-/* WQE IN DDR DEFINES */\r
-/* CHANGE THE DEFINE BELOW TO BE DEFINED TO ZERO TO DISABLE WQEs IN DDR */\r
-#define THH_LOG2_WQE_DDR_SPACE_PER_QP 0 /* was 4096 */\r
-\r
-#define THH_DDR_LOG2_MTT_ENTRIES_PER_SEG (3)\r
-#define THH_DDR_LOG2_MTT_SEGS_PER_REGION (1)\r
-\r
-#define THH_DDR_LOG2_INFLIGHT_RDMA_PER_QP (3)\r
-#define THH_DDR_LOG2_MIN_QP_PER_MCG (3) /* minimum QPs per MCG. May be increased by calculations */\r
-#define THH_DDR_LOG2_MAX_MCG (13) /* log2 max MCG entries */\r
-#define THH_DDR_LOG2_MCG_HASH_PROPORTION (-1) /* log2 of proportion of MCG entries in mcg hash table*/\r
-#define THH_DDR_LOG2_MAX_EQ (6)\r
-#define THH_DDR_MAX_PRIV_UDAVS (1<<16)\r
-#define THH_USE_PRIV_UDAV (FALSE)\r
-#define THH_MAX_ASYNC_EQ_SIZE (1<<14) /* max number of outstanding async events */\r
-\r
-typedef struct THH_profile_input_st {\r
- u_int32_t max_qps; /* max number of QPs to configure */\r
- u_int32_t max_cqs;\r
- u_int32_t max_pds;\r
- u_int32_t max_regions;\r
- u_int32_t max_windows;\r
-\r
- u_int32_t min_qps; /* min number of QPs to configure */\r
- u_int32_t min_cqs;\r
- u_int32_t min_pds;\r
- u_int32_t min_regions;\r
- u_int32_t min_windows;\r
-\r
- u_int32_t reduction_pct_qps; /* percent by which to reduce QPs if need reduction */\r
- u_int32_t reduction_pct_cqs; /* percent by which to reduce CQs if need reduction */\r
- u_int32_t reduction_pct_pds; /* percent by which to reduce PDs if need reduction */\r
- u_int32_t reduction_pct_regions;\r
- u_int32_t reduction_pct_windows;\r
-\r
- u_int32_t log2_max_eq;\r
- u_int32_t log2_mtt_entries_per_seg;\r
- u_int32_t log2_mtt_segs_per_region;\r
- u_int32_t log2_inflight_rdma_per_qp;\r
- u_int32_t log2_max_mcg;\r
- u_int32_t log2_min_qp_per_mcg;\r
- int log2_mcg_hash_proportion;\r
- u_int32_t max_priv_udavs;\r
- MT_bool use_priv_udav;\r
- u_int32_t log2_wqe_ddr_space_per_qp;\r
-} THH_profile_input_t;\r
-\r
-/* NOTE: In the case of NON-privileged UDAV, we need one internal region per allocated PD. The number of PDs */\r
-/* by default is #QPs/4. This means that the number of internal regions in the MPT is not properly calculated. */\r
-/* However, there is a problem in that the MTT segment size MUST be a power of 2 (so that MTT entry addresses */\r
-/* are composed of a segment address and an entry offset in the segment). Using a segment size of 16 requires */\r
-/* reducing the number of supported QPs. For now, we are ignoring this issue, since users will mostly run */\r
-/* in UDAV protected mode */\r
-\r
-/* INIT_IB: No provision for overriding GUID0 on the chip is provided for now. some customers may wish to override the \r
- * default GUIDs burned into the chip. A define will not do the job, since each chip in a network \r
- * must have a different GUID0. When we provide default-override capability, we need to think about allowing\r
- * the administrator of a network to specify GUIDs per card on a host */\r
-\r
-\r
-\r
-/* DEFINES WHICH SHOULD REALLY COME FROM THE FIRMWARE. */\r
-\r
-#define THH_DDR_LOG2_SEG_SIZE_PER_REGION (3)\r
-#define THH_DDR_MCG_ENTRY_SIZE (64)\r
-#define THH_DDR_MCG_BYTES_PER_QP (4)\r
-#define THH_DDR_MCG_ENTRY_HEADER_SIZE (32)\r
-#define THH_DDR_LOG2_RDB_ENTRY_SIZE (5)\r
-#define THH_DDR_LOG2_EQC_ENTRY_SIZE (ceil_log2(hob->dev_lims.eqc_entry_sz))\r
-#define THH_DDR_LOG2_EEC_ENTRY_SIZE (ceil_log2(hob->dev_lims.eec_entry_sz))\r
-#define THH_DDR_LOG2_EEEC_ENTRY_SIZE (ceil_log2(hob->dev_lims.eeec_entry_sz))\r
-#define THH_DDR_LOG2_QPC_ENTRY_SIZE (ceil_log2(hob->dev_lims.qpc_entry_sz))\r
-#define THH_DDR_LOG2_EQPC_ENTRY_SIZE (ceil_log2(hob->dev_lims.eqpc_entry_sz))\r
-#define THH_DDR_LOG2_SRQC_ENTRY_SIZE (ceil_log2(hob->dev_lims.srq_entry_sz))\r
-#define THH_DDR_LOG2_MTT_ENTRY_SIZE (3)\r
-#define THH_DDR_LOG2_MIN_MTT_SEG_SIZE (6)\r
-#define THH_DDR_LOG2_MPT_ENTRY_SIZE (6)\r
-#define THH_DDR_LOG2_CQC_ENTRY_SIZE (ceil_log2(hob->dev_lims.cqc_entry_sz))\r
-#define THH_DDR_LOG2_UAR_SCR_ENTRY_SIZE (ceil_log2(hob->dev_lims.uar_scratch_entry_sz))\r
-#define THH_DDR_ADDR_VEC_SIZE (32)\r
-\r
-/* END firmware defines */\r
-\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
- \r
-#include <mtl_common.h>\r
-#include <cr_types.h>\r
-#include <MT23108_PRM.h>\r
-#include <vapi.h>\r
-#include <vapi_common.h>\r
-#include <hh.h>\r
-#include <thh_hob_priv.h>\r
-#include <sm_mad.h>\r
-#include <tlog2.h>\r
-#include <thh_default_profile.h>\r
-#include <thhul_pdm.h>\r
-#include <thh_srqm.h>\r
-\r
-#define TEST_RETURN_FATAL(hob) if ((hob->thh_state & THH_STATE_HAVE_ANY_FATAL) != 0) { \\r
- MTL_ERROR1(MT_FLFMT("%s: Device in FATAL state"), __func__); \\r
- return HH_EFATAL; \\r
- }\r
-#define TEST_CMD_FATAL(ret) if (ret == THH_CMD_STAT_EFATAL) { \\r
- MTL_ERROR1(MT_FLFMT("%s: cmdif returned FATAL"), __func__); \\r
- return HH_EFATAL; \\r
- }\r
-#define FREE_RSRC_RET(hob) rc = ((have_fatal == TRUE) ? HH_OK : rc) ; return rc\r
-#define DECLARE_FATAL_VARS MT_bool have_fatal=FALSE\r
-#define WAIT_IF_FATAL(hob) THH_hob_wait_if_fatal(hob,&have_fatal);\r
-#define IB_MAX_MESSAGE_SIZE (1 << 31)\r
-#define CMD_EQ_SIZE 250 /* to be smaller then 8K - so it's EQ can get into physical memory */\r
-\r
-#if 4 <= MAX_DEBUG\r
-#define THH_PRINT_PROFILE(a) THH_print_profile(a)\r
-#define THH_PRINT_USR_PROFILE(a) THH_print_usr_profile(a)\r
-#else\r
-#define THH_PRINT_PROFILE(a) \r
-#define THH_PRINT_USR_PROFILE(a)\r
-#endif\r
-\r
-/* global reference here for cmdif when putting Outbox in DDR memory*/\r
-#ifdef DEBUG_MEM_OV\r
-#define CMDIF_SIZE_IN_DDR 0x100000 /* allocate 1M in DDR memory*/ \r
-MT_phys_addr_t cmdif_dbg_ddr; /* address in ddr used for out params in debug mode */\r
-#endif\r
-\r
-\r
-#define THH_WATERMARK 1024 /* 1K*/\r
-\r
-#define GET_DDR_ADDR(phys_addr,hide_ddr,ddr_base) ((u_int64_t) ((((hide_ddr) == TRUE)&&(sizeof(MT_phys_addr_t)<=4)) ? \\r
- (((u_int64_t)(phys_addr)) | ((ddr_base) & MAKE_ULONGLONG(0xFFFFFFFF00000000))) : phys_addr))\r
- \r
-static HH_ret_t THH_hob_query_struct_init(THH_hob_t hob, MT_bool have_usr_profile, VAPI_hca_cap_t *hca_cap_p);\r
-static HH_ret_t THH_hob_halt_hca(/*IN*/ THH_hob_t hob);\r
-\r
-\r
-static void THH_dummy_async_event(HH_hca_hndl_t hca_hndl, HH_event_record_t *event_rec_p, void* ptr)\r
-{\r
- /* TBD : This should be an error */\r
- MTL_TRACE1("THH_dummy_async_event: called for devices %s with event type 0x%x",\r
- hca_hndl->dev_desc, event_rec_p->etype);\r
- return;\r
-}\r
-\r
-static void THH_dummy_comp_event(HH_hca_hndl_t hca_hndl, HH_cq_hndl_t cq_num, void* ptr)\r
-{\r
- /* TBD : This should be an error */\r
- MTL_TRACE1("THH_dummy_comp_event: called for device %s and cq num 0x%x",\r
- hca_hndl->dev_desc, cq_num);\r
- return;\r
-}\r
-\r
-int THH_hob_fatal_err_thread(void *arg);\r
-\r
-/******************************************************************************\r
-******************************************************************************\r
-************************ INTERNAL FUNCTIONS *********************************\r
-******************************************************************************\r
-******************************************************************************/\r
-#if 4 <= MAX_DEBUG\r
-static void THH_print_profile(THH_profile_t *profile) \r
-{\r
- MTL_DEBUG1("Profile printout\n");\r
-\r
- MTL_DEBUG1(" ddr_alloc_vec_size = "SIZE_T_DFMT"\n",profile->ddr_alloc_vec_size);\r
- MTL_DEBUG1(" ddr_size = "SIZE_T_XFMT" ("SIZE_T_DFMT")\n", \r
- profile->ddr_size,profile->ddr_size );\r
-\r
- MTL_DEBUG1(" ddr_size_code = %d\n", profile->ddr_size_code);\r
- \r
- MTL_DEBUG1(" num_external_mem_regions = "SIZE_T_XFMT" ("SIZE_T_DFMT")\n", \r
- profile->num_external_mem_regions,profile->num_external_mem_regions );\r
- MTL_DEBUG1(" num_mem_windows = "SIZE_T_XFMT" ("SIZE_T_DFMT")\n", \r
- profile->num_mem_windows,profile->num_mem_windows);\r
-\r
- MTL_DEBUG1(" log2_max_qps = "SIZE_T_DFMT"\n", profile->log2_max_qps);\r
- MTL_DEBUG1(" max_num_qps = "SIZE_T_XFMT" ("SIZE_T_DFMT")\n", \r
- profile->max_num_qps,profile->max_num_qps);\r
- MTL_DEBUG1(" log2_max_cqs = "SIZE_T_DFMT"\n", profile->log2_max_cqs);\r
- MTL_DEBUG1(" max_num_cqs = "SIZE_T_XFMT" ("SIZE_T_DFMT")\n", \r
- profile->max_num_cqs,profile->max_num_cqs);\r
- MTL_DEBUG1(" max_num_pds = "SIZE_T_XFMT" ("SIZE_T_DFMT")\n", \r
- profile->max_num_pds,profile->max_num_pds);\r
-\r
- MTL_DEBUG1(" log2_max_mpt_entries = "SIZE_T_DFMT"\n", profile->log2_max_mpt_entries);\r
- MTL_DEBUG1(" log2_max_mtt_entries = "SIZE_T_DFMT"\n", profile->log2_max_mtt_entries);\r
- MTL_DEBUG1(" log2_mtt_segs_per_region = "SIZE_T_DFMT"\n", profile->log2_mtt_segs_per_region);\r
- MTL_DEBUG1(" log2_mtt_entries_per_seg = "SIZE_T_DFMT"\n", profile->log2_mtt_entries_per_seg);\r
-\r
- \r
- MTL_DEBUG1(" log2_max_uar = "SIZE_T_DFMT"\n", profile->log2_max_uar);\r
- MTL_DEBUG1(" log2_uar_pg_size = %d\n", profile->log2_uar_pg_size);\r
- \r
- MTL_DEBUG1(" log2_wqe_ddr_space_per_qp = "SIZE_T_DFMT"\n",profile->log2_wqe_ddr_space_per_qp);\r
-\r
- MTL_DEBUG1(" use_priv_udav = %s\n", (profile->use_priv_udav ? "TRUE" : "FALSE"));\r
- MTL_DEBUG1(" max_priv_udavs = "SIZE_T_XFMT" ("SIZE_T_DFMT")\n", \r
- profile->max_priv_udavs,profile->max_priv_udavs);\r
- \r
- MTL_DEBUG1(" log2_max_mcgs = "SIZE_T_DFMT"\n", profile->log2_max_mcgs);\r
- MTL_DEBUG1(" qps_per_mcg = "SIZE_T_DFMT"\n", profile->qps_per_mcg);\r
- MTL_DEBUG1(" log2_mcg_entry_size = "SIZE_T_DFMT"\n", profile->log2_mcg_entry_size);\r
- MTL_DEBUG1(" log2_mcg_hash_size = "SIZE_T_DFMT"\n",profile->log2_mcg_hash_size);\r
-\r
-\r
- MTL_DEBUG1(" log2_max_eecs = "SIZE_T_DFMT"\n",profile->log2_max_eecs);\r
-\r
- MTL_DEBUG1(" log2_max_eqs = %d\n", profile->log2_max_eqs);\r
- return;\r
-}\r
-\r
-static void THH_print_usr_profile(EVAPI_hca_profile_t *profile) \r
-{\r
- MTL_DEBUG1("User Profile printout\n");\r
-\r
- MTL_DEBUG1(" num_qp = %d\n",profile->num_qp);\r
- MTL_DEBUG1(" num_cq = %d\n",profile->num_cq);\r
- MTL_DEBUG1(" num_pd = %d\n",profile->num_pd);\r
- MTL_DEBUG1(" num_mr = %d\n",profile->num_mr);\r
- MTL_DEBUG1(" num_mw = %d\n",profile->num_mw);\r
- MTL_DEBUG1(" max_qp_ous_rd_atom = %d\n",profile->max_qp_ous_rd_atom);\r
- MTL_DEBUG1(" max_mcg = %d\n",profile->max_mcg);\r
- MTL_DEBUG1(" qp_per_mcg = %d\n",profile->qp_per_mcg);\r
- MTL_DEBUG1(" require = %s\n",(profile->require == 0) ? "FALSE" : "TRUE");\r
- return;\r
-}\r
-#endif\r
-\r
-static const char* THH_get_ddr_allocation_string (u_int32_t index)\r
-{\r
- switch(index) {\r
- case 0: return "mtt sz";\r
- case 1: return "mpt sz";\r
- case 2: return "qpc sz";\r
- case 3: return "eqpc sz";\r
- case 4: return "srqc sz";\r
- case 5: return "cqc sz";\r
- case 6: return "rdb sz";\r
- case 7: return "uar scratch sz";\r
- case 8: return "eqc sz";\r
- case 9: return "mcg sz";\r
- case 10: return "eec sz";\r
- case 11: return "eeec sz";\r
- #if 0\r
- case 12: return "wqe pool sz";\r
- case 13: return "uplink qp sz";\r
- case 14: return "uplink mem sz";\r
- #endif\r
- default: return "UNKNOWN";\r
-\r
- }\r
-}\r
-\r
-\r
-/*\r
- * THH_get_ddr_size_code\r
- *\r
- */\r
-static void THH_print_hw_props(THH_hw_props_t *hw_props_p) \r
-{\r
- MTL_DEBUG4("%s: cr_base = " PHYS_ADDR_FMT "\n", __func__, hw_props_p->cr_base);\r
-// MTL_DEBUG4("%s: ddr_base = " PHYS_ADDR_FMT "\n", __func__hw_props_p->ddr_base);\r
- MTL_DEBUG4("%s: uar_base = " PHYS_ADDR_FMT "\n", __func__, hw_props_p->uar_base);\r
- MTL_DEBUG4("%s: device_id = 0x%x\n", __func__, hw_props_p->device_id);\r
- MTL_DEBUG4("%s: pci_vendor_id = 0x%x\n", __func__, hw_props_p->pci_vendor_id);\r
- MTL_DEBUG4("%s: intr_pin = 0x%x\n", __func__, hw_props_p->interrupt_props.intr_pin);\r
-#ifndef __DARWIN__\r
- //MOSAL_IRQ_ID_t does not have to be integer\r
- MTL_DEBUG4("%s: irq = 0x%x\n", __func__, hw_props_p->interrupt_props.irq);\r
-#endif /* not defined __DARWIN__ */\r
- MTL_DEBUG4("%s: bus = %d\n", __func__, hw_props_p->bus);\r
- MTL_DEBUG4("%s: dev_func = 0x%x\n", __func__, hw_props_p->dev_func);\r
-}\r
-\r
-/*\r
- * THH_get_ddr_size_code\r
- *\r
- */\r
-static THH_ddr_size_enum_t THH_get_ddr_size_code(MT_size_t ddr_size) \r
-{\r
- MTL_DEBUG4("THH_get_ddr_size_code: ddr size = "SIZE_T_FMT"\n", ddr_size);\r
- if (ddr_size < (1UL<<25)) {\r
- return THH_DDR_SIZE_32M;\r
- } else if (ddr_size < (1UL<<26)) {\r
- return THH_DDR_SIZE_64M;\r
- } else if (ddr_size < (1UL<<27)) {\r
- return THH_DDR_SIZE_128M;\r
- } else if (ddr_size < (1UL<<28)) {\r
- return THH_DDR_SIZE_256M;\r
- } else if (ddr_size < (1UL<<29)) {\r
- return THH_DDR_SIZE_512M;\r
- } else if (ddr_size < (1UL<<30)) {\r
- return THH_DDR_SIZE_1024M;\r
- } else if (ddr_size < (1UL<<31)) {\r
- return THH_DDR_SIZE_2048M;\r
- } else if (ddr_size < 0xFFFFFFFF) {\r
- return THH_DDR_SIZE_4096M;\r
- } else {\r
- return THH_DDR_SIZE_BIG;\r
- }\r
-}\r
-#ifndef __DARWIN__\r
-//TODO: all this code is OS dependent!\r
-//Must work with the pointer to PCI device\r
-\r
-/* \r
- * read_pci_config -- reads all configuration registers for given device\r
- * except for skipping regs 22 and 23\r
- */\r
-static HH_ret_t read_pci_config(u_int8_t bus, u_int8_t devfun, u_int32_t *config) \r
-{\r
- u_int8_t offset = 0;\r
- HH_ret_t rc = HH_OK;\r
-\r
- for (offset = 0; offset < 64; offset += 4) {\r
- if (offset == 22 || offset == 23) {\r
- continue;\r
- }\r
- rc = MOSAL_PCI_read_config_dword(bus,devfun,offset,config);\r
- if (rc != MT_OK) {\r
- return HH_ERR;\r
- }\r
- config++;\r
- }\r
- return HH_OK;\r
-}\r
-static HH_ret_t write_pci_config(u_int8_t bus, u_int8_t devfun, u_int32_t *config) \r
-{\r
- u_int8_t offset = 0;\r
- HH_ret_t rc = HH_OK;\r
-\r
- for (offset = 0; offset < 64; offset += 4) {\r
- if (offset == 22 || offset == 23) {\r
- continue;\r
- }\r
- rc = MOSAL_PCI_write_config_dword(bus,devfun,offset,*config);\r
- if (rc != MT_OK) {\r
- return HH_ERR;\r
- }\r
- config++;\r
- }\r
- return HH_OK;\r
-}\r
-/******************************************************************************\r
- * Function: THH_hob_get_pci_br_config\r
- *\r
- * Description: Gets p2p bridge configuration for this hca's bridge \r
- *\r
- * input:\r
- * hob\r
- * output: \r
- * ack_timeout_p \r
- * returns:\r
- * HH_OK\r
- * HH_EINVAL\r
- * HH_EINVAL_HCA_HNDL\r
- * HH_ERR\r
- *\r
- * Comments: Does MAD query to get the data in real time. This function is used\r
- * in pre-calculation of VAPI_query_hca values (at open_hca time).\r
- *\r
- *****************************************************************************/\r
-static HH_ret_t THH_hob_get_pci_br_config(THH_hob_t hob)\r
-{\r
- call_result_t rc;\r
- u_int16_t index=0;\r
- u_int8_t bus;\r
- u_int8_t dev_func;\r
- MOSAL_PCI_cfg_hdr_t cfg_hdr;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- /* scan all bridges to find mellanox pci bridge which belongs to this hca */\r
- while (TRUE) {\r
- /*1. find device */\r
- rc = MOSAL_PCI_find_device(hob->hw_props.pci_vendor_id,\r
- (hob->hw_props.device_id)+2,\r
- index, &bus, &dev_func);\r
- index++;\r
- if (rc != MT_OK) {\r
- MTL_DEBUG4(MT_FLFMT("%s: No more InfiniBridges."), __func__); \r
- break;\r
- }\r
- MTL_DEBUG4(MT_FLFMT("%s: InfiniBridge %d: pci_find_device returned: bus=%d, dev_func=%d"), \r
- __func__, index, bus, dev_func);\r
- \r
- /*2. get pci header */\r
- rc = MOSAL_PCI_get_cfg_hdr(bus, dev_func, &cfg_hdr);\r
- if (rc != MT_OK) {\r
- MTL_ERROR4(MT_FLFMT("%s: Could not get header for device bus %d, dev_func 0x%x"),\r
- __func__, bus, dev_func); \r
- continue;\r
- }\r
-\r
- if ((cfg_hdr.type1.header_type & 0x7F) != MOSAL_PCI_HEADER_TYPE1) {\r
- MTL_DEBUG1(MT_FLFMT("%s: Wrong PCI header type (0x%02X). Should be type 1. Device ignored."),\r
- __func__, cfg_hdr.type0.header_type);\r
- continue; \r
- }\r
-\r
- /*3. check if this is our bridge */\r
- if (cfg_hdr.type1.sec_bus != hob->hw_props.bus) {\r
- MTL_DEBUG1(MT_FLFMT("%s: Not our bridge. bus = %d, dev_num=%d"),\r
- __func__, bus, dev_func );\r
- continue; \r
- }\r
-\r
- /* found our bridge. Read and save its configuration */\r
- MTL_DEBUG1(MT_FLFMT("%s: found bridge. bus = %d, dev_num=%d"),\r
- __func__, bus, dev_func );\r
- if (read_pci_config(bus,dev_func,hob->pci_bridge_info.config) != MT_OK) {\r
- return (HH_ERR);\r
- } else {\r
- hob->pci_bridge_info.bus = bus;\r
- hob->pci_bridge_info.dev_func = dev_func;\r
- hob->pci_bridge_info.is_valid = TRUE;\r
- return HH_OK;\r
- }\r
- }\r
-\r
- return HH_ERR; // did not find bridge\r
-}\r
-#endif /* not defined __DARWIN__ */\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_get_node_guid\r
- *\r
- * Description: Gets node GUID for this HCA. \r
- *\r
- * input:\r
- * hob\r
- * port_num - 1 or 2\r
- * output: \r
- * node_guid - pointer to a GUID structure\r
- * returns:\r
- * HH_OK\r
- * HH_EINVAL\r
- * HH_EINVAL_HCA_HNDL\r
- * HH_ERR\r
- *\r
- * Comments: Does MAD query to get the data in real time. This function is used\r
- * in pre-calculation of VAPI_query_hca values (at open_hca time).\r
- *\r
- *****************************************************************************/\r
-static HH_ret_t THH_hob_get_node_guid(THH_hob_t hob,\r
- IB_guid_t *node_guid)\r
-{\r
- SM_MAD_NodeInfo_t node_info;\r
- u_int8_t *mad_frame_in;\r
- u_int8_t *mad_frame_out;\r
- THH_cmd_status_t cmd_ret;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- MTL_DEBUG4("==> THH_hob_get_node_guid\n");\r
- TEST_RETURN_FATAL(hob);\r
-\r
- mad_frame_in = TNMALLOC(u_int8_t, IB_MAD_SIZE);\r
- if ( !mad_frame_in ) {\r
- return HH_EAGAIN;\r
- }\r
- mad_frame_out = TNMALLOC(u_int8_t, IB_MAD_SIZE);\r
- if ( !mad_frame_out ) {\r
- FREE(mad_frame_in);\r
- return HH_EAGAIN;\r
- }\r
- memset(mad_frame_in, 0, sizeof(mad_frame_in));\r
- memset(mad_frame_out, 0, sizeof(mad_frame_out));\r
-\r
- /* get PKey table using MAD commands in THH_cmd object */\r
- /* First, build the MAD header */\r
- MADHeaderBuild(IB_CLASS_SMP, \r
- 0,\r
- IB_METHOD_GET,\r
- IB_SMP_ATTRIB_NODEINFO,\r
- (u_int32_t) 0,\r
- &(mad_frame_in[0]));\r
-\r
- /* issue the query */\r
- cmd_ret = THH_cmd_MAD_IFC(hob->cmd, 0, 0, 1, &(mad_frame_in[0]), &(mad_frame_out[0]));\r
- if (cmd_ret != THH_CMD_STAT_OK) {\r
- TEST_CMD_FATAL(cmd_ret);\r
- MTL_ERROR2( "THH_hob_get_pkey_tbl: ERROR : Get Node Info command failed (%d) for port 1\n", cmd_ret);\r
- MTL_DEBUG4("<== THH_hob_get_node_guid. ERROR\n");\r
- FREE(mad_frame_out);\r
- FREE(mad_frame_in);\r
- return HH_EINVAL;\r
- }\r
- MadBufPrint(&(mad_frame_out[0]));\r
- NodeInfoMADToSt(&node_info, &(mad_frame_out[0]));\r
- NodeInfoPrint(&node_info);\r
- \r
-// guid = node_info.qwNodeGUID;\r
-// MTL_DEBUG4("THH_hob_get_node_guid: Node GUID = 0x%Lx\n", guid);\r
-// for (i = 7; i >= 0 ; --i) {\r
-// (*node_guid)[i] = (u_int8_t) (guid & 0x0FF);\r
-// guid >>= 8;\r
-// }\r
- memcpy((*node_guid), node_info.qwNodeGUID, sizeof(IB_guid_t));\r
- MTL_DEBUG4("<== THH_hob_get_node_guid\n");\r
- FREE(mad_frame_out);\r
- FREE(mad_frame_in);\r
- return HH_OK;\r
-}\r
-\r
-/* now obtained from DEV_LIMS */\r
-#if 0\r
-/******************************************************************************\r
- * Function: THH_hob_get_ack_timeout\r
- *\r
- * Description: Gets ack timeout for this HCA. \r
- *\r
- * input:\r
- * hob\r
- * output: \r
- * ack_timeout_p \r
- * returns:\r
- * HH_OK\r
- * HH_EINVAL\r
- * HH_EINVAL_HCA_HNDL\r
- * HH_ERR\r
- *\r
- * Comments: Does MAD query to get the data in real time. This function is used\r
- * in pre-calculation of VAPI_query_hca values (at open_hca time).\r
- *\r
- *****************************************************************************/\r
-static HH_ret_t THH_hob_get_ack_timeout(\r
- THH_hob_t hob,\r
- u_int8_t* ack_timeout_p)\r
-{\r
- SM_MAD_PortInfo_t port_info;\r
- u_int8_t *mad_frame_in;\r
- u_int8_t *mad_frame_out;\r
- THH_cmd_status_t cmd_ret;\r
-\r
- MTL_DEBUG4("ENTERING THH_hob_get_ack_timeout\n");\r
-\r
- mad_frame_in = TNMALLOC(u_int8_t, IB_MAD_SIZE);\r
- if ( !mad_frame_in ) {\r
- return HH_EAGAIN;\r
- }\r
- mad_frame_out = TNMALLOC(u_int8_t, IB_MAD_SIZE);\r
- if ( !mad_frame_out ) {\r
- FREE(mad_frame_in);\r
- return HH_EAGAIN;\r
- }\r
- memset(mad_frame_in, 0, sizeof(mad_frame_in));\r
- memset(mad_frame_out, 0, sizeof(mad_frame_out));\r
-\r
- /* get PortInfo for port 12 (first port) */\r
- /* First, build the MAD header */\r
-\r
- MADHeaderBuild(IB_CLASS_SMP, \r
- 0,\r
- IB_METHOD_GET,\r
- IB_SMP_ATTRIB_PORTINFO,\r
- (u_int32_t) 1,\r
- &(mad_frame_in[0]));\r
-\r
- /* issue the query */\r
- cmd_ret = THH_cmd_MAD_IFC(hob->cmd, 0, 0, 1, &(mad_frame_in[0]), &(mad_frame_out[0]));\r
- if (cmd_ret != THH_CMD_STAT_OK) {\r
- TEST_CMD_FATAL(cmd_ret);\r
- MTL_ERROR2( "THH_hob_get_ack_timeout: ERROR : Get Port Info command failed (%d) for port 1\n", cmd_ret);\r
- FREE(mad_frame_out);\r
- FREE(mad_frame_in);\r
- return HH_ERR;\r
- }\r
- PortInfoMADToSt(&port_info, &(mad_frame_out[0]));\r
- PortInfoPrint(&port_info);\r
-\r
- *ack_timeout_p = port_info.cRespTimeValue;\r
- FREE(mad_frame_out);\r
- FREE(mad_frame_in);\r
- return HH_OK;\r
-}\r
-#endif\r
-\r
-/******************************************************************************\r
- * Function: calculate_ddr_alloc_vec\r
- *\r
- * Description: Calculates sizes for DDR area allocation from profile\r
- *\r
- * input:\r
- * hob\r
- * profile -- pointer to data structure containing computation input\r
- * output: \r
- * alloc_size_vec -- pointer to vector of allocation sizes to compute\r
- * \r
- * returns:\r
- * HH_OK\r
- *\r
- *\r
- *****************************************************************************/\r
-static void calculate_ddr_alloc_vec(/*IN*/ THH_hob_t hob,\r
- /*IN*/ THH_profile_t *profile, \r
- /*OUT*/THH_ddr_allocation_vector_t *alloc_size_vec)\r
-{\r
-\r
- alloc_size_vec->log2_mtt_size = profile->log2_max_mtt_entries + THH_DDR_LOG2_MTT_ENTRY_SIZE; \r
- alloc_size_vec->log2_mpt_size = profile->log2_max_mpt_entries + THH_DDR_LOG2_MPT_ENTRY_SIZE; \r
- alloc_size_vec->log2_qpc_size = profile->log2_max_qps + THH_DDR_LOG2_QPC_ENTRY_SIZE;\r
- alloc_size_vec->log2_eqpc_size = profile->log2_max_qps + THH_DDR_LOG2_EQPC_ENTRY_SIZE; \r
- alloc_size_vec->log2_srqc_size = hob->dev_lims.srq ? \r
- profile->log2_max_srqs + THH_DDR_LOG2_SRQC_ENTRY_SIZE : THH_DDRMM_INVALID_SZ;\r
- alloc_size_vec->log2_cqc_size = profile->log2_max_cqs + THH_DDR_LOG2_CQC_ENTRY_SIZE;\r
- alloc_size_vec->log2_rdb_size = profile->log2_max_qps + profile->log2_inflight_rdma_per_qp + \r
- THH_DDR_LOG2_RDB_ENTRY_SIZE;\r
- alloc_size_vec->log2_uar_scratch_size = profile->log2_max_uar + THH_DDR_LOG2_UAR_SCR_ENTRY_SIZE; \r
- alloc_size_vec->log2_eqc_size = profile->log2_max_eqs + THH_DDR_LOG2_EQC_ENTRY_SIZE; \r
- if (THH_DEV_LIM_MCG_ENABLED(hob)) {\r
- alloc_size_vec->log2_mcg_size = profile->log2_max_mcgs + profile->log2_mcg_entry_size;\r
- } else {\r
- alloc_size_vec->log2_mcg_size = 0;\r
- }\r
- alloc_size_vec->log2_eec_size = profile->log2_max_eecs + THH_DDR_LOG2_EEC_ENTRY_SIZE; \r
- alloc_size_vec->log2_eeec_size = profile->log2_max_eecs + THH_DDR_LOG2_EEEC_ENTRY_SIZE; /* in-flight rdma */\r
-\r
- return;\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_check_profile\r
- *\r
- * Description: Validates profile values against tavor max values, as obtained\r
- * from GET_DEV_LIM query\r
- *\r
- * Details:\r
- *\r
- *****************************************************************************/\r
-static HH_ret_t THH_check_profile(THH_hob_t hob)\r
-{\r
- \r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (hob->profile.log2_uar_pg_size < hob->dev_lims.log_pg_sz) {\r
- MTL_ERROR1("THH_calculate_default_profile: log2 UAR page size(%u) is less than the Tavor minimum (%u)\n", \r
- hob->profile.log2_uar_pg_size, hob->dev_lims.log_pg_sz);\r
- return HH_EAGAIN;\r
- }\r
- hob->profile.log2_max_qps = (hob->profile.log2_max_qps > hob->dev_lims.log_max_qp) ? \r
- hob->dev_lims.log_max_qp : hob->profile.log2_max_qps; \r
- hob->profile.log2_max_mcgs = (hob->profile.log2_max_mcgs > hob->dev_lims.log_max_mcg) ? \r
- hob->dev_lims.log_max_mcg : hob->profile.log2_max_mcgs;\r
- hob->profile.log2_max_eecs = (hob->profile.log2_max_eecs > hob->dev_lims.log_max_ee) ? \r
- hob->dev_lims.log_max_ee : hob->profile.log2_max_eecs;\r
- hob->profile.log2_max_cqs = (hob->profile.log2_max_cqs > hob->dev_lims.log_max_cq) ? \r
- hob->dev_lims.log_max_cq : hob->profile.log2_max_cqs;\r
- hob->profile.log2_max_uar = (hob->profile.log2_max_uar > hob->dev_lims.uar_sz + 20UL - hob->profile.log2_uar_pg_size) ? \r
- hob->dev_lims.uar_sz + 20UL - hob->profile.log2_uar_pg_size : hob->profile.log2_max_uar;\r
-\r
- hob->profile.log2_max_eqs = (hob->profile.log2_max_eqs > hob->dev_lims.log_max_eq) ? \r
- hob->dev_lims.log_max_eq : hob->profile.log2_max_eqs; \r
- hob->profile.max_num_pds = (hob->profile.max_num_pds > (1UL<<hob->dev_lims.log_max_pd)) ? \r
- (1UL<<hob->dev_lims.log_max_pd) : hob->profile.max_num_pds; \r
-\r
- if (THH_DEV_LIM_MCG_ENABLED(hob)) {\r
- hob->profile.qps_per_mcg = (hob->profile.qps_per_mcg > (MT_size_t) (1U<<hob->dev_lims.log_max_qp_mcg)) ? \r
- (MT_size_t) (1U<<hob->dev_lims.log_max_qp_mcg) : hob->profile.qps_per_mcg;\r
- }\r
-\r
- return HH_OK;\r
-}\r
-\r
-\r
-#define THH_PROFILE_CALC_QP_AT_MINIMUM (1)\r
-#define THH_PROFILE_CALC_CQ_AT_MINIMUM (1 << 1)\r
-#define THH_PROFILE_CALC_PD_AT_MINIMUM (1 << 2)\r
-#define THH_PROFILE_CALC_REG_AT_MINIMUM (1 << 3)\r
-#define THH_PROFILE_CALC_WIN_AT_MINIMUM (1 << 4)\r
-#define THH_PROFILE_CALC_ALL_AT_MINIMUM (THH_PROFILE_CALC_QP_AT_MINIMUM | THH_PROFILE_CALC_CQ_AT_MINIMUM | \\r
- THH_PROFILE_CALC_PD_AT_MINIMUM | THH_PROFILE_CALC_REG_AT_MINIMUM | \\r
- THH_PROFILE_CALC_WIN_AT_MINIMUM )\r
- \r
-static int check_profile_sanity(THH_hob_t hob, EVAPI_hca_profile_t *user_profile, THH_profile_input_t *thh_profile)\r
-{\r
- u_int64_t tmp_calc;\r
- /* check for bad minimum values */\r
- if ((user_profile->num_qp == 0) || (user_profile->num_cq == 0) || (user_profile->num_pd == 0) ||\r
- (user_profile->num_mr == 0) || (user_profile->max_qp_ous_rd_atom == 0) ) {\r
- MTL_ERROR1(MT_FLFMT("profile: QPs or CQs or PDs or MRs or max_qp_ous_rd_atom equal to 0"));\r
- return 0;\r
- }\r
- if (user_profile->num_qp > (1U<<hob->dev_lims.log_max_qp)) {\r
- MTL_ERROR1(MT_FLFMT("profile: num QPs more than device limit(%d)"),\r
- (1U<<hob->dev_lims.log_max_qp));\r
- return 0;\r
- } else if (user_profile->num_qp < 1) {\r
- MTL_ERROR1(MT_FLFMT("profile: num QPs must be at least 1"));\r
- return 0;\r
- }\r
-\r
- if (user_profile->num_cq > (1U<<hob->dev_lims.log_max_cq)) {\r
- MTL_ERROR1(MT_FLFMT("profile: num CQs more than device limit(%d)"),\r
- (1U<<hob->dev_lims.log_max_cq));\r
- return 0;\r
- } else if (user_profile->num_cq < 1) {\r
- MTL_ERROR1(MT_FLFMT("profile: num CQs must be at least 1"));\r
- return 0;\r
- }\r
-\r
- if (user_profile->num_pd > (1U<<hob->dev_lims.log_max_pd)) {\r
- MTL_ERROR1(MT_FLFMT("profile: num PDs more than device limit(%d)"),\r
- (1U<<hob->dev_lims.log_max_pd));\r
- return 0;\r
- } else if (user_profile->num_pd < 1) {\r
- MTL_ERROR1(MT_FLFMT("profile: num PDs must be at least 1"));\r
- return 0;\r
- }\r
- if (user_profile->num_mr < 1) {\r
- MTL_ERROR1(MT_FLFMT("profile: num MRs must be at least 1"));\r
- return 0;\r
- }\r
- if (user_profile->max_qp_ous_rd_atom > (1U<<hob->dev_lims.log_max_ra_res_qp)) {\r
- MTL_ERROR1(MT_FLFMT("profile: max_qp_ous_rd_atom more than device limit (%d)"),\r
- (1U<<hob->dev_lims.log_max_ra_res_qp));\r
- return 0;\r
- }\r
-\r
- if (ceil_log2((u_int64_t)user_profile->max_mcg) > hob->dev_lims.log_max_mcg) {\r
- MTL_ERROR1(MT_FLFMT("profile: num MCGs more than device limit(%d)"),\r
- (1U<<hob->dev_lims.log_max_mcg));\r
- return 0;\r
- }\r
-\r
- if (ceil_log2((u_int64_t)user_profile->qp_per_mcg) > hob->dev_lims.log_max_qp_mcg) {\r
- MTL_ERROR1(MT_FLFMT("profile: QPs per multicast group greater than device limit (%d)"),\r
- (1U<<hob->dev_lims.log_max_qp_mcg));\r
- return 0;\r
- }\r
- if (user_profile->num_cq > (user_profile->num_qp * 2)) {\r
- MTL_ERROR1(MT_FLFMT("profile: CQs more than twice QPs in hca profile"));\r
- return 0;\r
- }\r
- if ((user_profile->max_mcg > 0) && (user_profile->qp_per_mcg < 8)) {\r
- MTL_ERROR1(MT_FLFMT("profile: if MCGs not zero, QP_PER_MCG must be >= 8"));\r
- return 0;\r
- }\r
- if (ceil_log2(user_profile->num_mr) > hob->dev_lims.log_max_mpts) {\r
- MTL_ERROR1("profile: Requested MRs use more MTTs than HCA provides\n");\r
- return 0;\r
- }\r
- \r
- tmp_calc = (u_int64_t)((u_int64_t) user_profile->num_qp +\r
- (u_int64_t) (unsigned long)THH_NUM_RSVD_QP +\r
- (u_int64_t) user_profile->num_cq + \r
- (u_int64_t) user_profile->num_mr);\r
- if ( hob->dev_lims.log_max_mtt_seg < ceil_log2( tmp_calc * (u_int64_t)(1U<<thh_profile->log2_mtt_segs_per_region) )) {\r
- MTL_ERROR1("profile: Requested parameters (CQs + QPs + MRs) use more MTTs than HCA provides\n");\r
- return 0;\r
- }\r
-\r
-\r
- if (ceil_log2(user_profile->num_mr) > hob->dev_lims.log_max_mpts) {\r
- MTL_ERROR1("profile: Requested MRs use more MPTs than HCA provides\n");\r
- return 0;\r
- }\r
-\r
- if (ceil_log2(user_profile->num_mw) > hob->dev_lims.log_max_mpts) {\r
- MTL_ERROR1("profile: Requested MWs use more MPTs than HCA provides\n");\r
- return 0;\r
- }\r
-\r
- tmp_calc = (u_int64_t)((u_int64_t) user_profile->num_qp +\r
- (u_int64_t) (unsigned long)THH_NUM_RSVD_QP +\r
- (u_int64_t) user_profile->num_cq + \r
- (u_int64_t) user_profile->num_mr + \r
- (u_int64_t) user_profile->num_mw);\r
-\r
- if ( hob->dev_lims.log_max_mpts < ceil_log2( tmp_calc)) {\r
- MTL_ERROR1("profile: Requested parameters (CQs + QPs + MRs + MWs) use more MPTs than HCA provides\n");\r
- return 0;\r
- }\r
- return 1;\r
-}\r
-/******************************************************************************\r
- * Function: THH_calculate_profile\r
- *\r
- * Description: Calculates and installs profile values\r
- *\r
- * input\r
- * hob\r
- * profile_user_data - pointer to a user override for the data used\r
- * in calculating the THH profile.\r
- *\r
- * Details:\r
- *\r
- * All calculations are derived from the following data:\r
- *\r
- * - max QPs = 64k per 128M DDR size (= 2^16)\r
- * - max MPT entries per HCA: 1M (= 2^20)\r
- * - avg Regions/windows per QP 8 (= 2^3)\r
- * - avg Segments per Region 8 (= 2^3)\r
- * - avg inflight RDMA per QP 4 (= 2^2)\r
- *\r
- * Calculations are as follows:\r
- * Max UARs = 1 per QP\r
- * Max CQs = 1 per QP\r
- * Max PDs = 1 per QP\r
- * Max Regions/Wins per QP = 8, divided as follows:\r
- * internal regions = 2 per QP (1 for QP, one for CQ)\r
- * external regions = 2 per QP\r
- * windows = 4 per QP\r
- *\r
- * MPT:\r
- * Tavor has a max of 1M regions/windows per HCA, and the MPT size must\r
- * be a power of 2. It is pointless to have fewer than 8 regions/windows per QP\r
- * (as divided up above). This means that the maximum number of QPs allowable,\r
- * regardless of DDR size, is 128K. Therefore, the presence of the "min" function\r
- * in calculating the max number of MPT entries. In effect, the 1M table size limitation\r
- * means that a DDR larger than 256M will only add to the user-available DDR memory, and\r
- * not to the driver's internal tables.\r
- *\r
- * MTT:\r
- * The default MTT size allocated has 2 segments per Region, with a segment size of 8 entries.\r
- *\r
- * MCG: for 128M: 4096 Groups per HCA, with 16 QPs per group (so that entry size is 64 bytes).\r
- * for 256M: 8192 Groups per HCA, with 16 QPs per group (so that entry size is 64 bytes).\r
- *\r
- * NOTES:\r
- * If the profile_user_data is NULL, default values are used. After the profile calculation,\r
- * a check is done to see that all values are within HCA_DEV_LIM values, and that the result\r
- * does not exceed the DDR memory size. If any violations are encountered, the number of QPs\r
- * is reduced by half, and the calculation is redone.\r
- * \r
- *****************************************************************************/\r
-static HH_ret_t THH_calculate_profile(THH_hob_t hob, \r
- EVAPI_hca_profile_t *profile_user_data,\r
- EVAPI_hca_profile_t *sugg_profile_p)\r
-{\r
- u_int8_t log2_host_pg_size;\r
- EVAPI_hca_profile_t local_user_profile;\r
- THH_profile_input_t profile_input_data;\r
- u_int64_t tot_ddr_allocs;\r
- THH_ddr_allocation_vector_t ddr_alloc_vec;\r
- MT_size_t *ddr_alloc_iterator, temp_size;\r
- u_int32_t i;\r
- MT_bool ddr_calc_loop = TRUE, need_to_loop = FALSE;\r
- u_int32_t calc_at_minimum = 0;\r
-// EVAPI_hca_profile_t hca_profile;\r
-\r
-\r
- if (profile_user_data != NULL) {\r
- \r
- memcpy(&local_user_profile, profile_user_data, sizeof(EVAPI_hca_profile_t));\r
-\r
- /* default value substitutions */\r
- local_user_profile.num_qp = (local_user_profile.num_qp == 0xFFFFFFFF) ? \r
- THH_PROF_MAX_QPS : local_user_profile.num_qp; \r
- local_user_profile.num_cq = (local_user_profile.num_cq == 0xFFFFFFFF) ? \r
- THH_PROF_MAX_CQS : local_user_profile.num_cq; \r
- local_user_profile.num_pd = (local_user_profile.num_pd == 0xFFFFFFFF) ? \r
- THH_PROF_MAX_PDS : local_user_profile.num_pd; \r
- local_user_profile.num_mr = (local_user_profile.num_mr == 0xFFFFFFFF) ? \r
- THH_PROF_MAX_REGIONS : local_user_profile.num_mr; \r
- local_user_profile.num_mw = (local_user_profile.num_mw == 0xFFFFFFFF) ? \r
- THH_PROF_MAX_WINDOWS : local_user_profile.num_mw;\r
- \r
- local_user_profile.max_qp_ous_rd_atom = (local_user_profile.max_qp_ous_rd_atom == 0xFFFFFFFF) ? \r
- (1 << THH_DDR_LOG2_INFLIGHT_RDMA_PER_QP):\r
- local_user_profile.max_qp_ous_rd_atom; \r
-\r
- local_user_profile.max_mcg = (local_user_profile.max_mcg == 0xFFFFFFFF) ? \r
- (1 << THH_DDR_LOG2_MAX_MCG):local_user_profile.max_mcg; \r
- \r
- local_user_profile.qp_per_mcg = (local_user_profile.qp_per_mcg == 0xFFFFFFFF) ? \r
- (1 << THH_DDR_LOG2_MIN_QP_PER_MCG):local_user_profile.qp_per_mcg; \r
- \r
- if (sugg_profile_p != NULL) {\r
- memcpy(sugg_profile_p, &local_user_profile, sizeof(EVAPI_hca_profile_t));\r
- }\r
-\r
- profile_input_data.max_qps = local_user_profile.num_qp ;\r
- profile_input_data.max_cqs = local_user_profile.num_cq ;\r
- profile_input_data.max_pds = local_user_profile.num_pd ;\r
- profile_input_data.max_regions = local_user_profile.num_mr ;\r
- profile_input_data.max_windows = local_user_profile.num_mw ;\r
-\r
- profile_input_data.min_qps = (1U<<hob->dev_lims.log2_rsvd_qps) + THH_NUM_RSVD_QP + 1;\r
- profile_input_data.min_cqs = (1U<<hob->dev_lims.log2_rsvd_cqs) + 1;\r
- profile_input_data.min_pds = hob->dev_lims.num_rsvd_pds + THH_NUM_RSVD_PD + 1;\r
- profile_input_data.min_regions = (1 << hob->dev_lims.log2_rsvd_mtts) + 1;\r
- profile_input_data.min_windows = (1 << hob->dev_lims.log2_rsvd_mrws);\r
- \r
- profile_input_data.reduction_pct_qps = 10;\r
- profile_input_data.reduction_pct_cqs = 10;\r
- profile_input_data.reduction_pct_pds = 10;\r
- profile_input_data.reduction_pct_regions = 10;\r
- profile_input_data.reduction_pct_windows = 10;\r
- \r
- profile_input_data.log2_inflight_rdma_per_qp = ceil_log2(local_user_profile.max_qp_ous_rd_atom);\r
- profile_input_data.log2_max_mcg = ceil_log2(local_user_profile.max_mcg);\r
- profile_input_data.log2_min_qp_per_mcg = ceil_log2(local_user_profile.qp_per_mcg);\r
- \r
- profile_input_data.log2_max_eq = THH_DDR_LOG2_MAX_EQ;\r
- profile_input_data.log2_mcg_hash_proportion = THH_DDR_LOG2_MCG_HASH_PROPORTION;\r
- profile_input_data.log2_mtt_entries_per_seg = THH_DDR_LOG2_MTT_ENTRIES_PER_SEG;\r
- profile_input_data.log2_mtt_segs_per_region = THH_DDR_LOG2_MTT_SEGS_PER_REGION;\r
- profile_input_data.use_priv_udav = THH_USE_PRIV_UDAV;\r
- profile_input_data.log2_wqe_ddr_space_per_qp = THH_LOG2_WQE_DDR_SPACE_PER_QP;\r
- /*sanity checks */\r
- if (check_profile_sanity(hob,&local_user_profile, &profile_input_data) == 0) {\r
- MTL_ERROR1(MT_FLFMT("THH_calculate_profile: user profile not valid"));\r
- return HH_EINVAL_PARAM;\r
- }\r
- } else {\r
- /* use internally defined default values */\r
- profile_input_data.max_qps = THH_PROF_MAX_QPS;\r
- profile_input_data.max_cqs = THH_PROF_MAX_CQS;\r
- profile_input_data.max_pds = THH_PROF_MAX_PDS;\r
- profile_input_data.max_regions = THH_PROF_MAX_REGIONS;\r
- profile_input_data.max_windows = THH_PROF_MAX_WINDOWS;\r
- profile_input_data.max_priv_udavs = THH_DDR_MAX_PRIV_UDAVS;\r
- \r
- profile_input_data.min_qps = THH_PROF_MIN_QPS;\r
- profile_input_data.min_cqs = THH_PROF_MIN_CQS;\r
- profile_input_data.min_pds = THH_PROF_MIN_PDS;\r
- profile_input_data.min_regions = THH_PROF_MIN_REGIONS;\r
- profile_input_data.min_windows = THH_PROF_MIN_WINDOWS;\r
-\r
- profile_input_data.reduction_pct_qps = THH_PROF_PCNT_REDUCTION_QPS;\r
- profile_input_data.reduction_pct_cqs = THH_PROF_PCNT_REDUCTION_CQS;\r
- profile_input_data.reduction_pct_pds = THH_PROF_PCNT_REDUCTION_PDS;\r
- profile_input_data.reduction_pct_regions = THH_PROF_PCNT_REDUCTION_REGIONS;\r
- profile_input_data.reduction_pct_windows = THH_PROF_PCNT_REDUCTION_WINDOWS;\r
- \r
- profile_input_data.log2_inflight_rdma_per_qp = THH_DDR_LOG2_INFLIGHT_RDMA_PER_QP;\r
- profile_input_data.log2_max_eq = THH_DDR_LOG2_MAX_EQ;\r
- profile_input_data.log2_max_mcg = THH_DDR_LOG2_MAX_MCG;\r
- profile_input_data.log2_min_qp_per_mcg = THH_DDR_LOG2_MIN_QP_PER_MCG;\r
- profile_input_data.log2_mcg_hash_proportion = THH_DDR_LOG2_MCG_HASH_PROPORTION;\r
- profile_input_data.log2_mtt_entries_per_seg = THH_DDR_LOG2_MTT_ENTRIES_PER_SEG;\r
- profile_input_data.log2_mtt_segs_per_region = THH_DDR_LOG2_MTT_SEGS_PER_REGION;\r
- profile_input_data.use_priv_udav = THH_USE_PRIV_UDAV;\r
- profile_input_data.log2_wqe_ddr_space_per_qp = THH_LOG2_WQE_DDR_SPACE_PER_QP;\r
- }\r
-\r
- hob->profile.use_priv_udav = profile_input_data.use_priv_udav;\r
- hob->profile.max_priv_udavs = profile_input_data.max_priv_udavs;\r
- \r
- /* need inflight rdma per QP for rdb size in DDR, and for THH_qpm_create */\r
- hob->profile.log2_inflight_rdma_per_qp = (u_int8_t) profile_input_data.log2_inflight_rdma_per_qp;\r
-\r
- /* manipulate MCG max if not inputting a profile, or if inputting profile which allows reduction */\r
- /* Reduce the number of MCGs for smaller DDR memories */\r
- hob->profile.log2_max_mcgs = profile_input_data.log2_max_mcg;\r
- if ((hob->profile.ddr_size_code < THH_DDR_SIZE_128M)\r
- && ((profile_user_data == NULL)|| (local_user_profile.require == FALSE))) {\r
- hob->profile.log2_max_mcgs--;\r
- }\r
-\r
- log2_host_pg_size = MOSAL_SYS_PAGE_SHIFT;\r
- if (log2_host_pg_size < hob->dev_lims.log_pg_sz) {\r
- MTL_ERROR1("THH_calculate_default_profile: Host min page size(%lu) is too small\n", \r
- (unsigned long ) MOSAL_SYS_PAGE_SIZE);\r
- return HH_EAGAIN;\r
- }\r
-\r
- /* do not allocate DDR memory for MCGs if MCG is not enabled in dev_limits */\r
- hob->profile.ddr_alloc_vec_size = (THH_DEV_LIM_MCG_ENABLED(hob) ? \r
- THH_DDR_ALLOCATION_VEC_SIZE : THH_DDR_ALLOCATION_VEC_SIZE - 1) ; /* no eec as yet */\r
- hob->profile.log2_wqe_ddr_space_per_qp = profile_input_data.log2_wqe_ddr_space_per_qp;\r
- \r
- /* MCG calculations - not in recalculation loop, since the amount of memory involved is very small*/\r
- /* each MCG entry must be a power-of-2 size. To guarantee a power-of-2, we take a "ceiling" log of the */\r
- /* MCG entry size(in bytes), and then compute the actual number of QPs per mcg backwards from the mcg_size variable. */\r
- /* We also require (as a sanity check) that the log2_mcg_hash_size be greater than zero */\r
- if ((THH_DEV_LIM_MCG_ENABLED(hob)) &&\r
- ((int)(hob->profile.log2_max_mcgs + profile_input_data.log2_mcg_hash_proportion) > 0)) {\r
- hob->profile.log2_mcg_entry_size = ceil_log2(((1U<<profile_input_data.log2_min_qp_per_mcg) * THH_DDR_MCG_BYTES_PER_QP) + \r
- THH_DDR_MCG_ENTRY_HEADER_SIZE);\r
- hob->profile.qps_per_mcg = ( (1U<<(hob->profile.log2_mcg_entry_size)) - THH_DDR_MCG_ENTRY_HEADER_SIZE) / \r
- THH_DDR_MCG_BYTES_PER_QP;\r
- \r
- /* the hash proportion is the log of the power-of-2 fraction of the total MCG entries used for the hash table. */\r
- /* Thus, for example, a proportion of (1/2) gets a log2_mcg_hash_proportion = -1 */\r
- hob->profile.log2_mcg_hash_size = hob->profile.log2_max_mcgs + profile_input_data.log2_mcg_hash_proportion;\r
- } else {\r
- /*UD MCGs not available on this HCA*/\r
- hob->profile.log2_mcg_entry_size = 0;\r
- hob->profile.qps_per_mcg = 0;\r
- hob->profile.log2_mcg_hash_size = 0;\r
- hob->profile.log2_max_mcgs = 0;\r
- }\r
- \r
- hob->profile.log2_mtt_entries_per_seg = profile_input_data.log2_mtt_entries_per_seg;\r
- hob->profile.log2_mtt_segs_per_region = profile_input_data.log2_mtt_segs_per_region;\r
- \r
- hob->profile.log2_uar_pg_size = log2_host_pg_size;\r
- hob->profile.log2_max_uar = hob->dev_lims.uar_sz + 20 - hob->profile.log2_uar_pg_size;\r
-/*** warning C4242: '=' : conversion from 'u_int32_t' to 'u_int8_t', possible loss of data ***/\r
- hob->profile.log2_max_eqs = (u_int8_t)profile_input_data.log2_max_eq; /* 64 EQs */\r
- hob->profile.max_num_pds = profile_input_data.max_pds;\r
-\r
- hob->profile.max_num_qps = profile_input_data.max_qps;\r
-\r
- hob->profile.log2_max_qps = ceil_log2(profile_input_data.max_qps+ \r
- (1U<<hob->dev_lims.log2_rsvd_qps) + THH_NUM_RSVD_QP); \r
- \r
- /* adjust max QPs downward (if using internal profile, or if user profile permits)\r
- * if the few reserved QPs cause max qps to go beyond a power-of-2.\r
- */\r
-\r
- if (hob->profile.log2_max_qps > ceil_log2(profile_input_data.max_qps)) {\r
- MTL_DEBUG1(MT_FLFMT("%s: reserved qps cause profile qps to jump a power-of-2"),__func__);\r
- if ((profile_user_data==NULL) || (local_user_profile.require == FALSE)) {\r
- hob->profile.log2_max_qps--;\r
- hob->profile.max_num_qps = (1U<<hob->profile.log2_max_qps) - (1U<<hob->dev_lims.log2_rsvd_qps)\r
- - THH_NUM_RSVD_QP;\r
- MTL_DEBUG1(MT_FLFMT("%s: Adjusting max qps to "SIZE_T_DFMT),__func__, hob->profile.max_num_qps);\r
- }\r
- }\r
-\r
- /* TBD: Expose max_srqs to profile given by user and use MOD_STAT_CFG */\r
- if (hob->dev_lims.srq) {\r
- hob->profile.log2_max_srqs = hob->dev_lims.log_max_srqs;\r
- hob->profile.max_num_srqs = \r
- (1U << hob->dev_lims.log_max_srqs) - (1 << hob->dev_lims.log2_rsvd_srqs);\r
- } else {\r
- hob->profile.log2_max_srqs = 0;\r
- hob->profile.max_num_srqs = 0;\r
- }\r
- \r
- hob->profile.max_num_cqs = profile_input_data.max_cqs;\r
- hob->profile.log2_max_cqs = ceil_log2(profile_input_data.max_cqs + \r
- (1U<<hob->dev_lims.log2_rsvd_cqs)); \r
- /* adjust max CQs downward (if using internal profile, or if user profile permits) \r
- * if the few reserved CQs cause max cqs to go beyond a power-of-2.\r
- */\r
-\r
- if (hob->profile.log2_max_cqs > ceil_log2(profile_input_data.max_cqs)) {\r
- MTL_DEBUG1(MT_FLFMT("%s: reserved cqs cause profile cqs to jump a power-of-2"),__func__);\r
- if ((profile_user_data == NULL) || (local_user_profile.require == FALSE)) {\r
- hob->profile.log2_max_cqs--;\r
- hob->profile.max_num_cqs = (1U<<hob->profile.log2_max_cqs) - (1U<<hob->dev_lims.log2_rsvd_cqs);\r
- MTL_DEBUG1(MT_FLFMT("%s: Adjusting max cqs to "SIZE_T_DFMT),__func__, hob->profile.max_num_cqs);\r
- }\r
- }\r
- hob->profile.num_external_mem_regions = profile_input_data.max_regions; /* 2 per QP */\r
- hob->profile.num_mem_windows = profile_input_data.max_windows;\r
- hob->profile.log2_max_eecs = 0;\r
-\r
- while (ddr_calc_loop) {\r
- MT_bool continue_calc_loop;\r
-\r
- continue_calc_loop = FALSE;\r
- \r
- MTL_DEBUG4("THH_calculate_profile: max_qps = "SIZE_T_FMT", max_cqs = "SIZE_T_FMT", max_priv_udav="SIZE_T_FMT\r
- ",\nmax_pds="SIZE_T_FMT",max_reg="SIZE_T_FMT", max_win="SIZE_T_FMT"\n",\r
- hob->profile.max_num_qps, hob->profile.max_num_cqs, hob->profile.max_priv_udavs,\r
- hob->profile.max_num_pds, hob->profile.num_external_mem_regions, \r
- hob->profile.num_mem_windows); \r
-\r
- /* add all raw resources without Tavor-reserved quantities */\r
- temp_size = hob->profile.max_num_qps + THH_NUM_RSVD_QP + \r
- hob->profile.max_num_cqs + hob->profile.num_external_mem_regions;\r
- \r
- hob->profile.log2_max_mtt_entries = ceil_log2(\r
- ( temp_size * (1U<<profile_input_data.log2_mtt_segs_per_region)\r
- * (1U<<profile_input_data.log2_mtt_entries_per_seg))\r
- + (1 << hob->dev_lims.log2_rsvd_mtts)\r
- );\r
- \r
- /* add all raw resources without Tavor-reserved quantities */\r
- temp_size = hob->profile.max_num_qps + THH_NUM_RSVD_QP + hob->profile.max_num_cqs \r
- + hob->profile.num_external_mem_regions + hob->profile.num_mem_windows;\r
- \r
- hob->profile.log2_max_mpt_entries = ceil_log2(temp_size + (1 << hob->dev_lims.log2_rsvd_mrws));\r
- \r
- \r
- if (hob->profile.log2_max_mtt_entries - profile_input_data.log2_mtt_entries_per_seg \r
- > hob->dev_lims.log_max_mtt_seg) {\r
- continue_calc_loop = TRUE;\r
- need_to_loop = TRUE;\r
- }\r
- \r
- if (!continue_calc_loop) {\r
- /* Now, compute the total DDR size, and verify that we have not over-allocated it. If yes, reduce QPs by half, and */\r
- /* recompute all above parameters starting with log2_max_regions */\r
- calculate_ddr_alloc_vec(hob, &(hob->profile),&ddr_alloc_vec);\r
- \r
- /* Add up all the sizes in the ddr allocation vector */\r
- tot_ddr_allocs = 0;\r
- ddr_alloc_iterator = (MT_size_t *)&(ddr_alloc_vec);\r
- for (i = 0; i < hob->profile.ddr_alloc_vec_size; i++, ddr_alloc_iterator++) {\r
- if ((*ddr_alloc_iterator) == THH_DDRMM_INVALID_SZ) {\r
- temp_size = 0; /* no allocation */\r
- } else if ((*ddr_alloc_iterator) >= ceil_log2(hob->profile.ddr_size)) {\r
- temp_size = hob->profile.ddr_size;\r
- } else {\r
- temp_size = (((MT_size_t) 1ul) << (*ddr_alloc_iterator));\r
- }\r
- MTL_DEBUG4("THH_calculate_profile:DDR: %s = "SIZE_T_XFMT"("SIZE_T_DFMT")\n", \r
- THH_get_ddr_allocation_string(i), temp_size, temp_size); \r
- tot_ddr_allocs += temp_size;\r
- }\r
- \r
- /* see if need to reserve space for WQEs in DDR */\r
- if (hob->profile.log2_wqe_ddr_space_per_qp != 0) {\r
- temp_size = (((MT_size_t) 1ul) << (hob->profile.log2_max_qps + hob->profile.log2_wqe_ddr_space_per_qp));\r
- MTL_DEBUG4("THH_calculate_profile: WQEs ddr area = "SIZE_T_XFMT" ("SIZE_T_DFMT")\n", \r
- temp_size, temp_size); \r
- tot_ddr_allocs += temp_size;\r
- }\r
- \r
- /* see if need to reserve space for privileged UDAVs in DDR */\r
- if (hob->profile.use_priv_udav) {\r
- temp_size = hob->profile.max_priv_udavs * (sizeof(struct tavorprm_ud_address_vector_st) / 8);\r
- MTL_DEBUG4("THH_calculate_profile: privileged UDAVs ddr area = "SIZE_T_XFMT" ("SIZE_T_DFMT")\n",\r
- temp_size, temp_size); \r
- tot_ddr_allocs += temp_size;\r
- }\r
- \r
- /* test against DDR size */\r
- MTL_DEBUG4("THH_calculate_profile: total DDR allocs = %d MB (incl reserved areas)\n",(int)(tot_ddr_allocs>>20)); \r
- if ((hob->profile.ddr_size < tot_ddr_allocs) || \r
- ((profile_user_data == NULL) && (hob->profile.max_num_qps>(1U<<16)))){ \r
- /*do not want more than 64K QPs if using internal defaults*/\r
- continue_calc_loop = TRUE;\r
- need_to_loop = TRUE;\r
- }\r
-\r
- }\r
- if (continue_calc_loop) {\r
- u_int64_t temp;\r
- u_int32_t u32_temp, change_flag;\r
- /* Reduce flagged profile input params by factor of 10 percent */\r
- change_flag = 0;\r
- if ((calc_at_minimum & THH_PROFILE_CALC_QP_AT_MINIMUM) == 0) {\r
- change_flag++;\r
- temp = (u_int64_t)(hob->profile.max_num_qps) * (100 - profile_input_data.reduction_pct_qps);\r
- /*check for overflow. If have overflow, use approximate percentages (divide by 1024) */\r
- if (temp & MAKE_ULONGLONG(0xFFFFFFFF00000000)) {\r
- temp = (u_int64_t)(hob->profile.max_num_qps) * (1024 - (profile_input_data.reduction_pct_qps*10));\r
- temp >>= 10;\r
- u32_temp = (u_int32_t)(temp & 0xFFFFFFFF);\r
- } else {\r
- /* use more exact percentages -- but still not floating point */\r
- u32_temp = (u_int32_t)temp;\r
- u32_temp /= 100;\r
- }\r
- if (u32_temp <= (u_int32_t)profile_input_data.min_qps) {\r
- calc_at_minimum |= THH_PROFILE_CALC_QP_AT_MINIMUM;\r
- u32_temp = profile_input_data.min_qps;\r
- }\r
- hob->profile.max_num_qps = u32_temp;\r
- hob->profile.log2_max_qps = ceil_log2(u32_temp + (1U<<hob->dev_lims.log2_rsvd_qps) \r
- + THH_NUM_RSVD_QP);\r
- }\r
- \r
- \r
- if ((calc_at_minimum & THH_PROFILE_CALC_CQ_AT_MINIMUM) == 0) {\r
- change_flag++;\r
- temp = (u_int64_t)(hob->profile.max_num_cqs) * (100 - profile_input_data.reduction_pct_cqs);\r
- if (temp & MAKE_ULONGLONG(0xFFFFFFFF00000000)) {\r
- temp = (u_int64_t)(hob->profile.max_num_cqs) * (1024 - (profile_input_data.reduction_pct_cqs*10));\r
- temp >>= 10;\r
- u32_temp = (u_int32_t)(temp & 0xFFFFFFFF);\r
- } else {\r
- /* use more exact percentages -- but still not floating point */\r
- u32_temp = (u_int32_t)temp;\r
- u32_temp /= 100;\r
- }\r
- if (u32_temp <= (u_int32_t)profile_input_data.min_cqs) {\r
- calc_at_minimum |= THH_PROFILE_CALC_CQ_AT_MINIMUM;\r
- u32_temp = profile_input_data.min_cqs;\r
- }\r
- hob->profile.max_num_cqs = u32_temp;\r
- hob->profile.log2_max_cqs = ceil_log2(u32_temp + (1U<<hob->dev_lims.log2_rsvd_cqs));\r
- }\r
-\r
- if ((calc_at_minimum & THH_PROFILE_CALC_PD_AT_MINIMUM) == 0) {\r
- change_flag++;\r
- temp = (u_int64_t)(hob->profile.max_num_pds) * (100 - profile_input_data.reduction_pct_pds);\r
- if (temp & MAKE_ULONGLONG(0xFFFFFFFF00000000)) {\r
- temp = (u_int64_t)(hob->profile.max_num_pds) * (1024 - (profile_input_data.reduction_pct_pds*10));\r
- temp >>= 10;\r
- u32_temp = (u_int32_t)(temp & 0xFFFFFFFF);\r
- } else {\r
- /* use more exact percentages -- but still not floating point */\r
- u32_temp = (u_int32_t)temp;\r
- u32_temp /= 100;\r
- }\r
- if (u32_temp <= (u_int32_t)profile_input_data.min_pds) {\r
- calc_at_minimum |= THH_PROFILE_CALC_PD_AT_MINIMUM;\r
- u32_temp = profile_input_data.min_pds;\r
- }\r
- hob->profile.max_num_pds = u32_temp;\r
- }\r
-\r
- if ((calc_at_minimum & THH_PROFILE_CALC_REG_AT_MINIMUM) == 0) {\r
- change_flag++;\r
- temp = (u_int64_t)(hob->profile.num_external_mem_regions) * (100 - profile_input_data.reduction_pct_regions);\r
- if (temp & MAKE_ULONGLONG(0xFFFFFFFF00000000)) {\r
- temp = (u_int64_t)(hob->profile.num_external_mem_regions) * (1024 - (profile_input_data.reduction_pct_regions*10));\r
- temp >>= 10;\r
- u32_temp = (u_int32_t)(temp & 0xFFFFFFFF);\r
- } else {\r
- /* use more exact percentages -- but still not floating point */\r
- u32_temp = (u_int32_t)temp;\r
- u32_temp /= 100;\r
- }\r
- if (u32_temp <= (u_int32_t)profile_input_data.min_regions) {\r
- calc_at_minimum |= THH_PROFILE_CALC_REG_AT_MINIMUM;\r
- u32_temp = profile_input_data.min_regions;\r
- }\r
- hob->profile.num_external_mem_regions = u32_temp;\r
- }\r
-\r
- if ((calc_at_minimum & THH_PROFILE_CALC_WIN_AT_MINIMUM) == 0) {\r
- change_flag++;\r
- temp = (u_int64_t)(hob->profile.num_mem_windows) * (100 - profile_input_data.reduction_pct_windows);\r
- if (temp & MAKE_ULONGLONG(0xFFFFFFFF00000000)) {\r
- temp = (u_int64_t)(hob->profile.num_mem_windows) * (1024 - (profile_input_data.reduction_pct_windows*10));\r
- temp >>= 10;\r
- u32_temp = (u_int32_t)(temp & 0xFFFFFFFF);\r
- } else {\r
- /* use more exact percentages -- but still not floating point */\r
- u32_temp = (u_int32_t)temp;\r
- u32_temp /= 100;\r
- }\r
- if (u32_temp <= (u_int32_t)profile_input_data.min_windows) {\r
- calc_at_minimum |= THH_PROFILE_CALC_WIN_AT_MINIMUM;\r
- u32_temp = profile_input_data.min_windows;\r
- }\r
- hob->profile.num_mem_windows = u32_temp;\r
- }\r
- if (hob->profile.log2_inflight_rdma_per_qp > THH_DDR_LOG2_INFLIGHT_RDMA_PER_QP) {\r
- hob->profile.log2_inflight_rdma_per_qp--;\r
- change_flag++;\r
- }\r
-\r
- /* check if we were able to perform any reductions */\r
- if (change_flag == 0) {\r
- MTL_ERROR1("THH_calculate_default_profile: DDR memory to small for MIN profile\n");\r
- ddr_alloc_iterator = (MT_size_t *)&(ddr_alloc_vec);\r
- for (i = 0; i < hob->profile.ddr_alloc_vec_size; i++, ddr_alloc_iterator++) {\r
- if ((*ddr_alloc_iterator) == THH_DDRMM_INVALID_SZ) {\r
- temp_size = 0; /* no allocation */\r
- } else if ((*ddr_alloc_iterator) >= ceil_log2(hob->profile.ddr_size)) {\r
- temp_size = hob->profile.ddr_size;\r
- MTL_ERROR1(MT_FLFMT("THH_calculate_profile: %s uses ALL available DDR memory"), \r
- THH_get_ddr_allocation_string(i)); \r
- } else {\r
- temp_size = (((MT_size_t) 1ul) << (*ddr_alloc_iterator));\r
- }\r
- MTL_ERROR1(MT_FLFMT("THH_calculate_profile:DDR: %s = "SIZE_T_XFMT"("SIZE_T_DFMT")"), \r
- THH_get_ddr_allocation_string(i), temp_size, temp_size); \r
- }\r
- return HH_EAGAIN;\r
- }\r
- } else {\r
- ddr_calc_loop = FALSE;\r
- }\r
- }\r
- \r
- THH_check_profile(hob); /* final adjustment to catch dev-lim overruns*/\r
-\r
- /* adjust mcg hash table after final adjustment of mcg size */\r
- if (THH_DEV_LIM_MCG_ENABLED(hob)) {\r
- hob->profile.log2_mcg_hash_size = (hob->profile.log2_max_mcgs) + profile_input_data.log2_mcg_hash_proportion;\r
-/*** error C4296: '<' : expression is always false ***/\r
- //if (hob->profile.log2_mcg_hash_size < 0) {\r
- // hob->profile.log2_mcg_hash_size = 0;\r
- //}\r
- }\r
-\r
- THH_PRINT_PROFILE(&(hob->profile));\r
- MTL_DEBUG4("Leaving THH_calculate_profile\n");\r
-\r
- if (sugg_profile_p != NULL) { \r
- sugg_profile_p->num_mw = (u_int32_t)hob->profile.num_mem_windows;\r
- sugg_profile_p->num_qp = (u_int32_t)hob->profile.max_num_qps;\r
- sugg_profile_p->num_cq = (u_int32_t)hob->profile.max_num_cqs;\r
- sugg_profile_p->num_pd = (u_int32_t)hob->profile.max_num_pds;\r
- sugg_profile_p->num_mr = (u_int32_t)hob->profile.num_external_mem_regions;\r
- sugg_profile_p->max_qp_ous_rd_atom = (1U<<hob->profile.log2_inflight_rdma_per_qp);\r
- }\r
- if ((profile_user_data != NULL) && (profile_user_data->require != 0) && (need_to_loop == TRUE)) {\r
- MTL_ERROR1("THH_calculate_default_profile: Provided profile requires too many resources\n");\r
- return HH_ENOMEM;\r
- }\r
- return HH_OK;\r
-}\r
-\r
-/*****************************************************************************\r
-******************************************************************************\r
-************************ HOB Interface FUNCTIONS ****************************\r
-******************************************************************************\r
-******************************************************************************/\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_close_hca\r
- *\r
- * Description: This function stops HCA hardware activity and frees all associated resources.\r
- *\r
- * input:\r
- * hca_hndl\r
- * output: \r
- * none\r
- * returns:\r
- * HH_OK\r
- * HH_EINVAL_HCA_HNDL\r
- * HH_ERR\r
- *\r
- * Comments: If any errors occur, continue process of de-allocating resources. However, log the errors,\r
- * and return HH_ERR instead of HH_OK\r
- *\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_close_hca_internal(HH_hca_hndl_t hca_hndl, MT_bool invoked_from_destroy)\r
-{\r
- /* TBD - Complete function */\r
- THH_cmd_status_t cmd_ret;\r
- MT_bool have_error = FALSE;\r
- HH_ret_t ret = HH_OK;\r
- MT_phys_addr_t *ddr_alloc_area;\r
- MT_size_t *ddr_alloc_size;\r
- u_int32_t i;\r
- u_int16_t num_ports;\r
- call_result_t res;\r
- THH_hob_t thh_hob_p;\r
- DECLARE_FATAL_VARS;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_close_hca: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_close_hca : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_close_hca : ERROR : HOB is already destroyed\n");\r
- return HH_ERR;\r
- }\r
- \r
- /* uninterruptible acquire. Want to be sure to clean up */\r
- MOSAL_mutex_acq_ui(&(thh_hob_p->mtx));\r
- if (hca_hndl->status == HH_HCA_STATUS_CLOSED) {\r
- MOSAL_mutex_rel(&(thh_hob_p->mtx));\r
- MTL_ERROR1("THH_hob_close_hca: Device already closed\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- \r
- /* move the HCA to CLOSING state, preserving fatal indicators */\r
- MOSAL_spinlock_dpc_lock(&thh_hob_p->fatal_spl);\r
- if ((thh_hob_p->thh_state & THH_STATE_RUNNING) == 0) {\r
- MOSAL_spinlock_unlock(&thh_hob_p->fatal_spl);\r
- MOSAL_mutex_rel(&(thh_hob_p->mtx));\r
- MTL_ERROR1(MT_FLFMT("THH_hob_close_hca: already invoked"));\r
- return HH_EBUSY;\r
- }\r
- thh_hob_p->thh_state &= THH_STATE_HAVE_ANY_FATAL;\r
- thh_hob_p->thh_state |= THH_STATE_CLOSING;\r
- MOSAL_spinlock_unlock(&thh_hob_p->fatal_spl);\r
-\r
- /* transfer to closing state */ \r
- WAIT_IF_FATAL(thh_hob_p);\r
- if (have_fatal == FALSE) {\r
- num_ports = thh_hob_p->dev_lims.num_ports;\r
- for (i = 1; i <= num_ports; i++) {\r
- cmd_ret = THH_cmd_CLOSE_IB(thh_hob_p->cmd, (IB_port_t) i);\r
- if (cmd_ret != THH_CMD_STAT_OK) {\r
- MTL_ERROR1("THH_hob_close_hca: THH_cmd_CLOSE_IB error (%d)\n", cmd_ret);\r
- have_error = TRUE;\r
- }\r
- }\r
- }\r
- /* test if a fatal error occurred during CLOSE_IB. */\r
- if (have_fatal == FALSE) {\r
- WAIT_IF_FATAL(thh_hob_p);\r
- }\r
- thh_hob_p->compl_eq = THH_INVALID_EQN;\r
- thh_hob_p->ib_eq = THH_INVALID_EQN;\r
- \r
- /* destroy eventq mgr. Event manager must destroy all EQs */\r
- ret = THH_eventp_destroy( thh_hob_p->eventp );\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_close_hca: THH_eventp_destroy error (%d)\n", ret);\r
- have_error = TRUE;\r
- }\r
- thh_hob_p->eventp = (THH_eventp_t)THH_INVALID_HNDL;\r
-\r
- if (thh_hob_p->mcgm != (THH_mcgm_t)THH_INVALID_HNDL) {\r
- ret = THH_mcgm_destroy(thh_hob_p->mcgm );\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_close_hca: THH_mcgm_destroy error (%d)\n", ret);\r
- have_error = TRUE;\r
- }\r
- thh_hob_p->mcgm = (THH_mcgm_t)THH_INVALID_HNDL;\r
- }\r
-\r
- MTL_DEBUG4("%s: calling MOSAL_unmap_phys_addr FOR KAR = " VIRT_ADDR_FMT "\n", __func__,\r
- (MT_virt_addr_t) thh_hob_p->kar_addr);\r
- if ((res = (MOSAL_unmap_phys_addr(MOSAL_get_kernel_prot_ctx(), (MT_virt_addr_t) thh_hob_p->kar_addr, \r
- ((MT_size_t)1 << thh_hob_p->profile.log2_uar_pg_size)))) != MT_OK) {\r
- MTL_ERROR1("THH_hob_close_hca: MOSAL_unmap_phys_addr error for kar: %d\n", res);\r
- have_error = TRUE;\r
- }\r
- thh_hob_p->kar_addr = (MT_virt_addr_t) 0;\r
- \r
- ret = THH_uar_destroy(thh_hob_p->kar);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_close_hca: THH_uar_destroy error (%d)\n", ret);\r
- have_error = TRUE;\r
- }\r
- thh_hob_p->kar = (THH_uar_t)THH_INVALID_HNDL;\r
-\r
-\r
- if (thh_hob_p->udavm_use_priv) {\r
- ret = THH_udavm_destroy(thh_hob_p->udavm);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_close_hca: THH_udavm_destroy error (%d)\n", ret);\r
- have_error = TRUE;\r
- }\r
- thh_hob_p->udavm = (THH_udavm_t)THH_INVALID_HNDL;\r
-\r
- ret = THH_mrwm_deregister_mr(thh_hob_p->mrwm, thh_hob_p->udavm_lkey);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_close_hca: THH_mrwm_deregister_mr error (%d)\n", ret);\r
- have_error = TRUE;\r
- }\r
-\r
- if ((res = MOSAL_unmap_phys_addr( MOSAL_get_kernel_prot_ctx(), \r
- (MT_virt_addr_t) thh_hob_p->udavm_table , \r
- thh_hob_p->udavm_table_size )) != MT_OK) {\r
- MTL_ERROR1("THH_hob_close_hca: MOSAL_unmap_phys_addr error for udavm: %d\n", res);\r
- have_error = TRUE;\r
- }\r
- thh_hob_p->udavm_table = (MT_virt_addr_t) NULL;\r
-\r
- ret = THH_ddrmm_free(thh_hob_p->ddrmm, thh_hob_p->udavm_table_ddr, thh_hob_p->udavm_table_size);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_close_hca: THH_ddrmm_free error (%d)\n", ret);\r
- have_error = TRUE;\r
- }\r
- \r
- }\r
- thh_hob_p->udavm = (THH_udavm_t)THH_INVALID_HNDL;\r
- thh_hob_p->udavm_table = (MT_virt_addr_t) NULL;\r
- thh_hob_p->udavm_table_ddr = (MT_phys_addr_t) 0;\r
- thh_hob_p->udavm_table_size = 0;\r
- thh_hob_p->udavm_lkey = 0;\r
-\r
- if (thh_hob_p->srqm != (THH_srqm_t)THH_INVALID_HNDL) { /* SRQs are supported - SRQM exists */\r
- ret = THH_srqm_destroy( thh_hob_p->srqm);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_close_hca: THH_srqm_destroy error %s(%d)\n", HH_strerror_sym(ret), ret);\r
- have_error = TRUE;\r
- }\r
- thh_hob_p->srqm = (THH_srqm_t)THH_INVALID_HNDL;\r
- }\r
- \r
- ret = THH_qpm_destroy( thh_hob_p->qpm, have_error);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_close_hca: THH_qpm_destroy error (%d)\n", ret);\r
- have_error = TRUE;\r
- }\r
- thh_hob_p->qpm = (THH_qpm_t)THH_INVALID_HNDL;\r
-\r
- FREE(thh_hob_p->init_ib_props);\r
- thh_hob_p->init_ib_props = ( THH_port_init_props_t *) NULL;\r
-\r
- ret = THH_cqm_destroy( thh_hob_p->cqm, have_error);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_close_hca: THH_cqm_destroy error (%d)\n", ret);\r
- have_error = TRUE;\r
- }\r
- thh_hob_p->cqm = (THH_cqm_t)THH_INVALID_HNDL;\r
-\r
- ret = THH_mrwm_destroy(thh_hob_p->mrwm, have_error);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_close_hca: THH_mrwm_destroy error (%d)\n", ret);\r
- have_error = TRUE;\r
- }\r
- thh_hob_p->mrwm = (THH_mrwm_t)THH_INVALID_HNDL;\r
-\r
- ret = THH_uldm_destroy(thh_hob_p->uldm );\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_close_hca: THH_uldm_destroy error (%d)\n", ret);\r
- have_error = TRUE;\r
- }\r
- thh_hob_p->uldm = (THH_uldm_t)THH_INVALID_HNDL;\r
-\r
- ret = THH_cmd_revoke_ddrmm(thh_hob_p->cmd);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_close_hca: THH_cmd_revoke_ddrmm error (%d)\n", ret);\r
- have_error = TRUE;\r
- }\r
-\r
- ddr_alloc_area = (MT_phys_addr_t *) &(thh_hob_p->ddr_alloc_base_addrs_vec);\r
- ddr_alloc_size = (MT_size_t *)&(thh_hob_p->ddr_alloc_size_vec);\r
- for (i = 0; i < thh_hob_p->profile.ddr_alloc_vec_size; i++, ddr_alloc_area++, ddr_alloc_size++) {\r
- ret = *ddr_alloc_area != THH_DDRMM_INVALID_PHYS_ADDR ?\r
- THH_ddrmm_free(thh_hob_p->ddrmm,*ddr_alloc_area, ((MT_size_t)1<< (*ddr_alloc_size))) : HH_OK;\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_close_hca: THH_ddrmm_free error (%d). i = %d\n", ret, i);\r
- have_error = TRUE;\r
- }\r
- }\r
-\r
- /* test for fatal again here */\r
- if (have_fatal == FALSE) {\r
- WAIT_IF_FATAL(thh_hob_p);\r
- }\r
- if (have_fatal == FALSE) {\r
- MTL_TRACE1("THH_hob_close_hca: Performing THH_cmd_CLOSE_HCA (no fatal)\n");\r
-#ifdef SIMULATE_HALT_HCA\r
- cmd_ret = THH_cmd_CLOSE_HCA(thh_hob_p->cmd);\r
-#else\r
- cmd_ret = THH_cmd_CLOSE_HCA(thh_hob_p->cmd, FALSE);\r
-#endif\r
- if (cmd_ret != THH_CMD_STAT_OK) {\r
- MTL_ERROR1("THH_hob_close_hca: THH_cmd_CLOSE_HCA error (%d)\n", cmd_ret);\r
- have_error = TRUE;\r
- }\r
- }\r
- hca_hndl->status = HH_HCA_STATUS_CLOSED;\r
-\r
- /* move state to "CLOSED"*/\r
- MOSAL_spinlock_dpc_lock(&thh_hob_p->fatal_spl);\r
- thh_hob_p->thh_state &= THH_STATE_HAVE_ANY_FATAL;\r
- thh_hob_p->thh_state |= THH_STATE_CLOSED;\r
- MOSAL_spinlock_unlock(&thh_hob_p->fatal_spl);\r
- MOSAL_mutex_rel(&(thh_hob_p->mtx));\r
-\r
- MTL_TRACE2("THH_hob_close_hca: device name %s\n", hca_hndl->dev_desc);\r
-\r
- if (have_fatal == FALSE) {\r
- WAIT_IF_FATAL(thh_hob_p);\r
- }\r
- if ((have_fatal == TRUE) && (invoked_from_destroy == FALSE)) {\r
- // Leo: (WINDOWS) restart doen't work because the card reset doesn't work\r
- #ifndef __WIN__\r
- MTL_TRACE1("THH_hob_close_hca: HAVE FATAL, restarting\n");\r
- ret = THH_hob_restart(hca_hndl);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_close_hca: THH_hob_restart error (%d)\n", ret);\r
- have_error = TRUE;\r
- }\r
- #endif\r
- }\r
- if (have_error && (have_fatal == FALSE)) {\r
- return HH_ERR;\r
- } else {\r
- return(HH_OK);\r
- }\r
-} /* THH_hob_close_hca_internal */\r
-\r
-HH_ret_t THH_hob_close_hca(HH_hca_hndl_t hca_hndl)\r
-{\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- return (THH_hob_close_hca_internal(hca_hndl,FALSE));\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_destroy\r
- *\r
- * Description: Deregister given device from HH and free the HH object.\r
- *\r
- * input:\r
- * hca_hndl\r
- * output: \r
- * none\r
- * returns:\r
- * HH_OK\r
- * HH_EINVAL_HCA_HNDL\r
- *\r
- * Comments: If HCA is still open,THH_hob_close_hca() is \r
- * invoked before freeing the THH_hob.\r
- *\r
- * Returns HH_EINVAL_HCA_HNDL if any function called internally fails \r
- *\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_destroy(HH_hca_hndl_t hca_hndl)\r
-{\r
- HH_ret_t ret, fn_ret = HH_OK;\r
- THH_cmd_status_t cmd_ret;\r
- THH_hob_t hob_p;\r
- int int_ret = 0;\r
-#if !defined(__DARWIN__) && !defined(__WIN__)\r
- MT_virt_addr_t va;\r
-#endif\r
- call_result_t mosal_ret;\r
- MT_bool have_fatal = FALSE;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_destroy: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_destroy : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- \r
- /* return ERROR if device is still open */\r
- if (hca_hndl->status != HH_HCA_STATUS_CLOSED) {\r
- MTL_ERROR1("THH_hob_destroy: Unloading device %s: while it is still open. Attempting to close it.\n", hca_hndl->dev_desc);\r
- ret = THH_hob_close_hca_internal(hca_hndl, TRUE);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_destroy: Could not close device %s: not opened or unknown (err=%d)\n", hca_hndl->dev_desc, ret);\r
- fn_ret = HH_EINVAL_HCA_HNDL;\r
- }\r
- hca_hndl->status = HH_HCA_STATUS_CLOSED;\r
- }\r
-\r
- MTL_TRACE2("THH_hob_destroy: removing the device %s\n", hca_hndl->dev_desc);\r
- hob_p = THHOBP(hca_hndl);\r
- if (hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_destroy : ERROR : HOB is already destroyed\n");\r
- return HH_ERR;\r
- }\r
- \r
-\r
- /* move the HCA to DESTROYING state, preserving fatal indicators */\r
- MOSAL_spinlock_dpc_lock(&hob_p->fatal_spl);\r
- if ((hob_p->thh_state & THH_STATE_DESTROYING) != 0) {\r
- MOSAL_spinlock_unlock(&hob_p->fatal_spl);\r
- MTL_ERROR1(MT_FLFMT("THH_hob_destroy: already invoked"));\r
- return HH_EBUSY;\r
- }\r
- hob_p->thh_state &= THH_STATE_HAVE_ANY_FATAL;\r
- hob_p->thh_state |= THH_STATE_DESTROYING;\r
- MOSAL_spinlock_unlock(&hob_p->fatal_spl);\r
- \r
-#ifndef __DARWIN__ /* TODO: add support in darwin for fatal error handling */\r
-\r
- /* release the fatal signalling thread */\r
- hob_p->fatal_thread_obj.have_fatal = FALSE;\r
- MOSAL_syncobj_signal(&hob_p->fatal_thread_obj.fatal_err_sync);\r
- mosal_ret = MOSAL_syncobj_waiton(&(hob_p->fatal_thread_obj.stop_sync), 10000000);\r
- if (mosal_ret != MT_OK) {\r
- if (mosal_ret == MT_EINTR) {\r
- MTL_DEBUG1(MT_FLFMT("%s: Received OS interrupt while initializing fatal error thread (err = %d)"), \r
- __func__,mosal_ret);\r
- fn_ret = HH_EINTR;\r
- } else {\r
- MTL_ERROR1(MT_FLFMT("%s: Timeout on destroying fatal error thread (err = %d)"), \r
- __func__,mosal_ret);\r
- fn_ret = HH_ERR;\r
- }\r
- }\r
-\r
-#endif /* not defined __DARWIN__ */\r
-\r
- /* unregister the device from HH */\r
- ret = HH_rem_hca_dev(hca_hndl);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_destroy: Could not remove device 0x%p: unknown (%d)\n", hca_hndl, ret);\r
- fn_ret = HH_EINVAL_HCA_HNDL;\r
- }\r
-\r
- /* destroy objects created in hob_create, and issue SYS_DIS command to Tavor */\r
- ret = THH_ddrmm_destroy(hob_p->ddrmm);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_destroy: Could not destroy ddrmm object (err = %d)\n", ret);\r
- fn_ret = HH_ERR;\r
- }\r
- /* do SYS_DIS only if do not have a fatal error state */\r
- if ((hob_p->thh_state & THH_STATE_HAVE_ANY_FATAL) == 0) {\r
- have_fatal = FALSE;\r
- cmd_ret = THH_cmd_SYS_DIS(hob_p->cmd);\r
- if (cmd_ret != THH_CMD_STAT_OK) {\r
- MTL_ERROR1("THH_hob_destroy: SYS_DIS command failed (err = %d)\n", cmd_ret);\r
- if (cmd_ret == THH_CMD_STAT_EFATAL) {\r
- have_fatal = TRUE;\r
- }\r
- fn_ret = HH_ERR;\r
- }\r
- } else {\r
- /* halt the HCA if delayed-halt flag was set, in fatal case only, \r
- * to make sure that there is no PCI activity. If fatal occurred during SYS_DIS above,\r
- * HCA was already closed, so don't need the "halt hca" operation\r
- */\r
- have_fatal = TRUE;\r
- if (hob_p->module_flags.fatal_delay_halt != 0) {\r
- MTL_DEBUG1(MT_FLFMT("%s: performing delayed halt-hca"), __func__);\r
- THH_hob_halt_hca(hob_p);\r
- }\r
- }\r
- \r
- ret = THH_cmd_destroy(hob_p->cmd);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_destroy: Could not destroy cmd object (err = %d)\n", ret);\r
- fn_ret = HH_ERR;\r
- }\r
-\r
- /* do PCI reset here if have a catastrophic error */\r
- if (have_fatal == TRUE) {\r
- /* perform sw reset */\r
- MTL_ERROR1(MT_FLFMT("%s: FATAL ERROR "), __func__);\r
-\r
-#if !defined(__DARWIN__) && !defined(__WIN__)\r
-#if 0 /*defined(__WIN__)*/\r
- if (hob_p->pci_hca_info.is_valid == TRUE) {\r
- MOSAL_reset_card( hob_p->pci_hca_info.bus, hob_p->pci_hca_info.dev_func );\r
- } \r
-#else \r
- /* Do the Tavor RESET */\r
- va = MOSAL_io_remap(hob_p->hw_props.cr_base + 0xF0010, 4);\r
- if ( va ) {\r
- /* perform sw reset */\r
- MTL_ERROR1(MT_FLFMT("%s: PERFORMING SW RESET. pa="PHYS_ADDR_FMT" va="VIRT_ADDR_FMT),\r
- __func__, hob_p->hw_props.cr_base + 0xF0010, va);\r
- MOSAL_MMAP_IO_WRITE_DWORD(((unsigned long)va),MOSAL_cpu_to_be32(0x00000001));\r
- /* sleep for one second, per PRM */\r
- MOSAL_delay_execution(1000000);\r
- MOSAL_io_unmap(va);\r
- }\r
-\r
- /* now, rewrite the PCI configuration */\r
- if (hob_p->pci_bridge_info.is_valid == TRUE) {\r
- write_pci_config(hob_p->pci_bridge_info.bus, hob_p->pci_bridge_info.dev_func,\r
- hob_p->pci_bridge_info.config);\r
- }\r
- if (hob_p->pci_hca_info.is_valid == TRUE) {\r
- write_pci_config(hob_p->pci_hca_info.bus, hob_p->pci_hca_info.dev_func,\r
- hob_p->pci_hca_info.config);\r
- }\r
-#endif /* defined __WIN__ */\r
-#endif /* not defined __DARWIN__ */\r
- }\r
-\r
- int_ret = VIP_delay_unlock_destroy(hob_p->delay_unlocks);\r
- if (int_ret != 0) {\r
- MTL_ERROR1("THH_hob_destroy: Could not destroy delay_unlocks (err = %d)\n", int_ret);\r
- fn_ret = HH_ERR;\r
- }\r
- \r
- if (hob_p->fw_error_buf_start_va != (MT_virt_addr_t)(MT_ulong_ptr_t) NULL) {\r
- MOSAL_io_unmap(hob_p->fw_error_buf_start_va);\r
- }\r
-\r
- if (hob_p->fw_error_buf != NULL) {\r
- FREE(hob_p->fw_error_buf);\r
- }\r
-\r
- MOSAL_mutex_free(&(hob_p->mtx));\r
- /* Finally, free the THH object */\r
- FREE(hca_hndl->device);\r
- hca_hndl->device = NULL;\r
-\r
- return(fn_ret);\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_open_hca\r
- *\r
- * Description: This function opens the given HCA and initializes the HCA with \r
- * given properties/ capabilities. if prop_props_p is NULL a default \r
- * HCA profile will be set up.\r
- *\r
- * input:\r
- * hca_hndl\r
- * prop_props_p - Proprietary properties (Non IB)\r
- * output: \r
- * none\r
- * returns:\r
- * HH_OK\r
- * HH_EINVAL\r
- * HH_EBUSY\r
- *\r
- * Comments: If HCA is still open,THH_hob_close_hca() is \r
- * invoked before freeing the THH_hob.\r
- *\r
- * Returns HH_EINVAL_HCA_HNDL if any function called internally fails \r
- *\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_open_hca(HH_hca_hndl_t hca_hndl, \r
- EVAPI_hca_profile_t *prop_props_p,\r
- EVAPI_hca_profile_t *sugg_profile_p)\r
-{\r
- MT_virt_addr_t kar_addr;\r
- HH_ret_t ret;\r
- THH_cmd_status_t cmd_ret;\r
- THH_hca_props_t local_hca_props;\r
- MT_phys_addr_t *ddr_alloc_area;\r
- MT_size_t *ddr_alloc_size;\r
- u_int32_t i;\r
- THH_internal_mr_t udav_internal_mr;\r
- MT_size_t udav_entry_size = 0, udav_table_size = 0;\r
- MT_phys_addr_t udav_phys_addr = 0;\r
- MT_virt_addr_t udav_virt_addr = 0;\r
- VAPI_lkey_t dummy_key;\r
- THH_eventp_res_t event_res;\r
- u_int16_t num_ports, last_port_initialized;\r
- THH_hob_t thh_hob_p;\r
- VAPI_size_t udav_vapi_size;\r
- THH_qpm_init_t thh_qpm_init_params;\r
- MT_bool have_fatal = FALSE;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- MTL_DEBUG4("Entering THH_hob_open_hca\n");\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_open_hca: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_open_hca : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_open_hca: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- /* Get user profile if available -- if not, use default proportionally to resources. */\r
-\r
- /* DDR parameters. Get from default profile. For each one, check that does not exceed */\r
- /* The maximum resource value supportable by the installed card. */\r
-\r
-/*\r
- Objects:\r
- cmd; -- already exists\r
- ddrmm; -- already exists\r
- uldm; -- uar, pd: log2_max_uar, log2_max_pg_sz, max_pd\r
- mrwm; -- log2_mpt_sz (log2 of number of entries in MPT)\r
- log2_mtt_sz (Log2 of number of entries in the MTT) \r
- max_mem_reg (Maximum memory regions to be allocated in the MPT for external registration only)\r
- max_mem_reg_internal (Maximum memory regions to be alloc in the MPT for internal use only (WQEs and CQEs buffers) )\r
- max_mem_win (Maximum memory windows to be allocated in the MPT)\r
- cqm; -- log2_max_cq,\r
- eecm; -- \r
- qpm; -- log2_max_qp,\r
- privileged_ud_av (boolean)\r
- udavm; -- max_av\r
- mcgm; -- num mcg's: IBTA min = 512, 8 QPs/group\r
- eventp; -- 64 event queues\r
- kar; -- UAR 0 (no extra resources needed)\r
- \r
-*/\r
-\r
- /* Test if have fatal error, and move thh_state to "opening" */\r
- MOSAL_spinlock_dpc_lock(&thh_hob_p->fatal_spl);\r
- if ((thh_hob_p->thh_state & THH_STATE_HAVE_ANY_FATAL) != 0) {\r
- /* already in FATAL state */\r
- MOSAL_spinlock_unlock(&thh_hob_p->fatal_spl);\r
- MTL_DEBUG4(MT_FLFMT("%s: already in FATAL state"), __func__); \r
- MT_RETURN(HH_EFATAL);\r
- } else if (thh_hob_p->thh_state != THH_STATE_CLOSED) {\r
- MOSAL_spinlock_unlock(&thh_hob_p->fatal_spl);\r
- MTL_ERROR1(MT_FLFMT("THH_hob_open_hca: ERROR : Device not closed. state = 0x%x"),thh_hob_p->thh_state );\r
- MT_RETURN(HH_EBUSY);\r
- }\r
- thh_hob_p->thh_state = THH_STATE_OPENING;\r
- MOSAL_spinlock_unlock(&thh_hob_p->fatal_spl);\r
- \r
- /* get the MUTEX */\r
- if (MOSAL_mutex_acq(&(thh_hob_p->mtx), TRUE) != MT_OK) {\r
- MTL_ERROR1(MT_FLFMT("THH_hob_open_hca: received signal. returning"));\r
- ret = HH_EINTR;\r
- goto post_state_change_error;\r
- }\r
- if (hca_hndl->status == HH_HCA_STATUS_OPENED) {\r
- MTL_ERROR1("THH_hob_open_hca: ERROR : Device already open\n");\r
- ret = HH_EBUSY;\r
- goto post_mutex_acquire_err;\r
- }\r
-\r
- if (prop_props_p != NULL) {\r
- THH_PRINT_USR_PROFILE(prop_props_p);\r
- }\r
- ret = THH_calculate_profile(thh_hob_p, prop_props_p, sugg_profile_p);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("THH_hob_open_hca: could not create internal profile (%d)"), ret);\r
- if (sugg_profile_p != NULL) {\r
- THH_PRINT_USR_PROFILE(sugg_profile_p);\r
- }\r
- //ret = HH_ERR;\r
- goto post_mutex_acquire_err;\r
- }\r
- if (sugg_profile_p != NULL) {\r
- THH_PRINT_USR_PROFILE(sugg_profile_p);\r
- }\r
-\r
- /* check profile against QUERY_DEV_LIMS data*/\r
- ret = THH_check_profile(thh_hob_p);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_open_hca: Profile check failed (%d)\n", ret);\r
- ret = HH_ERR;\r
- goto post_mutex_acquire_err;\r
- }\r
-\r
- /* Do ddrmm allocation here, because we need the allocated MCG base address */\r
- /* for the INIT_HCA command following the centralized DDR allocation */\r
- calculate_ddr_alloc_vec(thh_hob_p, &(thh_hob_p->profile), &(thh_hob_p->ddr_alloc_size_vec));\r
-\r
- /* Allocate all required DDR areas */\r
- ret = THH_ddrmm_alloc_sz_aligned(thh_hob_p->ddrmm, \r
- thh_hob_p->profile.ddr_alloc_vec_size, /*number of chunks */\r
- (MT_size_t *) &(thh_hob_p->ddr_alloc_size_vec), /* IN */\r
- (MT_phys_addr_t *)&(thh_hob_p->ddr_alloc_base_addrs_vec) ); /* OUT */\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_open_hca: could not allocate required areas in DDR (%s)\n", HH_strerror_sym(ret));\r
- ret = HH_ERR;\r
- goto post_mutex_acquire_err;\r
- }\r
- \r
- /* call cmd interface to initialize its mailboxes in DDR */\r
- ret = THH_cmd_assign_ddrmm(thh_hob_p->cmd, thh_hob_p->ddrmm);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_open_hca: Failed THH_cmd_assign_ddrmm (%s)\n",HH_strerror_sym(ret)); \r
- goto cmd_assign_ddrmm_err;\r
- }\r
- \r
- /* set up parameters for INIT HCA */\r
- memset(&local_hca_props, 0, sizeof(THH_hca_props_t));\r
-#ifdef MT_LITTLE_ENDIAN\r
- local_hca_props.he = TAVOR_IF_HOST_LTLENDIAN;\r
-#else\r
- local_hca_props.he = TAVOR_IF_HOST_BIGENDIAN;\r
-#endif\r
- local_hca_props.re = FALSE; /* not a router */\r
- local_hca_props.udp = TRUE; /* check port in UD AV */ \r
- local_hca_props.ud = thh_hob_p->profile.use_priv_udav; \r
- \r
- local_hca_props.qpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr = \r
- GET_DDR_ADDR(thh_hob_p->ddr_alloc_base_addrs_vec.cqc_base_addr,thh_hob_p->ddr_props.dh,\r
- thh_hob_p->ddr_props.ddr_start_adr);\r
- local_hca_props.qpc_eec_cqc_eqc_rdb_parameters.eec_base_addr = \r
- GET_DDR_ADDR(thh_hob_p->ddr_alloc_base_addrs_vec.eec_base_addr,thh_hob_p->ddr_props.dh,\r
- thh_hob_p->ddr_props.ddr_start_adr);\r
- local_hca_props.qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr = \r
- GET_DDR_ADDR(thh_hob_p->ddr_alloc_base_addrs_vec.eqc_base_addr,thh_hob_p->ddr_props.dh,\r
- thh_hob_p->ddr_props.ddr_start_adr);\r
- local_hca_props.qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr = \r
- GET_DDR_ADDR(thh_hob_p->ddr_alloc_base_addrs_vec.qpc_base_addr,thh_hob_p->ddr_props.dh,\r
- thh_hob_p->ddr_props.ddr_start_adr);\r
- local_hca_props.qpc_eec_cqc_eqc_rdb_parameters.rdb_base_addr = \r
- GET_DDR_ADDR(thh_hob_p->ddr_alloc_base_addrs_vec.rdb_base_addr,thh_hob_p->ddr_props.dh,\r
- thh_hob_p->ddr_props.ddr_start_adr);\r
- local_hca_props.qpc_eec_cqc_eqc_rdb_parameters.log_num_of_cq = \r
- (u_int8_t)thh_hob_p->profile.log2_max_cqs;\r
- // local_hca_props.qpc_eec_cqc_eqc_rdb_parameters.log_num_of_ee = thh_hob_p->profile.log2_max_eecs;\r
- local_hca_props.qpc_eec_cqc_eqc_rdb_parameters.log_num_of_ee = 0;\r
- local_hca_props.qpc_eec_cqc_eqc_rdb_parameters.log_num_eq = thh_hob_p->profile.log2_max_eqs;\r
- local_hca_props.qpc_eec_cqc_eqc_rdb_parameters.log_num_of_qp = (u_int8_t)thh_hob_p->profile.log2_max_qps;\r
- local_hca_props.qpc_eec_cqc_eqc_rdb_parameters.eqpc_base_addr = \r
- GET_DDR_ADDR(thh_hob_p->ddr_alloc_base_addrs_vec.eqpc_base_addr,thh_hob_p->ddr_props.dh,\r
- thh_hob_p->ddr_props.ddr_start_adr);\r
- local_hca_props.qpc_eec_cqc_eqc_rdb_parameters.log_num_of_srq = (u_int8_t)thh_hob_p->profile.log2_max_srqs;\r
- local_hca_props.qpc_eec_cqc_eqc_rdb_parameters.srqc_base_addr = \r
- GET_DDR_ADDR(thh_hob_p->ddr_alloc_base_addrs_vec.srqc_base_addr,thh_hob_p->ddr_props.dh,\r
- thh_hob_p->ddr_props.ddr_start_adr);\r
- local_hca_props.qpc_eec_cqc_eqc_rdb_parameters.eeec_base_addr = \r
- GET_DDR_ADDR(thh_hob_p->ddr_alloc_base_addrs_vec.eeec_base_addr,thh_hob_p->ddr_props.dh,\r
- thh_hob_p->ddr_props.ddr_start_adr);\r
- \r
- local_hca_props.udavtable_memory_parameters.l_key = THH_UDAVM_PRIV_RESERVED_LKEY;\r
- local_hca_props.udavtable_memory_parameters.pd = THH_RESERVED_PD;\r
- local_hca_props.udavtable_memory_parameters.xlation_en = TRUE;\r
- \r
- local_hca_props.tpt_parameters.log_mpt_sz = (u_int8_t)thh_hob_p->profile.log2_max_mpt_entries;\r
- local_hca_props.tpt_parameters.mpt_base_adr = \r
- GET_DDR_ADDR(thh_hob_p->ddr_alloc_base_addrs_vec.mpt_base_addr,thh_hob_p->ddr_props.dh,\r
- thh_hob_p->ddr_props.ddr_start_adr);\r
- local_hca_props.tpt_parameters.mtt_base_addr = \r
- GET_DDR_ADDR(thh_hob_p->ddr_alloc_base_addrs_vec.mtt_base_addr,thh_hob_p->ddr_props.dh,\r
- thh_hob_p->ddr_props.ddr_start_adr);\r
- local_hca_props.tpt_parameters.pfto = 0; /* TBD -- not yet supported. Page Fault RNR Timeout */\r
- local_hca_props.tpt_parameters.mtt_segment_size = (u_int8_t)((thh_hob_p->profile.log2_mtt_entries_per_seg + THH_DDR_LOG2_MTT_ENTRY_SIZE)\r
- - THH_DDR_LOG2_MIN_MTT_SEG_SIZE);\r
- \r
- local_hca_props.uar_parameters.uar_base_addr = thh_hob_p->hw_props.uar_base;\r
- local_hca_props.uar_parameters.uar_page_sz = thh_hob_p->profile.log2_uar_pg_size - 12;\r
- local_hca_props.uar_parameters.uar_scratch_base_addr = \r
- GET_DDR_ADDR(thh_hob_p->ddr_alloc_base_addrs_vec.uar_scratch_base_addr,thh_hob_p->ddr_props.dh,\r
- thh_hob_p->ddr_props.ddr_start_adr);\r
- \r
- local_hca_props.multicast_parameters.log_mc_table_sz = (u_int8_t)thh_hob_p->profile.log2_max_mcgs;\r
- local_hca_props.multicast_parameters.mc_base_addr = \r
- GET_DDR_ADDR(thh_hob_p->ddr_alloc_base_addrs_vec.mcg_base_addr,thh_hob_p->ddr_props.dh,\r
- thh_hob_p->ddr_props.ddr_start_adr);\r
- local_hca_props.multicast_parameters.mc_hash_fn = 0;\r
- local_hca_props.multicast_parameters.log_mc_table_entry_sz = (u_int16_t)(thh_hob_p->profile.log2_mcg_entry_size);\r
- local_hca_props.multicast_parameters.mc_table_hash_sz = 1 << (thh_hob_p->profile.log2_mcg_hash_size);\r
-\r
- /* INIT_HCA command */\r
- cmd_ret = THH_cmd_INIT_HCA(thh_hob_p->cmd,&local_hca_props);\r
- if (cmd_ret != THH_CMD_STAT_OK) {\r
- MTL_ERROR1("THH_hob_open_hca: CMD_error in THH_cmd_INIT_HCA (%d)\n", cmd_ret);\r
- ret = HH_EAGAIN;\r
- goto init_hca_err;\r
- }\r
-\r
- /* Now, query HCA to get actual allocated parameters */\r
- cmd_ret = THH_cmd_QUERY_HCA(thh_hob_p->cmd, &(thh_hob_p->hca_props));\r
- if (cmd_ret != THH_CMD_STAT_OK) {\r
- MTL_ERROR1("THH_hob_open_hca: CMD_error in THH_cmd_QUERY_HCA (%d)\n", cmd_ret);\r
- ret = HH_EAGAIN;\r
- goto query_hca_err;\r
- }\r
- \r
- /* create uldm */\r
- ret = THH_uldm_create(thh_hob_p, thh_hob_p->hw_props.uar_base, (u_int8_t) thh_hob_p->profile.log2_max_uar,\r
- (u_int8_t) thh_hob_p->profile.log2_uar_pg_size, \r
- (u_int32_t) (thh_hob_p->profile.max_num_pds + thh_hob_p->dev_lims.num_rsvd_pds + THH_NUM_RSVD_PD),\r
- &(thh_hob_p->uldm)); if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_open_hca: could not create uldm (%d)\n", ret);\r
- goto uldm_create_err;\r
- }\r
-\r
- thh_hob_p->mrwm_props.mtt_base = GET_DDR_ADDR(thh_hob_p->ddr_alloc_base_addrs_vec.mtt_base_addr,thh_hob_p->ddr_props.dh,\r
- thh_hob_p->ddr_props.ddr_start_adr);\r
- thh_hob_p->mrwm_props.mpt_base = GET_DDR_ADDR(thh_hob_p->ddr_alloc_base_addrs_vec.mpt_base_addr,thh_hob_p->ddr_props.dh,\r
- thh_hob_p->ddr_props.ddr_start_adr);\r
- thh_hob_p->mrwm_props.log2_mpt_sz = (u_int8_t)thh_hob_p->profile.log2_max_mpt_entries;\r
- thh_hob_p->mrwm_props.log2_mtt_sz = (u_int8_t)thh_hob_p->profile.log2_max_mtt_entries;\r
- thh_hob_p->mrwm_props.log2_mtt_seg_sz = (u_int8_t)thh_hob_p->profile.log2_mtt_entries_per_seg;\r
- thh_hob_p->mrwm_props.max_mem_reg = thh_hob_p->profile.num_external_mem_regions;\r
- thh_hob_p->mrwm_props.max_mem_reg_internal = thh_hob_p->profile.max_num_qps + thh_hob_p->profile.max_num_cqs;\r
- thh_hob_p->mrwm_props.max_mem_win = thh_hob_p->profile.num_mem_windows;\r
- thh_hob_p->mrwm_props.log2_max_mtt_segs = (u_int8_t)(thh_hob_p->profile.log2_max_mtt_entries - \r
- thh_hob_p->mrwm_props.log2_mtt_seg_sz);\r
- thh_hob_p->mrwm_props.log2_rsvd_mpts = thh_hob_p->dev_lims.log2_rsvd_mrws;\r
- thh_hob_p->mrwm_props.log2_rsvd_mtt_segs = thh_hob_p->dev_lims.log2_rsvd_mtts;\r
-\r
- ret = THH_mrwm_create(thh_hob_p, &(thh_hob_p->mrwm_props), &(thh_hob_p->mrwm));\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_open_hca: could not create mrwm (%d)\n", ret);\r
- goto mrwm_create_err;\r
- }\r
- \r
- /* Create objects */\r
- ret = THH_cqm_create(thh_hob_p, (u_int8_t) thh_hob_p->profile.log2_max_cqs,\r
- thh_hob_p->dev_lims.log2_rsvd_cqs, &(thh_hob_p->cqm));\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_open_hca: could not create cqm (%d)\n", ret);\r
- goto cqm_create_err;\r
- }\r
- \r
- /* create qpm object here */\r
-\r
- /* initialize INIT_IB parameters here for possible use by qpm */\r
- num_ports = thh_hob_p->dev_lims.num_ports;\r
-\r
- thh_hob_p->init_ib_props = (THH_port_init_props_t *) MALLOC(num_ports * sizeof(THH_port_init_props_t));\r
- if (!(thh_hob_p->init_ib_props)) {\r
- MTL_ERROR1( "THH_hob_open_hca: ERROR : cannot allocate memory for port init props)\n");\r
- goto init_ib_props_malloc_err;\r
- }\r
- for (i = 1; i <= num_ports; i++) {\r
- /* redundant for now. However, leaving option for setting different properties per port */\r
- thh_hob_p->init_ib_props[i-1].e = TRUE;\r
- thh_hob_p->init_ib_props[i-1].g0 = FALSE;\r
- thh_hob_p->init_ib_props[i-1].max_gid = (1 << (thh_hob_p->dev_lims.log_max_gid));\r
- thh_hob_p->init_ib_props[i-1].mtu_cap = thh_hob_p->dev_lims.max_mtu;\r
- thh_hob_p->init_ib_props[i-1].max_pkey = (1 << (thh_hob_p->dev_lims.log_max_pkey));\r
- thh_hob_p->init_ib_props[i-1].vl_cap = thh_hob_p->dev_lims.max_vl;\r
- thh_hob_p->init_ib_props[i-1].port_width_cap = thh_hob_p->dev_lims.max_port_width;\r
- }\r
- \r
- memset(&(thh_qpm_init_params), 0, sizeof(thh_qpm_init_params));\r
- thh_qpm_init_params.rdb_base_index = \r
- /* 32 low-order bits, right-shifted by log of size of rdb entry */\r
- (u_int32_t)(((u_int64_t)(GET_DDR_ADDR(thh_hob_p->ddr_alloc_base_addrs_vec.rdb_base_addr,thh_hob_p->ddr_props.dh,\r
- thh_hob_p->ddr_props.ddr_start_adr))) & (u_int64_t)0xFFFFFFFF ) \r
- >> THH_DDR_LOG2_RDB_ENTRY_SIZE;\r
- thh_qpm_init_params.log2_max_qp = (u_int8_t) thh_hob_p->profile.log2_max_qps;\r
- thh_qpm_init_params.log2_max_outs_rdma_atom = thh_hob_p->profile.log2_inflight_rdma_per_qp;\r
- thh_qpm_init_params.log2_max_outs_dst_rd_atom = thh_hob_p->dev_lims.log_max_ra_req_qp;\r
- thh_qpm_init_params.n_ports = (u_int8_t)num_ports;\r
- thh_qpm_init_params.port_props = \r
- (thh_hob_p->module_flags.legacy_sqp == TRUE ? NULL : thh_hob_p->init_ib_props );\r
- thh_qpm_init_params.log2_rsvd_qps = thh_hob_p->dev_lims.log2_rsvd_qps;\r
- \r
- ret = THH_qpm_create(thh_hob_p, &(thh_qpm_init_params), &(thh_hob_p->qpm));\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_open_hca: could not create qpm %s(%d)\n", HH_strerror_sym(ret), ret);\r
- goto qpm_create_err;\r
- }\r
-\r
- if (thh_hob_p->dev_lims.srq) {\r
- ret= THH_srqm_create(thh_hob_p, \r
- (u_int8_t)thh_hob_p->profile.log2_max_srqs, thh_hob_p->dev_lims.log2_rsvd_srqs,\r
- &(thh_hob_p->srqm));\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_open_hca: could not create srqm - %s(%d)\n", HH_strerror_sym(ret), ret);\r
- goto srqm_create_err;\r
- }\r
- } else {\r
- thh_hob_p->srqm= (THH_srqm_t)THH_INVALID_HNDL; /* SRQs are not supported */\r
- }\r
-\r
- /* CREATE ALL CONTAINED OBJECTS */\r
- \r
- /* create UDAVm if privileged UDAV is set */\r
- if (thh_hob_p->profile.use_priv_udav) {\r
- \r
- thh_hob_p->udavm_use_priv = TRUE;\r
- \r
- /* create the table in DDR memory */\r
- udav_entry_size = (unsigned)(sizeof(struct tavorprm_ud_address_vector_st) / 8);\r
- udav_table_size = thh_hob_p->profile.max_priv_udavs * udav_entry_size;\r
-\r
- ret = THH_ddrmm_alloc(thh_hob_p->ddrmm, udav_table_size, ceil_log2(udav_entry_size),\r
- &udav_phys_addr);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_open_hca: could not allocate protected udavm area in DDR(err = %d)\n", ret);\r
- goto udavm_ddrmm_alloc_err;\r
- }\r
- udav_virt_addr = (MT_virt_addr_t) MOSAL_map_phys_addr( udav_phys_addr , udav_table_size,\r
- MOSAL_MEM_FLAGS_NO_CACHE | MOSAL_MEM_FLAGS_PERM_WRITE | MOSAL_MEM_FLAGS_PERM_READ , \r
- MOSAL_get_kernel_prot_ctx());\r
- if (udav_virt_addr == (MT_virt_addr_t) NULL) {\r
- MTL_ERROR1("THH_hob_open_hca: could not map physical address " PHYS_ADDR_FMT " to virtual\n", \r
- udav_phys_addr);\r
- goto udavm_mosal_map_err;\r
- }\r
-\r
- memset(&udav_internal_mr, 0, sizeof(udav_internal_mr));\r
- udav_internal_mr.force_memkey = TRUE;\r
- udav_internal_mr.memkey = THH_UDAVM_PRIV_RESERVED_LKEY;\r
- udav_internal_mr.pd = THH_RESERVED_PD;\r
- udav_internal_mr.size = udav_table_size;\r
- udav_internal_mr.start = udav_virt_addr;\r
- udav_internal_mr.vm_ctx = MOSAL_get_kernel_prot_ctx();\r
- if (udav_phys_addr) {\r
- VAPI_phy_addr_t udav_phy = udav_phys_addr;\r
- udav_internal_mr.num_bufs = 1; /* != 0 iff physical buffesrs supplied */\r
- udav_internal_mr.phys_buf_lst = &udav_phy; /* size = num_bufs */\r
- udav_vapi_size = (VAPI_size_t) udav_table_size;\r
- udav_internal_mr.buf_sz_lst = &udav_vapi_size; /* [num_bufs], corresponds to phys_buf_lst */\r
- }\r
-\r
- thh_hob_p->udavm_table_size = udav_table_size;\r
- thh_hob_p->udavm_table = udav_virt_addr;\r
- thh_hob_p->udavm_table_ddr = udav_phys_addr;\r
-\r
- ret = THH_mrwm_register_internal(thh_hob_p->mrwm, &udav_internal_mr, &dummy_key);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_open_hca: could not register created udavm table (%d)\n", ret);\r
- goto udavm_table_register_err;\r
- }\r
- thh_hob_p->udavm_lkey = dummy_key;\r
-\r
- ret = THH_udavm_create(&(thh_hob_p->version_info), \r
- dummy_key,\r
- udav_virt_addr,\r
- udav_table_size,\r
- TRUE,\r
- &(thh_hob_p->udavm),\r
- &(thh_hob_p->av_ddr_base),\r
- &(thh_hob_p->av_host_base));\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_open_hca: could not create udavm (%d)\n", ret);\r
- goto udavm_create_err;\r
- }\r
-\r
- } else {\r
- thh_hob_p->udavm_use_priv = FALSE;\r
- }\r
-\r
- /* CREATE KAR (kernel UAR), using UAR 1 for this purpose. */\r
- kar_addr = (MT_virt_addr_t) MOSAL_map_phys_addr( thh_hob_p->hw_props.uar_base + ((MT_phys_addr_t)1 << thh_hob_p->profile.log2_uar_pg_size),\r
- ((MT_size_t)1 << thh_hob_p->profile.log2_uar_pg_size),\r
- MOSAL_MEM_FLAGS_NO_CACHE | MOSAL_MEM_FLAGS_PERM_WRITE, \r
- MOSAL_get_kernel_prot_ctx());\r
- if (kar_addr == (MT_virt_addr_t) NULL) {\r
-#ifndef __DARWIN__\r
- MTL_ERROR1("THH_hob_open_hca: MOSAL_map_phys_addr failed for prot ctx %d, addr " PHYS_ADDR_FMT ", size %d\n",\r
- MOSAL_get_kernel_prot_ctx(),\r
- (MT_phys_addr_t) (thh_hob_p->hw_props.uar_base),\r
- (1 << thh_hob_p->profile.log2_uar_pg_size));\r
-#else\r
- MTL_ERROR1("THH_hob_open_hca: MOSAL_map_phys_addr failed: addr " PHYS_ADDR_FMT ", size %d\n",\r
- (MT_phys_addr_t) (thh_hob_p->hw_props.uar_base),\r
- (1 << thh_hob_p->profile.log2_uar_pg_size));\r
-#endif\r
- goto kar_map_phys_addr_err;\r
- }\r
- thh_hob_p->kar_addr = kar_addr;\r
- MTL_DEBUG4("%s: MOSAL_map_phys_addr FOR KAR = " VIRT_ADDR_FMT "\n", __func__, kar_addr);\r
- ret = THH_uar_create(&(thh_hob_p->version_info), 1/* Kernel UAR page index */, \r
- (void *) kar_addr, &(thh_hob_p->kar));\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_open_hca: could not create KAR (%d)\n", ret);\r
- thh_hob_p->kar_addr = (MT_virt_addr_t) 0;\r
- goto kar_create_err;\r
- }\r
- \r
- //sharon: wrote fixed numbers till fw bug fixed\r
- if (THH_DEV_LIM_MCG_ENABLED(thh_hob_p)) {\r
- ret = THH_mcgm_create(thh_hob_p, \r
- ((VAPI_size_t)1 << thh_hob_p->hca_props.multicast_parameters.log_mc_table_sz),\r
- /*thh_hob_p->hca_props.multicast_parameters.mc_table_hash_sz*/\r
- (VAPI_size_t)1 << (thh_hob_p->profile.log2_mcg_hash_size),\r
- (u_int16_t)thh_hob_p->profile.qps_per_mcg, \r
- &(thh_hob_p->mcgm) );\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_open_hca: could not create mcgm (%d)\n", ret);\r
- thh_hob_p->hca_capabilities.max_mcast_grp_num = 0; \r
- thh_hob_p->hca_capabilities.max_mcast_qp_attach_num = 0; \r
- thh_hob_p->hca_capabilities.max_total_mcast_qp_attach_num = 0;\r
- thh_hob_p->mcgm = (THH_mcgm_t)THH_INVALID_HNDL;\r
- }\r
- }\r
-\r
- /* CREATE EVENTP*/\r
- event_res.cr_base = thh_hob_p->hw_props.cr_base;\r
- event_res.intr_clr_bit = thh_hob_p->adapter_props.intapin;\r
- event_res.irq = thh_hob_p->hw_props.interrupt_props.irq;\r
- event_res.is_srq_enable = thh_hob_p->dev_lims.srq;\r
-\r
- ret = THH_eventp_create (thh_hob_p, &event_res, thh_hob_p->kar, &(thh_hob_p->eventp));\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_open_hca: could not create eventp (%d)\n", ret);\r
- goto eventp_create_err;\r
- }\r
-\r
- /* CREATE THE VARIOUS EVENT QUEUES (eventp object operations) */\r
- /* register dummy completion and async event handlers */\r
- /* set max outstanding EQEs to max number of CQs configured */\r
-\r
- ret = THH_eventp_setup_ib_eq(thh_hob_p->eventp, \r
- &THH_dummy_async_event,\r
- NULL, \r
- (MT_size_t)(thh_hob_p->module_flags.async_eq_size == 0 ? \r
- THH_MAX_ASYNC_EQ_SIZE :\r
- thh_hob_p->module_flags.async_eq_size ), \r
- &(thh_hob_p->ib_eq));\r
- if (ret != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("THH_hob_open_hca: ERROR : cannot set up async event queue for size "SIZE_T_DFMT" (ret=%d)"), \r
- (MT_size_t)(thh_hob_p->module_flags.async_eq_size == 0 ? \r
- THH_MAX_ASYNC_EQ_SIZE :thh_hob_p->module_flags.async_eq_size ),ret);\r
- goto eventp_async_err;\r
- }\r
-\r
- ret = THH_eventp_setup_comp_eq(thh_hob_p->eventp, \r
- &THH_dummy_comp_event , \r
- NULL,\r
- (MT_size_t)(1 <<(thh_hob_p->profile.log2_max_cqs)) - \r
- (MT_size_t)(1ul << (thh_hob_p->dev_lims.log2_rsvd_cqs)), \r
- &(thh_hob_p->compl_eq));\r
- if (ret != HH_OK) {\r
- MTL_ERROR1( "THH_hob_open_hca: ERROR : cannot set up completion event queue (%d)\n", ret);\r
- goto eventp_compl_err;\r
- }\r
-\r
-\r
- /* PERFORM INIT_IB only for legacy SQPs. Use max values obtained from QUERY_DEV_LIMS */\r
-\r
- last_port_initialized = 0;\r
- \r
- if (thh_hob_p->module_flags.legacy_sqp == TRUE) { \r
- for (i = 1; i <= num_ports; i++) {\r
- MTL_TRACE2("THH_hob_open_hca: INIT_IB COMMAND\n");\r
- cmd_ret = THH_cmd_INIT_IB(thh_hob_p->cmd, (IB_port_t) i, &(thh_hob_p->init_ib_props[i-1]));\r
- if (cmd_ret != THH_CMD_STAT_OK) {\r
- MTL_ERROR1("THH_hob_open_hca: CMD_error in THH_cmd_INIT_IB (%d) for port %d\n", cmd_ret, i);\r
- if (cmd_ret ==THH_CMD_STAT_EFATAL) {\r
- ret = HH_EFATAL;\r
- } else {\r
- ret = HH_EAGAIN;\r
- }\r
- goto init_ib_err;\r
- }\r
-\r
- else {\r
- MTL_TRACE2("THH_hob_open_hca: INIT_IB COMMAND completed successfuly\n");\r
- }\r
- last_port_initialized++;\r
- }\r
- }\r
-\r
-\r
- /* This must be called after INIT_IB, since it uses the max_pkey value stored in that struct */\r
- MTL_TRACE2("THH_hob_open_hca: Before THH_hob_query_struct_init\n");\r
- ret = THH_hob_query_struct_init(thh_hob_p, \r
- ((prop_props_p == NULL)? FALSE : TRUE),\r
- &(thh_hob_p->hca_capabilities));\r
- if (ret != HH_OK) {\r
- MTL_ERROR1( "THH_hob_query_struct_init: ERROR : cannot initialize data for query_hca (%d)\n", ret);\r
- goto query_struct_init_err;\r
- }\r
-\r
- /* TK - start events after all CMDs are done */\r
-\r
-#if (! defined __DARWIN__) || (defined DARWIN_WITH_INTERRUPTS_CMDIF)\r
- ret = THH_eventp_setup_cmd_eq(thh_hob_p->eventp, CMD_EQ_SIZE /* to overcome a FW bug */\r
- /*(1 << (thh_hob_p->fw_props.log_max_outstanding_cmd))*/ );\r
- if (ret != HH_OK) {\r
- MTL_ERROR1( "THH_hob_open_hca: ERROR : cannot set up command event queue (%d)\n", ret);\r
- goto eventp_cmd_err;\r
- }\r
-#endif \r
-\r
- /* move the HCA to running state if had no fatal. If had fatal, return HH_EFATAL */\r
- MOSAL_spinlock_dpc_lock(&thh_hob_p->fatal_spl);\r
- if ((thh_hob_p->thh_state & THH_STATE_HAVE_ANY_FATAL) != 0) {\r
- /* already in FATAL state */\r
- MTL_DEBUG4(MT_FLFMT("%s: already in FATAL state"), __func__); \r
- MOSAL_spinlock_unlock(&thh_hob_p->fatal_spl);\r
- ret = HH_EFATAL;\r
- goto fatal_err_at_end;\r
- }\r
- thh_hob_p->thh_state = THH_STATE_RUNNING;\r
- MOSAL_spinlock_unlock(&thh_hob_p->fatal_spl);\r
- \r
- MTL_TRACE2("THH_hob_open_hca: device name %s\n", hca_hndl->dev_desc);\r
- hca_hndl->status = HH_HCA_STATUS_OPENED;\r
- \r
- /* free the mutex */\r
- MOSAL_mutex_rel(&(thh_hob_p->mtx));\r
-\r
- return(HH_OK);\r
-\r
-fatal_err_at_end:\r
-eventp_cmd_err:\r
-query_struct_init_err:\r
-init_ib_err:\r
- /* see if need to close IB for some ports. Do not close ports on fatal error*/\r
- MOSAL_spinlock_dpc_lock(&thh_hob_p->fatal_spl);\r
- /*test fatal again, here -- may have gotten FATAL before end of OPEN_hca process */\r
- if ((thh_hob_p->thh_state & THH_STATE_HAVE_ANY_FATAL) != 0) {\r
- /* got FATAL during OPEN_HCA */\r
- MTL_DEBUG4(MT_FLFMT("THH_hob_open_hca: In FATAL state")); \r
- have_fatal = TRUE;\r
- } else {\r
- have_fatal = FALSE;\r
- }\r
- MOSAL_spinlock_unlock(&thh_hob_p->fatal_spl);\r
- if ((last_port_initialized) && (have_fatal == FALSE)) {\r
- for (i = 1; i <= last_port_initialized; i++) {\r
- MTL_DEBUG4(MT_FLFMT("THH_hob_open_hca: closing IB port %d"), i); \r
- THH_cmd_CLOSE_IB(thh_hob_p->cmd, (IB_port_t) i);\r
- }\r
- }\r
- thh_hob_p->compl_eq = THH_INVALID_EQN;\r
-\r
-eventp_compl_err:\r
- thh_hob_p->ib_eq = THH_INVALID_EQN;\r
-\r
-eventp_async_err:\r
- THH_eventp_destroy(thh_hob_p->eventp);\r
-\r
-eventp_create_err:\r
- if (thh_hob_p->mcgm != (THH_mcgm_t)THH_INVALID_HNDL) {\r
- THH_mcgm_destroy(thh_hob_p->mcgm );\r
- thh_hob_p->mcgm = (THH_mcgm_t)THH_INVALID_HNDL;\r
- }\r
-\r
- THH_uar_destroy(thh_hob_p->kar);\r
- thh_hob_p->kar = (THH_uar_t)THH_INVALID_HNDL;\r
-\r
-kar_create_err:\r
- MOSAL_unmap_phys_addr(MOSAL_get_kernel_prot_ctx(), (MT_virt_addr_t) kar_addr, \r
- ((MT_size_t)1 << thh_hob_p->profile.log2_uar_pg_size));\r
- thh_hob_p->kar_addr = (MT_virt_addr_t) 0;\r
-\r
-kar_map_phys_addr_err:\r
- if (thh_hob_p->profile.use_priv_udav) {\r
- THH_udavm_destroy(thh_hob_p->udavm);\r
- }\r
- thh_hob_p->udavm = (THH_udavm_t)THH_INVALID_HNDL;\r
-udavm_create_err:\r
- if (thh_hob_p->profile.use_priv_udav) {\r
- THH_mrwm_deregister_mr(thh_hob_p->mrwm, dummy_key);\r
- thh_hob_p->udavm_lkey = 0;\r
- }\r
-udavm_table_register_err:\r
- if (thh_hob_p->profile.use_priv_udav) {\r
- MOSAL_unmap_phys_addr( MOSAL_get_kernel_prot_ctx(), (MT_virt_addr_t) udav_virt_addr , udav_table_size );\r
- thh_hob_p->udavm_table = (MT_virt_addr_t) NULL;\r
- }\r
-\r
-udavm_mosal_map_err:\r
- if (thh_hob_p->profile.use_priv_udav) {\r
- THH_ddrmm_free(thh_hob_p->ddrmm, udav_phys_addr, udav_table_size);\r
- thh_hob_p->udavm_table_ddr = (MT_phys_addr_t) 0;\r
- thh_hob_p->udavm_table_size = 0;\r
- }\r
-\r
-udavm_ddrmm_alloc_err:\r
- THH_srqm_destroy(thh_hob_p->srqm);\r
- thh_hob_p->srqm = (THH_srqm_t)THH_INVALID_HNDL;\r
-\r
-srqm_create_err:\r
- THH_qpm_destroy( thh_hob_p->qpm, TRUE);\r
- thh_hob_p->qpm = (THH_qpm_t)THH_INVALID_HNDL;\r
-\r
-qpm_create_err:\r
- FREE(thh_hob_p->init_ib_props);\r
- thh_hob_p->init_ib_props = ( THH_port_init_props_t *) NULL;\r
-\r
-init_ib_props_malloc_err:\r
- THH_cqm_destroy( thh_hob_p->cqm, TRUE);\r
- thh_hob_p->cqm = (THH_cqm_t)THH_INVALID_HNDL;\r
-\r
-cqm_create_err:\r
- THH_mrwm_destroy(thh_hob_p->mrwm, TRUE);\r
- thh_hob_p->mrwm = (THH_mrwm_t)THH_INVALID_HNDL;\r
-\r
-mrwm_create_err:\r
- THH_uldm_destroy(thh_hob_p->uldm );\r
- thh_hob_p->uldm = (THH_uldm_t)THH_INVALID_HNDL;\r
-uldm_create_err:\r
-query_hca_err:\r
-#ifdef SIMULATE_HALT_HCA\r
- THH_cmd_CLOSE_HCA(thh_hob_p->cmd);\r
-#else\r
- MOSAL_spinlock_dpc_lock(&thh_hob_p->fatal_spl);\r
- /*test fatal again, here -- may have gotten FATAL before end of OPEN_hca process */\r
- if ((thh_hob_p->thh_state & THH_STATE_HAVE_ANY_FATAL) != 0) {\r
- /* got FATAL during OPEN_HCA */\r
- MTL_DEBUG4(MT_FLFMT("THH_hob_open_hca: In FATAL state")); \r
- have_fatal = TRUE;\r
- } else {\r
- have_fatal = FALSE;\r
- }\r
- MOSAL_spinlock_unlock(&thh_hob_p->fatal_spl);\r
- if (have_fatal) {\r
- if (thh_hob_p->module_flags.fatal_delay_halt == 0) {\r
- MTL_DEBUG1(MT_FLFMT("%s: halting the HCA"), __func__);\r
- THH_cmd_CLOSE_HCA(thh_hob_p->cmd, TRUE);\r
- }\r
- } else {\r
- MTL_DEBUG1(MT_FLFMT("%s: closing the HCA on non-fatal error %d"), __func__, ret);\r
- THH_cmd_CLOSE_HCA(thh_hob_p->cmd, FALSE);\r
- }\r
-#endif\r
-\r
-init_hca_err:\r
- THH_cmd_revoke_ddrmm(thh_hob_p->cmd);\r
-\r
-cmd_assign_ddrmm_err:\r
-\r
- ddr_alloc_area = (MT_phys_addr_t *) &(thh_hob_p->ddr_alloc_base_addrs_vec);\r
- ddr_alloc_size = (MT_size_t *)&(thh_hob_p->ddr_alloc_size_vec);\r
- for (i = 0; i < thh_hob_p->profile.ddr_alloc_vec_size; i++, ddr_alloc_area++, ddr_alloc_size++) {\r
- if (*ddr_alloc_area != THH_DDRMM_INVALID_PHYS_ADDR) \r
- /* Do not free in case skipped during allocation (e.g., SRQC) */\r
- THH_ddrmm_free(thh_hob_p->ddrmm,*ddr_alloc_area, ((MT_size_t)1 << (*ddr_alloc_size)));\r
- }\r
-\r
-post_mutex_acquire_err:\r
- MOSAL_mutex_rel(&(thh_hob_p->mtx));\r
- \r
-post_state_change_error:\r
- MOSAL_spinlock_dpc_lock(&thh_hob_p->fatal_spl);\r
- /*test fatal again, here -- may have gotten FATAL before end of OPEN_hca process */\r
- if ((thh_hob_p->thh_state & THH_STATE_HAVE_ANY_FATAL) != 0) {\r
- /* got FATAL during OPEN_HCA */\r
- MTL_DEBUG4(MT_FLFMT("THH_hob_open_hca: In FATAL state")); \r
- have_fatal = TRUE;\r
- } else {\r
- /* restore the state to closed */\r
- have_fatal = FALSE;\r
- thh_hob_p->thh_state = THH_STATE_CLOSED;\r
- }\r
- MOSAL_spinlock_unlock(&thh_hob_p->fatal_spl);\r
- if (have_fatal) {\r
- THH_hob_restart(hca_hndl);\r
- }\r
- return ret;\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_query\r
- *\r
- * Description: Implements VAPI_query_hca verb. Data is already stored in HOB object.\r
- *\r
- * input:\r
- * hca_hndl\r
- * output: \r
- * hca_cap_p -- pointer to output structure\r
- * returns:\r
- * HH_OK\r
- * HH_EINVAL_HCA_HNDL\r
- *\r
- *****************************************************************************/\r
- HH_ret_t THH_hob_query(HH_hca_hndl_t hca_hndl, \r
- VAPI_hca_cap_t *hca_cap_p)\r
-{\r
- THH_hob_t hob;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_query : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- \r
- hob = THHOBP(hca_hndl);\r
-\r
- if (hob == NULL) {\r
- MTL_ERROR1("THH_hob_query : ERROR : No device registered\n");\r
- return HH_EINVAL;\r
- }\r
- \r
- TEST_RETURN_FATAL(hob);\r
-\r
- /* check if ib_init_props have been created -- indicates that open_hca called for this device */\r
- if (hob->init_ib_props == (THH_port_init_props_t *)NULL) {\r
- MTL_ERROR1("THH_hob_query: ERROR : HCA device has not yet been opened\n");\r
- return HH_EINVAL;\r
- }\r
-\r
- memcpy(hca_cap_p, &(hob->hca_capabilities), sizeof(VAPI_hca_cap_t));\r
- return HH_OK;\r
-}\r
-\r
-#define SET_MAX_SG(a) (((a) < (u_int32_t)hob->dev_lims.max_sg) ? (a) : hob->dev_lims.max_sg)\r
-/******************************************************************************\r
- * Function: THH_hob_query_struct_init\r
- *\r
- * Description: Pre-computes the data for VAPI_query_hca. Called during THH_hob_open_hca()\r
- *\r
- * input:\r
- * hob\r
- * output: \r
- * hca_cap_p -- pointer to output structure\r
- * returns:\r
- * HH_OK\r
- * HH_EINVAL_HCA_HNDL\r
- *\r
- * Comments: Needs to use a MAD query for some of the parameters\r
- *\r
- *****************************************************************************/\r
-static HH_ret_t THH_hob_query_struct_init(THH_hob_t hob,\r
- MT_bool have_usr_profile, \r
- VAPI_hca_cap_t *hca_cap_p)\r
-{\r
- HH_ret_t ret;\r
- u_int32_t flags = 0;\r
- u_int32_t log2_num_spare_segs = 0;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- MTL_DEBUG4("Entering THH_hob_query_struct_init\n");\r
- /* Maximum Number of QPs supported. */\r
-#if 0\r
- hca_cap_p->max_num_qp = hob->profile.max_num_qps - THH_NUM_RSVD_QP -\r
- ((have_usr_profile == FALSE)? 0 : (1U<<hob->dev_lims.log2_rsvd_qps) );\r
-#else\r
- hca_cap_p->max_num_qp = (u_int32_t)hob->profile.max_num_qps;\r
-#endif\r
- hca_cap_p->max_num_srq = (u_int32_t)hob->profile.max_num_srqs;\r
- hca_cap_p->srq_resize_supported= TRUE;\r
- /* Maximum Number of oustanding WR on any WQ. */\r
- hca_cap_p->max_qp_ous_wr = (1 << (hob->dev_lims.log_max_qp_sz)) - 1; \r
- hca_cap_p->max_wqe_per_srq = (1 << (hob->dev_lims.log_max_srq_sz)) - 1; \r
- \r
- /* Various flags (VAPI_hca_cap_flags_t) */\r
-\r
-// VAPI_RESIZE_OUS_WQE_CAP = 1 /* Not currently supported */\r
-\r
- flags = (hob->hca_props.udp ? VAPI_UD_AV_PORT_ENFORCE_CAP : 0) |\r
- (hob->dev_lims.apm ? VAPI_AUTO_PATH_MIG_CAP : 0 ) |\r
- (hob->dev_lims.rm ? VAPI_RAW_MULTI_CAP : 0) |\r
- (hob->dev_lims.pkv ? VAPI_BAD_PKEY_COUNT_CAP : 0) |\r
- (hob->dev_lims.qkv ? VAPI_BAD_QKEY_COUNT_CAP : 0) |\r
- VAPI_CHANGE_PHY_PORT_CAP | VAPI_RC_RNR_NAK_GEN_CAP | VAPI_PORT_ACTIVE_EV_CAP;\r
- \r
-\r
- hca_cap_p->flags = flags; \r
- /* Max num of scatter/gather entries for desc other than RD */\r
- hca_cap_p->max_num_sg_ent = SET_MAX_SG(28); \r
- /* Max num of scatter entries for SRQs */\r
- hca_cap_p->max_srq_sentries = SET_MAX_SG(31); \r
- /* Max num of scatter/gather entries for RD desc - not supported */\r
- hca_cap_p->max_num_sg_ent_rd = 0 ; \r
- /* Max num of supported CQs */\r
-#if 0\r
- hca_cap_p->max_num_cq = hob->profile.max_num_cqs -\r
- ((have_usr_profile == FALSE)? 0 : (1U<<hob->dev_lims.log2_rsvd_cqs) );\r
-#else\r
- hca_cap_p->max_num_cq = (u_int32_t)hob->profile.max_num_cqs;\r
-#endif \r
- /* Max num of supported entries per CQ */\r
- hca_cap_p->max_num_ent_cq = (1 << (hob->dev_lims.log_max_cq_sz)) - 1 /*for extra cqe needed */; \r
- /* Maximum number of memory region supported. */\r
-#if 0\r
- hca_cap_p->max_num_mr = hob->profile.num_external_mem_regions - \r
- ((have_usr_profile == FALSE)? 0 : (1U<<hob->dev_lims.log2_rsvd_mtts) );\r
-#else\r
- hca_cap_p->max_num_mr = (u_int32_t)hob->profile.num_external_mem_regions; \r
-#endif \r
- /* Largest contigous block of memory region in bytes. This may be achieved by registering\r
- * PHYSICAL memory directly for the region, (and using a page size for the region equal to\r
- * the size of the physical memory block you are registering). The PRM allocates 5 bytes\r
- * for registering the log2 of the page size (with a 4K page size having page-size val 0).\r
- * Thus, the maximum page size per MTT entry is 4k * 2^31 (= 2^(31+12). A single region \r
- * can include multiple entries, and we can use all the spare MTT entries available for\r
- * this HUGE region. The driver requires that every memory region have at least a single\r
- * segment available for registration. We can thus use all the spare segments (we have\r
- * allocated 2 segments per region, but only really need one) to this region. If there are\r
- * no spare MTT entries, we calculate the value based on the usual mtt entries per segment.\r
- * This will still be a HUGE number (probably 2^46 or greater). \r
- */\r
- if (hob->profile.log2_mtt_segs_per_region == 0)\r
- log2_num_spare_segs = (u_int32_t)hob->profile.log2_mtt_entries_per_seg;\r
- else \r
- log2_num_spare_segs = (u_int32_t)(hob->profile.log2_max_mtt_entries - hob->profile.log2_mtt_segs_per_region);\r
-\r
- /* check that do not overflow 2^64 !! */\r
- if (log2_num_spare_segs >= 21) \r
- hca_cap_p->max_mr_size = MAKE_ULONGLONG(0xFFFFFFFFFFFFFFFF);\r
- else\r
- hca_cap_p->max_mr_size = (((u_int64_t)1L) << (31 + 12 + log2_num_spare_segs)) ; \r
- /* Maximum number of protection domains supported. */\r
-#if 0\r
- hca_cap_p->max_pd_num = hob->profile.max_num_pds - THH_NUM_RSVD_PD - \r
- ((have_usr_profile == FALSE)? 0 : hob->dev_lims.num_rsvd_pds );\r
-#else\r
- hca_cap_p->max_pd_num = (u_int32_t)hob->profile.max_num_pds;\r
-#endif\r
- /* Largest page size supported by this HCA */\r
- hca_cap_p->page_size_cap = (1 << (hob->dev_lims.log_pg_sz)); \r
- /* Number of physical ports of the HCA. */\r
- hca_cap_p->phys_port_num = hob->dev_lims.num_ports; \r
- /* Maximum number of partitions supported . */\r
- hca_cap_p->max_pkeys = hob->init_ib_props[0].max_pkey; \r
- /* Maximum number of oust. RDMA read/atomic as target */\r
- hca_cap_p->max_qp_ous_rd_atom = 1 << (hob->profile.log2_inflight_rdma_per_qp); \r
- /* EE Maximum number of outs. RDMA read/atomic as target -- NOT YET SUPPORTED */\r
- hca_cap_p->max_ee_ous_rd_atom = 0; \r
- /* Max. Num. of resources used for RDMA read/atomic as target */\r
- hca_cap_p->max_res_rd_atom = ((1 << (hob->ddr_alloc_size_vec.log2_rdb_size - THH_DDR_LOG2_RDB_ENTRY_SIZE)) > 255 ? \r
- 255 :(1 << (hob->ddr_alloc_size_vec.log2_rdb_size - THH_DDR_LOG2_RDB_ENTRY_SIZE))) ; \r
- /* Max. Num. of outs. RDMA read/atomic as initiator. Note that 255 is the max in the struct */\r
- hca_cap_p->max_qp_init_rd_atom = ((1 << (hob->dev_lims.log_max_ra_req_qp)) > 255 ? \r
- 255 : (1 << (hob->dev_lims.log_max_ra_req_qp))); \r
- /* EE Max. Num. of outs. RDMA read/atomic as initiator -- NOT YET SUPPORTED */\r
- hca_cap_p->max_ee_init_rd_atom = 0;\r
- /* Level of Atomicity supported: if supported, is only within this HCA*/\r
- hca_cap_p->atomic_cap = (hob->dev_lims.atm ? VAPI_ATOMIC_CAP_HCA : VAPI_ATOMIC_CAP_NONE); \r
- /* Maximum number of EEC supported. -- NOT YET SUPPORTED */\r
-#if 0\r
- hca_cap_p->max_ee_num = 1 << (hob->hca_props.qpc_eec_cqc_rdb_parameters.log_num_of_ee);\r
-#else\r
- hca_cap_p->max_ee_num = 0;\r
-#endif\r
- /* Maximum number of IB_RDD supported -- NOT YET SUPPORTED */\r
- hca_cap_p-> max_rdd_num = 0; \r
- /* Maximum Number of memory windows supported */\r
-#if 0\r
- hca_cap_p->max_mw_num = hob->profile.num_mem_windows - \r
- ((have_usr_profile == FALSE)? 0 : (1U<<hob->dev_lims.log2_rsvd_mrws) );\r
-#else\r
- hca_cap_p->max_mw_num = (u_int32_t)hob->profile.num_mem_windows; \r
-#endif\r
- /* Maximum number of Raw IPV6 QPs supported -- NOT YET SUPPORTED */ \r
- hca_cap_p->max_raw_ipv6_qp = 0; \r
- /* Maximum number of Raw Ethertypes QPs supported -- NOT YET SUPPORTED */\r
- hca_cap_p->max_raw_ethy_qp = 0; \r
- /* Maximum Number of multicast groups */\r
- hca_cap_p->max_mcast_grp_num = 1 << (hob->hca_props.multicast_parameters.log_mc_table_sz); \r
- /* Maximum number of QP per multicast group */\r
- hca_cap_p->max_mcast_qp_attach_num = ( (1U<<(hob->hca_props.multicast_parameters.log_mc_table_entry_sz)) \r
- - THH_DDR_MCG_ENTRY_HEADER_SIZE) / \r
- THH_DDR_MCG_BYTES_PER_QP;\r
- /* Maximum number of QPs which can be attached to a mcast grp */\r
- hca_cap_p->max_total_mcast_qp_attach_num = hca_cap_p->max_mcast_grp_num * hca_cap_p->max_mcast_qp_attach_num;\r
- /* Maximum number of address handles */\r
- hca_cap_p->max_ah_num = (u_int32_t)(hob->profile.use_priv_udav ? hob->profile.max_priv_udavs : \r
- THHUL_PDM_MAX_UL_UDAV_PER_PD*(hob->profile.max_num_pds+THH_NUM_RSVD_PD));\r
- /* max number of fmrs for the use is the number of user entries in MPT */\r
-#if 0\r
- hca_cap_p->max_num_fmr = hob->profile.num_external_mem_regions - \r
- ((have_usr_profile == FALSE)? 0 : (1U<<hob->dev_lims.log2_rsvd_mtts) );\r
-#else\r
- hca_cap_p->max_num_fmr = (u_int32_t)((hob->ddr_props.dh == FALSE) ? hob->profile.num_external_mem_regions : 0);\r
-#endif\r
-/* max maps per fmr is the max number that can be expressed by the MS bits of a u_int32_t\r
- that are unused for MPT addressing (which will occupy the LS bits of that u_int32_t).*/\r
- hca_cap_p->max_num_map_per_fmr = (1 << (32 - hob->profile.log2_max_mpt_entries)) - 1;\r
- \r
- /* Log2 4.096usec Max. RX to ACK or NAK delay */\r
- hca_cap_p->local_ca_ack_delay = hob->dev_lims.local_ca_ack_delay;\r
-\r
- /* Node GUID for this hca */\r
- ret = THH_hob_get_node_guid(hob,&(hca_cap_p->node_guid)); \r
-\r
- return(ret);\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_modify\r
- *\r
- * Description: Implements the VAPI_modify_hca verb\r
- *\r
- * input:\r
- * hca_hndl\r
- * port_num - 1 or 2\r
- * hca_attr_p - contains values to modify\r
- * hca_attr_mask_p - mask specifying which values in hca_attr_p should\r
- * be used for modification.\r
- * output: \r
- * none\r
- * returns:\r
- * HH_OK\r
- * HH_EINVAL\r
- * HH_EINVAL_HCA_HNDL\r
- * HH_EINVAL_PORT\r
- * HH_ENOSYS\r
- *\r
- * Comments: Implements IB Spec 1.0a now. must be modified to support IB Spec 1.1\r
- * JPM\r
- *\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_modify(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- VAPI_hca_attr_t *hca_attr_p,\r
- VAPI_hca_attr_mask_t *hca_attr_mask_p)\r
-{\r
- /* TBD, will use SET_IB command. Problem is that can only set PKey and QKey counters to zero. */\r
- HH_ret_t retn;\r
- THH_cmd_status_t cmd_ret;\r
- VAPI_hca_port_t port_props;\r
- THH_set_ib_props_t set_ib_props;\r
- IB_port_cap_mask_t capabilities; \r
- THH_hob_t hob;\r
- \r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_modify: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_modify : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
-\r
- hob = THHOBP(hca_hndl);\r
-\r
- if (hob == NULL) {\r
- MTL_ERROR1("THH_hob_modify : ERROR : No device registered\n");\r
- return HH_EINVAL;\r
- }\r
- TEST_RETURN_FATAL(hob);\r
-\r
- if (port_num > hob->dev_lims.num_ports || port_num < 1) {\r
- MTL_ERROR2( "THH_hob_modify: ERROR : invalid port number(%d)\n", port_num);\r
- return HH_EINVAL_PORT;\r
- }\r
-\r
- memset(&set_ib_props, 0, sizeof(THH_set_ib_props_t));\r
- \r
- set_ib_props.rqk = hca_attr_p->reset_qkey_counter;\r
-\r
- /* start with current capabilities */\r
- retn = THH_hob_query_port_prop(hca_hndl, port_num, &port_props);\r
- if (retn != HH_OK) {\r
- MTL_ERROR1("THH_hob_modify : ERROR : cannot get current capabilities (%d)\n", retn);\r
- return HH_EAGAIN;\r
- }\r
- capabilities = port_props.capability_mask;\r
- \r
- /* now, modify the capability mask according to the input */\r
- if (HCA_ATTR_IS_FLAGS_SET(*hca_attr_mask_p)) {\r
- /* calculate capabilities modification mask */\r
- if(HCA_ATTR_IS_SET(*hca_attr_mask_p, HCA_ATTR_IS_SM) ) {\r
- if (hca_attr_p->is_sm) {\r
- IB_CAP_MASK_SET(capabilities, IB_CAP_MASK_IS_SM);\r
- } else {\r
- IB_CAP_MASK_CLR(capabilities, IB_CAP_MASK_IS_SM);\r
- }\r
- }\r
- if(HCA_ATTR_IS_SET(*hca_attr_mask_p, HCA_ATTR_IS_SNMP_TUN_SUP) ) {\r
- if (hca_attr_p->is_snmp_tun_sup) {\r
- IB_CAP_MASK_SET(capabilities, IB_CAP_MASK_IS_SNMP_TUNN_SUP);\r
- } else {\r
- IB_CAP_MASK_CLR(capabilities, IB_CAP_MASK_IS_SNMP_TUNN_SUP);\r
- }\r
- }\r
- if(HCA_ATTR_IS_SET(*hca_attr_mask_p, HCA_ATTR_IS_DEV_MGT_SUP) ) {\r
- if (hca_attr_p->is_dev_mgt_sup) {\r
- IB_CAP_MASK_SET(capabilities, IB_CAP_MASK_IS_DEVICE_MGMT_SUP);\r
- } else {\r
- IB_CAP_MASK_CLR(capabilities, IB_CAP_MASK_IS_DEVICE_MGMT_SUP);\r
- }\r
- }\r
- if(HCA_ATTR_IS_SET(*hca_attr_mask_p, HCA_ATTR_IS_VENDOR_CLS_SUP) ) {\r
- if (hca_attr_p->is_vendor_cls_sup) {\r
- IB_CAP_MASK_SET(capabilities, IB_CAP_MASK_IS_VENDOR_CLS_SUP);\r
- } else {\r
- IB_CAP_MASK_CLR(capabilities, IB_CAP_MASK_IS_VENDOR_CLS_SUP);\r
- }\r
- }\r
- if(HCA_ATTR_IS_SET(*hca_attr_mask_p, HCA_ATTR_IS_CLIENT_REREGISTRATION_SUP) ) {\r
- if (hca_attr_p->is_client_reregister_sup) {\r
- IB_CAP_MASK_SET(capabilities, IB_CAP_MASK_IS_CLIENT_REREGISTRATION_SUP);\r
- } else {\r
- IB_CAP_MASK_CLR(capabilities, IB_CAP_MASK_IS_CLIENT_REREGISTRATION_SUP);\r
- }\r
- } \r
- }\r
-\r
- set_ib_props.capability_mask = capabilities;\r
- \r
- /* now, perform the CMD */\r
- cmd_ret = THH_cmd_SET_IB(hob->cmd , port_num, &set_ib_props);\r
- if (cmd_ret != THH_CMD_STAT_OK) {\r
- TEST_CMD_FATAL(cmd_ret);\r
- MTL_ERROR1("THH_hob_modify: CMD_error in THH_cmd_SET_IB (%d)\n", cmd_ret);\r
- return HH_EINVAL;\r
- }\r
-\r
- return(HH_OK);\r
-}\r
-/******************************************************************************\r
- * Function: THH_hob_query_port_prop\r
- *\r
- * Description: Implements the VAPI_query_hca_port_prop verb\r
- *\r
- * input:\r
- * hca_hndl\r
- * port_num - 1 or 2\r
- * output: \r
- * hca_port_p - port properties output structure\r
- * returns:\r
- * HH_OK\r
- * HH_EINVAL\r
- * HH_EINVAL_HCA_HNDL\r
- * HH_EINVAL_PORT\r
- * HH_ERR\r
- *\r
- * Comments: Does MAD query to get the data in real time. Data is not pre-fetched, because\r
- * the current port state is needed for the answer -- so the query must be performed\r
- * anyway.\r
- *\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_query_port_prop(HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- VAPI_hca_port_t *hca_port_p ) \r
-{\r
- SM_MAD_PortInfo_t port_info;\r
- u_int8_t *mad_frame_in;\r
- u_int8_t *mad_frame_out;\r
- THH_cmd_status_t cmd_ret;\r
-\r
- THH_hob_t hob;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_query_port_prop: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_query_port_prop : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- hob = THHOBP(hca_hndl);\r
- if (hob == NULL) {\r
- MTL_ERROR1("THH_hob_query_port_prop : ERROR : No device registered\n");\r
- return HH_EINVAL;\r
- }\r
- TEST_RETURN_FATAL(hob);\r
-\r
- if (port_num > hob->dev_lims.num_ports || port_num < 1) {\r
- MTL_ERROR2( "THH_hob_query_port_prop: ERROR : invalid port number(%d)\n", port_num);\r
- return HH_EINVAL_PORT;\r
- }\r
-\r
- mad_frame_in = TNMALLOC(u_int8_t, IB_MAD_SIZE);\r
- if ( !mad_frame_in ) {\r
- return HH_EAGAIN;\r
- }\r
- mad_frame_out = TNMALLOC(u_int8_t, IB_MAD_SIZE);\r
- if ( !mad_frame_out ) {\r
- FREE(mad_frame_in);\r
- return HH_EAGAIN;\r
- }\r
- memset(mad_frame_in, 0, sizeof(mad_frame_in));\r
- memset(mad_frame_out, 0, sizeof(mad_frame_out));\r
-\r
- /* get port props using MAD commands in THH_cmd object */\r
- /* First, build the MAD header */\r
- MADHeaderBuild(IB_CLASS_SMP, \r
- 0,\r
- IB_METHOD_GET,\r
- IB_SMP_ATTRIB_PORTINFO,\r
- (u_int32_t) port_num,\r
- &(mad_frame_in[0]));\r
-\r
- /* issue the query */\r
- cmd_ret = THH_cmd_MAD_IFC(hob->cmd, 0, 0, port_num, &(mad_frame_in[0]), &(mad_frame_out[0]));\r
- if (cmd_ret != THH_CMD_STAT_OK) {\r
- TEST_CMD_FATAL(cmd_ret);\r
- MTL_ERROR2( "THH_hob_query_port_prop: ERROR : Get Port Info command failed (%d) for port %d\n", cmd_ret, port_num);\r
- FREE(mad_frame_out);\r
- FREE(mad_frame_in);\r
- if ( cmd_ret == THH_CMD_STAT_EINTR ) {\r
- return HH_EINTR;\r
- }\r
- return HH_ERR;\r
- }\r
- /* now, translate the response to a structure */\r
- PortInfoMADToSt(&port_info, &(mad_frame_out[0]));\r
-\r
- /* finally, extract the information we want */\r
- hca_port_p->bad_pkey_counter = port_info.wPKViolations;\r
- hca_port_p->capability_mask = port_info.dwCapMask;\r
- hca_port_p->gid_tbl_len = port_info.bGUIDCap;\r
- hca_port_p->lid = port_info.wLID;\r
- hca_port_p->lmc = port_info.cLMC;\r
- hca_port_p->max_msg_sz = IB_MAX_MESSAGE_SIZE;\r
- hca_port_p->max_mtu = hob->dev_lims.max_mtu;\r
- hca_port_p->max_vl_num = port_info.cVLCap;\r
- hca_port_p->pkey_tbl_len = hob->init_ib_props[port_num-1].max_pkey;\r
- hca_port_p->qkey_viol_counter = port_info.wQKViolations;\r
- hca_port_p->sm_lid = port_info.wMasterSMLID;\r
- hca_port_p->sm_sl = port_info.cMasterSMSL;\r
- hca_port_p->state = port_info.cPortState;\r
- hca_port_p->subnet_timeout = port_info.cSubnetTO;\r
-\r
- hca_port_p->initTypeReply = 0; /* not yet supported in FW */\r
- \r
- FREE(mad_frame_out);\r
- FREE(mad_frame_in);\r
- return(HH_OK);\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_get_pkey_tbl_local\r
- *\r
- * Description: Gets PKEY table for a given port \r
- *\r
- * input:\r
- * hca_hndl\r
- * port_num - 1 or 2\r
- * tbl_len_in - size of table provided for response (in pkeys)\r
- * use_mad_query_for_pkeys - if TRUE, query Tavor for pkeys\r
- * else, use pkey_table tracking in thh_qpm\r
- * output: \r
- * tbl_len_out - size of returned table (in pkeys)\r
- * pkey_tbl_p - pointer to table containing data (space provided by caller)\r
- * returns:\r
- * HH_OK\r
- * HH_EINVAL\r
- * HH_EINVAL_HCA_HNDL\r
- * HH_ERR\r
- *\r
- * Comments: Does MAD query to get the data in real time. \r
- *\r
- *****************************************************************************/\r
-static HH_ret_t THH_hob_get_pkey_tbl_local(HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- u_int16_t tbl_len_in,\r
- u_int16_t *tbl_len_out,\r
- IB_pkey_t *pkey_tbl_p,\r
- MT_bool use_mad_query_for_pkeys)\r
-{\r
- SM_MAD_Pkey_table_t pkey_table;\r
- u_int8_t *mad_frame_in;\r
- u_int8_t *mad_frame_out;\r
- int i,j;\r
- int num_pkeys, pkey_index, num_pkeytable_commands;\r
- THH_cmd_status_t cmd_ret;\r
- THH_hob_t thh_hob_p;\r
- THH_qpm_t qpm;\r
- HH_ret_t hh_ret = HH_OK;\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
-\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_get_pkey_tbl: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_get_pkey_tbl : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- /* check if have valid port number */\r
- if (port_num > thh_hob_p->dev_lims.num_ports || port_num < 1) {\r
- MTL_ERROR1("THH_hob_get_pkey_tbl: port number (%d) not valid)\n", port_num);\r
- return HH_EINVAL_PORT;\r
- }\r
- \r
- if (tbl_len_out == NULL) {\r
- return HH_EINVAL;\r
- }\r
- \r
-\r
- /* check that pkey table has enough space */\r
- num_pkeys = thh_hob_p->init_ib_props[port_num-1].max_pkey;\r
-/*** warning C4242: '=' : conversion from 'int' to 'u_int16_t', possible loss of data ***/\r
- *tbl_len_out = (u_int16_t)num_pkeys;\r
-\r
- if (tbl_len_in < num_pkeys) {\r
- if (!tbl_len_in) {\r
- MTL_TRACE2( "THH_hob_get_pkey_tbl: returning number of pkeys configured (%d)\n", num_pkeys);\r
- } else {\r
- MTL_ERROR2( "THH_hob_get_pkey_tbl: ERROR : not enough space in return value table. num keys = %d\n",\r
- num_pkeys);\r
- }\r
- return HH_EAGAIN;\r
- }\r
-\r
- /* check that have valid output buffer area */\r
- if (pkey_tbl_p == NULL) {\r
- return HH_EINVAL;\r
- }\r
-\r
-\r
- mad_frame_in = TNMALLOC(u_int8_t, IB_MAD_SIZE);\r
- if ( !mad_frame_in ) {\r
- return HH_EAGAIN;\r
- }\r
- mad_frame_out = TNMALLOC(u_int8_t, IB_MAD_SIZE);\r
- if ( !mad_frame_out ) {\r
- FREE(mad_frame_in);\r
- return HH_EAGAIN;\r
- }\r
- \r
- /* get KEY table using MAD command in THH_cmd object */\r
- /* get PKey table using MAD commands in THH_cmd object */\r
- /* First, build the MAD header */\r
- if (use_mad_query_for_pkeys == TRUE) {\r
- num_pkeytable_commands = ((num_pkeys - 1) / 32) + 1;\r
- \r
- pkey_index = 0;\r
- for (i = 0; i < num_pkeytable_commands; i++) {\r
- memset(mad_frame_in, 0, sizeof(mad_frame_in));\r
- memset(mad_frame_out, 0, sizeof(mad_frame_out));\r
- MADHeaderBuild(IB_CLASS_SMP, \r
- 0,\r
- IB_METHOD_GET,\r
- IB_SMP_ATTRIB_PARTTABLE,\r
- (u_int32_t) (32*i),\r
- &(mad_frame_in[0]));\r
- \r
- cmd_ret = THH_cmd_MAD_IFC(thh_hob_p->cmd, 0, 0, port_num, &(mad_frame_in[0]), &(mad_frame_out[0]));\r
- if (cmd_ret != THH_CMD_STAT_OK) {\r
- TEST_CMD_FATAL(cmd_ret);\r
- MTL_ERROR2( "THH_hob_get_pkey_tbl: ERROR : Get Partition Table command failed (%d) for port %d\n", cmd_ret, port_num);\r
- FREE(mad_frame_out);\r
- FREE(mad_frame_in);\r
- return HH_ERR;\r
- }\r
- PKeyTableMADToSt(&pkey_table, &(mad_frame_out[0]));\r
- \r
- for (j = 0; j < 32; j++) {\r
- pkey_tbl_p[pkey_index++] = pkey_table.pkey[j];\r
- if (pkey_index == num_pkeys) {\r
- break;\r
- }\r
- }\r
- }\r
- } else {\r
- hh_ret = THH_hob_get_qpm ( thh_hob_p, &qpm );\r
- if (hh_ret != HH_OK) {\r
- MTL_ERROR2( "THH_hob_get_qpm: invalid QPM handle (ret= %d)\n", hh_ret);\r
- FREE(mad_frame_out);\r
- FREE(mad_frame_in);\r
- return HH_EINVAL;\r
- }\r
-/*** warning C4242: '=' : conversion from 'int' to 'u_int16_t', possible loss of data ***/\r
- hh_ret = THH_qpm_get_all_pkeys(qpm,port_num,(u_int16_t)num_pkeys, pkey_tbl_p);\r
- if (hh_ret != HH_OK) {\r
- MTL_ERROR2( "THH_qpm_get_all_sgids failed (ret= %d)\n", hh_ret);\r
- FREE(mad_frame_out);\r
- FREE(mad_frame_in);\r
- return HH_EINVAL;\r
- }\r
- }\r
-\r
- FREE(mad_frame_out);\r
- FREE(mad_frame_in);\r
- return(HH_OK);\r
-}\r
-/******************************************************************************\r
- * Function: THH_hob_get_pkey_tbl\r
- *\r
- * Description: Gets PKEY table for a given port \r
- *\r
- * input:\r
- * hca_hndl\r
- * port_num - 1 or 2\r
- * tbl_len_in - size of table provided for response (in pkeys)\r
- * output: \r
- * tbl_len_out - size of returned table (in pkeys)\r
- * pkey_tbl_p - pointer to table containing data (space provided by caller)\r
- * returns:\r
- * HH_OK\r
- * HH_EINVAL\r
- * HH_EINVAL_HCA_HNDL\r
- * HH_ERR\r
- *\r
- * Comments: Does MAD query to get the data in real time. \r
- *\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_get_pkey_tbl(HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- u_int16_t tbl_len_in,\r
- u_int16_t *tbl_len_out,\r
- IB_pkey_t *pkey_tbl_p)\r
-{\r
- MT_bool is_legacy = FALSE;\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- FUNC_IN;\r
-\r
- MTL_DEBUG4("THH_hob_get_pkey_tbl: hca_hndl=0x%p, port= %d, return table len = %d\n",\r
- hca_hndl, port_num, tbl_len_in);\r
-\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_get_pkey_tbl : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_get_pkey_tbl : ERROR : No device registered\n");\r
- return HH_EINVAL;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
- THH_hob_get_legacy_mode(thh_hob_p, &is_legacy);\r
- return(THH_hob_get_pkey_tbl_local(hca_hndl,port_num,tbl_len_in,\r
- tbl_len_out,pkey_tbl_p,is_legacy));\r
-\r
-}\r
-\r
-HH_ret_t THH_hob_init_pkey_tbl( HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- u_int16_t tbl_len_in,\r
- u_int16_t* tbl_len_out,\r
- IB_pkey_t *pkey_tbl_p)\r
-{\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- return(THH_hob_get_pkey_tbl_local(hca_hndl,port_num,tbl_len_in,\r
- tbl_len_out,pkey_tbl_p,1));\r
-\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_get_gid_tbl_local\r
- *\r
- * Description: Gets GID table for a given port \r
- *\r
- * input:\r
- * hca_hndl\r
- * port_num - 1 or 2\r
- * tbl_len_in - size of table provided for response (in pkeys)\r
- * use_mad_query_for_gid_prefix - if TRUE, query Tavor for gid prefix.\r
- * else, use gid_table tracking in thh_qpm\r
- * output: \r
- * tbl_len_out - size of returned table (in pkeys)\r
- * param_gid_p - pointer to table containing data (space provided by caller)\r
- * returns:\r
- * HH_OK\r
- * HH_EINVAL\r
- * HH_EINVAL_HCA_HNDL\r
- * HH_ERR\r
- *\r
- * Comments: Does MAD query to get the data in real time. \r
- *\r
- *****************************************************************************/\r
-#ifndef IVAPI_THH\r
-static \r
-#endif\r
-HH_ret_t THH_hob_get_gid_tbl_local( HH_hca_hndl_t hca_hndl,\r
- IB_port_t port,\r
- u_int16_t tbl_len_in,\r
- u_int16_t* tbl_len_out,\r
- IB_gid_t* param_gid_p,\r
- MT_bool use_mad_query_for_gid_prefix)\r
-{\r
- SM_MAD_PortInfo_t port_info;\r
- SM_MAD_GUIDInfo_t guid_info;\r
- u_int8_t *mad_frame_in;\r
- u_int8_t *mad_frame_out;\r
- THH_cmd_status_t cmd_ret;\r
- int num_guids, guid_index;\r
- int num_guidinfo_commands;\r
- u_int8_t *gid_p = (u_int8_t *) param_gid_p;\r
- int i,j;\r
- HH_ret_t hh_ret = HH_OK;\r
- THH_qpm_t qpm;\r
- IB_gid_t gid;\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- FUNC_IN;\r
-\r
- MTL_DEBUG4("THH_hob_get_gid_tbl_local: hca_hndl=0x%p, port= %d, return table len = %d\n",\r
- hca_hndl, port, tbl_len_in);\r
-\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK && use_mad_query_for_gid_prefix) {\r
- MTL_ERROR1("THH_hob_get_gid_tbl: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_get_gid_tbl : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
- \r
-\r
- /* check if have valid port number */\r
- if (port > thh_hob_p->dev_lims.num_ports || port < 1) {\r
- MTL_ERROR1("THH_hob_get_gid_tbl: port number (%d) not valid)\n", port);\r
- return HH_EINVAL_PORT;\r
- }\r
-\r
- if (tbl_len_out == NULL) {\r
- return HH_EINVAL;\r
- }\r
- \r
-\r
- /* check that gid table has enough space */\r
- num_guids = thh_hob_p->init_ib_props[port-1].max_gid;\r
-/*** warning C4242: '=' : conversion from 'int' to 'u_int16_t', possible loss of data ***/\r
- *tbl_len_out = (u_int16_t)num_guids;\r
-\r
- if (tbl_len_in < num_guids) {\r
- if (!tbl_len_in) {\r
- MTL_TRACE2( "THH_hob_get_gid_tbl: returning gid table configured size (%d)\n", num_guids);\r
- } else {\r
- MTL_ERROR2( "THH_hob_get_gid_tbl: ERROR : not enough space in return value table. Need %d\n",\r
- num_guids);\r
- }\r
- return HH_EAGAIN;\r
- }\r
-\r
- /* check that have valid output buffer area */\r
- if (param_gid_p == NULL) {\r
- return HH_EINVAL;\r
- }\r
-\r
-\r
- /* get GID table using MAD commands in THH_cmd object */\r
- if (use_mad_query_for_gid_prefix == TRUE) {\r
-\r
- mad_frame_in = TNMALLOC(u_int8_t, IB_MAD_SIZE);\r
- if ( !mad_frame_in ) {\r
- return HH_EAGAIN;\r
- }\r
- mad_frame_out = TNMALLOC(u_int8_t, IB_MAD_SIZE);\r
- if ( !mad_frame_out ) {\r
- FREE(mad_frame_in);\r
- return HH_EAGAIN;\r
- }\r
- /* First, get the GID prefix from via MAD query */\r
- memset(mad_frame_in, 0, sizeof(mad_frame_in));\r
- memset(mad_frame_out, 0, sizeof(mad_frame_out));\r
- MADHeaderBuild(IB_CLASS_SMP, \r
- 0,\r
- IB_METHOD_GET,\r
- IB_SMP_ATTRIB_PORTINFO,\r
- (u_int32_t) port,\r
- &(mad_frame_in[0]));\r
- \r
- /* issue the query */\r
- cmd_ret = THH_cmd_MAD_IFC(thh_hob_p->cmd, 0, 0, port, &(mad_frame_in[0]), &(mad_frame_out[0]));\r
- if (cmd_ret != THH_CMD_STAT_OK) {\r
- TEST_CMD_FATAL(cmd_ret);\r
- MTL_ERROR2( "THH_hob_get_gid_tbl: ERROR : Get Port Info command failed (%d) for port %d\n", cmd_ret, port);\r
- FREE(mad_frame_out);\r
- FREE(mad_frame_in);\r
- return HH_ERR;\r
- }\r
- PortInfoMADToSt(&port_info, &(mad_frame_out[0]));\r
- PortInfoPrint(&port_info);\r
- memcpy(&gid, &(port_info.qwGIDPrefix), sizeof(port_info.qwGIDPrefix));\r
-\r
- /* Now, get the GUIDs, and build GIDS */\r
- num_guidinfo_commands = ((num_guids - 1) / 8) + 1;\r
-\r
- guid_index = 0;\r
- for (i = 0; i < num_guidinfo_commands; i++) {\r
- memset(mad_frame_in, 0, sizeof(mad_frame_in));\r
- memset(mad_frame_out, 0, sizeof(mad_frame_out));\r
- MADHeaderBuild(IB_CLASS_SMP, \r
- 0,\r
- IB_METHOD_GET,\r
- IB_SMP_ATTRIB_GUIDINFO,\r
- (u_int32_t) (i*8),\r
- &(mad_frame_in[0]));\r
-\r
- cmd_ret = THH_cmd_MAD_IFC(thh_hob_p->cmd, 0, 0, port, &(mad_frame_in[0]), &(mad_frame_out[0]));\r
- if (cmd_ret != THH_CMD_STAT_OK) {\r
- TEST_CMD_FATAL(cmd_ret);\r
- MTL_ERROR2( "THH_hob_get_gid_tbl: ERROR : Get GUID Info command failed (%d) for port %d\n", cmd_ret, port);\r
- FREE(mad_frame_out);\r
- FREE(mad_frame_in);\r
- return HH_ERR;\r
- }\r
- GUIDInfoMADToSt(&guid_info, &(mad_frame_out[0]));\r
- GUIDInfoPrint(&guid_info);\r
-\r
- for (j = 0; j < 8; j++) {\r
- memcpy (gid_p, &(gid), sizeof(port_info.qwGIDPrefix));\r
- gid_p += sizeof(port_info.qwGIDPrefix);\r
- memcpy (gid_p, &(guid_info.guid[j]), sizeof(IB_guid_t));\r
- gid_p += sizeof(u_int64_t);\r
- guid_index++;\r
- if (guid_index == num_guids) {\r
- break;\r
- }\r
- }\r
- }\r
- FREE(mad_frame_out);\r
- FREE(mad_frame_in);\r
- } else {\r
- memset(&port_info, 0, sizeof(port_info));\r
- hh_ret = THH_hob_get_qpm ( thh_hob_p, &qpm );\r
- if (hh_ret != HH_OK) {\r
- MTL_ERROR2( "THH_hob_get_qpm: invalid QPM handle (ret= %d)\n", hh_ret);\r
- return HH_EINVAL;\r
- }\r
-/*** warning C4242: 'function' : conversion from 'int' to 'u_int8_t', possible loss of data ***/\r
- hh_ret = THH_qpm_get_all_sgids(qpm,port,(u_int8_t)num_guids, param_gid_p);\r
- if (hh_ret != HH_OK) {\r
- MTL_ERROR2( "THH_qpm_get_all_sgids failed (ret= %d)\n", hh_ret);\r
- return HH_EINVAL;\r
- }\r
- return HH_OK;\r
- }\r
-\r
- return HH_OK;\r
-} /* THH_get_gid_tbl */\r
-/******************************************************************************\r
- * Function: THH_hob_get_gid_tbl\r
- *\r
- * Description: Gets GID table for a given port \r
- *\r
- * input:\r
- * hca_hndl\r
- * port_num - 1 or 2\r
- * tbl_len_in - size of table provided for response (in pkeys)\r
- * output: \r
- * tbl_len_out - size of returned table (in pkeys)\r
- * param_gid_p - pointer to table containing data (space provided by caller)\r
- * returns:\r
- * HH_OK\r
- * HH_EINVAL\r
- * HH_EINVAL_HCA_HNDL\r
- * HH_ERR\r
- *\r
- * Comments: Does MAD query to get the data in real time. \r
- *\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_get_gid_tbl( HH_hca_hndl_t hca_hndl,\r
- IB_port_t port,\r
- u_int16_t tbl_len_in,\r
- u_int16_t* tbl_len_out,\r
- IB_gid_t* param_gid_p)\r
-{\r
- MT_bool is_legacy = FALSE;\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- FUNC_IN;\r
-\r
- MTL_DEBUG4("THH_hob_get_gid_tbl: hca_hndl=0x%p, port= %d, return table len = %d\n",\r
- hca_hndl, port, tbl_len_in);\r
-\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_get_gid_tbl : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_get_gid_tbl : ERROR : No device registered\n");\r
- return HH_EINVAL;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
- \r
- THH_hob_get_legacy_mode(thh_hob_p, &is_legacy);\r
- return(THH_hob_get_gid_tbl_local(hca_hndl,port,tbl_len_in,\r
- tbl_len_out,param_gid_p,is_legacy));\r
-\r
-}\r
-\r
-HH_ret_t THH_hob_init_gid_tbl( HH_hca_hndl_t hca_hndl,\r
- IB_port_t port,\r
- u_int16_t tbl_len_in,\r
- u_int16_t* tbl_len_out,\r
- IB_gid_t* param_gid_p)\r
-{\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- return(THH_hob_get_gid_tbl_local(hca_hndl,port,tbl_len_in,\r
- tbl_len_out,param_gid_p,1));\r
-\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_set_comp_eventh\r
- *\r
- * Description: Sets completion event handler for VIP layer (below vapi). Used internally\r
- * by VAPI \r
- *\r
- * input:\r
- * hca_hndl\r
- * event - pointer to handler function\r
- * private_data - pointer to context data provided to handler\r
- * returns:\r
- * HH_OK\r
- * HH_EAGAIN\r
- * HH_EINVAL_HCA_HNDL\r
- * HH_ERR\r
- *\r
- * Comments: Initial (dummy) handler is provided during open_hca. Therefore,\r
- * the function THH_eventp_replace_handler is used to register the handler.\r
- *\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_set_comp_eventh(HH_hca_hndl_t hca_hndl,\r
- HH_comp_eventh_t event,\r
- void* private_data)\r
-{\r
- HH_ret_t ret;\r
- THH_eventp_handler_t ev_hndlr;\r
- \r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_set_comp_eventh: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_set_comp_eventh : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_set_comp_eventh: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- if (event == NULL) {\r
- event = THH_dummy_comp_event;\r
- } else {\r
- TEST_RETURN_FATAL(thh_hob_p);\r
- }\r
- ev_hndlr.comp_event_h = event;\r
-\r
-\r
- if (thh_hob_p->eventp == (THH_eventp_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_set_comp_eventh: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- /* neutralizing for VAPI start */\r
- // return HH_OK;\r
-\r
- ret = THH_eventp_replace_handler(thh_hob_p->eventp,thh_hob_p->compl_eq, ev_hndlr, private_data);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1( "THH_hob_set_comp_eventh: ERROR : cannot register completion event handler (%d)\n", ret);\r
- return HH_ERR;\r
- }\r
- \r
- return HH_OK;\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_set_async_eventh\r
- *\r
- * Description: Sets async handler for VIP layer (below vapi). Used internally\r
- * by VAPI \r
- *\r
- * input:\r
- * hca_hndl\r
- * event - pointer to handler function\r
- * private_data - pointer to context data provided to handler\r
- * returns:\r
- * HH_OK\r
- * HH_EAGAIN\r
- * HH_EINVAL_HCA_HNDL\r
- * HH_ERR\r
- *\r
- * Comments: Initial (dummy) handler is provided during open_hca. Therefore,\r
- * the function THH_eventp_replace_handler is used to register the handler.\r
- *\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_set_async_eventh( HH_hca_hndl_t hca_hndl,\r
- HH_async_eventh_t event,\r
- void* private_data)\r
-{\r
- HH_ret_t ret;\r
- THH_eventp_handler_t ev_hndlr;\r
-\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_set_async_eventh: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_set_async_eventh : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (event == NULL) {event = &THH_dummy_async_event;\r
- } else {\r
- TEST_RETURN_FATAL(thh_hob_p);\r
- }\r
- \r
- ev_hndlr.ib_comp_event_h = event;\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_set_async_eventh: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- if (thh_hob_p->eventp == (THH_eventp_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_set_async_eventh: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-// neutralizing for VAPI start\r
-// return HH_OK;\r
- \r
- ret = THH_eventp_replace_handler(thh_hob_p->eventp,thh_hob_p->ib_eq, ev_hndlr, private_data);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1( "THH_hob_set_async_eventh: ERROR : cannot register async event handler (%d)\n", ret);\r
- return HH_ERR;\r
- }\r
-\r
- /* track async event handler setting for use in fatal error handling */\r
- MOSAL_spinlock_dpc_lock(&thh_hob_p->async_spl);\r
- thh_hob_p->async_eventh = event;\r
- thh_hob_p->async_ev_private_context = private_data;\r
- MOSAL_spinlock_unlock(&thh_hob_p->async_spl);\r
-\r
- return HH_OK;\r
-}\r
-\r
-\r
-#ifndef __DARWIN__\r
-int THH_hob_fatal_err_thread(void *arg)\r
- {\r
- THH_hob_t hob_p;\r
- THH_hob_cat_err_thread_t *fatal_thread_obj_p = (THH_hob_cat_err_thread_t *)arg;\r
- HH_event_record_t fatal_ev_rec;\r
- THH_cmd_t cmd_if;\r
- THH_eventp_t eventp;\r
- call_result_t mosal_ret;\r
- \r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- MTL_TRACE2("%s: Initializing\n", __func__);\r
-\r
- hob_p = (THH_hob_t)(fatal_thread_obj_p->hob);\r
- MOSAL_thread_set_name(&fatal_thread_obj_p->mto, "cleanup_thread");\r
-\r
-\r
- /* signal that thread is up */\r
- fatal_thread_obj_p->have_fatal = FALSE;\r
- MOSAL_syncobj_signal(&fatal_thread_obj_p->start_sync);\r
-\r
- MTL_TRACE3("%s: about to wait on fatal error signal\n", __func__);\r
- mosal_ret=MOSAL_syncobj_waiton(&hob_p->fatal_thread_obj.fatal_err_sync,\r
- MOSAL_SYNC_TIMEOUT_INFINITE);\r
- if (mosal_ret == MT_EINTR || hob_p->fatal_thread_obj.have_fatal == FALSE) {\r
- MTL_DEBUG1(MT_FLFMT("%s: GOT termination request"), __func__);\r
- /* if no fatal error, just return */\r
- MOSAL_syncobj_signal(&fatal_thread_obj_p->stop_sync);\r
- return 1;\r
- }\r
- MTL_ERROR1(MT_FLFMT("%s: RECEIVED FATAL ERROR WAKEUP"), __func__);\r
-\r
- /* fatal error processing */\r
- if (THH_hob_get_cmd_if(hob_p, &cmd_if) == HH_OK) {\r
- THH_cmd_handle_fatal(cmd_if);\r
- }\r
- if (THH_hob_get_eventp(hob_p,&eventp) == HH_OK) {\r
- THH_eventp_handle_fatal(eventp);\r
- }\r
-\r
- /* Halt HCA here */\r
- if (hob_p->module_flags.fatal_delay_halt == 0) {\r
- MTL_DEBUG1(MT_FLFMT("%s: halting the HCA"), __func__);\r
- THH_hob_halt_hca(hob_p);\r
- }\r
-\r
- MOSAL_spinlock_dpc_lock(&hob_p->fatal_spl);\r
- /* turn off STARTED bit, and turn on HALTED bit */\r
- hob_p->thh_state &= ~(THH_STATE_FATAL_START);\r
- hob_p->thh_state |= THH_STATE_FATAL_HCA_HALTED;\r
- MOSAL_syncobj_signal(&hob_p->thh_fatal_complete_syncobj);\r
- MOSAL_spinlock_unlock(&hob_p->fatal_spl);\r
-\r
- /* INVOKE THE async event callback with fatal error */\r
- if (hob_p->hh_hca_hndl != NULL && hob_p->async_eventh != NULL) {\r
- MTL_TRACE1(MT_FLFMT("%s: INVOKE ASYNC CALLBACK"), __func__); \r
- memset(&fatal_ev_rec, 0, sizeof(HH_event_record_t));\r
- fatal_ev_rec.etype = VAPI_LOCAL_CATASTROPHIC_ERROR;\r
- fatal_ev_rec.syndrome = hob_p->fatal_syndrome;\r
- (*(hob_p->async_eventh))(hob_p->hh_hca_hndl, &fatal_ev_rec, hob_p->async_ev_private_context);\r
- }\r
- MOSAL_syncobj_signal(&fatal_thread_obj_p->stop_sync);\r
- return 0;\r
-}\r
-#endif /* not defined __DARWIN__ */\r
-\r
-\r
-/*\r
- * mosal_find_capbility_ptr\r
- */\r
-static call_result_t mosal_find_capbility_ptr(u_int8_t bus,\r
- u_int8_t dev_func,\r
- u_int8_t cap_id,\r
- u_int8_t *cap_ptr_p)\r
-{\r
- call_result_t rc;\r
- u_int8_t cap_ptr;\r
- u_int32_t cap_val_dw;\r
-\r
- /* read cap pointer */\r
- rc = MOSAL_PCI_read_config_byte(bus, dev_func, 0x34, &cap_ptr);\r
- if ( rc != MT_OK ) {\r
- MTL_ERROR1(MT_FLFMT("%s: failed reading cap pointer - %s"), __func__, mtl_strerror(rc));\r
- return rc; \r
- }\r
-\r
- while ( 1 ) {\r
- rc = MOSAL_PCI_read_config_dword(bus, dev_func, cap_ptr, &cap_val_dw);\r
- if ( rc != MT_OK ) {\r
- MTL_ERROR1(MT_FLFMT("%s: failed reading dword at address 0x%x - %s"), __func__, cap_ptr, mtl_strerror(rc));\r
- return rc; \r
- }\r
- if ( (cap_val_dw&0xff) == cap_id ) {\r
- *cap_ptr_p = cap_ptr;\r
- return MT_OK;\r
- }\r
- cap_ptr = (u_int8_t)(cap_val_dw>>8) & 0xfc; /* mask 2 lsbs */\r
- if ( cap_ptr == 0 ) break;\r
- }\r
- return MT_ENORSC;\r
-}\r
-\r
-\r
-/*\r
- * THH_set_max_read_request_size\r
- *\r
- * set Max Read Request Size for Arbel in Tavor mode 5 => 4096 bytes\r
- */\r
-static call_result_t THH_set_max_read_request_size(THH_hw_props_t *hw_props_p)\r
-{\r
- call_result_t rc;\r
- u_int8_t cap_ptr;\r
- u_int16_t cap_val;\r
- u_int8_t mrrs_val = 5; /* => 4096 bytes */\r
- const u_int8_t rbc_cap_id = 16; /* Max Read Request Size capability ID */\r
-\r
- rc = mosal_find_capbility_ptr(hw_props_p->bus, hw_props_p->dev_func, rbc_cap_id, &cap_ptr);\r
- if ( rc != MT_OK ) {\r
- MTL_DEBUG1(MT_FLFMT("%s: failed to find MRRS capability - %s"), __func__, mtl_strerror_sym(rc));\r
- return rc;\r
- }\r
- rc = MOSAL_PCI_read_config_word(hw_props_p->bus, hw_props_p->dev_func, cap_ptr+8, &cap_val);\r
- if ( rc != MT_OK ) {\r
- MTL_ERROR1(MT_FLFMT("%s: failed to read rbc - %s"), __func__, mtl_strerror_sym(rc));\r
- return rc;\r
- }\r
- cap_val &= 0x8fff;\r
- cap_val |= (mrrs_val<<12);\r
- rc = MOSAL_PCI_write_config_word(hw_props_p->bus, hw_props_p->dev_func, cap_ptr+8, cap_val);\r
- if ( rc != MT_OK ) {\r
- MTL_ERROR1(MT_FLFMT("%s: failed to write rbc - %s"), __func__, mtl_strerror_sym(rc));\r
- }\r
- return rc;\r
-}\r
-\r
-/*\r
- * THH_set_rbc\r
- *\r
- * set the default Read Byte Count for Tavor - 3 ==> 4096 bytes\r
- */\r
-static call_result_t THH_set_rbc(THH_hw_props_t *hw_props_p)\r
-{\r
- call_result_t rc;\r
- u_int8_t cap_ptr, cap_val;\r
- u_int8_t rbc_val = 3;\r
- const u_int8_t rbc_cap_id = 7; /* Read Byte Count capability ID */\r
-\r
- rc = mosal_find_capbility_ptr(hw_props_p->bus, hw_props_p->dev_func, rbc_cap_id, &cap_ptr);\r
- if ( rc != MT_OK ) {\r
- MTL_DEBUG1(MT_FLFMT("%s: failed to find RBC capability - %s"), __func__, mtl_strerror_sym(rc));\r
- return rc;\r
- }\r
- rc = MOSAL_PCI_read_config_byte(hw_props_p->bus, hw_props_p->dev_func, cap_ptr+2, &cap_val);\r
- if ( rc != MT_OK ) {\r
- MTL_ERROR1(MT_FLFMT("%s: failed to read rbc - %s"), __func__, mtl_strerror_sym(rc));\r
- return rc;\r
- }\r
- cap_val &= 0xf3;\r
- cap_val |= (rbc_val<<2);\r
- rc = MOSAL_PCI_write_config_byte(hw_props_p->bus, hw_props_p->dev_func, cap_ptr+2, cap_val);\r
- if ( rc != MT_OK ) {\r
- MTL_ERROR1(MT_FLFMT("%s: failed to write rbc - %s"), __func__, mtl_strerror_sym(rc));\r
- }\r
- return rc;\r
-}\r
-\r
-\r
-\r
-/*\r
- * THH_set_capabilities\r
- */\r
-static void THH_set_capabilities(THH_hw_props_t *hw_props_p)\r
-{\r
- /* set the default Read Byte Count for Tavor */\r
- THH_set_rbc(hw_props_p);\r
-\r
- /* set max read request size in capabilty structure of PCI express */\r
- THH_set_max_read_request_size(hw_props_p);\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_create\r
- *\r
- * Description: Creates the HOB object for an HCA, and registers it in HH \r
- *\r
- * input:\r
- * hw_props_p -- PCI properties (BARs, etc)\r
- * hca_seq_num - a sequence number assigned to this HCA to differentiate it \r
- * from other HCAs on this host\r
- * mod_flags - flags passed in at module initialization (e.g., insmod)\r
- * output: \r
- * hh_hndl_p - size of returned table (in pkeys)\r
- * returns:\r
- * HH_OK\r
- * HH_EAGAIN\r
- * HH_ERR -- other errors\r
- *\r
- * Comments: This function involves the following steps: \r
- * 1.Allocate THH_hob data context. \r
- * 2.Create the THH_cmd_if object instance (in order to enable \r
- * queries of HCA resources even before HCA is opened). \r
- * 3.Invoke ENABLE_SYS command ((polling mode). \r
- * 4.Query HCA for available DDRmemory resources \r
- * (use the Command interface in polling mode)and create \r
- * the THH_ddrmm object based on results. \r
- * 5.Query HCA for other capabilties and save them in THH_hob context. \r
- * 6.Register HCA in HH (i.e.call HH_add_hca_dev()).\r
- *\r
- * Also initializes the HOB mutex for controlling Open HCA and Close HCA \r
- *\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_create(/*IN*/ THH_hw_props_t *hw_props_p,\r
- /*IN*/ u_int32_t hca_seq_num,\r
- /*IN*/ THH_module_flags_t *mod_flags,\r
- /*OUT*/ HH_hca_hndl_t *hh_hndl_p )\r
-{\r
-\r
- //HH_hca_hndl_t hca_hndl = 0;\r
- HH_ret_t ret;\r
- HH_if_ops_t *if_ops_p = 0;\r
- THH_hob_t hob_p;\r
- MT_size_t ddr_size;\r
- MT_size_t fw_size;\r
- HH_hca_hndl_t new_hh_hndl;\r
- THH_cmd_status_t cmd_ret;\r
- HH_hca_dev_t tdev;\r
- u_int64_t fw_version;\r
- u_int32_t req_fw_maj_version=0;\r
- u_int16_t req_fw_min_version = 0;\r
- u_int16_t req_fw_submin_version = 0;\r
- int int_ret = 0;\r
- call_result_t mosal_ret = MT_OK;\r
- MT_phys_addr_t cmdif_uar0_arg;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- MTL_DEBUG4("Entering THH_hob_create\nhca_seq_num = %d, legacy_flag = %s, av_in_host_mem = %s\n", \r
- hca_seq_num, (mod_flags->legacy_sqp == FALSE ? "FALSE" : "TRUE"),\r
- (mod_flags->av_in_host_mem == FALSE ? "FALSE" : "TRUE"));\r
- THH_print_hw_props(hw_props_p);\r
-\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_create: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- THH_set_capabilities(hw_props_p);\r
-\r
- /* Allocate THH hob structure */ \r
- hob_p = (THH_hob_t)MALLOC(sizeof(struct THH_hob_st));\r
-\r
- if (hob_p == 0) {\r
- MTL_ERROR1("THH_hob_create: could not allocate memory for THH hob\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- MTL_DEBUG1("THH_hob_create: HOB address = 0x%p\n", hob_p);\r
- memset(hob_p, 0, sizeof(struct THH_hob_st));\r
-\r
- \r
- /* initialize the HOB mutex */\r
- MOSAL_mutex_init(&(hob_p->mtx));\r
-\r
- /* set device name */\r
- sprintf(hob_p->dev_name, "InfiniHost%d",hca_seq_num); \r
-#if !defined(__DARWIN__)\r
- printk("\nMellanox Tavor Device Driver is creating device \"%s\" (bus=%02x, devfn=%02x)\n\n", \r
- hob_p->dev_name,hw_props_p->bus,hw_props_p->dev_func);\r
-#else\r
- MTL_DEBUG1("\nMellanox Tavor Device Driver is creating device \"%s\"\n\n", hob_p->dev_name);\r
-#endif\r
-\r
- /* set embedded object handles to invalid */\r
- \r
- hob_p->cmd = (THH_cmd_t)THH_INVALID_HNDL;\r
- hob_p->ddrmm = (THH_ddrmm_t)THH_INVALID_HNDL;\r
- hob_p->uldm = (THH_uldm_t)THH_INVALID_HNDL;\r
- hob_p->mrwm = (THH_mrwm_t)THH_INVALID_HNDL;\r
- hob_p->cqm = (THH_cqm_t)THH_INVALID_HNDL;\r
-//hob_p->eecm = (THH_eecm_t)THH_INVALID_HNDL; /* JPM -- EECM ADDITIONS HERE */\r
- hob_p->qpm = (THH_qpm_t)THH_INVALID_HNDL;\r
- hob_p->udavm = (THH_udavm_t)THH_INVALID_HNDL;\r
- hob_p->mcgm = (THH_mcgm_t)THH_INVALID_HNDL;\r
- hob_p->eventp = (THH_eventp_t)THH_INVALID_HNDL;\r
- hob_p->kar = (THH_uar_t)THH_INVALID_HNDL;\r
- \r
- /* initialize EQ handles to all EQs invalid */\r
- hob_p->compl_eq = THH_INVALID_EQN;\r
- hob_p->ib_eq = THH_INVALID_EQN;\r
-\r
- /* initialize fatal error handling fields */\r
- memcpy(&(hob_p->hw_props), hw_props_p, sizeof(THH_hw_props_t));\r
- memcpy(&(hob_p->module_flags), mod_flags, sizeof(THH_module_flags_t));\r
- hob_p->hca_seq_num = hca_seq_num;\r
- hob_p->thh_state = THH_STATE_CREATING;\r
- if (MOSAL_spinlock_init(&(hob_p->fatal_spl)) != MT_OK){\r
- MTL_ERROR4(MT_FLFMT("%s: Failed to initializing fatal error spinlock"), __func__); \r
- ret= HH_ERR;\r
- goto err_free_hob;\r
- }\r
- if (MOSAL_spinlock_init(&(hob_p->async_spl)) != MT_OK){\r
- MTL_ERROR4(MT_FLFMT("%s: Failed to initializing async handler tracking spinlock"), __func__); \r
- ret= HH_ERR;\r
- goto err_free_hob;\r
- }\r
- /* dummy async event handler is passed to THH_eventp when initializing ib_eq */\r
- hob_p->async_eventh = &THH_dummy_async_event;\r
- hob_p->async_ev_private_context = NULL;\r
-\r
-#ifndef __DARWIN__\r
- /* get bridge config info */\r
- ret = THH_hob_get_pci_br_config(hob_p);\r
-\r
- /* get hca config info */\r
- ret = read_pci_config(hw_props_p->bus,hw_props_p->dev_func,hob_p->pci_hca_info.config);\r
- hob_p->pci_hca_info.bus = hw_props_p->bus;\r
- hob_p->pci_hca_info.dev_func = hw_props_p->dev_func;\r
- hob_p->pci_hca_info.is_valid = TRUE;\r
-#endif /* not defined __DARWIN__ */\r
-\r
- /* create the THH_cmd object so that can initialize and query the adapter */\r
- /* HCR register offset */\r
- if ( mod_flags->cmdif_post_uar0) {\r
- cmdif_uar0_arg = hw_props_p->uar_base;\r
- }\r
- else {\r
- cmdif_uar0_arg = (MT_phys_addr_t) MAKE_ULONGLONG(0xFFFFFFFFFFFFFFFF);\r
- }\r
- ret = THH_cmd_create(hob_p, hw_props_p->hw_ver, hw_props_p->cr_base, cmdif_uar0_arg, &(hob_p->cmd),\r
- mod_flags->inifinite_cmd_timeout, mod_flags->num_cmds_outs);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_create: could not create CMD object (%d)\n", ret);\r
- ret = HH_ERR;\r
- goto err_free_hob;\r
- }\r
-\r
-\r
- /* invoke SYS_ENA command on tavor to initialize it -- load firmware from flash, etc.*/\r
- cmd_ret = THH_cmd_SYS_EN(hob_p->cmd);\r
- if (cmd_ret != THH_CMD_STAT_OK) {\r
- if (cmd_ret == THH_CMD_STAT_EFATAL) {\r
- MTL_ERROR1(MT_FLFMT("THH_hob_create: FATAL ERROR in THH_cmd_SYS_EN"));\r
- ret = HH_EFATAL;\r
- } else {\r
- MTL_ERROR1(MT_FLFMT("THH_hob_create: CMD_error in THH_cmd_SYS_EN (%d)"), cmd_ret);\r
- ret = HH_ERR;\r
- }\r
- goto cmd_err;\r
- }\r
-\r
-\r
- /* do query firmware command */\r
- cmd_ret = THH_cmd_QUERY_FW(hob_p->cmd, &(hob_p->fw_props));\r
- if (cmd_ret != THH_CMD_STAT_OK) {\r
- if (cmd_ret == THH_CMD_STAT_EFATAL) {\r
- MTL_ERROR1(MT_FLFMT("THH_hob_create: FATAL ERROR in THH_cmd_QUERY_FW"));\r
- ret = HH_EFATAL;\r
- } else {\r
- MTL_ERROR1(MT_FLFMT("THH_hob_create: CMD_error in THH_cmd_QUERY_FW (%d)"), cmd_ret);\r
- ret = HH_ERR;\r
- }\r
- goto undo_sys_ena;\r
- }\r
- fw_version = hob_p->fw_props.fw_rev_major;\r
- fw_version = (fw_version <<16) | hob_p->fw_props.fw_rev_minor;\r
- fw_version = (fw_version <<16) | hob_p->fw_props.fw_rev_subminor;\r
- /* enter data into version info structure */\r
- hob_p->version_info.fw_ver_major = hob_p->fw_props.fw_rev_major;\r
- hob_p->version_info.fw_ver_minor = hob_p->fw_props.fw_rev_minor;\r
- hob_p->version_info.fw_ver_subminor = hob_p->fw_props.fw_rev_subminor;\r
- hob_p->version_info.hw_ver = hob_p->hw_props.hw_ver;\r
- hob_p->version_info.cmd_if_ver = hob_p->fw_props.cmd_interface_rev;\r
-\r
-\r
- if (fw_version < THH_MIN_FW_VERSION) {\r
- req_fw_maj_version = (u_int32_t) ((((u_int64_t)THH_MIN_FW_VERSION)>>32) & MAKE_ULONGLONG(0xFFFFFFFF));\r
- req_fw_min_version = (u_int16_t) ((((u_int64_t)THH_MIN_FW_VERSION)>>16) & MAKE_ULONGLONG(0xFFFF));\r
- req_fw_submin_version = (u_int16_t) (((u_int64_t)THH_MIN_FW_VERSION) & MAKE_ULONGLONG(0xFFFF));\r
- MTL_ERROR1("THH_hob_create: INSTALLED FIRMWARE VERSION IS NOT SUPPORTED:\n Installed: %x.%x.%x, Minimum Required: %x.%x.%x\n\n",\r
- hob_p->fw_props.fw_rev_major, hob_p->fw_props.fw_rev_minor, hob_p->fw_props.fw_rev_subminor,\r
- req_fw_maj_version, req_fw_min_version, req_fw_submin_version);\r
- ret = HH_ERR;\r
- goto undo_sys_ena;\r
- }\r
-\r
- /* map the firmware error buffer if the appropriate fw version is installed */\r
- if ((fw_version >= THH_MIN_FW_ERRBUF_VERSION) &&\r
- (hob_p->fw_props.error_buf_start != (u_int64_t) 0) &&\r
- (hob_p->fw_props.error_buf_size != 0)) \r
- {\r
-\r
- /* wa for FW bug number 19695 */\r
- if ( (hob_p->fw_props.error_buf_start<hw_props_p->cr_base) || (hob_p->fw_props.error_buf_start>(hw_props_p->cr_base+0x100000)) ) {\r
- MTL_ERROR1(MT_FLFMT("%s: fw_props.error_buf_start is outside of cr-space start="U64_FMT", size=0x%x"),\r
- __func__, hob_p->fw_props.error_buf_start, hob_p->fw_props.error_buf_size);\r
- ret = HH_ERR;\r
- goto undo_sys_ena;\r
- }\r
- \r
- MTL_DEBUG4(MT_FLFMT("THH_hob_create: using cat err buf. pa=0x"U64_FMT", sz=%d"),\r
- hob_p->fw_props.error_buf_start, hob_p->fw_props.error_buf_size);\r
- hob_p->fw_error_buf_start_va = MOSAL_io_remap(hob_p->fw_props.error_buf_start, \r
- 4*(hob_p->fw_props.error_buf_size));\r
- if (hob_p->fw_error_buf_start_va == (MT_virt_addr_t)(MT_ulong_ptr_t) NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: Could not map fw error buffer (phys addr = "U64_FMT", size=%d"),\r
- __func__, hob_p->fw_props.error_buf_start, hob_p->fw_props.error_buf_size);\r
- } else {\r
- hob_p->fw_error_buf = TNMALLOC(u_int32_t,hob_p->fw_props.error_buf_size);\r
- if (hob_p->fw_error_buf == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: Could not allocate buffer for FW catastrophic error info"),__func__);\r
- }\r
- }\r
- }\r
-\r
- /* Get device limits */\r
- cmd_ret = THH_cmd_QUERY_DEV_LIM(hob_p->cmd, &(hob_p->dev_lims));\r
- if (cmd_ret != THH_CMD_STAT_OK) {\r
- if (cmd_ret == THH_CMD_STAT_EFATAL) {\r
- MTL_ERROR1(MT_FLFMT("THH_hob_create: FATAL ERROR in THH_cmd_QUERY_DEV_LIM"));\r
- ret = HH_EFATAL;\r
- } else {\r
- MTL_ERROR1(MT_FLFMT("THH_hob_create: CMD_error in THH_cmd_QUERY_DEV_LIM (%d)"), cmd_ret);\r
- ret = HH_ERR;\r
- }\r
- goto undo_sys_ena;\r
- }\r
-\r
- MTL_DEBUG1(MT_FLFMT("%s: log_max_srq=%u log2_rsvd_srqs=%u srq_entry_sz=%u srq=%ssupported"), __func__,\r
- hob_p->dev_lims.log_max_srqs, hob_p->dev_lims.log2_rsvd_srqs, \r
- hob_p->dev_lims.srq_entry_sz, hob_p->dev_lims.srq ? " ":"NOT-");\r
-\r
- /* Enable SRQ only for FW version 3.1 and up */\r
- if ((hob_p->dev_lims.srq) && \r
- (fw_version < THH_MIN_FW_VERSION_SRQ)) {\r
- MTL_ERROR1("%s: Disabling SRQ support due to FW version: "\r
- "Installed: %x.%x.%x, Minimum Required: 3.1.0\n", __func__,\r
- hob_p->fw_props.fw_rev_major, hob_p->fw_props.fw_rev_minor, hob_p->fw_props.fw_rev_subminor);\r
- hob_p->dev_lims.srq= FALSE;\r
- }\r
-\r
-\r
- /* query tavor for DDR memory resources data */\r
- cmd_ret = THH_cmd_QUERY_DDR(hob_p->cmd, &(hob_p->ddr_props));\r
- if (cmd_ret != THH_CMD_STAT_OK) {\r
- if (cmd_ret == THH_CMD_STAT_EFATAL) {\r
- MTL_ERROR1(MT_FLFMT("THH_hob_create: FATAL ERROR in THH_cmd_QUERY_DDR"));\r
- ret = HH_EFATAL;\r
- } else {\r
- MTL_ERROR1(MT_FLFMT("THH_hob_create: CMD_error in THH_cmd_QUERY_DDR (%d)"), cmd_ret);\r
- ret = HH_ERR;\r
- }\r
- goto undo_sys_ena;\r
- }\r
-\r
- /* HIDE-DDR set in firmware: sanity checks */\r
-#if 0\r
- /* 1. fail if using 32-bit platform (not PAE and not IA64) */\r
- if ((hob_p->ddr_props.dh == TRUE) && (sizeof(MT_phys_addr_t) <=4)) {\r
- MTL_ERROR1("THH_hob_create: HIDE_DDR is not supported on platforms using 32-bit physical addresses\n\n");\r
- ret = HH_ERR;\r
- goto undo_sys_ena;\r
- }\r
-#endif\r
-\r
- /* 2. Fail if firmware version is not recent enough. */\r
- if ((hob_p->ddr_props.dh == TRUE) && (fw_version < THH_MIN_FW_HIDE_DDR_VERSION)) {\r
- req_fw_maj_version = (u_int32_t) ((((u_int64_t)THH_MIN_FW_HIDE_DDR_VERSION)>>32) & 0xFFFFFFFF);\r
- req_fw_min_version = (u_int16_t) ((((u_int64_t)THH_MIN_FW_HIDE_DDR_VERSION)>>16) & 0xFFFF);\r
- req_fw_submin_version = (u_int16_t) (((u_int64_t)THH_MIN_FW_HIDE_DDR_VERSION) & 0xFFFF);\r
- MTL_ERROR1("THH_hob_create: INSTALLED FIRMWARE VERSION DOES NOT SUPPORT HIDE_DDR:\n Installed: %x.%x.%x, Minimum Required: %x.%x.%x\n\n",\r
- hob_p->fw_props.fw_rev_major, hob_p->fw_props.fw_rev_minor, hob_p->fw_props.fw_rev_subminor,\r
- req_fw_maj_version, req_fw_min_version, req_fw_submin_version);\r
- ret = HH_ERR;\r
- goto undo_sys_ena;\r
- }\r
- \r
-#ifdef DEBUG_MEM_OV\r
-cmdif_dbg_ddr = hob_p->ddr_props.ddr_start_adr; /* address in ddr used for out params in debug mode */\r
-#endif\r
-\r
- /* print info messages that device is operating in HIDE DDR mode (not an error) */\r
- if (hob_p->ddr_props.dh == TRUE) {\r
- MTL_ERROR1("Device %s is operating in HIDE_DDR mode.\n", hob_p->dev_name);\r
- }\r
- \r
-\r
-/* query tavor for adapter data */\r
- cmd_ret = THH_cmd_QUERY_ADAPTER(hob_p->cmd, &(hob_p->adapter_props));\r
- if (cmd_ret != THH_CMD_STAT_OK) {\r
- if (cmd_ret == THH_CMD_STAT_EFATAL) {\r
- MTL_ERROR1(MT_FLFMT("THH_hob_create: FATAL ERROR in THH_cmd_QUERY_ADAPTER"));\r
- ret = HH_EFATAL;\r
- } else {\r
- MTL_ERROR1(MT_FLFMT("THH_hob_create: CMD_error in THH_cmd_QUERY_ADAPTER (%d)"), cmd_ret);\r
- ret = HH_ERR;\r
- }\r
- goto undo_sys_ena;\r
- }\r
- if ( (hob_p->fw_props.fw_end_addr <= hob_p->fw_props.fw_base_addr) ||\r
- hob_p->fw_props.fw_base_addr < hob_p->ddr_props.ddr_start_adr ||\r
- hob_p->fw_props.fw_end_addr > hob_p->ddr_props.ddr_end_adr) {\r
- /* FW region is either improper, or does not lie within bounds of DDR */\r
- MTL_ERROR1("THH_hob_create: FW region is either improper, or is outside DDR\nFW end = "U64_FMT\r
- ", FW start = "U64_FMT"\n DDR end = "U64_FMT", DDR start = "U64_FMT"\n", \r
- hob_p->fw_props.fw_end_addr, hob_p->fw_props.fw_base_addr, \r
- hob_p->ddr_props.ddr_end_adr, hob_p->ddr_props.ddr_start_adr);\r
- ret = HH_ERR;\r
- goto undo_sys_ena;\r
-\r
- }\r
- fw_size = (MT_size_t) (hob_p->fw_props.fw_end_addr - hob_p->fw_props.fw_base_addr + 1);\r
-\r
- if (hob_p->ddr_props.ddr_end_adr < hob_p->ddr_props.ddr_start_adr) {\r
- MTL_ERROR1("THH_hob_create: DDR end address ("U64_FMT") is less than DDR base addr (" U64_FMT ")\n", \r
- hob_p->ddr_props.ddr_end_adr, hob_p->ddr_props.ddr_start_adr);\r
- ret = HH_ERR;\r
- goto undo_sys_ena;\r
- }\r
-\r
- ddr_size = (MT_size_t) (hob_p->ddr_props.ddr_end_adr - hob_p->ddr_props.ddr_start_adr + 1) ;\r
- hob_p->profile.ddr_size = ddr_size - fw_size;\r
-\r
- /* DDR size code is used in THH_calculate_profile to set number of QPs proportionally to size */\r
- hob_p->profile.ddr_size_code = THH_get_ddr_size_code(ddr_size - fw_size);\r
-\r
- ret = THH_ddrmm_create((MT_phys_addr_t) (hob_p->ddr_props.ddr_start_adr), ddr_size, &(hob_p->ddrmm));\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_create: could not create DDRMM object (%d)\n", ret);\r
- goto undo_sys_ena;\r
- }\r
-\r
- ret = THH_ddrmm_reserve(hob_p->ddrmm, hob_p->fw_props.fw_base_addr, fw_size);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_create: could not reserve FW space in DDRMM object (err = %d)\n", ret);\r
- goto undo_ddrm_create;\r
- }\r
- \r
-#ifdef DEBUG_MEM_OV\r
- ret = THH_ddrmm_reserve(hob_p->ddrmm, hob_p->ddr_props.ddr_start_adr, CMDIF_SIZE_IN_DDR);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_create: could not reserve DDR Outbox space in DDRMM object (err = %d)\n", ret);\r
- goto undo_ddrm_create;\r
- }\r
-#endif\r
-\r
- /*create the delay unlock object for catastrophic error use */\r
- int_ret = VIP_delay_unlock_create(&hob_p->delay_unlocks);\r
- if (int_ret != 0) {\r
- MTL_ERROR1("THH_hob_create: could create delay unlock object (err = %d)\n", int_ret);\r
- ret = HH_ENOMEM;\r
- goto delay_unlock_err;\r
- }\r
- \r
-\r
-#ifndef __DARWIN__ /* TODO, need to take care of fatal errors in Darwin */\r
- \r
- /* launch catastrophic error thread */\r
- hob_p->fatal_thread_obj.hob = (struct THH_hob_st *)hob_p;\r
- MOSAL_syncobj_init(&hob_p->fatal_thread_obj.start_sync);\r
- MOSAL_syncobj_init(&hob_p->fatal_thread_obj.stop_sync);\r
- MOSAL_syncobj_init(&hob_p->fatal_thread_obj.fatal_err_sync);\r
- MOSAL_syncobj_init(&hob_p->thh_fatal_complete_syncobj);\r
- hob_p->fatal_thread_obj.have_fatal = FALSE;\r
- mosal_ret = MOSAL_thread_start(&hob_p->fatal_thread_obj.mto, MOSAL_KTHREAD_CLONE_FLAGS,\r
- THH_hob_fatal_err_thread, (void *)(&(hob_p->fatal_thread_obj)));\r
-// if (mosal_ret != MT_OK) {\r
-// MTL_ERROR1("THH_hob_create: could not create fatal error thread (err = %d)\n", mosal_ret);\r
-// ret = HH_ERR;\r
-// goto fatal_thr_create_err;\r
-// }\r
- \r
- /*wait for fatal thread initialization complete */\r
- mosal_ret = MOSAL_syncobj_waiton(&(hob_p->fatal_thread_obj.start_sync), 10000000);\r
- if (mosal_ret != MT_OK) {\r
- if (mosal_ret == MT_EINTR) {\r
- MTL_DEBUG1(MT_FLFMT("%s: Received OS interrupt while initializing fatal error thread (err = %d)"), \r
- __func__,mosal_ret);\r
- ret = HH_EINTR;\r
- } else {\r
- MTL_ERROR1(MT_FLFMT("%s: Timeout on initializing fatal error thread (err = %d)"), \r
- __func__,mosal_ret);\r
- ret = HH_ERR;\r
- }\r
- goto fatal_thr_init_err;\r
- }\r
- MTL_DEBUG4("%s: Created send completion thread.\n", __func__);\r
- /* set up the procedure mapping table and register the tavor device */\r
-\r
-#endif /* ! defined __DARWIN__ */\r
-\r
- if_ops_p = &(hob_p->if_ops);\r
-\r
-#ifndef IVAPI_THH \r
- HH_ifops_tbl_set_enosys(if_ops_p); /* by default, all retuen HH_ENOSYS */\r
-#endif \r
-\r
- /* HCA Calls */\r
- if_ops_p->HHIF_open_hca = &THH_hob_open_hca;\r
- if_ops_p->HHIF_close_hca = &THH_hob_close_hca;\r
- if_ops_p->HHIF_alloc_ul_resources = &THH_hob_alloc_ul_res;\r
- if_ops_p->HHIF_free_ul_resources = &THH_hob_free_ul_res;\r
- if_ops_p->HHIF_query_hca = &THH_hob_query;\r
- if_ops_p->HHIF_modify_hca = &THH_hob_modify;\r
-\r
- /* Misc HCA Operations*/\r
- if_ops_p->HHIF_query_port_prop = &THH_hob_query_port_prop;\r
- if_ops_p->HHIF_get_pkey_tbl = &THH_hob_get_pkey_tbl;\r
- if_ops_p->HHIF_get_gid_tbl = &THH_hob_get_gid_tbl;\r
-\r
- /* Protection Domain Calls */\r
- if_ops_p->HHIF_alloc_pd = &THH_hob_alloc_pd;\r
- if_ops_p->HHIF_free_pd = &THH_hob_free_pd;\r
- if_ops_p->HHIF_alloc_rdd = &THH_hob_alloc_rdd;\r
- if_ops_p->HHIF_free_rdd = &THH_hob_free_rdd;\r
-\r
- /* privileged UD AV */\r
- if_ops_p->HHIF_create_priv_ud_av = &THH_hob_create_ud_av;\r
- if_ops_p->HHIF_modify_priv_ud_av = &THH_hob_modify_ud_av;\r
- if_ops_p->HHIF_query_priv_ud_av = &THH_hob_query_ud_av;\r
- if_ops_p->HHIF_destroy_priv_ud_av = &THH_hob_destroy_ud_av;\r
-\r
- /* Memory Registration */\r
- if_ops_p->HHIF_register_mr = &THH_hob_register_mr;\r
- if_ops_p->HHIF_reregister_mr = &THH_hob_reregister_mr;\r
- if_ops_p->HHIF_register_smr = &THH_hob_register_smr;\r
- if_ops_p->HHIF_query_mr = &THH_hob_query_mr;\r
- if_ops_p->HHIF_deregister_mr = &THH_hob_deregister_mr;\r
-\r
- if_ops_p->HHIF_alloc_mw = &THH_hob_alloc_mw;\r
- if_ops_p->HHIF_query_mw = &THH_hob_query_mw;\r
- if_ops_p->HHIF_free_mw = &THH_hob_free_mw;\r
-\r
- /* Fast memory regions */\r
- if_ops_p->HHIF_alloc_fmr = &THH_hob_alloc_fmr;\r
- if_ops_p->HHIF_map_fmr = &THH_hob_map_fmr;\r
- if_ops_p->HHIF_unmap_fmr = &THH_hob_unmap_fmr;\r
- if_ops_p->HHIF_free_fmr = &THH_hob_free_fmr;\r
-\r
- /* Completion Queues */\r
- if_ops_p->HHIF_create_cq = &THH_hob_create_cq;\r
- if_ops_p->HHIF_resize_cq = &THH_hob_resize_cq;\r
- if_ops_p->HHIF_query_cq = &THH_hob_query_cq;\r
- if_ops_p->HHIF_destroy_cq = &THH_hob_destroy_cq;\r
-\r
- /* Queue Pair */\r
- if_ops_p->HHIF_create_qp = &THH_hob_create_qp;\r
- if_ops_p->HHIF_get_special_qp = &THH_hob_get_special_qp;\r
- if_ops_p->HHIF_modify_qp = &THH_hob_modify_qp;\r
- if_ops_p->HHIF_query_qp = &THH_hob_query_qp;\r
- if_ops_p->HHIF_destroy_qp = &THH_hob_destroy_qp;\r
-#if defined(MT_SUSPEND_QP)\r
- if_ops_p->HHIF_suspend_qp = &THH_hob_suspend_qp;\r
- if_ops_p->HHIF_suspend_cq = &THH_hob_suspend_cq;\r
-#endif\r
- /* SRQ */\r
- if_ops_p->HHIF_create_srq = &THH_hob_create_srq;\r
- if_ops_p->HHIF_query_srq = &THH_hob_query_srq;\r
- if_ops_p->HHIF_modify_srq = &THH_hob_modify_srq;\r
- if_ops_p->HHIF_destroy_srq = &THH_hob_destroy_srq;\r
-\r
- /* EEC */\r
- if_ops_p->HHIF_create_eec = &THH_hob_create_eec;\r
- if_ops_p->HHIF_modify_eec = &THH_hob_modify_eec;\r
- if_ops_p->HHIF_query_eec = &THH_hob_query_eec;\r
- if_ops_p->HHIF_destroy_eec = &THH_hob_destroy_eec;\r
-\r
- if_ops_p->HHIF_set_comp_eventh = &THH_hob_set_comp_eventh;\r
- if_ops_p->HHIF_set_async_eventh = &THH_hob_set_async_eventh;\r
- \r
- \r
- \r
- /* Multicast groups */\r
- if_ops_p->HHIF_attach_to_multicast = &THH_hob_attach_to_multicast;\r
- if_ops_p->HHIF_detach_from_multicast = &THH_hob_detach_from_multicast;\r
- \r
- /* Process local MAD */\r
- if_ops_p->HHIF_process_local_mad = &THH_hob_process_local_mad;\r
- \r
- if_ops_p->HHIF_ddrmm_alloc = &THH_hob_ddrmm_alloc;\r
- if_ops_p->HHIF_ddrmm_query = &THH_hob_ddrmm_query;\r
- if_ops_p->HHIF_ddrmm_free = &THH_hob_ddrmm_free;\r
-\r
- /*\r
- * Register device in the init structure\r
- *\r
- */\r
- tdev.dev_desc = hob_p->dev_name;\r
- tdev.user_lib = "TBD libhcatavor"; /* for future dynamic use */\r
- tdev.vendor_id = MT_MELLANOX_IEEE_VENDOR_ID;\r
- tdev.dev_id = (u_int32_t)hw_props_p->device_id;\r
- MTL_DEBUG1("hw_props_p: device_id = 0x%X, pci_vendor_id=0x%X,hw_ver=0x%X\n",\r
- hw_props_p->device_id, hw_props_p->pci_vendor_id, hw_props_p->hw_ver);\r
- tdev.fw_ver= tdev.fw_ver = hob_p->fw_props.fw_rev_major;\r
- tdev.fw_ver = (tdev.fw_ver <<16) | hob_p->fw_props.fw_rev_minor;\r
- tdev.fw_ver = (tdev.fw_ver <<16) | hob_p->fw_props.fw_rev_subminor;;\r
- tdev.hw_ver = hob_p->hw_props.hw_ver; \r
- tdev.if_ops = if_ops_p;\r
- tdev.hca_ul_resources_sz = sizeof(THH_hca_ul_resources_t);\r
- tdev.pd_ul_resources_sz = sizeof(THH_pd_ul_resources_t);\r
- tdev.cq_ul_resources_sz = sizeof(THH_cq_ul_resources_t);\r
- tdev.srq_ul_resources_sz = sizeof(THH_srq_ul_resources_t);\r
- tdev.qp_ul_resources_sz = sizeof(THH_qp_ul_resources_t);\r
- tdev.device = (void *) hob_p;\r
- tdev.status = HH_HCA_STATUS_CLOSED;\r
-\r
- /* Grab the mutex now, just before adding the device to HH */\r
- MTL_DEBUG4("THH_hob_create: about to grab mutex\n");\r
- if (MOSAL_mutex_acq(&(hob_p->mtx), TRUE) != MT_OK) {\r
- MTL_DEBUG1(MT_FLFMT("%s: Received signal. returning HH_EINTR"), __func__);\r
- ret = HH_EINTR;\r
- goto err_acq_mutex;\r
- }\r
-\r
- MTL_DEBUG4("THH_hob_create: Before HH_add_hca_dev\n");\r
- ret = HH_add_hca_dev(&tdev, &new_hh_hndl);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_hob_create: could not register device %s in HCA HAL\n",\r
- hob_p->dev_name);\r
- goto err_release_mutex;\r
- }\r
-\r
- /* insert HH hca handle into device structure */\r
- ((THH_hob_t)(new_hh_hndl->device))->hh_hca_hndl = new_hh_hndl;\r
- MTL_TRACE1("THH_hob_create: hh_hca_hndl created = %p\n", (void *) new_hh_hndl);\r
-\r
- if (hh_hndl_p != NULL) {\r
- *hh_hndl_p = new_hh_hndl;\r
- }\r
- MOSAL_spinlock_dpc_lock(&hob_p->fatal_spl);\r
- hob_p->thh_state = THH_STATE_CLOSED;\r
- MOSAL_spinlock_unlock(&hob_p->fatal_spl);\r
- \r
- MOSAL_mutex_rel(&(hob_p->mtx));\r
-\r
- return(HH_OK);\r
-\r
- /* ERROR HANDLING: undoes previous steps in reverse order, as needed */\r
-err_release_mutex: \r
- MOSAL_mutex_rel(&(hob_p->mtx));\r
-err_acq_mutex: \r
- VIP_delay_unlock_destroy(hob_p->delay_unlocks);\r
-\r
-fatal_thr_init_err:\r
- /* signal the waited-on sync object, so that thread exits */\r
- MOSAL_syncobj_signal(&(hob_p->fatal_thread_obj.fatal_err_sync));\r
-\r
-//fatal_thr_create_err:\r
-delay_unlock_err:\r
-undo_ddrm_create:\r
- THH_ddrmm_destroy(hob_p->ddrmm);\r
-\r
-undo_sys_ena:\r
- if (hob_p->fw_error_buf_start_va != (MT_virt_addr_t)(MT_ulong_ptr_t) NULL) {\r
- MOSAL_io_unmap(hob_p->fw_error_buf_start_va);\r
- }\r
-\r
- if (hob_p->fw_error_buf != NULL) {\r
- FREE(hob_p->fw_error_buf);\r
- }\r
-\r
-cmd_ret = THH_cmd_SYS_DIS(hob_p->cmd);\r
-if (cmd_ret != THH_CMD_STAT_OK) {\r
- if (cmd_ret == THH_CMD_STAT_EFATAL) {\r
- MTL_ERROR1(MT_FLFMT("THH_hob_create: FATAL ERROR in THH_cmd_SYS_DIS"));\r
- } else {\r
- MTL_ERROR1(MT_FLFMT("THH_hob_create: CMD_error in THH_cmd_SYS_DIS (%d)"), cmd_ret);\r
- }\r
-}\r
-cmd_err:\r
- THH_cmd_destroy(hob_p->cmd);\r
- \r
-err_free_hob:\r
- MOSAL_mutex_free(&(hob_p->mtx));\r
- FREE(hob_p);\r
- return (ret);\r
-}\r
-\r
-\r
-/*****************************************************************************\r
-******************************************************************************\r
-************** EXTERNALLY VISIBLE FUNCTIONS, WITH PROTOTYPES IN THH_HOB.H ****\r
-******************************************************************************\r
-*****************************************************************************/\r
-\r
-\r
-HH_ret_t THH_hob_get_ver_info ( /*IN*/ THH_hob_t hob, \r
- /*OUT*/ THH_ver_info_t *version_p )\r
-{\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (hob == NULL) {\r
- MTL_ERROR1("THH_hob_get_ver_info: ERROR : No device registered\n");\r
- return HH_EINVAL;\r
- }\r
- \r
- memcpy(version_p, &(hob->version_info), sizeof(THH_ver_info_t));\r
- return HH_OK;\r
-}\r
-\r
-\r
-HH_ret_t THH_hob_get_cmd_if ( /*IN*/ THH_hob_t hob, \r
- /*OUT*/ THH_cmd_t *cmd_if_p )\r
-{\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (hob == NULL) {\r
- MTL_ERROR1("THH_hob_get_cmd_if: ERROR : No device registered\n");\r
- return HH_EINVAL;\r
- }\r
-\r
-\r
- if (hob->cmd == THH_CMDIF_INVALID_HANDLE) {\r
- MTL_ERROR1("THH_hob_get_cmd_if: ERROR : HCA device has not yet been opened\n");\r
- return HH_EINVAL;\r
- }\r
-\r
- *cmd_if_p = hob->cmd;\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THH_hob_get_uldm ( /*IN*/ THH_hob_t hob, \r
- /*OUT*/ THH_uldm_t *uldm_p )\r
-{\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (hob == NULL) {\r
- MTL_ERROR1("THH_hob_get_uldm: ERROR : No device registered\n");\r
- return HH_EINVAL;\r
- }\r
-\r
-\r
- if (hob->uldm == (THH_uldm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_get_uldm: ERROR : HCA device has not yet been opened\n");\r
- return HH_EINVAL;\r
- }\r
-\r
- *uldm_p = hob->uldm;\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THH_hob_get_ddrmm ( /*IN*/ THH_hob_t hob, \r
- /*OUT*/ THH_ddrmm_t *ddrmm_p )\r
-{\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (hob == NULL) {\r
- MTL_ERROR1("THH_hob_get_ddrmm: ERROR : No device registered\n");\r
- return HH_EINVAL;\r
- }\r
-\r
-\r
- if (hob->ddrmm == (THH_ddrmm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_get_ddrmm: ERROR : HCA device has not yet been opened\n");\r
- return HH_EINVAL;\r
- }\r
-\r
- *ddrmm_p = hob->ddrmm;\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THH_hob_get_mrwm ( /*IN*/ THH_hob_t hob, \r
- /*OUT*/ THH_mrwm_t *mrwm_p )\r
-{\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (hob == NULL) {\r
- MTL_ERROR1("THH_hob_get_mrwm: ERROR : No device registered\n");\r
- return HH_EINVAL;\r
- }\r
-\r
-\r
- if (hob->mrwm == (THH_mrwm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_get_mrwm: ERROR : HCA device has not yet been opened\n");\r
- return HH_EINVAL;\r
- }\r
- \r
- *mrwm_p = hob->mrwm;\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THH_hob_get_qpm ( /*IN*/ THH_hob_t hob, \r
- /*OUT*/ THH_qpm_t *qpm_p )\r
-{\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (hob == NULL) {\r
- MTL_ERROR1("THH_hob_get_qpm: ERROR : No device registered\n");\r
- return HH_EINVAL;\r
- }\r
-\r
-\r
- if (hob->qpm == (THH_qpm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_get_qpm: ERROR : HCA device has not yet been opened\n");\r
- return HH_EINVAL;\r
- }\r
- \r
- *qpm_p = hob->qpm;\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THH_hob_get_cqm ( /*IN*/ THH_hob_t hob, \r
- /*OUT*/ THH_cqm_t *cqm_p )\r
-{\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (hob == NULL) {\r
- MTL_ERROR1("THH_hob_get_cqm: ERROR : No device registered\n");\r
- return HH_EINVAL;\r
- }\r
-\r
-\r
- if (hob->cqm == (THH_cqm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_get_cqm: ERROR : HCA device has not yet been opened\n");\r
- return HH_EINVAL;\r
- }\r
- \r
- *cqm_p = hob->cqm;\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THH_hob_get_eventp ( /*IN*/ THH_hob_t hob, \r
- /*OUT*/ THH_eventp_t *eventp_p )\r
-{\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (hob == NULL) {\r
- MTL_ERROR1("THH_hob_get_eventp: ERROR : No device registered\n");\r
- return HH_EINVAL;\r
- }\r
-\r
-\r
- if (hob->eventp== (THH_eventp_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_get_eventp: ERROR : HCA device has not yet been opened\n");\r
- return HH_EINVAL;\r
- }\r
- \r
- *eventp_p = hob->eventp;\r
- return HH_OK;\r
-}\r
-HH_ret_t THH_hob_get_udavm_info ( /*IN*/ THH_hob_t hob, \r
- /*OUT*/ THH_udavm_t *udavm_p,\r
- /*OUT*/ MT_bool *use_priv_udav,\r
- /*OUT*/ MT_bool *av_in_host_mem,\r
- /*OUT*/ VAPI_lkey_t *lkey ,\r
- /*OUT*/ u_int32_t *max_ah_num,\r
- /*OUT*/ MT_bool *hide_ddr)\r
-{\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (hob == NULL) {\r
- MTL_ERROR1("THH_hob_get_udavm_info: ERROR : No device registered\n");\r
- return HH_EINVAL;\r
- }\r
-\r
- *av_in_host_mem = (MT_bool) (hob->module_flags.av_in_host_mem);\r
-\r
- *use_priv_udav = hob->udavm_use_priv;\r
- *hide_ddr = (hob->ddr_props.dh ? TRUE : FALSE);\r
- *max_ah_num = hob->hca_capabilities.max_ah_num;\r
- if (!(hob->udavm_use_priv)) {\r
- return HH_OK;\r
- }\r
-\r
- if (hob->udavm == (THH_udavm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_get_udavm_info: ERROR : HCA device has not yet been opened\n");\r
- return HH_EINVAL;\r
- }\r
- \r
- *udavm_p = hob->udavm;\r
- *lkey = hob->udavm_lkey;\r
-\r
- return HH_OK;\r
-}\r
-\r
-\r
-HH_ret_t THH_hob_get_hca_hndl ( /*IN*/ THH_hob_t hob, \r
- /*OUT*/ HH_hca_hndl_t *hca_hndl_p )\r
-{\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (hob == NULL) {\r
- MTL_ERROR1("THH_hob_get_hca_hndl: ERROR : No device registered\n");\r
- return HH_EINVAL;\r
- }\r
- \r
- *hca_hndl_p = hob->hh_hca_hndl;\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THH_hob_check_qp_init_attrs ( /*IN*/ THH_hob_t hob,\r
- /*IN*/ HH_qp_init_attr_t * init_attr_p,\r
- /*IN*/ MT_bool is_special_qp )\r
-{\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (hob == NULL) {\r
- MTL_ERROR1("THH_hob_get_check_qp_init_attrs: ERROR : No device registered\n");\r
- return HH_EINVAL;\r
- }\r
-\r
-\r
- if (init_attr_p == NULL) {\r
- MTL_ERROR1("THH_hob_get_check_qp_init_attrs: ERROR : null attributes\n");\r
- return HH_EINVAL;\r
- }\r
-\r
- if (init_attr_p->qp_cap.max_oust_wr_rq > hob->hca_capabilities.max_qp_ous_wr ||\r
- init_attr_p->qp_cap.max_oust_wr_sq > hob->hca_capabilities.max_qp_ous_wr){\r
- MTL_ERROR1("%s : max outs work requests more than HCA maximum\n", __func__);\r
- return HH_E2BIG_WR_NUM;\r
- }\r
-\r
- if (is_special_qp || init_attr_p->ts_type != VAPI_TS_RD) {\r
- if (init_attr_p->qp_cap.max_sg_size_rq > hob->hca_capabilities.max_num_sg_ent ||\r
- init_attr_p->qp_cap.max_sg_size_sq > hob->hca_capabilities.max_num_sg_ent) {\r
- MTL_ERROR1("%s : max s/g list size more than HCA maximum\n", __func__);\r
- return HH_E2BIG_SG_NUM;\r
- }\r
- } else {\r
- /* is RD */\r
- if (init_attr_p->qp_cap.max_sg_size_rq > hob->hca_capabilities.max_num_sg_ent_rd ||\r
- init_attr_p->qp_cap.max_sg_size_sq > hob->hca_capabilities.max_num_sg_ent_rd) {\r
- MTL_ERROR1("%s : max s/g list size more than HCA maximum\n", __func__);\r
- return HH_E2BIG_SG_NUM;\r
- } \r
- }\r
- return HH_OK;\r
-}\r
-\r
-/* Used in restarting HCA on fatal error, in function THH_hob_restart */\r
-HH_ret_t THH_hob_get_init_params(/*IN*/ THH_hob_t thh_hob_p, \r
- /*OUT*/ THH_hw_props_t *hw_props_p,\r
- /*OUT*/ u_int32_t *hca_seq_num,\r
- /*OUT*/ THH_module_flags_t *mod_flags)\r
-{\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: ERROR : No device registered"), __func__); \r
- return HH_EAGAIN;\r
- }\r
- memcpy(hw_props_p, &thh_hob_p->hw_props, sizeof(THH_hw_props_t));\r
- *hca_seq_num = thh_hob_p->hca_seq_num;\r
- memcpy(mod_flags, &thh_hob_p->module_flags, sizeof(THH_module_flags_t));\r
- return HH_OK;\r
-}\r
-static HH_ret_t THH_hob_halt_hca(/*IN*/ THH_hob_t hob)\r
-{\r
-#ifdef SIMULATE_HALT_HCA\r
- THH_cmd_CLOSE_IB(hob->cmd,1);\r
- THH_cmd_CLOSE_IB(hob->cmd,2);\r
- THH_cmd_CLOSE_HCA(hob->cmd, FALSE);\r
- THH_cmd_SYS_DIS(hob->cmd);\r
-#else\r
- THH_cmd_status_t stat;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- stat = THH_cmd_CLOSE_HCA(hob->cmd, TRUE); // HALT the HCA\r
- MTL_ERROR1(MT_FLFMT("%s: HALT HCA returned 0x%x"), __func__,stat); \r
-#endif\r
- return HH_OK;\r
-}\r
-\r
-static VAPI_event_syndrome_t get_fatal_err_syndrome(THH_hob_t hob) \r
-{\r
- u_int32_t temp;\r
- int i;\r
- \r
- if ((hob->fw_error_buf_start_va != (MT_virt_addr_t)(MT_ulong_ptr_t) NULL) && \r
- (hob->fw_error_buf != NULL) && \r
- (hob->fw_props.error_buf_size > 0) ) {\r
- MOSAL_MMAP_IO_READ_BUF_DWORD(hob->fw_error_buf_start_va,\r
- hob->fw_error_buf,hob->fw_props.error_buf_size);\r
- /* check for non-zero data in fw catastrophic error buffer */\r
- temp = 0;\r
- for (i = 0; i < (int) hob->fw_props.error_buf_size; i++) {\r
- temp |= hob->fw_error_buf[i];\r
- }\r
- if (temp == 0) {\r
- return VAPI_CATAS_ERR_GENERAL; \r
- } else {\r
- /* Have non-zero data. print out the syndrome details, and return general category */\r
- for (i = 0; i < (int) hob->fw_props.error_buf_size; i++) {\r
- MTL_ERROR1(MT_FLFMT("get_fatal_err_syndrome: FW CATASTR ERRBUF[%d] = 0x%x"),\r
- i, MOSAL_be32_to_cpu(hob->fw_error_buf[i]));\r
- }\r
- switch( (MOSAL_be32_to_cpu(hob->fw_error_buf[0])>>24) & 0xFF) {\r
- case TAVOR_IF_EV_CATAS_ERR_FW_INTERNAL_ERR:\r
- return VAPI_CATAS_ERR_FW_INTERNAL;\r
- case TAVOR_IF_EV_CATAS_ERR_MISBEHAVED_UAR_PAGE:\r
- return VAPI_CATAS_ERR_MISBEHAVED_UAR_PAGE;\r
- case TAVOR_IF_EV_CATAS_ERR_UPLINK_BUS_ERR:\r
- return VAPI_CATAS_ERR_UPLINK_BUS_ERR;\r
- case TAVOR_IF_EV_CATAS_ERR_HCA_DDR_DATA_ERR:\r
- return VAPI_CATAS_ERR_HCA_DDR_DATA_ERR;\r
- case TAVOR_IF_EV_CATAS_ERR_INTERNAL_PARITY_ERR:\r
- return VAPI_CATAS_ERR_INTERNAL_PARITY_ERR;\r
- default:\r
- return VAPI_CATAS_ERR_GENERAL; \r
- }\r
- }\r
- } else {\r
- /* no access to the fw cat error buffer */\r
- return VAPI_CATAS_ERR_GENERAL; \r
- }\r
-}\r
-/****************************************************************************************\r
- * name: MGT_HOB_rcv\r
- * function: handles receive channel listening \r
- * args:\r
- * returns:\r
- * descr: This procedure is spawned as a thread main routine .\r
- * posts the initial receive buffers, then handles the completion queue polling\r
- * and data recording of Completion Queue events (the FIFO) for a test session\r
- ****************************************************************************************/\r
-\r
-HH_ret_t THH_hob_fatal_error(/*IN*/ THH_hob_t hob,\r
- /*IN*/ THH_fatal_err_t fatal_err_type,\r
- /*IN*/ VAPI_event_syndrome_t syndrome)\r
-{\r
-#ifndef __DARWIN__\r
- THH_cmd_t cmd_if;\r
- THH_eventp_t eventp;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- FUNC_IN;\r
- MTL_DEBUG1(MT_FLFMT("%s: device=%s, err_type=%d, syndrome=%d"), __func__, \r
- hob->dev_name, fatal_err_type, syndrome);\r
-\r
- if (hob == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: ERROR : No device registered"), __func__); \r
- MT_RETURN(HH_EAGAIN);\r
- }\r
- \r
- /* make sure that only one invocation is allowed */\r
- MOSAL_spinlock_dpc_lock(&hob->fatal_spl);\r
- if ((hob->thh_state & THH_STATE_HAVE_ANY_FATAL) != 0) {\r
- /* already in FATAL state */\r
- MTL_DEBUG4(MT_FLFMT("%s: already in FATAL state"), __func__); \r
- MOSAL_spinlock_unlock(&hob->fatal_spl);\r
- MT_RETURN(HH_OK);\r
- }\r
-\r
- MTL_ERROR1(MT_FLFMT("%s: device=%s, err_type=%d, syndrome=%d"), __func__, \r
- hob->dev_name, fatal_err_type, syndrome);\r
- \r
- switch(fatal_err_type) {\r
- /* get syndrome from iomapped firmware memory */\r
- case THH_FATAL_MASTER_ABORT: /* detected master abort */\r
- hob->fatal_syndrome = VAPI_CATAS_ERR_MASTER_ABORT;\r
- break;\r
- case THH_FATAL_GOBIT: /* GO bit of HCR remains set (i.e., stuck) */\r
- hob->fatal_syndrome = VAPI_CATAS_ERR_GO_BIT;\r
- break;\r
- case THH_FATAL_CMD_TIMEOUT: /* timeout on a command execution */\r
- hob->fatal_syndrome = VAPI_CATAS_ERR_CMD_TIMEOUT;\r
- break;\r
- case THH_FATAL_EQ_OVF: /* an EQ has overflowed */\r
- hob->fatal_syndrome = VAPI_CATAS_ERR_EQ_OVERFLOW;\r
- break;\r
- case THH_FATAL_EVENT: /* firmware has generated a LOCAL CATASTROPHIC ERR event */\r
- hob->fatal_syndrome = get_fatal_err_syndrome(hob);\r
- break;\r
- case THH_FATAL_CR: /* unexpected read from CR-space */\r
- hob->fatal_syndrome = VAPI_CATAS_ERR_EQ_OVERFLOW;\r
- break;\r
- case THH_FATAL_TOKEN: /* invalid token on command completion */\r
- hob->fatal_syndrome = VAPI_CATAS_ERR_FATAL_TOKEN;\r
- break;\r
- case THH_FATAL_EXTERNAL: /* invalid token on command completion */\r
- hob->fatal_syndrome = VAPI_CATAS_ERR_FATAL_EXTERNAL;\r
- break;\r
- case THH_FATAL_NONE: \r
- default:\r
- hob->fatal_syndrome = VAPI_CATAS_ERR_GENERAL;\r
- }\r
-\r
- MTL_ERROR1(MT_FLFMT("%s: Fatal Event Syndrome = %s (%d)"), \r
- __func__,VAPI_event_syndrome_sym(hob->fatal_syndrome), hob->fatal_syndrome);\r
-\r
- if (hob->thh_state == THH_STATE_RUNNING) {\r
- /* make use of thread to perform HALT and signal user apps */\r
- hob->thh_state |= THH_STATE_FATAL_START;\r
- } else {\r
- /* creating, opening, closing, or destroying HCA.\r
- * Indicate HCA_HALTED directly.\r
- */\r
- hob->thh_state |= THH_STATE_FATAL_HCA_HALTED;\r
- }\r
- MOSAL_spinlock_unlock(&hob->fatal_spl);\r
-\r
- /* notify cmd and eventp objects, if they exist */\r
- if (THH_hob_get_cmd_if(hob, &cmd_if) == HH_OK) {\r
- THH_cmd_notify_fatal(cmd_if, fatal_err_type);\r
- }\r
- \r
- if (THH_hob_get_eventp(hob,&eventp) == HH_OK) {\r
- THH_eventp_notify_fatal(eventp, fatal_err_type);\r
- }\r
-\r
- /* now, signal the fatal error thread, ONLY IF WE WERE IN RUNNING STATE */ \r
- if ((hob->thh_state & THH_STATE_RUNNING) != 0) {\r
- hob->fatal_thread_obj.have_fatal = TRUE;\r
- MTL_TRACE1(MT_FLFMT("%s: signalling fatal thread"), __func__); \r
- MOSAL_syncobj_signal(&hob->fatal_thread_obj.fatal_err_sync);\r
- }\r
-\r
-#endif /* not defined __DARWIN__ - TODO in darwin, implement the fatal error handling */\r
- MT_RETURN(HH_OK);\r
-}\r
-\r
-HH_ret_t THH_hob_get_state(THH_hob_t thh_hob_p, THH_hob_state_t *fatal_state)\r
-{\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: ERROR : No device registered"), __func__); \r
- return HH_EAGAIN;\r
- }\r
- \r
- if (fatal_state == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: ERROR : NULL fatal_state parameter"), __func__); \r
- return HH_EINVAL;\r
- }\r
-\r
- MOSAL_spinlock_dpc_lock(&thh_hob_p->fatal_spl);\r
- *fatal_state = thh_hob_p->thh_state;\r
- MOSAL_spinlock_unlock(&thh_hob_p->fatal_spl);\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THH_hob_get_fatal_syncobj(THH_hob_t thh_hob_p, MOSAL_syncobj_t *syncobj)\r
-{\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: ERROR : No device registered"), __func__); \r
- return HH_EAGAIN;\r
- }\r
- \r
- if (syncobj == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: ERROR : NULL syncobj return parameter"), __func__); \r
- return HH_EINVAL;\r
- }\r
-\r
- *syncobj = thh_hob_p->thh_fatal_complete_syncobj;\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THH_hob_wait_if_fatal(THH_hob_t thh_hob_p, MT_bool *had_fatal)\r
-{\r
- THH_hob_state_t state;\r
-\r
- FUNC_IN;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: Received NULL HOB pointer"), __func__); \r
- *had_fatal = FALSE;\r
- MT_RETURN(HH_OK);\r
- }\r
-\r
- /*get fatal state value */\r
- MOSAL_spinlock_dpc_lock(&(thh_hob_p->fatal_spl));\r
- state = thh_hob_p->thh_state;\r
- MOSAL_spinlock_unlock(&(thh_hob_p->fatal_spl));\r
- \r
- MTL_DEBUG4(MT_FLFMT("%s: FATAL STATE=%d"), __func__, state); \r
-\r
- if ((state & THH_STATE_HAVE_ANY_FATAL) == 0) {\r
- *had_fatal = FALSE;\r
- MT_RETURN(HH_OK);\r
- }\r
- \r
- /* We were in running state. Wait for fatal thread to complete HCA HALT */\r
- if ((state & THH_STATE_FATAL_START) != 0) {\r
- MOSAL_syncobj_waiton_ui(&thh_hob_p->thh_fatal_complete_syncobj, 10000000);\r
- }\r
- \r
- /* We are in the FATAL_HCA_HALTED compound state */\r
- *had_fatal = TRUE;\r
- MT_RETURN(HH_OK);\r
-\r
-}\r
-\r
-HH_ret_t THH_hob_restart(/*IN*/ HH_hca_hndl_t hca_hndl)\r
-{\r
- THH_hw_props_t hw_props;\r
- u_int32_t hca_seq_num;\r
- THH_module_flags_t mod_flags;\r
- THH_hob_t thh_hob_p;\r
- HH_hca_hndl_t new_hh_hca_hndl; \r
- HH_ret_t rc;\r
- \r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- FUNC_IN;\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1(MT_FLFMT("%s: NOT IN TASK CONTEXT"), __func__); \r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: ERROR : Invalid HCA handle"), __func__); \r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: ERROR : no device registered"), __func__); \r
- return HH_EAGAIN;\r
- }\r
-\r
- if ((thh_hob_p->thh_state & THH_STATE_FATAL_HCA_HALTED) == 0) {\r
- MTL_ERROR1(MT_FLFMT("%s: HCA is not halted (state 0x%x)"), __func__, thh_hob_p->thh_state); \r
- return HH_ERR;\r
- }\r
-\r
- THH_hob_get_init_params(thh_hob_p, &hw_props, &hca_seq_num, &mod_flags);\r
-\r
- /* PCI reset is done in destroy, if have catastrophic error */\r
- rc = THH_hob_destroy(hca_hndl);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: cannot destroy old HOB (ret=%d)"), __func__, rc); \r
- }\r
-\r
- rc = THH_hob_create(&hw_props,hca_seq_num,&mod_flags,&new_hh_hca_hndl);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: cannot create new HOB (ret=%d)"), __func__, rc); \r
- }\r
- return rc;\r
-}\r
-\r
-/*****************************************************************************\r
-******************************************************************************\r
-************** PASS-THROUGH FUNCTIONS ********************************** ****\r
-******************************************************************************\r
-*****************************************************************************/\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_alloc_ul_res <==> THH_uldm_alloc_ul_res\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_alloc_ul_res(HH_hca_hndl_t hca_hndl,\r
- MOSAL_protection_ctx_t prot_ctx,\r
- void *hca_ul_resources_p)\r
-{\r
- THH_hca_ul_resources_t* res = (THH_hca_ul_resources_t *)hca_ul_resources_p;\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_alloc_ul_res: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_alloc_ul_res : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- /* Need to see that uldm object has been allocated. Then, need to invoke\r
- * the alloc_ul_resources method of the uldm here. \r
- * NOTE: may want the constructor to already pre-allocate the ul resources based upon\r
- * configuration info obtained via query.\r
- */\r
- memset(res, 0, sizeof(THH_hca_ul_resources_t));\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_alloc_ul_res: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
- if (thh_hob_p->uldm == (THH_uldm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_alloc_ul_res: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- /* Set THH_hob's information in given hca_ul_res_p buffer */\r
- ((THH_hca_ul_resources_t*)hca_ul_resources_p)->hh_hca_hndl= hca_hndl;\r
- memcpy(&(((THH_hca_ul_resources_t*)hca_ul_resources_p)->version),\r
- &(thh_hob_p->version_info),sizeof(THH_ver_info_t));\r
- ((THH_hca_ul_resources_t*)hca_ul_resources_p)->priv_ud_av = thh_hob_p->profile.use_priv_udav;\r
- ((THH_hca_ul_resources_t*)hca_ul_resources_p)->log2_mpt_size = (u_int32_t)thh_hob_p->profile.log2_max_mpt_entries;\r
- ((THH_hca_ul_resources_t*)hca_ul_resources_p)->av_ddr_base = thh_hob_p->av_ddr_base;\r
- ((THH_hca_ul_resources_t*)hca_ul_resources_p)->av_host_base = thh_hob_p->av_host_base;\r
- ((THH_hca_ul_resources_t*)hca_ul_resources_p)->max_qp_ous_wr= thh_hob_p->hca_capabilities.max_qp_ous_wr;\r
- ((THH_hca_ul_resources_t*)hca_ul_resources_p)->max_srq_ous_wr= thh_hob_p->hca_capabilities.max_wqe_per_srq;\r
- ((THH_hca_ul_resources_t*)hca_ul_resources_p)->max_num_sg_ent= thh_hob_p->hca_capabilities.max_num_sg_ent;\r
- ((THH_hca_ul_resources_t*)hca_ul_resources_p)->max_num_sg_ent_srq= thh_hob_p->hca_capabilities.max_srq_sentries;\r
- ((THH_hca_ul_resources_t*)hca_ul_resources_p)->max_num_sg_ent_rd= thh_hob_p->hca_capabilities.max_num_sg_ent_rd;\r
- ((THH_hca_ul_resources_t*)hca_ul_resources_p)->max_num_ent_cq= thh_hob_p->hca_capabilities.max_num_ent_cq;\r
-\r
- /* Invoke THH_uldm in order to get a UAR resource */\r
- return THH_uldm_alloc_ul_res(thh_hob_p->uldm, prot_ctx, \r
- (THH_hca_ul_resources_t *)hca_ul_resources_p);\r
-} /* THH_alloc_ul_resources */\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_free_ul_res <==> THH_uldm_free_ul_res\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_free_ul_res(HH_hca_hndl_t hca_hndl,\r
- void *hca_ul_resources_p)\r
-{\r
- THH_hca_ul_resources_t* res = (THH_hca_ul_resources_t *)hca_ul_resources_p;\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_free_ul_res: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_free_ul_res : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- /* Need to see that uldm object has been allocated. Then, need to invoke\r
- * the alloc_ul_resources method of the uldm here. \r
- * NOTE: may want the constructor to already pre-allocate the ul resources based upon\r
- * configuration info obtained via query.\r
- */\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_free_ul_res: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- if (thh_hob_p->uldm == (THH_uldm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_free_ul_res: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_uldm_free_ul_res(thh_hob_p->uldm, res);\r
-} /* THH_free_ul_resources */\r
-\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_alloc_pd <==> THH_uldm_alloc_pd\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_alloc_pd(HH_hca_hndl_t hca_hndl, \r
- MOSAL_protection_ctx_t prot_ctx, \r
- void * pd_ul_resources_p,\r
- HH_pd_hndl_t *pd_num_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
- HH_ret_t ret;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_alloc_pd: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_alloc_pd : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_alloc_pd: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->uldm == (THH_uldm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_alloc_pd: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- ret = THH_uldm_alloc_pd(thh_hob_p->uldm, prot_ctx, \r
- (THH_pd_ul_resources_t *)pd_ul_resources_p, pd_num_p);\r
-// MTL_DEBUG4("THH_hob_alloc_pd: ret = %d\n", ret);\r
- return ret;\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_free_pd <==> THH_uldm_free_pd\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_free_pd(HH_hca_hndl_t hca_hndl, HH_pd_hndl_t pd_num)\r
-{\r
- u_int32_t max_pd;\r
- THH_hob_t thh_hob_p;\r
- HH_ret_t rc = HH_OK;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_free_pd: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR; \r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_free_pd : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL; \r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_free_pd: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- max_pd = (1 << thh_hob_p->dev_lims.log_max_pd);\r
- if (pd_num > max_pd - 1) {\r
- MTL_ERROR1("THH_hob_free_pd: ERROR : PD number (%d) is greater than max allowed (%d)\n", pd_num, max_pd);\r
- return HH_EAGAIN;\r
- }\r
-\r
- if (thh_hob_p->uldm == (THH_uldm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_free_pd: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
- \r
- rc = THH_uldm_free_pd(thh_hob_p->uldm, pd_num);\r
- return rc; \r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_alloc_rdd <==> THH_eecm_alloc_rdd\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_alloc_rdd(HH_hca_hndl_t hh_dev_p, \r
- HH_rdd_hndl_t *rdd_p)\r
-{\r
-#if 0\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_alloc_rdd: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_alloc_rdd : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_alloc_rdd: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->eecm == (THH_eecm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_alloc_rdd: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_eecm_alloc_rdd(thh_hob_p->uldm, rdd_p);\r
-#else\r
- return HH_ENOSYS;\r
-#endif\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_free_rdd <==> THH_eecm_free_rdd\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_free_rdd(HH_hca_hndl_t hh_dev_p, HH_rdd_hndl_t rdd)\r
-{\r
-#if 0\r
- THH_hob_t thh_hob_p;\r
- HH_ret_t rc = HH_OK;\r
-\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_free_rdd: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_free_rdd : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_free_rdd: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
-\r
- if (thh_hob_p->eecm == (THH_eecm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_free_rdd: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- rc = THH_eecm_free_rdd(thh_hob_p->uldm, rdd);\r
- return rc;\r
-#else\r
- return HH_ENOSYS;\r
-#endif\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_create_ud_av <==> THH_udavm_create_av\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_create_ud_av(HH_hca_hndl_t hca_hndl,\r
- HH_pd_hndl_t pd,\r
- VAPI_ud_av_t *av_p, \r
- HH_ud_av_hndl_t *ah_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_create_ud_av: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_create_ud_av : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_create_ud_av: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->udavm == (THH_udavm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_create_ud_av: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_udavm_create_av(thh_hob_p->udavm, pd, av_p, ah_p);\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_modify_ud_av <==> THH_udavm_modify_av\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_modify_ud_av(HH_hca_hndl_t hca_hndl, \r
- HH_ud_av_hndl_t ah,\r
- VAPI_ud_av_t *av_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_modify_ud_av: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_modify_ud_av : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_modify_ud_av: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->udavm == (THH_udavm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_modify_ud_av: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_udavm_modify_av(thh_hob_p->udavm, ah, av_p);\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_query_ud_av <==> THH_udavm_query_av\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_query_ud_av(HH_hca_hndl_t hca_hndl, \r
- HH_ud_av_hndl_t ah,\r
- VAPI_ud_av_t *av_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_query_ud_av: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_query_ud_av : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_query_ud_av: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->udavm == (THH_udavm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_query_ud_av: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_udavm_query_av(thh_hob_p->udavm, ah, av_p);\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_destroy_ud_av <==> THH_udavm_destroy_av\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_destroy_ud_av(HH_hca_hndl_t hca_hndl, \r
- HH_ud_av_hndl_t ah)\r
-{\r
- THH_hob_t thh_hob_p;\r
- HH_ret_t rc = HH_OK;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_destroy_ud_av: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_destroy_ud_av : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_destroy_ud_av: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
-\r
- if (thh_hob_p->udavm == (THH_udavm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_destroy_ud_av: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
- rc = THH_udavm_destroy_av(thh_hob_p->udavm, ah);\r
- return rc;\r
-}\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_register_mr <==> THH_mrwm_register_mr\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_register_mr(HH_hca_hndl_t hca_hndl, \r
- HH_mr_t *mr_props_p, \r
- VAPI_lkey_t *lkey_p, \r
- IB_rkey_t *rkey_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_register_mr: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_register_mr : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_register_mr: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->mrwm == (THH_mrwm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_register_mr: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_mrwm_register_mr(thh_hob_p->mrwm, mr_props_p, lkey_p, rkey_p);\r
-}\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_reregister_mr <==> THH_mrwm_reregister_mr\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_reregister_mr(HH_hca_hndl_t hca_hndl,\r
- VAPI_lkey_t lkey, \r
- VAPI_mr_change_t change_mask,\r
- HH_mr_t *mr_props_p, \r
- VAPI_lkey_t* lkey_p, \r
- IB_rkey_t *rkey_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_reregister_mr: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_reregister_mr : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_reregister_mr: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->mrwm == (THH_mrwm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_reregister_mr: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_mrwm_reregister_mr(thh_hob_p->mrwm, lkey, change_mask, mr_props_p,lkey_p, rkey_p);\r
-}\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_register_smr <==> THH_mrwm_register_smr\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_register_smr(HH_hca_hndl_t hca_hndl, \r
- HH_smr_t *mr_props_p, \r
- VAPI_lkey_t *lkey_p, \r
- IB_rkey_t *rkey_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_register_smr: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_register_smr : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_register_smr: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->mrwm == (THH_mrwm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_register_smr: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_mrwm_register_smr(thh_hob_p->mrwm, mr_props_p, lkey_p, rkey_p);\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_query_mr <==> THH_mrwm_query_mr\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_query_mr(HH_hca_hndl_t hca_hndl, \r
- VAPI_lkey_t lkey, \r
- HH_mr_info_t *mr_info_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_query_mr: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_query_mr : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_query_mr: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->mrwm == (THH_mrwm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_query_mr: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_mrwm_query_mr(thh_hob_p->mrwm, lkey, mr_info_p);\r
-}\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_deregister_mr <==> THH_mrwm_deregister_mr\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_deregister_mr(HH_hca_hndl_t hca_hndl, \r
- VAPI_lkey_t lkey)\r
-{\r
- THH_hob_t thh_hob_p;\r
- HH_ret_t rc;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_deregister_mr: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_deregister_mr : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_deregister_mr: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
-\r
- if (thh_hob_p->mrwm == (THH_mrwm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_deregister_mr: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- rc = THH_mrwm_deregister_mr(thh_hob_p->mrwm, lkey);\r
- return rc;\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_alloc_mw <==> THH_mrwm_alloc_mw\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_alloc_mw(HH_hca_hndl_t hca_hndl, \r
- HH_pd_hndl_t pd,\r
- IB_rkey_t *initial_rkey_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_alloc_mw: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_alloc_mw : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
-\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_alloc_mw: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->mrwm == (THH_mrwm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_alloc_mw: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_mrwm_alloc_mw(thh_hob_p->mrwm, pd, initial_rkey_p);\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_query_mw <==> THH_mrwm_query_mw\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_query_mw(HH_hca_hndl_t hca_hndl,\r
- IB_rkey_t initial_rkey,\r
- IB_rkey_t *current_rkey_p,\r
- HH_pd_hndl_t *pd_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_query_mw: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_query_mw : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_query_mw: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->mrwm == (THH_mrwm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_query_mw: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- MTL_TRACE1("%s: -KL- called for key 0x%x", __func__,initial_rkey);\r
- return THH_mrwm_query_mw(thh_hob_p->mrwm, initial_rkey, current_rkey_p, pd_p);\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_free_mw <==> THH_mrwm_free_mw\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_free_mw(HH_hca_hndl_t hca_hndl, \r
- IB_rkey_t initial_rkey)\r
-{\r
- THH_hob_t thh_hob_p;\r
- HH_ret_t rc;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_free_mw: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_free_mw : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_free_mw: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
-\r
- if (thh_hob_p->mrwm == (THH_mrwm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_free_mw: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- rc = THH_mrwm_free_mw(thh_hob_p->mrwm, initial_rkey);\r
- return rc;\r
-}\r
-\r
-\r
- /* Fast Memory Regions */\r
- /***********************/\r
-/******************************************************************************\r
- * Function: THH_hob_create_cq <==> THH_mrwm_alloc_fmr\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_alloc_fmr(HH_hca_hndl_t hca_hndl,\r
- HH_pd_hndl_t pd,\r
- VAPI_mrw_acl_t acl, \r
- MT_size_t max_pages, /* Maximum number of pages that can be mapped using this region */\r
- u_int8_t log2_page_sz, /* Fixed page size for all maps on a given FMR */\r
- VAPI_lkey_t* last_lkey_p) /* To be used as the initial FMR handle */\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_alloc_fmr : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_alloc_fmr: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->mrwm == (THH_mrwm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_alloc_fmr: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- if (thh_hob_p->ddr_props.dh == TRUE) {\r
- /* Must hide DDR memory. alloc fmr not supported */\r
- MTL_ERROR1("THH_hob_alloc_fmr: Device is operating in HIDE_DDR mode. Cannot alloc fmr\n");\r
- return HH_ENOSYS;\r
- }\r
-\r
- return THH_mrwm_alloc_fmr(thh_hob_p->mrwm,pd,acl,max_pages,log2_page_sz,last_lkey_p);\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_map_fmr <==> THH_mrwm_map_fmr\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_map_fmr(HH_hca_hndl_t hca_hndl,\r
- VAPI_lkey_t last_lkey,\r
- EVAPI_fmr_map_t* map_p,\r
- VAPI_lkey_t* lkey_p,\r
- IB_rkey_t* rkey_p)\r
-\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_map_fmr : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_map_fmr: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->mrwm == (THH_mrwm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_map_fmr: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_mrwm_map_fmr(thh_hob_p->mrwm,last_lkey,map_p,lkey_p,rkey_p);\r
-}\r
- \r
-/******************************************************************************\r
- * Function: THH_hob_unmap_fmr <==> THH_mrwm_unmap_fmr\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_unmap_fmr(HH_hca_hndl_t hca_hndl,\r
- u_int32_t num_of_fmrs_to_unmap,\r
- VAPI_lkey_t* last_lkeys_array)\r
-\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_unmap_fmr : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_unmap_fmr: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->mrwm == (THH_mrwm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_unmap_fmr: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_mrwm_unmap_fmr(thh_hob_p->mrwm,num_of_fmrs_to_unmap,last_lkeys_array);\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_free_fmr <==> THH_mrwm_free_fmr\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_free_fmr(HH_hca_hndl_t hca_hndl,\r
- VAPI_lkey_t last_lkey) /* as returned on last successful mapping operation */\r
-\r
-{\r
- THH_hob_t thh_hob_p;\r
- HH_ret_t rc = HH_OK;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_free_fmr : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_free_fmr: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
-\r
- if (thh_hob_p->mrwm == (THH_mrwm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_free_fmr: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- rc = THH_mrwm_free_fmr(thh_hob_p->mrwm,last_lkey);\r
- return rc;\r
-}\r
-\r
- \r
- /******************************************************************************\r
- * Function: THH_hob_create_cq <==> THH_cqm_create_cq\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_create_cq(HH_hca_hndl_t hca_hndl, \r
- MOSAL_protection_ctx_t user_prot_context, \r
- void *cq_ul_resources_p,\r
- HH_cq_hndl_t *cq_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_create_cq: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_create_cq : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_create_cq: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
- if (thh_hob_p->cqm == (THH_cqm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_create_cq: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_cqm_create_cq(thh_hob_p->cqm, user_prot_context, thh_hob_p->compl_eq,\r
- thh_hob_p->ib_eq, \r
- (THH_cq_ul_resources_t*)cq_ul_resources_p, cq_p);\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_resize_cq <==> THH_cqm_modify_cq\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_resize_cq(HH_hca_hndl_t hca_hndl, \r
- HH_cq_hndl_t cq,\r
- void *cq_ul_resources_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_resize_cq: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_resize_cq : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_resize_cq: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->cqm == (THH_cqm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_resize_cq: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_cqm_resize_cq(thh_hob_p->cqm, cq, (THH_cq_ul_resources_t*)cq_ul_resources_p);\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_query_cq <==> THH_cqm_query_cq\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_query_cq(HH_hca_hndl_t hca_hndl, \r
- HH_cq_hndl_t cq,\r
- VAPI_cqe_num_t *num_o_cqes_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_query_cq: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_query_cq : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_query_cq: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->cqm == (THH_cqm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_query_cq: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_cqm_query_cq(thh_hob_p->cqm, cq, num_o_cqes_p);\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_destroy_cq <==> THH_cqm_destroy_cq\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_destroy_cq(HH_hca_hndl_t hca_hndl, \r
- HH_cq_hndl_t cq)\r
-{\r
- THH_hob_t thh_hob_p;\r
- HH_ret_t rc = HH_OK;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_destroy_cq: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_destroy_cq : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_destroy_cq: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
-\r
- if (thh_hob_p->cqm == (THH_cqm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_destroy_cq: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- rc = THH_cqm_destroy_cq(thh_hob_p->cqm, cq);\r
- return rc;\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_create_qp <==> THH_qpm_create_qp\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_create_qp(HH_hca_hndl_t hca_hndl, \r
- HH_qp_init_attr_t *init_attr_p, \r
- void *qp_ul_resources_p, \r
- IB_wqpn_t *qpn_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
- HH_ret_t rc = HH_OK;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_create_qp: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_create_qp : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_create_qp: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->qpm == (THH_qpm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_create_qp: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- if ((rc=THH_hob_check_qp_init_attrs(thh_hob_p,init_attr_p,FALSE)) != HH_OK) {\r
- MTL_ERROR1("THH_hob_create_qp: ERROR : requested capabilities exceed HCA limits\n");\r
- return rc;\r
- }\r
-\r
- return THH_qpm_create_qp(thh_hob_p->qpm, init_attr_p, 0, (THH_qp_ul_resources_t*)qp_ul_resources_p, qpn_p);\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_get_special_qp <==> THH_qpm_get_special_qp\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_get_special_qp(HH_hca_hndl_t hca_hndl,\r
- VAPI_special_qp_t qp_type,\r
- IB_port_t port, \r
- HH_qp_init_attr_t *init_attr_p, \r
- void *qp_ul_resources_p, \r
- IB_wqpn_t *sqp_hndl_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
- HH_ret_t rc = HH_OK;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_get_special_qp: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_get_special_qp : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_get_special_qp: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
- if (thh_hob_p->qpm == (THH_qpm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_get_special_qp: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- if ((rc=THH_hob_check_qp_init_attrs(thh_hob_p,init_attr_p,TRUE)) != HH_OK) {\r
- MTL_ERROR1("THH_hob_get_special_qp: ERROR : requested capabilities exceed HCA limits\n");\r
- return rc;\r
- }\r
-\r
- return THH_qpm_get_special_qp(thh_hob_p->qpm, qp_type, port, init_attr_p, (THH_qp_ul_resources_t*)qp_ul_resources_p, sqp_hndl_p);\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_modify_qp <==> THH_qpm_modify_qp\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_modify_qp(HH_hca_hndl_t hca_hndl, \r
- IB_wqpn_t qpn, \r
- VAPI_qp_state_t cur_qp_state,\r
- VAPI_qp_attr_t *qp_attr_p,\r
- VAPI_qp_attr_mask_t *qp_attr_mask_p)\r
-{\r
- HH_ret_t ret;\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_modify_qp: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_modify_qp : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_modify_qp: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
- if (thh_hob_p->qpm == (THH_qpm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_modify_qp: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
- \r
- ret = THH_qpm_modify_qp(thh_hob_p->qpm, qpn, cur_qp_state, qp_attr_p, qp_attr_mask_p);\r
-\r
- return ret;\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_query_qp <==> THH_qpm_query_qp\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_query_qp(HH_hca_hndl_t hca_hndl, \r
- IB_wqpn_t qpn, \r
- VAPI_qp_attr_t *qp_attr_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_query_qp: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_query_qp : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_query_qp: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->qpm == (THH_qpm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_query_qp: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_qpm_query_qp(thh_hob_p->qpm, qpn, qp_attr_p);\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_destroy_qp <==> THH_qpm_destroy_qp\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_destroy_qp(HH_hca_hndl_t hca_hndl, \r
- IB_wqpn_t qpn)\r
-{\r
- THH_hob_t thh_hob_p;\r
- HH_ret_t rc = HH_OK;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_destroy_qp: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_destroy_qp : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_destroy_qp: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
-\r
- if (thh_hob_p->qpm == (THH_qpm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_destroy_qp: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- rc = THH_qpm_destroy_qp(thh_hob_p->qpm, qpn);\r
- return rc;\r
-}\r
-\r
-/* HH_create_srq */\r
-HH_ret_t THH_hob_create_srq(HH_hca_hndl_t hca_hndl, HH_pd_hndl_t pd, void *srq_ul_resources_p, \r
- HH_srq_hndl_t *srq_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("%s: NOT IN TASK CONTEXT)\n", __func__);\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("%s : ERROR : Invalid HCA handle\n", __func__);\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("%s: ERROR : No device registered\n", __func__);\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
- if (thh_hob_p->srqm == (THH_srqm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("%s: SRQs are not supported in this HCA configuration\n", __func__);\r
- return HH_ENOSYS;\r
- }\r
-\r
- return THH_srqm_create_srq(thh_hob_p->srqm, pd, srq_ul_resources_p, srq_p);\r
-}\r
-\r
-HH_ret_t THH_hob_query_srq(HH_hca_hndl_t hca_hndl, HH_srq_hndl_t srq, u_int32_t *limit_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("%s: NOT IN TASK CONTEXT)\n", __func__);\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("%s : ERROR : Invalid HCA handle\n", __func__);\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("%s: ERROR : No device registered\n", __func__);\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
- if (thh_hob_p->srqm == (THH_srqm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("%s: SRQs are not supported in this HCA configuration", __func__);\r
- return HH_ENOSYS;\r
- }\r
-\r
- return THH_srqm_query_srq(thh_hob_p->srqm, srq, limit_p);\r
-}\r
-\r
-HH_ret_t THH_hob_modify_srq(HH_hca_hndl_t hca_hndl, HH_srq_hndl_t srq, void *srq_ul_resources_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MTL_TRACE4("%s: srq=0x%X)\n", __func__, srq);\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("%s: NOT IN TASK CONTEXT)\n", __func__);\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("%s : ERROR : Invalid HCA handle\n", __func__);\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("%s: ERROR : No device registered\n", __func__);\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
- if (thh_hob_p->srqm == (THH_srqm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("%s: SRQs are not supported in this HCA configuration", __func__);\r
- return HH_ENOSYS;\r
- }\r
-\r
- return THH_srqm_modify_srq(thh_hob_p->srqm, srq, srq_ul_resources_p);\r
-}\r
-\r
-\r
-HH_ret_t THH_hob_destroy_srq(HH_hca_hndl_t hca_hndl, HH_srq_hndl_t srq)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("%s: NOT IN TASK CONTEXT)\n", __func__);\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("%s : ERROR : Invalid HCA handle\n", __func__);\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("%s: ERROR : No device registered\n", __func__);\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
- if (thh_hob_p->srqm == (THH_srqm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("%s: SRQs are not supported in this HCA configuration", __func__);\r
- return HH_ENOSYS;\r
- }\r
-\r
- return THH_srqm_destroy_srq(thh_hob_p->srqm, srq);\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_process_local_mad <==> THH_qpm_process_local_mad\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_process_local_mad(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port,\r
- IB_lid_t slid, /* For Mkey violation trap */\r
- EVAPI_proc_mad_opt_t proc_mad_opts,\r
- void * mad_in_p,\r
- void * mad_out_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_process_local_mad: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_process_local_mad : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_process_local_mad: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->qpm == (THH_qpm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_destroy_qp: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_qpm_process_local_mad(thh_hob_p->qpm,port,slid,proc_mad_opts,mad_in_p,mad_out_p);\r
-}\r
- \r
-\r
-/******************************************************************************\r
- * Function: THH_hob_ddrmm_alloc <==> THH_ddrmm_alloc\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_ddrmm_alloc(\r
- HH_hca_hndl_t hca_hndl,\r
- VAPI_size_t size, \r
- u_int8_t align_shift,\r
- VAPI_phy_addr_t* buf_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
- MT_phys_addr_t adrs;\r
- HH_ret_t ret = HH_OK;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1(MT_FLFMT(" NOT IN TASK CONTEXT\n"));\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1(MT_FLFMT("ERROR : Invalid HCA handle\n"));\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("ERROR : No device registered\n"));\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->ddrmm == (THH_ddrmm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1(MT_FLFMT("ERROR : HCA device has not yet been opened\n"));\r
- return HH_EAGAIN;\r
- }\r
-\r
- if (thh_hob_p->ddr_props.dh == TRUE) {\r
- /* Must hide DDR memory. alloc fmr not supported */\r
- MTL_ERROR1(MT_FLFMT("%s: Device is operating in HIDE_DDR mode. Cannot alloc ddr memory"), __func__);\r
- return HH_ENOSYS;\r
- }\r
-\r
- MTL_DEBUG1(MT_FLFMT("before THH_ddrmm_alloc \n"));\r
- /* tavor ALWAYS has DDR, on other devices we should query if ther's DDR */\r
-/*** warning C4242: 'function' : conversion from 'VAPI_size_t' to 'MT_size_t', possible loss of data ***/\r
- ret = THH_ddrmm_alloc(thh_hob_p->ddrmm,(MT_size_t)size,align_shift,&adrs);\r
- MTL_DEBUG1(MT_FLFMT("after THH_ddrmm_alloc \n"));\r
- *buf_p = (VAPI_phy_addr_t)adrs;\r
- return ret;\r
- \r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_ddrmm_query <==> THH_ddrmm_query\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_ddrmm_query(\r
- HH_hca_hndl_t hca_hndl,\r
- u_int8_t align_shift, \r
- VAPI_size_t* total_mem, \r
- VAPI_size_t* free_mem, \r
- VAPI_size_t* largest_chunk, \r
- VAPI_phy_addr_t* largest_free_addr_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
- \r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1(MT_FLFMT(" NOT IN TASK CONTEXT\n"));\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1(MT_FLFMT("ERROR : Invalid HCA handle\n"));\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("ERROR : No device registered\n"));\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->ddrmm == (THH_ddrmm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1(MT_FLFMT("ERROR : HCA device has not yet been opened\n"));\r
- return HH_EAGAIN;\r
- }\r
-\r
- if (thh_hob_p->ddr_props.dh == TRUE) {\r
- /* Must hide DDR memory. alloc fmr not supported */\r
- MTL_ERROR1(MT_FLFMT("%s: Device is operating in HIDE_DDR mode. Cannot query ddr memory"), __func__);\r
- return HH_ENOSYS;\r
- }\r
-\r
- MTL_DEBUG1(MT_FLFMT("before THH_ddrmm_query \n"));\r
- /* tavor ALWAYS has DDR, on other devices we should query if ther's DDR */\r
- return THH_ddrmm_query(thh_hob_p->ddrmm,align_shift,total_mem,free_mem,largest_chunk,largest_free_addr_p);\r
- \r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_ddrmm_free <==> THH_ddrmm_free\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_ddrmm_free(\r
- HH_hca_hndl_t hca_hndl,\r
- VAPI_phy_addr_t buf,\r
- VAPI_size_t size)\r
- \r
-{\r
- THH_hob_t thh_hob_p;\r
- HH_ret_t rc = HH_OK;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1(MT_FLFMT(" NOT IN TASK CONTEXT\n"));\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1(MT_FLFMT("ERROR : Invalid HCA handle\n"));\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("ERROR : No device registered\n"));\r
- return HH_EAGAIN;\r
- }\r
-\r
-\r
- if (thh_hob_p->ddrmm == (THH_ddrmm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1(MT_FLFMT("ERROR : HCA device has not yet been opened\n"));\r
- return HH_EAGAIN;\r
- }\r
-\r
-/*** warning C4242: 'function' : conversion from 'VAPI_size_t' to 'MT_size_t', possible loss of data ***/\r
- rc = THH_ddrmm_free(thh_hob_p->ddrmm,buf,(MT_size_t)size);\r
- return rc;\r
-}\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_get_qp1_pkey <==> THH_qpm_get_qp1_pkey\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_get_qp1_pkey(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port,/*IN */\r
- VAPI_pkey_t* pkey_p/*OUT*/)\r
-\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1(MT_FLFMT("Invalid HCA handle"));\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("Invalid HCA handle"));\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
- if (thh_hob_p->qpm == (THH_qpm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1(MT_FLFMT("HCA %s has not yet been opened"),thh_hob_p->dev_name);\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_qpm_get_qp1_pkey(thh_hob_p->qpm,port,pkey_p);\r
-}\r
-\r
-HH_ret_t THH_hob_get_pkey(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port,/*IN */\r
- VAPI_pkey_ix_t pkey_index, /*IN*/\r
- VAPI_pkey_t* pkey_p/*OUT*/)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1(MT_FLFMT("Invalid HCA handle"));\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("Invalid HCA handle"));\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
- if (thh_hob_p->qpm == (THH_qpm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1(MT_FLFMT("HCA %s has not yet been opened"),thh_hob_p->dev_name);\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_qpm_get_pkey(thh_hob_p->qpm,port,pkey_index,pkey_p);\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_get_sgid <==> THH_qpm_get_sgid\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_get_sgid(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port,/*IN */\r
- u_int8_t index,/*IN*/\r
- IB_gid_t* gid_p/*OUT*/)\r
-\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1(MT_FLFMT("Invalid HCA handle"));\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("Invalid HCA handle"));\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
- if (thh_hob_p->qpm == (THH_qpm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1(MT_FLFMT("HCA %s has not yet been opened"),thh_hob_p->dev_name);\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_qpm_get_sgid(thh_hob_p->qpm,port,index,gid_p);\r
-}\r
-\r
-HH_ret_t THH_hob_get_legacy_mode(THH_hob_t thh_hob_p,MT_bool *p_mode)\r
-{\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("Invalid HCA handle"));\r
- return HH_EAGAIN;\r
- }\r
-\r
- *p_mode = thh_hob_p->module_flags.legacy_sqp;\r
-\r
- return HH_OK;\r
-}\r
-\r
-\r
- /******************************************************************************\r
- * Function: THH_hob_create_eec <==> THH_eecm_create_eec\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_create_eec(HH_hca_hndl_t hca_hndl, \r
- HH_rdd_hndl_t rdd, \r
- IB_eecn_t *eecn_p)\r
-{\r
-#if 0\r
- THH_hob_t thh_hob_p;\r
-\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_create_eec: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_create_eec : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_create_eec: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
-\r
- if (thh_hob_p->eecm == (THH_eecm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_create_eec: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_eecm_create_eec(thh_hob_p->eecm, rdd, eecn_p);\r
-#else\r
- return HH_ENOSYS;\r
-#endif\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_modify_eec <==> THH_eecm_modify_eec\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_modify_eec(HH_hca_hndl_t hca_hndl,\r
- IB_eecn_t eecn, \r
- VAPI_qp_state_t cur_ee_state, \r
- VAPI_qp_attr_t *ee_attr_p, \r
- VAPI_qp_attr_mask_t *ee_attr_mask_p)\r
-{\r
-#if 0\r
- THH_hob_t thh_hob_p;\r
-\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_modify_eec: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_modify_eec : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_modify_eec: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->eecm == (THH_eecm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_modify_eec: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_eecm_modify_eec(thh_hob_p->eecm, eecn, cur_ee_state, ee_attr_p, ee_attr_mask_p);\r
-#else\r
- return HH_ENOSYS;\r
-#endif\r
-}\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_query_eec <==> THH_eecm_query_eec\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_query_eec(HH_hca_hndl_t hca_hndl,\r
- IB_eecn_t eecn, \r
- VAPI_qp_attr_t *ee_attr_p)\r
-{\r
-#if 0\r
- THH_hob_t thh_hob_p;\r
-\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_query_eec: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_query_eec : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_query_eec: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->eecm == (THH_eecm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_query_eec: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_eecm_query_eec(thh_hob_p->eecm, eecn, ee_attr_p);\r
-#else\r
- return HH_ENOSYS;\r
-#endif\r
-}\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_destroy_eec <==> THH_eecm_destroy_eec\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_destroy_eec(HH_hca_hndl_t hca_hndl,\r
- IB_eecn_t eecn)\r
-{\r
-#if 0\r
- THH_hob_t thh_hob_p;\r
- HH_ret_t rc = HH_OK;\r
-\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_destroy_eec: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_destroy_eec : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_destroy_eec: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
-\r
- if (thh_hob_p->eecm == (THH_eecm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_destroy_eec: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- rc = THH_eecm_destroy_eec(thh_hob_p->eecm, eecn);\r
- return rc;\r
-#else\r
- return HH_ENOSYS;\r
-#endif\r
-}\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_attach_to_multicast <==> THH_mcgm_attach_qp\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_attach_to_multicast(\r
- HH_hca_hndl_t hca_hndl, \r
- IB_wqpn_t qpn,\r
- IB_gid_t dgid)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_attach_to_multicast: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_attach_to_multicast : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_attach_to_multicast: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
- if (thh_hob_p->mcgm == (THH_mcgm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_attach_to_multicast: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_mcgm_attach_qp(thh_hob_p->mcgm, qpn, dgid);\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_detach_from_multicast <==> THH_mcgm_detach_qp\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_detach_from_multicast(\r
- HH_hca_hndl_t hca_hndl, \r
- IB_wqpn_t qpn,\r
- IB_gid_t dgid)\r
-{\r
- THH_hob_t thh_hob_p;\r
- HH_ret_t rc = HH_OK;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_detach_from_multicast: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_detach_from_multicast : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_detach_from_multicast: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- if (thh_hob_p->mcgm == (THH_mcgm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1( "THH_hob_detach_from_multicast: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- rc = THH_mcgm_detach_qp(thh_hob_p->mcgm, qpn, dgid);\r
- return rc;\r
-}\r
-\r
-VIP_delay_unlock_t THH_hob_get_delay_unlock(THH_hob_t hob)\r
-{ \r
- if (hob == NULL) {\r
- return NULL;\r
- } else {\r
- return (hob->delay_unlocks);\r
- }\r
-}\r
-\r
-HH_ret_t THH_get_debug_info(\r
- HH_hca_hndl_t hca_hndl, /*IN*/\r
- THH_debug_info_t *debug_info_p /*OUT*/\r
-)\r
-{\r
- THH_hob_t hob_p;\r
- HH_ret_t rc = HH_OK;\r
- MT_bool have_error = FALSE;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_get_debug_info: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_get_debug_info : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- hob_p = THHOBP(hca_hndl);\r
-\r
- if (hob_p == NULL) {\r
- MTL_ERROR1("THH_get_debug_info: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- memset(debug_info_p, 0, sizeof(THH_debug_info_t));\r
- \r
- memcpy(&(debug_info_p->hw_props), &(hob_p->hw_props), sizeof(THH_hw_props_t));\r
- memcpy(&(debug_info_p->profile), &(hob_p->profile), sizeof(THH_profile_t));\r
- memcpy(&(debug_info_p->ddr_addr_vec), &(hob_p->ddr_alloc_base_addrs_vec), \r
- sizeof(THH_ddr_base_addr_vector_t));\r
- memcpy(&(debug_info_p->ddr_size_vec), &(hob_p->ddr_alloc_size_vec), \r
- sizeof(THH_ddr_allocation_vector_t));\r
- debug_info_p->num_ddr_addrs = THH_DDR_ALLOCATION_VEC_SIZE;\r
- memcpy(&(debug_info_p->mrwm_props), &(hob_p->mrwm_props), sizeof(THH_mrwm_props_t));\r
-\r
- debug_info_p->hide_ddr = hob_p->ddr_props.dh;\r
-\r
- rc = THH_uldm_get_num_objs(hob_p->uldm,&(debug_info_p->allocated_ul_res),&(debug_info_p->allocated_pd));\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("THH_get_debug_info: proc THH_uldm_get_num_of_objs returned ERROR"));\r
- have_error = TRUE;\r
- }\r
- \r
- rc = THH_mrwm_get_num_objs(hob_p->mrwm,&(debug_info_p->allocated_mr_int),\r
- &(debug_info_p->allocated_mr_ext), &(debug_info_p->allocated_mw));\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("THH_get_debug_info: proc THH_mrwm_get_num_of_objs returned ERROR"));\r
- have_error = TRUE;\r
- }\r
-\r
- rc = THH_qpm_get_num_qps(hob_p->qpm,&(debug_info_p->allocated_qp));\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("THH_get_debug_info: proc THH_tqpm_get_num_of_qps returned ERROR"));\r
- have_error = TRUE;\r
- }\r
- \r
- rc = THH_cqm_get_num_cqs(hob_p->cqm,&(debug_info_p->allocated_cq));\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("THH_get_debug_info: proc THH_tcqm_get_num_of_cqs returned ERROR"));\r
- have_error = TRUE;\r
- }\r
- \r
- rc = THH_mcgm_get_num_mcgs(hob_p->mcgm,&(debug_info_p->allocated_mcg));\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("THH_get_debug_info: proc THH_mcgm_get_num_of_mcgs returned ERROR"));\r
- have_error = TRUE;\r
- }\r
-\r
- return (have_error ? HH_ERR : HH_OK);\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_get_num_ports\r
- *\r
- * Description: Gets number of physical ports configured for HCA \r
- *\r
- * input:\r
- * hca_hndl\r
- * output: \r
- * num_ports_p - 1 or 2\r
- * returns:\r
- * HH_OK\r
- * HH_EINVAL\r
- * HH_EINVAL_HCA_HNDL\r
- * HH_ERR\r
- *\r
- * Comments: Does MAD query to get the data in real time. \r
- *\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_get_num_ports( HH_hca_hndl_t hca_hndl,\r
- IB_port_t *num_ports_p)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1(MT_FLFMT("Invalid HCA handle"));\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
- \r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("Invalid HCA handle"));\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
- *num_ports_p = (IB_port_t)(thh_hob_p->dev_lims.num_ports);\r
- return HH_OK;\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_external_fatal\r
- *\r
- * Description: Artificially generates the fatal error flow from an external \r
- * call \r
- *\r
- * input:\r
- * hca_hndl\r
- * output: \r
- * \r
- * returns:\r
- * HH_OK\r
- * HH_EINVAL_HCA_HNDL\r
- * HH_EFATAL -- driver already in fatal state\r
- *\r
- * Comments: Meant to enable performing a VAPI STOP following a Tavor reset. \r
- *\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_external_fatal( HH_hca_hndl_t hca_hndl)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1(MT_FLFMT("Invalid HCA handle"));\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
- \r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("Invalid HCA handle"));\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
- MTL_ERROR1(MT_FLFMT("%s: Generating a fatal error for device %s"), \r
- __func__, hca_hndl->dev_desc);\r
- THH_hob_fatal_error(thh_hob_p, THH_FATAL_EXTERNAL,VAPI_EV_SYNDROME_NONE);\r
- return HH_OK;\r
-}\r
-\r
-#if defined(MT_SUSPEND_QP)\r
-/******************************************************************************\r
- * Function: THH_hob_suspend_qp <==> THH_qpm_suspend_qp\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_suspend_qp(HH_hca_hndl_t hca_hndl, \r
- IB_wqpn_t qpn, \r
- MT_bool suspend_flag)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_suspend_qp: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_suspend_qp : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_suspend_qp: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->qpm == (THH_qpm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_suspend_qp: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_qpm_suspend_qp(thh_hob_p->qpm, qpn, suspend_flag);\r
-}\r
-/******************************************************************************\r
- * Function: THH_hob_suspend_cq <==> THH_qpm_suspend_cq\r
- *****************************************************************************/\r
-HH_ret_t THH_hob_suspend_cq(HH_hca_hndl_t hca_hndl, \r
- HH_cq_hndl_t cq, \r
- MT_bool do_suspend)\r
-{\r
- THH_hob_t thh_hob_p;\r
-\r
- MT_RETURN_IF_LOW_STACK(THH_WATERMARK);\r
- if (MOSAL_get_exec_ctx() != MOSAL_IN_TASK) {\r
- MTL_ERROR1("THH_hob_suspend_qp: NOT IN TASK CONTEXT)\n");\r
- return HH_ERR;\r
- }\r
-\r
- if (hca_hndl == NULL) {\r
- MTL_ERROR1("THH_hob_suspend_qp : ERROR : Invalid HCA handle\n");\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- thh_hob_p = THHOBP(hca_hndl);\r
-\r
- if (thh_hob_p == NULL) {\r
- MTL_ERROR1("THH_hob_suspend_qp: ERROR : No device registered\n");\r
- return HH_EAGAIN;\r
- }\r
- TEST_RETURN_FATAL(thh_hob_p);\r
-\r
-\r
- if (thh_hob_p->cqm == (THH_cqm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_hob_suspend_qp: ERROR : HCA device has not yet been opened\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- return THH_cqm_suspend_cq(thh_hob_p->cqm, cq, do_suspend);\r
-}\r
-#endif\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_THH_HOB_H\r
-#define H_THH_HOB_H\r
-\r
-#include <vapi.h>\r
-#include <vip_delay_unlock.h>\r
-#include <mosal.h>\r
-#include <hh.h>\r
-#include <thh.h>\r
-\r
-#define THH_RESERVED_PD 0\r
-\r
-/* the memory key used for the UDAVM in THH (privileged mode) */\r
-#define THH_UDAVM_PRIV_RESERVED_LKEY 0\r
-\r
-#define THH_INVALID_HNDL ((MT_ulong_ptr_t) (-1L))\r
-\r
-typedef struct THH_intr_props_st {\r
- MOSAL_IRQ_ID_t irq;\r
- u_int8_t intr_pin;\r
-} THH_intr_props_t;\r
-\r
-typedef struct THH_hw_props_st {\r
- u_int8_t bus;\r
- u_int8_t dev_func;\r
- u_int16_t device_id;\r
- u_int16_t pci_vendor_id;\r
- u_int32_t hw_ver;\r
- MT_phys_addr_t cr_base;\r
- MT_phys_addr_t uar_base;\r
- MT_phys_addr_t ddr_base;\r
- THH_intr_props_t interrupt_props;\r
-} THH_hw_props_t;\r
-\r
-\r
-/* Prototypes */\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_create \r
- *\r
- * Arguments:\r
- * hw_props_p - pointer to HW properties.\r
- * hca_seq_num - a sequence number assigned to this HCA to differentiate it \r
- * from other HCAs on this host\r
- * mod_flags - ptr to struct containing flags passed during module initialization\r
- * (e.g. insmod)\r
- * hh_hndl_p - Returned HH context handle. HOB object is accessed via device field \r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameter\r
- *\r
- * Description:\r
- * Allocate THH_hob object and register the device in HH.\r
- */\r
-DLL_API HH_ret_t THH_hob_create(/*IN*/ THH_hw_props_t *hw_props_p,\r
- /*IN*/ u_int32_t hca_seq_num,\r
- /*IN*/ THH_module_flags_t *mod_flags,\r
- /*OUT*/ HH_hca_hndl_t *hh_hndl_p );\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_destroy \r
- *\r
- * Arguments:\r
- * hca_hndl - The HCA handle allocated on device registration \r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL_HCA_HNDL - The HCA either is not opened or is unknown\r
- *\r
- * Description:\r
- * Deregister given device from HH and free all associated resources.\r
- * If the HCA is still open, perform THH_hob_close_hca() before freeing the THH_hob.\r
- */\r
-DLL_API HH_ret_t THH_hob_destroy(HH_hca_hndl_t hca_hndl);\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_get_ver_info \r
- *\r
- * Arguments:\r
- * hob\r
- * version_p - Returned version information \r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- *\r
- * Description:\r
- * Get version information of device associated with given hob.\r
- */\r
-DLL_API HH_ret_t THH_hob_get_ver_info ( /*IN*/ THH_hob_t hob, \r
- /*OUT*/ THH_ver_info_t *version_p );\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_get_cmd_if \r
- *\r
- * Arguments:\r
- * hob\r
- * cmd_if_p - Included command interface object \r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- *\r
- * Description:\r
- * Get a handle to associated command interface object.\r
- */\r
-DLL_API HH_ret_t THH_hob_get_cmd_if ( /*IN*/ THH_hob_t hob, \r
- /*OUT*/ THH_cmd_t *cmd_if_p );\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_get_uldm \r
- *\r
- * Arguments:\r
- * hob\r
- * uldm_p - Included THH_uldm object \r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- *\r
- * Description:\r
- * Get a handle to associated user-level domain management object.\r
- */\r
-DLL_API HH_ret_t THH_hob_get_uldm ( /*IN*/ THH_hob_t hob, \r
- /*OUT*/ THH_uldm_t *uldm_p );\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_get_mrwm \r
- *\r
- * Arguments:\r
- * hob\r
- * mrwm_p - Included THH_mrwm object \r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- *\r
- * Description:\r
- * Get a handle to associated memory regions/windows management object.\r
- */\r
-DLL_API HH_ret_t THH_hob_get_mrwm ( /*IN*/ THH_hob_t hob, \r
- /*OUT*/ THH_mrwm_t *mrwm_p );\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_get_udavm_info \r
- *\r
- * Arguments:\r
- * hob\r
- * udavm_p - Included THH_udavm object\r
- * use_priv_udav - flag: TRUE if using privileged UDAV mode\r
- * av_on_board - flag: TRUE if should use DDR SDRAM on Tavor for UDAVs\r
- * lkey - lkey allocated for udav table in privileged UDAV mode \r
- * hide_ddr - flag: TRUE if should use host memory for UDAVs\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- *\r
- * Description:\r
- * return udavm information (needed by uldm object in PD allocation).\r
- */\r
-DLL_API HH_ret_t THH_hob_get_udavm_info ( /*IN*/ THH_hob_t hob, \r
- /*OUT*/ THH_udavm_t *udavm_p,\r
- /*OUT*/ MT_bool *use_priv_udav,\r
- /*OUT*/ MT_bool *av_on_board,\r
- /*OUT*/ VAPI_lkey_t *lkey,\r
- /*OUT*/ u_int32_t *max_ah_num,\r
- /*OUT*/ MT_bool *hide_ddr);\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_get_hca_hndl \r
- *\r
- * Arguments:\r
- * hob\r
- * hca_hndl_p - Included THH_mrwm object \r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- *\r
- * Description:\r
- * Get a handle to the HH hca object.\r
- */\r
-DLL_API HH_ret_t THH_hob_get_hca_hndl ( /*IN*/ THH_hob_t hob, \r
- /*OUT*/ HH_hca_hndl_t *hca_hndl_p );\r
-/******************************************************************************\r
- * Function: THH_hob_get_ddrmm \r
- *\r
- * Arguments:\r
- * hob\r
- * uldm_p - Included THH_ddrmm object \r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- *\r
- * Description:\r
- * Get a handle to DDR memory management object.\r
- */\r
-DLL_API HH_ret_t THH_hob_get_ddrmm ( /*IN*/ THH_hob_t hob, \r
- /*OUT*/ THH_ddrmm_t *ddrmm_p );\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_get_qpm \r
- *\r
- * Arguments:\r
- * hob\r
- * eventp_p - Included THH_qpm object \r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- *\r
- * Description:\r
- * Get a handle to qp management object.\r
- */\r
-DLL_API HH_ret_t THH_hob_get_qpm ( /*IN*/ THH_hob_t hob, \r
- /*OUT*/ THH_qpm_t *qpm_p );\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_get_cqm \r
- *\r
- * Arguments:\r
- * hob\r
- * eventp_p - Included THH_cqm object \r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- *\r
- * Description:\r
- * Get a handle to cq management object.\r
- */\r
-DLL_API HH_ret_t THH_hob_get_cqm ( /*IN*/ THH_hob_t hob, \r
- /*OUT*/ THH_cqm_t *cqm_p );\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_get_eventp \r
- *\r
- * Arguments:\r
- * hob\r
- * eventp_p - Included THH_eventp object \r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- *\r
- * Description:\r
- * Get a handle to event management object.\r
- */\r
-DLL_API HH_ret_t THH_hob_get_eventp ( /*IN*/ THH_hob_t hob, \r
- /*OUT*/ THH_eventp_t *eventp_p );\r
-\r
-/* Function for special QPs (provide info. for building MLX IB headers) */\r
-DLL_API HH_ret_t THH_hob_get_sgid(HH_hca_hndl_t hca_hndl,IB_port_t port,u_int8_t idx, IB_gid_t* gid_p);\r
-DLL_API HH_ret_t THH_hob_get_qp1_pkey(HH_hca_hndl_t hca_hndl,IB_port_t port,VAPI_pkey_t* pkey);\r
-DLL_API HH_ret_t THH_hob_get_pkey(HH_hca_hndl_t hca_hndl,IB_port_t port,VAPI_pkey_ix_t pkey_index,\r
- VAPI_pkey_t* pkey_p/*OUT*/);\r
-DLL_API HH_ret_t THH_hob_get_gid_tbl(HH_hca_hndl_t hca_hndl,IB_port_t port,u_int16_t tbl_len_in,\r
- u_int16_t* tbl_len_out,IB_gid_t* param_gid_p);\r
-DLL_API HH_ret_t THH_hob_init_gid_tbl(HH_hca_hndl_t hca_hndl,IB_port_t port,u_int16_t tbl_len_in,\r
- u_int16_t* tbl_len_out,IB_gid_t* param_gid_p);\r
-DLL_API HH_ret_t THH_hob_get_pkey_tbl(HH_hca_hndl_t hca_hndl,IB_port_t port_num,\r
- u_int16_t tbl_len_in,u_int16_t *tbl_len_out,IB_pkey_t *pkey_tbl_p);\r
-DLL_API HH_ret_t THH_hob_init_pkey_tbl(HH_hca_hndl_t hca_hndl,IB_port_t port_num,\r
- u_int16_t tbl_len_in,u_int16_t *tbl_len_out,IB_pkey_t *pkey_tbl_p);\r
-DLL_API HH_ret_t THH_hob_get_legacy_mode(THH_hob_t thh_hob_p,MT_bool *p_mode);\r
-DLL_API HH_ret_t THH_hob_check_qp_init_attrs (THH_hob_t hob, HH_qp_init_attr_t * init_attr_p,\r
- MT_bool is_special_qp );\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_hob_fatal_error \r
- *\r
- * Arguments:\r
- * hob\r
- * fatal_err_type - type of fatal error which occurred \r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- *\r
- * Description:\r
- * Initiates centralized fatal error handling when a fatal error is detected\r
- */\r
-DLL_API HH_ret_t THH_hob_fatal_error(/*IN*/ THH_hob_t hob,\r
- /*IN*/ THH_fatal_err_t fatal_err_type,\r
- /*IN*/ VAPI_event_syndrome_t syndrome);\r
-\r
-VIP_delay_unlock_t THH_hob_get_delay_unlock(THH_hob_t hob);\r
-\r
-DLL_API HH_ret_t THH_hob_get_init_params(/*IN*/ THH_hob_t thh_hob_p, \r
- /*OUT*/ THH_hw_props_t *hw_props_p,\r
- /*OUT*/ u_int32_t *hca_seq_num,\r
- /*OUT*/ THH_module_flags_t *mod_flags);\r
-DLL_API HH_ret_t THH_hob_restart(HH_hca_hndl_t hca_hndl);\r
-\r
-DLL_API HH_ret_t THH_hob_get_state(THH_hob_t thh_hob_p, THH_hob_state_t *fatal_state);\r
-DLL_API HH_ret_t THH_hob_get_fatal_syncobj(THH_hob_t thh_hob_p, MOSAL_syncobj_t *syncobj);\r
-DLL_API HH_ret_t THH_hob_wait_if_fatal(THH_hob_t thh_hob_p, MT_bool *had_fatal);\r
-\r
-DLL_API HH_ret_t THH_hob_query_port_prop(HH_hca_hndl_t hca_hndl,IB_port_t port_num,VAPI_hca_port_t *hca_port_p );\r
-DLL_API HH_ret_t THH_hob_alloc_ul_res(HH_hca_hndl_t hca_hndl,MOSAL_protection_ctx_t prot_ctx,void *hca_ul_resources_p);\r
-DLL_API HH_ret_t THH_hob_free_ul_res(HH_hca_hndl_t hca_hndl,void *hca_ul_resources_p);\r
-DLL_API HH_ret_t THH_hob_alloc_pd(HH_hca_hndl_t hca_hndl, MOSAL_protection_ctx_t prot_ctx, void * pd_ul_resources_p,HH_pd_hndl_t *pd_num_p);\r
-DLL_API HH_ret_t THH_hob_free_pd(HH_hca_hndl_t hca_hndl, HH_pd_hndl_t pd_num);\r
-DLL_API HH_ret_t THH_hob_alloc_rdd(HH_hca_hndl_t hh_dev_p, HH_rdd_hndl_t *rdd_p);\r
-DLL_API HH_ret_t THH_hob_free_rdd(HH_hca_hndl_t hh_dev_p, HH_rdd_hndl_t rdd);\r
-DLL_API HH_ret_t THH_hob_create_ud_av(HH_hca_hndl_t hca_hndl,HH_pd_hndl_t pd,VAPI_ud_av_t *av_p, HH_ud_av_hndl_t *ah_p);\r
-DLL_API HH_ret_t THH_hob_modify_ud_av(HH_hca_hndl_t hca_hndl, HH_ud_av_hndl_t ah,VAPI_ud_av_t *av_p);\r
-DLL_API HH_ret_t THH_hob_query_ud_av(HH_hca_hndl_t hca_hndl, HH_ud_av_hndl_t ah,VAPI_ud_av_t *av_p);\r
-DLL_API HH_ret_t THH_hob_destroy_ud_av(HH_hca_hndl_t hca_hndl, HH_ud_av_hndl_t ah);\r
-DLL_API HH_ret_t THH_hob_register_mr(HH_hca_hndl_t hca_hndl,HH_mr_t *mr_props_p,VAPI_lkey_t *lkey_p,IB_rkey_t *rkey_p);\r
-DLL_API HH_ret_t THH_hob_reregister_mr(HH_hca_hndl_t hca_hndl,VAPI_lkey_t lkey, VAPI_mr_change_t change_mask, HH_mr_t *mr_props_p, \r
- VAPI_lkey_t* lkey_p,IB_rkey_t *rkey_p);\r
-DLL_API HH_ret_t THH_hob_register_smr(HH_hca_hndl_t hca_hndl,HH_smr_t *mr_props_p,VAPI_lkey_t *lkey_p,IB_rkey_t *rkey_p);\r
-DLL_API HH_ret_t THH_hob_query_mr(HH_hca_hndl_t hca_hndl,VAPI_lkey_t lkey,HH_mr_info_t *mr_info_p);\r
-DLL_API HH_ret_t THH_hob_deregister_mr(HH_hca_hndl_t hca_hndl,VAPI_lkey_t lkey);\r
-DLL_API HH_ret_t THH_hob_alloc_mw(HH_hca_hndl_t hca_hndl,HH_pd_hndl_t pd,IB_rkey_t *initial_rkey_p);\r
-DLL_API HH_ret_t THH_hob_query_mw(HH_hca_hndl_t hca_hndl,IB_rkey_t initial_rkey,IB_rkey_t *current_rkey_p,HH_pd_hndl_t *pd_p);\r
-DLL_API HH_ret_t THH_hob_free_mw(HH_hca_hndl_t hca_hndl,IB_rkey_t initial_rkey);\r
-DLL_API HH_ret_t THH_hob_alloc_fmr(HH_hca_hndl_t hca_hndl, HH_pd_hndl_t pd,\r
- VAPI_mrw_acl_t acl,MT_size_t max_pages,u_int8_t log2_page_sz,VAPI_lkey_t* last_lkey_p);\r
-DLL_API HH_ret_t THH_hob_map_fmr(HH_hca_hndl_t hca_hndl,VAPI_lkey_t last_lkey,\r
- EVAPI_fmr_map_t* map_p,VAPI_lkey_t* lkey_p,IB_rkey_t* rkey_p);\r
-DLL_API HH_ret_t THH_hob_unmap_fmr(HH_hca_hndl_t hca_hndl,u_int32_t num_of_fmrs_to_unmap, VAPI_lkey_t* last_lkeys_array);\r
-DLL_API HH_ret_t THH_hob_free_fmr(HH_hca_hndl_t hca_hndl,VAPI_lkey_t last_lkey);\r
-DLL_API HH_ret_t THH_hob_create_cq(HH_hca_hndl_t hca_hndl,MOSAL_protection_ctx_t user_prot_context,\r
- void *cq_ul_resources_p,HH_cq_hndl_t *cq_p);\r
-DLL_API HH_ret_t THH_hob_resize_cq(HH_hca_hndl_t hca_hndl,HH_cq_hndl_t cq,void *cq_ul_resources_p);\r
-DLL_API HH_ret_t THH_hob_query_cq(HH_hca_hndl_t hca_hndl,HH_cq_hndl_t cq,VAPI_cqe_num_t *num_o_cqes_p);\r
-DLL_API HH_ret_t THH_hob_destroy_cq(HH_hca_hndl_t hca_hndl,HH_cq_hndl_t cq);\r
-DLL_API HH_ret_t THH_hob_create_qp(HH_hca_hndl_t hca_hndl,HH_qp_init_attr_t *init_attr_p, void *qp_ul_resources_p,IB_wqpn_t *qpn_p);\r
-DLL_API HH_ret_t THH_hob_get_special_qp(HH_hca_hndl_t hca_hndl,VAPI_special_qp_t qp_type,IB_port_t port, \r
- HH_qp_init_attr_t *init_attr_p,void *qp_ul_resources_p,IB_wqpn_t *sqp_hndl_p);\r
-DLL_API HH_ret_t THH_hob_modify_qp(HH_hca_hndl_t hca_hndl,IB_wqpn_t qpn,VAPI_qp_state_t cur_qp_state,\r
- VAPI_qp_attr_t *qp_attr_p,VAPI_qp_attr_mask_t *qp_attr_mask_p);\r
-DLL_API HH_ret_t THH_hob_query_qp(HH_hca_hndl_t hca_hndl,IB_wqpn_t qpn,VAPI_qp_attr_t *qp_attr_p);\r
-DLL_API HH_ret_t THH_hob_destroy_qp(HH_hca_hndl_t hca_hndl,IB_wqpn_t qpn);\r
-\r
-DLL_API HH_ret_t THH_hob_create_srq(HH_hca_hndl_t hca_hndl, HH_pd_hndl_t pd, void *srq_ul_resources_p, \r
- HH_srq_hndl_t *srq_p);\r
-DLL_API HH_ret_t THH_hob_query_srq(HH_hca_hndl_t hca_hndl, HH_srq_hndl_t srq, u_int32_t *limit_p);\r
-DLL_API HH_ret_t THH_hob_modify_srq(HH_hca_hndl_t hca_hndl, HH_srq_hndl_t srq, void *srq_ul_resources_p);\r
-DLL_API HH_ret_t THH_hob_destroy_srq(HH_hca_hndl_t hca_hndl, HH_srq_hndl_t srq);\r
-\r
-\r
-DLL_API HH_ret_t THH_hob_process_local_mad(HH_hca_hndl_t hca_hndl,IB_port_t port_num, IB_lid_t slid,\r
- EVAPI_proc_mad_opt_t proc_mad_opts, void *mad_in_p, void * mad_out_p );\r
-\r
-\r
-DLL_API HH_ret_t THH_hob_ddrmm_alloc(HH_hca_hndl_t hca_hndl,VAPI_size_t size,u_int8_t align_shift,VAPI_phy_addr_t* buf_p);\r
-DLL_API HH_ret_t THH_hob_ddrmm_query(HH_hca_hndl_t hca_hndl,u_int8_t align_shift,VAPI_size_t* total_mem, \r
- VAPI_size_t* free_mem,VAPI_size_t* largest_chunk, \r
- VAPI_phy_addr_t* largest_free_addr_p);\r
-\r
-DLL_API HH_ret_t THH_hob_ddrmm_free(HH_hca_hndl_t hca_hndl,VAPI_phy_addr_t buf, VAPI_size_t size);\r
-\r
-\r
-DLL_API HH_ret_t THH_hob_create_eec(HH_hca_hndl_t hca_hndl,HH_rdd_hndl_t rdd,IB_eecn_t *eecn_p);\r
-DLL_API HH_ret_t THH_hob_modify_eec(HH_hca_hndl_t hca_hndl,IB_eecn_t eecn,VAPI_qp_state_t cur_ee_state, \r
- VAPI_qp_attr_t *ee_attr_p,VAPI_qp_attr_mask_t *ee_attr_mask_p);\r
-DLL_API HH_ret_t THH_hob_query_eec(HH_hca_hndl_t hca_hndl,IB_eecn_t eecn,VAPI_qp_attr_t *ee_attr_p);\r
-DLL_API HH_ret_t THH_hob_destroy_eec(HH_hca_hndl_t hca_hndl,IB_eecn_t eecn);\r
-DLL_API HH_ret_t THH_hob_attach_to_multicast(HH_hca_hndl_t hca_hndl,IB_wqpn_t qpn,IB_gid_t dgid);\r
-DLL_API HH_ret_t THH_hob_detach_from_multicast(HH_hca_hndl_t hca_hndl,IB_wqpn_t qpn,IB_gid_t dgid);\r
-DLL_API HH_ret_t THH_hob_get_num_ports( HH_hca_hndl_t hca_hndl, IB_port_t *num_ports_p);\r
-DLL_API HH_ret_t THH_hob_external_fatal( HH_hca_hndl_t hca_hndl);\r
-\r
-#ifdef IVAPI_THH\r
-\r
-DLL_API HH_ret_t THH_hob_set_comp_eventh(HH_hca_hndl_t hca_hndl,\r
- HH_comp_eventh_t event,\r
- void* private_data);\r
-DLL_API HH_ret_t THH_hob_set_async_eventh(HH_hca_hndl_t hca_hndl,\r
- HH_async_eventh_t event,\r
- void* private_data);\r
-DLL_API HH_ret_t THH_hob_open_hca(HH_hca_hndl_t hca_hndl, \r
- EVAPI_hca_profile_t *prop_props_p,\r
- EVAPI_hca_profile_t *sugg_profile_p);\r
-DLL_API HH_ret_t THH_hob_close_hca(HH_hca_hndl_t hca_hndl);\r
-DLL_API HH_ret_t THH_hob_query(HH_hca_hndl_t hca_hndl, VAPI_hca_cap_t *hca_cap_p);\r
-DLL_API HH_ret_t THH_hob_modify(HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- VAPI_hca_attr_t *hca_attr_p,\r
- VAPI_hca_attr_mask_t *hca_attr_mask_p);\r
-\r
-#endif /* IVAPI_THH */\r
-#if defined(MT_SUSPEND_QP)\r
-HH_ret_t THH_hob_suspend_qp(HH_hca_hndl_t hca_hndl, \r
- IB_wqpn_t qpn, \r
- MT_bool suspend_flag);\r
-HH_ret_t THH_hob_suspend_cq(HH_hca_hndl_t hca_hndl, \r
- HH_cq_hndl_t cq, \r
- MT_bool do_suspend);\r
-#endif\r
-\r
-#endif /* H_THH_H */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_THH_HOB_PRIV_H\r
-#define H_THH_HOB_PRIV_H\r
-\r
-#include <mosal.h>\r
-#include <vapi.h>\r
-#include <hh.h>\r
-#include <tavor_dev_defs.h>\r
-#include <thh.h>\r
-#include <thh_hob.h>\r
-#include <epool.h>\r
-#include <tddrmm.h>\r
-#include <cmdif.h>\r
-#include <uar.h>\r
-#include <thh_uldm.h>\r
-#include <tmrwm.h>\r
-#include <tcqm.h>\r
-#include <tqpm.h>\r
-#include <udavm.h>\r
-#include <mcgm.h>\r
-#include <eventp.h>\r
-#include <vip_delay_unlock.h>\r
-\r
-/********************* TEMPORARY DEFINES, INCLUDED UNTIL THINGS GET FIXED UP ****************/\r
-\r
-\r
-/* ******************* END TEMPORARY DEFINES ******************* */\r
-\r
-#define THHOBP(hca_hndl) ((THH_hob_t)(hca_hndl->device))\r
-#define THHOB(hca_id) ((THH_hob_t)(HH_hca_dev_tbl[hca_id].device))\r
-\r
-#define THH_RESERVED_PD 0\r
-#define THH_DEV_LIM_MCG_ENABLED(hob) (hob->dev_lims.udm == 1)\r
-\r
-\r
-typedef struct THH_ib_props_st {\r
- int dummy;\r
-} THH_ib_props_t;\r
-\r
-/* minimum required firmware -- major_rev=1, minor_rev = 0x0015, sub_minor (patch) = 0 */\r
-#define THH_MIN_FW_VERSION MAKE_ULONGLONG(0x0000000100150000)\r
-#define THH_MIN_FW_ERRBUF_VERSION MAKE_ULONGLONG(0x0000000100180000)\r
-#define THH_MIN_FW_HIDE_DDR_VERSION MAKE_ULONGLONG(0x0000000100180000)\r
-#define THH_MIN_FW_VERSION_SRQ MAKE_ULONGLONG(0x0000000300010000)\r
-\r
-/* Definitions for default profile */\r
-/* NOTE: All table sizes MUST be a power of 2 */\r
-\r
-#define THH_DDR_ALLOCATION_VEC_SIZE 10 /* EEC not implemented yet */\r
-typedef struct THH_ddr_allocation_vector_st {\r
- MT_size_t log2_mtt_size;\r
- MT_size_t log2_mpt_size;\r
- MT_size_t log2_qpc_size;\r
- MT_size_t log2_eqpc_size; /* QPC alt path */\r
- MT_size_t log2_srqc_size;\r
- MT_size_t log2_cqc_size;\r
- MT_size_t log2_rdb_size; /* in-flight rdma */\r
- MT_size_t log2_uar_scratch_size;\r
- MT_size_t log2_eqc_size;\r
- MT_size_t log2_mcg_size;\r
- MT_size_t log2_eec_size;\r
- MT_size_t log2_eeec_size; /* EEC alt path */\r
-#if 0\r
- MT_size_t log2_wqe_pool_size;\r
- MT_size_t log2_uplink_qp_size;\r
- MT_size_t log2_uplink_mem_size;\r
-#endif\r
-} THH_ddr_allocation_vector_t;\r
-\r
-typedef struct THH_ddr_base_addr_vector_st {\r
- MT_phys_addr_t mtt_base_addr;\r
- MT_phys_addr_t mpt_base_addr;\r
- MT_phys_addr_t qpc_base_addr;\r
- MT_phys_addr_t eqpc_base_addr;\r
- MT_phys_addr_t srqc_base_addr;\r
- MT_phys_addr_t cqc_base_addr;\r
- MT_phys_addr_t rdb_base_addr; /* in-flight rdma */\r
- MT_phys_addr_t uar_scratch_base_addr;\r
- MT_phys_addr_t eqc_base_addr;\r
- MT_phys_addr_t mcg_base_addr;\r
- MT_phys_addr_t eec_base_addr;\r
- MT_phys_addr_t eeec_base_addr;\r
-#if 0\r
- MT_phys_addr_t log2_wqe_pool_size;\r
- MT_phys_addr_t log2_uplink_qp_size;\r
- MT_phys_addr_t log2_uplink_mem_size;\r
-#endif\r
-} THH_ddr_base_addr_vector_t;\r
-\r
-typedef enum {\r
- THH_DDR_SIZE_BAD,\r
- THH_DDR_SIZE_32M = 1,\r
- THH_DDR_SIZE_64M,\r
- THH_DDR_SIZE_128M,\r
- THH_DDR_SIZE_256M,\r
- THH_DDR_SIZE_512M,\r
- THH_DDR_SIZE_1024M,\r
- THH_DDR_SIZE_2048M,\r
- THH_DDR_SIZE_4096M,\r
- THH_DDR_SIZE_BIG,\r
-} THH_ddr_size_enum_t;\r
-\r
-typedef struct THH_non_ddr_defaults_st {\r
- MT_bool use_priv_udav;\r
- THH_ddr_size_enum_t ddr_size_code;\r
- MT_size_t ddr_size;\r
- MT_size_t max_num_pds;\r
- MT_size_t num_external_mem_regions;\r
- MT_size_t num_mem_windows;\r
- MT_size_t ddr_alloc_vec_size;\r
- MT_size_t log2_max_uar;\r
- MT_size_t log2_max_qps;\r
- MT_size_t max_num_qps;\r
- MT_size_t log2_max_srqs;\r
- MT_size_t max_num_srqs;\r
- MT_size_t log2_wqe_ddr_space_per_qp;\r
- MT_size_t log2_max_cqs;\r
- MT_size_t max_num_cqs;\r
- MT_size_t log2_max_eecs;\r
- MT_size_t log2_max_mcgs;\r
- MT_size_t log2_mcg_entry_size;\r
- MT_size_t log2_mcg_hash_size;\r
- MT_size_t qps_per_mcg;\r
- MT_size_t log2_max_mpt_entries;\r
- MT_size_t log2_max_mtt_entries;\r
- MT_size_t log2_mtt_entries_per_seg;\r
- MT_size_t log2_mtt_segs_per_region;\r
- u_int8_t log2_max_eqs;\r
- u_int8_t log2_uar_pg_size;\r
- MT_size_t max_priv_udavs;\r
- u_int8_t log2_inflight_rdma_per_qp;\r
-} THH_profile_t;\r
-\r
-#define THH_DEF_CQ_PER_QP 1\r
-\r
-#define TAVOR_MAX_EQ 64\r
-#define THH_COMPL_EQ_IX 0\r
-#define THH_IB_EQ_IX 1\r
-#define THH_CMD_EQ_IX 2\r
-#define THH_MT_EQ_IX 3\r
-\r
-typedef struct THH_hob_port_info_st {\r
- u_int32_t capability_bits;\r
-}THH_hob_port_info_t;\r
-\r
-/* catastrophic error thread structure */\r
-typedef struct THH_hob_cat_err_thread_st {\r
- MOSAL_thread_t mto;\r
- MOSAL_mutex_t mutex;\r
- MOSAL_syncobj_t start_sync; /* sync object needed on start of thread */\r
- MOSAL_syncobj_t stop_sync; /* sync object needed on exit of thread */\r
- MOSAL_syncobj_t fatal_err_sync; /* wait on fatal_err_sync object */\r
- struct THH_hob_st *hob; /* pointer to this thread's HOB object */\r
- volatile MT_bool have_fatal; /*TRUE ==> catastrophic error has occurred */\r
- /*FALSE ==> just exit. */\r
-} THH_hob_cat_err_thread_t;\r
-\r
-typedef struct THH_hob_pci_info_st {\r
- MT_bool is_valid;\r
- u_int8_t bus;\r
- u_int8_t dev_func;\r
- u_int32_t config[64];\r
-} THH_hob_pci_info_t;\r
-\r
-typedef struct THH_hob_st {\r
- /* THH_hob_create parameters */\r
- u_int32_t hca_seq_num;\r
- THH_module_flags_t module_flags;\r
- THH_hw_props_t hw_props;\r
-\r
- char dev_name[20];\r
- u_int32_t dev_id;\r
- HH_hca_hndl_t hh_hca_hndl;\r
-\r
- THH_dev_lim_t dev_lims; /* QUERY_DEV_LIM */\r
- THH_adapter_props_t adapter_props; /* QUERY_ADAPTER */\r
- THH_fw_props_t fw_props; /* QUERY_FW */\r
- THH_ddr_props_t ddr_props; /* QUERY_DDR */\r
- THH_ib_props_t ib_props; /* QUERY_IB */\r
-\r
- THH_port_init_props_t *init_ib_props; /* VMALLOCed. One entry per port */\r
- /* HCA Props */\r
- THH_hca_props_t hca_props;\r
-\r
- VAPI_hca_cap_t hca_capabilities; /* filled at end of open_hca, and saved for Query_hca */\r
- \r
- MT_virt_addr_t fw_error_buf_start_va;\r
- u_int32_t * fw_error_buf; /* kmalloced buffer ready to hold info at cat error */\r
-\r
- THH_ddr_allocation_vector_t ddr_alloc_size_vec;\r
- THH_ddr_base_addr_vector_t ddr_alloc_base_addrs_vec;\r
- THH_profile_t profile;\r
-\r
- /* HH Interface */\r
- HH_if_ops_t if_ops;\r
-\r
- /* Version information */\r
- THH_ver_info_t version_info;\r
-\r
- /* udavm information if privileged is used*/\r
- MT_bool udavm_use_priv;\r
- VAPI_lkey_t udavm_lkey;\r
- MT_virt_addr_t udavm_table;\r
- MT_phys_addr_t udavm_table_ddr;\r
- MT_size_t udavm_table_size;\r
-\r
- /* EQ handles */\r
- THH_eqn_t compl_eq;\r
- THH_eqn_t ib_eq;\r
-\r
- /* Mutexes, etc */\r
- MOSAL_mutex_t mtx; /* used internally */ \r
-\r
- /* CONTAINED OBJECTS HANDLES */\r
- THH_cmd_t cmd;\r
- THH_ddrmm_t ddrmm;\r
- THH_uldm_t uldm;\r
- THH_mrwm_t mrwm;\r
- THH_cqm_t cqm;\r
- /* THH_eecm_t eecm; */\r
- THH_qpm_t qpm;\r
- THH_srqm_t srqm;\r
- THH_udavm_t udavm;\r
-\r
- char *av_ddr_base; \r
- char *av_host_base;\r
-\r
- THH_mcgm_t mcgm;\r
- THH_eventp_t eventp;\r
- THH_uar_t kar;\r
- MT_virt_addr_t kar_addr;\r
- \r
- /* for THH_get_debug_info() */\r
- THH_mrwm_props_t mrwm_props;\r
-\r
- /* fatal error handling fields */\r
- VAPI_event_syndrome_t fatal_syndrome;\r
- THH_hob_state_t thh_state;\r
- MOSAL_syncobj_t thh_fatal_complete_syncobj;\r
- HH_async_eventh_t async_eventh; /* saved handler and context, registered by VIP */\r
- void* async_ev_private_context;\r
- MOSAL_spinlock_t async_spl;\r
- MOSAL_spinlock_t fatal_spl;\r
-\r
- VIP_delay_unlock_t delay_unlocks;\r
- THH_hob_cat_err_thread_t fatal_thread_obj;\r
-\r
- THH_hob_pci_info_t pci_bridge_info;\r
- THH_hob_pci_info_t pci_hca_info;\r
-\r
-} THH_hob_dev_t;\r
-\r
-typedef struct {\r
- THH_hw_props_t hw_props;\r
- THH_profile_t profile;\r
- THH_ddr_base_addr_vector_t ddr_addr_vec;\r
- THH_ddr_base_addr_vector_t ddr_size_vec;\r
- u_int32_t num_ddr_addrs;\r
- THH_mrwm_props_t mrwm_props;\r
- MT_bool hide_ddr;\r
-\r
- /* Allocated resources count */\r
- u_int32_t allocated_ul_res; /* From ULDM */\r
- /* (in current implementation ul_res num. is the same as UAR num., excluding UAR1) */\r
- u_int32_t allocated_pd; /* From ULDM */\r
- u_int32_t allocated_cq; /* From TCQM */\r
- u_int32_t allocated_qp; /* From TQPM */\r
- u_int32_t allocated_mr_int; /* From TMRWM */\r
- u_int32_t allocated_mr_ext; /* From TMRWM */\r
- u_int32_t allocated_mw; /* From TMRWM */\r
- u_int32_t allocated_mcg; /* From MCGM */\r
-} THH_debug_info_t ; \r
-\r
-\r
-HH_ret_t THH_get_debug_info(\r
- HH_hca_hndl_t hca_hndl, /*IN*/\r
- THH_debug_info_t *debug_info_p /*OUT*/\r
-);\r
-\r
-\r
-#endif /* H_THH_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
- \r
-#include <mtl_common.h>\r
-#include <hh.h>\r
-#include <thh.h>\r
-#include <thh_init.h>\r
-\r
-extern void THH_cqm_init(void);\r
-extern void THH_qpm_init(void);\r
-extern void THH_mrwm_init(void);\r
-\r
-HH_ret_t THH_init(void)\r
-{\r
- /* This function should be called by the DDK entry point, to perform any module initializations */\r
- /* that are global (and not per HCA). In Linux, for example, the DDK entry point is "init_module". */\r
-\r
- THH_cqm_init();\r
- THH_qpm_init();\r
- THH_mrwm_init();\r
- return(HH_OK);\r
-}\r
-\r
-\r
-HH_ret_t THH_cleanup(void)\r
-{\r
- /* This function should be called by the DDK exit point, to perform any module initializations */\r
- /* that are global (and not per HCA). In Linux, for example, the DDK exit point is "cleanup_module". */\r
- return(HH_OK);\r
-}\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#ifndef H_THH_INIT_H\r
-#define H_THH_INIT_H\r
-\r
-\r
-/* global THH data structures */\r
-\r
-\r
-#include <vapi.h>\r
-#include <hh.h>\r
-\r
-\r
-HH_ret_t THH_init(void); /* Kernel module entry point */\r
-HH_ret_t THH_cleanup(void); /* Kernel module cleanup point */\r
-\r
-#endif /* H_THH_INIT_H */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-/* Hopefully, we'll get the following fw restrictions out... */\r
-#define SUPPORT_DESTROY_QPI_REUSE 1\r
-#define SUPPORT_2ERR 1\r
-#define SUPPORT_DESTROY 1\r
-/* #define DELAY_CONF_SPECIAL_QPS 1 */\r
-\r
-#include <tqpm.h>\r
-#if defined(USE_STD_MEMORY)\r
-# include <memory.h>\r
-#endif\r
-#include <mtl_common.h> \r
-#include <mosal.h> \r
-#include <epool.h>\r
-#include <tlog2.h>\r
-#include <cmdif.h>\r
-#include <tmrwm.h>\r
-#include <thh_uldm.h>\r
-#include <thh_hob.h>\r
-#include <tddrmm.h>\r
-#include <vapi_common.h>\r
-#include <vip_array.h>\r
-#include <ib_defs.h>\r
-#include <tavor_if_defs.h>\r
-#include <sm_mad.h>\r
-\r
-extern void MadBufPrint(void *madbuf);\r
- \r
-static void printGIDTable(THH_qpm_t qpm);\r
-static void printPKeyTable(THH_qpm_t qpm);\r
-\r
-#define CMDRC2HH_ND(cmd_rc) ((cmd_rc == THH_CMD_STAT_OK) ? HH_OK : \\r
- (cmd_rc == THH_CMD_STAT_EINTR) ? HH_EINTR : HH_EFATAL)\r
-\r
-#define ELSE_ACQ_ERROR(f) else { MTL_ERROR1("%s MOSAL_mutex_acq failed\n", f); }\r
-#define logIfErr(f) \\r
- if (rc != HH_OK) { MTL_ERROR1("%s: rc=%s\n", f, HH_strerror_sym(rc)); }\r
-\r
-\r
-#if !defined(ARR_SIZE)\r
-# define ARR_SIZE(a) (sizeof(a)/sizeof(a[0]))\r
-#endif\r
-\r
-/* These are the tunebale parameters */\r
-enum\r
-{\r
- TUNABLE_ACK_REQ_FREQ = 10,\r
- TUNABLE_FLIGHT_LIMIT = 9\r
-};\r
-\r
-\r
-enum {WQE_CHUNK_SIZE_LOG2 = 6,\r
- WQE_CHUNK_SIZE = 1ul << WQE_CHUNK_SIZE_LOG2,\r
- WQE_CHUNK_MASK = WQE_CHUNK_SIZE - 1\r
- };\r
-\r
-\r
-\r
-typedef struct\r
-{\r
- IB_wqpn_t qpn;\r
- HH_srq_hndl_t srqn; /* If invalid, equals HH_EINVAL_SRQ_HNDL */ \r
- u_int32_t pd;\r
- u_int32_t rdd;\r
- u_int32_t cqn_snd;\r
- u_int32_t cqn_rcv;\r
-\r
- /* The following is kept merely to support query */\r
- VAPI_qp_cap_t cap;\r
-\r
- /* kept to support modify-qp/query-qp */\r
- VAPI_rdma_atom_acl_t remote_atomic_flags;/* Enable/Disable RDMA and atomic */\r
- u_int8_t qp_ous_rd_atom; /* Maximum number of oust. RDMA read/atomic as target */\r
- u_int8_t ous_dst_rd_atom; /* Number of outstanding RDMA rd/atomic ops at destination */\r
- \r
- u_int8_t st; /* sufficient for THH_service_type_t - enum */\r
- VAPI_qp_state_t state;\r
- unsigned int ssc:1;\r
- unsigned int rsc:1;\r
-\r
- MT_virt_addr_t wqes_buf; /* WQEs buffer virtual address */\r
- MT_size_t wqes_buf_sz;\r
- VAPI_lkey_t lkey;\r
- THH_uar_index_t uar_index; /* index of UAR used for this QP */\r
- MT_phys_addr_t pa_ddr;\r
-#if defined(MT_SUSPEND_QP)\r
- MT_bool is_suspended;\r
-#endif\r
-} TQPM_sw_qpc_t;\r
-\r
-\r
-typedef struct\r
-{\r
- signed char tab[VAPI_ERR+1][VAPI_ERR+1]; /* -1 or THH_qpee_transition_t */\r
-} State_machine;\r
-\r
-static const VAPI_special_qp_t qp_types[] = {\r
- VAPI_SMI_QP, VAPI_GSI_QP, /* _Used_ for special QPs */\r
- VAPI_RAW_IPV6_QP, VAPI_RAW_ETY_QP /* Not used: but supported for query */\r
-};\r
-enum {n_qp_types = ARR_SIZE(qp_types)};\r
-\r
-typedef struct\r
-{\r
- u_int8_t n_ports;\r
- MT_bool configured;\r
- IB_wqpn_t first_sqp_qpn; /* Above FW reserved QPCs */\r
- THH_port_init_props_t* port_props;\r
- TQPM_sw_qpc_t** sqp_ctx; /* Context for special QPs is outside of the VIP_array */\r
-} Special_QPs;\r
-\r
-\r
-/* The main QP-manager structure \r
- * Note that {(EPool_t flist), (THH_ddrmm_t ddrmm)}\r
- * have their own mutex-es controlling multi-threads.\r
- */\r
-typedef struct THH_qpm_st\r
-{\r
- /* Capabilities */\r
- u_int8_t log2_max_qp;\r
- u_int32_t rdb_base_index;\r
- u_int8_t log2_max_outs_rdma_atom;\r
- u_int8_t log2_max_outs_dst_rd_atom;\r
- u_int32_t max_outs_rdma_atom; /* convenient 2^log2_max_outs_rdma_atom */\r
- u_int32_t idx_mask; /* convenient (2^log2_max_qp) - 1 */\r
-\r
- /* SW resources tables */\r
- Special_QPs sqp_info;\r
- VIP_array_p_t qp_tbl; /* Index 0 into the table is first_sqp_qpn+NUM_SQP */\r
- u_int32_t first_rqp; /* First regular QP */\r
- u_int8_t* qpn_prefix; /* persistant 8 bit prefix change for QP numbers */\r
- /* In order to avoid holding to much memory for QP numbers prefix we:\r
- * 1) Manipulate only upper 8 bits of the 24 bit QPN \r
- * 2) Hold only MAX_QPN_PREFIX numbers to be shared among QPs with the same lsb of index */\r
- MOSAL_mutex_t mtx; /* protect sqp_ctx and pkey/sgid tables */\r
-\r
- /* convenient handle saving */\r
- THH_hob_t hob;\r
- THH_cmd_t cmd_if;\r
- THH_uldm_t uldm;\r
- THH_mrwm_t mrwm_internal;\r
- THH_ddrmm_t ddrmm;\r
- \r
- /* mirror of the port gid tbl - for special qps*/\r
- IB_gid_t* sgid_tbl[NUM_PORTS];\r
- u_int16_t num_sgids[NUM_PORTS];\r
-\r
- /* mirror of the port qp1 pkey - values are kept CPU endian - little endian*/\r
- VAPI_pkey_t* pkey_tbl[NUM_PORTS]; \r
- u_int16_t pkey_tbl_sz[NUM_PORTS];\r
- VAPI_pkey_ix_t qp1_pkey_idx[NUM_PORTS];\r
- MT_bool port_active[NUM_PORTS];\r
-} TQPM_t;\r
-\r
-static MT_bool constants_ok = TRUE; /* guarding this tqpm module */\r
-static State_machine state_machine; /* const after THH_qpm_init */\r
-static const u_int32_t valid_tavor_ibmtu_mask = \r
- (1ul << MTU256) | \r
- (1ul << MTU512) | \r
- (1ul << MTU1024) | \r
- (1ul << MTU2048);\r
-\r
-\r
-static u_int8_t native_page_shift;\r
-static u_int32_t native_page_size;\r
-static u_int32_t native_page_low_mask;\r
-\r
-/************************************************************************/\r
-/************************************************************************/\r
-/* private functions */\r
-\r
-\r
-\r
-/************************************************************************/\r
-static inline MT_bool is_sqp(THH_qpm_t qpm,IB_wqpn_t qpn) \r
-{\r
- u_int32_t qp_idx = qpn & qpm->idx_mask;\r
-\r
- return ((qp_idx >= qpm->sqp_info.first_sqp_qpn) && (qp_idx < qpm->first_rqp));\r
-}\r
-\r
-/************************************************************************/\r
-static inline MT_bool is_sqp0(THH_qpm_t qpm,IB_wqpn_t qpn,IB_port_t* port_p) \r
-{\r
- u_int32_t qp_idx = qpn & qpm->idx_mask;\r
- MT_bool is_true;\r
- \r
- is_true = ((qp_idx >= qpm->sqp_info.first_sqp_qpn) && \r
- (qp_idx < qpm->sqp_info.first_sqp_qpn + qpm->sqp_info.n_ports));\r
- if (is_true == TRUE) {\r
- *port_p = ((qp_idx-(qpm->sqp_info.first_sqp_qpn & qpm->idx_mask))%qpm->sqp_info.n_ports) + 1;\r
- }\r
-\r
- MTL_DEBUG1(MT_FLFMT("%s: qpn=0x%x, mask=0x%x, first=0x%x, nports=0x%x, *port = %d, ret=%s"),__func__,\r
- qpn, qpm->idx_mask,qpm->sqp_info.first_sqp_qpn, qpm->sqp_info.n_ports, *port_p,\r
- (is_true==FALSE)?"FALSE":"TRUE");\r
- return is_true;\r
-}\r
-\r
-/************************************************************************/\r
-static inline MT_bool is_sqp1(THH_qpm_t qpm,IB_wqpn_t qpn,IB_port_t* port_p) \r
-{\r
- u_int32_t qp_idx = qpn & qpm->idx_mask;\r
- MT_bool is_true = FALSE;\r
-\r
- is_true = ((qp_idx >= qpm->sqp_info.first_sqp_qpn + qpm->sqp_info.n_ports) && \r
- (qp_idx < qpm->sqp_info.first_sqp_qpn + (2 * qpm->sqp_info.n_ports) ));\r
- if (is_true == TRUE) {\r
- *port_p = ((qp_idx-((qpm->sqp_info.first_sqp_qpn & qpm->idx_mask)+qpm->sqp_info.n_ports))%qpm->sqp_info.n_ports) + 1;\r
- }\r
- MTL_DEBUG1(MT_FLFMT("%s: qpn=0x%x, mask=0x%x, first=0x%x, nports=0x%x, *port = %d, ret=%s"),__func__,\r
- qpn, qpm->idx_mask,qpm->sqp_info.first_sqp_qpn, qpm->sqp_info.n_ports, *port_p,\r
- (is_true==FALSE)?"FALSE":"TRUE");\r
- return is_true;\r
-}\r
-/************************************************************************/\r
-static inline MT_bool check_2update_pkey(VAPI_qp_state_t cur_state,VAPI_qp_state_t new_state,\r
- VAPI_qp_attr_mask_t* attr_mask_p)\r
-{\r
- if (*attr_mask_p & QP_ATTR_PKEY_IX)\r
- {\r
- /*obligatory */\r
- if ((cur_state == VAPI_RESET) && (new_state == VAPI_INIT))\r
- {\r
- return TRUE;\r
- }\r
- /* optional */\r
- if ((cur_state == VAPI_INIT) && (new_state == VAPI_RTR))\r
- {\r
- return TRUE;\r
- }\r
- /* optional */\r
- if ((cur_state == VAPI_SQD) && (new_state == VAPI_RTS))\r
- {\r
- return TRUE;\r
- }\r
- }\r
- return FALSE;\r
-}\r
-/************************************************************************/\r
-static MT_bool check_constants(void)\r
-{\r
- static const VAPI_qp_state_t states[] = \r
- {\r
- VAPI_INIT,VAPI_RESET,VAPI_RTR,VAPI_RTS,VAPI_SQD,VAPI_SQE,VAPI_ERR\r
- };\r
- static const IB_mtu_t mtu_vals[] = /* Check all IB MTU values */\r
- { /* not just Tavor's. */\r
- MTU256, MTU512, MTU1024, MTU2048, MTU4096\r
- };\r
- int i;\r
- for (i = 0, constants_ok = TRUE; i != ARR_SIZE(states); ++i)\r
- {\r
-/*** error C4296: '<=' : expression is always true ***/\r
- constants_ok = constants_ok && /*(0 <= states[i]) &&*/ (states[i] < VAPI_ERR+1);\r
- }\r
- for (i = 0; i != ARR_SIZE(mtu_vals); ++i)\r
- {\r
-/*** error C4296: '<=' : expression is always true ***/\r
- constants_ok = constants_ok && /*(0 <= mtu_vals[i]) &&*/ (mtu_vals[i] < 32);\r
- }\r
- MTL_DEBUG4(MT_FLFMT("constants_ok=%d"), constants_ok);\r
- return constants_ok;\r
-} /* check_constants */\r
-\r
-\r
-/************************************************************************/\r
-static inline int defined_qp_state(int qp_state)\r
-{\r
- int def = ((VAPI_RESET <= qp_state) && (qp_state <= VAPI_ERR));\r
- MTL_DEBUG4(MT_FLFMT("qp_state=%d, def=%d"), qp_state, def);\r
- return def;\r
-} /* defined_qp_state */\r
-\r
-\r
-/************************************************************************/\r
-static void init_state_machine(State_machine* xs2s)\r
-{\r
- int fi, ti;\r
-\r
- for (fi = 0; fi != (VAPI_ERR+1); ++fi)\r
- {\r
- /* first, initialize as undefined */\r
- for (ti = 0; ti != VAPI_ERR; ++ti)\r
- {\r
- xs2s->tab[fi][ti] = -1;\r
- }\r
- xs2s->tab[fi][VAPI_ERR] = QPEE_TRANS_2ERR; /* undef later fi=VAPI_RESET */\r
- xs2s->tab[fi][VAPI_RESET] = QPEE_TRANS_ERR2RST;\r
- }\r
-\r
- xs2s->tab[VAPI_RESET][VAPI_ERR] = -1; /* Apr/21/2002 meeting */\r
-\r
- /* see state graph in Tavor-PRM, (12.3 Command Summary) */\r
- xs2s->tab[VAPI_RESET][VAPI_INIT] = QPEE_TRANS_RST2INIT;\r
- xs2s->tab[VAPI_INIT] [VAPI_INIT] = QPEE_TRANS_INIT2INIT;\r
- xs2s->tab[VAPI_INIT] [VAPI_RTR] = QPEE_TRANS_INIT2RTR;\r
- xs2s->tab[VAPI_RTR] [VAPI_RTS] = QPEE_TRANS_RTR2RTS;\r
- xs2s->tab[VAPI_RTS] [VAPI_RTS] = QPEE_TRANS_RTS2RTS;\r
- xs2s->tab[VAPI_SQE] [VAPI_RTS] = QPEE_TRANS_SQERR2RTS;\r
- xs2s->tab[VAPI_RTS] [VAPI_SQD] = QPEE_TRANS_RTS2SQD;\r
- xs2s->tab[VAPI_SQD] [VAPI_RTS] = QPEE_TRANS_SQD2RTS;\r
- xs2s->tab[VAPI_ERR] [VAPI_RESET] = QPEE_TRANS_ERR2RST;\r
-} /* init_state_machine */\r
-/*******************************************************************************/\r
-/*\r
- * init_sgid_table\r
- */\r
-static HH_ret_t init_sgid_tbl(THH_qpm_t qpm)\r
-{\r
- HH_ret_t ret = HH_OK; \r
- HH_hca_hndl_t hca_hndl;\r
- u_int16_t tbl_len_out;\r
- MT_bool destroy_tbl = FALSE;\r
- int i;\r
-\r
- if (qpm == NULL) {\r
- MTL_ERROR1("[%s]: ERROR: NULL qpm value \n",__FUNCTION__);\r
- return HH_EINVAL;\r
- }\r
- for (i=0; i< qpm->sqp_info.n_ports; i++)\r
- {\r
- qpm->num_sgids[i] = 0;\r
- }\r
-\r
- ret = THH_hob_get_hca_hndl(qpm->hob,&hca_hndl); \r
- if (ret != HH_OK)\r
- {\r
- MTL_ERROR1("[%s]: ERROR: THH_hob_get_hca_hndl failed \n",__FUNCTION__);\r
- return ret;\r
- }\r
- \r
- for (i=0; i< qpm->sqp_info.n_ports; i++)\r
- {\r
- qpm->sgid_tbl[i] = (IB_gid_t*)TQPM_GOOD_ALLOC((sizeof(IB_gid_t) * DEFAULT_SGID_TBL_SZ)); \r
- //query the gid table for all ports\r
- ret = THH_hob_init_gid_tbl(hca_hndl,i+1,DEFAULT_SGID_TBL_SZ,&tbl_len_out,qpm->sgid_tbl[i]);\r
- if (ret != HH_OK)\r
- {\r
- if (ret == HH_EAGAIN)\r
- {\r
- TQPM_GOOD_FREE(qpm->sgid_tbl[i],(sizeof(IB_gid_t) * DEFAULT_SGID_TBL_SZ));\r
- qpm->sgid_tbl[i] = (IB_gid_t*)TQPM_GOOD_ALLOC(sizeof(IB_gid_t) * tbl_len_out); \r
- ret = THH_hob_init_gid_tbl(hca_hndl,i+1,tbl_len_out,&tbl_len_out,qpm->sgid_tbl[i]);\r
- if (ret != HH_OK)\r
- {\r
- destroy_tbl = TRUE;\r
- }\r
- \r
- }else destroy_tbl = TRUE; \r
- }\r
- \r
- if (destroy_tbl)\r
- {\r
- MTL_ERROR1("[%s]: ERROR: THH_hob_get_gid_tbl failed for port %d\n",__FUNCTION__,i+1); \r
- TQPM_GOOD_FREE(qpm->sgid_tbl[i],(sizeof(IB_gid_t) * tbl_len_out) );\r
- qpm->sgid_tbl[i] = NULL;\r
- qpm->num_sgids[i] = 0;\r
- }else\r
- {\r
- qpm->num_sgids[i] = tbl_len_out;\r
- }\r
- \r
- destroy_tbl = FALSE;\r
- }\r
- \r
- //TBD: ret for one port failure\r
- MT_RETURN(ret);\r
-}\r
-\r
-/*\r
- * init_pkey_table\r
- */\r
-static HH_ret_t init_pkey_tbl(THH_qpm_t qpm)\r
-{\r
- HH_ret_t ret = HH_OK; \r
- HH_hca_hndl_t hca_hndl;\r
- u_int16_t tbl_len_out;\r
- MT_bool destroy_tbl = FALSE;\r
- int i;\r
-\r
- if (qpm == NULL) {\r
- MTL_ERROR1("[%s]: ERROR: NULL qpm value \n",__FUNCTION__);\r
- return HH_EINVAL;\r
- }\r
- for (i=0; i< qpm->sqp_info.n_ports; i++)\r
- {\r
- qpm->qp1_pkey_idx[i] = 0xffff;\r
- }\r
- \r
- for (i=0; i< qpm->sqp_info.n_ports; i++)\r
- {\r
- qpm->pkey_tbl_sz[i] = 0;\r
- }\r
-\r
- ret = THH_hob_get_hca_hndl(qpm->hob,&hca_hndl); \r
- if (ret != HH_OK)\r
- {\r
- MTL_ERROR1("[%s]: ERROR: THH_hob_get_hca_hndl failed \n",__FUNCTION__);\r
- return ret;\r
- }\r
- \r
- for (i=0; i< qpm->sqp_info.n_ports; i++)\r
- {\r
- qpm->pkey_tbl[i] = (VAPI_pkey_t*)TQPM_GOOD_ALLOC((sizeof(VAPI_pkey_t)*DEFAULT_PKEY_TBL_SZ)); \r
- \r
- //query the pkey table for all ports \r
- ret = THH_hob_init_pkey_tbl(hca_hndl,i+1,DEFAULT_PKEY_TBL_SZ,&tbl_len_out,qpm->pkey_tbl[i]);\r
- if (ret != HH_OK)\r
- {\r
- if (ret == HH_EAGAIN)\r
- {\r
- TQPM_GOOD_FREE(qpm->pkey_tbl[i],(sizeof(VAPI_pkey_t)*DEFAULT_PKEY_TBL_SZ));\r
- qpm->pkey_tbl[i] = (VAPI_pkey_t*)TQPM_GOOD_ALLOC((sizeof(VAPI_pkey_t)* tbl_len_out)); \r
- ret = THH_hob_init_pkey_tbl(hca_hndl,i+1,tbl_len_out,&tbl_len_out,qpm->pkey_tbl[i]);\r
- if (ret != HH_OK)\r
- {\r
- destroy_tbl = TRUE;\r
- }\r
- \r
- }else destroy_tbl = TRUE; \r
- }\r
- \r
- if (destroy_tbl)\r
- {\r
- MTL_ERROR1("[%s]: ERROR: THH_hob_get_pkey_tbl failed for port %d\n",__FUNCTION__,i+1); \r
- TQPM_GOOD_FREE(qpm->pkey_tbl[i],(sizeof(VAPI_pkey_t)*tbl_len_out));\r
- qpm->pkey_tbl[i] = NULL;\r
- qpm->pkey_tbl_sz[i] = 0;\r
- }else \r
- {\r
- if ( qpm->pkey_tbl[i][0] == 0 )\r
- {\r
- qpm->pkey_tbl[i][0] = 0xffff;\r
- }\r
- qpm->pkey_tbl_sz[i] = tbl_len_out;\r
- }\r
- \r
- destroy_tbl = FALSE;\r
- }\r
- \r
- //TBD: ret for one port failure\r
- MT_RETURN(ret);\r
-}\r
-\r
-/************************************************************************/\r
-static MT_bool copy_port_props(TQPM_t* qpm, const THH_qpm_init_t* init_attr_p)\r
-{\r
- MT_bool ok = TRUE;\r
- const THH_port_init_props_t* in_port_props = init_attr_p->port_props;\r
- if (in_port_props)\r
- {\r
- unsigned int n_ports = init_attr_p->n_ports;\r
- THH_port_init_props_t* props = TNMALLOC(THH_port_init_props_t, n_ports);\r
- if (props)\r
- {\r
- memcpy(props, in_port_props, n_ports * sizeof(THH_port_init_props_t));\r
- qpm->sqp_info.port_props = props;\r
- }\r
- else\r
- {\r
- MTL_ERROR1(MT_FLFMT("Allocating port_props (%d) failed"), n_ports);\r
- ok = FALSE;\r
- }\r
- } else {\r
- qpm->sqp_info.port_props = NULL;\r
- }\r
- MTL_DEBUG4(MT_FLFMT("copy_port_props: qpm=0x%p, ok=%d"), qpm, ok);\r
- return ok;\r
-} /* copy_port_props */\r
-\r
-\r
-\r
-/************************************************************************/\r
-static HH_ret_t conf_special_qps(TQPM_t* qpm)\r
-{\r
- HH_ret_t rc = HH_OK;\r
- static const VAPI_special_qp_t qp01[2] = {VAPI_SMI_QP, VAPI_GSI_QP};\r
- Special_QPs* sqp = &qpm->sqp_info;\r
- unsigned int n_ports = sqp->n_ports;\r
- IB_wqpn_t qpn = sqp->first_sqp_qpn;\r
- unsigned ti;\r
- for (ti = 0; (ti != 2) && (rc == HH_OK); ++ti, qpn += n_ports)\r
- {\r
- VAPI_special_qp_t qp_type = qp01[ti];\r
- THH_cmd_status_t cmd_rc = \r
- THH_cmd_CONF_SPECIAL_QP(qpm->cmd_if, qp_type, qpn);\r
- switch(cmd_rc) {\r
- case THH_CMD_STAT_OK:\r
- rc = HH_OK;\r
- break;\r
- case THH_CMD_STAT_EINTR:\r
- rc = HH_EINTR;\r
- break;\r
- default:\r
- MTL_ERROR1(MT_FLFMT("THH_cmd_CONF_SPECIAL_QP ti=%d, qpn=0x%x, crc=%d=%s"),\r
- ti, qpn, cmd_rc, str_THH_cmd_status_t(cmd_rc));\r
- rc = HH_EFATAL;\r
- }\r
- }\r
- MTL_DEBUG4(MT_FLFMT("rc=%d"), rc);\r
- return rc;\r
-} /* conf_special_qps */\r
-\r
-\r
-/************************************************************************/\r
-/* We ensure allocating and freeing DDR memory of sizes\r
- * that are least native page size. The rational is that this is \r
- * the minimal mappable memory.\r
- */\r
-static MT_size_t complete_pg_sz(MT_size_t sz)\r
-{\r
- MTL_DEBUG4(MT_FLFMT("complete_pg_sz: sz="SIZE_T_FMT), sz);\r
- if ((sz & native_page_low_mask) != 0)\r
- {\r
- MTL_DEBUG4(MT_FLFMT("fixing up non page-aligned size="SIZE_T_FMT), sz);\r
- sz &= ~((MT_size_t)native_page_low_mask);\r
- sz += native_page_size;\r
- MTL_DEBUG4(MT_FLFMT("complete_pg_sz: enlarging to sz="SIZE_T_FMT), sz);\r
- }\r
- return sz;\r
-} /* complete_pg_sz */\r
-\r
-\r
-/************************************************************************/\r
-/* We ensure the buffer completely falls within a 4Gb block.\r
- * Now, 4G = 4*1*K*1K*1K = 4*1024^3 = 2^(2+3*10) = 2^32 ==> 32 bits.\r
- * We take advantage of being able to shift right by WQE_CHUNK_SIZE_LOG2 bits.\r
- * So instead of testing 32-bit overflow,\r
- * we test (32-WQE_CHUNK_SIZE_LOG2)-bit overflow.\r
- * Thus being able to test using 32 bits calculations.\r
- */\r
-static MT_bool within_4GB(MT_virt_addr_t buf, MT_size_t sz)\r
-{\r
- static const unsigned int shift_4GdivWQCZ = 32 - WQE_CHUNK_SIZE_LOG2;\r
- MT_virt_addr_t bbeg_rsh = buf >> WQE_CHUNK_SIZE_LOG2;\r
- MT_virt_addr_t bend_rsh = bbeg_rsh + (sz >> WQE_CHUNK_SIZE_LOG2);\r
- MT_bool same_4GB = ((bbeg_rsh >> shift_4GdivWQCZ) ==\r
- (bend_rsh >> shift_4GdivWQCZ));\r
- MTL_DEBUG4(MT_FLFMT("same_4GB=%d"), same_4GB);\r
- return same_4GB;\r
-} /* within_4GB */\r
-\r
-\r
-/************************************************************************/\r
-/* If buffer is supplied, validate address.\r
- * If null buffer supplied, alloc a physical DDR buffer and map it.\r
- * We have to check for 'Within 4GB' anyway.\r
- * When mapping, we allow a second chance to pass the 4GB restriction.\r
- * If allocated, we also return the physical memory address.\r
- */\r
-static HH_ret_t check_make_wqes_buf(\r
- THH_qpm_t qpm, \r
- THH_qp_ul_resources_t* qp_ul_resources_p,\r
- HH_pd_hndl_t pd,\r
- MOSAL_protection_ctx_t* ctx_p,\r
- MT_phys_addr_t* pa_p\r
-)\r
-{\r
- HH_ret_t rc = HH_OK;\r
- MT_virt_addr_t wqes_buf = qp_ul_resources_p->wqes_buf;\r
- MT_size_t buf_sz = qp_ul_resources_p->wqes_buf_sz;\r
-\r
- MTL_DEBUG4(MT_FLFMT("wqes_buf="VIRT_ADDR_FMT", buf_sz="SIZE_T_FMT), wqes_buf, buf_sz);\r
- if (wqes_buf != 0)\r
- {\r
- MT_virt_addr_t unalligned_bits = wqes_buf & WQE_CHUNK_MASK;\r
- if ((unalligned_bits != 0) || !within_4GB(wqes_buf, buf_sz))\r
- {\r
- wqes_buf = 0;\r
- rc = HH_EINVAL_PARAM;\r
- }\r
- }\r
- else if (buf_sz != 0) /* When uses SRQ, buf_sz may be 0 */\r
- {\r
- rc = THH_uldm_get_protection_ctx(qpm->uldm, pd, ctx_p);\r
- if (rc == HH_OK)\r
- {\r
- qp_ul_resources_p->wqes_buf_sz = buf_sz =\r
- complete_pg_sz(buf_sz); /* fixed up size returned */\r
- rc = THH_ddrmm_alloc(qpm->ddrmm, buf_sz, native_page_shift, pa_p);\r
- MTL_DEBUG4(MT_FLFMT("rc=%d"), rc);\r
- if (rc == HH_OK)\r
- {\r
- static const MOSAL_mem_flags_t\r
- mem_flags = MOSAL_MEM_FLAGS_NO_CACHE |\r
- MOSAL_MEM_FLAGS_PERM_READ |\r
- MOSAL_MEM_FLAGS_PERM_WRITE;\r
- MT_virt_addr_t va_1stmapped = wqes_buf = (MT_virt_addr_t)\r
- MOSAL_map_phys_addr(*pa_p, buf_sz, mem_flags, *ctx_p);\r
- if (wqes_buf && !within_4GB(wqes_buf, buf_sz))\r
- { /* bad luck? give mapping another chance, to fit, before unmap! */\r
- wqes_buf = (MT_virt_addr_t)MOSAL_map_phys_addr(\r
- *pa_p, buf_sz, mem_flags, *ctx_p);\r
- MOSAL_unmap_phys_addr(*ctx_p, (MT_virt_addr_t)va_1stmapped, buf_sz);\r
- if (wqes_buf && !within_4GB(wqes_buf, buf_sz))\r
- {\r
- MOSAL_unmap_phys_addr(*ctx_p, (MT_virt_addr_t)wqes_buf, buf_sz);\r
- wqes_buf = 0;\r
- }\r
- }\r
- qp_ul_resources_p->wqes_buf = wqes_buf;\r
- if (wqes_buf == 0)\r
- {\r
- THH_ddrmm_free(qpm->ddrmm, *pa_p, buf_sz);\r
- *pa_p = 0;\r
- rc = HH_EAGAIN;\r
- }\r
- }\r
- }\r
- }\r
- return rc;\r
-} /* check_make_wqes_buf */\r
-\r
-\r
-/************************************************************************/\r
-static MT_bool attr_hh2swqpc(\r
- const HH_qp_init_attr_t* hh_attr,\r
- MT_bool mlx,\r
- TQPM_sw_qpc_t* sw_qpc_p\r
-)\r
-{\r
- MT_bool ok = TRUE;\r
-\r
- memset(sw_qpc_p, 0, sizeof(TQPM_sw_qpc_t));\r
- sw_qpc_p->pd = hh_attr->pd;\r
- sw_qpc_p->rdd = hh_attr->rdd;\r
- sw_qpc_p->srqn = hh_attr->srq;\r
- sw_qpc_p->cqn_snd = hh_attr->sq_cq;\r
- sw_qpc_p->cqn_rcv = hh_attr->rq_cq;\r
- sw_qpc_p->cap = hh_attr->qp_cap;\r
-\r
- /* st THH_service_type_t */\r
- if (mlx)\r
- {\r
- sw_qpc_p->st = THH_ST_MLX;\r
- }\r
- else\r
- {\r
- switch (hh_attr->ts_type)\r
- {\r
- case VAPI_TS_RC: sw_qpc_p->st = THH_ST_RC; break;\r
-// JPM: RD and UC are not currently supported\r
-// case VAPI_TS_RD: summ_p->st = THH_ST_RD; break;\r
- case VAPI_TS_UC: sw_qpc_p->st = THH_ST_UC; break;\r
- case VAPI_TS_UD: sw_qpc_p->st = THH_ST_UD; break;\r
- default: ok = FALSE; MTL_ERROR1(MT_FLFMT("ts_type=%d"), hh_attr->ts_type);\r
- }\r
- }\r
-\r
- sw_qpc_p->ssc = (hh_attr->sq_sig_type == VAPI_SIGNAL_ALL_WR);\r
- sw_qpc_p->rsc = (hh_attr->rq_sig_type == VAPI_SIGNAL_ALL_WR);\r
- return ok;\r
-} /* attr_summary */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t create_qp(\r
- THH_qpm_t qpm, /* IN */\r
- HH_qp_init_attr_t* init_attr_p, /* IN */\r
- MT_bool mlx, /* IN */\r
- THH_qp_ul_resources_t* qp_ul_resources_p, /* IO */\r
- TQPM_sw_qpc_t* new_qp_p /* IN */\r
-)\r
-{\r
- VAPI_lkey_t lkey;\r
- HH_ret_t rc, mrc = HH_ERR; \r
- MT_phys_addr_t pa_ddr = 0;\r
- MOSAL_protection_ctx_t ctx;\r
-\r
- rc = (attr_hh2swqpc(init_attr_p, mlx, new_qp_p) ? HH_OK : HH_EINVAL_SERVICE_TYPE);\r
- if (rc == HH_OK)\r
- {\r
- rc = check_make_wqes_buf(qpm, qp_ul_resources_p, init_attr_p->pd, \r
- &ctx, &pa_ddr);\r
- }\r
- if ((rc == HH_OK) && (qp_ul_resources_p->wqes_buf_sz != 0))\r
- /* If there is WQEs buffer to register */\r
- {\r
- THH_internal_mr_t params;\r
- memset(¶ms, 0, sizeof(params));\r
- params.start = qp_ul_resources_p->wqes_buf,\r
- params.size = qp_ul_resources_p->wqes_buf_sz;\r
- params.pd = init_attr_p->pd;\r
- params.vm_ctx = ctx;\r
- params.force_memkey = FALSE;\r
- params.memkey = (VAPI_lkey_t)0;\r
- if (pa_ddr)\r
- {\r
- VAPI_phy_addr_t phy_array = (VAPI_phy_addr_t)pa_ddr; /* 1 element array - for register internal */\r
- params.num_bufs = 1;\r
- params.phys_buf_lst = &phy_array; /* Addresses of automatic */\r
- params.buf_sz_lst = ¶ms.size; /* automatic variables! */\r
- }\r
- mrc = THH_mrwm_register_internal(qpm->mrwm_internal, ¶ms, &lkey);\r
- rc = mrc;\r
- }\r
- if (rc == HH_OK)\r
- {\r
- /* save parameters in this manager */\r
- new_qp_p->state= VAPI_RESET;\r
- new_qp_p->wqes_buf= qp_ul_resources_p->wqes_buf;\r
- new_qp_p->wqes_buf_sz= qp_ul_resources_p->wqes_buf_sz;\r
- new_qp_p->uar_index= qp_ul_resources_p->uar_index;\r
- new_qp_p->lkey = (qp_ul_resources_p->wqes_buf_sz != 0) ? lkey : 0/*Invalid*/;\r
- new_qp_p->pa_ddr = pa_ddr;\r
- }\r
- if (rc != HH_OK)\r
- { /* clean */\r
- if (mrc == HH_OK) { THH_mrwm_deregister_mr(qpm->mrwm_internal, lkey); }\r
- if (pa_ddr != 0)\r
- {\r
- MT_size_t wqes_buf_sz = qp_ul_resources_p->wqes_buf_sz; /* pg complete */\r
- MOSAL_unmap_phys_addr(ctx, (MT_virt_addr_t)qp_ul_resources_p->wqes_buf, \r
- wqes_buf_sz);\r
- THH_ddrmm_free(qpm->ddrmm, pa_ddr, wqes_buf_sz);\r
- }\r
- }\r
- MTL_DEBUG4(MT_FLFMT("rc=%d, ul_res->wqes_buf="VIRT_ADDR_FMT), \r
- rc, qp_ul_resources_p->wqes_buf);\r
- return rc;\r
-} /* create_qp */\r
-\r
-\r
-\r
-\r
-/************************************************************************/\r
-static void udav2qpc_path(const VAPI_ud_av_t* av, THH_address_path_t* path)\r
-{\r
- path->sl = av->sl;\r
- path->my_lid_path_bits = av->src_path_bits;\r
- path->flow_label = av->flow_label;\r
- path->hop_limit = av->hop_limit;\r
- path->max_stat_rate = (av->static_rate == 0) ? 0 : 1 ; /* IPD=0 -> 0 , IPD=3 -> 1, everything else ->1 */\r
- path->g = av->grh_flag;\r
- path->mgid_index = av->sgid_index;\r
- path->rlid = av->dlid;\r
- path->tclass = av->traffic_class;\r
- memcpy(&path->rgid, &av->dgid, sizeof(path->rgid));\r
-} /* udav2qpc_path */\r
-\r
-\r
-/************************************************************************/\r
-static IB_mtu_t log2mtu_to_ib_mtu(u_int8_t lg2mtu)\r
-{\r
- IB_mtu_t ib_mtu = TAVOR_LOG2_MAX_MTU;\r
- switch (lg2mtu)\r
- {\r
- case 8: ib_mtu = MTU256; break;\r
- case 9: ib_mtu = MTU512; break;\r
- case 10: ib_mtu = MTU1024; break;\r
- case 11: ib_mtu = MTU2048; break;\r
- case 12: ib_mtu = MTU4096; break;\r
- default:\r
- MTL_ERROR1(MT_FLFMT("Unsupported MTU for log2(max_msg)=%d, use ibmtu=%d"),\r
- lg2mtu, ib_mtu);\r
- }\r
- return ib_mtu;\r
-} /* log2mtu_to_ib_mtu */\r
-\r
-\r
-/************************************************************************/\r
-static void qpc_path2udav(const THH_address_path_t* path, VAPI_ud_av_t* av)\r
-{\r
- av->sl = path->sl;\r
- av->src_path_bits = path->my_lid_path_bits;\r
- av->flow_label = path->flow_label;\r
- av->hop_limit = path->hop_limit;\r
- av->static_rate = (path->max_stat_rate == 0) ? 0 : 3;\r
- av->grh_flag = path->g;\r
- av->sgid_index = path->mgid_index;\r
- av->dlid = path->rlid;\r
- av->traffic_class = path->tclass;\r
- memcpy(&av->dgid, &path->rgid, sizeof(path->rgid));\r
-} /* qpc_path2udav */\r
-\r
-\r
-/************************************************************************/\r
-static void qpc_default(THH_qpee_context_t* qpc_p)\r
-{\r
- memset(qpc_p, 0, sizeof(THH_qpee_context_t));\r
- qpc_p->ver = 0;\r
- //qpc_p->te = 1;\r
- /*qpc_p->ce = 1; */\r
- qpc_p->ack_req_freq = TUNABLE_ACK_REQ_FREQ;\r
- qpc_p->flight_lim = TUNABLE_FLIGHT_LIMIT;\r
- qpc_p->ric = FALSE; /* Provide E2E credits in ACKs */\r
- qpc_p->sic = FALSE; /* Consider to E2E credits */\r
- qpc_p->msg_max = 31; /* HW checks message <= (QP MTU, UD msg_max) */\r
- qpc_p->mtu = MTU2048;\r
-} /* qpc_default */\r
-\r
-\r
-/************************************************************************/\r
-/* Initialize THH_qpee_context_t structure with\r
- * attributes given or computed upon QP creation.\r
- *\r
- */\r
-static void init2qpc_using_create_values(\r
- const TQPM_sw_qpc_t* qp_p,\r
- THH_qpee_context_t* qpc_p\r
-)\r
-{\r
-\r
- qpc_p->st = qp_p->st;\r
- qpc_p->pd = qp_p->pd;\r
- qpc_p->rdd = qp_p->rdd;\r
- qpc_p->srq = (qp_p->srqn != HH_INVAL_SRQ_HNDL); \r
- qpc_p->srqn = qp_p->srqn;\r
- qpc_p->cqn_snd = qp_p->cqn_snd;\r
- qpc_p->cqn_rcv = qp_p->cqn_rcv;\r
-/*** warning C4242: '=' : conversion from 'const unsigned int' to 'MT_bool', possible loss of data ***/\r
- qpc_p->ssc = (MT_bool)qp_p->ssc;\r
-/*** warning C4242: '=' : conversion from 'const unsigned int' to 'MT_bool', possible loss of data ***/\r
- qpc_p->rsc = (MT_bool)qp_p->rsc;\r
-\r
- qpc_p->usr_page = qp_p->uar_index;\r
- qpc_p->wqe_base_adr = (sizeof(MT_virt_addr_t) <= 4 \r
- ? (u_int32_t)0\r
- : (u_int32_t)(((u_int64_t)qp_p->wqes_buf) >> 32));\r
- qpc_p->wqe_lkey = qp_p->lkey;\r
-} /* init2qpc_using_create_values */\r
-\r
-\r
-\r
-/************************************************************************/\r
-static void qpc2vapi_attr(\r
- const THH_qpee_context_t* qpc_p, \r
- VAPI_qp_attr_t* qp_attr_p\r
-)\r
-{\r
- VAPI_rdma_atom_acl_t aflags = 0;\r
- memset(qp_attr_p, 0, sizeof(*qp_attr_p));\r
- qp_attr_p->qp_state = qpc_p->state;\r
- qp_attr_p->sq_draining = qpc_p->sq_draining;\r
- qp_attr_p->qp_num = qpc_p->local_qpn_een;\r
- aflags |= (qpc_p->rae ? VAPI_EN_REM_ATOMIC_OP : 0);\r
- aflags |= (qpc_p->rwe ? VAPI_EN_REM_WRITE : 0);\r
- aflags |= (qpc_p->rre ? VAPI_EN_REM_READ : 0);\r
- qp_attr_p->remote_atomic_flags = aflags;\r
- qp_attr_p->qkey = qpc_p->q_key;\r
- qp_attr_p->path_mtu = qpc_p->mtu;\r
- switch (qpc_p->pm_state)\r
- {\r
- case PM_STATE_MIGRATED: qp_attr_p->path_mig_state = VAPI_MIGRATED; break;\r
- case PM_STATE_REARM: qp_attr_p->path_mig_state = VAPI_REARM; break;\r
- case PM_STATE_ARMED: qp_attr_p->path_mig_state = VAPI_ARMED; break;\r
- default: ; /* hmmm... */\r
- }\r
- qp_attr_p->rq_psn = qpc_p->next_rcv_psn;\r
- qp_attr_p->sq_psn = qpc_p->next_send_psn;\r
- qp_attr_p->qp_ous_rd_atom = ((qpc_p->rae || qpc_p->rre)\r
- ? 1u << qpc_p->rra_max : 0);\r
- qp_attr_p->ous_dst_rd_atom = ((qpc_p->sre==0)&&(qpc_p->sae)==0) ? 0 : 1u << qpc_p->sra_max;\r
- qp_attr_p->min_rnr_timer = qpc_p->min_rnr_nak;\r
- qp_attr_p->dest_qp_num = qpc_p->remote_qpn_een;\r
- qp_attr_p->pkey_ix = qpc_p->primary_address_path.pkey_index;\r
- qp_attr_p->port = qpc_p->primary_address_path.port_number;\r
- qpc_path2udav(&qpc_p->primary_address_path, &qp_attr_p->av);\r
- qp_attr_p->timeout = qpc_p->primary_address_path.ack_timeout;\r
- qp_attr_p->retry_count = qpc_p->retry_count;\r
- qp_attr_p->rnr_retry = qpc_p->primary_address_path.rnr_retry;\r
- qp_attr_p->alt_pkey_ix = qpc_p->alternative_address_path.pkey_index;\r
- qp_attr_p->alt_port = qpc_p->alternative_address_path.port_number;\r
- qpc_path2udav(&qpc_p->alternative_address_path, &qp_attr_p->alt_av);\r
- qp_attr_p->alt_timeout = qpc_p->alternative_address_path.ack_timeout;\r
- /* qp_attr_p->alt_retry_count = qpc_p->alternative_address_path. */\r
- //qp_attr_p->alt_rnr_retry = qpc_p->alternative_address_path.rnr_retry;\r
-} /* qpc2vapi_attr */\r
-\r
-\r
-\r
-/************************************************************************/\r
-/* Transfer VAPI_qp_attr_t struct to THH_qpee_context_t struct \r
- * Consider the caller attr_mask for generate opt_mask for the \r
- * command interface.\r
- */\r
-static HH_ret_t vapi2qpc_modify(\r
- THH_qpm_t qpm,\r
- TQPM_sw_qpc_t* qp_p,\r
- const VAPI_qp_attr_t* attr_p,\r
- const THH_qpee_transition_t trans,\r
- const u_int32_t attr_mask,\r
- THH_qpee_context_t* qpc_p,\r
- u_int32_t* opt_mask_p\r
-)\r
-{\r
- HH_ret_t rc = HH_OK;\r
- u_int32_t opt_mask = 0;\r
- IB_port_t sqp_port;\r
- MT_bool is_sqp = (is_sqp0(qpm,qp_p->qpn,&sqp_port) || is_sqp1(qpm,qp_p->qpn,&sqp_port));\r
- \r
- qpc_p->st= qp_p->st;\r
-\r
- if (attr_mask & QP_ATTR_CAP)\r
- {\r
- /* resizing WQ size (QP size) not supported */\r
- rc = HH_ENOSYS;\r
- goto done;\r
- }\r
- \r
- if (attr_mask & QP_ATTR_SCHED_QUEUE) {\r
- qpc_p->sched_queue = attr_p->sched_queue;\r
- opt_mask |= TAVOR_IF_QPEE_OPTPAR_SCHED_QUEUE; /* For INIT2RTR and SQD2RTS */\r
- } else { \r
- /* The default assignment below will be effective only on RST2INIT \r
- * when sched_queue is not explicitly provided (but is required parameter) */\r
- qpc_p->sched_queue = attr_p->av.sl; \r
- }\r
- \r
- /* if (1 || attr_mask & QP_ATTR_QP_NUM) */\r
- {\r
- qpc_p->local_qpn_een = attr_p->qp_num;\r
- }\r
- qpc_p->sae = qpc_p->swe = qpc_p->sre = 1; /* Enforcement only on responder side (per IB) */\r
- \r
- \r
- if (attr_mask & QP_ATTR_PKEY_IX)\r
- {\r
- /* error should have been checked in upper level, so just C-implicit mask */\r
-/*** warning C4242: '=' : conversion from 'const VAPI_pkey_ix_t' to 'u_int8_t', possible loss of data ***/\r
- qpc_p->primary_address_path.pkey_index = (u_int8_t)attr_p->pkey_ix;\r
- opt_mask |= TAVOR_IF_QPEE_OPTPAR_PKEY_INDEX;\r
- }\r
- \r
- if ((attr_mask & QP_ATTR_PORT) ||\r
- ((is_sqp == TRUE) && (trans == TAVOR_IF_CMD_RST2INIT_QPEE)) ) { \r
- /* "The following attributes are not applicable if the QP specified is a Special QP:"... */\r
- /* (IB-spec. 1.1: Page 512) - But Tavor requires them for SQ association */\r
-\r
- /* according to change in tavor_if_defs.h (23.12.2002 - port was seperated from AV). */\r
- opt_mask |= TAVOR_IF_QPEE_OPTPAR_PORT_NUM;\r
- // no port changes for special QPs!\r
- if ( is_sqp == FALSE ) {\r
- qpc_p->primary_address_path.port_number = attr_p->port;\r
- } else {\r
- qpc_p->primary_address_path.port_number = sqp_port;\r
- }\r
- }\r
-\r
- /* patch for vl15 problem */\r
- /* TBD sched_queue based on ULP ??? */\r
- /* for now qp0(sm) - 0x8, all others = 0x0;\r
- */ \r
- if(is_sqp0(qpm,qp_p->qpn,&sqp_port))\r
- { \r
- qpc_p->sched_queue = 0x8; \r
- opt_mask |= TAVOR_IF_QPEE_OPTPAR_SCHED_QUEUE;\r
- }\r
- else\r
- {\r
- qpc_p->sched_queue = attr_p->av.sl;\r
- opt_mask |= TAVOR_IF_QPEE_OPTPAR_SCHED_QUEUE;\r
- }\r
-\r
- if (attr_mask & QP_ATTR_QKEY)\r
- {\r
- qpc_p->q_key = attr_p->qkey;\r
- opt_mask |= TAVOR_IF_QPEE_OPTPAR_Q_KEY;\r
- }\r
- if (attr_mask & QP_ATTR_AV)\r
- {\r
- udav2qpc_path(&attr_p->av, &qpc_p->primary_address_path);\r
- opt_mask |= TAVOR_IF_QPEE_OPTPAR_PRIMARY_ADDR_PATH;\r
- }\r
- \r
- // special QPs get msg_max & MTU of UD QPs.\r
- if (qp_p->st == THH_ST_UD || is_sqp )\r
- {\r
- qpc_p->msg_max = TAVOR_LOG2_MAX_MTU;\r
- qpc_p->mtu = log2mtu_to_ib_mtu(TAVOR_LOG2_MAX_MTU);\r
- }\r
- else if (attr_mask & QP_ATTR_PATH_MTU) {\r
- { /* See check_constants() that verifies using following shift is fine. */\r
- if (((1ul << attr_p->path_mtu) & valid_tavor_ibmtu_mask) != 0)\r
- { \r
- qpc_p->mtu = attr_p->path_mtu;\r
- }\r
- else\r
- {\r
- MTL_ERROR1(MT_FLFMT("Unsupported mtu=%d value"), attr_p->path_mtu);\r
- rc = HH_EINVAL_PARAM;\r
- }\r
- }\r
- }\r
- \r
- if (attr_mask & QP_ATTR_TIMEOUT){\r
- qpc_p->primary_address_path.ack_timeout = attr_p->timeout;\r
- /*sqd->rts: this attr is optional , rtr->rts: this attr is mandatory */\r
- opt_mask |= TAVOR_IF_QPEE_OPTPAR_ACK_TIMEOUT;\r
- }\r
- \r
- if (attr_mask & QP_ATTR_RETRY_COUNT)\r
- {\r
- /* according to change in tavor_if_defs.h (23.12.2002 - retry_count was seperated from AV). */\r
- opt_mask |= TAVOR_IF_QPEE_OPTPAR_RETRY_COUNT;\r
- qpc_p->retry_count = attr_p->retry_count;\r
- }\r
- \r
- if (attr_mask & QP_ATTR_RNR_RETRY) \r
- {\r
- qpc_p->primary_address_path.rnr_retry = attr_p->rnr_retry;\r
- opt_mask |= TAVOR_IF_QPEE_OPTPAR_RNR_RETRY;\r
- qpc_p->alternative_address_path.rnr_retry = attr_p->rnr_retry;\r
- opt_mask |= TAVOR_IF_QPEE_OPTPAR_ALT_RNR_RETRY;\r
- }\r
- /*if (attr_mask & QP_ATTR_RQ_PSN)*/\r
- {\r
- qpc_p->next_rcv_psn = attr_p->rq_psn;\r
- }\r
- \r
- if (attr_mask & QP_ATTR_REMOTE_ATOMIC_FLAGS)\r
- {\r
- VAPI_rdma_atom_acl_t flags = attr_p->remote_atomic_flags;\r
- qpc_p->rae = (flags & VAPI_EN_REM_ATOMIC_OP) ? 1 : 0;\r
- qpc_p->rwe = (flags & VAPI_EN_REM_WRITE) ? 1 : 0;\r
- qpc_p->rre = (flags & VAPI_EN_REM_READ) ? 1 : 0;\r
-\r
- /* if current outstanding rd-atomic value is 0, disable rdma-read and atomic capability*/\r
- if ((trans == QPEE_TRANS_RTR2RTS)||(trans==QPEE_TRANS_RTS2RTS)||(trans==QPEE_TRANS_SQERR2RTS)) {\r
- if (qp_p->qp_ous_rd_atom == 0) {\r
- MTL_DEBUG3(MT_FLFMT("%s: setting rae/rre to zero, because qp_ous_rd_atom is 0. Trans=%d"), \r
- __func__,trans);\r
- qpc_p->rae = qpc_p->rre = 0;\r
- }\r
- }\r
- opt_mask |= TAVOR_IF_QPEE_OPTPAR_RRE |\r
- TAVOR_IF_QPEE_OPTPAR_RAE |\r
- TAVOR_IF_QPEE_OPTPAR_REW;\r
-\r
- }\r
- \r
- if (attr_mask & QP_ATTR_QP_OUS_RD_ATOM)\r
- {\r
- if (attr_p->qp_ous_rd_atom != 0)\r
- {\r
- qpc_p->rra_max = ceil_log2(attr_p->qp_ous_rd_atom);\r
- if (qpc_p->rra_max > qpm->log2_max_outs_rdma_atom)\r
- {\r
- MTL_ERROR1(MT_FLFMT("Error rra_max=0x%x > QPM's log2_max=0x%x, attr_p->qp_ous_rd_atom = 0x%x"),\r
- qpc_p->rra_max, qpm->log2_max_outs_rdma_atom,attr_p->qp_ous_rd_atom);\r
- rc = HH_EINVAL_PARAM;\r
- } else {\r
- if ((trans==QPEE_TRANS_SQD2RTS)&&(qp_p->qp_ous_rd_atom==0)) {\r
- /* outstanding rd/atomics was previously zero, so need to restore rd/atomic flags */\r
- MTL_DEBUG3(MT_FLFMT("%s: restoring rae/rre to requested values, because qp_ous_rd_atom changed from 0. Trans=%d"), \r
- __func__,trans);\r
- qpc_p->rae = (qp_p->remote_atomic_flags & VAPI_EN_REM_ATOMIC_OP) ? 1 : 0;\r
- qpc_p->rre = (qp_p->remote_atomic_flags & VAPI_EN_REM_READ) ? 1 : 0;\r
- opt_mask |= TAVOR_IF_QPEE_OPTPAR_RRE | TAVOR_IF_QPEE_OPTPAR_RAE;\r
- }\r
- }\r
- } else {\r
- qpc_p->rra_max = 0;\r
- if (qpc_p->rre || qpc_p->rae) \r
- {\r
- MTL_ERROR1(MT_FLFMT("%s: Warning: resetting rre+rae bits for qp_ous_rd_atom=0. Trans=%d"),\r
- __func__, trans);\r
- qpc_p->rre = qpc_p->rae = 0;\r
- opt_mask |= (TAVOR_IF_QPEE_OPTPAR_RRE | TAVOR_IF_QPEE_OPTPAR_RAE);\r
- }\r
- }\r
- opt_mask |= TAVOR_IF_QPEE_OPTPAR_RRA_MAX;\r
- }\r
- \r
-\r
- if (attr_mask & QP_ATTR_OUS_DST_RD_ATOM)\r
- {\r
- qpc_p->sra_max = (attr_p->ous_dst_rd_atom == 0) ? 0: floor_log2(attr_p->ous_dst_rd_atom);\r
- qpc_p->swe = 1;\r
- if ((attr_p->ous_dst_rd_atom)==0) {\r
- qpc_p->sre = qpc_p->sae = 0;\r
- } else {\r
- if (qpc_p->sra_max > qpm->log2_max_outs_dst_rd_atom)\r
- {\r
- MTL_ERROR1(MT_FLFMT("Error sra_max=0x%x > QPM's log2_max=0x%x, attr_p->qp_ous_dst_rd_atom = 0x%x"),\r
- qpc_p->sra_max, qpm->log2_max_outs_dst_rd_atom,attr_p->ous_dst_rd_atom);\r
- rc = HH_EINVAL_PARAM;\r
- }\r
- qpc_p->sre = qpc_p->sae = 1;\r
- }\r
- opt_mask |= TAVOR_IF_QPEE_OPTPAR_SRA_MAX;\r
- }\r
- \r
- if (attr_mask & QP_ATTR_ALT_PATH)\r
- {\r
- udav2qpc_path(&attr_p->alt_av, &qpc_p->alternative_address_path);\r
- opt_mask |= TAVOR_IF_QPEE_OPTPAR_ALT_ADDR_PATH;\r
- //}\r
- //if (attr_mask & QP_ATTR_ALT_TIMEOUT)\r
- //{\r
- qpc_p->alternative_address_path.ack_timeout = attr_p->alt_timeout;\r
- //opt_mask |= TAVOR_IF_QPEE_OPTPAR_ALT_ADDR_PATH;\r
- //}\r
- //if (attr_mask & QP_ATTR_ALT_RETRY_COUNT)\r
- //{\r
-// qpc_p->alternative_address_path.ack_timeout = attr_p->alt_timeout;\r
- //opt_mask |= TAVOR_IF_QPEE_OPTPAR_ALT_ADDR_PATH;\r
- //}\r
- //if (attr_mask & QP_ATTR_ALT_RNR_RETRY)\r
- //{\r
- /* according to change in tavor_if_defs.h (23.12.2002). */\r
- // qpc_p->alternative_address_path.rnr_retry = attr_p->alt_rnr_retry;\r
- // opt_mask |= TAVOR_IF_QPEE_OPTPAR_ALT_RNR_RETRY;\r
- \r
- //}\r
- //if (attr_mask & QP_ATTR_ALT_PKEY_IX)\r
- //{\r
-/*** warning C4242: '=' : conversion from 'const VAPI_pkey_ix_t' to 'u_int8_t', possible loss of data ***/\r
- qpc_p->alternative_address_path.pkey_index = (u_int8_t)attr_p->alt_pkey_ix;\r
- //opt_mask |= TAVOR_IF_QPEE_OPTPAR_ALT_ADDR_PATH;\r
- //}\r
- //if (attr_mask & QP_ATTR_ALT_PORT)\r
- //{\r
- qpc_p->alternative_address_path.port_number = attr_p->alt_port;\r
- //opt_mask |= TAVOR_IF_QPEE_OPTPAR_ALT_ADDR_PATH;\r
- }\r
- if (attr_mask & QP_ATTR_MIN_RNR_TIMER)\r
- {\r
-/*** warning C4242: '=' : conversion from 'const IB_rnr_nak_timer_code_t' to 'u_int8_t', possible loss of data ***/\r
- qpc_p->min_rnr_nak = (u_int8_t)attr_p->min_rnr_timer;\r
- opt_mask |= TAVOR_IF_QPEE_OPTPAR_RNR_TIMEOUT;\r
- }\r
- if (attr_mask & QP_ATTR_SQ_PSN)\r
- {\r
- qpc_p->next_send_psn = attr_p->sq_psn;\r
- }\r
- \r
- if (attr_mask & QP_ATTR_PATH_MIG_STATE)\r
- {\r
- switch (attr_p->path_mig_state)\r
- {\r
- case VAPI_MIGRATED: qpc_p->pm_state = PM_STATE_MIGRATED; break;\r
- case VAPI_REARM: qpc_p->pm_state = PM_STATE_REARM; break;\r
- case VAPI_ARMED: qpc_p->pm_state = PM_STATE_ARMED; break;\r
- default: rc = HH_EINVAL_PARAM;\r
- }\r
- opt_mask |= TAVOR_IF_QPEE_OPTPAR_PM_STATE;\r
- } else { /* Default required in order to assure initialization */\r
- qpc_p->pm_state = PM_STATE_MIGRATED;\r
- }\r
- \r
- if (attr_mask & QP_ATTR_DEST_QP_NUM)\r
- {\r
- qpc_p->remote_qpn_een = attr_p->dest_qp_num;\r
- }\r
- *opt_mask_p = opt_mask;\r
-\r
-done:\r
- MTL_DEBUG4(MT_FLFMT("vapi2qpc_modify: rc=%d"), rc);\r
- return rc;\r
-} /* vapi2qpc_modify */\r
-\r
-/************************************************************************/\r
-/* Track rdma/atomic parameter changes \r
- */\r
-static void track_rdma_atomic(\r
- const VAPI_qp_attr_t* attr_p,\r
- const u_int32_t attr_mask,\r
- TQPM_sw_qpc_t* qp_p\r
-)\r
-{\r
- \r
- if (attr_mask & QP_ATTR_REMOTE_ATOMIC_FLAGS)\r
- {\r
- qp_p->remote_atomic_flags = attr_p->remote_atomic_flags;\r
-\r
- }\r
- \r
- if (attr_mask & QP_ATTR_QP_OUS_RD_ATOM)\r
- {\r
- if (attr_p->qp_ous_rd_atom != 0)\r
- {\r
- qp_p->qp_ous_rd_atom = (1<<ceil_log2(attr_p->qp_ous_rd_atom));\r
- } else{\r
- qp_p->qp_ous_rd_atom = 0;\r
- }\r
- }\r
-\r
- if (attr_mask & QP_ATTR_OUS_DST_RD_ATOM)\r
- {\r
- qp_p->ous_dst_rd_atom = attr_p->ous_dst_rd_atom;\r
- }\r
- \r
- return;\r
-} /* vapi2qpc_modify */\r
-\r
-\r
-/************************************************************************/\r
-static HH_ret_t prepare_special_qp(\r
- THH_qpm_t qpm, \r
- IB_wqpn_t qpn,\r
- THH_qpee_transition_t trans\r
-)\r
-{\r
- IB_port_t port = 0; /* regular=0, non-special [1..) */\r
- HH_ret_t rc = HH_OK;\r
- \r
- MTL_DEBUG4(MT_FLFMT("entry point."));\r
- \r
- if (((trans == QPEE_TRANS_INIT2RTR) || (trans == QPEE_TRANS_ERR2RST)) &&\r
- (is_sqp0(qpm,qpn,&port))) \r
- { \r
- if (!qpm->sqp_info.configured)\r
- {\r
- MTL_DEBUG4(MT_FLFMT("calling conf_special_qps() ."));\r
- rc = conf_special_qps(qpm);\r
- if (rc == HH_OK)\r
- {\r
- qpm->sqp_info.configured = TRUE;\r
- }\r
- }\r
- if ((rc == HH_OK) && (qpm->sqp_info.port_props != NULL))\r
- {\r
- THH_cmd_status_t cmd_rc = THH_CMD_STAT_OK;\r
- \r
- MTL_DEBUG1(MT_FLFMT("%s: port = %d, qpn = 0x%x"), __func__, port, qpn);\r
- if( trans == QPEE_TRANS_INIT2RTR && (qpm->port_active[port-1] == FALSE) ) {\r
- cmd_rc = THH_cmd_INIT_IB(qpm->cmd_if, port, \r
- &qpm->sqp_info.port_props[port-1]);\r
- if( cmd_rc == THH_CMD_STAT_OK )\r
- qpm->port_active[port-1] = TRUE;\r
- }\r
- \r
- else if( trans == QPEE_TRANS_ERR2RST && (qpm->port_active[port-1] == TRUE) ) {\r
- cmd_rc = THH_cmd_CLOSE_IB(qpm->cmd_if, port);\r
- if ( cmd_rc == THH_CMD_STAT_OK )\r
- qpm->port_active[port-1] = FALSE;\r
- }\r
-\r
- rc = (CMDRC2HH_ND(cmd_rc));\r
- MTL_DEBUG4(MT_FLFMT("cmd_rc=%d=%s, trans=%d"), \r
- cmd_rc, str_THH_cmd_status_t(cmd_rc), trans);\r
- }\r
- }\r
-\r
- return rc;\r
-} /* prepare_special_qp */\r
-\r
-\r
-/************************************************************************/\r
-/* Following Tavor-PRM 13.6.x optparammask possible bits */\r
-static inline u_int32_t x_optmask(THH_qpee_transition_t t)\r
-{\r
- static const u_int32_t common_mask =\r
- TAVOR_IF_QPEE_OPTPAR_ALT_ADDR_PATH |\r
- TAVOR_IF_QPEE_OPTPAR_ALT_RNR_RETRY |\r
- TAVOR_IF_QPEE_OPTPAR_RRE |\r
- TAVOR_IF_QPEE_OPTPAR_RAE |\r
- TAVOR_IF_QPEE_OPTPAR_REW |\r
- TAVOR_IF_QPEE_OPTPAR_Q_KEY |\r
- TAVOR_IF_QPEE_OPTPAR_RNR_TIMEOUT;\r
-\r
- u_int32_t mask = 0;\r
- switch (t) /* cases of mask=0, use above defauly and commented out */\r
- {\r
- /* case QPEE_TRANS_RST2INIT : mask=0 */\r
- case QPEE_TRANS_INIT2INIT:\r
- mask = \r
- TAVOR_IF_QPEE_OPTPAR_RRE |\r
- TAVOR_IF_QPEE_OPTPAR_RAE |\r
- TAVOR_IF_QPEE_OPTPAR_REW |\r
- TAVOR_IF_QPEE_OPTPAR_Q_KEY |\r
- TAVOR_IF_QPEE_OPTPAR_PORT_NUM | \r
- TAVOR_IF_QPEE_OPTPAR_PKEY_INDEX;\r
- break;\r
-\r
- case QPEE_TRANS_INIT2RTR :\r
- mask = common_mask | TAVOR_IF_QPEE_OPTPAR_PKEY_INDEX | TAVOR_IF_QPEE_OPTPAR_SCHED_QUEUE;\r
- break;\r
-\r
- case QPEE_TRANS_RTR2RTS :\r
- mask = common_mask | TAVOR_IF_QPEE_OPTPAR_PM_STATE;\r
- break;\r
-\r
- case QPEE_TRANS_RTS2RTS :\r
- mask = common_mask | TAVOR_IF_QPEE_OPTPAR_PM_STATE;\r
- break;\r
-\r
- case QPEE_TRANS_SQERR2RTS:\r
- mask =\r
- TAVOR_IF_QPEE_OPTPAR_RRE |\r
- TAVOR_IF_QPEE_OPTPAR_RAE |\r
- TAVOR_IF_QPEE_OPTPAR_REW |\r
- TAVOR_IF_QPEE_OPTPAR_Q_KEY |\r
- TAVOR_IF_QPEE_OPTPAR_RNR_TIMEOUT;\r
- break;\r
- /* case QPEE_TRANS_2ERR : mask=0 */\r
- /* case QPEE_TRANS_RTS2SQD : mask=0 */\r
- case QPEE_TRANS_SQD2RTS :\r
- mask = TAVOR_IF_QPEE_OPTPAR_ALL | TAVOR_IF_QPEE_OPTPAR_SCHED_QUEUE;\r
- break;\r
- /* case QPEE_TRANS_ERR2RST : mask=0 */\r
- default:;\r
- }\r
- return mask;\r
-} /* x_optmask */\r
-\r
-\r
-\r
-/************************************************************************/\r
-static inline void rst2init_dummy_attributes(THH_qpee_context_t* qpc_p, MT_bool is_sqp, IB_port_t port )\r
-{\r
- qpc_p->primary_address_path.pkey_index = 0;\r
- qpc_p->primary_address_path.port_number = is_sqp ? port : 1;\r
- qpc_p->q_key = 1;\r
-}\r
-\r
-static HH_ret_t modify_qp_checks(\r
- THH_qpm_t qpm, /* IN */\r
- TQPM_sw_qpc_t* qp_p, /* IN */\r
- VAPI_qp_state_t cur_qp_state, /* IN */\r
- VAPI_qp_attr_t* qp_attr_p, /* IN */\r
- VAPI_qp_attr_mask_t attr_mask, /* IN */\r
- THH_qpee_transition_t* trans_p, /* OUT */\r
- VAPI_qp_attr_t* altfix_attr_p, /* OUT */\r
- MT_bool* trivial_rst2rst /* OUT */\r
-)\r
-{\r
- HH_ret_t rc = HH_OK;\r
- IB_port_t port;\r
- MT_bool is_sqp; \r
- \r
- is_sqp = (is_sqp0(qpm,qp_p->qpn,&port)) | (is_sqp1(qpm,qp_p->qpn,&port));\r
- \r
- *trivial_rst2rst = FALSE;\r
-\r
- if ( (cur_qp_state == VAPI_RESET) &&\r
- (qp_p->state == VAPI_RESET) &&\r
- (qp_attr_p->qp_state == VAPI_RESET) )\r
- {\r
- rc = HH_OK;\r
- *trivial_rst2rst = TRUE;\r
- } \r
- \r
- else if ( ((cur_qp_state != qp_p->state) &&\r
- (cur_qp_state != VAPI_ERR) && /* user may know of error */\r
- (cur_qp_state != VAPI_SQE)) || /* may know of send-queue error */\r
- !defined_qp_state(cur_qp_state) ||\r
- !defined_qp_state(qp_attr_p->qp_state)\r
- )\r
- {\r
- rc = HH_EINVAL_QP_STATE; \r
- MTL_ERROR1(MT_FLFMT("mismatch: state, cur_qp_state=%s, qp_p->state=%s."),\r
- VAPI_qp_state_sym(cur_qp_state), VAPI_qp_state_sym(qp_p->state));\r
- MTL_ERROR1(MT_FLFMT("mismatch cont.: curr_qp_state=%s,qp_attr_p->qp_state=%s."),\r
- VAPI_qp_state_sym(cur_qp_state),VAPI_qp_state_sym(qp_attr_p->qp_state));\r
- }\r
- else\r
- {\r
- /* Support for RESET->ERR transition. First do RESET->INIT*/\r
- if ((cur_qp_state == VAPI_RESET) && (qp_attr_p->qp_state == VAPI_ERR) &&\r
- (qp_p->state == VAPI_RESET)) {\r
- /* pre transition to init state if requesting 2ERR from RESET state*/\r
- THH_qpee_context_t qpc;\r
- THH_cmd_status_t rce;\r
- qpc_default(&qpc);\r
- init2qpc_using_create_values(qp_p, &qpc);\r
- rst2init_dummy_attributes(&qpc, is_sqp, port);\r
- qpc.local_qpn_een = qp_p->qpn;\r
- rce = THH_cmd_MODIFY_QP(qpm->cmd_if, qp_p->qpn, QPEE_TRANS_RST2INIT, &qpc, 0);\r
- MTL_DEBUG1(MT_FLFMT("pre 2INIT, rce=%d=%s"),rce,str_THH_cmd_status_t(rce));\r
- rc = ((rce == THH_CMD_STAT_OK) ? HH_OK : \r
- (rce == THH_CMD_STAT_RESOURCE_BUSY) ? HH_EBUSY :\r
- (rce == THH_CMD_STAT_EINTR) ? HH_EINTR : HH_EFATAL );\r
- cur_qp_state = VAPI_INIT; /* we just did move to */\r
-\r
- /* QP with SRQ modified to reset - must first modify to ERR to flush all WQEs */\r
- } else if ((qp_attr_p->qp_state == VAPI_RESET) && (qp_p->state != VAPI_ERR) &&\r
- (qp_p->srqn != HH_INVAL_SRQ_HNDL)) {\r
- THH_cmd_status_t rce;\r
- MTL_DEBUG4(\r
- MT_FLFMT("%s: Moving QP 0x%X to error state before moving to reset (uses SRQ 0x%X)"),\r
- __func__, qp_p->qpn, qp_p->srqn);\r
- rce = THH_cmd_MODIFY_QP(qpm->cmd_if, qp_p->qpn, QPEE_TRANS_2ERR, 0, 0);\r
- rc = ((rce == THH_CMD_STAT_OK) ? HH_OK : \r
- (rce == THH_CMD_STAT_RESOURCE_BUSY) ? HH_EBUSY :\r
- (rce == THH_CMD_STAT_EINTR) ? HH_EINTR : HH_EFATAL );\r
- if (rc == HH_OK) {\r
- cur_qp_state = VAPI_ERR; /* we just did move to */\r
- qp_p->state= VAPI_ERR;\r
- }\r
- }\r
- }\r
- if (rc == HH_OK)\r
- {\r
- *trans_p = state_machine.tab[cur_qp_state][qp_attr_p->qp_state];\r
- /* if qp_attr_p->en_sqd_asyn_notif was set, we add a flag to xition value passed\r
- to THH_cmd_MODIFY_QPEE(). no need to check (qp_attr_p->qp_state == VAPI_SQD) - \r
- te flag is masked off anyway upon entry of THH_cmd_MODIFY_QPEE()*/\r
- if( qp_attr_p->en_sqd_asyn_notif && (*trans_p == QPEE_TRANS_RTS2SQD) ) {\r
- *trans_p = QPEE_TRANS_RTS2SQD_WITH_EVENT;\r
- }\r
- MTL_DEBUG4(MT_FLFMT("cur=%s, next=%s, trans=%d"),\r
- VAPI_qp_state_sym(cur_qp_state), \r
- VAPI_qp_state_sym(qp_attr_p->qp_state), *trans_p);\r
- if ( (*trans_p == (THH_qpee_transition_t)(-1)) && (trivial_rst2rst == FALSE) )\r
- {\r
- rc = HH_EINVAL_QP_STATE; MTL_DEBUG4(MT_FLFMT("bad trans"));\r
- }\r
- /*\r
- // since all alt_av related fields were combined under QP_ATTR_ALT_PATH\r
- // there is no need to check for partial delivery of them.\r
- else\r
- {\r
- if (!fix_partial_alternate(attr_mask, qpm->cmd_if, qpn, qp_attr_p,\r
- altfix_attr_p, &qp_attr_p))\r
- {\r
- rc = HH_EINVAL_PARAM;\r
- }\r
- }\r
- */\r
- }\r
- MTL_DEBUG4(MT_FLFMT("rc=%d=%s, trans=%d"), rc, HH_strerror_sym(rc), *trans_p);\r
- return rc;\r
-} /* modify_qp_checks */\r
-\r
-\r
-\r
-/************************************************************************/\r
-/************************************************************************/\r
-/* interface functions */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_qpm_create(\r
- THH_hob_t hob, /* IN */\r
- const THH_qpm_init_t* init_attr_p, /* IN */\r
- THH_qpm_t* qpm_p /* OUT */\r
-)\r
-{\r
- HH_ret_t rc = HH_EAGAIN;\r
- VIP_common_ret_t vret;\r
- TQPM_t* qpm;\r
- u_int8_t log2_max_qp = init_attr_p->log2_max_qp;\r
- u_int8_t log2_max_outs = init_attr_p->log2_max_outs_rdma_atom;\r
- u_int32_t rdb_base_align_mask = (1ul << log2_max_outs) - 1,i;\r
- unsigned long tavor_num_reserved_qps = 1ul << init_attr_p->log2_rsvd_qps;\r
- unsigned long nqp = 1ul << log2_max_qp;\r
- unsigned long nsqp= NUM_SQP_PER_PORT * init_attr_p->n_ports; /* Number of special QPs */\r
- unsigned long nrqp= nqp - tavor_num_reserved_qps - nsqp; /* Number of regular QPs */\r
- \r
- *qpm_p = NULL; // needed to know if to free mutex. will be non-NULL only if everything OK\r
- if ((!constants_ok) || (log2_max_qp > 24) || \r
- (nqp <= tavor_num_reserved_qps) || (init_attr_p->rdb_base_index & rdb_base_align_mask) ) {\r
- MTL_ERROR1(MT_FLFMT("%s: Invalid initialization parameters for THH_qpm"),__func__);\r
- return HH_EINVAL;\r
- }\r
-\r
- qpm = TMALLOC(TQPM_t);\r
- if (qpm == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: Failed allocation of THH_qpm object"),__func__);\r
- return HH_EAGAIN;\r
- }\r
- memset(qpm, 0, sizeof(TQPM_t));\r
-\r
- qpm->qpn_prefix= (u_int8_t *)MALLOC(MAX_QPN_PREFIX);\r
- if (qpm->qpn_prefix == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: Failed allocation of qpn_prefix table (%u entries)"),__func__,\r
- MAX_QPN_PREFIX);\r
- goto failed_qpn_prefix;\r
- }\r
- memset(qpm->qpn_prefix,0,MAX_QPN_PREFIX);\r
-\r
- vret= VIP_array_create_maxsize(nrqp > 1024 ? 1024 : nrqp, nrqp, &qpm->qp_tbl);\r
- if (vret != VIP_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: Failed VIP_array_create(1024) (vret=%d)"),__func__,vret);\r
- rc= HH_EAGAIN;\r
- goto failed_qp_tbl;\r
- }\r
-\r
- MTL_DEBUG4("{THH_qpm_create: hob=%p, log2MaxQP=%d, qpm=%p, rsvd_qps=%lu, " \r
- "ra_idx=0x%x, log2_max_outs=%d\n", \r
- hob, log2_max_qp, qpm, tavor_num_reserved_qps,\r
- init_attr_p->rdb_base_index, init_attr_p->log2_max_outs_rdma_atom);\r
-\r
- MTL_DEBUG4("{THH_qpm_create: constants_ok=%d, rdb_base_index=0x%x, align_mask=0x%x\n",\r
- constants_ok, init_attr_p->rdb_base_index, rdb_base_align_mask); \r
- \r
- if ((THH_hob_get_cmd_if(hob, &qpm->cmd_if) != HH_OK) ||\r
- (THH_hob_get_mrwm(hob, &qpm->mrwm_internal) != HH_OK) ||\r
- (THH_hob_get_ddrmm(hob, &qpm->ddrmm) != HH_OK) ||\r
- (THH_hob_get_uldm(hob, &qpm->uldm) != HH_OK))\r
- {\r
- MTL_ERROR1(MT_FLFMT("%s: Failed getting internal HOB objects"),__func__);\r
- rc= HH_ERR;\r
- goto failed_obj_get;\r
- }\r
- rc = HH_OK;\r
- \r
- qpm->hob = hob;\r
- qpm->log2_max_qp = log2_max_qp;\r
- \r
- /* speacial QPs info */\r
- qpm->sqp_info.sqp_ctx= TNMALLOC(TQPM_sw_qpc_t*, nsqp);\r
- if (qpm->sqp_info.sqp_ctx == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: Failed allocating sqp_ctx"),__func__);\r
- goto failed_sqp_ctx;\r
- }\r
- memset(qpm->sqp_info.sqp_ctx, 0, nsqp * sizeof(TQPM_sw_qpc_t*));\r
- qpm->sqp_info.first_sqp_qpn = tavor_num_reserved_qps;\r
- qpm->sqp_info.configured = FALSE; /* configure on demand */\r
- qpm->sqp_info.n_ports= init_attr_p->n_ports;\r
- if (!copy_port_props(qpm, init_attr_p))\r
- {\r
- goto failed_port_props;\r
- }\r
-\r
- \r
- qpm->first_rqp= qpm->sqp_info.first_sqp_qpn + nsqp; /* Index of first QP in qp_tbl */\r
- qpm->rdb_base_index = init_attr_p->rdb_base_index;\r
- qpm->log2_max_outs_rdma_atom = log2_max_outs;\r
- qpm->log2_max_outs_dst_rd_atom = init_attr_p->log2_max_outs_dst_rd_atom;\r
- qpm->max_outs_rdma_atom = (1ul << log2_max_outs);\r
- qpm->idx_mask = (1ul << log2_max_qp) - 1;\r
- \r
- if (qpm->sqp_info.port_props) {/* used as flag for non legacy behavior */\r
- for(i = 0;i < init_attr_p->n_ports;i++) {\r
- qpm->port_active[i] = FALSE;\r
- }\r
-#if !defined(DELAY_CONF_SPECIAL_QPS)\r
- rc = conf_special_qps(qpm);\r
- if (rc != HH_OK) goto failed_conf_sqp;\r
-#endif\r
- }\r
- MOSAL_mutex_init(&qpm->mtx);\r
- \r
- init_sgid_tbl(qpm);\r
- init_pkey_tbl(qpm);\r
-\r
- MTL_TRACE1("}THH_qpm_create: qpm=%p\n", qpm);\r
- logIfErr("THH_qpm_create");\r
- *qpm_p = qpm;\r
- return HH_OK;\r
-\r
- failed_conf_sqp:\r
- if (qpm->sqp_info.port_props != NULL) FREE(qpm->sqp_info.port_props);\r
- failed_port_props:\r
- FREE(qpm->sqp_info.sqp_ctx);\r
- failed_sqp_ctx:\r
- failed_obj_get:\r
- VIP_array_destroy(qpm->qp_tbl,NULL);\r
- failed_qp_tbl:\r
- FREE(qpm->qpn_prefix);\r
- failed_qpn_prefix:\r
- FREE(qpm);\r
- return rc;\r
-} /* THH_qpm_create */\r
-\r
-static void TQPM_free_sw_qpc(void *sw_qpc)\r
-{\r
- TQPM_sw_qpc_t* qp_p= (TQPM_sw_qpc_t*)sw_qpc;\r
- if (qp_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: Invoked for NULL SW QP context"), __func__);\r
- } else {\r
- MTL_ERROR1(MT_FLFMT("%s: Cleaning QP left-overs (qpn=0x%X)"), __func__, qp_p->qpn);\r
- FREE(sw_qpc);\r
- }\r
-}\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_qpm_destroy(THH_qpm_t qpm /* IN */, MT_bool hca_failure /* IN */)\r
-{\r
- int i;\r
- VIP_common_ret_t vret=VIP_OK;\r
- u_int32_t nsqp= qpm->first_rqp - qpm->sqp_info.first_sqp_qpn; /* Number of special QPs */\r
-\r
- MTL_TRACE1("{THH_qpm_destroy: qpm=%p, hfail=%d\n", qpm, hca_failure);\r
- /* Clean regular QPs "left-overs" */\r
- MTL_TRACE2(MT_FLFMT("%s: Cleaning VIP_array..."), __func__);\r
- vret= VIP_array_destroy(qpm->qp_tbl, TQPM_free_sw_qpc);\r
- if (vret != VIP_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: Failed VIP_array_destroy for qp_tbl (%d - %s)"), __func__,\r
- vret, VAPI_strerror_sym(vret));\r
- /* Continue - the show must go on... */\r
- }\r
-\r
- /* Cleaning special QPs left-overs */\r
- MTL_TRACE2(MT_FLFMT("%s: Cleaning special QPs..."), __func__);\r
- for (i= 0; i < (int)nsqp; i++) {\r
- if (qpm->sqp_info.sqp_ctx[i] != NULL) {FREE(qpm->sqp_info.sqp_ctx[i]);}\r
- }\r
- FREE(qpm->sqp_info.sqp_ctx);\r
- if (qpm->sqp_info.port_props != NULL) {\r
- MTL_TRACE2(MT_FLFMT("%s: Cleaning port_props..."), __func__);\r
- FREE(qpm->sqp_info.port_props);\r
- }\r
- \r
-/* free pkey & sgid tbl */ \r
- MTL_TRACE2(MT_FLFMT("%s: Cleaning SGID table..."), __func__);\r
- for (i=0; i< qpm->sqp_info.n_ports; i++)\r
- {\r
- if (qpm->sgid_tbl[i] != NULL)\r
- {\r
- TQPM_GOOD_FREE(qpm->sgid_tbl[i],(sizeof(IB_gid_t) * qpm->num_sgids[i]));\r
- }\r
- }\r
-\r
- MTL_TRACE2(MT_FLFMT("%s: Cleaning Pkey table..."), __func__);\r
- for (i=0; i< qpm->sqp_info.n_ports; i++)\r
- {\r
- if (qpm->pkey_tbl[i] != NULL)\r
- {\r
- TQPM_GOOD_FREE(qpm->pkey_tbl[i],(sizeof(VAPI_pkey_t)*qpm->pkey_tbl_sz[i]));\r
- }\r
- }\r
-\r
- MTL_TRACE2(MT_FLFMT("%s: Cleaning qpn_prefix..."), __func__);\r
- FREE(qpm->qpn_prefix);\r
- MOSAL_mutex_free(&qpm->mtx);\r
- FREE(qpm);\r
- MTL_TRACE1("}THH_qpm_destroy\n");\r
- return HH_OK;\r
-} /* THH_qpm_destroy */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_qpm_create_qp(\r
- THH_qpm_t qpm, /* IN */\r
- HH_qp_init_attr_t* init_attr_p, /* IN */\r
- MT_bool mlx, /* IN */\r
- THH_qp_ul_resources_t* qp_ul_resources_p, /* IO */\r
- IB_wqpn_t* qpn_p /* OUT */\r
-)\r
-{\r
- HH_ret_t rc = HH_EAGAIN;\r
- VIP_common_ret_t vret;\r
- u_int32_t qp_idx;\r
- TQPM_sw_qpc_t *new_qp_p;\r
- VIP_array_handle_t qp_hndl;\r
- u_int32_t wild_bits;\r
-\r
- MTL_TRACE1("{THH_qpm_create_qp: qpm=%p, mlx=%d\n", qpm, mlx);\r
- if ((init_attr_p->srq != HH_INVAL_SRQ_HNDL) && (init_attr_p->ts_type != VAPI_TS_RC)) {\r
- /* SRQs are supported only for RC QPs in Tavor */\r
- MTL_ERROR2(MT_FLFMT("%s: SRQ association with transport service type %s(%d)"\r
- " - only RC QPs are allowed with SRQs."),\r
- __func__, VAPI_ts_type_sym(init_attr_p->ts_type), init_attr_p->ts_type);\r
- return HH_ENOSYS;\r
- }\r
-\r
- new_qp_p= TMALLOC(TQPM_sw_qpc_t);\r
- if (new_qp_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: Failed allocating memory for new SW-QPC"),__func__);\r
- return HH_EAGAIN;\r
- }\r
- memset(new_qp_p,0,sizeof(TQPM_sw_qpc_t));\r
- vret= VIP_array_insert(qpm->qp_tbl, new_qp_p, &qp_hndl ); \r
- if (vret != VIP_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: Failed allocating QP (%d - %s), qpm->qp_tbl=%p"),__func__, \r
- vret, VAPI_strerror_sym(vret), qpm->qp_tbl);\r
- rc= (HH_ret_t)vret;\r
- goto failed_array_insert;\r
- }\r
- qp_idx= qp_hndl + qpm->first_rqp;\r
- if (qp_idx >= (1U<<qpm->log2_max_qp)) {\r
- MTL_ERROR1(MT_FLFMT("%s: QP index (0x%x) greater than (1<<log2_max_qp)-1 (0x%x)"),__func__, \r
- qp_idx, (1<<qpm->log2_max_qp)-1);\r
- }\r
- rc = create_qp(qpm, init_attr_p, mlx, qp_ul_resources_p, new_qp_p);\r
- if (rc != HH_OK) goto failed_create_qp;\r
- \r
- /* perturb high bits */\r
- wild_bits = qpm->qpn_prefix[qp_idx & QPN_PREFIX_INDEX_MASK]++;\r
- new_qp_p->qpn = ( (wild_bits << qpm->log2_max_qp) | qp_idx ) & 0xFFFFFF;\r
- if (new_qp_p->qpn == 0xFFFFFF) new_qp_p->qpn= qp_idx; /* 0xFFFFFF is reserved for multicast */\r
- \r
- *qpn_p = new_qp_p->qpn;\r
- MTL_TRACE1("}THH_qpm_create_qp: qpn=0x%x\n", *qpn_p);\r
- logIfErr("THH_qpm_create_qp");\r
- return rc;\r
-\r
- failed_create_qp:\r
- VIP_array_erase(qpm->qp_tbl, qp_hndl, NULL);\r
- failed_array_insert:\r
- FREE(new_qp_p);\r
- return rc;\r
-} /* THH_qpm_create_qp */\r
-\r
-\r
-/************************************************************************/\r
-HH_ret_t THH_qpm_get_special_qp(\r
- THH_qpm_t qpm, /* IN */\r
- VAPI_special_qp_t qp_type, /* IN */\r
- IB_port_t port, /* IN */\r
- HH_qp_init_attr_t* init_attr_p, /* IN */\r
- THH_qp_ul_resources_t* qp_ul_resources_p, /* IO */\r
- IB_wqpn_t* sqp_hndl_p /* OUT */\r
-)\r
-{\r
- const Special_QPs* sqp_info = &qpm->sqp_info;\r
- HH_ret_t rc = HH_OK;\r
- unsigned int port_idx = port - 1;\r
- unsigned int qpti = 0; /* SQP Type index */\r
- MTL_TRACE1("{THH_qpm_get_special_qp: qpm=%p\n", qpm);\r
- if (qpm->sqp_info.port_props == NULL)\r
- {\r
- MTL_ERROR1(MT_FLFMT("get_special_qp: not supported in legacy mode"));\r
- rc = HH_ENOSYS;\r
- }\r
- else\r
- {\r
- if (port_idx >= sqp_info->n_ports)\r
- {\r
- MTL_ERROR1(MT_FLFMT("THH_qpm_get_special_qp: bad port=%d"), port);\r
- rc = HH_EINVAL_PORT;\r
- }\r
- for (qpti = 0; (qpti != n_qp_types) && (qp_types[qpti] != qp_type); ++qpti);\r
- if (qpti == NUM_SQP_PER_PORT)\r
- {\r
- MTL_ERROR1(MT_FLFMT("THH_qpm_get_special_qp: bad qp_type=%d"), qp_type);\r
- rc = HH_EINVAL_PARAM;\r
- }\r
- \r
-\r
-#if defined(DELAY_CONF_SPECIAL_QPS)\r
- if ((rc == HH_OK) && (!qpm->sqp_info.configured))\r
- {\r
- rc = conf_special_qps(qpm);\r
- if (rc == HH_OK)\r
- {\r
- qpm->sqp_info.configured = TRUE;\r
- }\r
- }\r
-#endif\r
- }\r
- if (rc == HH_OK)\r
- {\r
- u_int32_t sqp_indx= (qpm->sqp_info.n_ports * qpti) + port_idx;\r
- if (MOSAL_mutex_acq(&qpm->mtx, TRUE) != MT_OK) return HH_EINTR;\r
-\r
- if (qpm->sqp_info.sqp_ctx[sqp_indx] == NULL) { /* This SQP is not used */\r
- // making sure of MLX xport service for special QPs:\r
- qpm->sqp_info.sqp_ctx[sqp_indx]= TMALLOC(TQPM_sw_qpc_t);\r
- if (qpm->sqp_info.sqp_ctx[sqp_indx] == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: Failed allocating memory for new SW-QPC"),__func__);\r
- rc= HH_EAGAIN;\r
- } else {\r
- init_attr_p->ts_type = THH_ST_MLX; \r
- rc = create_qp(qpm, init_attr_p, TRUE, qp_ul_resources_p, qpm->sqp_info.sqp_ctx[sqp_indx]);\r
- if (rc != HH_OK) {\r
- FREE(qpm->sqp_info.sqp_ctx[sqp_indx]);\r
- qpm->sqp_info.sqp_ctx[sqp_indx]= NULL;\r
- } else {\r
- qpm->sqp_info.sqp_ctx[sqp_indx]->qpn= qpm->sqp_info.first_sqp_qpn + sqp_indx;\r
- MTL_DEBUG4(MT_FLFMT(\r
- "%s: Allocated SQP of type %d (port %d) with qpn=0x%X "\r
- "(qpti=%u sqp_indx=%u first_sqp_qpn=0x%X)"), __func__,\r
- qp_type, port, qpm->sqp_info.sqp_ctx[sqp_indx]->qpn, \r
- qpti,sqp_indx,qpm->sqp_info.first_sqp_qpn);\r
- *sqp_hndl_p = qpm->sqp_info.sqp_ctx[sqp_indx]->qpn;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- rc = HH_EBUSY;\r
- }\r
- MOSAL_mutex_rel(&qpm->mtx);\r
- \r
- }\r
- MTL_TRACE1("}THH_qpm_get_special_qp\n");\r
- logIfErr("THH_qpm_get_special_qp");\r
- return rc;\r
-} /* THH_qpm_get_special_qp */\r
-\r
-static inline HH_ret_t THH_modify_cmdrc2rc(THH_cmd_status_t cmd_rc)\r
-{\r
- HH_ret_t rc;\r
- switch(cmd_rc){\r
- case THH_CMD_STAT_OK:\r
- rc = HH_OK;\r
- break;\r
- case THH_CMD_STAT_EINTR:\r
- rc = HH_EINTR;\r
- break;\r
- case THH_CMD_STAT_BAD_PARAM:\r
- case THH_CMD_STAT_BAD_INDEX:\r
- rc = HH_EINVAL_PARAM;\r
- break;\r
- case THH_CMD_STAT_BAD_RESOURCE: /* accessing reserved qp/ee */\r
- case THH_CMD_STAT_RESOURCE_BUSY:\r
- rc = HH_EBUSY;\r
- break;\r
- case THH_CMD_STAT_BAD_QPEE_STATE:\r
- rc = HH_EINVAL_QP_STATE;\r
- break;\r
- case THH_CMD_STAT_BAD_RES_STATE:\r
- rc = HH_EINVAL_MIG_STATE;\r
- break;\r
- case THH_CMD_STAT_BAD_SYS_STATE:\r
- rc = HH_ERR; /* HCA is disabled */\r
- break;\r
- default:\r
- rc = HH_EFATAL;\r
- }\r
- return rc;\r
-}\r
-/************************************************************************/\r
-/* We protect against erroneous application modifying same QP\r
- * in multi-threads. We use a mutex per QPM.\r
- * It may be more efficient to have a mutex per QP,\r
- * but we leave it for future consideration.\r
- */\r
-HH_ret_t THH_qpm_modify_qp(\r
- THH_qpm_t qpm, /* IN */\r
- IB_wqpn_t qpn, /* IN */\r
- VAPI_qp_state_t cur_qp_state, /* IN */\r
- VAPI_qp_attr_t* qp_attr_p, /* IN */\r
- VAPI_qp_attr_mask_t* qp_attr_mask_p /* IN */\r
-)\r
-{\r
- VAPI_qp_attr_t altfix_attr;\r
- THH_qpee_transition_t trans;\r
- VIP_array_obj_t qp_obj;\r
- TQPM_sw_qpc_t* qp_p;\r
- HH_ret_t rc = HH_EAGAIN;\r
- VIP_common_ret_t vret;\r
- int i;\r
- u_int32_t qp_idx = qpn & qpm->idx_mask;\r
- MT_bool trivial_rst2rst;\r
-\r
- MTL_DEBUG1("{THH_qpm_modify_qp: qpm=%p, qpn=0x%x, curr_state=%d\n, next_state=%d", \r
- qpm, qpn, cur_qp_state,qp_attr_p->qp_state);\r
- if (is_sqp(qpm,qpn)) {\r
- if (MOSAL_mutex_acq(&qpm->mtx, TRUE) != MT_OK) return HH_EINTR;\r
- qp_p= qpm->sqp_info.sqp_ctx[qpn - qpm->sqp_info.first_sqp_qpn];\r
- if (qp_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: Given special QP handle is not active (qpn=0x%X)"),__func__,qpn);\r
- MOSAL_mutex_rel(&qpm->mtx);\r
- return HH_EINVAL_QP_NUM;\r
- }\r
- } else { /* regular RQ */\r
- vret= VIP_array_find_hold(qpm->qp_tbl, qp_idx - qpm->first_rqp, &qp_obj);\r
- qp_p= (TQPM_sw_qpc_t*)qp_obj;\r
- if ((vret != VIP_OK) || (qpn != qp_p->qpn)) {\r
- MTL_ERROR1(MT_FLFMT("%s: Invalid QP handle (qpn=0x%X)"),__func__,qpn);\r
- if (vret == VIP_OK) VIP_array_find_release(qpm->qp_tbl, qp_idx - qpm->first_rqp);\r
- return HH_EINVAL_QP_NUM;\r
- }\r
- }\r
- \r
- rc = modify_qp_checks(qpm, qp_p, cur_qp_state, qp_attr_p, *qp_attr_mask_p, \r
- &trans, &altfix_attr,&trivial_rst2rst);\r
- MTL_DEBUG4(MT_FLFMT("trans=%d, rst2rst=%d"), trans, trivial_rst2rst);\r
- if (rc == HH_OK && !trivial_rst2rst)\r
- {\r
- THH_qpee_context_t qpc;\r
- u_int32_t opt_mask;\r
- u_int32_t qp_idx = qpn & qpm->idx_mask;\r
- MT_bool legacy_mode;\r
-\r
- qpc_default(&qpc);\r
- qpc.state = qp_attr_p->qp_state;\r
- if ((qp_attr_p->qp_state == VAPI_INIT) && (cur_qp_state != VAPI_INIT))\r
- {\r
- init2qpc_using_create_values(qp_p, &qpc);\r
- }\r
- \r
- // just making sure qpn is correct.\r
- qp_attr_p->qp_num = qpn;\r
- rc = vapi2qpc_modify(qpm, qp_p, qp_attr_p, trans, *qp_attr_mask_p, \r
- &qpc, &opt_mask);\r
- \r
- qpc.local_qpn_een = qpn;\r
- qpc.ra_buff_indx = qpm->rdb_base_index + qp_idx * qpm->max_outs_rdma_atom;\r
- //MTL_ERROR1("%s: opt mask before screening was: 0x%x", __func__,opt_mask);\r
- opt_mask &= x_optmask(trans);\r
- //MTL_ERROR1("%s: opt mask after screening was: 0x%x", __func__,opt_mask);\r
- \r
- /*\r
- prepare_special_qp() will call INIT_IB/CLOSE_IB \r
- for special QPs & their associated port.\r
- this should be done only when operating in non legacy\r
- mode (legacy mode has executed INIT_IB from THH_hob_open_hca() ).\r
- */\r
- if( (rc == HH_OK) && (is_sqp(qpm,qpn)) ) {\r
- rc = THH_hob_get_legacy_mode(qpm->hob,&legacy_mode);\r
- if( rc == HH_OK && (legacy_mode == FALSE) ) {\r
- MTL_TRACE2("%s: operating under non legacy mode - activating port.", __func__);\r
- rc = prepare_special_qp(qpm, qpn, trans);\r
- }\r
- }\r
- \r
- if (rc == HH_OK)\r
- {\r
- THH_cmd_status_t cmd_rc = \r
- THH_cmd_MODIFY_QP(qpm->cmd_if, qpn, trans, &qpc, opt_mask);\r
-\r
- rc = THH_modify_cmdrc2rc(cmd_rc);\r
- MTL_DEBUG4(MT_FLFMT("cmd_rc=%d=%s"), \r
- cmd_rc, str_THH_cmd_status_t(cmd_rc));\r
- if (rc == HH_OK)\r
- {\r
- IB_port_t sqp1_port;\r
- /* check whether to update pkey index of qp1 in our struct*/ \r
- if (is_sqp1(qpm,qpn,&sqp1_port))\r
- {\r
- if (check_2update_pkey(cur_qp_state,qp_attr_p->qp_state,qp_attr_mask_p))\r
- {\r
- MTL_DEBUG4("updating pkey in the required transition. port %d \n",sqp1_port);\r
- qpm->qp1_pkey_idx[sqp1_port-1/*idx!*/] = qp_attr_p->pkey_ix;\r
- for (i=0; i< qpm->sqp_info.n_ports; i++)\r
- {\r
- MTL_DEBUG1("port %d: qp1 pkey idx:%x \n",i+1,qpm->qp1_pkey_idx[i]);\r
- }\r
- }\r
- }\r
-\r
- qp_p->state = qp_attr_p->qp_state;\r
- track_rdma_atomic(qp_attr_p,*qp_attr_mask_p, qp_p); \r
- }\r
- }\r
- }\r
- \r
- if (is_sqp(qpm,qpn)) {\r
- MOSAL_mutex_rel(&qpm->mtx);\r
- } else { /* regular RQ */\r
- VIP_array_find_release(qpm->qp_tbl, qp_idx - qpm->first_rqp);\r
- }\r
- \r
- MTL_TRACE1("}THH_qpm_modify_qp\n");\r
- logIfErr("THH_qpm_modify_qp");\r
- return rc;\r
-} /* THH_qpm_modify_qp */\r
-\r
-\r
-/************************************************************************/\r
-/* Same comment about mutex as above THH_qpm_modify_qp(...) applies */\r
-HH_ret_t THH_qpm_query_qp(\r
- THH_qpm_t qpm, /* IN */\r
- IB_wqpn_t qpn, /* IN */\r
- VAPI_qp_attr_t* qp_attr_p /* IN */\r
-)\r
-{\r
- HH_ret_t rc = HH_OK;\r
- VIP_common_ret_t vret;\r
- IB_port_t dummy_port;\r
- VIP_array_obj_t qp_obj;\r
- TQPM_sw_qpc_t* qp_p;\r
- u_int32_t qp_idx = qpn & qpm->idx_mask;\r
-\r
- MTL_TRACE1("{THH_qpm_query_qp: qpm=%p, qpn=0x%x\n", qpm, qpn);\r
- if (is_sqp(qpm,qpn)) {\r
- if (MOSAL_mutex_acq(&qpm->mtx, TRUE) != MT_OK) return HH_EINTR;\r
- qp_p= qpm->sqp_info.sqp_ctx[qpn - qpm->sqp_info.first_sqp_qpn];\r
- if (qp_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: Given special QP handle is not active (qpn=0x%X)"),__func__,qpn);\r
- return HH_EINVAL_QP_NUM;\r
- }\r
- } else { /* regular RQ */\r
- vret= VIP_array_find_hold(qpm->qp_tbl, qp_idx - qpm->first_rqp, &qp_obj);\r
- qp_p= (TQPM_sw_qpc_t*)qp_obj;\r
- if ((vret != VIP_OK) || (qpn != qp_p->qpn)) {\r
- MTL_ERROR1(MT_FLFMT("%s: Invalid QP handle (qpn=0x%X)"),__func__,qpn);\r
- if (vret == VIP_OK) VIP_array_find_release(qpm->qp_tbl, qp_idx - qpm->first_rqp);\r
- return HH_EINVAL_QP_NUM;\r
- }\r
- }\r
- \r
- memset(qp_attr_p, 0, sizeof(VAPI_qp_attr_t));\r
-\r
- switch (qp_p->state)\r
- {\r
- case VAPI_RESET:\r
- qp_attr_p->qp_state = VAPI_RESET;\r
- qp_attr_p->qp_num = qpn;\r
- if (is_sqp0(qpm,qp_attr_p->qp_num,&dummy_port)) {\r
- qp_attr_p->qp_num = 0;\r
- } else if (is_sqp1(qpm,qp_attr_p->qp_num,&dummy_port)) {\r
- qp_attr_p->qp_num = 1;\r
- }\r
- break;\r
- default:\r
- {\r
- THH_qpee_context_t qpc;\r
- THH_cmd_status_t crc = THH_cmd_QUERY_QP(qpm->cmd_if, qpn, &qpc);\r
- if (crc == THH_CMD_STAT_OK)\r
- {\r
- qpc2vapi_attr(&qpc, qp_attr_p);\r
- if (is_sqp0(qpm,qp_attr_p->qp_num,&dummy_port)) {\r
- qp_attr_p->qp_num = 0;\r
- } else if (is_sqp1(qpm,qp_attr_p->qp_num,&dummy_port)) {\r
- qp_attr_p->qp_num = 1;\r
- }\r
- } else {\r
- rc = ((crc == THH_CMD_STAT_OK) ? HH_OK : \r
- (crc == THH_CMD_STAT_EINTR) ? HH_EINTR : \r
- (crc == THH_CMD_STAT_RESOURCE_BUSY) ? HH_EBUSY : HH_EFATAL);\r
- MTL_ERROR1(MT_FLFMT("ERROR: THH_cmd_QUERY_QP returned %s"),str_THH_cmd_status_t(crc));\r
- }\r
- }\r
- }\r
- if (rc == HH_OK)\r
- {\r
- qp_attr_p->cap = qp_p->cap; \r
- qp_attr_p->ous_dst_rd_atom = qp_p->ous_dst_rd_atom;\r
- qp_attr_p->qp_ous_rd_atom = qp_p->qp_ous_rd_atom;\r
- qp_attr_p->remote_atomic_flags = qp_p->remote_atomic_flags;\r
- }\r
-\r
-\r
- if (is_sqp(qpm,qpn)) {\r
- MOSAL_mutex_rel(&qpm->mtx);\r
- } else { /* regular RQ */\r
- VIP_array_find_release(qpm->qp_tbl, qp_idx - qpm->first_rqp);\r
- }\r
- MTL_TRACE1("}THH_qpm_query_qp, state=%d=%s\n", \r
- qp_attr_p->qp_state, VAPI_qp_state_sym(qp_attr_p->qp_state));\r
- logIfErr("THH_qpm_query_qp");\r
- return rc;\r
-} /* THH_qpm_query_qp */\r
-\r
-\r
-/************************************************************************/\r
-/* Same comment about mutex as above THH_qpm_modify_qp(...) applies */\r
-HH_ret_t THH_qpm_destroy_qp(\r
- THH_qpm_t qpm, /* IN */\r
- IB_wqpn_t qpn /* IN */\r
-)\r
-{\r
- HH_ret_t rc = HH_OK;\r
- VIP_common_ret_t vret;\r
- u_int32_t qp_idx = qpn & qpm->idx_mask;\r
- TQPM_sw_qpc_t* qp2destroy;\r
- VIP_array_obj_t array_obj;\r
- \r
- MTL_TRACE1("{THH_qpm_destroy_qp: qpm=%p, qpn=0x%x\n", qpm, qpn);\r
-\r
- if (is_sqp(qpm,qpn)) {\r
- if (MOSAL_mutex_acq(&qpm->mtx, TRUE) != MT_OK) return MT_EINTR;\r
- qp2destroy= qpm->sqp_info.sqp_ctx[qp_idx - qpm->sqp_info.first_sqp_qpn];\r
- if (qp2destroy == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: Given special QP handle is not active (qpn=0x%X)"),__func__,qpn);\r
- MOSAL_mutex_rel(&qpm->mtx);\r
- return HH_EINVAL_QP_NUM;\r
- }\r
- } else {\r
- vret= VIP_array_erase_prepare(qpm->qp_tbl, qp_idx - qpm->first_rqp, &array_obj);\r
- qp2destroy= (TQPM_sw_qpc_t*)array_obj;\r
- if (vret != VIP_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: Failed VIP_array_erase_prepare for qpn=0x%X (%d - %s)"), __func__, \r
- qpn, vret, VAPI_strerror_sym(vret));\r
- return (vret == VIP_EINVAL_HNDL) ? HH_EINVAL_QP_NUM : (HH_ret_t)vret;\r
- }\r
- if (qpn != qp2destroy->qpn) {\r
- MTL_ERROR1(MT_FLFMT("%s: Invalid qpn=0x%X"), __func__, qpn);\r
- VIP_array_erase_undo(qpm->qp_tbl, qp_idx - qpm->first_rqp);\r
- return HH_EINVAL_QP_NUM;\r
- }\r
- }\r
-\r
-#if defined(MT_SUSPEND_QP)\r
- /* if qp is suspended, unsuspend it here, directly calling command interface */\r
- { \r
- THH_cmd_status_t crc;\r
- if (qp2destroy->is_suspended == TRUE) {\r
- crc = THH_cmd_SUSPEND_QP(qpm->cmd_if, qpn, FALSE);\r
- if (crc != THH_CMD_STAT_OK){ \r
- MTL_ERROR1(MT_FLFMT("%s: FAILED unsuspending QP 0x%x. "),__func__, qpn);\r
- }\r
- }\r
- qp2destroy->is_suspended=FALSE;\r
- }\r
-#endif\r
-\r
- if (qp2destroy->state != VAPI_RESET) \r
- { /* Assure QP is left in RESET (SW ownership) */\r
- THH_qpee_context_t qpc;\r
- THH_cmd_status_t rce; \r
- qpc_default(&qpc);\r
- qpc.local_qpn_een = qpn;\r
-\r
- /*\r
- prepare_special_qp() will call INIT_IB/CLOSE_IB \r
- for special QPs & their associated port.\r
- this should be done only when operating in non legacy\r
- mode (legacy mode has executed INIT_IB from THH_hob_open_hca() ).\r
- */\r
- if( is_sqp(qpm,qpn) )\r
- {\r
- MT_bool legacy_mode;\r
-\r
- rc = THH_hob_get_legacy_mode(qpm->hob,&legacy_mode);\r
- if( rc == HH_OK && (legacy_mode == FALSE) )\r
- {\r
- MTL_TRACE2("%s: operating under non legacy mode - activating port.", __func__);\r
- rc = prepare_special_qp(qpm, qpn, QPEE_TRANS_ERR2RST);\r
- }\r
- }\r
-\r
- /* really ANY2RST transition, not ERR2RST */\r
- rce = THH_cmd_MODIFY_QP(qpm->cmd_if, qpn, QPEE_TRANS_ERR2RST, &qpc, 0);\r
- MTL_DEBUG4(MT_FLFMT("2RST: rc=%d=%s"), rce, str_THH_cmd_status_t(rce));\r
- rc = (((rce == THH_CMD_STAT_OK)||(rce == THH_CMD_STAT_EFATAL)) ? HH_OK : \r
- (rce == THH_CMD_STAT_EINTR) ? HH_EINTR :\r
- (rce == THH_CMD_STAT_RESOURCE_BUSY) ? HH_EBUSY : HH_EINVAL);\r
- }\r
-\r
- if ((rc == HH_OK) && (qp2destroy->wqes_buf_sz != 0)) \r
- { /* Release descriptor's memory region (if WQEs buffer exists - could happen with SRQ)*/\r
- rc= THH_mrwm_deregister_mr(qpm->mrwm_internal, qp2destroy->lkey); \r
- if (rc != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed deregistering internal MR (qpn=0x%X lkey=0x%X)"\r
- " ==> MR resource leak (%s)"), \r
- __func__, qp2destroy->qpn, qp2destroy->lkey, HH_strerror_sym(rc));\r
- }\r
- if (qp2destroy->pa_ddr != (MT_phys_addr_t)0)\r
- {\r
- MOSAL_protection_ctx_t ctx; /* was not saved, so recover */\r
- rc = THH_uldm_get_protection_ctx(qpm->uldm, qp2destroy->pd, &ctx);\r
- if (rc != HH_OK)\r
- {\r
- MTL_ERROR1("THH_qpm_destroy_qp: failed recover protection ctx\n");\r
- }\r
- else\r
- {\r
- MT_size_t buf_sz = complete_pg_sz(qp2destroy->wqes_buf_sz);\r
- MOSAL_unmap_phys_addr(ctx, qp2destroy->wqes_buf, buf_sz);\r
- THH_ddrmm_free(qpm->ddrmm, qp2destroy->pa_ddr, buf_sz);\r
- }\r
- }\r
- }\r
- \r
- if (rc == HH_OK) {\r
- if (is_sqp(qpm,qpn)) {\r
- qpm->sqp_info.sqp_ctx[qp_idx - qpm->sqp_info.first_sqp_qpn]= NULL;\r
- MOSAL_mutex_rel(&qpm->mtx);\r
- } else { /* regular RQ */\r
- VIP_array_erase_done(qpm->qp_tbl, qp_idx - qpm->first_rqp, NULL);\r
- }\r
- FREE(qp2destroy);\r
- \r
- } else { /* Failure */\r
- if (is_sqp(qpm,qpn)) {\r
- MOSAL_mutex_rel(&qpm->mtx);\r
- } else { /* regular RQ */\r
- VIP_array_erase_undo(qpm->qp_tbl, qp_idx - qpm->first_rqp);\r
- }\r
- }\r
-\r
- \r
- MTL_TRACE1("}THH_qpm_destroy_qp\n");\r
- logIfErr("THH_qpm_destroy_qp");\r
- return rc;\r
-} /* THH_qpm_destroy_qp */\r
-\r
-/************************************************************************/\r
-/* Assumed to be the first called in this module, single thread. */\r
-void THH_qpm_init(void)\r
-{\r
- MTL_TRACE1("THH_qpm_init{ compiled: date=%s, time=%s\n", __DATE__, __TIME__);\r
- if (check_constants())\r
- {\r
- init_state_machine(&state_machine);\r
- }\r
- else\r
- {\r
- MTL_ERROR1(MT_FLFMT("THH_qpm_init: ERROR bad constants."));\r
- }\r
- \r
- native_page_shift = MOSAL_SYS_PAGE_SHIFT;\r
- native_page_size = 1ul << native_page_shift;\r
- native_page_low_mask = (1ul << native_page_shift)-1;\r
- MTL_DEBUG4(MT_FLFMT("native_page: shift=%d, size=0x%x, mask=0x%x"), \r
- native_page_shift, native_page_size, native_page_low_mask);\r
- \r
- MTL_TRACE1("THH_qpm_init}\n");\r
-} /* THH_qpm_init */\r
-\r
-\r
-/***********************************************************************************/\r
-/******************************************************************************\r
- * Function: process_local_mad\r
- *****************************************************************************/\r
-HH_ret_t THH_qpm_process_local_mad(THH_qpm_t qpm, /* IN */\r
- IB_port_t port,/*IN */\r
- IB_lid_t slid, /* For Mkey violation trap */\r
- EVAPI_proc_mad_opt_t proc_mad_opts,/*IN */\r
- void * mad_in,/*IN */\r
- void * mad_out /*OUT*/\r
- )\r
-{\r
- THH_cmd_status_t cmd_ret;\r
- HH_ret_t ret = HH_OK;\r
- u_int8_t j,num_entries;\r
- u_int8_t* my_mad_in,*my_mad_out;\r
- u_int8_t* tbl_tmp = NULL;\r
- u_int32_t attr;\r
- SM_MAD_GUIDInfo_t guid_info;\r
- u_int32_t start_idx=0;\r
- SM_MAD_Pkey_table_t pkey_tbl;\r
- MT_bool set_op = FALSE;\r
- MT_bool validate_mkey = ((proc_mad_opts & EVAPI_MAD_IGNORE_MKEY) ? FALSE : TRUE);\r
-\r
- FUNC_IN;\r
- \r
- if (qpm == NULL) {\r
- MTL_ERROR1("[%s]: ERROR : Invalid qpm handle\n",__FUNCTION__);\r
- ret = HH_EINVAL;\r
- goto done;\r
- }\r
- \r
- if ((port > qpm->sqp_info.n_ports) || (port < 1)) {\r
- MTL_ERROR1("[%s]: ERROR : invalid port number (%d)\n",__FUNCTION__,port);\r
- ret = HH_EINVAL_PORT;\r
- goto done;\r
- }\r
-\r
- memset(mad_out, 0, IB_MAD_LEN);\r
- \r
- my_mad_in =(u_int8_t*)mad_in; \r
- \r
- MTL_DEBUG4("%s: MAD IN: \n", __func__);\r
- MadBufPrint(my_mad_in);\r
- \r
- attr = MOSAL_be32_to_cpu(((u_int32_t*)my_mad_in)[4]) >> 16;\r
- \r
- MTL_DEBUG4("%s: method:0x%x attr:0x%x validate_mkey: %s\n", __func__,\r
- my_mad_in[3],attr, (validate_mkey ? "TRUE" : "FALSE" ));\r
- \r
- if (my_mad_in[3] == IB_METHOD_SET) \r
- {\r
- set_op = TRUE; \r
- }\r
-\r
- \r
- cmd_ret = THH_cmd_MAD_IFC(qpm->cmd_if, validate_mkey, slid, port, mad_in, mad_out);\r
- if (cmd_ret != THH_CMD_STAT_OK) {\r
- MTL_ERROR2("[%s]: ERROR on port %d: %d \n",__FUNCTION__,port,cmd_ret);\r
- switch (cmd_ret) {\r
- case THH_CMD_STAT_EINTR: \r
- ret= HH_EINTR; break;\r
- case THH_CMD_STAT_BAD_PKT: \r
- case THH_CMD_STAT_EBADARG:\r
- ret= HH_EINVAL; break;\r
- case THH_CMD_STAT_BAD_INDEX: \r
- ret= HH_EINVAL_PORT; break;\r
- default: \r
- ret= HH_EFATAL;\r
- }\r
- goto done;\r
- } \r
- \r
- my_mad_out = (u_int8_t*)mad_out;\r
- \r
- MTL_DEBUG4("%s: MAD OUT: \n", __func__);\r
- MadBufPrint(my_mad_out);\r
- \r
- if (set_op)\r
- {\r
- switch (attr)\r
- {\r
- \r
- case IB_SMP_ATTRIB_PORTINFO: \r
- MTL_DEBUG2("[%s]: got SET_PORTINFO, port %d \n",__FUNCTION__,port);\r
- tbl_tmp = (u_int8_t*)(qpm->sgid_tbl[port-1]); \r
- num_entries = (u_int8_t)qpm->num_sgids[port-1]; \r
- \r
- for (j =0; j< num_entries; j++)\r
- {\r
- /* update all the gids' prefixes in my table - BIG Endian*/ \r
- memcpy(tbl_tmp + j*sizeof(IB_gid_t),((u_int8_t*)mad_out)+IB_SMP_DATA_START+8,8); \r
- }\r
- MTL_DEBUG2("[%s]: preffix:%d.%d.%d.%d.%d.%d.%d.%d \n",__FUNCTION__,tbl_tmp[0],tbl_tmp[1],\r
- tbl_tmp[2],tbl_tmp[3],tbl_tmp[4],tbl_tmp[5],\r
- tbl_tmp[6],tbl_tmp[7]);\r
- break;\r
- \r
- //requested to set gids, update in my table\r
- case IB_SMP_ATTRIB_GUIDINFO:\r
- MTL_DEBUG2("[%s]: got SET_GUIDINFO, port %d \n",__FUNCTION__,port);\r
- printGIDTable(qpm);\r
-\r
- tbl_tmp = (u_int8_t*)(qpm->sgid_tbl[port-1]); \r
- num_entries = (u_int8_t)qpm->num_sgids[port-1]; \r
-\r
- GUIDInfoMADToSt(&guid_info, my_mad_out);\r
- \r
- start_idx = MOSAL_be32_to_cpu(((u_int32_t*)my_mad_out)[5]);\r
- \r
- MTL_DEBUG2("%s: start idx %d \n", __func__,start_idx);\r
- /* skip in gid table to the starting idx to copy from */ \r
- tbl_tmp += (start_idx * sizeof(IB_gid_t));\r
- \r
- for (j = 0; j < 8; j++) {\r
- /* check start index first, just in case already out of range */\r
- if (start_idx >= num_entries) {\r
- break;\r
- }\r
- tbl_tmp += 8 /*sizeof gid prefix */;\r
- memcpy(tbl_tmp, &(guid_info.guid[j]), sizeof(IB_guid_t));\r
- tbl_tmp += sizeof(u_int64_t);\r
- start_idx++;\r
- }\r
- printGIDTable(qpm);\r
- \r
- break;\r
- \r
- case IB_SMP_ATTRIB_PARTTABLE:\r
- MTL_DEBUG2("[%s]: got SET_PORTTABLE, port %d \n",__FUNCTION__,port);\r
- printPKeyTable(qpm);\r
-\r
- num_entries = (u_int8_t)qpm->pkey_tbl_sz[port-1];\r
- \r
- /* Select only 16 LSBs */\r
- start_idx = (MOSAL_be32_to_cpu(((u_int32_t*)my_mad_out)[5])) & 0xFFFF;\r
- MTL_DEBUG2("%s: start idx %d \n", __func__,start_idx);\r
- \r
- /* copy & change the endieness */\r
- PKeyTableMADToSt(&pkey_tbl, my_mad_out);\r
-\r
- for (j = 0; j < 32; j++) {\r
- /* check start index first, just in case already out of range */\r
- if (start_idx >= num_entries) {\r
- break;\r
- }\r
- qpm->pkey_tbl[port-1][start_idx++] = pkey_tbl.pkey[j];\r
- }\r
- printPKeyTable(qpm);\r
- \r
- break;\r
- \r
- default: MTL_DEBUG5("%s: no need to do anything \n", __func__);\r
- }\r
- }/*end if set_op*/\r
- \r
-done: \r
- MT_RETURN(ret);\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_qpm_get_sgid\r
- *****************************************************************************/\r
-HH_ret_t THH_qpm_get_sgid(THH_qpm_t qpm, /* IN */\r
- IB_port_t port,/*IN */\r
- u_int8_t index, /*IN */\r
- IB_gid_t* gid_p/*OUT*/\r
- )\r
-{\r
- HH_ret_t ret= HH_OK;\r
-\r
- if ((port<1) || (port > qpm->sqp_info.n_ports))\r
- {\r
- return HH_EINVAL_PORT;\r
- }\r
- \r
- if (qpm->sgid_tbl[port-1] == NULL) \r
- {\r
- MTL_ERROR1("[%s]: ERROR: failure getting port %d gid tbl\n",__FUNCTION__,port);\r
- return HH_EINVAL_PARAM;\r
- }\r
-\r
- if (index >= qpm->num_sgids[port-1]) \r
- {\r
- MTL_ERROR1("[%s]: ERROR: invalid index",__FUNCTION__);\r
- return HH_EINVAL_PARAM;\r
- }\r
- printGIDTable(qpm);\r
- memcpy(*gid_p,qpm->sgid_tbl[port-1][index],sizeof(IB_gid_t));\r
- return ret;\r
-}\r
- \r
-/******************************************************************************\r
- * Function: THH_qpm_get_all_sgids\r
- *****************************************************************************/\r
-HH_ret_t THH_qpm_get_all_sgids(THH_qpm_t qpm, /* IN */\r
- IB_port_t port,/*IN */\r
- u_int8_t num_out_entries, /*IN */\r
- IB_gid_t* gid_p/*OUT*/\r
- )\r
-{\r
- HH_ret_t ret= HH_OK;\r
-\r
- if ((port<1) || (port > qpm->sqp_info.n_ports))\r
- {\r
- return HH_EINVAL_PORT;\r
- }\r
- \r
- if (qpm->sgid_tbl[port-1] == NULL) \r
- {\r
- MTL_ERROR1("[%s]: ERROR: failure getting port %d gid tbl\n",__FUNCTION__,port);\r
- return HH_EINVAL_PARAM;\r
- }\r
-\r
- if (num_out_entries < qpm->num_sgids[port-1]) \r
- {\r
- MTL_ERROR1("[%s]: ERROR: not enough space in output gid table",__FUNCTION__);\r
- return HH_EAGAIN;\r
- }\r
- memcpy(*gid_p,qpm->sgid_tbl[port-1],sizeof(IB_gid_t) * num_out_entries);\r
- return ret;\r
-}\r
- \r
-\r
-/******************************************************************************\r
- * Function: THH_qpm_get_qp1_pkey\r
- *****************************************************************************/\r
-HH_ret_t THH_qpm_get_qp1_pkey(THH_qpm_t qpm, /* IN */\r
- IB_port_t port,/*IN */\r
- VAPI_pkey_t* pkey_p/*OUT*/\r
- )\r
-{\r
-\r
- if ((port<1) || (port > qpm->sqp_info.n_ports))\r
- {\r
- MTL_ERROR1("%s: port number (%d) not valid\n", __func__,port);\r
- return HH_EINVAL_PORT;\r
- }\r
- \r
-\r
- if (qpm->pkey_tbl[port-1] == NULL) \r
- {\r
- MTL_ERROR1("[%s]: ERROR: failure getting port %d pkey tbl\n",__func__,port);\r
- return HH_EINVAL_PARAM;\r
- }\r
-\r
- //qp1 pkey isn't initialized yet\r
- if (qpm->qp1_pkey_idx[port-1] == 0xffff)\r
- {\r
- MTL_ERROR1("[%s]: ERROR: qp1 pkey for port %d isn't initialized yet \n",__func__,port);\r
- return HH_ERR;\r
- }\r
- MTL_DEBUG4("get Pkey: port %d idx: %d \n",port,qpm->qp1_pkey_idx[port-1]);\r
-\r
- *pkey_p = qpm->pkey_tbl[port-1][qpm->qp1_pkey_idx[port-1]];\r
- return HH_OK;\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_qpm_get_pkey\r
- *****************************************************************************/\r
-HH_ret_t THH_qpm_get_pkey(THH_qpm_t qpm, /* IN */\r
- IB_port_t port,/*IN */\r
- VAPI_pkey_ix_t pkey_index,/*IN*/\r
- VAPI_pkey_t* pkey_p/*OUT*/)\r
-{\r
- if ((port<1) || (port > qpm->sqp_info.n_ports)) {\r
- MTL_ERROR1("%s: port number (%d) not valid\n", __func__,port);\r
- return HH_EINVAL_PORT;\r
- }\r
-\r
- if (qpm->pkey_tbl[port-1] == NULL) {\r
- MTL_ERROR1("%s: ERROR: failure getting port %d pkey tbl\n",__func__,port);\r
- return HH_EINVAL_PARAM;\r
- }\r
-\r
- if (pkey_index >= qpm->pkey_tbl_sz[port-1]) {\r
- MTL_ERROR1("%s: given pkey_index (%d) is beyond pkey table end (%d entries)\n",__func__,\r
- pkey_index,qpm->pkey_tbl_sz[port-1]);\r
- return HH_EINVAL_PARAM;\r
- }\r
-\r
- *pkey_p = qpm->pkey_tbl[port-1][pkey_index];\r
- return HH_OK;\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_qpm_get_all_pkeys\r
- *****************************************************************************/\r
-HH_ret_t THH_qpm_get_all_pkeys(THH_qpm_t qpm, /* IN */\r
- IB_port_t port,/*IN */\r
- u_int16_t out_num_pkey_entries, /*IN */\r
- VAPI_pkey_t* pkey_p /*OUT*/\r
- )\r
-{\r
-\r
- if ((port<1) || (port > qpm->sqp_info.n_ports))\r
- {\r
- return HH_EINVAL_PORT;\r
- }\r
- \r
-\r
- if (qpm->pkey_tbl[port-1] == NULL) \r
- {\r
- MTL_ERROR1("[%s]: ERROR: failure getting port %d pkey tbl\n",__FUNCTION__,port);\r
- return HH_EINVAL_PARAM;\r
- }\r
-\r
- if (qpm->pkey_tbl_sz[port-1] > out_num_pkey_entries) {\r
- MTL_ERROR1("[%s]: ERROR: pkey out table too small (is %d, should be %d) \n",__FUNCTION__,\r
- out_num_pkey_entries, qpm->pkey_tbl_sz[port-1]);\r
- return HH_ERR;\r
- }\r
- MTL_DEBUG4("get Pkey table: port %d\n",port);\r
-\r
- memcpy(pkey_p, qpm->pkey_tbl[port-1], sizeof(VAPI_pkey_t)*qpm->pkey_tbl_sz[port-1]);\r
- return HH_OK;\r
-}\r
-\r
-\r
-static void printPKeyTable(THH_qpm_t qpm)\r
-{\r
-#if defined(MAX_DEBUG) && 5 <= MAX_DEBUG\r
- int i,j;\r
- \r
- for (i=0; i< qpm->sqp_info.n_ports; i++)\r
- {\r
- MTL_DEBUG5("port %d pkey tbl: \n",i+1);\r
- for (j=0; j< qpm->pkey_tbl_sz[i]; j++)\r
- {\r
- MTL_DEBUG5(" 0x%x ",qpm->pkey_tbl[i][j]);\r
- }\r
- MTL_DEBUG5("\n");\r
- }\r
-#else\r
- return;\r
-#endif\r
-}\r
-\r
-static void printGIDTable(THH_qpm_t qpm)\r
-{\r
-#if defined(MAX_DEBUG) && 5 <= MAX_DEBUG\r
- int i,k;\r
- \r
- for (k=0; k< qpm->sqp_info.n_ports; k++)\r
- {\r
- MTL_DEBUG5("port %d sgid tbl: \n",k+1);\r
- for (i=0; i< qpm->num_sgids[k]; i++)\r
- {\r
- MTL_DEBUG5("GID[%d] = %x.%x.%x.%x.%x.%x.%x.%x.%x.%x.%x.%x.%x.%x.%x.%x\n", k, \r
- qpm->sgid_tbl[k][i][0],qpm->sgid_tbl[k][i][1],qpm->sgid_tbl[k][i][2],qpm->sgid_tbl[k][i][3],\r
- qpm->sgid_tbl[k][i][4],qpm->sgid_tbl[k][i][5],qpm->sgid_tbl[k][i][6],qpm->sgid_tbl[k][i][7],\r
- qpm->sgid_tbl[k][i][8],qpm->sgid_tbl[k][i][9],qpm->sgid_tbl[k][i][10],qpm->sgid_tbl[k][i][11],\r
- qpm->sgid_tbl[k][i][12],qpm->sgid_tbl[k][i][13],qpm->sgid_tbl[k][i][14],qpm->sgid_tbl[k][i][15]); \r
- \r
- }\r
- MTL_DEBUG5("\n");\r
- }\r
-#else\r
- return;\r
-#endif\r
-}\r
-\r
-\r
-HH_ret_t THH_qpm_get_num_qps(THH_qpm_t qpm /* IN */, u_int32_t *num_qps_p /*OUT*/)\r
-{\r
- u_int32_t num_objs;\r
-\r
- if (qpm == NULL) {\r
- MTL_ERROR1("[%s]: ERROR : Invalid qpm handle\n",__FUNCTION__);\r
- return HH_EINVAL;\r
- }\r
-\r
- num_objs= VIP_array_get_num_of_objects(qpm->qp_tbl); \r
- if (num_objs == (u_int32_t) VIP_EINVAL_HNDL) {\r
- return HH_EINVAL;\r
- } else {\r
- *num_qps_p = num_objs;\r
- return HH_OK;\r
- }\r
-}\r
-\r
-#if defined(MT_SUSPEND_QP)\r
-/************************************************************************/\r
-/* Same comment about mutex as above THH_qpm_modify_qp(...) applies */\r
-HH_ret_t THH_qpm_suspend_qp(\r
- THH_qpm_t qpm, /* IN */\r
- IB_wqpn_t qpn, /* IN */\r
- MT_bool suspend_flag /* IN */\r
-)\r
-{\r
- HH_ret_t rc = HH_OK;\r
- VIP_common_ret_t vret;\r
- VIP_array_obj_t qp_obj;\r
- TQPM_sw_qpc_t* qp_p;\r
- u_int32_t qp_idx = qpn & qpm->idx_mask;\r
-\r
- MTL_TRACE1("{THH_qpm_suspend_qp: qpm=%p, qpn=0x%x, suspend_flag=%s\n", \r
- qpm, qpn, ((suspend_flag == TRUE) ? "TRUE" : "FALSE" ));\r
- if (is_sqp(qpm,qpn)) {\r
- if (MOSAL_mutex_acq(&qpm->mtx, TRUE) != MT_OK) return HH_EINTR;\r
- qp_p= qpm->sqp_info.sqp_ctx[qpn - qpm->sqp_info.first_sqp_qpn];\r
- if (qp_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: Given special QP handle is not active (qpn=0x%X)"),__func__,qpn);\r
- return HH_EINVAL_QP_NUM;\r
- }\r
- } else { /* regular QP */\r
- vret= VIP_array_find_hold(qpm->qp_tbl, qp_idx - qpm->first_rqp, &qp_obj);\r
- qp_p= (TQPM_sw_qpc_t*)qp_obj;\r
- if ((vret != VIP_OK) || (qpn != qp_p->qpn)) {\r
- MTL_ERROR1(MT_FLFMT("%s: Invalid QP handle (qpn=0x%X)"),__func__,qpn);\r
- if (vret == VIP_OK) VIP_array_find_release(qpm->qp_tbl, qp_idx - qpm->first_rqp);\r
- return HH_EINVAL_QP_NUM;\r
- }\r
- }\r
- \r
- /* issue tavor command in all cases, since we are not adding a "suspend" state to QP */\r
- do {\r
- THH_cmd_status_t crc;\r
- \r
- rc = HH_OK;\r
-\r
- if (qp_p->is_suspended == suspend_flag) {\r
- /* already in requested suspension state */\r
- MTL_ERROR1(MT_FLFMT("%s: qpn=0x%X is already in requested state (suspend = %s)"),\r
- __func__,qpn, (suspend_flag == FALSE)?"FALSE":"TRUE");\r
- break;\r
- }\r
- if (suspend_flag == FALSE) {\r
- /* unsuspend request -- restore the internal region */\r
- /* lkey = 0 ==> no send and no receive WQEs */\r
- if (qp_p->lkey != 0) {\r
- rc = THH_mrwm_suspend_internal(qpm->mrwm_internal,qp_p->lkey,FALSE);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: THH_mrwm_(un)suspend_internal failed (%d:%s). Region stays suspended"),\r
- __func__, rc, HH_strerror_sym(rc));\r
- break;\r
- }\r
- }\r
- }\r
- crc = THH_cmd_SUSPEND_QP(qpm->cmd_if, qpn, suspend_flag);\r
- if (crc == THH_CMD_STAT_OK)\r
- { \r
- rc = HH_OK;\r
- if (suspend_flag == TRUE) {\r
- /* suspend request -- suspend the internal region */\r
- /* lkey = 0 ==> no send and no receive WQEs */\r
- if (qp_p->lkey != 0) {\r
- rc = THH_mrwm_suspend_internal(qpm->mrwm_internal,qp_p->lkey,TRUE);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: suspend. THH_mrwm_suspend_internal failed (%d:%s). Suspended anyway"),\r
- __func__, rc, HH_strerror_sym(rc));\r
- rc = HH_OK;\r
- }\r
- }\r
- }\r
- } else {\r
- rc = ((crc == THH_CMD_STAT_BAD_PARAM) ? HH_EINVAL_PARAM :\r
- (crc == THH_CMD_STAT_BAD_INDEX) ? HH_EINVAL_QP_NUM : \r
- (crc == THH_CMD_STAT_BAD_RESOURCE) ? HH_EINVAL_QP_NUM : \r
- (crc == THH_CMD_STAT_BAD_RES_STATE) ? HH_EINVAL_QP_STATE : \r
- (crc == THH_CMD_STAT_BAD_QPEE_STATE) ? HH_EINVAL_QP_STATE : \r
- (crc == THH_CMD_STAT_BAD_QPEE_STATE) ? HH_EINVAL_QP_STATE : \r
- (crc == THH_CMD_STAT_BAD_SYS_STATE) ? HH_EINVAL_HCA_HNDL : \r
- (crc == THH_CMD_STAT_RESOURCE_BUSY) ? HH_EBUSY : HH_ERR);\r
- MTL_ERROR1(MT_FLFMT("ERROR: THH_cmd_SUSPEND_QP returned %s"),str_THH_cmd_status_t(crc));\r
- }\r
- qp_p->is_suspended = suspend_flag;\r
- } while(0);\r
-\r
- if (is_sqp(qpm,qpn)) {\r
- MOSAL_mutex_rel(&qpm->mtx);\r
- } else { /* regular RQ */\r
- VIP_array_find_release(qpm->qp_tbl, qp_idx - qpm->first_rqp);\r
- }\r
- logIfErr("THH_qpm_suspend_qp");\r
- return rc;\r
-} /* THH_qpm_query_qp */\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#if !defined(H_TQPM_H)\r
-#define H_TQPM_H\r
-\r
-#include <mtl_common.h>\r
-#include <vapi_types.h>\r
-#include <hh.h>\r
-#include <hhul.h>\r
-#include <thh.h>\r
-\r
-\r
-/************************************************************************\r
- * Structure to pass to THH_qpm_create(). Make sure to initialize\r
- * (via memset(&, 0, sizeof()) with zeros before setting fields.\r
- * Thus future enhancement may ease backward compatible.\r
- * \r
- * log2_max_qp - (log2) Max. number of QPs (QPC table size)\r
- * rdb_base_index - virtual index to area allocated by HOB (see PRM 5.2).\r
- * log2_max_outs_rdma_atom - log2 of number allocated per each QP,\r
- * statrting from rdb_base_index.\r
- * n_ports - Number of ports for this HCA. Needed for special QP allocation.\r
- */\r
-typedef struct\r
-{\r
- u_int32_t rdb_base_index;\r
- u_int8_t log2_max_qp;\r
- u_int8_t log2_rsvd_qps;\r
- u_int8_t log2_max_outs_rdma_atom;\r
- u_int8_t log2_max_outs_dst_rd_atom;\r
- u_int8_t n_ports;\r
- struct THH_port_init_props_st* port_props; /* (cmd_types.h) indexed from 1 */\r
-} THH_qpm_init_t;\r
-\r
-#define DEFAULT_SGID_TBL_SZ 32\r
-#define DEFAULT_PKEY_TBL_SZ 64\r
-#define NUM_PORTS 2 /* Hardware limit. Real n_ports is limited by the init params. */\r
-#define NUM_SQP_PER_PORT 4 /* SMI, GSI, RawEth, RawIPv6 */\r
-#define NUM_SQP (NUM_PORTS * NUM_SQP_PER_PORT)\r
-#define MAX_QPN_PREFIX_LOG 12\r
-#define MAX_QPN_PREFIX (1<<MAX_QPN_PREFIX_LOG)\r
-#define QPN_PREFIX_INDEX_MASK (MAX_QPN_PREFIX - 1)\r
-\r
-#define TQPM_GOOD_ALLOC(sz) THH_SMART_MALLOC(sz)\r
-#define TQPM_GOOD_FREE(ptr,sz) THH_SMART_FREE(ptr,sz)\r
-\r
-/************************************************************************\r
- * Function: THH_qpm_create\r
- *\r
- * Arguments:\r
- * hob - The THH_hob object in which this object will be included\r
- * init_attr_p Initialization parameters - see above.\r
- * cqm_p - The allocated QPM object\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- * HH_EAGAIN - Not enough resources available\r
- *\r
- * Description:\r
- * This function creates the THH_qpm object.\r
- */\r
-extern HH_ret_t THH_qpm_create(\r
- THH_hob_t hob, /* IN */\r
- const THH_qpm_init_t* init_attr_p, /* IN */\r
- THH_qpm_t* qpm_p /* OUT */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_qpm_destroy\r
- *\r
- * Arguments:\r
- * qpm - The object to destroy\r
- * hca_failure - When TRUE an HCA failure requires the destruction\r
- * of this object.\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid handle\r
- *\r
- * Description:\r
- * Free all QPM related resources.\r
- */\r
-extern HH_ret_t THH_qpm_destroy(\r
- THH_qpm_t qpm, /* IN */\r
- MT_bool hca_failure /* IN */\r
-);\r
-\r
-/************************************************************************\r
- * Function: THH_qpm_create_qp\r
- *\r
- * Arguments:\r
- * qpm - QPM object context\r
- * prot_ctx protection context of the calling thread\r
- * init_attr_p - QP's initial attributes\r
- * mlx - Ignore ts_type given in init_attr_p and make QP MLX\r
- * qp_ul_resources_p - Resources passed from user level.\r
- * qpn_p - The allocated QP handle\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- * HH_EAGAIN - Not enough resources available to complete operation\r
- *\r
- * Description:\r
- * Allocate a QP resource in the HCA (QP created in the Reset state).\r
- */\r
-extern HH_ret_t THH_qpm_create_qp(\r
- THH_qpm_t qpm, /* IN */\r
- HH_qp_init_attr_t* init_attr_p, /* IN */\r
- MT_bool mlx, /* IN */\r
- THH_qp_ul_resources_t* qp_ul_resources_p, /* IO */\r
- IB_wqpn_t* qpn_p /* OUT */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_qpm_get_special_qp\r
- * \r
- * Arguments:\r
- * qpm - QPM object context \r
- * qp_type - Special QP type \r
- * port - Special QP on given port \r
- * init_attr_p - QP's initial attributes \r
- * qp_ul_resources_p - Resources passed from user level \r
- * sqp_hndl_p - The allocated special QP handle (QPC index)\r
- * \r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- * HH_EAGAIN - Not enough resources available to complete operation\r
- * HH_EBUSY - Given QP type on given port is already in use \r
- */\r
-extern HH_ret_t THH_qpm_get_special_qp(\r
- THH_qpm_t qpm, /* IN */\r
- VAPI_special_qp_t qp_type, /* IN */\r
- IB_port_t port, /* IN */\r
- HH_qp_init_attr_t* init_attr_p, /* IN */\r
- THH_qp_ul_resources_t* qp_ul_resources_p, /* IO */\r
- IB_wqpn_t* sqp_hndl_p /* OUT */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_qpm_modify_qp\r
- *\r
- * Arguments:\r
- * qpm - THH_qpm object\r
- * qpn - The QP to modify\r
- * cur_qp_state - Assumed current QP state (modify from).\r
- * qp_attr_p - QP attributes structure\r
- * qp_attr_mask_p - Attributes actually valid in qp_attr_p\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters (NULL ptrs. etc.)\r
- * HH_EAGAIN - Not enough resources available to complete operation\r
- * HH_EINVAL_QP_NUM - Unknown QP\r
- * HH_EINVAL_QP_STATE - current_qp_state does not match actual QP state.\r
- *\r
- * Description:\r
- * Modify QP attributes and state.\r
- */\r
-extern HH_ret_t THH_qpm_modify_qp(\r
- THH_qpm_t qpm, /* IN */\r
- IB_wqpn_t qpn, /* IN */\r
- VAPI_qp_state_t cur_qp_state, /* IN */\r
- VAPI_qp_attr_t* qp_attr_p, /* IN */\r
- VAPI_qp_attr_mask_t* qp_attr_mask_p /* IN */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_qpm_query_qp\r
- * \r
- * Arguments:\r
- * qpm - THH_qpm object\r
- * qpn - The QP to modify\r
- * qp_attr_p - Returned QP attributes\r
- * \r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid handles\r
- * HH_EINVAL_QP_NUM\r
- * \r
- * Description:\r
- * Query QP state and attributes.\r
- */\r
-extern HH_ret_t THH_qpm_query_qp(\r
- THH_qpm_t qpm, /* IN */\r
- IB_wqpn_t qpn, /* IN */\r
- VAPI_qp_attr_t* qp_attr_p /* IN */\r
-);\r
-\r
-/************************************************************************\r
- * Function: THH_qpm_destroy_qp\r
- * \r
- * Arguments:\r
- * qpm - The THH_qpm object handle\r
- * qp - The QP to destroy\r
- * \r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid handles\r
- * \r
- * Description: Free QP resources.\r
- */\r
-\r
-extern HH_ret_t THH_qpm_destroy_qp(\r
- THH_qpm_t qpm, /* IN */\r
- IB_wqpn_t qp /* IN */\r
-);\r
-\r
-/************************************************************************\r
- * Function: THH_qpm_process_local_mad\r
- * \r
- * Arguments:\r
- * qpm - The THH_qpm object handle\r
- * port - the port the mad came in \r
- * proc_mad_opts - for setting non-default options\r
- * mad_in - \r
- * mad_out - \r
- * \r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid handles\r
- * HH_EINVAL_PORT - Invalid port \r
- * HH_ERR - error processing the mad\r
- * \r
- * Description: process the mad (FW) in the port \r
- */\r
-extern HH_ret_t THH_qpm_process_local_mad(THH_qpm_t qpm,\r
- IB_port_t port, IB_lid_t slid, /* For Mkey violation trap */\r
- EVAPI_proc_mad_opt_t proc_mad_opts, \r
- void* mad_in,void* mad_out_p);\r
-\r
-/************************************************************************\r
- * Function: THH_qpm_get_sgid\r
- * \r
- * Arguments:\r
- * qpm - The THH_qpm object handle\r
- * port - the port of the pkey table \r
- * idx - the index in the gid tbl\r
- * gid_p - \r
- * \r
- * Returns:\r
- * HH_OK\r
- * \r
- * Description: \r
- */\r
-HH_ret_t THH_qpm_get_sgid(THH_qpm_t qpm,IB_port_t port,u_int8_t idx, IB_gid_t* gid_p);\r
-\r
-/************************************************************************\r
- * Function: THH_qpm_get_all_sgids\r
- * \r
- * Arguments:\r
- * qpm - The THH_qpm object handle\r
- * port - the port of the pkey table \r
- * num_out_entries - the number of entries in the output gid tbl\r
- * gid_p - pointer to the output gid table \r
- * \r
- * Returns:\r
- * HH_OK\r
- * \r
- * Description: \r
- */\r
-HH_ret_t THH_qpm_get_all_sgids(THH_qpm_t qpm,IB_port_t port,u_int8_t num_out_entries, IB_gid_t* gid_p);\r
-\r
-/************************************************************************\r
- * Function: THH_qpm_get_qp1_pkey\r
- * \r
- * Arguments:\r
- * qpm - The THH_qpm object handle\r
- * port - the port of the pkey table \r
- * pkey_p - \r
- * \r
- * Returns:\r
- * HH_OK\r
- * \r
- * Description: \r
- */\r
-HH_ret_t THH_qpm_get_qp1_pkey(THH_qpm_t qpm,IB_port_t port,VAPI_pkey_t* pkey);\r
-\r
-/************************************************************************\r
- * Function: THH_qpm_get_qp1_pkey\r
- * \r
- * Arguments:\r
- * qpm - The THH_qpm object handle\r
- * port - the port of the pkey table \r
- * pkey_index - Index of Pkey to return\r
- * pkey_p - returned pkey\r
- * \r
- * Returns:\r
- * HH_EINVAL_PORT\r
- * HH_EINVAL_PARAM\r
- * HH_OK\r
- * \r
- * Description: \r
- * Return Pkey at given {port,index}\r
- */\r
-HH_ret_t THH_qpm_get_pkey(THH_qpm_t qpm, /* IN */\r
- IB_port_t port,/*IN */\r
- VAPI_pkey_ix_t pkey_index,/*IN*/\r
- VAPI_pkey_t* pkey_p/*OUT*/);\r
-\r
-/************************************************************************\r
- * Function: THH_qpm_get_all_pkeys\r
- * \r
- * Arguments:\r
- * qpm - The THH_qpm object handle\r
- * port - the port of the pkey table \r
- * out_num_pkey_entries - num of pkey entry slots in provided pkey table\r
- * pkey_p - output pkey table\r
- * \r
- * Returns:\r
- * HH_OK\r
- * \r
- * Description: \r
- */\r
-HH_ret_t THH_qpm_get_all_pkeys(THH_qpm_t qpm, IB_port_t port,\r
- u_int16_t out_num_pkey_entries, VAPI_pkey_t* pkey_p );\r
-\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_qpm_get_num_qps\r
- * \r
- * Arguments:\r
- * qpm - The THH_qpm object handle\r
- * num_qps_p - ptr to returned current num qps\r
- * \r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL -- if qpm invalid, or if vip array invalid.\r
- * \r
- * Description: \r
- * returns number of currently allocated QPs\r
- */\r
-HH_ret_t THH_qpm_get_num_qps(THH_qpm_t qpm /* IN */, u_int32_t *num_qps_p /*OUT*/);\r
-\r
-#if defined(MT_SUSPEND_QP)\r
-extern HH_ret_t THH_qpm_suspend_qp(\r
- THH_qpm_t qpm, /* IN */\r
- IB_wqpn_t qpn, /* IN */\r
- MT_bool suspend_flag /* IN */\r
-);\r
-#endif\r
-\r
-#endif /* H_TQPM_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
- \r
- \r
-/* DEFINES WHICH MAY BE USED TO CHANGE THE NUMBER AND PROPORTIONS */\r
-/* OF ALLOCATED RESOURCES */\r
-\r
-#ifndef H_THH_REQUESTED_PROFILE_H\r
-#define H_THH_REQUESTED_PROFILE_H\r
-\r
-\r
-#if 1\r
- /*standard default profile. Subtracts out the reserved resources from a power-of-2 */\r
- /*These values are used in THH_calculate_profile, in file thh_hob.c */\r
- /*The reserved resources are expressed in internal terms to guard against incompatibilities. */\r
-#define THH_PROF_MAX_QPS ((1<<16) - ((1<<hob->dev_lims.log2_rsvd_qps) + THH_NUM_RSVD_QP))\r
-#define THH_PROF_MAX_CQS ((1<<14) - (1<<hob->dev_lims.log2_rsvd_cqs))\r
-#define THH_PROF_MAX_PDS ((1<<14) - THH_NUM_RSVD_PD)\r
-#define THH_PROF_MAX_REGIONS ((1<<17) - (1 << hob->dev_lims.log2_rsvd_mtts))\r
-#define THH_PROF_MAX_WINDOWS ((1<<18) - (1 << hob->dev_lims.log2_rsvd_mrws))\r
-\r
-#define THH_PROF_MIN_QPS ((1<<14) - ((1<<hob->dev_lims.log2_rsvd_qps) + THH_NUM_RSVD_QP))\r
-#define THH_PROF_MIN_CQS ((1<<12) - (1<<hob->dev_lims.log2_rsvd_cqs))\r
-#define THH_PROF_MIN_PDS ((1<<12) - THH_NUM_RSVD_PD)\r
-#define THH_PROF_MIN_REGIONS ((1<<15) - (1 << hob->dev_lims.log2_rsvd_mtts))\r
-#define THH_PROF_MIN_WINDOWS ((1<<16) - (1 << hob->dev_lims.log2_rsvd_mrws))\r
-\r
-#else\r
- /* profile which will enable a maximum of\r
- * 1 million QPs, when the Tavor on-board memory\r
- * is 1 Gigabyte, at the expense of fewer CQs,\r
- * memory regions, and memory windows . To activate\r
- * this profile, change the "if 1" above to "if 0"\r
- * and recompile and reinstall the driver\r
- */\r
- \r
-#define THH_PROF_MAX_QPS ((1<<20) - 24)\r
-#define THH_PROF_MAX_CQS ((1<<18) - 128)\r
-#define THH_PROF_MAX_PDS ((1<<18) - 2)\r
-#define THH_PROF_MAX_REGIONS ((1<<18) - 16)\r
-#define THH_PROF_MAX_WINDOWS ((1<<19) - 16)\r
-\r
-#define THH_PROF_MIN_QPS ((1<<14) - 24)\r
-#define THH_PROF_MIN_CQS ((1<<17) - 128)\r
-#define THH_PROF_MIN_PDS ((1<<12) - 2)\r
-#define THH_PROF_MIN_REGIONS ((1<<18) - 16)\r
-#define THH_PROF_MIN_WINDOWS ((1<<19) - 16)\r
-\r
-#endif\r
-\r
-\r
-#define THH_PROF_PCNT_REDUCTION_QPS (50)\r
-#define THH_PROF_PCNT_REDUCTION_CQS (50)\r
-#define THH_PROF_PCNT_REDUCTION_PDS (50)\r
-#define THH_PROF_PCNT_REDUCTION_REGIONS (50)\r
-#define THH_PROF_PCNT_REDUCTION_WINDOWS (50)\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#define C_THH_SRQM_C\r
-\r
-#include <vapi_common.h>\r
-#include <vip_common.h>\r
-#include <vip_array.h>\r
-#include <thh_hob.h>\r
-#include <cmdif.h>\r
-#include <tmrwm.h>\r
-#include <thh_uldm.h>\r
-#include "thh_srqm.h"\r
-\r
-struct THH_srqm_st {\r
- VIP_array_p_t srq_array;\r
- THH_hob_t hob;\r
- THH_cmd_t cmdif;\r
- THH_mrwm_t mrwm;\r
- THH_uldm_t uldm;\r
- u_int32_t max_srq; /* Excluding reserved */\r
- u_int32_t rsvd_srq; /* Offset of first user SRQ from SRQC table base */\r
-};\r
-\r
-typedef struct THH_srq_st {\r
- VAPI_lkey_t lkey;\r
- /* No need for anything more for SRQ destruction. Still, VIP_array requires an "object" */\r
-} *THH_srq_t;\r
-\r
-/************************************************************************/\r
-/* Private functions */\r
-/************************************************************************/\r
-\r
-void free_srq_context(void* srq_context)\r
-{\r
- MTL_ERROR1(MT_FLFMT("THH_srqm_destroy: Garbage collection: Releasing SRQ #%u"),\r
- ((THH_srq_t)srq_context)->lkey);\r
- /* Internal memory regions are cleaned-up on THH_mrwm_destroy */\r
- FREE(srq_context);\r
-}\r
-\r
-\r
-/************************************************************************/\r
-/* Public functions */\r
-/************************************************************************/\r
-\r
-HH_ret_t THH_srqm_create(\r
- THH_hob_t hob, /* IN */\r
- u_int8_t log2_max_srq, /* IN */\r
- u_int8_t log2_rsvd_srq, /* IN */\r
- THH_srqm_t* srqm_p /* OUT */\r
-)\r
-{\r
- HH_ret_t ret;\r
- VIP_common_ret_t vret;\r
- u_int32_t rsvd_srq= 1 << log2_rsvd_srq;\r
- u_int32_t max_srq= (1 << log2_max_srq) - rsvd_srq;\r
- u_int32_t initial_array_sz= max_srq > 1024 ? 1024 : max_srq;\r
- MTL_DEBUG1(MT_FLFMT("%s: Invoked with log2_max_srq=0x%u log2_rsrv_srq=0x%u srqm_p=0x%p"), \r
- __func__, log2_max_srq, log2_rsvd_srq, srqm_p);\r
- \r
- *srqm_p= MALLOC(sizeof(struct THH_srqm_st));\r
- if (*srqm_p == NULL) return HH_EAGAIN;\r
-\r
- vret= VIP_array_create_maxsize(initial_array_sz, max_srq, &(*srqm_p)->srq_array);\r
- if (vret != VIP_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed VIP_array_create_maxsize (%u-%s)"), __func__, \r
- vret, VAPI_strerror_sym(vret));\r
- ret= HH_EAGAIN;\r
- goto vip_array_create_failed;\r
- }\r
-\r
- ret= THH_hob_get_cmd_if(hob, &(*srqm_p)->cmdif);\r
- if (ret != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed THH_hob_get_cmd_if (%s)"), __func__, HH_strerror_sym(ret));\r
- goto get_failed;\r
- }\r
-\r
- ret= THH_hob_get_mrwm(hob, &(*srqm_p)->mrwm);\r
- if (ret != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed THH_hob_get_mrwm (%s)"), __func__, HH_strerror_sym(ret));\r
- goto get_failed;\r
- }\r
-\r
- ret= THH_hob_get_uldm(hob, &(*srqm_p)->uldm);\r
- if (ret != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed THH_hob_get_uldm (%s)"), __func__, HH_strerror_sym(ret));\r
- goto get_failed;\r
- }\r
-\r
- (*srqm_p)->hob= hob;\r
- (*srqm_p)->max_srq= max_srq;\r
- (*srqm_p)->rsvd_srq= rsvd_srq;\r
- \r
- return HH_OK;\r
-\r
- get_failed:\r
- VIP_array_destroy((*srqm_p)->srq_array, NULL);\r
- vip_array_create_failed:\r
- FREE(*srqm_p);\r
- return ret;\r
-}\r
-\r
-\r
-HH_ret_t THH_srqm_destroy(\r
- THH_srqm_t srqm /* IN */\r
-)\r
-{\r
- VIP_common_ret_t vret;\r
- \r
- if (srqm == (THH_srqm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1(MT_FLFMT("%s: Invoked for THH_INVALID_HNDL"), __func__);\r
- return HH_EINVAL;\r
- }\r
- MTL_DEBUG1(MT_FLFMT("%s: Releasing SRQM handle 0x%p"), __func__, srqm);\r
-\r
- /* In case of abnormal HCA termination we may still have unreleased SRQ resources */\r
- vret= VIP_array_destroy(srqm->srq_array, free_srq_context);\r
- if (vret != VIP_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed VIP_array_destroy (%u-%s) - completing SRQM destroy anyway"),\r
- __func__, vret, VAPI_strerror_sym(vret));\r
- }\r
-\r
- FREE(srqm);\r
-\r
- return HH_OK;\r
-}\r
-\r
-\r
-HH_ret_t THH_srqm_create_srq(\r
- THH_srqm_t srqm, /* IN */\r
- HH_pd_hndl_t pd, /* IN */\r
- THH_srq_ul_resources_t *srq_ul_resources_p, /* IO */\r
- HH_srq_hndl_t *srq_p /* OUT */\r
-)\r
-{\r
- HH_ret_t ret;\r
- THH_cmd_status_t cmd_ret;\r
- VIP_common_ret_t vret;\r
- VIP_array_handle_t vip_hndl;\r
- THH_srq_t srq;\r
- THH_internal_mr_t mr_props;\r
- MOSAL_prot_ctx_t vm_ctx;\r
- u_int32_t srqn;\r
- THH_srq_context_t thh_srqc;\r
-\r
- if (srq_ul_resources_p->wqes_buf == 0) {\r
- MTL_ERROR1(MT_FLFMT("%s: Got wqes_buf=NULL. WQEs in DDR-mem are not supported, yet."), \r
- __func__);\r
- return HH_ENOSYS;\r
- }\r
-\r
- ret = THH_uldm_get_protection_ctx(srqm->uldm, pd, &vm_ctx);\r
- if (ret != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed THH_uldm_get_protection_ctx (%s)"), __func__, \r
- mtl_strerror_sym(ret));\r
- return ret;\r
- }\r
-\r
- srq= MALLOC(sizeof(struct THH_srq_st));\r
- if (srq == NULL) {\r
- return HH_EAGAIN;\r
- }\r
-\r
- vret= VIP_array_insert(srqm->srq_array, srq, &vip_hndl);\r
- if (vret != VIP_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed VIP_array_insert (%u)"), __func__, vret);\r
- ret= HH_EAGAIN;\r
- goto vip_array_insert_failed;\r
- }\r
-\r
- memset(&mr_props, 0, sizeof(mr_props));\r
- mr_props.start= srq_ul_resources_p->wqes_buf;\r
- mr_props.size= srq_ul_resources_p->wqes_buf_sz;\r
- mr_props.pd= pd;\r
- mr_props.vm_ctx= vm_ctx;\r
- mr_props.force_memkey = FALSE;\r
- ret= THH_mrwm_register_internal(srqm->mrwm, &mr_props, &srq->lkey);\r
- if (ret != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed THH_mrwm_register_internal (%s)"), __func__, \r
- HH_strerror_sym(ret));\r
- goto register_internal_failed;\r
- }\r
-\r
- srqn= vip_hndl + srqm->rsvd_srq;\r
-\r
- thh_srqc.pd= pd;\r
- thh_srqc.l_key= srq->lkey;\r
- thh_srqc.wqe_addr_h= /* Upper 32b of WQEs buffer */\r
- (u_int32_t)((sizeof(MT_virt_addr_t) > 4) ? (srq_ul_resources_p->wqes_buf >> 32) : 0);\r
- thh_srqc.ds= (u_int32_t)(srq_ul_resources_p->wqe_sz >> 4); /* 16B chunks */\r
- if (thh_srqc.ds > 0x3F) \r
- thh_srqc.ds=0x3F; /* Stride may be 1024, but max WQE size is 1008 (ds is 6bit) */\r
- thh_srqc.uar= srq_ul_resources_p->uar_index;\r
- cmd_ret= THH_cmd_SW2HW_SRQ(srqm->cmdif, srqn, &thh_srqc);\r
- if (cmd_ret != THH_CMD_STAT_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed THH_cmd_SW2HW_SRQ for srqn=0x%X (%s)"), __func__, \r
- srqn, str_THH_cmd_status_t(cmd_ret));\r
- ret= HH_EFATAL; /* Unexpected error */\r
- goto sw2hw_failed;\r
- }\r
-\r
- *srq_p= srqn;\r
- MTL_DEBUG4(MT_FLFMT("%s: Allocated SRQn=0x%X"), __func__, srqn); \r
- return HH_OK;\r
-\r
- sw2hw_failed:\r
- THH_mrwm_deregister_mr(srqm->mrwm, srq->lkey);\r
- register_internal_failed:\r
- VIP_array_erase(srqm->srq_array, vip_hndl, NULL);\r
- vip_array_insert_failed:\r
- FREE(srq);\r
- return ret;\r
-}\r
-\r
-HH_ret_t THH_srqm_destroy_srq(\r
- THH_srqm_t srqm, /* IN */\r
- HH_srq_hndl_t srqn /* IN */\r
-)\r
-{\r
- HH_ret_t ret;\r
- THH_cmd_status_t cmd_ret;\r
- VIP_common_ret_t vret;\r
- VIP_array_obj_t vip_obj;\r
- THH_srq_t srq;\r
- MT_bool have_fatal= FALSE;\r
-\r
- vret= VIP_array_erase_prepare(srqm->srq_array, srqn - srqm->rsvd_srq, &vip_obj);\r
- if (vret != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed VIP_array_erase_prepare (%u)"), __func__, vret);\r
- return HH_EINVAL;\r
- }\r
- srq= (THH_srq_t)vip_obj;\r
-\r
- cmd_ret= THH_cmd_HW2SW_SRQ(srqm->cmdif, srqn, NULL);\r
- if (cmd_ret != THH_CMD_STAT_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: Failed THH_cmd_SW2HW_SRQ for srqn=0x%X (%s)"), __func__, \r
- srqn, str_THH_cmd_status_t(cmd_ret));\r
- have_fatal= TRUE; /* Unexpected error */\r
- } else {\r
- ret= THH_mrwm_deregister_mr(srqm->mrwm, srq->lkey);\r
- if (ret != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed THH_mrwm_deregister_mr (%s)"), __func__,\r
- HH_strerror_sym(ret));\r
- have_fatal= TRUE;\r
- }\r
- }\r
-\r
- if (!have_fatal) {\r
- vret= VIP_array_erase_done(srqm->srq_array, srqn - srqm->rsvd_srq, NULL);\r
- if (vret != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed VIP_array_erase_done (%u)"), __func__, vret);\r
- have_fatal= TRUE;\r
- } else {\r
- FREE(srq);\r
- }\r
-\r
- } else {\r
- VIP_array_erase_undo(srqm->srq_array, srqn - srqm->rsvd_srq); \r
- /* Leave for srqm_destroy cleanup */\r
- }\r
-\r
- return HH_OK; /* resource cleanup is always OK - even if fatal */\r
-}\r
-\r
-\r
-HH_ret_t THH_srqm_query_srq(\r
- THH_srqm_t srqm, /* IN */\r
- HH_srq_hndl_t srq, /* IN */\r
- u_int32_t *limit_p /* OUT */\r
-)\r
-{\r
- VIP_common_ret_t vret;\r
- \r
- vret= VIP_array_find_hold(srqm->srq_array, srq - srqm->rsvd_srq, NULL);\r
- if (vret != HH_OK) {\r
- return HH_EINVAL_SRQ_HNDL;\r
- }\r
-\r
- *limit_p= 0; /* Tavor does not support SRQ limit, so the limit event is disarmed */\r
-\r
- VIP_array_find_release(srqm->srq_array, srq - srqm->rsvd_srq);\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THH_srqm_modify_srq(\r
- THH_srqm_t srqm, /* IN */\r
- HH_srq_hndl_t srqn, /* IN */\r
- THH_srq_ul_resources_t *srq_ul_resources_p /* IO */\r
-)\r
-{\r
- HH_ret_t ret = HH_OK;\r
- VIP_common_ret_t vret;\r
- VIP_array_obj_t vip_obj;\r
- THH_srq_t srq_obj;\r
- THH_internal_mr_t mr_props;\r
- THH_mrwm_modify_flags_t flags = THH_MRWM_MODIFY_FLAGS_TRANSLATION;\r
-\r
- MTL_TRACE1(MT_FLFMT("%s: SRQn=0x%X"), __func__, srqn);\r
-\r
- if (srq_ul_resources_p->wqes_buf_sz == 0) {\r
- /* "Shrinking" SRQ succeeds with NOP */\r
- return HH_OK;\r
- }\r
-\r
- if (srq_ul_resources_p->wqes_buf == 0) {\r
- MTL_ERROR1(MT_FLFMT("%s: Got wqes_buf=NULL. WQEs in DDR-mem are not supported, yet."), \r
- __func__);\r
- return HH_ENOSYS;\r
- }\r
-\r
- vret= VIP_array_find_hold(srqm->srq_array, srqn - srqm->rsvd_srq, &vip_obj);\r
- if (vret != HH_OK) {\r
- return HH_EINVAL_SRQ_HNDL;\r
- }\r
- srq_obj= (THH_srq_t)vip_obj;\r
-\r
- memset(&mr_props, 0, sizeof(mr_props));\r
- mr_props.start= srq_ul_resources_p->wqes_buf;\r
- mr_props.size= srq_ul_resources_p->wqes_buf_sz;\r
-\r
- ret= THH_mrwm_modify_internal(srqm->mrwm, srq_obj->lkey, &mr_props, flags);\r
- if (ret != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed THH_mrwm_modify_internal (%d: %s), start="VIRT_ADDR_FMT", size="SIZE_T_DFMT),\r
- __func__, ret, HH_strerror_sym(ret), srq_ul_resources_p->wqes_buf, srq_ul_resources_p->wqes_buf_sz);\r
- } else {\r
- MTL_DEBUG4(MT_FLFMT("%s: modified SRQn=0x%X. start="VIRT_ADDR_FMT", new size="SIZE_T_DFMT), \r
- __func__, srqn, srq_ul_resources_p->wqes_buf, srq_ul_resources_p->wqes_buf_sz); \r
- }\r
- VIP_array_find_release(srqm->srq_array, srqn - srqm->rsvd_srq);\r
- return ret;\r
-}\r
-\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_THH_SRQM_H\r
-#define H_THH_SRQM_H\r
-\r
-#include <mtl_common.h>\r
-#include <vapi_types.h>\r
-#include <hh.h>\r
-#include <hhul.h>\r
-#include <thh.h>\r
-\r
-/************************************************************************\r
- * Function: THH_srqm_create\r
- *\r
- * Arguments:\r
- * hob - The THH_hob object in which this object will be included\r
- * log2_max_srq - Size of SRQC table\r
- * log2_rsvd_srq - Log2 number of reserved SRQs\r
- * srqm_p - Returned SRQ object\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- * HH_EAGAIN - Not enough resources available\r
- *\r
- * Description:\r
- * This function creates the THH_srqm object.\r
- */\r
-HH_ret_t THH_srqm_create(\r
- THH_hob_t hob, /* IN */\r
- u_int8_t log2_max_srq, /* IN */\r
- u_int8_t log2_rsvd_srq, /* IN */\r
- THH_srqm_t* srqm_p /* OUT */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_srqm_destroy\r
- *\r
- * Arguments:\r
- * srqm - The object to destroy\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid handle\r
- *\r
- * Description:\r
- * Free all SRQM related resources.\r
- */\r
-HH_ret_t THH_srqm_destroy(\r
- THH_srqm_t srqm /* IN */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_srqm_create_srq\r
- *\r
- * Arguments:\r
- * srqm - HCA (SRQM) context\r
- * pd - PD of SRQ to create\r
- * srq_ul_resources_p - THH's private SRQ attributes (WQEs buffer, etc.)\r
- * srq_p - New SRQ handle\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- * HH_EAGAIN - Not enough resources available to complete operation\r
- *\r
- * Description:\r
- * Allocate a SRQ resource in the HCA.\r
- */\r
-HH_ret_t THH_srqm_create_srq(\r
- THH_srqm_t srqm, /* IN */\r
- HH_pd_hndl_t pd, /* IN */\r
- THH_srq_ul_resources_t *srq_ul_resources_p, /* IO */\r
- HH_srq_hndl_t *srq_p /* OUT */\r
-);\r
-\r
-/************************************************************************\r
- * Function: THH_srqm_destroy_srq\r
- *\r
- * Arguments:\r
- * srqm - HCA (SRQM) context\r
- * srq - SRQ to destroy\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameters\r
- *\r
- * Description:\r
- * Release a SRQ resource. No checks for associated QPs (VIP's responsibility).\r
- */\r
-HH_ret_t THH_srqm_destroy_srq(\r
- THH_srqm_t srqm, /* IN */\r
- HH_srq_hndl_t srq /* IN */\r
-);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_srqm_query_srq\r
- *\r
- * Arguments:\r
- * srqm - HCA (SRQM) context\r
- * srq - SRQ to query\r
- * limit_p - Current SRQ limit\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_ESRQ - SRQ is in error state\r
- * HH_EINVAL - Invalid parameters\r
- *\r
- * Description:\r
- * Query SRQ's limit (and state).\r
- */\r
-HH_ret_t THH_srqm_query_srq(\r
- THH_srqm_t srqm, /* IN */\r
- HH_srq_hndl_t srq, /* IN */\r
- u_int32_t *limit_p /* OUT */\r
-);\r
-\r
-/************************************************************************\r
- * Function: THH_srqm_modify_srq\r
- *\r
- * Arguments:\r
- * srqm - HCA (SRQM) context\r
- * srq - SRQ to modify\r
- * \r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_ESRQ - SRQ is in error state\r
- * HH_EINVAL - Invalid parameters\r
- * HH_EAGAIN - Not enough resources available to complete operation\r
- *\r
- * Description:\r
- * Modify SRQ's size or limit.\r
- */\r
-HH_ret_t THH_srqm_modify_srq(\r
- THH_srqm_t srqm, /* IN */\r
- HH_srq_hndl_t srq, /* IN */\r
- THH_srq_ul_resources_t *srq_ul_resources_p /* IO */\r
-);\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_THHUL_H\r
-#define H_THHUL_H\r
-\r
-#include "thh_common.h"\r
- \r
-/* THHUL objects handles */\r
-typedef struct THHUL_hob_st *THHUL_hob_t;\r
-typedef struct THHUL_pdm_st *THHUL_pdm_t;\r
-typedef struct THHUL_cqm_st *THHUL_cqm_t;\r
-typedef struct THHUL_qpm_st *THHUL_qpm_t;\r
-typedef struct THHUL_srqm_st *THHUL_srqm_t;\r
-typedef struct THHUL_mwm_st *THHUL_mwm_t;\r
-\r
-#endif /* H_THHUL_H */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#define C_THHUL_CQM_C\r
-\r
-#include <hh.h>\r
-#include <hhul.h>\r
-#include <MT23108.h>\r
-#include <MT23108_PRM.h>\r
-#include <thhul.h>\r
-#include <thhul_hob.h>\r
-#include <thhul_srqm.h>\r
-#include <thhul_qpm.h>\r
-#include <uar.h>\r
-#include "thhul_cqm.h"\r
-\r
-#include <mtperf.h>\r
-MTPERF_NEW_SEGMENT(free_cqe,5000);\r
-\r
-/* Uncomment the line below in order to get CQ dump when the same WQE is used twice simultaneously*/\r
-/* #define THHUL_CQM_DEBUG_WQE_REUSE */\r
-\r
-/* Always support fork (assumes number of CQs per process is limited) */\r
-#define MT_FORK_SUPPORT\r
-\r
-\r
-/* Limit kmalloc to 2 pages (if this fails, vmalloc will fail too) */\r
-#define CQ_KMALLOC_LIMIT (2*MOSAL_SYS_PAGE_SIZE)\r
-\r
-/* Maximum CQ doorbell to coalesce/delay (too much is not effective ?) */\r
-#define MAX_CQDB2DELAY 255\r
-\r
-/* CQE size */\r
-#define LOG2_CQE_SZ 5 /* 32 bytes */\r
-#define CQE_SZ (1U<<LOG2_CQE_SZ)\r
-\r
-/* Assuming that in original CQE (big-endian) the owner field is in the last byte (bit 7) */\r
-#define CQE_OWNER_SHIFT 7 /* Bit of ownership (in the byte) */\r
-#define CQE_OWNER_BYTE_OFFSET 0x1F /* Last byte of a CQE */\r
-#define CQE_OPCODE_BYTE_OFFSET 0x1C /* Opcode/status byte */\r
-#define CQE_S_BYTE_OFFSET 0x1D /* Send queue bit at MSb position */\r
-#define CQE_S_BYTE_MASK 0x80\r
-#define CQE_WQE_ADR_BIT_SZ 6 /* Number of bits in "wqe_adr" field */\r
-\r
-/* new CQE error handling */\r
-#define CQE_ERROR_ON_SQ 0xFF /* Opcode field value for SQ completion error */\r
-#define CQE_ERROR_ON_RQ 0xFE /* Opcode field value for RQ completion error */\r
-#define CQE_ERROR_STATUS_MASK 0xFE /* Common mask for both 0xFF and 0xFE "error status" opcodes */\r
-#define CQE_ERROR_SYNDROM_BIT_OFFSET (MT_BIT_OFFSET(tavorprm_completion_queue_entry_st,\\r
- immediate_ethertype_pkey_indx_eecredits)+24)\r
-#define CQE_ERROR_SYNDROM_BIT_SIZE 8 \r
-#define CQE_ERROR_VENDOR_SYNDROM_BIT_OFFSET (CQE_ERROR_SYNDROM_BIT_OFFSET-8)\r
-#define CQE_ERROR_VENDOR_SYNDROM_BIT_SIZE 8\r
-#define CQE_ERROR_DBDCNT_BIT_OFFSET (MT_BIT_OFFSET(tavorprm_completion_queue_entry_st,\\r
- immediate_ethertype_pkey_indx_eecredits))\r
-#define CQE_ERROR_DBDCNT_BIT_SIZE 16 \r
-\r
-\r
-#define MAX_CQ_NUM 0x00FFFFFF\r
-#define INVALID_CQ_NUM 0xFFFFFFFF\r
-#define MAX_NCOMP_NOTIF 0x7FFF /* req_ncomp_notif support up to 2^15-1 */\r
-\r
-/* IB opcodes for RQ CQEs (bits 4:0) */\r
-typedef enum {\r
- IB_OP_SEND_LAST =2,\r
- IB_OP_SEND_ONLY =4,\r
- IB_OP_SEND_IMM_LAST =3,\r
- IB_OP_SEND_IMM_ONLY =5,\r
- IB_OP_RDMAW_IMM_LAST =9,\r
- IB_OP_RDMAW_IMM_ONLY =11\r
-} THHUL_ib_opcode_t;\r
-\r
-\r
-typedef enum {\r
- THHUL_CQ_PREP, /* Before THHUL_cqm_create_cq_done */\r
- THHUL_CQ_IDLE, /* No resize is in progress */\r
- THHUL_CQ_RESIZE_PREP, /* Allocation and activation of resized buffer is in progress\r
- (before return from HH_resize_cq) */\r
- THHUL_CQ_RESIZE_DONE /* In fixed resize-CQ flow, the transition to the resized buffer may \r
- * happen before the return from VIPKL_resize_cq \r
- * (before THHUL_cqm_resize_cq_done) */\r
-} THHUL_cq_state_t;\r
-\r
-typedef struct {\r
- void* cqe_buf_orig; /* Address returned from VMALLOC */\r
- MT_virt_addr_t cqe_buf_base; /* Aligned to CQE size */\r
- u_int8_t log2_num_o_cqes; /* (log2) number of CQEs in the buffer (including one reserved) */\r
- u_int16_t spare_cqes; /* CQEs beyond requested number of CQEs for this buffer */\r
- u_int32_t consumer_index;\r
-} THHUL_cqe_buf_t;\r
-\r
-typedef struct THHUL_cq_st {\r
- THHUL_cqe_buf_t cur_buf;/* Main CQ buffer properties */\r
- THHUL_cqe_buf_t resized_buf;/* Next (resized) CQ buffer properties */\r
- u_int32_t pending_cq_dbell; /* Pending CQ doorbells \r
- * (DBs to rung when reach spare_cqes or on event req.) */\r
- u_int32_t cur_spare_cqes; /* CQEs beyond requested number of CQEs (for CQ DB coalescing) */\r
- THHUL_cq_state_t cq_state;\r
- THH_uar_t uar;\r
- HH_cq_hndl_t cq_num; /* Hardware CQ number */\r
- THHUL_qpm_t qpm; /* Make this available close to the CQ context */\r
- MOSAL_spinlock_t cq_lock;\r
- MT_bool cq_resize_fixed; /* FW fix for FM issue #16966/#17002: comp. events during resize */\r
- /* Above piece of information is held here to reduce overhead when polling the CQ */\r
- /* (on account of memory footprint) */\r
- /* CQ list administration */\r
- struct THHUL_cq_st *next;\r
-} THHUL_cq_t;\r
-\r
-struct THHUL_cqm_st {\r
- THHUL_cq_t *cq_list;\r
- MOSAL_mutex_t cqm_lock; /* This protects list - not time critical (only for adding/removing) */\r
-} /* *THHUL_cqm_t */;\r
-\r
-struct THHUL_cqe_st {\r
- IB_wqpn_t qpn;\r
- IB_eecn_t eecn;\r
- IB_wqpn_t rqpn;\r
- IB_sl_t sl;\r
- MT_bool grh_present;\r
- u_int8_t ml_path;\r
- IB_lid_t rlid;\r
-\r
-} THHUL_cqe_t;\r
-\r
-#ifdef THHUL_CQM_DEBUG_WQE_REUSE\r
-#define DUMP_CQE_PRINT_CMD MTL_ERROR4\r
-#else\r
-#define DUMP_CQE_PRINT_CMD MTL_DEBUG4\r
-#endif\r
-\r
-#define DUMP_CQE(cq_num,cqe_index,cqe) \\r
- {DUMP_CQE_PRINT_CMD("CQ[0x%X]:cqe[0x%X] = %08X %08X %08X %08X %08X %08X %08X %08X\n", \\r
- cq_num,cqe_index, \\r
- MOSAL_be32_to_cpu(cqe[0]), \\r
- MOSAL_be32_to_cpu(cqe[1]), \\r
- MOSAL_be32_to_cpu(cqe[2]), \\r
- MOSAL_be32_to_cpu(cqe[3]), \\r
- MOSAL_be32_to_cpu(cqe[4]), \\r
- MOSAL_be32_to_cpu(cqe[5]), \\r
- MOSAL_be32_to_cpu(cqe[6]), \\r
- MOSAL_be32_to_cpu(cqe[7]));}\r
-\r
-\r
-/**********************************************************************************************\r
- * Private inline functions \r
- **********************************************************************************************/\r
-\r
-/* Check if a CQE is in hardware ownership (over original CQE) */\r
-inline static MT_bool is_cqe_hw_own(volatile u_int32_t* cqe_p)\r
-{\r
- return (((volatile u_int8_t*)cqe_p)[CQE_OWNER_BYTE_OFFSET] >> CQE_OWNER_SHIFT); \r
- /* bit is '1 for HW-own.*/\r
-}\r
-\r
-/* Return CQE to HW ownership (change bit directly over CQE) */\r
-inline static void\r
-set_cqe_to_hw_own(\r
- IN volatile u_int32_t* const cqe_p )\r
-{\r
- ((volatile u_int8_t*)cqe_p)[CQE_OWNER_BYTE_OFFSET]= (1 << CQE_OWNER_SHIFT);\r
-}\r
-\r
-/* Set ownership of CQE to hardware ownership (over original CQE) and */\r
-/* increment consumer index (software + hardware) */\r
-/* This function assumes CQ lock is already acquired by this thread */\r
-#if 0 /* oRiginal code */\r
-inline static void free_cqe(THHUL_cq_t *cq_p, volatile u_int32_t* cqe_p)\r
-{\r
-#ifndef NO_CQ_CI_DBELL\r
- HH_ret_t rc = HH_OK;\r
-#endif \r
- /* Pass ownership to HW */\r
- set_cqe_to_hw_own(cqe_p);\r
- \r
-#ifndef NO_CQ_CI_DBELL\r
- if (cq_p->pending_cq_dbell >= cq_p->cur_spare_cqes) {\r
- MTL_DEBUG4(MT_FLFMT("%s: Ringing CQ DB (CQN=0x%X) to increment CI by %u"),__func__,\r
- cq_p->cq_num, cq_p->pending_cq_dbell+1);\r
- /* Ring CQ-cmd doorbell to update consumer index (pending + this CQE)*/\r
- rc= THH_uar_cq_cmd(cq_p->uar,TAVOR_IF_UAR_CQ_INC_CI,cq_p->cq_num,cq_p->pending_cq_dbell);\r
- if (MOSAL_EXPECT_FALSE(rc != HH_OK)) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed THH_uar_cq_cmd (%s)"), __func__, HH_strerror_sym(rc));\r
- /* Even though, this is not a show stopper. Let's continue until we get CQ error. */\r
- cq_p->pending_cq_dbell++; /* Maybe we will get luckier next time */\r
- } else {\r
- cq_p->pending_cq_dbell= 0;\r
- }\r
- } else { /* postpone CQ doorbell ringing on account of spare CQEs */\r
- cq_p->pending_cq_dbell++;\r
- }\r
-#endif /* NO_CQ_CI_DBELL */\r
- /* Update software consumer index */\r
- /*(modulo number of CQEs in buffer, which is one more than the maximum CQEs outstanding) */ \r
- cq_p->cur_buf.consumer_index= (cq_p->cur_buf.consumer_index + 1) & MASK32(cq_p->cur_buf.log2_num_o_cqes); \r
-}\r
-#else /*free_wqe */\r
-//TODO: cnt should be 32-bits.\r
-inline static void\r
-dbell_cqe(THHUL_cq_t *cq_p, uint32_t cnt )\r
-{\r
-#ifndef NO_CQ_CI_DBELL\r
- volatile u_int32_t chimeWords[2];\r
- THH_uar_t uar = cq_p->uar;\r
-\r
- cq_p->pending_cq_dbell += cnt;\r
-\r
- if( cq_p->pending_cq_dbell >= cq_p->cur_spare_cqes )\r
- {\r
- MTL_DEBUG4(MT_FLFMT("%s: Ringing CQ DB (CQN=0x%X) to increment CI by %u"),__func__,\r
- cq_p->cq_num, cq_p->pending_cq_dbell+1);\r
- /* Ring CQ-cmd doorbell to update consumer index (pending + this CQE)*/\r
- chimeWords[0] = MOSAL_cpu_to_be32(0\r
- | (u_int32_t)cq_p->cq_num\r
- | (TAVOR_IF_UAR_CQ_INC_CI << CQ_CMD_DBELL_BIT_OFFSET)\r
- );\r
- /* Subtract one since the doorbell value of zero increments by one. */\r
- chimeWords[1] = MOSAL_cpu_to_be32(--cq_p->pending_cq_dbell);\r
-\r
-#ifdef __MOSAL_MMAP_IO_WRITE_QWORD_ATOMIC__\r
- MOSAL_MMAP_IO_WRITE_QWORD(uar->uar_base + UAR_CQ_DBELL_OFFSET, *(volatile u_int64_t*)chimeWords);\r
-#else\r
- MOSAL_spinlock_dpc_lock(&(uar->uar_lock));\r
- MOSAL_MMAP_IO_WRITE_QWORD(uar->uar_base + UAR_CQ_DBELL_OFFSET, *(volatile u_int64_t*)chimeWords);\r
- MOSAL_spinlock_unlock(&(uar->uar_lock));\r
-#endif\r
-\r
- cq_p->pending_cq_dbell= 0;\r
- }\r
-#endif /* NO_CQ_CI_DBELL */\r
-}\r
-\r
-inline static void free_cqe(THHUL_cq_t *cq_p, volatile u_int32_t* cqe_p)\r
-{\r
- /* Pass ownership to HW */\r
- set_cqe_to_hw_own( cqe_p );\r
-\r
- dbell_cqe( cq_p, 1 );\r
-\r
- /* Update software consumer index */\r
- /*(modulo number of CQEs in buffer, which is one more than the maximum CQEs outstanding) */ \r
- cq_p->cur_buf.consumer_index= (cq_p->cur_buf.consumer_index + 1) & MASK32(cq_p->cur_buf.log2_num_o_cqes); \r
-}\r
-#endif\r
-\r
-\r
-/* Reuse given CQE in order to report "flush-error" for the next WQE in a queue */\r
-inline static void recycle_cqe(volatile u_int32_t* cqe_p, \r
- u_int32_t next_wqe_addr_32lsb, u_int32_t new_dbd_cnt)\r
-{\r
- /* Operations done directly on original "big-endian" CQE */\r
- /* Set next WQE's address */\r
- cqe_p[MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,wqe_adr)>>2]= MOSAL_cpu_to_be32(\r
- next_wqe_addr_32lsb & (~MASK32(CQE_WQE_ADR_BIT_SZ)) ); /* Mask off "wqe_adr" */\r
- /* Mark as "ERR_FLUSH" with updated dbd_cnt */\r
- cqe_p[MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,immediate_ethertype_pkey_indx_eecredits)>>2]=\r
- MOSAL_cpu_to_be32(\r
- (TAVOR_IF_COMP_STATUS_ERR_FLUSH << (CQE_ERROR_SYNDROM_BIT_OFFSET & MASK32(5)) ) |\r
- new_dbd_cnt);\r
-}\r
-\r
-/* Translate from Tavor's error syndrom (in CQE.ib_syn) status encoding to VAPI's */\r
-inline static VAPI_wc_status_t decode_error_syndrome(tavor_if_comp_status_t tstatus)\r
-{\r
- switch (tstatus) {\r
- case TAVOR_IF_COMP_STATUS_ERR_LCL_LEN: \r
- return VAPI_LOC_LEN_ERR;\r
- case TAVOR_IF_COMP_STATUS_ERR_LCL_QP_OP:\r
- return VAPI_LOC_QP_OP_ERR;\r
- case TAVOR_IF_COMP_STATUS_ERR_LCL_EE_OP:\r
- return VAPI_LOC_EE_OP_ERR;\r
- case TAVOR_IF_COMP_STATUS_ERR_LCL_PROT:\r
- return VAPI_LOC_PROT_ERR;\r
- case TAVOR_IF_COMP_STATUS_ERR_FLUSH:\r
- return VAPI_WR_FLUSH_ERR;\r
- case TAVOR_IF_COMP_STATUS_ERR_MWIN_BIND:\r
- return VAPI_MW_BIND_ERR;\r
- case TAVOR_IF_COMP_STATUS_ERR_BAD_RESP:\r
- return VAPI_BAD_RESP_ERR;\r
- case TAVOR_IF_COMP_STATUS_ERR_LCL_ACCS:\r
- return VAPI_LOC_ACCS_ERR;\r
- case TAVOR_IF_COMP_STATUS_ERR_RMT_INVAL_REQ:\r
- return VAPI_REM_INV_REQ_ERR;\r
- case TAVOR_IF_COMP_STATUS_ERR_RMT_ACCSS:\r
- return VAPI_REM_ACCESS_ERR;\r
- case TAVOR_IF_COMP_STATUS_ERR_RMT_OP:\r
- return VAPI_REM_OP_ERR;\r
- case TAVOR_IF_COMP_STATUS_ERR_TRANS_RETRY_EX:\r
- return VAPI_RETRY_EXC_ERR;\r
- case TAVOR_IF_COMP_STATUS_ERR_RNR_RETRY_EX:\r
- return VAPI_RNR_RETRY_EXC_ERR;\r
- case TAVOR_IF_COMP_STATUS_ERR_LCL_RDD_VIOL:\r
- return VAPI_LOC_RDD_VIOL_ERR;\r
- case TAVOR_IF_COMP_STATUS_ERR_RMT_INVAL_REQ_RD:\r
- return VAPI_REM_INV_RD_REQ_ERR;\r
- case TAVOR_IF_COMP_STATUS_ERR_RMT_ABORT:\r
- return VAPI_REM_ABORT_ERR;\r
- case TAVOR_IF_COMP_STATUS_ERR_INVAL_EEC_NUM:\r
- return VAPI_INV_EECN_ERR;\r
- case TAVOR_IF_COMP_STATUS_ERR_INVAL_EEC_STT:\r
- return VAPI_INV_EEC_STATE_ERR;\r
- default:\r
- MTL_ERROR1(MT_FLFMT("Invalid CQE error syndrome (0x%X)"),tstatus);\r
- return VAPI_COMP_GENERAL_ERR;\r
- }\r
-}\r
-\r
-inline static ib_wc_status_t\r
-decode_error_syndrome2(\r
- IN tavor_if_comp_status_t tstatus )\r
-{\r
- switch( tstatus )\r
- {\r
- case TAVOR_IF_COMP_STATUS_ERR_LCL_LEN: \r
- return IB_WCS_LOCAL_LEN_ERR;\r
-\r
- case TAVOR_IF_COMP_STATUS_ERR_LCL_QP_OP:\r
- return IB_WCS_LOCAL_OP_ERR;\r
-\r
- case TAVOR_IF_COMP_STATUS_ERR_LCL_PROT:\r
- return IB_WCS_LOCAL_PROTECTION_ERR;\r
-\r
- case TAVOR_IF_COMP_STATUS_ERR_FLUSH:\r
- return IB_WCS_WR_FLUSHED_ERR;\r
-\r
- case TAVOR_IF_COMP_STATUS_ERR_MWIN_BIND:\r
- return IB_WCS_MEM_WINDOW_BIND_ERR;\r
-\r
- case TAVOR_IF_COMP_STATUS_ERR_BAD_RESP:\r
- return IB_WCS_TIMEOUT_RETRY_ERR;\r
-\r
- case TAVOR_IF_COMP_STATUS_ERR_LCL_ACCS:\r
- return IB_WCS_LOCAL_PROTECTION_ERR;\r
-\r
- case TAVOR_IF_COMP_STATUS_ERR_RMT_INVAL_REQ:\r
- return IB_WCS_REM_INVALID_REQ_ERR;\r
-\r
- case TAVOR_IF_COMP_STATUS_ERR_RMT_ACCSS:\r
- return IB_WCS_REM_ACCESS_ERR;\r
-\r
- case TAVOR_IF_COMP_STATUS_ERR_RMT_OP:\r
- return IB_WCS_REM_OP_ERR;\r
-\r
- case TAVOR_IF_COMP_STATUS_ERR_TRANS_RETRY_EX:\r
- return IB_WCS_TIMEOUT_RETRY_ERR;\r
-\r
- case TAVOR_IF_COMP_STATUS_ERR_RNR_RETRY_EX:\r
- return IB_WCS_RNR_RETRY_ERR;\r
-\r
- case TAVOR_IF_COMP_STATUS_ERR_LCL_RDD_VIOL:\r
- return IB_WCS_LOCAL_PROTECTION_ERR;\r
-\r
- case TAVOR_IF_COMP_STATUS_ERR_RMT_ABORT:\r
- return IB_WCS_REM_OP_ERR;\r
-\r
- default:\r
- MTL_ERROR1(MT_FLFMT("Invalid CQE error syndrome (0x%X)"),tstatus);\r
- return IB_WCS_LOCAL_OP_ERR;\r
- }\r
-}\r
-\r
-inline static HH_ret_t decode_opcode(MT_bool send_q, u_int8_t cqe_opcode,\r
- VAPI_cqe_opcode_t *vapi_cqe_opcode_p, MT_bool *immediate_valid_p)\r
-{\r
- *immediate_valid_p= FALSE; /* Innocent until proven guilty... */\r
- if (send_q) { /* Send queue - use "nopcode" encoding */\r
- switch (cqe_opcode) {\r
- case TAVOR_IF_NOPCODE_RDMAW:\r
- *vapi_cqe_opcode_p= VAPI_CQE_SQ_RDMA_WRITE;\r
- return HH_OK;\r
- case TAVOR_IF_NOPCODE_RDMAW_IMM:\r
- *vapi_cqe_opcode_p= VAPI_CQE_SQ_RDMA_WRITE;\r
- *immediate_valid_p= TRUE;\r
- return HH_OK;\r
- case TAVOR_IF_NOPCODE_SEND:\r
- *vapi_cqe_opcode_p= VAPI_CQE_SQ_SEND_DATA;\r
- return HH_OK;\r
- case TAVOR_IF_NOPCODE_SEND_IMM:\r
- *vapi_cqe_opcode_p= VAPI_CQE_SQ_SEND_DATA;\r
- *immediate_valid_p= TRUE;\r
- return HH_OK;\r
- case TAVOR_IF_NOPCODE_RDMAR:\r
- *vapi_cqe_opcode_p= VAPI_CQE_SQ_RDMA_READ;\r
- return HH_OK;\r
- case TAVOR_IF_NOPCODE_ATOM_CMPSWP:\r
- *vapi_cqe_opcode_p= VAPI_CQE_SQ_COMP_SWAP;\r
- return HH_OK;\r
- case TAVOR_IF_NOPCODE_ATOM_FTCHADD:\r
- *vapi_cqe_opcode_p= VAPI_CQE_SQ_FETCH_ADD;\r
- return HH_OK;\r
- case TAVOR_IF_NOPCODE_BIND_MEMWIN:\r
- *vapi_cqe_opcode_p= VAPI_CQE_SQ_BIND_MRW;\r
- return HH_OK;\r
- default:\r
- return HH_EINVAL; /* Invalid opcode - shouldn't happen */\r
- }\r
- \r
- } else { /* receive queue - use IB encoding */\r
- /* bits 4:0 are of the opcode are common to all transport types */\r
- switch (cqe_opcode & MASK32(5)) { \r
- case IB_OP_SEND_LAST:\r
- case IB_OP_SEND_ONLY:\r
- *vapi_cqe_opcode_p= VAPI_CQE_RQ_SEND_DATA;\r
- return HH_OK;\r
- case IB_OP_SEND_IMM_LAST:\r
- case IB_OP_SEND_IMM_ONLY:\r
- *vapi_cqe_opcode_p= VAPI_CQE_RQ_SEND_DATA;\r
- *immediate_valid_p= TRUE;\r
- return HH_OK;\r
- case IB_OP_RDMAW_IMM_LAST:\r
- case IB_OP_RDMAW_IMM_ONLY:\r
- *vapi_cqe_opcode_p= VAPI_CQE_RQ_RDMA_WITH_IMM;\r
- *immediate_valid_p= TRUE;\r
- return HH_OK;\r
- default:\r
- return HH_EINVAL;\r
- }\r
- }\r
-}\r
-\r
-\r
-inline static HH_ret_t decode_opcode2(\r
- IN boolean_t send_q,\r
- IN uint8_t cqe_opcode,\r
- OUT ib_wc_type_t *p_wc_type,\r
- OUT boolean_t *p_imm_valid )\r
-{\r
- *p_imm_valid = FALSE; /* Innocent until proven guilty... */\r
- if( send_q )\r
- {\r
- /* Send queue - use "nopcode" encoding */\r
- switch( cqe_opcode )\r
- {\r
- case TAVOR_IF_NOPCODE_RDMAW_IMM:\r
- *p_imm_valid = TRUE;\r
- case TAVOR_IF_NOPCODE_RDMAW:\r
- *p_wc_type = IB_WC_RDMA_WRITE;\r
- return HH_OK;\r
-\r
- case TAVOR_IF_NOPCODE_SEND_IMM:\r
- *p_imm_valid = TRUE;\r
- case TAVOR_IF_NOPCODE_SEND:\r
- *p_wc_type = IB_WC_SEND;\r
- return HH_OK;\r
-\r
- case TAVOR_IF_NOPCODE_RDMAR:\r
- *p_wc_type = IB_WC_RDMA_READ;\r
- return HH_OK;\r
-\r
- case TAVOR_IF_NOPCODE_ATOM_CMPSWP:\r
- *p_wc_type = IB_WC_COMPARE_SWAP;\r
- return HH_OK;\r
-\r
- case TAVOR_IF_NOPCODE_ATOM_FTCHADD:\r
- *p_wc_type = IB_WC_FETCH_ADD;\r
- return HH_OK;\r
-\r
- case TAVOR_IF_NOPCODE_BIND_MEMWIN:\r
- *p_wc_type = IB_WC_MW_BIND;\r
- return HH_OK;\r
-\r
- default:\r
- return HH_EINVAL; /* Invalid opcode - shouldn't happen */\r
- }\r
- }\r
- else\r
- {\r
- /* receive queue - use IB encoding */\r
- /* bits 4:0 are of the opcode are common to all transport types */\r
- switch( cqe_opcode & MASK32(5) )\r
- { \r
- case IB_OP_SEND_IMM_LAST:\r
- case IB_OP_SEND_IMM_ONLY:\r
- *p_imm_valid = TRUE;\r
- case IB_OP_SEND_LAST:\r
- case IB_OP_SEND_ONLY:\r
- *p_wc_type = IB_WC_RECV;\r
- return HH_OK;\r
-\r
- case IB_OP_RDMAW_IMM_LAST:\r
- case IB_OP_RDMAW_IMM_ONLY:\r
- *p_wc_type = IB_WC_RECV_RDMA_WRITE;\r
- *p_imm_valid = TRUE;\r
- return HH_OK;\r
-\r
- default:\r
- return HH_EINVAL;\r
- }\r
- }\r
-}\r
-\r
-\r
-/* Extract CQE fields but for "status", "free_res_count" and "id" (already filled in poll4cqe) */\r
-/* This function is used only for successfull completions. */\r
-/* Given CQE is already in CPU endianess */\r
-inline static HH_ret_t extract_cqe(u_int32_t *cqe, VAPI_wc_desc_t *vapi_cqe_p, \r
- VAPI_special_qp_t qp_type, VAPI_ts_type_t qp_ts_type) \r
-{\r
- HH_ret_t rc;\r
- MT_bool send_cqe= MT_EXTRACT_ARRAY32(cqe,\r
- MT_BIT_OFFSET(tavorprm_completion_queue_entry_st,s),\r
- MT_BIT_SIZE(tavorprm_completion_queue_entry_st,s));\r
- \r
- rc= decode_opcode(\r
- send_cqe ,\r
- MT_EXTRACT_ARRAY32(cqe,\r
- MT_BIT_OFFSET(tavorprm_completion_queue_entry_st,opcode),\r
- MT_BIT_SIZE(tavorprm_completion_queue_entry_st,opcode) ),\r
- &(vapi_cqe_p->opcode),&(vapi_cqe_p->imm_data_valid));\r
- if (rc != HH_OK) {\r
- MTL_ERROR4(MT_FLFMT("Invalid %s Opcode=0x%X"),send_cqe ? "send" : "receive",\r
- MT_EXTRACT_ARRAY32(cqe,\r
- MT_BIT_OFFSET(tavorprm_completion_queue_entry_st,opcode),\r
- MT_BIT_SIZE(tavorprm_completion_queue_entry_st,opcode) ) );\r
- return rc;\r
- }\r
- if (send_cqe && \r
- ((vapi_cqe_p->opcode == VAPI_CQE_SQ_COMP_SWAP) || \r
- (vapi_cqe_p->opcode == VAPI_CQE_SQ_FETCH_ADD) \r
- ) \r
- ) { /* Atomic operations are always of length 8 */\r
- vapi_cqe_p->byte_len= 8;\r
- } else { /* Get bytes transfered from CQE (see FM issue #15659) */\r
- vapi_cqe_p->byte_len= cqe[MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,byte_cnt)>>2];\r
- }\r
- \r
- /* Get data from immediate_ethertype_pkey_indx_eecredits if valid */\r
- \r
- switch (qp_ts_type) {\r
- case VAPI_TS_UD:\r
- if (!send_cqe) { /* see IB-spec. 11.4.2.1: Output Modifiers */\r
- vapi_cqe_p->remote_node_addr.type= VAPI_RNA_UD;\r
- vapi_cqe_p->remote_node_addr.qp_ety.qp= \r
- cqe[MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,rqpn)>>2] & MASK32(24);\r
- vapi_cqe_p->remote_node_addr.ee_dlid.dst_path_bits= MT_EXTRACT_ARRAY32(cqe,\r
- MT_BIT_OFFSET(tavorprm_completion_queue_entry_st,ml_path),\r
- MT_BIT_SIZE(tavorprm_completion_queue_entry_st,ml_path) );\r
- vapi_cqe_p->remote_node_addr.slid= MT_EXTRACT_ARRAY32(cqe,\r
- MT_BIT_OFFSET(tavorprm_completion_queue_entry_st,rlid),MT_BIT_SIZE(tavorprm_completion_queue_entry_st,rlid));\r
- vapi_cqe_p->remote_node_addr.sl= MT_EXTRACT_ARRAY32(cqe,\r
- MT_BIT_OFFSET(tavorprm_completion_queue_entry_st,sl),MT_BIT_SIZE(tavorprm_completion_queue_entry_st,sl));\r
- vapi_cqe_p->grh_flag= MT_EXTRACT_ARRAY32(cqe,\r
- MT_BIT_OFFSET(tavorprm_completion_queue_entry_st,g),MT_BIT_SIZE(tavorprm_completion_queue_entry_st,g));\r
- }\r
- break;\r
- case VAPI_TS_RD:\r
- if (!send_cqe) { /* see IB-spec. 11.4.2.1: Output Modifiers */\r
- vapi_cqe_p->remote_node_addr.type= VAPI_RNA_RD;\r
- vapi_cqe_p->remote_node_addr.qp_ety.qp= \r
- cqe[MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,rqpn)>>2] & MASK32(24);\r
- vapi_cqe_p->remote_node_addr.ee_dlid.loc_eecn= \r
- cqe[MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,my_ee)>>2] & MASK32(24);\r
- }\r
- break;\r
- default:\r
- break;\r
- }\r
- \r
-\r
- switch (qp_type) {\r
- case VAPI_REGULAR_QP:\r
- /*if (vapi_cqe_p->imm_data_valid) */ \r
- /* Copy immediate_ethertype_pkey_indx_eecredits even if no immediate data, \r
- * in order to get eecredits (for SQ) */\r
- vapi_cqe_p->imm_data = \r
- cqe[MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,immediate_ethertype_pkey_indx_eecredits)>>2];\r
- break;\r
- case VAPI_RAW_ETY_QP:\r
- vapi_cqe_p->remote_node_addr.type= VAPI_RNA_RAW_ETY;\r
-/*** warning C4242: '=' : conversion from 'u_int32_t' to 'VAPI_ethertype_t', possible loss of data ***/\r
- vapi_cqe_p->remote_node_addr.qp_ety.ety= (VAPI_ethertype_t)\r
- cqe[MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,immediate_ethertype_pkey_indx_eecredits)>>2];\r
- break;\r
- \r
- case VAPI_GSI_QP:\r
- vapi_cqe_p->pkey_ix= \r
- cqe[MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,immediate_ethertype_pkey_indx_eecredits)>>2]\r
- >> 16; /* Pkey index is on bits 31:16 */\r
- vapi_cqe_p->imm_data_valid= FALSE; \r
- /* QP1's RQ requests complete as "send w/immediate", even though it is just a send */\r
- break;\r
- \r
- default:\r
- break;\r
-\r
- }\r
-\r
- return HH_OK;\r
-}\r
-\r
-#define CQE_RLID_DWORD_OFFSET MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,rlid)>>2\r
-#define CQE_MY_EE_DWORD_OFFSET MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,my_ee)>>2\r
-#define CQE_RQPN_DWORD_OFFSET MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,rqpn)>>2\r
-#define CQE_MY_EE_BIT_MASK MASK32(24)\r
-#define CQE_RQPN_BIT_MASK MASK32(24)\r
-\r
-#define CQE_S_DWORD_OFFSET MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,s)>>2\r
-#define CQE_S_BIT_MASK MASK32(MT_BIT_SIZE(tavorprm_completion_queue_entry_st,s))\r
-#define CQE_S_SHIFT (MT_BIT_OFFSET(tavorprm_completion_queue_entry_st,s) & MASK32(5))\r
-\r
-/* this is optimized version of extract_cqe and passing opcode for poll4cqe */\r
-inline static HH_ret_t extract_cqe_new(u_int32_t *cqe, VAPI_wc_desc_t *vapi_cqe_p, \r
- VAPI_special_qp_t qp_type, VAPI_ts_type_t qp_ts_type,u_int32_t opcode) \r
-{\r
- //HH_ret_t rc;\r
- \r
- MT_bool send_cqe= (cqe[CQE_S_DWORD_OFFSET]>>CQE_S_SHIFT) & CQE_S_BIT_MASK;\r
- \r
- if (MOSAL_EXPECT_FALSE(decode_opcode(send_cqe, \r
- (u_int8_t)opcode, \r
- &(vapi_cqe_p->opcode),\r
- &(vapi_cqe_p->imm_data_valid)) \r
- != HH_OK))\r
- \r
- {\r
- MTL_ERROR4(MT_FLFMT("Invalid %s Opcode=0x%X"),send_cqe ? "send" : "receive",\r
- MT_EXTRACT_ARRAY32(cqe,\r
- MT_BIT_OFFSET(tavorprm_completion_queue_entry_st,opcode),\r
- MT_BIT_SIZE(tavorprm_completion_queue_entry_st,opcode) ) );\r
- return HH_EINVAL;\r
- }\r
- \r
- /* short circuit this case */ \r
- if (MOSAL_EXPECT_FALSE(qp_ts_type == VAPI_TS_RC)) {\r
- return HH_OK; \r
- }\r
- \r
-#define CQE_ML_PATH_BIT_MASK MASK32(MT_BIT_SIZE(tavorprm_completion_queue_entry_st,ml_path))\r
-#define CQE_ML_PATH_DWORD_OFFSET MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,ml_path)>>2\r
-#define CQE_ML_PATH_SHIFT (MT_BIT_OFFSET(tavorprm_completion_queue_entry_st,ml_path) & MASK32(5))\r
-\r
-#define CQE_RLID_BIT_MASK MASK32(MT_BIT_SIZE(tavorprm_completion_queue_entry_st,rlid))\r
-#define CQE_RLID_SHIFT (MT_BIT_OFFSET(tavorprm_completion_queue_entry_st,rlid) & MASK32(5))\r
-#define CQE_SL_BIT_MASK MASK32(MT_BIT_SIZE(tavorprm_completion_queue_entry_st,sl))\r
-#define CQE_SL_DWORD_OFFSET MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,sl)>>2\r
-#define CQE_SL_SHIFT (MT_BIT_OFFSET(tavorprm_completion_queue_entry_st,sl) & MASK32(5))\r
-#define CQE_G_BIT_MASK MASK32(MT_BIT_SIZE(tavorprm_completion_queue_entry_st,g))\r
-#define CQE_G_DWORD_OFFSET MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,g)>>2\r
-#define CQE_G_SHIFT (MT_BIT_OFFSET(tavorprm_completion_queue_entry_st,g) & MASK32(5))\r
- \r
- \r
- /* see IB-spec. 11.4.2.1: Output Modifiers */\r
- if (!send_cqe) {\r
- if (qp_ts_type == VAPI_TS_UD) {\r
- \r
- vapi_cqe_p->remote_node_addr.type= VAPI_RNA_UD;\r
- \r
- vapi_cqe_p->remote_node_addr.qp_ety.qp= \r
- cqe[CQE_RQPN_DWORD_OFFSET] & CQE_RQPN_BIT_MASK;\r
-\r
- vapi_cqe_p->remote_node_addr.ee_dlid.dst_path_bits = \r
- (cqe[CQE_ML_PATH_DWORD_OFFSET]>>CQE_ML_PATH_SHIFT)& CQE_ML_PATH_BIT_MASK; \r
- vapi_cqe_p->remote_node_addr.slid=\r
- (cqe[CQE_RLID_DWORD_OFFSET]>>CQE_RLID_SHIFT)& CQE_RLID_BIT_MASK;\r
- vapi_cqe_p->remote_node_addr.sl= \r
- (cqe[CQE_SL_DWORD_OFFSET]>>CQE_SL_SHIFT)& CQE_SL_BIT_MASK;\r
- vapi_cqe_p->grh_flag= (cqe[CQE_G_DWORD_OFFSET]>>CQE_G_SHIFT)& CQE_G_BIT_MASK;\r
- }\r
- else\r
- {\r
- if (qp_ts_type == VAPI_TS_RD) {\r
- vapi_cqe_p->remote_node_addr.type = VAPI_RNA_RD;\r
- \r
- /*RQPN field not converted to be yet */\r
- vapi_cqe_p->remote_node_addr.qp_ety.qp= \r
- cqe[CQE_RQPN_DWORD_OFFSET] & CQE_RQPN_BIT_MASK;\r
- vapi_cqe_p->remote_node_addr.ee_dlid.loc_eecn= \r
- cqe[CQE_MY_EE_DWORD_OFFSET] & CQE_MY_EE_BIT_MASK;\r
- }\r
-\r
- }\r
- }\r
-\r
- switch (qp_type) {\r
- case VAPI_RAW_ETY_QP: \r
- vapi_cqe_p->remote_node_addr.type = VAPI_RNA_RAW_ETY;\r
- vapi_cqe_p->remote_node_addr.qp_ety.ety = (VAPI_ethertype_t)vapi_cqe_p->imm_data;\r
- break;\r
- \r
- case VAPI_GSI_QP:\r
- vapi_cqe_p->pkey_ix= vapi_cqe_p->imm_data >> 16;/* Pkey index is on bits 31:16 */\r
- vapi_cqe_p->imm_data_valid= FALSE; \r
- /* QP1's RQ requests complete as "send w/immediate", even though it is just a send */\r
-\r
- break;\r
- default:\r
- break;\r
-\r
- }\r
- \r
- return HH_OK;\r
-}\r
-\r
-/* Given CQ must be locked when calling this function */\r
-static inline void sync_consumer_index(THHUL_cq_t *cq_p, const char* caller)\r
-{\r
- HH_ret_t rc;\r
-\r
- if (cq_p->pending_cq_dbell > 0) {\r
- MTL_DEBUG4(MT_FLFMT("%s: Ringing CQ DB (CQN=0x%X) to increment CI by %u"),caller,\r
- cq_p->cq_num, cq_p->pending_cq_dbell);\r
- rc= THH_uar_cq_cmd(cq_p->uar,TAVOR_IF_UAR_CQ_INC_CI,cq_p->cq_num,cq_p->pending_cq_dbell-1);\r
- if (rc != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed THH_uar_cq_cmd (%s)"), caller, HH_strerror_sym(rc));\r
- /* Even though, this is not a show stopper. Let's continue until we get CQ error. */\r
- } else {\r
- cq_p->pending_cq_dbell= 0;\r
- }\r
- }\r
-}\r
-\r
-/**********************************************************************************************\r
- * Private functions declarations\r
- **********************************************************************************************/\r
-static HH_ret_t cqe_buf_alloc(THHUL_cqe_buf_t *cqe_buf, VAPI_cqe_num_t num_o_cqes);\r
-\r
-static void cqe_buf_free(THHUL_cqe_buf_t *cqe_buf);\r
-\r
-static const char* cq_state_str(THHUL_cq_state_t cq_state)\r
-{\r
- switch (cq_state) {\r
- case THHUL_CQ_PREP: return "THHUL_CQ_PREP";\r
- case THHUL_CQ_IDLE: return "THHUL_CQ_IDLE";\r
- case THHUL_CQ_RESIZE_PREP: return "THHUL_CQ_RESIZE_PREP";\r
- default: return "(unknown state)";\r
- }\r
-}\r
-\r
-static u_int32_t cqe_buf_cleanup(THHUL_cqe_buf_t *cqe_buf,IB_wqpn_t qp,\r
- THHUL_srqm_t srqm, HHUL_srq_hndl_t srq,\r
- u_int32_t *cur_producer_index_p);\r
-\r
-static void cqe_buf_cpy2resized(\r
- THHUL_cqe_buf_t *cur_buf, \r
- THHUL_cqe_buf_t *resized_buf, \r
- MT_bool compute_new_pi); /* New resize-CQ flow */\r
-\r
-static VAPI_cqe_num_t count_cqes(/*IN*/ THHUL_cq_t *cq_p, \r
- /*IN*/ VAPI_cqe_num_t cqe_num_limit,\r
- /*OUT*/ VAPI_cqe_num_t *hw_cqe_cnt_p);\r
-\r
-\r
-\r
-/**********************************************************************************************\r
- * Public API Functions (defined in thhul_hob.h)\r
- **********************************************************************************************/\r
-\r
-\r
-HH_ret_t THHUL_cqm_create( \r
- /*IN*/ THHUL_hob_t hob, \r
- /*OUT*/ THHUL_cqm_t *cqm_p \r
-) \r
-{ \r
- THHUL_cqm_t new_cqm;\r
-\r
- new_cqm= (THHUL_cqm_t)MALLOC(sizeof(struct THHUL_cqm_st));\r
- if (new_cqm == NULL) {\r
- MTL_ERROR1("THHUL_cqm_create: Failed to allocate memory for a new CQM.\n");\r
- return HH_EAGAIN;\r
- }\r
- new_cqm->cq_list= NULL;\r
- MOSAL_mutex_init(&(new_cqm->cqm_lock));\r
-\r
- *cqm_p= new_cqm;\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THHUL_cqm_destroy (\r
- /*IN*/ THHUL_cqm_t cqm\r
-) \r
-{ \r
- THHUL_cq_t *thhul_cq;\r
- \r
- while (cqm->cq_list) { \r
- thhul_cq = cqm->cq_list;\r
- cqm->cq_list= thhul_cq->next;\r
- cqe_buf_free(&(thhul_cq->cur_buf));\r
- FREE(thhul_cq);\r
- }\r
-\r
- MOSAL_mutex_free(&(cqm->cqm_lock));\r
- FREE(cqm);\r
- return HH_OK; \r
-}\r
-\r
-\r
-HH_ret_t THHUL_cqm_create_cq_prep(\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ VAPI_cqe_num_t num_o_cqes, \r
- /*OUT*/ HHUL_cq_hndl_t *hhul_cq_p, \r
- /*OUT*/ VAPI_cqe_num_t *num_o_cqes_p, \r
- /*OUT*/ void/*THH_cq_ul_resources_t*/ *cq_ul_resources_p \r
-) \r
-{ \r
- THHUL_cqm_t cqm;\r
- THHUL_cq_t *new_cq;\r
- THH_cq_ul_resources_t *ul_res_p= (THH_cq_ul_resources_t*)cq_ul_resources_p;\r
- HH_ret_t rc;\r
- THH_hca_ul_resources_t hca_ul_res;\r
-\r
- rc= THHUL_hob_get_cqm(hca,&cqm);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1("THHUL_cqm_create_cq_prep: Invalid HCA handle.\n");\r
- return HH_EINVAL;\r
- }\r
-\r
- rc= THHUL_hob_get_hca_ul_res(hca,&hca_ul_res);\r
- if (rc != HH_OK) {\r
- MTL_ERROR2("THHUL_cqm_create_cq_prep: Failed THHUL_hob_get_hca_ul_res (err=%d).\n",rc);\r
- return rc;\r
- }\r
-\r
- if (num_o_cqes > hca_ul_res.max_num_ent_cq) {\r
- MTL_ERROR2("THHUL_cqm_create_cq_prep: cq_num_of_entries requested exceeds hca cap\n");\r
- return HH_E2BIG_CQE_NUM;\r
- }\r
-\r
- new_cq= (THHUL_cq_t*)MALLOC(sizeof(THHUL_cq_t));\r
- if (new_cq == NULL) {\r
- MTL_ERROR1("THHUL_cqm_create_cq_prep: Failed to allocate THHUL_cq_t.\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- rc= cqe_buf_alloc(&new_cq->cur_buf,num_o_cqes);\r
- if (rc != HH_OK) goto failed_cqe_buf;\r
- new_cq->cq_state= THHUL_CQ_PREP; \r
- new_cq->cur_spare_cqes= new_cq->cur_buf.spare_cqes;\r
- new_cq->pending_cq_dbell= 0;\r
- \r
- new_cq->cq_resize_fixed= (hca_ul_res.version.fw_ver_major >= 3);\r
-\r
- rc= THHUL_hob_get_uar(hca,&(new_cq->uar));\r
- if (rc != HH_OK) {\r
- MTL_ERROR1("THHUL_cqm_create_cq_prep: Failed getting THHUL_hob's UAR (err=%d).\n",rc);\r
- goto failed_uar;\r
- }\r
- rc= THH_uar_get_index(new_cq->uar,&(ul_res_p->uar_index)); \r
- if (rc != HH_OK) {\r
- MTL_ERROR1("THHUL_cqm_create_cq_prep: Failed getting UAR index.\n");\r
- goto failed_uar;\r
- }\r
-\r
- rc= THHUL_hob_get_qpm(hca,&(new_cq->qpm));\r
- if (rc != HH_OK) {\r
- MTL_ERROR1("THHUL_cqm_create_cq_prep: Failed getting THHUL_hob's QPM (err=%d).\n",rc);\r
- goto failed_qpm;\r
- }\r
-\r
- new_cq->cq_num= INVALID_CQ_NUM;\r
- MOSAL_spinlock_init(&(new_cq->cq_lock));\r
- /* Add CQ to CQs list */\r
- if (MOSAL_mutex_acq(&(cqm->cqm_lock),TRUE) != 0) {rc= HH_EINTR; goto failed_mutex;}\r
- new_cq->next= cqm->cq_list; /* Add before first (if any) */\r
- cqm->cq_list= new_cq;\r
- MOSAL_mutex_rel(&(cqm->cqm_lock));\r
-\r
- /* Output modifiers */\r
- *hhul_cq_p= (HHUL_cq_hndl_t)new_cq;\r
- /* One CQE is always reserved (for CQ-full indication) */\r
- *num_o_cqes_p= (1U << new_cq->cur_buf.log2_num_o_cqes) - 1 - new_cq->cur_buf.spare_cqes; \r
- ul_res_p->cqe_buf= new_cq->cur_buf.cqe_buf_base; /* Registration is required only from here */\r
- ul_res_p->cqe_buf_sz= (1U << new_cq->cur_buf.log2_num_o_cqes) * CQE_SZ ; \r
- /* ul_res_p->uar_index ==> already set above */\r
- return HH_OK;\r
-\r
- failed_mutex:\r
- failed_qpm:\r
- failed_uar:\r
- cqe_buf_free(&(new_cq->cur_buf));\r
- failed_cqe_buf:\r
- FREE(new_cq);\r
- return rc; \r
-}\r
-\r
-\r
-HH_ret_t THHUL_cqm_create_cq_done(\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_cq_hndl_t hhul_cq, \r
- /*IN*/ HH_cq_hndl_t hh_cq, \r
- /*IN*/ void/*THH_cq_ul_resources_t*/ *cq_ul_resources_p \r
-) \r
-{ \r
- THHUL_cq_t *cq= (THHUL_cq_t*)hhul_cq;\r
- \r
- if (cq == NULL) {\r
- MTL_ERROR1("THHUL_cqm_create_cq_done: NULL CQ handle.\n");\r
- return HH_EINVAL;\r
- }\r
- if (hh_cq > MAX_CQ_NUM) {\r
- MTL_ERROR1("THHUL_cqm_create_cq_done: Invalid CQ number (0x%X).\n",hh_cq);\r
- return HH_EINVAL;\r
- }\r
- \r
- MOSAL_spinlock_dpc_lock(&(cq->cq_lock));\r
- if (cq->cq_state != THHUL_CQ_PREP) {\r
- MOSAL_spinlock_unlock(&(cq->cq_lock));\r
- MTL_ERROR1("THHUL_cqm_create_cq_done: Library inconsistancy ! Given CQ is not in THHUL_CQ_PREP state.\n");\r
- return HH_ERR;\r
- }\r
- cq->cq_state= THHUL_CQ_IDLE; \r
- cq->cq_num= hh_cq;\r
- MOSAL_spinlock_unlock(&(cq->cq_lock));\r
- \r
- return HH_OK; \r
-}\r
-\r
-\r
-HH_ret_t THHUL_cqm_destroy_cq_done(\r
- /*IN*/ HHUL_hca_hndl_t hca_hndl, \r
- /*IN*/ HHUL_cq_hndl_t cq \r
-) \r
-{ \r
- THHUL_cq_t *thhul_cq= (THHUL_cq_t*)cq;\r
- THHUL_cq_t *prev_cq,*cur_cq;\r
- THHUL_cqm_t cqm;\r
- HH_ret_t rc;\r
-\r
- rc= THHUL_hob_get_cqm(hca_hndl,&cqm);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1("THHUL_cqm_destroy_cq_done: Invalid HCA handle.\n");\r
- return HH_EINVAL;\r
- }\r
- if (cq == NULL) {\r
- MTL_ERROR1("THHUL_cqm_destroy_cq_done: NULL CQ handle.\n");\r
- return HH_EINVAL;\r
- }\r
- \r
- if (thhul_cq->cq_state == THHUL_CQ_RESIZE_PREP) {\r
- /* Someone invoked VAPI_destroy_cq while invoking VAPI_resize_cq */\r
- MTL_ERROR2(MT_FLFMT("%s: Invoked while in THHUL_CQ_RESIZE_PREP (cqn=0x%X) !"),__func__,\r
- thhul_cq->cq_num);\r
- return HH_EBUSY;\r
- }\r
- /* Remove from CQs list */\r
- MOSAL_mutex_acq_ui(&(cqm->cqm_lock));\r
- for (cur_cq= cqm->cq_list, prev_cq= NULL; cur_cq != NULL; \r
- prev_cq= cur_cq, cur_cq= cur_cq->next) {\r
- if (cur_cq == cq) break;\r
- }\r
- if (cur_cq == NULL) { /* CQ not found */\r
- MOSAL_mutex_rel(&(cqm->cqm_lock));\r
- MTL_ERROR1("THHUL_cqm_destroy_cq_done: invalid CQ handle (not found).\n");\r
- return HH_EINVAL;\r
- }\r
- if (prev_cq == NULL) { /* First in list */\r
- cqm->cq_list= thhul_cq->next; /* Make next be the first */\r
- } else { \r
- prev_cq->next= thhul_cq->next; /* Link previous to next */\r
- }\r
- MOSAL_mutex_rel(&(cqm->cqm_lock));\r
- \r
- /* Cleanup CQ resources */\r
- cqe_buf_free(&(thhul_cq->cur_buf));\r
- FREE(thhul_cq);\r
- return HH_OK;\r
-}\r
-\r
-\r
-ib_api_status_t THHUL_cqm_resize_cq_prep(\r
- /*IN*/ HHUL_hca_hndl_t hca_hndl, \r
- /*IN*/ HHUL_cq_hndl_t cq, \r
- /*IN*/ VAPI_cqe_num_t num_o_cqes, \r
- /*OUT*/ VAPI_cqe_num_t *num_o_cqes_p, \r
- /*OUT*/ void/*THH_cq_ul_resources_t*/ *cq_ul_resources_p \r
-) \r
-{ \r
- THHUL_cq_t *cq_p= (THHUL_cq_t*)cq;\r
- THH_cq_ul_resources_t *ul_res_p= (THH_cq_ul_resources_t*)cq_ul_resources_p;\r
- HH_ret_t rc;\r
- THH_hca_ul_resources_t hca_ul_res;\r
- THHUL_cqe_buf_t new_buf;\r
-\r
- if (cq_p == NULL) {\r
- MTL_ERROR1("%s: NULL CQ handle.\n",__func__);\r
- return IB_INVALID_CQ_HANDLE;\r
- }\r
- \r
- rc= THHUL_hob_get_hca_ul_res(hca_hndl,&hca_ul_res);\r
- if (rc != HH_OK) {\r
- MTL_ERROR2("THHUL_cqm_create_cq_prep: Failed THHUL_hob_get_hca_ul_res (err=%d).\n",rc);\r
- return IB_ERROR;\r
- }\r
-\r
- if (num_o_cqes > hca_ul_res.max_num_ent_cq) {\r
- MTL_ERROR2("THHUL_cqm_create_cq_prep: cq_num_of_entries requested exceeds hca cap\n");\r
- return IB_INVALID_CQ_SIZE;\r
- }\r
-\r
- rc= cqe_buf_alloc(&new_buf,num_o_cqes);\r
- if (rc != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Allocating buffer for resized CQ 0x%X has failed"),__func__,\r
- cq_p->cq_num);\r
- return IB_INSUFFICIENT_MEMORY;\r
- }\r
- \r
- MOSAL_spinlock_dpc_lock(&(cq_p->cq_lock));\r
- if (cq_p->cq_state != THHUL_CQ_IDLE) {\r
- MTL_ERROR1("%s: CQ is not in IDLE state (current state=%d=%s)\n", __func__,\r
- cq_p->cq_state,cq_state_str(cq_p->cq_state));\r
- MOSAL_spinlock_unlock(&(cq_p->cq_lock));\r
- cqe_buf_free(&new_buf);\r
- return IB_INVALID_STATE;\r
- }\r
- memcpy(&cq_p->resized_buf, &new_buf, sizeof(THHUL_cqe_buf_t));\r
-\r
- /* Update CQ to real number of outstanding CQEs */\r
- /* (avoid failure in case of reduction in CQ size which matches real num. of outstanding CQEs)*/\r
- sync_consumer_index(cq_p, __func__);\r
- /* start working with the limitations of the new CQEs buffer \r
- * (after resizing we don't want to be in "overdraft") */\r
- if (cq_p->cur_buf.spare_cqes > cq_p->resized_buf.spare_cqes) { \r
- cq_p->cur_spare_cqes = cq_p->resized_buf.spare_cqes;\r
- }\r
- \r
- cq_p->cq_state= THHUL_CQ_RESIZE_PREP; \r
- MOSAL_spinlock_unlock(&(cq_p->cq_lock));\r
- \r
- memset(ul_res_p,0,sizeof(THH_cq_ul_resources_t));\r
- ul_res_p->cqe_buf= cq_p->resized_buf.cqe_buf_base; /* Registration is required only from here */\r
- ul_res_p->cqe_buf_sz= (1U<<cq_p->resized_buf.log2_num_o_cqes) * CQE_SZ ; \r
- *num_o_cqes_p= (1U<<cq_p->resized_buf.log2_num_o_cqes) - 1 - cq_p->resized_buf.spare_cqes;\r
-\r
- return IB_SUCCESS;\r
-}\r
-\r
-\r
-HH_ret_t THHUL_cqm_resize_cq_done( \r
- /*IN*/ HHUL_hca_hndl_t hca_hndl, \r
- /*IN*/ HHUL_cq_hndl_t cq, \r
- /*IN*/ void/*THH_cq_ul_resources_t*/ *cq_ul_resources_p \r
-) \r
-{ \r
- THHUL_cq_t *cq_p= (THHUL_cq_t*)cq;\r
- THH_cq_ul_resources_t *ul_res_p= (THH_cq_ul_resources_t*)cq_ul_resources_p;\r
- THHUL_cqe_buf_t rm_buf;\r
- \r
- if (cq_p == NULL) {\r
- MTL_ERROR1("THHUL_cqm_resize_cq_done: NULL CQ handle.\n");\r
- return HH_EINVAL;\r
- }\r
- \r
- MOSAL_spinlock_dpc_lock(&(cq_p->cq_lock));\r
- \r
- if (cq_p->cq_state == THHUL_CQ_RESIZE_PREP) { \r
- /* Still polling in old buffer */\r
- if (!ul_res_p) { /* HH_resize_cq failed - clean up allocated buffer */\r
- /* save buffer info to perform cleanup outside of spinlock */\r
- memcpy(&rm_buf,&(cq_p->resized_buf),sizeof(THHUL_cqe_buf_t));\r
- /* restore original "spare_cqes" of cur_buf (may have been reduced in resize_cq_prep) */\r
- cq_p->cur_spare_cqes= cq_p->cur_buf.spare_cqes;\r
-\r
- } else { /* Activate resized buffer */\r
- cq_p->resized_buf.consumer_index= ul_res_p->new_producer_index; /* for old resize flow */\r
- /* copy CQEs from old buffer to resized buffer */\r
- cqe_buf_cpy2resized(&(cq_p->cur_buf),&(cq_p->resized_buf), cq_p->cq_resize_fixed); \r
- memcpy(&rm_buf,&(cq_p->cur_buf),sizeof(THHUL_cqe_buf_t)); /* save old buffer */\r
- /* Make resize buffer current. New consumer index is already updated. */\r
- memcpy(&(cq_p->cur_buf),&(cq_p->resized_buf),sizeof(THHUL_cqe_buf_t));\r
- cq_p->cur_spare_cqes= cq_p->cur_buf.spare_cqes; /* work with the spare CQEs of new buffer */\r
- }\r
- \r
- } else if (cq_p->cq_state == THHUL_CQ_RESIZE_DONE) {\r
- /* Transition to resized buffer already done. No CQEs to copy. Just free old buffer */\r
- /* (transition done in cq_transition_to_resized_buf) */\r
- if (!ul_res_p) { \r
- /* Sanity check - RESIZE_CQ command is not suppose to fail if new buffer was activated */\r
- MTL_ERROR1(MT_FLFMT("%s: Inconsistancy ! Got failure in RESIZE_CQ"\r
- " after finding CQEs in the new buffer (cqn=0x%X)"),\r
- __func__, cq_p->cq_num);\r
- }\r
- memcpy(&rm_buf,&(cq_p->resized_buf),sizeof(THHUL_cqe_buf_t)); /* save old buffer */\r
- \r
- } else { /* Invalid CQ state for this function call */\r
- MOSAL_spinlock_unlock(&(cq_p->cq_lock));\r
- MTL_ERROR1("THHUL_cqm_resize_cq_done: Given CQ is not in THHUL_CQ_RESIZE_PREP/DONE state.\n");\r
- return HH_ERR;\r
- }\r
- \r
- /* Good flow finalization */\r
- cq_p->cq_state= THHUL_CQ_IDLE; /* new resize may be initiated */\r
- MOSAL_spinlock_unlock(&(cq_p->cq_lock));\r
- cqe_buf_free(&rm_buf); /* Free old CQEs buffer (must be done outside spinlock section) */\r
- return HH_OK; \r
-}\r
-\r
-\r
-HH_ret_t THHUL_cqm_cq_cleanup( \r
- /*IN*/ HHUL_cq_hndl_t cq, \r
- /*IN*/ IB_wqpn_t qp,\r
- /*IN*/ THHUL_srqm_t srqm,\r
- /*IN*/ HHUL_srq_hndl_t srq\r
-) \r
-{ \r
- THHUL_cq_t *thhul_cq_p= (THHUL_cq_t*)cq;\r
- u_int32_t removed_cqes= 0;\r
- u_int32_t cur_buf_pi; /* Current buffer producer index */\r
- HH_ret_t rc= HH_OK;\r
- \r
- MTL_DEBUG2("THHUL_cqm_cq_cleanup(cq_p=%p,qp=%d) {\n",thhul_cq_p,qp);\r
- if (thhul_cq_p == NULL) {\r
- MTL_ERROR1("THHUL_cqm_cq_cleanup: NULL CQ handle.\n");\r
- return HH_EINVAL;\r
- }\r
- \r
- MOSAL_spinlock_dpc_lock(&(thhul_cq_p->cq_lock));\r
-\r
- removed_cqes+= cqe_buf_cleanup(&(thhul_cq_p->cur_buf), qp, srqm, srq, &cur_buf_pi );\r
- /* In case we are resizing the CQ, new buffer may already include CQEs of that QP */\r
- if (thhul_cq_p->cq_state == THHUL_CQ_RESIZE_PREP) {\r
- /* Update resized's CI based on new resize-cq flow (FM issue #16969). \r
- * (This flow will fail for old flow anyway - so no need to distinguish between cases) \r
- */\r
- thhul_cq_p->resized_buf.consumer_index= \r
- cur_buf_pi & MASK32(thhul_cq_p->resized_buf.log2_num_o_cqes);\r
- removed_cqes+= cqe_buf_cleanup(&(thhul_cq_p->resized_buf), qp, srqm, srq, &cur_buf_pi);\r
- }\r
- \r
-#ifndef NO_CQ_CI_DBELL\r
- /* Ring CQ-cmd doorbell to update consumer index (Removed CQEs + pending CQ doorbells) */\r
- if (removed_cqes) {\r
- rc= THH_uar_cq_cmd(thhul_cq_p->uar,TAVOR_IF_UAR_CQ_INC_CI,thhul_cq_p->cq_num,\r
- thhul_cq_p->pending_cq_dbell + removed_cqes - 1);\r
- if (rc != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed THH_uar_cq_cmd (%s)"), __func__, HH_strerror_sym(rc));\r
- /* Even though, this is not a show stopper. Let's continue until we get CQ error. */\r
-/*** warning C4242: '+=' : conversion from 'u_int32_t' to 'u_int16_t', possible loss of data ***/\r
- thhul_cq_p->pending_cq_dbell += (u_int16_t)removed_cqes; /* Maybe we will get luckier next time */\r
- } else {\r
- thhul_cq_p->pending_cq_dbell= 0;\r
- }\r
- }\r
-#endif\r
- \r
- MOSAL_spinlock_unlock(&(thhul_cq_p->cq_lock));\r
-\r
- return rc; \r
-}\r
-\r
-#ifdef THHUL_CQM_DEBUG_WQE_REUSE\r
-void THHUL_cqm_dump_cq(\r
- /*IN*/ HHUL_cq_hndl_t cq \r
-)\r
-{\r
- THHUL_cq_t *thhul_cq_p= (THHUL_cq_t*)cq;\r
- volatile u_int32_t *cur_cqe;\r
- int cqe_index;\r
- static HHUL_cq_hndl_t last_cq= NULL;\r
- static u_int32_t last_consumer_index= 0xFFFFFFFF;\r
-\r
- /* Do not dump again for the same CQ/consumer-index */\r
- if ((cq == last_cq) && (last_consumer_index == thhul_cq_p->cur_buf.consumer_index)) return;\r
- last_cq= cq; last_consumer_index= thhul_cq_p->cur_buf.consumer_index;\r
-\r
- MTL_ERROR4("THHUL_cqm_dump_cq: cq=%d consumer_index=%d\n",\r
- thhul_cq_p->cq_num,last_consumer_index);\r
- for (cqe_index= 0; cqe_index < (1 << thhul_cq_p->cur_buf.log2_num_o_cqes); cqe_index++) {\r
- cur_cqe= (volatile u_int32_t *)\r
- (thhul_cq_p->cur_buf.cqe_buf_base + (cqe_index << LOG2_CQE_SZ)); \r
- DUMP_CQE(thhul_cq_p->cq_num,cqe_index,cur_cqe);\r
- }\r
-\r
-}\r
-#endif\r
-\r
-/* Check if can transition to new (resized) CQEs buffer and make cur_buf<--resized_buf\r
- * - Valid for fixed resize cq FW version\r
- * - Return TRUE if transition and cur_cqe is updated to new location in resized buf.\r
- * - Must be invoked with CQ lock locked and only when CQE at current CI is invalid\r
- */\r
-static MT_bool cq_transition_to_resized_buf(\r
- THHUL_cq_t *cq_p,\r
- volatile u_int32_t **cur_cqe_p\r
-)\r
-{\r
- THHUL_cqe_buf_t rm_buf;\r
- \r
- if ((cq_p->cq_state == THHUL_CQ_RESIZE_PREP) &&\r
- (cq_p->cq_resize_fixed)) { /* Peek into resized buffer */\r
- cq_p->resized_buf.consumer_index= /* Expected new CI */\r
- cq_p->cur_buf.consumer_index & MASK32(cq_p->resized_buf.log2_num_o_cqes);\r
- *cur_cqe_p= (volatile u_int32_t *)\r
- (cq_p->resized_buf.cqe_buf_base + \r
- (cq_p->resized_buf.consumer_index << LOG2_CQE_SZ)); \r
- if (!is_cqe_hw_own(*cur_cqe_p)) { /* Found CQE in new (resized) buffer */\r
- MTL_DEBUG4(MT_FLFMT("%s: transition to resized (cqn=0x%x old_pi=%u new_pi=%u cur_cqe=%p)"),\r
- __func__,\r
- cq_p->cq_num, cq_p->cur_buf.consumer_index, cq_p->resized_buf.consumer_index,\r
- *cur_cqe_p);\r
- /* Transition to resized buffer */\r
- memcpy(&rm_buf,&(cq_p->cur_buf),sizeof(THHUL_cqe_buf_t)); /* save old buffer */\r
- /* Make resize buffer current. New consumer index is already updated. */\r
- memcpy(&(cq_p->cur_buf),&(cq_p->resized_buf),sizeof(THHUL_cqe_buf_t));\r
- cq_p->cur_spare_cqes= cq_p->cur_buf.spare_cqes; /* work with the spare CQEs of new buffer */\r
- /* Save old buffer to be freed in "resize_done" (no need to hurry...) */\r
- memcpy(&(cq_p->resized_buf),&rm_buf,sizeof(THHUL_cqe_buf_t)); \r
- cq_p->cq_state= THHUL_CQ_RESIZE_DONE; /* THHUL_cqm_resize_cq_done is still expected */\r
- return TRUE;\r
- }\r
- }\r
- return FALSE;\r
-}\r
-\r
-#define CQE_IMMEDIATE_DWORD_OFFSET \\r
- MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,immediate_ethertype_pkey_indx_eecredits)>>2\r
-#define CQE_BYTE_CNT_DWORD_OFFSET MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,byte_cnt)>>2\r
-\r
-\r
-#define CQE_WQE_ADDR_BYTE_OFFSET MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,wqe_adr)>>2\r
-#define CQE_WQE_ADDR_BIT_MASK (~MASK32(CQE_WQE_ADR_BIT_SZ))\r
-\r
-#define CQE_MY_QPN_BYTE_OFFSET MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,my_qpn)>>2\r
-#define CQE_MY_QPN_BYTE_BIT_MASK MASK32(24)\r
-\r
-#define CQE_OPCODE_BIT_MASK MASK32(MT_BIT_SIZE(tavorprm_completion_queue_entry_st,opcode))\r
-#define CQE_OPCODE_DWORD_OFFSET MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,opcode)>>2\r
-#define CQE_OPCODE_SHIFT (MT_BIT_OFFSET(tavorprm_completion_queue_entry_st,opcode) & MASK32(5))\r
-\r
-#ifdef WIN32\r
-/* Successful completion */\r
-HH_ret_t\r
-THHUL_cqm_comp_wc(\r
- IN THHUL_cq_t* const p_thhul_cq,\r
- IN const IB_wqpn_t qpn,\r
- IN const uint32_t wqe_addr_32lsb,\r
- IN volatile uint32_t* const cqe,\r
- IN const uint8_t opcode,\r
- IN const boolean_t send_cqe,\r
- OUT ib_wc_t* const p_wc )\r
-{\r
- boolean_t imm_valid;\r
- VAPI_special_qp_t qp_type;\r
- VAPI_ts_type_t qp_ts_type;\r
- u_int32_t i;\r
- HH_ret_t rc = HH_OK;\r
- u_int32_t free_res_count;\r
-\r
- rc = THHUL_qpm_comp_ok( p_thhul_cq->qpm, qpn, wqe_addr_32lsb,\r
- &qp_type, &qp_ts_type, &(p_wc->wr_id), &free_res_count, NULL );\r
- if( MOSAL_EXPECT_FALSE( rc != HH_OK ) )\r
- {\r
- MTL_ERROR1("THHUL_cqm_poll4cqe: Failed updating associated QP.\n");\r
- for( i= 0; i < (CQE_SZ>>2); i++ )\r
- {\r
- MTL_ERROR1(MT_FLFMT("CQ[0x%X][%u][%u]=0x%X"),p_thhul_cq->cq_num,\r
- (p_thhul_cq->cur_buf.consumer_index - 1) & MASK32(p_thhul_cq->cur_buf.log2_num_o_cqes),\r
- i, cl_ntoh32(cqe[i]));\r
- }\r
- return rc;\r
- }\r
-\r
- rc = decode_opcode2( send_cqe, opcode, &p_wc->wc_type, &imm_valid );\r
- if( MOSAL_EXPECT_FALSE( rc != HH_OK) )\r
- {\r
- MTL_ERROR4(MT_FLFMT("Invalid %s Opcode=0x%X"),\r
- send_cqe ? "send" : "receive", opcode );\r
- return rc;\r
- }\r
- p_wc->length = cl_ntoh32(cqe[CQE_BYTE_CNT_DWORD_OFFSET]);\r
-\r
- /* Need the op-code before copying the immediate data. */\r
- if( !send_cqe )\r
- {\r
-\r
- switch( qp_ts_type )\r
- {\r
- case VAPI_TS_UD:\r
- p_wc->recv.ud.recv_opt = 0;\r
-\r
- p_wc->recv.ud.remote_qp =\r
- cqe[CQE_RQPN_DWORD_OFFSET] &\r
- CL_HTON32(CQE_RQPN_BIT_MASK);\r
-\r
- p_wc->recv.ud.path_bits =\r
- ((uint8_t*)cqe)[0xD];\r
- /* The path bits now also have the GRH valid flag. */\r
- if( p_wc->recv.ud.path_bits & 0x80 )\r
- {\r
- p_wc->recv.ud.recv_opt |= IB_RECV_OPT_GRH_VALID;\r
- p_wc->recv.ud.path_bits &= 0x7F;\r
- }\r
- p_wc->recv.ud.remote_lid =\r
- ((net16_t*)cqe)[0x7];\r
- if( p_wc->recv.ud.remote_lid == IB_LID_PERMISSIVE ||\r
- cl_ntoh16(p_wc->recv.ud.remote_lid) >= IB_LID_MCAST_START_HO )\r
- {\r
- p_wc->recv.ud.path_bits = 0;\r
- }\r
-\r
- p_wc->recv.ud.remote_sl =\r
- (((uint8_t*)cqe)[0xC] >> 4);\r
-\r
- if( qp_type == VAPI_GSI_QP )\r
- {\r
- p_wc->recv.ud.pkey_index =\r
- (uint16_t)(cl_ntoh32(cqe[CQE_IMMEDIATE_DWORD_OFFSET]) >> 16);\r
- }\r
- else if( imm_valid )\r
- {\r
- p_wc->recv.ud.recv_opt |= IB_RECV_OPT_IMMEDIATE;\r
- p_wc->recv.ud.immediate_data = cqe[CQE_IMMEDIATE_DWORD_OFFSET];\r
- }\r
- break;\r
-\r
- case VAPI_TS_RC:\r
- case VAPI_TS_UC:\r
- if( imm_valid )\r
- {\r
- p_wc->recv.conn.recv_opt |= IB_RECV_OPT_IMMEDIATE;\r
- p_wc->recv.ud.immediate_data = cqe[CQE_IMMEDIATE_DWORD_OFFSET];\r
- }\r
- else\r
- {\r
- p_wc->recv.conn.recv_opt = 0;\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
- }\r
-\r
- p_wc->status = IB_WCS_SUCCESS;\r
-\r
- MTPERF_TIME_START(free_cqe);\r
- /*\r
- * Pass ownership to HW, but delay ringing the doorbell until\r
- * we're done polling\r
- */\r
- set_cqe_to_hw_own(cqe);\r
- p_thhul_cq->cur_buf.consumer_index =\r
- (p_thhul_cq->cur_buf.consumer_index + 1) &\r
- MASK32(p_thhul_cq->cur_buf.log2_num_o_cqes);\r
- MTPERF_TIME_END(free_cqe);\r
-\r
- return HH_OK;\r
-}\r
-\r
-\r
-/* Completion with error */\r
-HH_ret_t\r
-THHUL_cqm_failed_wc( \r
- IN THHUL_cq_t* const p_thhul_cq,\r
- IN const IB_wqpn_t qpn,\r
- IN const uint32_t wqe_addr_32lsb,\r
- IN volatile uint32_t* const cqe,\r
- IN const uint8_t opcode,\r
- OUT ib_wc_t* const p_wc )\r
-{\r
- u_int32_t next_wqe_addr_32lsb;\r
- u_int8_t dbd_bit;\r
- u_int32_t i,dbd_cnt;\r
- HH_ret_t rc = HH_OK;\r
- u_int32_t free_res_count;\r
- /* The CQE copy is required to hold in CPU endianess. */\r
- u_int32_t cqe_cpy[CQE_SZ>>2]; /* CQE copy */\r
-\r
-\r
- /* Make CQE copy in correct endianess */\r
- for (i= 0; i < (CQE_SZ>>2); i++)\r
- cqe_cpy[i]= MOSAL_be32_to_cpu(cqe[i]);\r
-\r
- MTL_DEBUG4("THHUL_cqm_poll4cqe: completion with error: cq=%d consumer_index=%d\n",\r
- p_thhul_cq->cq_num, p_thhul_cq->cur_buf.consumer_index);\r
- DUMP_CQE(p_thhul_cq->cq_num, p_thhul_cq->cur_buf.consumer_index, cqe);\r
- rc= THHUL_qpm_comp_err(p_thhul_cq->qpm, qpn, wqe_addr_32lsb,\r
- &p_wc->wr_id,&free_res_count,&next_wqe_addr_32lsb,&dbd_bit);\r
- if( rc != HH_OK )\r
- {\r
- MTL_ERROR1("THHUL_cqm_poll4cqe: Failed updating associated QP.\n");\r
- return rc;\r
- }\r
- p_wc->status= decode_error_syndrome2((tavor_if_comp_status_t)MT_EXTRACT_ARRAY32(cqe_cpy,\r
- CQE_ERROR_SYNDROM_BIT_OFFSET, CQE_ERROR_SYNDROM_BIT_SIZE) );\r
- p_wc->vendor_specific = MT_EXTRACT_ARRAY32(cqe_cpy,\r
- CQE_ERROR_VENDOR_SYNDROM_BIT_OFFSET, CQE_ERROR_VENDOR_SYNDROM_BIT_SIZE);\r
- dbd_cnt= MT_EXTRACT_ARRAY32(cqe_cpy,CQE_ERROR_DBDCNT_BIT_OFFSET, CQE_ERROR_DBDCNT_BIT_SIZE);\r
- if ((next_wqe_addr_32lsb == THHUL_QPM_END_OF_WQE_CHAIN) || /* End of WQE chain */\r
- ((dbd_cnt + 1 - dbd_bit) == 0) ) /* or dbd counter reached 0 */\r
- {\r
- MTPERF_TIME_START(free_cqe);\r
- free_cqe( p_thhul_cq, cqe ); /* Free original CQE and update consumer index */\r
- MTPERF_TIME_END(free_cqe);\r
- }\r
- else\r
- {\r
- recycle_cqe( cqe, next_wqe_addr_32lsb, dbd_cnt - dbd_bit );\r
- } \r
- /*\r
- * Only WQE-ID, free_res_count and status are required for completion with error. \r
- * No other CQE fields are extracted (see IB-spec. 11.4.2.1).\r
- * Even though, for the sake of some legacy code:\r
- * ...putting an opcode to distinguish completion of SQ from RQ\r
- */\r
- if( opcode == CQE_ERROR_ON_SQ )\r
- {\r
- p_wc->wc_type = IB_WC_SEND;\r
- }\r
- else\r
- {\r
- /* receive queue completion */\r
- p_wc->wc_type = IB_WC_RECV; \r
- }\r
- return HH_OK;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-THHUL_cqm_poll4wc( \r
- IN HHUL_hca_hndl_t hca_hndl, \r
- IN HHUL_cq_hndl_t cq, \r
- IN OUT ib_wc_t** const pp_free_wclist,\r
- OUT ib_wc_t** const pp_done_wclist )\r
-{\r
- THHUL_cq_t *thhul_cq_p= (THHUL_cq_t*)cq;\r
- volatile u_int32_t *cur_cqe;\r
- u_int32_t wqe_addr_32lsb;\r
- IB_wqpn_t qpn;\r
- uint8_t opcode;\r
- uint8_t send_cqe;\r
- HH_ret_t rc = HH_OK;\r
- ib_wc_t *p_wc, **pp_next;\r
- u_int32_t wc_cnt = 0;\r
-\r
- if (MOSAL_EXPECT_FALSE(thhul_cq_p == NULL))\r
- {\r
- MTL_ERROR1("THHUL_cqm_poll4cqe: NULL CQ handle.\n");\r
- return IB_INVALID_CQ_HANDLE;\r
- }\r
-\r
- CL_ASSERT( pp_free_wclist );\r
- CL_ASSERT( *pp_free_wclist );\r
- CL_ASSERT( pp_done_wclist );\r
-\r
- MOSAL_spinlock_dpc_lock(&(thhul_cq_p->cq_lock));\r
-\r
- /* Check if CQE at consumer index is valid */\r
- cur_cqe= (volatile u_int32_t*)\r
- (thhul_cq_p->cur_buf.cqe_buf_base +\r
- (thhul_cq_p->cur_buf.consumer_index << LOG2_CQE_SZ));\r
- pp_next = pp_done_wclist;\r
- p_wc = *pp_free_wclist;\r
- while( p_wc )\r
- {\r
- if( is_cqe_hw_own(cur_cqe) && /* CQE is still in HW ownership */\r
- !cq_transition_to_resized_buf( thhul_cq_p, &cur_cqe ) )\r
- {\r
- break;\r
- }\r
-\r
- /* Extract QP/WQE context fields from the CQE */\r
- /* Byte 6 */ \r
- wqe_addr_32lsb= MOSAL_be32_to_cpu(cur_cqe[CQE_WQE_ADDR_BYTE_OFFSET]) & \r
- CQE_WQE_ADDR_BIT_MASK;\r
-\r
- /* Byte 0*/\r
- qpn = MOSAL_be32_to_cpu(cur_cqe[CQE_MY_QPN_BYTE_OFFSET]) & CQE_MY_QPN_BYTE_BIT_MASK;\r
-\r
- /* new CQE: completion status is taken from "opcode" field */\r
- opcode = ((volatile uint8_t*)cur_cqe)[CQE_OPCODE_BYTE_OFFSET];\r
- send_cqe = \r
- ((volatile uint8_t*)cur_cqe)[CQE_S_BYTE_OFFSET] & CQE_S_BYTE_MASK;\r
- if( MOSAL_EXPECT_TRUE((opcode & CQE_ERROR_STATUS_MASK) != CQE_ERROR_STATUS_MASK) )\r
- {\r
- /* Completed OK */\r
- rc = THHUL_cqm_comp_wc( thhul_cq_p, qpn, wqe_addr_32lsb, cur_cqe,\r
- opcode, send_cqe, p_wc );\r
- if( MOSAL_EXPECT_FALSE( rc != HH_OK ) )\r
- break;\r
- wc_cnt++;\r
- }\r
- else\r
- {\r
- /* Completion with error */\r
- rc = THHUL_cqm_failed_wc( thhul_cq_p, qpn, wqe_addr_32lsb, cur_cqe,\r
- opcode, p_wc );\r
- if( MOSAL_EXPECT_FALSE( rc != HH_OK ) )\r
- break;\r
- }\r
-\r
- *pp_next = p_wc;\r
- pp_next = &p_wc->p_next;\r
- p_wc = p_wc->p_next;\r
- cur_cqe= (volatile u_int32_t*)\r
- (thhul_cq_p->cur_buf.cqe_buf_base +\r
- (thhul_cq_p->cur_buf.consumer_index << LOG2_CQE_SZ));\r
- }\r
-\r
- if( wc_cnt )\r
- {\r
- /* Ring the doorbell for all successful WCs. */\r
- dbell_cqe( thhul_cq_p, wc_cnt );\r
- }\r
-\r
- MOSAL_spinlock_unlock(&(thhul_cq_p->cq_lock)); \r
-\r
- /* Set the head of the free list. */\r
- *pp_free_wclist = p_wc;\r
- /* Clear the tail of the done list. */\r
- *pp_next = NULL;\r
-\r
- if( rc != HH_OK )\r
- return IB_ERROR;\r
- else if( *pp_done_wclist )\r
- return IB_SUCCESS;\r
- else\r
- return IB_NOT_FOUND;\r
-}\r
-\r
-\r
-ib_api_status_t\r
-THHUL_cqm_count_cqe( \r
- IN HHUL_hca_hndl_t hca_hndl,\r
- IN HHUL_cq_hndl_t cq,\r
- OUT uint32_t* const p_n_cqes )\r
-{\r
- THHUL_cq_t *cq_p= (THHUL_cq_t*)cq;\r
- VAPI_cqe_num_t cqe_num;\r
-\r
- /* parameters checks */\r
- if (cq_p == NULL) {\r
- MTL_ERROR1("THHUL_cqm_count_cqe: NULL CQ handle.\n");\r
- return IB_INVALID_CQ_HANDLE;\r
- }\r
-\r
- if( !p_n_cqes )\r
- return IB_INVALID_PARAMETER;\r
-\r
- /* Find CQE and check ownership */\r
- MOSAL_spinlock_dpc_lock(&(cq_p->cq_lock));\r
- /* The following check must be done with CQ-lock locked, since resize may change cur_buf \r
- on the same time */\r
- cqe_num = ((1U << cq_p->cur_buf.log2_num_o_cqes) - cq_p->cur_buf.spare_cqes - 1);\r
- *p_n_cqes = count_cqes(cq_p,cqe_num,NULL);\r
- \r
- MOSAL_spinlock_unlock(&(cq_p->cq_lock)); \r
-\r
- return IB_SUCCESS; \r
-}\r
-#endif\r
-\r
-\r
-HH_ret_t THHUL_cqm_peek_cq( \r
- /*IN*/ HHUL_hca_hndl_t hca_hndl, \r
- /*IN*/ HHUL_cq_hndl_t cq, \r
- /*IN*/ VAPI_cqe_num_t cqe_num\r
-)\r
-{\r
- THHUL_cq_t *cq_p= (THHUL_cq_t*)cq;\r
- volatile u_int32_t *cur_cqe;\r
- HH_ret_t ret;\r
-\r
- /* parameters checks */\r
- if (cq_p == NULL) {\r
- MTL_ERROR1("THHUL_cqm_peek_cq: NULL CQ handle.\n");\r
- return HH_EINVAL_CQ_HNDL;\r
- }\r
-\r
- /* Find CQE and check ownership */\r
- MOSAL_spinlock_dpc_lock(&(cq_p->cq_lock));\r
- /* The following check must be done with CQ-lock locked, since resize may change cur_buf \r
- on the same time */\r
- if ((cqe_num >= ((1U << cq_p->cur_buf.log2_num_o_cqes) - cq_p->cur_buf.spare_cqes)) || (cqe_num == 0)) { \r
- /* reminder: 1 CQE is always reserved */\r
- MTL_ERROR2("THHUL_cqm_peek_cq(cqn=0x%X): cqe_num=%u , max_num_o_cqes=%u .\n",\r
- cq_p->cq_num,cqe_num,\r
- ((1U << cq_p->cur_buf.log2_num_o_cqes) - cq_p->cur_buf.spare_cqes - 1));\r
- ret= HH_E2BIG_CQE_NUM;\r
- } else {\r
- cur_cqe= (volatile u_int32_t *)\r
- (cq_p->cur_buf.cqe_buf_base + \r
- (((cq_p->cur_buf.consumer_index + cqe_num - 1) & MASK32(cq_p->cur_buf.log2_num_o_cqes)) \r
- << LOG2_CQE_SZ));\r
- ret= ( (!is_cqe_hw_own(cur_cqe)) || (count_cqes(cq_p,cqe_num,NULL) >= cqe_num)) ? HH_OK : HH_CQ_EMPTY ;\r
- }\r
- \r
- MOSAL_spinlock_unlock(&(cq_p->cq_lock)); \r
-\r
- return ret; \r
-}\r
-\r
-\r
-HH_ret_t THHUL_cqm_query_cq( \r
- /*IN*/ HHUL_hca_hndl_t hca_hndl, \r
- /*IN*/ HHUL_cq_hndl_t cq, \r
- /*OUT*/ VAPI_cqe_num_t *num_o_cqes_p)\r
-{\r
- THHUL_cq_t *cq_p= (THHUL_cq_t*)cq;\r
- HH_ret_t ret=HH_OK;\r
-\r
- /* parameters checks */\r
- if (cq_p == NULL) {\r
- MTL_ERROR1("THHUL_cqm_query_cq: NULL CQ handle.\n");\r
- return HH_EINVAL_CQ_HNDL;\r
- }\r
-\r
- /* Find CQE and check ownership */\r
- MOSAL_spinlock_dpc_lock(&(cq_p->cq_lock));\r
- *num_o_cqes_p= ((1U << cq_p->cur_buf.log2_num_o_cqes) -1 - cq_p->cur_buf.spare_cqes) ;\r
- \r
- MOSAL_spinlock_unlock(&(cq_p->cq_lock)); \r
-\r
- return ret; \r
-}\r
-\r
-static void rearm_cq(THHUL_cq_t *cq_p, MT_bool solicitedNotification) {\r
- volatile u_int32_t chimeWords[2];\r
- THH_uar_t uar = cq_p->uar;\r
-\r
-#ifndef __MOSAL_MMAP_IO_WRITE_QWORD_ATOMIC__\r
- MOSAL_spinlock_dpc_lock(&(uar->uar_lock));\r
-#endif\r
-\r
-#if THHUL_CQM_COALESCE_CQ_DOORBELLS\r
- if (cq_p->coalesce_count) {\r
- cq_p->coalesce_count = 0;\r
- chimeWords[0] = MOSAL_cpu_to_be32(0\r
- | (u_int32_t)cq_p->cq_num\r
- | (TAVOR_IF_UAR_CQ_SET_CI << 24)\r
- );\r
-\r
- chimeWords[1] = MOSAL_cpu_to_be32(cq_p->cur_buf.consumer_index);\r
- MOSAL_MMAP_IO_WRITE_QWORD(uar->uar_base + UAR_CQ_DBELL_OFFSET, *(volatile u_int64_t*)chimeWords);\r
- }\r
-#endif\r
-\r
- chimeWords[0] = MOSAL_cpu_to_be32(0\r
- | (u_int32_t)cq_p->cq_num\r
- | ((solicitedNotification ? TAVOR_IF_UAR_CQ_NOTIF_SOLIC_COMP: TAVOR_IF_UAR_CQ_NOTIF_NEXT_COMP) << 24)\r
- );\r
-\r
- chimeWords[1] = 0xffffffff;\r
- MOSAL_MMAP_IO_WRITE_QWORD(uar->uar_base + UAR_CQ_DBELL_OFFSET, *(volatile u_int64_t*)chimeWords);\r
-\r
-#ifndef __MOSAL_MMAP_IO_WRITE_QWORD_ATOMIC__\r
- MOSAL_spinlock_unlock(&(uar->uar_lock));\r
-#endif\r
-\r
-}\r
-\r
-\r
-HH_ret_t THHUL_cqm_req_comp_notif( \r
- /*IN*/ HHUL_hca_hndl_t hca_hndl, \r
- /*IN*/ HHUL_cq_hndl_t cq, \r
- /*IN*/ VAPI_cq_notif_type_t notif_type \r
-) \r
-{ \r
- THHUL_cq_t *thhul_cq_p= (THHUL_cq_t*)cq;\r
- u_int32_t last_consumer_index;\r
- HH_ret_t rc;\r
-\r
- if (thhul_cq_p == NULL) {\r
- MTL_ERROR1("THHUL_cqm_req_comp_notif: NULL CQ handle.\n");\r
- return HH_EINVAL_CQ_HNDL;\r
- }\r
- \r
- MOSAL_spinlock_dpc_lock(&(thhul_cq_p->cq_lock));\r
-#ifdef NO_CQ_CI_DBELL\r
- /* In "overrun ignore" mode, last consumed must be given */\r
- last_consumer_index= \r
- ((thhul_cq_p->cur_buf.consumer_index - 1) & MASK32(thhul_cq_p->cur_buf.log2_num_o_cqes));\r
-#else\r
- /* Consumer index is updated on every poll, so InfiniHost has its updated value */\r
- last_consumer_index= 0xFFFFFFFF ; /* Use current CI value */\r
-#endif\r
- sync_consumer_index(thhul_cq_p, __func__);/*Consumer index must be updated before req. an event*/\r
- MOSAL_spinlock_unlock(&(thhul_cq_p->cq_lock));\r
-\r
- switch (notif_type) {\r
- case VAPI_SOLIC_COMP:\r
- rc= THH_uar_cq_cmd(thhul_cq_p->uar,TAVOR_IF_UAR_CQ_NOTIF_SOLIC_COMP,\r
- thhul_cq_p->cq_num,last_consumer_index);\r
- break;\r
- case VAPI_NEXT_COMP:\r
- rc= THH_uar_cq_cmd(thhul_cq_p->uar,TAVOR_IF_UAR_CQ_NOTIF_NEXT_COMP,\r
- thhul_cq_p->cq_num,last_consumer_index);\r
- break;\r
- default:\r
- rc= HH_EINVAL; /* Invalid notification request */\r
- }\r
- \r
- return rc; \r
-}\r
-\r
-HH_ret_t THHUL_cqm_req_ncomp_notif( \r
- /*IN*/ HHUL_hca_hndl_t hca_hndl, \r
- /*IN*/ HHUL_cq_hndl_t cq, \r
- /*IN*/ VAPI_cqe_num_t cqe_num \r
-) \r
-{ \r
- THHUL_cq_t *cq_p= (THHUL_cq_t*)cq;\r
- VAPI_cqe_num_t hw_cqe_cnt,sw_cqe_cnt;\r
- HH_ret_t rc;\r
-\r
- if (cq_p == NULL) {\r
- MTL_ERROR1("THHUL_cqm_req_ncomp_notif: NULL CQ handle.\n");\r
- return HH_EINVAL;\r
- }\r
-\r
- /* cqe_num fix (due to CQEs with error... external CQEs) :\r
- * Check if cqe_num requirement was already fulfilled with external/sw CQEs\r
- * If yes: generate immediate event by setting cqe_num to 1\r
- * Otherwise: cqe_num is set to the HW number of CQEs based on current difference from sw_cnt \r
- */\r
- MOSAL_spinlock_dpc_lock(&(cq_p->cq_lock));\r
- /* Check cqe_num limits (must be done with lock held to avoid a race with "resize") */\r
- if ((cqe_num >= ((1U << cq_p->cur_buf.log2_num_o_cqes) - cq_p->cur_buf.spare_cqes)) || \r
- (cqe_num == 0) ||\r
- (cqe_num > MAX_NCOMP_NOTIF)) { \r
- /* reminder: 1 CQE is always reserved */\r
- MTL_ERROR2("THHUL_cqm_req_ncomp_notif(cqn=%d): cqe_num=%d , max_num_o_cqes=%d .\n",\r
- cq_p->cq_num,cqe_num,\r
- ((1U << cq_p->cur_buf.log2_num_o_cqes) - cq_p->cur_buf.spare_cqes - 1));\r
- MOSAL_spinlock_unlock(&(cq_p->cq_lock));\r
- return HH_E2BIG_CQE_NUM;\r
- }\r
- sw_cqe_cnt= count_cqes(cq_p,cqe_num,&hw_cqe_cnt);\r
- cqe_num= (sw_cqe_cnt >= cqe_num) ? 1 : hw_cqe_cnt + (cqe_num - sw_cqe_cnt) ;\r
-\r
- sync_consumer_index(cq_p, __func__);/*Consumer index must be updated before req. an event*/\r
-\r
- rc= THH_uar_cq_cmd(cq_p->uar,TAVOR_IF_UAR_CQ_NOTIF_NCOMP,cq_p->cq_num,cqe_num);\r
- MOSAL_spinlock_unlock(&(cq_p->cq_lock));\r
- \r
- return rc; \r
-}\r
-\r
-/**********************************************************************************************\r
- * Private Functions \r
- **********************************************************************************************/\r
-\r
-\r
-static HH_ret_t cqe_buf_alloc(THHUL_cqe_buf_t *cqe_buf, VAPI_cqe_num_t num_o_cqes)\r
-{\r
- u_int32_t i;\r
- volatile u_int8_t* cur_cqe_owner_byte;\r
- VAPI_cqe_num_t actual_num_o_cqes; /* Number of CQEs in the CQEs buffer */\r
- VAPI_cqe_num_t possible_spare_cqes;\r
- \r
- cqe_buf->log2_num_o_cqes= floor_log2(num_o_cqes) + 1; /* next power of 2 including extra CQE */\r
- actual_num_o_cqes= (1 << cqe_buf->log2_num_o_cqes); \r
-#if defined(MT_KERNEL) && defined(__LINUX__)\r
- if (((actual_num_o_cqes + 1) * CQE_SZ) <= CQ_KMALLOC_LIMIT) \r
- cqe_buf->cqe_buf_orig= \r
- MOSAL_pci_phys_alloc_consistent((actual_num_o_cqes + 1) * CQE_SZ, LOG2_CQE_SZ); /* one extra for alignment */\r
- else\r
-#endif\r
-#if !defined(MT_KERNEL) && defined(MT_FORK_SUPPORT)\r
-/* Fork workaroud - cover full pages */\r
- cqe_buf->cqe_buf_orig= \r
- MOSAL_pci_virt_alloc_consistent(\r
- (MOSAL_SYS_PAGE_SIZE-1)/*for page alignement*/ +\r
- MT_UP_ALIGNX_ULONG_PTR(actual_num_o_cqes * CQE_SZ, MOSAL_SYS_PAGE_SHIFT),\r
- LOG2_CQE_SZ);\r
-#else\r
- cqe_buf->cqe_buf_orig= \r
-#ifdef WIN32\r
- /* Use pageable memory, since it gets registered. */\r
- cl_pzalloc( (actual_num_o_cqes + 1) * CQE_SZ );\r
-#else /* WIN32 */\r
- MOSAL_pci_virt_alloc_consistent((actual_num_o_cqes + 1) * CQE_SZ, LOG2_CQE_SZ); /* one extra for alignment */\r
-#endif /* WIN32 */\r
-#endif\r
- if (cqe_buf->cqe_buf_orig == NULL) {\r
- MTL_ERROR1("%s: Failed to allocate CQEs buffer of 0x%X bytes.\n",__func__,\r
- (actual_num_o_cqes + 1) * CQE_SZ);\r
- return HH_EAGAIN;\r
- }\r
-#if !defined(MT_KERNEL) && defined(MT_FORK_SUPPORT)\r
- cqe_buf->cqe_buf_base= MT_UP_ALIGNX_VIRT((MT_virt_addr_t)cqe_buf->cqe_buf_orig,MOSAL_SYS_PAGE_SHIFT);\r
-#else \r
- /* buffer must be aligned to CQE size */\r
- cqe_buf->cqe_buf_base= MT_UP_ALIGNX_VIRT((MT_virt_addr_t)cqe_buf->cqe_buf_orig,LOG2_CQE_SZ);\r
-#endif\r
- /* Initialize all CQEs to HW ownership */\r
- cur_cqe_owner_byte= (volatile u_int8_t*)(cqe_buf->cqe_buf_base+CQE_OWNER_BYTE_OFFSET);\r
- for (i= 0; i < actual_num_o_cqes; i++) { \r
- *cur_cqe_owner_byte= (1<<CQE_OWNER_SHIFT);\r
- cur_cqe_owner_byte+= CQE_SZ;\r
- }\r
- possible_spare_cqes= actual_num_o_cqes - 1/*Reserved CQE*/ - num_o_cqes; /* For CQ DB coalescing */\r
- cqe_buf->spare_cqes= (possible_spare_cqes > MAX_CQDB2DELAY) ? MAX_CQDB2DELAY : possible_spare_cqes;\r
- MTL_DEBUG4(MT_FLFMT("%s: spare_cqes=%u"),__func__,cqe_buf->spare_cqes);\r
- cqe_buf->consumer_index= 0;\r
- return HH_OK;\r
-}\r
-\r
-static void cqe_buf_free(THHUL_cqe_buf_t *cqe_buf)\r
-{\r
- /* Cleanup CQ resources */\r
-#if defined(MT_KERNEL) && defined(__LINUX__)\r
- if ((((1U<<cqe_buf->log2_num_o_cqes)+1)*CQE_SZ) <= CQ_KMALLOC_LIMIT) \r
- MOSAL_pci_phys_free_consistent(cqe_buf->cqe_buf_orig, ((1U<<cqe_buf->log2_num_o_cqes)+1)*CQE_SZ);\r
- else\r
-#endif\r
-#ifdef WIN32\r
- cl_free( cqe_buf->cqe_buf_orig );\r
-#else\r
- MOSAL_pci_virt_free_consistent(cqe_buf->cqe_buf_orig, ((1U<<cqe_buf->log2_num_o_cqes)+1)*CQE_SZ);\r
-#endif\r
-}\r
-\r
-/* Perform the "CQ cleanup" flow (removing of CQEs of a RESET QP) and return \r
- * amount of removed CQEs (the change in consumer index)\r
- * - cur_pi_p : return PI at given buffer (to be used in THHUL_CQ_RESIZE_PREP state)\r
- */\r
-static u_int32_t cqe_buf_cleanup(THHUL_cqe_buf_t *cqe_buf,IB_wqpn_t qp,\r
- THHUL_srqm_t srqm, HHUL_srq_hndl_t srq,\r
- u_int32_t *cur_producer_index_p)\r
-{\r
- u_int32_t cur_tail_index,next_consumer_index,cur_cqe_index;\r
- u_int32_t outstanding_cqes,i;\r
- u_int32_t removed_cqes= 0;\r
- volatile u_int32_t *cur_cqe_p;\r
- volatile u_int32_t *next_cqe_p;\r
- IB_wqpn_t cur_qpn;\r
- const u_int32_t num_o_cqes_mask= MASK32(cqe_buf->log2_num_o_cqes);\r
- MT_bool is_rq_cqe;\r
- u_int32_t wqe_addr_32lsb;\r
- VAPI_wr_id_t wqe_id;\r
- \r
-\r
- /* Find last CQE is software ownership (cur_tail) */\r
- outstanding_cqes= 0;\r
- cur_tail_index= cqe_buf->consumer_index;\r
-#ifndef NO_CQ_CI_DBELL\r
- while (1) { /* Break out when find a CQE in HW ownership */\r
- /* (there must be at least one CQE in HW ownership - the reserved "full" CQE)*/\r
-#else\r
- while (outstanding_cqes <= (1<<cqe_buf->log2_num_o_cqes)) {\r
- /* In CQ-overrun-ignore mode, all CQEs in CQ may be in SW ownership... */\r
-#endif\r
- cur_cqe_p= (volatile u_int32_t *)\r
- (cqe_buf->cqe_buf_base + (cur_tail_index << LOG2_CQE_SZ));\r
- if (is_cqe_hw_own(cur_cqe_p)) break; /* no more outstanding CQEs */ \r
-\r
- outstanding_cqes++;\r
- cur_tail_index= (cur_tail_index + 1) & num_o_cqes_mask;\r
- }\r
- *cur_producer_index_p= cur_tail_index; /* To be used on resized buffer */\r
- /* move back to last in SW ownership */\r
- cur_cqe_index= next_consumer_index= (cur_tail_index - 1) & num_o_cqes_mask;\r
-\r
- MTL_DEBUG4(MT_FLFMT("Found %d outstanding CQEs. Last CQE at index %d."),\r
- outstanding_cqes,cur_cqe_index);\r
- \r
- /* Scan back CQEs (cur_cqe) and move all CQEs not of given qpn back to "cur_head" */\r
- for (i= 0; i < outstanding_cqes; i++) {\r
- cur_cqe_p= (volatile u_int32_t *)\r
- (cqe_buf->cqe_buf_base + (cur_cqe_index << LOG2_CQE_SZ));\r
- cur_qpn= \r
- MOSAL_be32_to_cpu(cur_cqe_p[MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,my_qpn)>>2])\r
- & MASK32(24);\r
-\r
- if (cur_qpn == qp) { /* A CQE to remove */\r
- /* Go back only with the cur_cqe_index, leave next_consumer_index behind (for next copy) */\r
- cur_cqe_index= (cur_cqe_index - 1) & num_o_cqes_mask;\r
- \r
- /* If associated with SRQ must invoke THHUL_srqm_comp to release WQE */\r
- if (srq != HHUL_INVAL_SRQ_HNDL) {\r
- is_rq_cqe= (MT_EXTRACT32(\r
- MOSAL_be32_to_cpu(cur_cqe_p[MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,s)>>2]),\r
- MT_BIT_OFFSET(tavorprm_completion_queue_entry_st,s) & MASK32(5),\r
- MT_BIT_SIZE(tavorprm_completion_queue_entry_st,s)) == 0);\r
- if (is_rq_cqe) { /* Completion must be reported to SRQ */\r
- wqe_addr_32lsb= /* Mask off size bits from dword of WQE addr. */\r
- MOSAL_be32_to_cpu(\r
- cur_cqe_p[MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,wqe_adr)>>2]\r
- ) & \r
- (0xFFFFFFFF << MT_BIT_SIZE(tavorprm_completion_queue_entry_st,wqe_size));\r
- THHUL_srqm_comp(srqm, srq, wqe_addr_32lsb, &wqe_id); /* Release WQE */\r
- }\r
- }\r
-\r
- } else { /* A CQE to copy (if any CQE was removed) */\r
- if (cur_cqe_index != next_consumer_index) { /* Copy required */\r
- MTL_DEBUG4(MT_FLFMT("Moving CQE at index %d to index %d\n"),\r
- cur_cqe_index,next_consumer_index); \r
- next_cqe_p= (volatile u_int32_t *)\r
- (cqe_buf->cqe_buf_base + (next_consumer_index << LOG2_CQE_SZ));\r
- memcpy((void*)next_cqe_p,(void*)cur_cqe_p,CQE_SZ);\r
- }\r
- /* Go back with both indices */\r
- cur_cqe_index= (cur_cqe_index - 1) & num_o_cqes_mask;\r
- next_consumer_index= (next_consumer_index - 1) & num_o_cqes_mask;\r
- }\r
- }\r
- \r
- if (cur_cqe_index != next_consumer_index) { /* CQEs were removed */\r
- /* Return to hardware ownership CQEs at amount of removed CQEs (from consumer index side) */\r
- for (cur_cqe_index= cqe_buf->consumer_index; ; \r
- cur_cqe_index= (cur_cqe_index + 1) & num_o_cqes_mask) {\r
- removed_cqes++;\r
- cur_cqe_p= (volatile u_int32_t *) \r
- (cqe_buf->cqe_buf_base + (cur_cqe_index << LOG2_CQE_SZ));\r
- set_cqe_to_hw_own(cur_cqe_p);\r
- if (cur_cqe_index == next_consumer_index) break; /* Returned all including this one */\r
- \r
- }\r
- \r
- /* update consumer index - go back to location of last copied */\r
- cqe_buf->consumer_index= (next_consumer_index + 1) & num_o_cqes_mask; \r
- }\r
-\r
- return removed_cqes;\r
-}\r
-\r
-/* This function copies any old CQEs left in cur_buf to resized_buf */\r
-/* (Should be called with CQ lock held) */\r
-static void cqe_buf_cpy2resized(\r
- THHUL_cqe_buf_t *cur_buf, \r
- THHUL_cqe_buf_t *resized_buf, \r
- MT_bool compute_new_pi) /* New resize-CQ flow */\r
-{\r
- u_int32_t cur_cqe_index;\r
- u_int32_t outs_cqes_at_ci=0,outs_cqes_at_cq_base=0;\r
- u_int32_t *outs_cqes_p; /* pointer to currect count (one of the above) */\r
- volatile u_int32_t *cur_cqe_p;\r
- void *cur_cpy_p; /* Pointer to copy (from) point */\r
- void *resized_cpy_p; /* Pointer to copy (to) point */\r
- u_int32_t resized_cqes_at_top; /* CQEs available to buffer's top - when wrap around */\r
- u_int32_t resized_cur_pi; /* Current "producer index" */\r
- const u_int32_t num_o_cqes_mask= MASK32(cur_buf->log2_num_o_cqes);\r
- const u_int32_t new_num_o_cqes_mask= MASK32(resized_buf->log2_num_o_cqes); /* for modulo */\r
- \r
-\r
- /* Count number of CQEs in cur_buf */\r
- outs_cqes_p= &outs_cqes_at_ci; /* First count the CQEs above the consumer index */\r
- cur_cqe_index= cur_buf->consumer_index;\r
- while (1) { /* Break out when find a CQE in HW ownership */\r
- /* (there must be at least one CQE in HW ownership - the reserved "full" CQE)*/\r
- cur_cqe_p= (volatile u_int32_t *)\r
- (cur_buf->cqe_buf_base + (cur_cqe_index << LOG2_CQE_SZ));\r
- if (is_cqe_hw_own(cur_cqe_p)) break; /* no more outstanding CQEs */ \r
- (*outs_cqes_p)++;\r
- cur_cqe_index= (cur_cqe_index + 1) & num_o_cqes_mask;\r
- if (cur_cqe_index == 0) { /* next CQEs are at CQ base */\r
- outs_cqes_p= &outs_cqes_at_cq_base;\r
- }\r
- }\r
-\r
- if (compute_new_pi) {\r
- resized_buf->consumer_index= cur_cqe_index & new_num_o_cqes_mask; /* New fixed resize-CQ */\r
- MTL_DEBUG5(MT_FLFMT("%s: old_pi=%u new_pi=%u new_log2_sz=%u"), __func__,\r
- cur_cqe_index, resized_buf->consumer_index, resized_buf->log2_num_o_cqes);\r
- } else { /* legacy flow */\r
- /* Number of outstanding CQEs in old buffer is always less than new consumer index */\r
- if (resized_buf->consumer_index < outs_cqes_at_ci + outs_cqes_at_cq_base) { /* sanity check */\r
- MTL_ERROR1(MT_FLFMT(\r
- "THHUL_cqm_resize_cq_done: Unexpected error !"\r
- " found more outstanding CQEs (%d) than resized buffer's consumer index (%d) !"),\r
- outs_cqes_at_ci + outs_cqes_at_cq_base,resized_buf->consumer_index);\r
- return;\r
- }\r
- }\r
-\r
- resized_buf->consumer_index = /* This computation should work for legacy mode, too */\r
- (resized_buf->consumer_index - outs_cqes_at_ci - outs_cqes_at_cq_base) & new_num_o_cqes_mask;\r
- resized_cur_pi= resized_buf->consumer_index; /* Where CQE copy starts at resized buffer */\r
-\r
- if (outs_cqes_at_ci > 0) { /* First copy CQEs above consumer index */\r
- cur_cpy_p= (void *)\r
- (cur_buf->cqe_buf_base + (cur_buf->consumer_index << LOG2_CQE_SZ));\r
- resized_cpy_p= (void *)\r
- (resized_buf->cqe_buf_base + (resized_buf->consumer_index << LOG2_CQE_SZ));\r
- resized_cqes_at_top= (1U<<resized_buf->log2_num_o_cqes) - resized_cur_pi;\r
- if (resized_cqes_at_top > outs_cqes_at_ci) { /* enough room for all CQEs at CI ? */\r
- memcpy(resized_cpy_p, cur_cpy_p, outs_cqes_at_ci << LOG2_CQE_SZ);\r
- } else {\r
- memcpy(resized_cpy_p, cur_cpy_p, resized_cqes_at_top << LOG2_CQE_SZ);\r
- resized_cpy_p= (void *)(resized_buf->cqe_buf_base);\r
- (char*)cur_cpy_p += (resized_cqes_at_top << LOG2_CQE_SZ);\r
- memcpy(resized_cpy_p, cur_cpy_p, (outs_cqes_at_ci - resized_cqes_at_top) << LOG2_CQE_SZ);\r
- }\r
- resized_cur_pi= (resized_cur_pi + outs_cqes_at_ci) & new_num_o_cqes_mask;\r
- }\r
- if (outs_cqes_at_cq_base > 0) { /* Next copy CQEs at CQ base (wrap around...) */\r
- cur_cpy_p= (void *) cur_buf->cqe_buf_base ;\r
- resized_cpy_p= (void *) (resized_buf->cqe_buf_base + (resized_cur_pi << LOG2_CQE_SZ)) ;\r
- resized_cqes_at_top= (1U<<resized_buf->log2_num_o_cqes) - resized_cur_pi;\r
- if (resized_cqes_at_top > outs_cqes_at_cq_base) { /* enough room for all CQEs at base ? */\r
- memcpy(resized_cpy_p, cur_cpy_p, outs_cqes_at_cq_base << LOG2_CQE_SZ);\r
- } else {\r
- memcpy(resized_cpy_p, cur_cpy_p, resized_cqes_at_top << LOG2_CQE_SZ);\r
- resized_cpy_p= (void *)(resized_buf->cqe_buf_base);\r
- (char*)cur_cpy_p += (resized_cqes_at_top << LOG2_CQE_SZ);\r
- memcpy(resized_cpy_p, cur_cpy_p, (outs_cqes_at_cq_base - resized_cqes_at_top) << LOG2_CQE_SZ);\r
- }\r
- }\r
-\r
- return;\r
-}\r
-\r
-/* Count number of real CQEs (i.e., including CQEs with error) up to given limit */\r
-/* (return the real number of CQEs) */\r
-/* The function must be invoked with CQ lock held */\r
-static VAPI_cqe_num_t count_cqes( \r
- /*IN*/ THHUL_cq_t *cq_p,\r
- /*IN*/ VAPI_cqe_num_t cqe_cnt_limit, /* Limit count up to given HW CQEs */\r
- /*OUT*/ VAPI_cqe_num_t *hw_cqe_cnt_p /* HW CQEs count (optional) */\r
-)\r
-{\r
- volatile u_int32_t *cur_cqe;\r
- VAPI_cqe_num_t sw_cqe_cntr= 0;\r
- VAPI_cqe_num_t hw_cqe_cntr= 0;\r
- u_int32_t wqe_addr_32lsb;\r
- IB_wqpn_t qpn;\r
- u_int8_t opcode;\r
- u_int16_t dbdcnt= 0;\r
-\r
- /* Count CQEs including "external" of CQEs with error */\r
- while (hw_cqe_cntr < cqe_cnt_limit) {\r
- /* Find CQE and check ownership */\r
- cur_cqe= (volatile u_int32_t *)\r
- (cq_p->cur_buf.cqe_buf_base + \r
- (((cq_p->cur_buf.consumer_index + hw_cqe_cntr) & MASK32(cq_p->cur_buf.log2_num_o_cqes)) \r
- << LOG2_CQE_SZ));\r
- if (is_cqe_hw_own(cur_cqe)) break; /* no more CQEs */\r
-\r
- opcode= ((volatile u_int8_t*)cur_cqe)[CQE_OPCODE_BYTE_OFFSET]; /* get completion status */\r
- if ((opcode & CQE_ERROR_STATUS_MASK) != CQE_ERROR_STATUS_MASK) { /* Completed OK */ \r
- sw_cqe_cntr++;\r
- } else { /* CQE with error - count external CQEs */\r
- \r
- wqe_addr_32lsb= (\r
- MOSAL_cpu_to_be32(\r
- cur_cqe[MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st, wqe_adr)>>2])\r
- & \r
- (~MASK32(CQE_WQE_ADR_BIT_SZ)));\r
-\r
- qpn= (\r
- MOSAL_cpu_to_be32(\r
- cur_cqe[MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st, my_qpn)>>2]) \r
- & \r
- MASK32(24) );\r
- \r
-/*** warning C4244: '=' : conversion from 'unsigned long' to 'u_int16_t', possible loss of data ***/\r
- dbdcnt= (u_int16_t)(\r
- MOSAL_cpu_to_be32(\r
- cur_cqe[MT_BYTE_OFFSET(tavorprm_completion_queue_entry_st,\r
- immediate_ethertype_pkey_indx_eecredits)>>2]) \r
- & \r
- MASK32(CQE_ERROR_DBDCNT_BIT_SIZE) );\r
-\r
- /* Add total number of WQEs "hang" over given CQE with error */\r
- sw_cqe_cntr+= THHUL_qpm_wqe_cnt(cq_p->qpm, qpn, wqe_addr_32lsb, dbdcnt);\r
- }\r
- hw_cqe_cntr++; /* Continue to the next HW CQE */\r
- }\r
- \r
- if (hw_cqe_cnt_p) *hw_cqe_cnt_p= hw_cqe_cntr;\r
- MTL_DEBUG5(MT_FLFMT("%s: cqe_cnt_limit=%d sw_cqe_cntr=%d hw_cqe_cntr=%d\n"),__func__,\r
- cqe_cnt_limit,sw_cqe_cntr,hw_cqe_cntr);\r
- return sw_cqe_cntr;\r
-}\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_THHUL_CQM_H\r
-#define H_THHUL_CQM_H\r
-\r
-#include <mtl_common.h>\r
-#include <hhul.h>\r
-#include <thhul.h>\r
-#include <iba/ib_types.h>\r
-\r
-\r
-DLL_API HH_ret_t THHUL_cqm_create( \r
- /*IN*/ THHUL_hob_t hob, \r
- /*OUT*/ THHUL_cqm_t *cqm_p \r
-);\r
-\r
-DLL_API HH_ret_t THHUL_cqm_destroy (\r
- /*IN*/ THHUL_cqm_t cqm\r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_cqm_create_cq_prep(\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ VAPI_cqe_num_t num_o_cqes, \r
- /*OUT*/ HHUL_cq_hndl_t *hhul_cq_p, \r
- /*OUT*/ VAPI_cqe_num_t *num_o_cqes_p, \r
- /*OUT*/ void/*THH_cq_ul_resources_t*/ *cq_ul_resources_p \r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_cqm_create_cq_done(\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_cq_hndl_t hhul_cq, \r
- /*IN*/ HH_cq_hndl_t hh_cq, \r
- /*IN*/ void/*THH_cq_ul_resources_t*/ *cq_ul_resources_p \r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_cqm_destroy_cq_done(\r
- /*IN*/ HHUL_hca_hndl_t hca_hndl, \r
- /*IN*/ HHUL_cq_hndl_t cq \r
-);\r
-\r
-\r
-DLL_API ib_api_status_t THHUL_cqm_resize_cq_prep(\r
- /*IN*/ HHUL_hca_hndl_t hca_hndl, \r
- /*IN*/ HHUL_cq_hndl_t cq, \r
- /*IN*/ VAPI_cqe_num_t num_o_cqes, \r
- /*OUT*/ VAPI_cqe_num_t *num_o_cqes_p, \r
- /*OUT*/ void/*THH_cq_ul_resources_t*/ *cq_ul_resources_p \r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_cqm_resize_cq_done( \r
- /*IN*/ HHUL_hca_hndl_t hca_hndl, \r
- /*IN*/ HHUL_cq_hndl_t cq, \r
- /*IN*/ void/*THH_cq_ul_resources_t*/ *cq_ul_resources_p \r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_cqm_cq_cleanup( \r
- /*IN*/ HHUL_cq_hndl_t cq, \r
- /*IN*/ IB_wqpn_t qp,\r
- /*IN*/ THHUL_srqm_t srqm,\r
- /*IN*/ HHUL_srq_hndl_t srq\r
-);\r
-\r
-#ifdef WIN32\r
-DLL_API ib_api_status_t\r
-THHUL_cqm_poll4wc( \r
- IN HHUL_hca_hndl_t hca_hndl, \r
- IN HHUL_cq_hndl_t cq, \r
- IN OUT ib_wc_t** const pp_free_wclist,\r
- OUT ib_wc_t** const pp_done_wclist );\r
-\r
-DLL_API ib_api_status_t\r
-THHUL_cqm_count_cqe( \r
- IN HHUL_hca_hndl_t hca_hndl,\r
- IN HHUL_cq_hndl_t cq,\r
- OUT uint32_t* const p_n_cqes );\r
-#endif\r
-\r
-DLL_API HH_ret_t THHUL_cqm_query_cq( \r
- /*IN*/ HHUL_hca_hndl_t hca_hndl, \r
- /*IN*/ HHUL_cq_hndl_t cq, \r
- /*OUT*/ VAPI_cqe_num_t *num_o_cqes_p\r
-);\r
-\r
-DLL_API HH_ret_t THHUL_cqm_peek_cq( \r
- /*IN*/ HHUL_hca_hndl_t hca_hndl, \r
- /*IN*/ HHUL_cq_hndl_t cq, \r
- /*IN*/ VAPI_cqe_num_t cqe_num\r
-);\r
-\r
-DLL_API HH_ret_t THHUL_cqm_req_comp_notif( \r
- /*IN*/ HHUL_hca_hndl_t hca_hndl, \r
- /*IN*/ HHUL_cq_hndl_t cq, \r
- /*IN*/ VAPI_cq_notif_type_t notif_type \r
-);\r
-\r
-DLL_API HH_ret_t THHUL_cqm_req_ncomp_notif( \r
- /*IN*/ HHUL_hca_hndl_t hca_hndl, \r
- /*IN*/ HHUL_cq_hndl_t cq, \r
- /*IN*/ VAPI_cqe_num_t cqe_num \r
-) ;\r
-#endif /* H_THHUL_CQM_H */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#define C_THHUL_HOB_C\r
-\r
-#include <mosal.h>\r
-#include <MT23108.h>\r
-#include "thhul_hob.h"\r
-#include <thhul_pdm.h>\r
-#include <thhul_cqm.h>\r
-#include <thhul_srqm.h>\r
-#include <thhul_qpm.h>\r
-#include <thhul_mwm.h>\r
-#include <uar.h>\r
-\r
-#define GET_HOB(hhul_dev) (hhul_dev ? ((THHUL_hob_t)(hhul_dev->device)) : NULL)\r
-\r
-struct THHUL_hob_st { /* *THHUL_hob_t; */\r
- HHUL_hca_dev_t hhul_hca; /* HHUL's device context */\r
- THH_hca_ul_resources_t ul_res; /* Resources allocated by HH_alloc_ul_resources() */\r
- /* Included objects */\r
- THH_uar_t uar;\r
- THHUL_pdm_t pdm;\r
- THHUL_cqm_t cqm;\r
- THHUL_qpm_t qpm;\r
- THHUL_srqm_t srqm;\r
- THHUL_mwm_t mwm;\r
-\r
- /* global_resource_cnt:\r
- * A counter for resources set up for within this THHUL_hob context.\r
- * This counter enables avoiding object destruction in case there are still \r
- * resources that were not freed (e.g. QPs).\r
- * Each THHUL object is responsible to update this counter using THHUL_hob_res_add/rem */\r
- u_int32_t global_resource_cnt;\r
- MOSAL_mutex_t cntr_lock; /* A lock for assuring atomicity of the counter lock */\r
-};\r
-\r
-static HHUL_if_ops_t thhul_ops=\r
-{ \r
- THHUL_hob_destroy /* HHULIF_cleanup_user_level*/, \r
- THHUL_pdm_alloc_pd_prep /* HHULIF_alloc_pd_prep */,\r
- THHUL_pdm_alloc_pd_avs_prep /* HHULIF_alloc_pd_avs_prep */,\r
- THHUL_pdm_alloc_pd_done /* HHULIF_alloc_pd_done */,\r
- THHUL_pdm_free_pd_prep /* HHULIF_free_pd_prep */,\r
- THHUL_pdm_free_pd_done /* HHULIF_free_pd_done */,\r
- THHUL_mwm_alloc_mw /* HHULIF_alloc_mw */,\r
- THHUL_mwm_bind_mw /* HHULIF_bind_mw */,\r
- THHUL_mwm_free_mw /* HHULIF_free_mw */,\r
- THHUL_pdm_create_ud_av /* HHULIF_create_ud_av */,\r
- THHUL_pdm_modify_ud_av /* HHULIF_modify_ud_av */,\r
- THHUL_pdm_query_ud_av /* HHULIF_query_ud_av */,\r
- THHUL_pdm_destroy_ud_av /* HHULIF_destroy_ud_av */,\r
- THHUL_cqm_create_cq_prep /* HHULIF_create_cq_prep */,\r
- THHUL_cqm_create_cq_done /* HHULIF_create_cq_done */,\r
- THHUL_cqm_resize_cq_prep /* HHULIF_resize_cq_prep */,\r
- THHUL_cqm_resize_cq_done /* HHULIF_resize_cq_done */,\r
- NULL /* HHULIF_poll4cqe */,\r
- NULL /* HHULIF_poll_and_rearm_cq */, \r
- THHUL_cqm_peek_cq /* HHULIF_peek_cq */,\r
- THHUL_cqm_req_comp_notif /* HHULIF_req_comp_notif */,\r
- THHUL_cqm_req_ncomp_notif /* HHULIF_req_ncomp_notif */,\r
- THHUL_cqm_destroy_cq_done /* HHULIF_destroy_cq_done */,\r
- THHUL_qpm_create_qp_prep /* HHULIF_create_qp_prep */,\r
- THHUL_qpm_special_qp_prep /* HHULIF_special_qp_prep */,\r
- THHUL_qpm_create_qp_done /* HHULIF_create_qp_done */,\r
- THHUL_qpm_modify_qp_done /* HHULIF_modify_qp_done */,\r
- THHUL_qpm_post_send_req /* HHULIF_post_send_req */,\r
-#ifndef WIN32\r
- THHUL_qpm_post_send_req2 /* HHULIF_post_send_req2 */, \r
-#else\r
- NULL,\r
-#endif\r
- THHUL_qpm_post_inline_send_req /* HHULIF_post_inline_send_req */,\r
- THHUL_qpm_post_send_reqs /* HHULIF_post_send_reqs */,\r
- THHUL_qpm_post_gsi_send_req /* HHULIF_post_gsi_send_req */,\r
- THHUL_qpm_post_recv_req /* HHULIF_post_recv_req */,\r
-#ifndef WIN32\r
- THHUL_qpm_post_recv_req2 /* HHULIF_post_recv_req */, \r
-#else\r
- NULL,\r
-#endif\r
- THHUL_qpm_post_recv_reqs /* HHULIF_post_recv_reqs */,\r
- THHUL_qpm_destroy_qp_done /* HHULIF_destroy_qp_done */,\r
- THHUL_srqm_create_srq_prep/* HHULIF_create_srq_prep */,\r
- THHUL_srqm_create_srq_done/* HHULIF_create_srq_done */,\r
- THHUL_srqm_modify_srq_prep/* HHULIF_modify_srq_prep */,\r
- THHUL_srqm_modify_srq_done/* HHULIF_modify_srq_done */,\r
- THHUL_srqm_destroy_srq_done/* HHULIF_destroy_srq_done */,\r
- THHUL_srqm_post_recv_reqs /* HHULIF_post_srq */ \r
-};\r
-\r
-/* Private functions prototypes */\r
-static HH_ret_t alloc_hob_context(\r
- THHUL_hob_t *new_hob_p, \r
- THH_hca_ul_resources_t *hca_ul_resources_p\r
-);\r
-\r
-\r
-/**********************************************************************************************\r
- * Public API Functions (defined in thhul_hob.h)\r
- **********************************************************************************************/\r
-\r
-HH_ret_t THHUL_hob_create(\r
- /*IN*/ void/*THH_hca_ul_resources_t*/ *hca_ul_resources_p,\r
- /*IN*/ u_int32_t device_id,\r
- /*OUT*/ HHUL_hca_hndl_t *hca_p \r
-)\r
-{\r
- THHUL_hob_t new_hob;\r
- HH_ret_t rc;\r
-\r
- if (hca_ul_resources_p == NULL) {\r
- MTL_ERROR1("THHUL_hob_create: NULL hca_ul_resources_p.\n");\r
- return HH_EINVAL;\r
- }\r
-\r
- /* Allocate associated memory resources and included objects */\r
- rc= alloc_hob_context(&new_hob,(THH_hca_ul_resources_t*)hca_ul_resources_p);\r
- if (rc != HH_OK) return rc;\r
-\r
- /* Fill the HHUL_hca_dev_t structure */\r
- new_hob->hhul_hca.hh_hndl= ((THH_hca_ul_resources_t*)hca_ul_resources_p)->hh_hca_hndl;\r
- new_hob->hhul_hca.dev_desc= "InfiniHost(Tavor)";\r
- new_hob->hhul_hca.vendor_id= MT_MELLANOX_IEEE_VENDOR_ID;\r
- new_hob->hhul_hca.dev_id= device_id; \r
- \r
- new_hob->hhul_hca.hw_ver= ((THH_hca_ul_resources_t*)hca_ul_resources_p)->version.hw_ver;\r
- new_hob->hhul_hca.fw_ver= \r
- ((THH_hca_ul_resources_t*)hca_ul_resources_p)->version.fw_ver_major; \r
- new_hob->hhul_hca.fw_ver= (new_hob->hhul_hca.fw_ver << 16) |\r
- ((THH_hca_ul_resources_t*)hca_ul_resources_p)->version.fw_ver_minor; \r
- new_hob->hhul_hca.fw_ver= (new_hob->hhul_hca.fw_ver << 16) |\r
- ((THH_hca_ul_resources_t*)hca_ul_resources_p)->version.fw_ver_subminor; \r
- new_hob->hhul_hca.if_ops= &thhul_ops;\r
- new_hob->hhul_hca.hca_ul_resources_sz= sizeof(THH_hca_ul_resources_t);\r
- new_hob->hhul_hca.pd_ul_resources_sz= sizeof(THH_pd_ul_resources_t);\r
- new_hob->hhul_hca.cq_ul_resources_sz= sizeof(THH_cq_ul_resources_t);\r
- new_hob->hhul_hca.srq_ul_resources_sz= sizeof(THH_srq_ul_resources_t);\r
- new_hob->hhul_hca.qp_ul_resources_sz= sizeof(THH_qp_ul_resources_t);\r
- /* Get a copy of allocated resources */\r
- memcpy(&(new_hob->ul_res),hca_ul_resources_p,sizeof(THH_hca_ul_resources_t));\r
- new_hob->hhul_hca.hca_ul_resources_p= &(new_hob->ul_res);\r
- \r
- new_hob->hhul_hca.device= new_hob; /* Connect to new THHUL_hob */\r
- \r
- /* Return allocated HHUL device context */\r
- *hca_p= &(new_hob->hhul_hca);\r
- \r
- return HH_OK;\r
-}\r
-\r
-\r
-HH_ret_t THHUL_hob_destroy(/*IN*/ HHUL_hca_hndl_t hca)\r
-{\r
- THHUL_hob_t hob= GET_HOB(hca);\r
-\r
- if (hob == NULL) return HH_EINVAL; /* Invalid handle */\r
-\r
- THHUL_mwm_destroy(hob->mwm);\r
- THHUL_qpm_destroy(hob->qpm);\r
- THHUL_srqm_destroy(hob->srqm);\r
- THHUL_pdm_destroy(hob->pdm);\r
- THHUL_cqm_destroy(hob->cqm);\r
- THH_uar_destroy(hob->uar);\r
- FREE(hob);\r
- return HH_OK;\r
-}\r
-\r
-\r
-HH_ret_t THHUL_hob_query_version(\r
- /*IN*/ THHUL_hob_t hob,\r
- /*OUT*/ THH_ver_info_t *version_p \r
-)\r
-{\r
- if ((hob == NULL) || (version_p == NULL)) return HH_EINVAL; /* Invalid handle/pointer */\r
- memcpy(version_p,&(hob->ul_res.version),sizeof(THH_ver_info_t));\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THHUL_hob_get_hca_ul_handle\r
-(\r
- /*IN*/ THHUL_hob_t hob,\r
- /*OUT*/ HHUL_hca_hndl_t *hca_ul_p\r
-)\r
-{\r
- if ((hob == NULL) || (hca_ul_p == NULL)){ \r
- return HH_EINVAL; /* Invalid handle/pointer */\r
- }\r
- \r
- *hca_ul_p = &hob->hhul_hca;\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THHUL_hob_get_hca_ul_res_handle(\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*OUT*/ HH_hca_hndl_t *hca_ul_p)\r
-{\r
- THHUL_hob_t hob= (THHUL_hob_t)(hca->device);\r
-\r
- if ((hob == NULL) || (hca_ul_p == NULL)) {\r
- MTL_ERROR1("%s Wrong parameters: hob = %p, hca_ul_p=%p\n", __func__, hob, hca_ul_p); \r
- return HH_EINVAL; /* Invalid handle/pointer */\r
- }\r
- *hca_ul_p = hob->ul_res.hh_hca_hndl;\r
- return HH_OK;\r
-}\r
-\r
-\r
-HH_ret_t THHUL_hob_get_hca_ul_res(\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*OUT*/ THH_hca_ul_resources_t *hca_ul_res_p\r
-)\r
-{\r
- THHUL_hob_t hob= (THHUL_hob_t)(hca->device);\r
- \r
- if ((hob == NULL) || (hca_ul_res_p == NULL)) {\r
- MTL_ERROR1("%s Wrong parameters: hob = %p, hca_ul_res_p=%p\n", __func__, hob, hca_ul_res_p); \r
- return HH_EINVAL; /* Invalid handle/pointer */\r
- }\r
- memcpy(hca_ul_res_p,&(hob->ul_res),sizeof(THH_hca_ul_resources_t));\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THHUL_hob_get_pdm(/*IN*/ HHUL_hca_hndl_t hca,\r
- /*OUT*/ THHUL_pdm_t *pdm_p)\r
-{\r
- THHUL_hob_t hob= (THHUL_hob_t)(hca->device);\r
-\r
- if ((hob == NULL) || (pdm_p == NULL)) return HH_EINVAL; /* Invalid handle/pointer */\r
- *pdm_p= hob->pdm;\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THHUL_hob_get_cqm (/*IN*/ HHUL_hca_hndl_t hca,\r
- /*OUT*/ THHUL_cqm_t *cqm_p)\r
-{\r
- THHUL_hob_t hob= (THHUL_hob_t)(hca->device);\r
- \r
- if ((hob == NULL) || (cqm_p == NULL)) return HH_EINVAL; /* Invalid handle/pointer */\r
- *cqm_p= hob->cqm;\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THHUL_hob_get_qpm (/*IN*/ HHUL_hca_hndl_t hca, \r
- /*OUT*/ THHUL_qpm_t *qpm_p)\r
-{\r
- THHUL_hob_t hob= (THHUL_hob_t)(hca->device);\r
- \r
- if ((hob == NULL) || (qpm_p == NULL)) return HH_EINVAL; /* Invalid handle/pointer */\r
- *qpm_p= hob->qpm;\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THHUL_hob_get_srqm (/*IN*/ HHUL_hca_hndl_t hca, \r
- /*OUT*/ THHUL_srqm_t *srqm_p)\r
-{\r
- THHUL_hob_t hob= (THHUL_hob_t)(hca->device);\r
- \r
- if ((hob == NULL) || (srqm_p == NULL)) return HH_EINVAL; /* Invalid handle/pointer */\r
- *srqm_p= hob->srqm;\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THHUL_hob_get_uar (/*IN*/ HHUL_hca_hndl_t hca, \r
- /*OUT*/ THH_uar_t *uar_p)\r
-{\r
- THHUL_hob_t hob= (THHUL_hob_t)(hca->device);\r
- \r
- if ((hob == NULL) || (uar_p == NULL)) return HH_EINVAL; /* Invalid handle/pointer */\r
- *uar_p= hob->uar;\r
- return HH_OK;\r
-}\r
-\r
-\r
-HH_ret_t THHUL_hob_get_mwm (\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*OUT*/ THHUL_mwm_t *mwm_p\r
-)\r
-{\r
- THHUL_hob_t hob= (THHUL_hob_t)(hca->device);\r
- \r
- if ((hob == NULL) || (mwm_p == NULL)) return HH_EINVAL; /* Invalid handle/pointer */\r
- *mwm_p= hob->mwm;\r
- return HH_OK;\r
-}\r
-\r
-\r
-HH_ret_t THHUL_hob_is_priv_ud_av(\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*OUT*/ MT_bool *is_priv_ud_av_p\r
-)\r
-{\r
- THHUL_hob_t hob= (THHUL_hob_t)(hca->device);\r
- \r
- if ((hob == NULL) || (is_priv_ud_av_p == NULL)) return HH_EINVAL; /* Invalid handle/pointer */\r
- *is_priv_ud_av_p= hob->ul_res.priv_ud_av;\r
- return HH_OK;\r
-}\r
-\r
-\r
-/**********************************************************************************************\r
- * Private Functions\r
- **********************************************************************************************/\r
-\r
-\r
-/*******************************************************\r
- * Function: alloc_hob_context\r
- *\r
- * Description: Allocate the THHUL_hob object memory and included objects\r
- *\r
- * Arguments: new_hob_p - Object to allocate for\r
- * hca_ul_resources_p - As given to THHUL_hob_create()\r
- *\r
- * Returns: HH_OK\r
- * HH_EAGAIN\r
- *******************************************************/\r
-static HH_ret_t alloc_hob_context(\r
- THHUL_hob_t *new_hob_p, \r
- THH_hca_ul_resources_t *hca_ul_resources_p\r
-)\r
-{\r
- HH_ret_t rc;\r
-\r
- /* Allocate THHUL_hob own context */\r
- *new_hob_p= (THHUL_hob_t)MALLOC(sizeof(struct THHUL_hob_st));\r
- if (*new_hob_p == NULL) return HH_EAGAIN;\r
-\r
- /* Create included objects */\r
- rc= THH_uar_create(\r
- &(hca_ul_resources_p->version),\r
- hca_ul_resources_p->uar_index,\r
- (void*)(hca_ul_resources_p->uar_map),\r
- &((*new_hob_p)->uar));\r
- if (rc != HH_OK) {\r
- MTL_ERROR1("THHUL_hob_create: Failed creating THHUL_uar (err=%d).\n",rc);\r
- goto failed_uar;\r
- }\r
-\r
- rc= THHUL_pdm_create((*new_hob_p),hca_ul_resources_p->priv_ud_av,&((*new_hob_p)->pdm));\r
- if (rc != HH_OK) {\r
- MTL_ERROR1("THHUL_hob_create: Failed creating THHUL_pdm (%d=%s).\n", rc, HH_strerror_sym(rc));\r
- goto failed_pdm;\r
- }\r
-\r
- rc= THHUL_cqm_create((*new_hob_p),&((*new_hob_p)->cqm));\r
- if (rc != HH_OK) {\r
- MTL_ERROR1("THHUL_hob_create: Failed creating THHUL_cqm (%d=%s).\n", rc, HH_strerror_sym(rc));\r
- goto failed_cqm;\r
- }\r
-\r
- rc= THHUL_srqm_create((*new_hob_p),&((*new_hob_p)->srqm));\r
- if (rc != HH_OK) {\r
- MTL_ERROR1("THHUL_hob_create: Failed creating THHUL_srqm (%d=%s).\n", rc, HH_strerror_sym(rc));\r
- goto failed_srqm;\r
- }\r
- \r
- rc= THHUL_qpm_create((*new_hob_p), (*new_hob_p)->srqm, &((*new_hob_p)->qpm));\r
- if (rc != HH_OK) {\r
- MTL_ERROR1("THHUL_hob_create: Failed creating THHUL_qpm (%d=%s).\n", rc, HH_strerror_sym(rc));\r
- goto failed_qpm;\r
- }\r
-\r
- rc= THHUL_mwm_create((*new_hob_p),hca_ul_resources_p->log2_mpt_size,&((*new_hob_p)->mwm));\r
- if (rc != HH_OK) {\r
- MTL_ERROR1("THHUL_hob_create: Failed creating THHUL_mwm (%d=%s).\n", rc, HH_strerror_sym(rc));\r
- goto failed_mwm;\r
- }\r
-\r
- return HH_OK;\r
-\r
- /* Failure cleanup (error exit flow) */\r
- failed_mwm:\r
- THHUL_qpm_destroy((*new_hob_p)->qpm);\r
- failed_qpm:\r
- THHUL_srqm_destroy((*new_hob_p)->srqm);\r
- failed_srqm:\r
- THHUL_cqm_destroy((*new_hob_p)->cqm);\r
- failed_cqm:\r
- THHUL_pdm_destroy((*new_hob_p)->pdm);\r
- failed_pdm:\r
- THH_uar_destroy((*new_hob_p)->uar);\r
- failed_uar:\r
- FREE(*new_hob_p);\r
- return rc;\r
-}\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_THHUL_HOB_H\r
-#define H_THHUL_HOB_H\r
-\r
-#include <mtl_common.h>\r
-#include <hhul.h>\r
-#include <thhul.h>\r
-\r
-\r
-DLL_API HH_ret_t THHUL_hob_create(\r
- /*IN*/ void/*THH_hca_ul_resources_t*/ *hca_ul_resources_p, \r
- /*IN*/ u_int32_t device_id,\r
- /*OUT*/ HHUL_hca_hndl_t *hca_p \r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_hob_destroy(/*IN*/ HHUL_hca_hndl_t hca);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_hob_query_version(\r
- /*IN*/ THHUL_hob_t hob, \r
- /*OUT*/ THH_ver_info_t *version_p \r
-);\r
-\r
-DLL_API HH_ret_t THHUL_hob_get_hca_ul_handle(\r
- /*IN*/ THHUL_hob_t hob,\r
- /*OUT*/ HHUL_hca_hndl_t *hca_ul_p\r
-);\r
-\r
-DLL_API HH_ret_t THHUL_hob_get_hca_ul_res(\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*OUT*/ THH_hca_ul_resources_t *hca_ul_res_p\r
-);\r
-\r
-DLL_API HH_ret_t THHUL_hob_get_hca_ul_res_handle(\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*OUT*/ HH_hca_hndl_t *hca_ul_p\r
-);\r
-\r
-DLL_API HH_ret_t THHUL_hob_get_pdm(\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*OUT*/ THHUL_pdm_t *pdm_p\r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_hob_get_cqm (\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*OUT*/ THHUL_cqm_t *cqm_p\r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_hob_get_qpm (\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*OUT*/ THHUL_qpm_t *qpm_p\r
-);\r
-\r
-DLL_API HH_ret_t THHUL_hob_get_srqm (\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*OUT*/ THHUL_srqm_t *srqm_p\r
-);\r
-\r
-DLL_API HH_ret_t THHUL_hob_get_uar (\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*OUT*/ THH_uar_t *uar_p\r
-);\r
-\r
-DLL_API HH_ret_t THHUL_hob_get_mwm (\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*OUT*/ THHUL_mwm_t *mwm_p\r
-);\r
-\r
-DLL_API HH_ret_t THHUL_hob_is_priv_ud_av(\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*OUT*/ MT_bool *is_priv_ud_av_p\r
-);\r
-\r
-\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#define C_THHUL_MWM_C\r
-\r
-#include <hh.h>\r
-#include <hhul.h>\r
-#include <thhul_hob.h>\r
-#include <thhul_qpm.h>\r
-#include <thhul_mwm.h>\r
-\r
-typedef struct mwm_ul_ctx_st {\r
- /* TD: change the name.*/\r
- IB_rkey_t key;\r
- struct mwm_ul_ctx_st *next_p;\r
- struct mwm_ul_ctx_st *back_p;\r
-} mwm_ul_ctx;\r
-\r
-typedef struct THHUL_mwm_st {\r
- // TD: next member possibly redundant:\r
- u_int32_t log2_mpt_size;\r
- MOSAL_mutex_t mtx;\r
- mwm_ul_ctx *head_p;\r
-} tmwm_t;\r
-\r
-HH_ret_t THHUL_mwm_create\r
-( \r
- /*IN*/ THHUL_hob_t hob, \r
- /*IN*/ u_int32_t log2_mpt_size,\r
- /*OUT*/ THHUL_mwm_t *mwm_p \r
-) \r
-{ \r
- /*\r
- HH_ret_t rc;\r
- HHUL_hca_hndl_t hca;\r
- THH_hca_ul_resources_t hca_ul_res;\r
- */\r
- THHUL_mwm_t mwm;\r
- \r
- FUNC_IN;\r
- \r
- mwm = TMALLOC(tmwm_t);\r
-\r
- if( mwm == NULL )\r
- { \r
- MTL_ERROR1("%s mwm malloc failed\n", __func__);\r
- return HH_EAGAIN;\r
- }\r
-\r
- /* change to THHUL_hob_get_hca_ul_hob_handle()*/ \r
- /*\r
- if( (rc = THHUL_hob_get_hca_ul_handle(hob,&hca)) != HH_OK )\r
- {\r
- MTL_ERROR1("%sTHHUL_hob_get_hca_ul_handle() failed, ret=%d\n", __func__,rc); \r
- return rc;\r
- }\r
- \r
- if( (rc = THHUL_hob_get_hca_ul_res(hca,&hca_ul_res)) != HH_OK )\r
- {\r
- MTL_ERROR1("%sTHHUL_hob_get_hca_ul_res() failed, ret=%d\n", __func__,rc); \r
- return rc;\r
- }\r
- */\r
- mwm->log2_mpt_size = log2_mpt_size;\r
- mwm->head_p = NULL;\r
- MOSAL_mutex_init(&(mwm->mtx));\r
- \r
- *mwm_p = mwm;\r
- FUNC_OUT;\r
- \r
- return HH_OK;\r
-}\r
-\r
-\r
-HH_ret_t THHUL_mwm_destroy\r
-( \r
- /*IN*/ THHUL_mwm_t mwm \r
-) \r
-{ \r
- mwm_ul_ctx *cur_mw_p;\r
- \r
- while (mwm->head_p) { \r
- cur_mw_p= mwm->head_p;\r
- mwm->head_p = cur_mw_p->next_p;\r
- FREE(cur_mw_p);\r
- }\r
-\r
- MOSAL_mutex_free(&(mwm->mtx));\r
- FREE(mwm);\r
- MT_RETURN(HH_OK); \r
-}\r
-\r
-\r
-HH_ret_t THHUL_mwm_alloc_mw\r
-(\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ IB_rkey_t initial_rkey,\r
- /*OUT*/ HHUL_mw_hndl_t* mw_p\r
-) \r
-{ \r
- THHUL_mwm_t mwm;\r
-#ifdef THHUL_MWM_DEBUG_LIST\r
- mwm_ul_ctx *cur_mw_p;\r
-#endif\r
-\r
- FUNC_IN;\r
- \r
- if( ( THHUL_hob_get_mwm(hca,&mwm) != HH_OK ) || ( mwm == NULL ) )\r
- {\r
- MTL_ERROR1(MT_FLFMT("Error while retrieving mwm handle.\n"));\r
- return HH_EINVAL;\r
- }\r
-\r
- *mw_p = MALLOC(sizeof(mwm_ul_ctx));\r
- if( mw_p == NULL ) {\r
- MTL_ERROR1("%sallocation failed.\n", __func__);\r
- return HH_EAGAIN;\r
- }\r
-\r
- if (MOSAL_mutex_acq(&mwm->mtx,TRUE) != MT_OK) {\r
- FREE(mw_p);\r
- return HH_EINTR;\r
- }\r
- \r
- if( mwm->head_p )\r
- mwm->head_p->back_p = (struct mwm_ul_ctx_st *)*mw_p;\r
- ((mwm_ul_ctx *) *(mw_p))->next_p = mwm->head_p;\r
- ((mwm_ul_ctx *) *(mw_p))->back_p = NULL;\r
- ((mwm_ul_ctx *) *(mw_p))->key = initial_rkey;\r
-\r
- mwm->head_p = (struct mwm_ul_ctx_st *)*mw_p;\r
- \r
-#ifdef THHUL_MWM_DEBUG_LIST\r
- MTL_DEBUG5(MT_FLFMT("List check/dump:"));\r
- cur_mw_p= mwm->head_p;\r
- while (cur_mw_p) { /* Verify list consistancy */\r
- MTL_DEBUG5(MT_FLFMT("Rkey=0x%X"),cur_mw_p->key);\r
- /* verify next point back to current */\r
- if ((cur_mw_p->next_p) && (cur_mw_p->next_p->back_p != cur_mw_p)) { \r
- MTL_ERROR1(MT_FLFMT("Linked list is found to be inconsistant"));\r
- MOSAL_mutex_rel(&mwm->mtx);\r
- return HH_EINVAL;\r
- }\r
- cur_mw_p= cur_mw_p->next_p;\r
- }\r
- cur_mw_p= mwm->head_p;\r
- while (cur_mw_p) { /* Scan list to assure given handle is in the list */\r
- if (cur_mw_p == *mw_p) break;\r
- cur_mw_p= cur_mw_p->next_p;\r
- }\r
- if (cur_mw_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("New memory windows is not found in the list)"));\r
- MOSAL_mutex_rel(&mwm->mtx);\r
- return HH_EINVAL;\r
- }\r
-#endif\r
- \r
- MOSAL_mutex_rel(&mwm->mtx);\r
-\r
- FUNC_OUT; \r
- \r
- return HH_OK;; \r
-}\r
-\r
-HH_ret_t THHUL_mwm_bind_mw\r
-(\r
- /*IN*/ HHUL_hca_hndl_t hhul_hndl,\r
- /*IN*/ HHUL_mw_hndl_t mw,\r
- /*IN*/ HHUL_mw_bind_t* bind_prop_p,\r
- /*OUT*/ IB_rkey_t* bind_rkey_p\r
-) \r
-{ \r
- u_int32_t rc,new_key;\r
- THHUL_mwm_t mwm;\r
-\r
- FUNC_IN;\r
-\r
- MTL_DEBUG1("%s - dump of bind req:\n", __func__);\r
- MTL_DEBUG1("{\n");\r
- MTL_DEBUG1("init r_key: 0x%x.\n",((mwm_ul_ctx *) mw)->key);\r
- MTL_DEBUG1("acl: 0x%x.\n",bind_prop_p->acl);\r
- MTL_DEBUG1("comp_type: 0x%x.\n",bind_prop_p->comp_type);\r
- MTL_DEBUG1("id: 0x%x.\n",(u_int32_t) bind_prop_p->id);\r
- MTL_DEBUG1("lkey: 0x%x.\n",bind_prop_p->mr_lkey);\r
- MTL_DEBUG1("qp: " MT_ULONG_PTR_FMT ".\n",(MT_ulong_ptr_t) bind_prop_p->qp);\r
- MTL_DEBUG1("start: 0x%x:%x.\n",(u_int32_t) (bind_prop_p->start >> 32),(u_int32_t) bind_prop_p->start);\r
- MTL_DEBUG1("size: 0x%x:%x.\n",(u_int32_t) (bind_prop_p->size >> 32),(u_int32_t) bind_prop_p->size);\r
- MTL_DEBUG1("}\n");\r
-\r
- if( ( THHUL_hob_get_mwm(hhul_hndl,&mwm) != HH_OK ) || ( mwm == NULL ) )\r
- {\r
- MTL_ERROR1(MT_FLFMT("Error while retrieving mwm handle.\n"));\r
- return HH_EINVAL;\r
- }\r
-\r
- // req to bind a window to zero len is in fact an unbind req.\r
- // if unbunding, window e_key remains the same.\r
- // if binding, new r_key tag is the previous tag incremented by 1:\r
- new_key = ((mwm_ul_ctx *) mw)->key;\r
- /* TD: conventions */\r
- if( bind_prop_p->size > 0 ) { \r
- new_key += (1 << mwm->log2_mpt_size);\r
- }\r
- \r
- if( (rc = THHUL_qpm_post_bind_req(bind_prop_p,new_key)) != HH_OK ) {\r
- MTL_ERROR1("%s failed to post bind descriptor.\n", __func__);\r
- return rc;\r
- }\r
-\r
- ((mwm_ul_ctx *) mw)->key = new_key;\r
- *bind_rkey_p = new_key;\r
- \r
- FUNC_OUT;\r
- \r
- return HH_OK; \r
-}\r
-\r
-\r
-HH_ret_t THHUL_mwm_free_mw\r
-(\r
- /*IN*/ HHUL_hca_hndl_t hhul_hndl,\r
- /*IN*/ HHUL_mw_hndl_t mw\r
-) \r
-{ \r
- THHUL_mwm_t mwm;\r
-#ifdef THHUL_MWM_DEBUG_LIST\r
- mwm_ul_ctx *cur_mw_p;\r
-#endif\r
-\r
- FUNC_IN;\r
- \r
- if( ( THHUL_hob_get_mwm(hhul_hndl,&mwm) != HH_OK ) || ( mwm == NULL ) )\r
- {\r
- MTL_ERROR1(MT_FLFMT("Error while retrieving mwm handle.\n"));\r
- return HH_EINVAL;\r
- }\r
- \r
- MOSAL_mutex_acq_ui(&mwm->mtx);\r
- \r
-#ifdef THHUL_MWM_DEBUG_LIST\r
- MTL_DEBUG5(MT_FLFMT("List check/dump (removal of Rkey=0x%X):"),((mwm_ul_ctx*)mw)->key);\r
- cur_mw_p= mwm->head_p;\r
- while (cur_mw_p) { /* Verify list consistancy */\r
- MTL_DEBUG5(MT_FLFMT("Rkey=0x%X"),cur_mw_p->key);\r
- /* verify next point back to current */\r
- if ((cur_mw_p->next_p) && (cur_mw_p->next_p->back_p != cur_mw_p)) { \r
- MTL_ERROR1(MT_FLFMT("Linked list is found to be inconsistant"));\r
- MOSAL_mutex_rel(&mwm->mtx);\r
- return HH_EINVAL;\r
- }\r
- cur_mw_p= cur_mw_p->next_p;\r
- }\r
- cur_mw_p= mwm->head_p;\r
- while (cur_mw_p) { /* Scan list to assure given handle is in the list */\r
- if (cur_mw_p == mw) break;\r
- cur_mw_p= cur_mw_p->next_p;\r
- }\r
- if (cur_mw_p == NULL) {\r
- MTL_ERROR1(MT_FLFMT("Given memory window handle %p is unknown (not in list)"),\r
- (mwm_ul_ctx *) mw);\r
- MOSAL_mutex_rel(&mwm->mtx);\r
- return HH_EINVAL;\r
- }\r
-#endif\r
- // window list is empty:\r
- if( mwm->head_p == NULL )\r
- {\r
- MOSAL_mutex_rel(&mwm->mtx);\r
- return HH_EINVAL;\r
- }\r
-\r
- // single window in the list:\r
- if( mwm->head_p->next_p == NULL )\r
- {\r
- mwm->head_p = NULL;\r
- goto mwm_free_mw_exit;\r
- }\r
-\r
- // unlink from previous entry:\r
- if( ((mwm_ul_ctx *) mw)->back_p )\r
- {\r
- ((mwm_ul_ctx *) mw)->back_p->next_p = ((mwm_ul_ctx *) mw)->next_p;\r
- } else { /* Removing first - Make next (if any) the first */\r
- mwm->head_p= ((mwm_ul_ctx *) mw)->next_p;\r
- }\r
-\r
- // unlink from next entry:\r
- if( ((mwm_ul_ctx *) mw)->next_p )\r
- {\r
- ((mwm_ul_ctx *) mw)->next_p->back_p = ((mwm_ul_ctx *) mw)->back_p;\r
- }\r
-\r
-mwm_free_mw_exit:\r
- MOSAL_mutex_rel(&mwm->mtx);\r
- FREE(mw);\r
- \r
- FUNC_OUT;\r
- \r
- return HH_OK; \r
-}\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_THHUL_MWM_H\r
-#define H_THHUL_MWM_H\r
-\r
-#include <mtl_common.h>\r
-#include <hhul.h>\r
-#include <thhul.h>\r
-\r
-\r
-DLL_API HH_ret_t THHUL_mwm_create( \r
- /*IN*/ THHUL_hob_t hob,\r
- /*IN*/ u_int32_t log2_mpt_size,\r
- /*OUT*/ THHUL_mwm_t *mwm_p \r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_mwm_destroy( \r
- /*IN*/ THHUL_mwm_t mwm \r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_mwm_alloc_mw(\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ IB_rkey_t initial_rkey,\r
- /*OUT*/ HHUL_mw_hndl_t* mw_p\r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_mwm_bind_mw(\r
- /*IN*/ HHUL_hca_hndl_t hhul_hndl,\r
- /*IN*/ HHUL_mw_hndl_t mw,\r
- /*IN*/ HHUL_mw_bind_t* bind_prop_p,\r
- /*OUT*/ IB_rkey_t* bind_rkey_p\r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_mwm_free_mw(\r
- /*IN*/ HHUL_hca_hndl_t hhul_hndl,\r
- /*IN*/ HHUL_mw_hndl_t mw\r
-);\r
-\r
-#endif /* H_THHUL_QPM_H */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "thhul_pdm_priv.h"\r
-\r
-#define MT_FORK_SUPPORT\r
-\r
-HH_ret_t THHUL_pdm_create (\r
- THHUL_hob_t hob, \r
- MT_bool priv_ud_av, \r
- THHUL_pdm_t *pdm_p )\r
-{\r
- THHUL_pdm_t new_pdm_obj;\r
- HH_ret_t ret;\r
- VIP_common_ret_t vret;\r
- /* create new pdm object */\r
- new_pdm_obj = TMALLOC(struct THHUL_pdm_st);\r
- if (!new_pdm_obj) {\r
- return HH_EINVAL;\r
- }\r
- \r
- memset(new_pdm_obj, 0, sizeof(struct THHUL_pdm_st));\r
-\r
- ret = THHUL_hob_query_version( hob, &(new_pdm_obj->version)); \r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THHUL_pdm_create: ERROR (%d) : could not get version info\n", ret);\r
- FREE(new_pdm_obj);\r
- return HH_EINVAL;\r
- }\r
-\r
- new_pdm_obj->priv_ud_av = priv_ud_av;\r
- vret = VIP_array_create(THHUL_PDM_INITIAL_NUM_PDS,&(new_pdm_obj->pd_array));\r
- if (vret != VIP_OK) {\r
- MTL_ERROR1("THHUL_pdm_create: ERROR (%d) : could not create PD array\n", vret);\r
- FREE(new_pdm_obj);\r
- return HH_EAGAIN;\r
- }\r
-\r
- *pdm_p = new_pdm_obj;\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THHUL_pdm_destroy ( THHUL_pdm_t pdm)\r
-{\r
- THHUL_pd_t *ul_pd;\r
- HH_ret_t ret;\r
- THH_udavm_t udavm;\r
- VIP_common_ret_t vret;\r
- VIP_array_handle_t pd_h;\r
-\r
-\r
- VIP_ARRAY_FOREACH(pdm->pd_array,vret,pd_h,(VIP_array_obj_t*)&ul_pd)\r
- {\r
- udavm = ul_pd->udavm;\r
- /* For non-privileged UDAVs, destroy the UDAV user-level object allocated for this PD */\r
- if (!(pdm->priv_ud_av)) {\r
- /*udavm can legally be null if THHUL_pdm_alloc_pd_done was not called, due to \r
- * failure of THH_pdm_alloc_pd \r
- */\r
- if (udavm != NULL) {\r
- ret = THH_udavm_destroy(udavm);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THHUL_pdm_free_pd_done: ERROR (%d) : Could not destroy associated UDAV object\n", ret);\r
- /* continue, to free up the ul_pd anyway., and report successful 'free' */\r
- }\r
- }\r
- \r
- /* If udav was not allocated in DDR, free the allocated memory here */\r
- if (ul_pd->udav_nonddr_table != (MT_virt_addr_t) 0) {\r
- MOSAL_pci_virt_free_consistent((void *)ul_pd->udav_nonddr_table, ul_pd->uadv_nonddr_table_alloc_size);\r
- ul_pd->udav_nonddr_table = (MT_virt_addr_t) 0;\r
- ul_pd->udav_nonddr_table_aligned = (MT_virt_addr_t) 0;\r
- ul_pd->uadv_nonddr_table_alloc_size = 0;\r
- }\r
- }\r
- ul_pd->valid = FALSE; /* just in case OS does not detect heap errors, and does not zero entries */\r
- FREE(ul_pd);\r
- }\r
- \r
- VIP_array_destroy(pdm->pd_array,NULL);\r
- FREE(pdm);\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THHUL_pdm_alloc_pd_avs_prep (\r
- HHUL_hca_hndl_t hca, \r
- u_int32_t max_num_avs,\r
- HH_pdm_pd_flags_t pd_flags,\r
- HHUL_pd_hndl_t *pd_p, \r
- void *pd_ul_resources_p )\r
-{\r
- HH_ret_t ret;\r
- THHUL_pdm_t pdm;\r
- THHUL_pd_t *new_pd_p;\r
- THH_pd_ul_resources_t *pd_ul_res = (THH_pd_ul_resources_t *)pd_ul_resources_p;\r
- MT_size_t ud_av_table_sz = 0;\r
- VIP_common_ret_t vret;\r
- VIP_array_handle_t local_pd_hndl;\r
-\r
- ret = THHUL_hob_get_pdm(hca, &pdm);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THHUL_pdm_alloc_pd_avs_prep: ERROR (%d) : PDM object has not yet been created\n", ret);\r
- return HH_EINVAL;\r
- }\r
-\r
- new_pd_p = TMALLOC(THHUL_pd_t);\r
- memset(new_pd_p, 0, sizeof(THHUL_pd_t));\r
- memset(pd_ul_res, 0, sizeof(THH_pd_ul_resources_t));\r
-\r
- /* first, see if need to create a UDAV table (non-priv mode) */\r
- if (!pdm->priv_ud_av) {\r
-\r
- if (max_num_avs == 0) {\r
- MTL_ERROR1("THHUL_pdm_alloc_pd_avs_prep: max_num_avs requested cannot be zero.\n"); \r
- FREE(new_pd_p);\r
- return HH_EINVAL;\r
- }\r
- \r
- if (max_num_avs == EVAPI_DEFAULT_AVS_PER_PD) {\r
- max_num_avs = THHUL_PDM_MAX_UL_UDAV_PER_PD;\r
- MTL_DEBUG4("THHUL_pdm_alloc_pd_avs_prep: using default AVs per PD (=%u)\n", max_num_avs); \r
- }\r
- /* guarantee that table size is a multiple of page size. */\r
- ud_av_table_sz = max_num_avs * (sizeof(struct tavorprm_ud_address_vector_st) / 8);\r
-#if !defined(__KERNEL__) && defined(MT_FORK_SUPPORT)\r
- /* Add 1 page for page alignment + one page to cover last page */\r
- new_pd_p->uadv_nonddr_table_alloc_size = \r
- MT_UP_ALIGNX_SIZE(ud_av_table_sz, MOSAL_SYS_PAGE_SHIFT) + MOSAL_SYS_PAGE_SIZE - 1;\r
-#else \r
- /* malloc an extra udav entry to use for table-start alignment purposes */\r
- new_pd_p->uadv_nonddr_table_alloc_size = ud_av_table_sz + \r
- (1<<ceil_log2(sizeof(struct tavorprm_ud_address_vector_st) / 8));\r
-#endif\r
- \r
- MTL_DEBUG4("THHUL_pdm_alloc_pd_avs_prep: ud_av_table_sz = "SIZE_T_FMT", pd_flags=0x%x\n", \r
- ud_av_table_sz, pd_flags); \r
- new_pd_p->udav_nonddr_table = \r
- (MT_virt_addr_t) MOSAL_pci_virt_alloc_consistent(new_pd_p->uadv_nonddr_table_alloc_size,\r
- ceil_log2(sizeof(struct tavorprm_ud_address_vector_st) / 8) );\r
-\r
- if (new_pd_p->udav_nonddr_table == VA_NULL ) {\r
- MTL_ERROR1("THHUL_pdm_alloc_pd_avs_prep: ERROR : Could not Vmalloc UDAV table\n");\r
- ret = HH_ENOMEM;\r
- goto thh_pdm_udavm_create_err;\r
- }\r
- memset((void *)new_pd_p->udav_nonddr_table, 0, new_pd_p->uadv_nonddr_table_alloc_size);\r
- \r
-#if !defined(__KERNEL__) && defined(MT_FORK_SUPPORT)\r
- new_pd_p->udav_nonddr_table_aligned = /* Align to page start */\r
- MT_UP_ALIGNX_VIRT((new_pd_p->udav_nonddr_table), MOSAL_SYS_PAGE_SHIFT);\r
-#else\r
- /* now, align the buffer to the entry size */\r
- new_pd_p->udav_nonddr_table_aligned = \r
- MT_UP_ALIGNX_VIRT((new_pd_p->udav_nonddr_table), \r
- ceil_log2((sizeof(struct tavorprm_ud_address_vector_st) / 8)));\r
-#endif\r
- }\r
-\r
- /* add to array */\r
- if ((vret=VIP_array_insert(pdm->pd_array, (VIP_array_obj_t)new_pd_p, &local_pd_hndl)) != VIP_OK) {\r
- MTL_ERROR1("THHUL_pdm_alloc_pd_avs_prep: ERROR (%d) : Insertion failure.\n", vret);\r
- if (!pdm->priv_ud_av) {\r
- MOSAL_pci_virt_free_consistent((void *)new_pd_p->udav_nonddr_table, new_pd_p->uadv_nonddr_table_alloc_size);\r
- }\r
- FREE(new_pd_p);\r
- return HH_EAGAIN;\r
- }\r
-\r
- pd_ul_res->udavm_buf = new_pd_p->udav_nonddr_table_aligned;\r
- pd_ul_res->udavm_buf_sz = ud_av_table_sz;\r
- pd_ul_res->pd_flags = pd_flags;\r
- /* do a free_pd_prep here so that if the kernel call to create-pd fails, we can call\r
- * HHUL_free_pd_done directly (without worrying about a free-prep step. The logic needs\r
- * to be that explicitly call HHUL_free_prep ONLY if we successfully called HHUL_alloc_done */\r
- ret = THHUL_pdm_free_pd_prep (hca,(HHUL_pd_hndl_t)local_pd_hndl, FALSE); \r
- if (ret != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: THHUL_pdm_free_pd_prep failure (%d:%s)"), \r
- __func__, ret, HH_strerror_sym(ret));\r
- goto thh_pdm_udavm_create_err;\r
- }\r
- *pd_p = new_pd_p->hhul_pd_hndl = (HHUL_pd_hndl_t)local_pd_hndl; /* return allocated PD handle */\r
- return HH_OK;\r
-\r
-thh_pdm_udavm_create_err:\r
- FREE(new_pd_p);\r
- return ret;\r
-\r
-}\r
-\r
-HH_ret_t THHUL_pdm_alloc_pd_prep (\r
- HHUL_hca_hndl_t hca, \r
- HHUL_pd_hndl_t *pd_p, \r
- void *pd_ul_resources_p )\r
-{\r
- return THHUL_pdm_alloc_pd_avs_prep(hca, 256, PD_NO_FLAGS, pd_p, pd_ul_resources_p);\r
-}\r
-\r
-\r
-HH_ret_t THHUL_pdm_alloc_pd_done (\r
- HHUL_hca_hndl_t hca, \r
- HHUL_pd_hndl_t hhul_pd, \r
- HH_pd_hndl_t hh_pd, \r
- void *pd_ul_resources_p )\r
-{\r
- HH_ret_t ret;\r
- THHUL_pdm_t pdm;\r
- THH_pd_ul_resources_t *pd_ul_res = (THH_pd_ul_resources_t *)pd_ul_resources_p;\r
- THHUL_pd_t *ul_pd;\r
- VIP_common_ret_t vret;\r
-\r
- MTL_DEBUG3("==> THHUL_pdm_alloc_pd_done\n");\r
-\r
- ret = THHUL_hob_get_pdm(hca, &pdm);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THHUL_pdm_alloc_pd_done: ERROR (%d) : PDM object has not yet been created\n", ret);\r
- return HH_EINVAL;\r
- }\r
-\r
- /* undo the erase prep performed at the end of alloc prep */\r
- ret = THHUL_pdm_free_pd_prep (hca, hhul_pd,TRUE );\r
- if (ret != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: THHUL_pdm_free_pd_prep UNDO failure (%d:%s)"), \r
- __func__, ret, HH_strerror_sym(ret));\r
- return ret;\r
- }\r
-\r
- if ((vret=VIP_array_find_hold(pdm->pd_array,(VIP_array_handle_t)hhul_pd,\r
- (VIP_array_obj_t *)&ul_pd)) != VIP_OK) {\r
- if (vret == VIP_EBUSY) { \r
- MTL_DEBUG4("THHUL_pdm_alloc_pd_done: PD object is busy\n");\r
- return HH_EBUSY;\r
- } else {\r
- MTL_ERROR1("THHUL_pdm_alloc_pd_done: ERROR (%d) : Could not find PD object\n", vret);\r
- return HH_EINVAL_PD_HNDL;\r
- }\r
- }\r
- ul_pd->hh_pd_hndl = hh_pd;\r
-\r
- if (!pdm->priv_ud_av) {\r
- if (pd_ul_res->udavm_buf != ul_pd->udav_nonddr_table_aligned) {\r
- MTL_DEBUG3("THHUL_pdm_alloc_pd_done. USING DDR MEMORY.udavm_buf="\r
- VIRT_ADDR_FMT", nonddr_table="VIRT_ADDR_FMT", extra=%d\n",\r
- pd_ul_res->udavm_buf, ul_pd->udav_nonddr_table,\r
- (int)(sizeof(struct tavorprm_ud_address_vector_st) / 8) );\r
- MOSAL_pci_virt_free_consistent((void *)ul_pd->udav_nonddr_table, ul_pd->uadv_nonddr_table_alloc_size);\r
- ul_pd->udav_nonddr_table = (MT_virt_addr_t) 0;\r
- ul_pd->udav_nonddr_table_aligned = (MT_virt_addr_t) 0;\r
- ul_pd->uadv_nonddr_table_alloc_size = 0;\r
- } else {\r
- MTL_DEBUG3("THHUL_pdm_alloc_pd_done. USING HOST MEMORY.udavm_buf (aligned) ="\r
- VIRT_ADDR_FMT", non-aligned nonddr_table="VIRT_ADDR_FMT"\n",\r
- pd_ul_res->udavm_buf, ul_pd->udav_nonddr_table);\r
- }\r
- ret = THH_udavm_create( &(pdm->version), pd_ul_res->udavm_buf_memkey,\r
- pd_ul_res->udavm_buf,\r
- pd_ul_res->udavm_buf_sz,\r
- (ul_pd->uadv_nonddr_table_alloc_size != 0),\r
- &(ul_pd->udavm),\r
- &(ul_pd->av_ddr_base),\r
- &(ul_pd->av_host_base));\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THHUL_pdm_alloc_pd_done: ERROR (%d) : Could not create UDAV manager object\n", ret);\r
- MTL_DEBUG4("<== THHUL_pdm_alloc_pd_done. ERROR\n");\r
- VIP_array_find_release(pdm->pd_array,hhul_pd);\r
- return ret;\r
- }\r
- }\r
- else {\r
- THH_hca_ul_resources_t hca_ul_res;\r
- ret = THHUL_hob_get_hca_ul_res(hca,&hca_ul_res);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THHUL_pdm_alloc_pd_done: ERROR (%d) : THHUL_hob_get_hca_ul_res failed\n", ret);\r
- VIP_array_find_release(pdm->pd_array,hhul_pd);\r
- return ret;\r
- } else {\r
- ul_pd->av_ddr_base = hca_ul_res.av_ddr_base;\r
- ul_pd->av_host_base = hca_ul_res.av_host_base;\r
- }\r
- }\r
- \r
-\r
- /* save the memory key in all cases, for use by THHUL_qpm */\r
- ul_pd->lkey = pd_ul_res->udavm_buf_memkey;\r
- ul_pd->valid = TRUE;\r
- VIP_array_find_release(pdm->pd_array,hhul_pd);\r
- MTL_DEBUG3("<== THHUL_pdm_alloc_pd_done\n");\r
- return HH_OK;\r
-}\r
-\r
-\r
-HH_ret_t THHUL_pdm_free_pd_prep (\r
- HHUL_hca_hndl_t hca, \r
- HHUL_pd_hndl_t hhul_pd,\r
- MT_bool undo_flag )\r
-{\r
- HH_ret_t ret;\r
- THHUL_pdm_t pdm;\r
- VIP_common_ret_t vret;\r
-\r
- ret = THHUL_hob_get_pdm(hca, &pdm);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THHUL_pdm_free_pd_prep: ERROR (%d) : PDM object has not yet been created\n", ret);\r
- return HH_EINVAL;\r
- }\r
-\r
- /* undoing a previous prep */\r
- if (undo_flag == TRUE) {\r
- if ((vret=VIP_array_erase_undo(pdm->pd_array,(VIP_array_handle_t)hhul_pd)) != VIP_OK){\r
- MTL_ERROR1("THHUL_pdm_free_pd_prep: ERROR (%d) : invalid handle\n", vret);\r
- return HH_EINVAL_PD_HNDL;\r
- }\r
- return HH_OK;\r
- }\r
-\r
- /* preparing a PD FREE */\r
- /* need to find pd table entry in pd list */\r
- /* and signal it as prepared for erase. Purpose here is to see if still have outstanding AVs */\r
- /* on this PD, in which case erase_prepare will return busy. */\r
- if ((vret=VIP_array_erase_prepare(pdm->pd_array,(VIP_array_handle_t)hhul_pd, NULL)) != VIP_OK){\r
- if (vret == VIP_EBUSY) { \r
- MTL_DEBUG4("THHUL_pdm_free_pd_prep: PD object is busy\n");\r
- return HH_EBUSY;\r
- } else {\r
- MTL_ERROR1("THHUL_pdm_free_pd_prep: ERROR (%d) : Could not find PD object\n", vret);\r
- return HH_EINVAL_PD_HNDL;\r
- }\r
- }\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THHUL_pdm_free_pd_done (\r
- HHUL_hca_hndl_t hca, \r
- HHUL_pd_hndl_t hhul_pd )\r
-{\r
- HH_ret_t ret;\r
- THHUL_pdm_t pdm;\r
- THHUL_pd_t *ul_pd;\r
- THH_udavm_t udavm;\r
- VIP_common_ret_t vret;\r
-\r
- ret = THHUL_hob_get_pdm(hca, &pdm);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THHUL_pdm_free_pd_done: ERROR (%d) : PDM object has not yet been created\n", ret);\r
- return HH_EINVAL;\r
- }\r
-\r
- /* need to find pd table entry in pd list */\r
- /* and destroy udavm if needed, and delete the entry from list */\r
- if ((vret=VIP_array_erase_done(pdm->pd_array,(VIP_array_handle_t)hhul_pd,\r
- (VIP_array_obj_t*) &ul_pd)) != VIP_OK){\r
- MTL_ERROR1("THHUL_pdm_free_pd_done: ERROR (%d) : Could not find PD object\n", vret);\r
- return HH_EINVAL_PD_HNDL;\r
- }\r
- udavm = ul_pd->udavm;\r
-\r
-\r
- /* For non-privileged UDAVs, destroy the UDAV user-level object allocated for this PD */\r
- if (!(pdm->priv_ud_av)) {\r
- /*udavm can legally be null if THHUL_pdm_alloc_pd_done was not called, due to \r
- * failure of THH_pdm_alloc_pd \r
- */\r
- if (udavm != NULL) {\r
- ret = THH_udavm_destroy(udavm);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THHUL_pdm_free_pd_done: ERROR (%d) : Could not destroy associated UDAV object\n", ret);\r
- /* continue, to free up the ul_pd anyway., and report successful 'free' */\r
- }\r
- }\r
-\r
- /* If udav was not allocated in DDR, free the allocated memory here */\r
- if (ul_pd->udav_nonddr_table != (MT_virt_addr_t) 0) {\r
- MOSAL_pci_virt_free_consistent((void *)ul_pd->udav_nonddr_table, ul_pd->uadv_nonddr_table_alloc_size);\r
- ul_pd->udav_nonddr_table = (MT_virt_addr_t) 0;\r
- ul_pd->udav_nonddr_table_aligned = (MT_virt_addr_t) 0;\r
- ul_pd->uadv_nonddr_table_alloc_size = 0;\r
- }\r
- }\r
- ul_pd->valid = FALSE; /* just in case OS does not detect heap errors, and does not zero entries */\r
- FREE(ul_pd);\r
- return HH_OK;\r
-}\r
-\r
-\r
-HH_ret_t THHUL_pdm_create_ud_av ( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_pd_hndl_t hhul_pd, \r
- VAPI_ud_av_t *av_p, \r
- HHUL_ud_av_hndl_t *ah_p )\r
-{\r
- HH_ret_t ret;\r
- THHUL_pdm_t pdm;\r
- THHUL_pd_t *ul_pd ;\r
- VIP_common_ret_t vret;\r
-\r
- /* pre-allocation checks */\r
- if (av_p == NULL) {\r
- MTL_ERROR4("THHUL_pdm_create_ud_av: av_p is NULL.\n");\r
- MT_RETURN(HH_EINVAL_PARAM);\r
- }\r
- \r
- if (av_p->port == 0 || av_p->port > THHUL_TAVOR_NUM_PORTS) {\r
- MTL_ERROR1("THHUL_pdm_create_ud_av: ERROR: invalid port number specified (%d)\n"\r
- ,av_p->port);\r
- return HH_EINVAL_PORT;\r
- }\r
-\r
- ret = THHUL_hob_get_pdm(hca, &pdm);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THHUL_pdm_create_ud_av: ERROR (%d) : PDM object has not yet been created\n", ret);\r
- return HH_EINVAL;\r
- }\r
-\r
- if (pdm->priv_ud_av) {\r
- MTL_ERROR1("THHUL_pdm_create_ud_av: non_privileged UDAVs not configured\n");\r
- return HH_EINVAL;\r
- }\r
- \r
- /* need to find pd table entry in pd array */\r
- if ((vret=VIP_array_find_hold(pdm->pd_array,(VIP_array_handle_t)hhul_pd,\r
- (VIP_array_obj_t*) &ul_pd)) != VIP_OK) {\r
- MTL_ERROR1("THHUL_pdm_create_ud_av: ERROR (%d) : Could not find PD object\n", vret);\r
- return HH_EINVAL_PD_HNDL;\r
- } \r
- \r
- if (ul_pd->valid == FALSE) {\r
- MTL_ERROR1("THHUL_pdm_create_ud_av: ERROR: This PD is not allocated\n");\r
- ret = HH_EINVAL_PD_HNDL;\r
- goto err;\r
- }\r
-\r
- if (ul_pd->udavm == NULL) {\r
- MTL_ERROR1("THHUL_pdm_create_ud_av: ERROR: UDAVM object not allocated\n");\r
- ret = HH_EINVAL;\r
- goto err;\r
- }\r
-\r
- /* now, do it */\r
- ret = THH_udavm_create_av(ul_pd->udavm, ul_pd->hh_pd_hndl, av_p, (HH_ud_av_hndl_t *)ah_p);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THHUL_pdm_create_ud_av: ERROR (%d) : Could not create address vector\n", ret);\r
- goto err;\r
- }\r
-\r
- return HH_OK;\r
-\r
-err:\r
- VIP_array_find_release(pdm->pd_array,(VIP_array_handle_t)hhul_pd);\r
- return ret;\r
-}\r
-\r
-\r
-HH_ret_t THHUL_pdm_modify_ud_av (\r
- HHUL_hca_hndl_t hca, \r
- HHUL_ud_av_hndl_t ah, \r
- VAPI_ud_av_t *av_p )\r
-{\r
- HH_ret_t ret;\r
- THHUL_pdm_t pdm;\r
- THHUL_pd_t *ul_pd;\r
- VIP_common_ret_t vret;\r
- VIP_array_handle_t local_pd_hndl;\r
- MT_bool found = FALSE;\r
- \r
- /* error checks */\r
- if (av_p->port == 0 || av_p->port > THHUL_TAVOR_NUM_PORTS) {\r
- MTL_ERROR1("THHUL_pdm_modify_ud_av: ERROR: invalid port number specified (%d)\n"\r
- ,av_p->port);\r
- return HH_EINVAL_PORT;\r
- }\r
-\r
- ret = THHUL_hob_get_pdm(hca, &pdm);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THHUL_pdm_modify_ud_av: ERROR (%d) : PDM object has not yet been created\n", ret);\r
- return HH_EINVAL;\r
- }\r
- \r
- if (pdm->priv_ud_av) {\r
- MTL_ERROR1("THHUL_pdm_modify_ud_av: non_privileged UDAVs not configured\n");\r
- return HH_EINVAL;\r
- }\r
-\r
- /* find the associated PD handle for this AV */\r
- VIP_ARRAY_FOREACH_HOLD(pdm->pd_array, vret, local_pd_hndl, (VIP_array_obj_t *)&ul_pd, TRUE) {\r
- if ((vret != VIP_OK) && (vret != VIP_EAGAIN)) {\r
- MTL_ERROR1("THHUL_pdm_modify_ud_av: ERROR (%d) : Could not find PD object\n", vret);\r
- /* return invalid AV handle, because a PD error return is not acceptable here */\r
- /* IB Spec demands that destroy PD shall fail if it has any outstanding resources. */\r
- /* Essentially, then, we have allowed destroy PD anyway, so that the AV handle is */\r
- /* no loger valid. */\r
- return HH_EINVAL_AV_HNDL;\r
- }\r
- if (ul_pd->valid == FALSE) {\r
- /* ignore if PD is in process of being created */\r
- if (vret == VIP_OK) {VIP_array_find_release(pdm->pd_array,local_pd_hndl);}\r
- continue;\r
- }\r
- /* try to modify the UDAVM */\r
- ret = THH_udavm_modify_av(ul_pd->udavm,ah,av_p);\r
- if (ret == HH_OK) {\r
- if (vret == VIP_OK) {VIP_array_find_release(pdm->pd_array,local_pd_hndl);}\r
- found = TRUE;\r
- break;\r
- } else if (ret != HH_EINVAL_AV_HNDL) {\r
- MTL_ERROR1("THHUL_pdm_modify_ud_av: ERROR (%d) : invalid parameter\n", ret);\r
- if (vret == VIP_OK) {VIP_array_find_release(pdm->pd_array,local_pd_hndl);}\r
- return ret;\r
- } \r
- if (vret == VIP_OK) {VIP_array_find_release(pdm->pd_array,local_pd_hndl);}\r
- }\r
- \r
- if (found == FALSE)\r
- {\r
- return HH_EINVAL_AV_HNDL;\r
- }\r
-\r
- return HH_OK;\r
-}\r
-\r
-\r
-HH_ret_t THHUL_pdm_query_ud_av (\r
- HHUL_hca_hndl_t hca, \r
- HHUL_ud_av_hndl_t ah, \r
- VAPI_ud_av_t *av_p )\r
-{\r
- HH_ret_t ret;\r
- THHUL_pdm_t pdm;\r
- THHUL_pd_t *ul_pd;\r
- VIP_common_ret_t vret;\r
- VIP_array_handle_t local_pd_hndl;\r
- MT_bool found = FALSE;\r
- \r
- /* error checks */\r
- ret = THHUL_hob_get_pdm(hca, &pdm);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THHUL_pdm_query_ud_av: ERROR (%d) : PDM object has not yet been created\n", ret);\r
- return HH_EINVAL;\r
- }\r
- \r
- if (pdm->priv_ud_av) {\r
- MTL_ERROR1("THHUL_pdm_query_ud_av: non_privileged UDAVs not configured\n");\r
- return HH_EINVAL;\r
- }\r
-\r
- /* find the associated PD handle for this AV */\r
- VIP_ARRAY_FOREACH_HOLD(pdm->pd_array, vret, local_pd_hndl, (VIP_array_obj_t *)&ul_pd, TRUE) {\r
- if ((vret != VIP_OK) && (vret != VIP_EAGAIN)) {\r
- MTL_ERROR1("THHUL_pdm_query_ud_av: ERROR (%d) : Could not find PD object\n", vret);\r
- /* return invalid AV handle, because a PD error return is not acceptable here */\r
- /* IB Spec demands that destroy PD shall fail if it has any outstanding resources. */\r
- /* Essentially, then, we have allowed destroy PD anyway, so that the AV handle is */\r
- /* no loger valid. */\r
- return HH_EINVAL_AV_HNDL;\r
- }\r
- if (ul_pd->valid == FALSE) {\r
- /* ignore if PD is in process of being created */\r
- if (vret == VIP_OK) {VIP_array_find_release(pdm->pd_array,local_pd_hndl);}\r
- continue;\r
- }\r
- /* try to modify the UDAVM */\r
- ret = THH_udavm_query_av(ul_pd->udavm,ah,av_p);\r
- if (ret == HH_OK) {\r
- if (vret == VIP_OK) {VIP_array_find_release(pdm->pd_array,local_pd_hndl);}\r
- found = TRUE;\r
- break;\r
- } else if (ret != HH_EINVAL_AV_HNDL) {\r
- MTL_ERROR1("THHUL_pdm_query_ud_av: ERROR (%d) : invalid parameter\n", ret);\r
- if (vret == VIP_OK) {VIP_array_find_release(pdm->pd_array,local_pd_hndl);}\r
- return ret;\r
- } \r
- if (vret == VIP_OK) {VIP_array_find_release(pdm->pd_array,local_pd_hndl);}\r
- }\r
- \r
- if (found == FALSE)\r
- {\r
- return HH_EINVAL_AV_HNDL;\r
- }\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THHUL_pdm_destroy_ud_av (\r
- HHUL_hca_hndl_t hca, \r
- HHUL_ud_av_hndl_t ah )\r
-{\r
- HH_ret_t ret;\r
- THHUL_pdm_t pdm;\r
- THHUL_pd_t *ul_pd;\r
- VIP_common_ret_t vret;\r
- VIP_array_handle_t local_pd_hndl;\r
- MT_bool found = FALSE;\r
- \r
- /* error checks */\r
- ret = THHUL_hob_get_pdm(hca, &pdm);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THHUL_pdm_destroy_ud_av: ERROR (%d) : PDM object has not yet been created\n", ret);\r
- return HH_EINVAL;\r
- }\r
- \r
- if (pdm->priv_ud_av) {\r
- MTL_ERROR1("THHUL_pdm_destroy_ud_av: non_privileged UDAVs not configured\n");\r
- return HH_EINVAL;\r
- }\r
-\r
- /* find the associated PD handle for this AV */\r
- VIP_ARRAY_FOREACH_HOLD(pdm->pd_array, vret, local_pd_hndl, (VIP_array_obj_t *)&ul_pd, TRUE) {\r
- if ((vret != VIP_OK) && (vret != VIP_EAGAIN)) {\r
- MTL_ERROR1("THHUL_pdm_destroy_ud_av: ERROR (%d) : Could not find PD object\n", vret);\r
- /* We were unable to find a PD to which this udav handle was registered. */\r
- /* Return invalid AV handle, because a PD error return is not acceptable here */\r
- return HH_EINVAL_AV_HNDL;\r
- }\r
- /* try to modify the UDAVM */\r
- if (ul_pd->valid == FALSE) {\r
- /* ignore if PD is in process of being created */\r
- if (vret == VIP_OK) {VIP_array_find_release(pdm->pd_array,local_pd_hndl);}\r
- continue;\r
- }\r
- ret = THH_udavm_destroy_av(ul_pd->udavm,ah);\r
- if (ret == HH_OK) {\r
- if (vret == VIP_OK) {VIP_array_find_release(pdm->pd_array,local_pd_hndl);}\r
- found = TRUE;\r
- break;\r
- } else if (ret != HH_EINVAL_AV_HNDL) {\r
- if (vret == VIP_OK) {VIP_array_find_release(pdm->pd_array,local_pd_hndl);}\r
- MTL_ERROR1("THHUL_pdm_destroy_ud_av: ERROR (%d) : invalid parameter\n", ret);\r
- return ret;\r
- } \r
- if (vret == VIP_OK) {VIP_array_find_release(pdm->pd_array,local_pd_hndl);}\r
- }\r
- \r
- if (found == TRUE){\r
- /* decrement udav reference count for the PD */\r
- VIP_array_find_release(pdm->pd_array,local_pd_hndl);\r
- return HH_OK;\r
- } else {\r
- return HH_EINVAL_AV_HNDL;\r
- }\r
-}\r
-\r
-HH_ret_t THHUL_pdm_get_ud_av_memkey_sqp_ok(\r
- /*IN*/ THHUL_pdm_t pdm,\r
- /*IN*/ HHUL_pd_hndl_t hhul_pd,\r
- /*OUT*/MT_bool *ok_for_sqp,\r
- /*OUT*/ VAPI_lkey_t *ud_av_memkey_p,\r
- /*OUT*/ char **av_ddr_base,\r
- /*OUT*/ char **av_host_base\r
-)\r
-{\r
- /* sanity check */\r
- THHUL_pd_t *ul_pd;\r
- VIP_common_ret_t vret;\r
-\r
-/* need to find pd table entry in pd array */\r
- if ((vret=VIP_array_find_hold(pdm->pd_array,(VIP_array_handle_t)hhul_pd,\r
- (VIP_array_obj_t*) &ul_pd)) != VIP_OK) {\r
- if (vret == VIP_EBUSY) { \r
- MTL_DEBUG4("THHUL_pdm_get_ud_av_memkey: PD object is busy\n");\r
- return HH_EBUSY;\r
- } else {\r
- MTL_ERROR1("THHUL_pdm_get_ud_av_memkey: ERROR (%d) : Could not find PD object\n", vret);\r
- return HH_EINVAL_PD_HNDL;\r
- }\r
- } \r
- *ud_av_memkey_p = ((THHUL_pd_t *)(ul_pd))->lkey;\r
- *av_ddr_base = ((THHUL_pd_t *)(ul_pd))->av_ddr_base;\r
- *av_host_base = ((THHUL_pd_t *)(ul_pd))->av_host_base;\r
- \r
- /* is OK for special QP iff udav table is located in host memory */\r
-// *ok_for_sqp = ((THHUL_pd_t *)(ul_pd))->uadv_nonddr_table_alloc_size == 0 ? FALSE : TRUE;\r
- *ok_for_sqp = TRUE; // AV copy in host memory makes it always ok\r
- VIP_array_find_release(pdm->pd_array,(VIP_array_handle_t)hhul_pd);\r
- return HH_OK;\r
- \r
-} /* THHUL_pdm_get_ud_av_memkey */\r
-\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_THHUL_PDM_H\r
-#define H_THHUL_PDM_H\r
-\r
-#include <mtl_common.h>\r
-#include <hh.h>\r
-#include <hhul.h>\r
-#include <thhul.h>\r
-\r
-#define THHUL_PDM_MAX_UL_UDAV_PER_PD 256\r
-\r
-DLL_API HH_ret_t THHUL_pdm_create (\r
- /*IN*/ THHUL_hob_t hob, \r
- /*IN*/ MT_bool priv_ud_av, \r
- /*OUT*/ THHUL_pdm_t *pdm_p\r
-);\r
-\r
-DLL_API HH_ret_t THHUL_pdm_destroy (/*IN*/ THHUL_pdm_t pdm);\r
-\r
-DLL_API HH_ret_t THHUL_pdm_alloc_pd_prep (\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*OUT*/ HHUL_pd_hndl_t *pd_p, \r
- /*OUT*/ void/*THH_pd_ul_resources_t*/ *pd_ul_resources_p \r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_pdm_alloc_pd_done (\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_pd_hndl_t hhul_pd, \r
- /*IN*/ HH_pd_hndl_t hh_pd, \r
- /*IN*/ void/*THH_pd_ul_resources_t*/ *pd_ul_resources_p \r
-);\r
-\r
-DLL_API HH_ret_t THHUL_pdm_free_pd_prep (\r
- /*IN*/HHUL_hca_hndl_t hca, \r
- /*IN*/HHUL_pd_hndl_t hhul_pd,\r
- /*IN*/MT_bool undo_flag \r
-);\r
-\r
-DLL_API HH_ret_t THHUL_pdm_free_pd_done (\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_pd_hndl_t hhul_pd \r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_pdm_create_ud_av ( \r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_pd_hndl_t hhul_pd, \r
- /*IN*/ VAPI_ud_av_t *av_p, \r
- /*OUT*/ HHUL_ud_av_hndl_t *ah_p\r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_pdm_modify_ud_av (\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_ud_av_hndl_t ah, \r
- /*IN*/ VAPI_ud_av_t *av_p \r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_pdm_query_ud_av (\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_ud_av_hndl_t ah, \r
- /*OUT*/ VAPI_ud_av_t *av_p \r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_pdm_destroy_ud_av (\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_ud_av_hndl_t ah \r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_pdm_get_hh_pd(\r
- /*IN*/ THHUL_pdm_t pdm,\r
- /*IN*/ HHUL_pd_hndl_t hhul_pd,\r
- /*OUT*/ HH_pd_hndl_t *hh_pd_p\r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_pdm_get_ud_av_memkey_sqp_ok(\r
- /*IN*/ THHUL_pdm_t pdm,\r
- /*IN*/ HHUL_pd_hndl_t hhul_pd,\r
- /*OUT*/MT_bool *ok_for_sqp,\r
- /*OUT*/ VAPI_lkey_t *ud_av_memkey_p,\r
- /*OUT*/ char **av_ddr_base,\r
- /*OUT*/ char **av_host_base\r
-);\r
-\r
-DLL_API HH_ret_t THHUL_pdm_alloc_pd_avs_prep (\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ u_int32_t max_num_avs,\r
- /*IN*/ HH_pdm_pd_flags_t pd_flags,\r
- /*IN*/ HHUL_pd_hndl_t *pd_p, \r
- /*OUT*/ void *pd_ul_resources_p \r
-);\r
-\r
-\r
-#endif /* H_THHUL_PDM_H */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_THHUL_PDM_PRIV_H\r
-#define H_THHUL_PDM_PRIV_H\r
-\r
-#include <mtl_common.h>\r
-#include <cr_types.h>\r
-#include <MT23108_PRM.h>\r
-#include <thhul_pdm.h>\r
-#include <thh.h>\r
-#include <udavm.h>\r
-#include <thhul_hob.h>\r
-#include <vip_array.h>\r
-#include <vip_hashp2p.h>\r
-#include <mosal.h>\r
-\r
-/* number of tavor physical ports defined here */ \r
-/* for use in checking port number provided in addr vector */\r
-#define THHUL_TAVOR_NUM_PORTS 2\r
-\r
-/* allocate initially space for 16 PDs for user-space processes, and 256 for kernel-space */\r
-/* ----- OS-dependent implementation ----- */\r
-#ifndef MT_KERNEL\r
-#define THHUL_PDM_INITIAL_NUM_PDS 16\r
-#else\r
-#define THHUL_PDM_INITIAL_NUM_PDS 256\r
-#endif\r
-\r
-/* PD entry */\r
-typedef struct THHUL_pd_st {\r
- HH_pd_hndl_t hh_pd_hndl;\r
- THH_udavm_t udavm;\r
- char *av_ddr_base;\r
- char *av_host_base;\r
- \r
- MT_virt_addr_t udav_nonddr_table;\r
- MT_virt_addr_t udav_nonddr_table_aligned;\r
- MT_size_t uadv_nonddr_table_alloc_size;\r
- VAPI_lkey_t lkey;\r
- MT_bool valid;\r
- HHUL_pd_hndl_t hhul_pd_hndl; \r
-\r
-} THHUL_pd_t;\r
-\r
-struct THHUL_pdm_st {\r
- MT_bool priv_ud_av;\r
- THH_ver_info_t version;\r
- VIP_array_p_t pd_array;\r
-} ;\r
-\r
-#endif /* H_THHUL_PDM_H */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#define C_THHUL_QPM_C\r
-\r
-#include <mosal.h>\r
-#include <ib_defs.h>\r
-#include <nMPGA.h>\r
-#include <vapi.h>\r
-#include <tlog2.h>\r
-#include <MT23108.h>\r
-#include <thhul.h>\r
-#include <uar.h>\r
-#include <thhul_hob.h>\r
-#include <thhul_cqm.h>\r
-#include <thhul_srqm.h>\r
-#include <thhul_pdm.h>\r
-#include <udavm.h>\r
-#include <vapi_common.h>\r
-#include <complib/cl_math.h>\r
-\r
-\r
-/* THH_qpm Pkey and GID table access for usage of the special QPs (mlx IB headers) */\r
-#ifdef MT_KERNEL\r
-#include <thh_hob.h>\r
-#endif\r
-\r
-#if defined(MT_KERNEL) && defined(__LINUX__)\r
-#include <linux/mm.h>\r
-#include <asm/pgtable.h>\r
-#include <linux/highmem.h>\r
-#endif\r
-\r
-#include "thhul_qpm.h"\r
-\r
-#ifdef WIN32\r
-#include "hca_data.h"\r
-#endif\r
-\r
-#include <mtperf.h>\r
-MTPERF_NEW_SEGMENT(THH_uar_sendq_dbell,200);\r
-MTPERF_NEW_SEGMENT(WQE_build_send,2000);\r
-MTPERF_NEW_SEGMENT(SQ_WQE_copy,2000);\r
-\r
-#define USE_FAST_POST 1\r
-\r
-#ifndef MT_KERNEL\r
-/* instead of "ifdef"ing all over the code we define an empty macro */\r
-#define MOSAL_pci_phys_free_consistent(addr,sz) do {} while(0);\r
-#endif\r
-\r
-\r
-/* Limit kmalloc to 2 pages (if this fails, vmalloc will fail too) */\r
-#define WQ_KMALLOC_LIMIT (4*MOSAL_SYS_PAGE_SIZE)\r
-#define SMALL_VMALLOC_AREA (1<<28) /* VMALLOC area of 256MB or less is considered a scarce resource */\r
-\r
-#define LOG2_QP_HASH_TBL_SZ 8\r
-#define QP_HASH_TBL_SZ (1<<8)\r
-\r
-#define WQE_ALIGN_SHIFT 6 /* WQE address should be aligned to 64 Byte */\r
-#define WQE_SZ_MULTIPLE_SHIFT 4 /* WQE size must be 16 bytes multiple */\r
-/* WQE segments sizes */\r
-#define WQE_SEG_SZ_NEXT (sizeof(struct wqe_segment_next_st)/8) /* NEXT segment */\r
-#define WQE_SEG_SZ_CTRL (sizeof(struct wqe_segment_ctrl_send_st)/8) /* CTRL segment */\r
-#define WQE_SEG_SZ_RD (sizeof(struct wqe_segment_rd_st)/8) /* DATAGRAM:RD */\r
-#define WQE_SEG_SZ_UD (sizeof(struct wqe_segment_ud_st)/8) /* DATAGRAM:UD */\r
-#define WQE_SEG_SZ_RADDR (sizeof(struct wqe_segment_remote_address_st)/8) /* Remote address */\r
-#define WQE_SEG_SZ_ATOMIC (sizeof(struct wqe_segment_atomic_st)/8) /* Atomic */\r
-#define WQE_SEG_SZ_BIND (sizeof(struct wqe_segment_bind_st)/8) /* Bind */\r
-/* There is either BIND or RADDR+ATOMIC */\r
-#define WQE_SEG_SZ_BIND_RADDR_ATOMIC ((WQE_SEG_SZ_RADDR+WQE_SEG_SZ_ATOMIC) > WQE_SEG_SZ_BIND ? \\r
- (WQE_SEG_SZ_RADDR+WQE_SEG_SZ_ATOMIC) : WQE_SEG_SZ_BIND )\r
-#define WQE_SEG_SZ_SG_ENTRY (sizeof(struct wqe_segment_data_ptr_st)/8)/* Scatter/Gather entry(ptr)*/\r
-#define WQE_SEG_SZ_SG_ENTRY_DW (sizeof(struct wqe_segment_data_ptr_st)/32)/* (same in DWORDs) */\r
-/* INLINE segment for UD headers (SMI/GSI) */\r
-#define IB_RWH_SZ 4\r
-#define IB_ICRC_SZ 4\r
-#define WQE_INLINE_SZ_BCOUNT 4\r
-/* INLINE segment for UD headers (SMI/GSI) */\r
-#define WQE_INLINE_SZ_UD_HDR \\r
- MT_UP_ALIGNX_U32((WQE_INLINE_SZ_BCOUNT+IB_LRH_LEN+IB_GRH_LEN+IB_BTH_LEN+IB_DETH_LEN),4)\r
-/* INLINE segment for RAW-Ethertype */\r
-#define WQE_INLINE_SZ_RAW_HDR \\r
- MT_UP_ALIGNX_U32((WQE_INLINE_SZ_BCOUNT+IB_LRH_LEN+IB_RWH_SZ),4)\r
-#define WQE_INLINE_ICRC MT_UP_ALIGNX_U32(WQE_INLINE_SZ_BCOUNT+IB_ICRC_SZ,4)\r
-#define MAX_WQE_SZ 1008\r
-#define BIND_WQE_SZ (WQE_SEG_SZ_NEXT+WQE_SEG_SZ_CTRL+WQE_SEG_SZ_BIND)\r
-\r
-#define MAX_ALLOC_RETRY 3 /* Maximum retries to get WQEs buffer which does not cross 4GB boundry */\r
-\r
-#define IS_VALID_QPN(qpn) ((qpn) <= 0x00FFFFFF)\r
-#define DEFAULT_PKEY 0xFFFF\r
-#define QP1_PKEY_INDEX 0xFFFFFFFF\r
-\r
-#define RESERVED_MEMBIND_EECN 0 /* Pseudo EE-context reserved for memory binding processing */\r
-\r
-/* Dpool in size granularity of 1KB */\r
-#define THHUL_DPOOL_SZ_MIN_KB 1 /* Minimum WQEs buffer of 1KB */\r
-#define THHUL_DPOOL_SZ_MAX_KB 64 /* Max. is 64KB */\r
-#define THHUL_DPOOL_SZ_UNIT_SHIFT 10 /* 1KB units shift */\r
-#define THHUL_DPOOL_GRANULARITY_SHIFT 10 /* 1KB garnularity - for alignment */\r
-#define THHUL_DPOOL_SZ_BASE_BUF_KB \\r
- (THHUL_DPOOL_SZ_MAX_KB*2) /* Size of buffer shared among dpools*/\r
-\r
-/* Descriptors pool for small QPs */\r
-/* This data structure allows sharing of locked pages among QPs in order to reduce amount of\r
- locked pages and assure they cover full pages (fork support) */\r
-typedef struct THHUL_qp_dpool_st {\r
- MT_size_t buf_size_kb; /* Each buffer in the pool */\r
- void* free_buf_list;\r
- unsigned long ref_cnt; /* When reached zero, may be freed */\r
- void* orig_buf; /* Pointer to allocated memory chunk */\r
- MT_size_t orig_size;\r
- MT_bool used_virt_alloc;\r
- struct THHUL_qp_dpool_st *prev; /* list of dpools of same size */\r
- struct THHUL_qp_dpool_st *next; /* list of dpools of same size */\r
-} THHUL_qpm_dpool_t;\r
-\r
-typedef struct {\r
- VAPI_ud_av_t av;\r
- MPGA_headers_t hdrs;\r
-} special_qp_temp_t;\r
-\r
-#define CHIME_WORDS_PREFIX volatile\r
-#define WQE_IO_WRITE MOSAL_MMAP_IO_WRITE_DWORD\r
-\r
-typedef struct { /* Queue resources context */\r
- MT_virt_addr_t wqe_buf; /* The buffer for this queue WQEs - aligned to WQE size */ \r
- VAPI_wr_id_t *wqe_id; /* Array of max_outs entries for holding each WQE ID (WQE index based) */\r
- u_int32_t max_outs; /* Max. outstanding (number of WQEs in buffer) */\r
- u_int32_t cur_outs; /* Currently outstanding */\r
- u_int32_t max_sg_sz; /* Max. Scatter/Gather list size */\r
- MT_size_t log2_max_wqe_sz; /* WQE size is a power of 2 (software implementation requirement) */\r
- u_int32_t max_inline_data; /* For send queue only */\r
- u_int32_t next2post_index; /* Next WQE to use for posting (producer index)*/\r
- u_int32_t next2free_index; /* Next WQE to use free (consumer index) */\r
- volatile u_int32_t* last_posted_p; /* For WQE chain linkage (== NULL if none) */\r
- special_qp_temp_t *wqe_tmp; /* For av,headers in special QP Send */\r
- u_int32_t *wqe_draft;\r
- /* Implementation note:\r
- * Using the "wqe_draft" scratchpad is required since we may\r
- * perform many read-modify-writes while packing the WQE fields and we\r
- * have no idea on WQEs buffer location. In cases where the actual WQE is\r
- * in the attached DDR memory, a direct WQE packing will increase the \r
- * building latency since that memory is not cached and each "read-modify-write"\r
- * would consume time as well as PCI bandwidth.\r
- * So we build the WQE on the local stack and then copy it (along with the \r
- * swapping to big-endian, if needed).\r
- * Also note that this allows us to allocate the WQE on after all WQE is formatted,\r
- * thus minimizing the QP (spin)locking time.\r
- */\r
- VAPI_qp_state_t qp_state; /* User level assumed QP state */\r
- /* Implementation note:\r
- * qp_state is held per queue in order to avoid race in qp_state updates \r
- * which may result from polling different CQs for each queue.\r
- * We would also like to keep the common THHUL_qp_t static during the life\r
- * of the QP in order to avoid additional synchronization between send and\r
- * receive queue \r
- */\r
- MOSAL_spinlock_t q_lock; /* Protect concurrent usage of the queue */\r
-} queue_res_t;\r
-\r
-/* HHUL_qp_hndl_t is a pointer to this structure */\r
-typedef struct THHUL_qp_st {\r
- VAPI_special_qp_t sqp_type; /* VAPI_REGULAR_QP for non-special QP */\r
- IB_ts_t ts_type;\r
- IB_wqpn_t qpn;\r
- HHUL_pd_hndl_t pd;\r
- THH_uar_t uar; /* UAR to use for this QP */\r
- char *av_ddr_base;\r
- char *av_host_base;\r
- MT_bool is_priv_ud_av; /* Privileged UD AVs are enforced */\r
- VAPI_lkey_t ud_av_memkey; /* Memory key to put for UD AV handles */\r
- HHUL_cq_hndl_t sq_cq;\r
- HHUL_cq_hndl_t rq_cq;\r
- void* wqe_buf_orig; /* Pointer returned by qpm_malloc_within_4GB() for WQE buffer */\r
- MT_bool used_virt_alloc; /* Used "MOSAL_pci_virt_alloc_consistent" for buffer allocation */\r
- MT_size_t wqe_buf_orig_size; /* size in bytes of wqe_buf_orig */\r
- THHUL_qpm_dpool_t *dpool_p; /* If not NULL, wqe_buf_orig taken from this descriptors pool */\r
- queue_res_t sq_res; /* Send queue resources */\r
- queue_res_t rq_res; /* Receive queue resources */\r
- HHUL_srq_hndl_t srq; /* Set to HHUL_INVAL_SRQ_HNDL if not associated with a SRQ */\r
-} *THHUL_qp_t; \r
-\r
-#define QPM_USE_FIXED_QP_ARRAY 1\r
-#define TOTAL_QP_ARRAY_PER_QPM 2048\r
-#define QPM_QP_PER_ARRAY TOTAL_QP_ARRAY_PER_QPM/QP_HASH_TBL_SZ\r
-#define QP_ARRAY_REUSE 0xFFFFFFFE /* reuse qp array */\r
-#define QP_ARRAY_UNUSED 0xFFFFFFFF /* first unused array */\r
-\r
-typedef struct qp_array_st { \r
- IB_wqpn_t qpn;\r
- THHUL_qp_t qp;\r
-} qp_array_t;\r
-\r
-\r
-typedef struct qp_hash_entry_st { /* QPN-to-QP hash table entry */\r
- IB_wqpn_t qpn;\r
- THHUL_qp_t qp;\r
- struct qp_hash_entry_st *next; /* next in this hash bin */\r
-} qp_hash_entry_t;\r
-\r
-\r
-typedef struct qp_array_entry_st {\r
- qp_array_t qp_array[QPM_QP_PER_ARRAY+1]; /* set last one to QP_ARRAY_UNUSED*/\r
-}qp_array_entry_t;\r
-\r
-/* fixed array table is two dimensional.\r
- * QP_ARRAY_UNUSED : next entry in array.\r
- * QP_ARRAY_REUSE : Used previousely, but qp was destroyed. This can be recycled.\r
- * ex: array_tbl[i]->[qpn][QP_ARRAY_REUSE(can be reused)][qpn][QP_ARRAY_UNUSED(next entry)]...\r
- */ \r
-struct THHUL_qpm_st { /* THHUL_qpm_t is a pointer to this */\r
- qp_hash_entry_t* hash_tbl[QP_HASH_TBL_SZ];\r
- qp_array_entry_t array_tbl[QP_HASH_TBL_SZ];\r
- u_int32_t qp_cnt; /* Total number of QPs */\r
- MOSAL_spinlock_t hash_lock; /* used for qp_cnt protection, too */\r
- THHUL_qpm_dpool_t *dpool_p[THHUL_DPOOL_SZ_MAX_KB - THHUL_DPOOL_SZ_MIN_KB + 1];/* KB garanularity */\r
-#ifdef THHUL_QPM_DEBUG_DPOOL\r
- unsigned long dpool_cnt; \r
-#endif\r
- MOSAL_mutex_t dpool_lock;\r
- THHUL_srqm_t srqm;\r
-};\r
-\r
-/**********************************************************************************************\r
- * Private functions protoypes declarations\r
- **********************************************************************************************/\r
-static HH_ret_t qp_prep(\r
- HHUL_hca_hndl_t hca, \r
- VAPI_special_qp_t qp_type, \r
- HHUL_qp_init_attr_t *qp_init_attr_p, \r
- HHUL_qp_hndl_t *qp_hndl_p, \r
- VAPI_qp_cap_t *qp_cap_out_p, \r
- THH_qp_ul_resources_t *qp_ul_resources_p, \r
- MT_bool in_ddr_mem /* WQEs buffer allocated in attached DDR mem. or in main memory */\r
-);\r
-\r
-static HH_ret_t init_qp(\r
- HHUL_hca_hndl_t hca, \r
- HHUL_qp_init_attr_t *qp_init_attr_p, \r
- THHUL_qp_t new_qp\r
-);\r
-\r
-static HH_ret_t qpm_alloc_wqe_buf(\r
- /*IN*/ THHUL_qpm_t qpm,\r
- /*IN*/ MT_bool in_ddr_mem, /* Allocation of WQEs buffer is requested in attached DDR mem. */\r
- /*IN*/ u_int32_t max_outs_wqes, /* HCA cap. */\r
- /*IN*/ u_int32_t max_sg_ent, /* HCA cap. of max.s/g entries */\r
- /*IN/OUT*/ THHUL_qp_t new_qp,\r
- /*OUT*/ THH_qp_ul_resources_t *qp_ul_resources_p\r
-);\r
-\r
-static HH_ret_t qpm_alloc_aux_data_buf(\r
- /*IN/OUT*/ THHUL_qp_t new_qp\r
-);\r
-\r
-static HH_ret_t insert_to_hash(THHUL_qpm_t qpm, THHUL_qp_t qp);\r
-\r
-static HH_ret_t remove_from_hash(THHUL_qpm_t qpm, THHUL_qp_t qp);\r
-\r
-#ifndef __KERNEL__\r
-static void* dpool_alloc(THHUL_qpm_t qpm, u_int8_t buf_size_kb, THHUL_qpm_dpool_t **dpool_pp);\r
-\r
-static void dpool_free(THHUL_qpm_t qpm, THHUL_qpm_dpool_t *dpool_p, void* buf);\r
-\r
-#else\r
-#define dpool_free(qpm,dpool_p,buf) \\r
- MTL_ERROR1(MT_FLFMT("%s: Invoked dpool_free in kernel by mistake"), __func__)\r
- \r
-#endif\r
-\r
-/**********************************************************************************************\r
- * Private inline functions \r
- **********************************************************************************************/\r
-/* Computer hash value (bin index) for given QP number */\r
-inline static u_int32_t get_hash_index(IB_wqpn_t qpn)\r
-{\r
- return (qpn & MASK32(LOG2_QP_HASH_TBL_SZ));\r
-}\r
-\r
-inline static u_int32_t get_wqe_index(\r
- /*IN*/ queue_res_t *q_res_p, \r
- /*IN*/ u_int32_t wqe_addr_32lsb,\r
- /*OUT*/ u_int32_t *wqe_index_p\r
-)\r
-{\r
- u_int32_t wqe_buf_base_32lsb;\r
-\r
- /* TBD: On QP resize this will have to be modified (buffers may change during QP life cycle) */\r
- \r
- wqe_buf_base_32lsb= (u_int32_t)(q_res_p->wqe_buf);\r
- if (wqe_addr_32lsb >= wqe_buf_base_32lsb) { /* Assure index computation is positive */\r
- *wqe_index_p= (wqe_addr_32lsb - wqe_buf_base_32lsb) >> q_res_p->log2_max_wqe_sz;\r
- if (*wqe_index_p < q_res_p->max_outs) { /* WQE is within this queue */\r
- /* TBD: check if given wqe_addr_32lsb is aligned to WQE size */\r
- return HH_OK;\r
- }\r
- } \r
- \r
- return HH_EINVAL; /* WQE is not withing this queue */\r
-}\r
-\r
-\r
-\r
-static void dump_qp(qp_hash_entry_t *qp_p)\r
-{\r
- MTL_ERROR1("==== dump of qpn=%d ====\n", qp_p->qp->qpn);\r
- MTL_ERROR1("sqp_type=%s\n", VAPI_special_qp_sym(qp_p->qp->sqp_type));\r
- MTL_ERROR1("ts_type=%s\n", VAPI_ts_type_sym(qp_p->qp->ts_type));\r
- MTL_ERROR1("pd=%lu\n", qp_p->qp->pd);\r
- MTL_ERROR1("uar=%p\n", qp_p->qp->uar);\r
- MTL_ERROR1("is_priv_ud_av=%s\n", qp_p->qp->is_priv_ud_av ? "Yes" : "No");\r
- MTL_ERROR1("ud_av_memkey=0x%x\n", qp_p->qp->ud_av_memkey);\r
- MTL_ERROR1("sq_cq=%p\n", qp_p->qp->sq_cq);\r
- MTL_ERROR1("rq_cq=%p\n", qp_p->qp->rq_cq);\r
- MTL_ERROR1("wqe_buf_orig=%p\n", qp_p->qp->wqe_buf_orig);\r
- MTL_ERROR1("used_virt_alloc=%s\n", qp_p->qp->used_virt_alloc ? "Yes" : "No");\r
- MTL_ERROR1("wqe_buf_orig_size="SIZE_T_FMT"\n", qp_p->qp->wqe_buf_orig_size);\r
- MTL_ERROR1("dpool_p=%p\n", qp_p->qp->dpool_p);\r
-}\r
-\r
-\r
-#if QPM_USE_FIXED_QP_ARRAY\r
-\r
-inline static HH_ret_t find_wqe_from_array(\r
- /*IN*/ THHUL_qpm_t qpm, \r
- /*IN*/ IB_wqpn_t qpn, \r
- /*IN*/ u_int32_t wqe_addr_32lsb,\r
- /*OUT*/ THHUL_qp_t *qp_p,\r
- /*OUT*/ queue_res_t **q_res_pp,\r
- /*OUT*/ u_int32_t *wqe_index_p,\r
- /*OUT*/ VAPI_wr_id_t *wqe_id_p\r
-)\r
-{\r
- \r
- u_int32_t hash_index= get_hash_index(qpn);\r
- int i = 0; \r
- qp_array_entry_t *qp_array_p = &qpm->array_tbl[hash_index];\r
- IB_wqpn_t m_qpn = qp_array_p->qp_array[i].qpn;\r
-\r
- \r
- while(m_qpn != QP_ARRAY_UNUSED)\r
- {\r
- if(m_qpn == qpn)\r
- {\r
- THHUL_qp_t qp = *qp_p= qp_array_p->qp_array[i].qp; \r
- \r
- /* check if this WQE is of SQ */ \r
- if ((*wqe_index_p = (wqe_addr_32lsb - (u_int32_t)qp->sq_res.wqe_buf) >> qp->sq_res.log2_max_wqe_sz) \r
- < qp->sq_res.max_outs) \r
- {\r
- \r
- *q_res_pp= &((*qp_p)->sq_res); \r
- *wqe_id_p= (*q_res_pp)->wqe_id[*wqe_index_p]; \r
- return HH_OK;\r
- }\r
- /* check if this WQE is of RQ */\r
- if ((*qp_p)->srq == HHUL_INVAL_SRQ_HNDL) {\r
- if ((*wqe_index_p = (wqe_addr_32lsb - (u_int32_t)qp->rq_res.wqe_buf) >> qp->rq_res.log2_max_wqe_sz) \r
- < qp->rq_res.max_outs) \r
- { \r
- *q_res_pp= &((*qp_p)->rq_res);\r
- *wqe_id_p= (*q_res_pp)->wqe_id[*wqe_index_p]; \r
- return HH_OK;\r
- } \r
- } else { /* From SRQ ? */\r
- HH_ret_t rc;\r
- *q_res_pp= NULL;\r
- rc= THHUL_srqm_comp(qpm->srqm, (*qp_p)->srq, wqe_addr_32lsb, wqe_id_p);\r
- if (rc == HH_OK) {\r
- return HH_OK;\r
- }\r
- }\r
- }\r
- m_qpn = qp_array_p->qp_array[++i].qpn; \r
- } \r
-\r
- return HH_EINVAL; /* Invalid WQE address for this QP */ \r
-}\r
-#endif\r
-\r
-/* Find the queue context from the QP number and WQE address - using the hash table */\r
-#if 0 /*find_wqe */\r
-inline static HH_ret_t find_wqe(\r
- /*IN*/ THHUL_qpm_t qpm, \r
- /*IN*/ IB_wqpn_t qpn, \r
- /*IN*/ u_int32_t wqe_addr_32lsb,\r
- /*OUT*/ THHUL_qp_t *qp_p,\r
- /*OUT*/ queue_res_t **q_res_pp,\r
- /*OUT*/ u_int32_t *wqe_index_p,\r
- /*OUT*/ VAPI_wr_id_t *wqe_id_p\r
-)\r
-{\r
- u_int32_t hash_index= get_hash_index(qpn);\r
- qp_hash_entry_t *cur_entry;\r
- HH_ret_t rc;\r
-\r
-#if QPM_USE_FIXED_QP_ARRAY \r
- if(find_wqe_from_array(qpm,qpn,wqe_addr_32lsb,qp_p,q_res_pp,wqe_index_p,wqe_id_p) == HH_OK)\r
- return HH_OK;\r
-#endif\r
- \r
- MOSAL_spinlock_dpc_lock(&(qpm->hash_lock));\r
- for (cur_entry= qpm->hash_tbl[hash_index]; cur_entry != NULL;\r
- cur_entry= cur_entry->next) {\r
- if (cur_entry->qpn == qpn) break;\r
- }\r
- MOSAL_spinlock_unlock(&(qpm->hash_lock));\r
- if (cur_entry == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s(pid="MT_PID_FMT"): failed to find qpn=0x%x in the hash table"),\r
- __func__, MOSAL_getpid(), qpn);\r
- return HH_EINVAL_QP_NUM; /* not found */\r
- }\r
- *qp_p= cur_entry->qp;\r
- \r
- /* check if this WQE is of SQ */\r
- *q_res_pp= &((*qp_p)->sq_res);\r
- rc= get_wqe_index(*q_res_pp,wqe_addr_32lsb,wqe_index_p);\r
- if (rc == HH_OK) {\r
- *wqe_id_p= (*q_res_pp)->wqe_id[*wqe_index_p]; \r
- return HH_OK;\r
- }\r
- \r
- /* check if this WQE is of RQ */\r
- if ((*qp_p)->srq == HHUL_INVAL_SRQ_HNDL) {\r
- *q_res_pp= &((*qp_p)->rq_res);\r
- rc= get_wqe_index(*q_res_pp,wqe_addr_32lsb,wqe_index_p);\r
- if (rc == HH_OK) {\r
- *wqe_id_p= (*q_res_pp)->wqe_id[*wqe_index_p]; \r
- return HH_OK;\r
- }\r
- } else { /* From SRQ ? */\r
- *q_res_pp= NULL;\r
- rc= THHUL_srqm_comp(qpm->srqm, (*qp_p)->srq, wqe_addr_32lsb, wqe_id_p);\r
- if (rc != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed to find WQE in SRQ (WQE=0x%X QPn=0x%X)"), __func__,\r
- wqe_addr_32lsb, (*qp_p)->qpn);\r
- }\r
- }\r
- \r
- MTL_ERROR1(MT_FLFMT("%s(pid="MT_PID_FMT"): failed to find wqe"), __func__, MOSAL_getpid());\r
- dump_qp(cur_entry);\r
- return rc; /* Invalid WQE address for this QP */\r
-}\r
-#else /* find_wqe */\r
-\r
-/* optimized version of find_wqe */\r
-inline static HH_ret_t find_wqe(\r
- /*IN*/ THHUL_qpm_t qpm, \r
- /*IN*/ IB_wqpn_t qpn, \r
- /*IN*/ u_int32_t wqe_addr_32lsb,\r
- /*OUT*/ THHUL_qp_t *qp_p,\r
- /*OUT*/ queue_res_t **q_res_pp,\r
- /*OUT*/ u_int32_t *wqe_index_p,\r
- /*OUT*/ VAPI_wr_id_t *wqe_id_p\r
-)\r
-{\r
- u_int32_t hash_index;\r
- qp_hash_entry_t *cur_entry;\r
-#if QPM_USE_FIXED_QP_ARRAY \r
- if(find_wqe_from_array(qpm,qpn,wqe_addr_32lsb,qp_p,q_res_pp,wqe_index_p,wqe_id_p) == HH_OK)\r
- return HH_OK;\r
-#endif \r
-\r
- hash_index = get_hash_index(qpn);\r
-\r
- MOSAL_spinlock_dpc_lock(&(qpm->hash_lock));\r
- for (cur_entry= qpm->hash_tbl[hash_index]; cur_entry != NULL;\r
- cur_entry= cur_entry->next)\r
- {\r
- if (cur_entry->qpn == qpn)\r
- { \r
- THHUL_qp_t qp = *qp_p= cur_entry->qp;\r
- MOSAL_spinlock_unlock(&(qpm->hash_lock));\r
- /* check if this WQE is of SQ */ \r
- if ((*wqe_index_p = (wqe_addr_32lsb - (u_int32_t)qp->sq_res.wqe_buf) >> qp->sq_res.log2_max_wqe_sz) \r
- < qp->sq_res.max_outs) \r
- {\r
- *q_res_pp= &((*qp_p)->sq_res); \r
- *wqe_id_p= (*q_res_pp)->wqe_id[*wqe_index_p]; \r
- return HH_OK;\r
- }\r
- /* check if this WQE is of RQ */\r
- if ((*qp_p)->srq == HHUL_INVAL_SRQ_HNDL)\r
- {\r
- if ((*wqe_index_p = (wqe_addr_32lsb - (u_int32_t)qp->rq_res.wqe_buf) >> qp->rq_res.log2_max_wqe_sz) \r
- < qp->rq_res.max_outs) \r
- {\r
- *q_res_pp= &((*qp_p)->rq_res);\r
- *wqe_id_p= (*q_res_pp)->wqe_id[*wqe_index_p]; \r
- return HH_OK;\r
- } \r
- }\r
- else\r
- { /* From SRQ ? */\r
- HH_ret_t rc;\r
- *q_res_pp= NULL;\r
- rc= THHUL_srqm_comp(qpm->srqm, (*qp_p)->srq, wqe_addr_32lsb, wqe_id_p);\r
- if (rc != HH_OK)\r
- {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed to find WQE in SRQ (WQE=0x%X QPn=0x%X)"), __func__,\r
- wqe_addr_32lsb, (*qp_p)->qpn);\r
- }\r
- return rc;\r
- }\r
- } \r
- }\r
- MOSAL_spinlock_unlock(&(qpm->hash_lock));\r
-\r
- return HH_EINVAL; /* Invalid WQE address for this QP */\r
-}\r
-#endif /*find_wqe */\r
-\r
-#if 0 /* valid_2send, valid2recv */\r
-\r
-inline static MT_bool is_qpstate_valid_2send(VAPI_qp_state_t cur_state)\r
-{\r
- switch (cur_state) {\r
- case VAPI_RTS:\r
- case VAPI_SQD:\r
- case VAPI_ERR:\r
- case VAPI_SQE: return TRUE;\r
- break;\r
- default: return FALSE;\r
- }\r
-\r
-}\r
-inline static MT_bool is_qpstate_valid_2recv(VAPI_qp_state_t cur_state)\r
-{\r
- switch (cur_state) {\r
- case VAPI_INIT: \r
- case VAPI_RTR:\r
- case VAPI_RTS:\r
- case VAPI_SQD:\r
- case VAPI_ERR:\r
- case VAPI_SQE: return TRUE;\r
- break;\r
- default: return FALSE;\r
- }\r
-\r
-}\r
-#else /* valid_2send, valid2recv */\r
- \r
-inline static bool is_qpstate_valid_2send(VAPI_qp_state_t cur_state)\r
-{\r
- if(MOSAL_EXPECT_FALSE(cur_state < VAPI_RTS))\r
- return FALSE;\r
- return TRUE; \r
-}\r
-\r
-inline static bool is_qpstate_valid_2recv(VAPI_qp_state_t cur_state)\r
-{\r
- if(MOSAL_EXPECT_FALSE(cur_state < VAPI_INIT))\r
- return FALSE;\r
- return TRUE; \r
-}\r
-\r
-#endif /* valid_2send, valid2recv */\r
-\r
-inline static tavor_if_nopcode_t encode_nopcode(VAPI_wr_opcode_t opcode)\r
-{\r
- switch (opcode) {\r
- case VAPI_RDMA_WRITE:\r
- return TAVOR_IF_NOPCODE_RDMAW;\r
- case VAPI_RDMA_WRITE_WITH_IMM:\r
- return TAVOR_IF_NOPCODE_RDMAW_IMM;\r
- case VAPI_SEND:\r
- return TAVOR_IF_NOPCODE_SEND;\r
- case VAPI_SEND_WITH_IMM:\r
- return TAVOR_IF_NOPCODE_SEND_IMM;\r
- case VAPI_RDMA_READ:\r
- return TAVOR_IF_NOPCODE_RDMAR;\r
- case VAPI_ATOMIC_CMP_AND_SWP:\r
- return TAVOR_IF_NOPCODE_ATOM_CMPSWP;\r
- case VAPI_ATOMIC_FETCH_AND_ADD:\r
- return TAVOR_IF_NOPCODE_ATOM_FTCHADD;\r
- default:\r
- return TAVOR_IF_NOPCODE_NOP;\r
- }\r
-}\r
-\r
-/*********** WQE building functions ***********/\r
-inline u_int64_t translate_av(THHUL_qp_t qp, u_int64_t ah)\r
-{\r
- return ah - (u_int64_t)(MT_ulong_ptr_t)qp->av_host_base + (u_int64_t)(MT_ulong_ptr_t)qp->av_ddr_base;\r
-}\r
-\r
-/* Init a not-connected (invalid) "next" segment (i.e. NDS=0) */\r
-#if 0 /* qpm_WQE_init_next */\r
-inline static u_int32_t qpm_WQE_init_next(u_int32_t *wqe_buf)\r
-{\r
- memset(wqe_buf,0,WQE_SEG_SZ_NEXT);\r
- return WQE_SEG_SZ_NEXT;\r
-}\r
-#else /* qpm_WQE_init_next */\r
-/* Optimized qpm_WQE_init_next */\r
-inline static u_int32_t qpm_WQE_init_next(u_int32_t *wqe_buf)\r
-{\r
- /* WQE_SEG_SZ_NEXT = 8bytes, so write 64bit zero to address */ \r
- *(u_int64_t *)wqe_buf = 0;\r
- \r
- return WQE_SEG_SZ_NEXT;\r
-}\r
-#endif\r
-\r
-inline static u_int32_t qpm_WQE_pack_send_next(u_int32_t *segment_p, \r
- tavor_if_nopcode_t nopcode, MT_bool fence, u_int32_t dbd,\r
- u_int32_t next_wqe_32lsb, u_int32_t wqe_sz_16B_chunks,\r
- IB_eecn_t eecn)\r
-{\r
- memset(segment_p,0,WQE_SEG_SZ_NEXT); /* Clear all "RESERVED" */\r
- segment_p[MT_BYTE_OFFSET(wqe_segment_next_st,nda_31_6)>>2]= next_wqe_32lsb & (~MASK32(6));\r
- MT_INSERT_ARRAY32(segment_p,nopcode,\r
- MT_BIT_OFFSET(wqe_segment_next_st,nopcode),MT_BIT_SIZE(wqe_segment_next_st,nopcode));\r
- MT_INSERT_ARRAY32(segment_p,fence ? 1 : 0,\r
- MT_BIT_OFFSET(wqe_segment_next_st,f),MT_BIT_SIZE(wqe_segment_next_st,f));\r
- MT_INSERT_ARRAY32(segment_p,dbd,\r
- MT_BIT_OFFSET(wqe_segment_next_st,dbd),MT_BIT_SIZE(wqe_segment_next_st,dbd));\r
- MT_INSERT_ARRAY32(segment_p,wqe_sz_16B_chunks,\r
- MT_BIT_OFFSET(wqe_segment_next_st,nds),MT_BIT_SIZE(wqe_segment_next_st,nds));\r
- MT_INSERT_ARRAY32(segment_p,eecn,\r
- MT_BIT_OFFSET(wqe_segment_next_st,nee),MT_BIT_SIZE(wqe_segment_next_st,nee));\r
- return WQE_SEG_SZ_NEXT;\r
-}\r
-\r
-// u_int32_t offsets within wqe_segment_next_st structure\r
-#define NEXT_ST_NDA_31_6_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_next_st,nda_31_6)>>2\r
-#define NEXT_ST_NDS_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_next_st,nds)>>2\r
-\r
- // bit offsets within the given u_int32_t within wqe_segment_next_st\r
-#define BIT_MASK_FOR_NEXT_WQE_31SB (~MASK32(6)) \r
-#define NEXT_ST_NDS_BIT_OFFSET (MT_BIT_OFFSET(wqe_segment_next_st,nds) & 0x1f)\r
-#define NEXT_ST_DBD_BIT_OFFSET (MT_BIT_OFFSET(wqe_segment_next_st,dbd) & 0x1f)\r
-#define NEXT_ST_F_BIT_OFFSET (MT_BIT_OFFSET(wqe_segment_next_st,f) & 0x1f)\r
-#define NEXT_ST_NEE_BIT_OFFSET (MT_BIT_OFFSET(wqe_segment_next_st,nee) & 0x1f)\r
-/* Converted into Big Endian version */\r
-inline static u_int32_t WQE_pack_send_next_be(u_int32_t *segment_p, \r
- tavor_if_nopcode_t nopcode, MT_bool fence, u_int32_t dbd,\r
- u_int32_t next_wqe_32lsb, u_int32_t wqe_sz_16B_chunks,\r
- IB_eecn_t eecn)\r
-{\r
- segment_p[NEXT_ST_NDA_31_6_DWORD_OFFSET] = MOSAL_cpu_to_be32(0\r
- | (u_int32_t)nopcode\r
- | (next_wqe_32lsb & BIT_MASK_FOR_NEXT_WQE_31SB ));\r
- \r
- \r
- segment_p[NEXT_ST_NDS_DWORD_OFFSET] = MOSAL_cpu_to_be32(0 \r
- | (wqe_sz_16B_chunks << NEXT_ST_NDS_BIT_OFFSET ) // specify in 16 byte chunks\r
- | (fence << NEXT_ST_F_BIT_OFFSET )\r
- | (dbd << NEXT_ST_DBD_BIT_OFFSET)\r
- | (eecn << NEXT_ST_NEE_BIT_OFFSET)\r
- );\r
- return WQE_SEG_SZ_NEXT;\r
-}\r
-\r
-/* Pack Control segment (for sends) */\r
-inline static u_int32_t WQE_pack_ctrl_send(u_int32_t *segment_p, \r
- VAPI_comp_type_t comp_type, MT_bool se_bit, u_int32_t event_bit,\r
- u_int32_t imm_data)\r
-{\r
- memset(segment_p,0,WQE_SEG_SZ_CTRL); /* Clear all "RESERVED" */\r
- MT_INSERT_ARRAY32(segment_p,1,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_send_st,always1),MT_BIT_SIZE(wqe_segment_ctrl_send_st,always1));\r
- MT_INSERT_ARRAY32(segment_p,(comp_type == VAPI_SIGNALED) ? 1 : 0,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_send_st,c),MT_BIT_SIZE(wqe_segment_ctrl_send_st,c));\r
- MT_INSERT_ARRAY32(segment_p,se_bit ? 1 : 0,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_send_st,s),MT_BIT_SIZE(wqe_segment_ctrl_send_st,s));\r
- MT_INSERT_ARRAY32(segment_p,event_bit,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_send_st,e),MT_BIT_SIZE(wqe_segment_ctrl_send_st,e));\r
- segment_p[MT_BYTE_OFFSET(wqe_segment_ctrl_send_st,immediate)>>2]= imm_data;\r
- return WQE_SEG_SZ_CTRL;\r
-}\r
-\r
-/* Optimized vwerion of WQE_pack_ctrl_send\r
- * remove memset and pre-calculate offsets \r
- */\r
-#define CTRL_SEND_IMMEDIATE_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_ctrl_send_st,immediate)>>2\r
-#define CTRL_SEND_RESERVED0_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_ctrl_send_st,reserved0)>>2 \r
-#define CTRL_SEND_ALWAYS_BIT_OFFSET MT_BIT_OFFSET(wqe_segment_ctrl_send_st,always1)\r
-#define CTRL_SEND_S_BIT_OFFSET MT_BIT_OFFSET(wqe_segment_ctrl_send_st,s)\r
-#define CTRL_SEND_C_BIT_OFFSET MT_BIT_OFFSET(wqe_segment_ctrl_send_st,c)\r
-#define CTRL_SEND_E_BIT_OFFSET MT_BIT_OFFSET(wqe_segment_ctrl_send_st,e)\r
-\r
-inline static u_int32_t WQE_pack_ctrl_send_be(u_int32_t *segment_p, \r
- VAPI_comp_type_t comp_type, MT_bool se_bit, u_int32_t event_bit,\r
- u_int32_t imm_data)\r
-{\r
- \r
- u_int32_t *cur_loc_p = segment_p; \r
- segment_p[CTRL_SEND_RESERVED0_DWORD_OFFSET] = 0;\r
- WQE_IO_WRITE(&cur_loc_p[0], MOSAL_cpu_to_be32(0\r
- | (1 << CTRL_SEND_ALWAYS_BIT_OFFSET ) // this bit must be on\r
- | ((u_int32_t)(se_bit & 1) << CTRL_SEND_S_BIT_OFFSET ) // solicited event bit\r
- | (0 << CTRL_SEND_E_BIT_OFFSET ) // event bit is always zero right now\r
- | ((u_int32_t)((comp_type + 1) & 1) << CTRL_SEND_C_BIT_OFFSET ) \r
- ));\r
-\r
- WQE_IO_WRITE(&cur_loc_p[CTRL_SEND_IMMEDIATE_DWORD_OFFSET], imm_data);\r
-\r
- return WQE_SEG_SZ_CTRL;\r
-}\r
-\r
-inline static u_int32_t WQE_pack_ud(u_int32_t *segment_p,\r
- VAPI_lkey_t ud_av_memkey, u_int64_t ah, \r
- IB_wqpn_t destination_qp, IB_qkey_t q_key)\r
-{\r
- memset(segment_p,0,WQE_SEG_SZ_UD); /* Clear all "RESERVED" */\r
- segment_p[MT_BYTE_OFFSET(wqe_segment_ud_st,l_key)>>2]= ud_av_memkey;\r
- segment_p[MT_BYTE_OFFSET(wqe_segment_ud_st,av_address_63_32)>>2]= (u_int32_t)(ah>>32);\r
- segment_p[MT_BYTE_OFFSET(wqe_segment_ud_st,av_address_31_5)>>2]= ((u_int32_t)ah & (~MASK32(5)) );\r
- MT_INSERT_ARRAY32(segment_p,destination_qp,\r
- MT_BIT_OFFSET(wqe_segment_ud_st,destination_qp),\r
- MT_BIT_SIZE(wqe_segment_ud_st,destination_qp));\r
- segment_p[MT_BYTE_OFFSET(wqe_segment_ud_st,q_key)>>2]= q_key;\r
- return WQE_SEG_SZ_UD;\r
-}\r
-\r
-/* Optimized version of WQE_pack_ud\r
- * remove memset and pre-calculate offset\r
- */\r
-#define UD_ST_RESERV0_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_ud_st,reserved0)>>2 \r
-#define UD_ST_RESERV1_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_ud_st,reserved1)>>2 \r
-#define UD_ST_RESERV2_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_ud_st,reserved2)>>2\r
-#define UD_ST_RESERV2_DWORD_OFFSET1 ((MT_BYTE_OFFSET(wqe_segment_ud_st,reserved2)>>2)+ 1)\r
-#define UD_ST_RESERV2_DWORD_OFFSET2 ((MT_BYTE_OFFSET(wqe_segment_ud_st,reserved2)>>2)+ 2)\r
-#define UD_ST_RESERV2_DWORD_OFFSET3 ((MT_BYTE_OFFSET(wqe_segment_ud_st,reserved2)>>2)+ 3)\r
- \r
-#define UD_ST_RESERV3_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_ud_st,reserved3)>>2\r
-#define UD_ST_RESERV4_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_ud_st,reserved4)>>2\r
-#define UD_ST_RESERV4_DWORD_OFFSET1 ((MT_BYTE_OFFSET(wqe_segment_ud_st,reserved4)>>2) + 1)\r
-\r
-#define UD_ST_LKEY_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_ud_st,l_key)>>2\r
-#define UD_ST_ADDR_63_32_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_ud_st,av_address_63_32)>>2\r
-#define UD_ST_ADDR_31_5_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_ud_st,av_address_31_5)>>2\r
-#define UD_ST_DESTINATION_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_ud_st,destination_qp)>>2\r
-#define UD_ST_QKEY_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_ud_st,q_key)>>2\r
-#define UD_ST_AH_MASK (~MASK32(5))\r
-\r
-/* Convert into Big Endian version */\r
-inline static u_int32_t WQE_pack_ud_be(u_int32_t *segment_p,\r
- VAPI_lkey_t ud_av_memkey, u_int64_t ah, \r
- IB_wqpn_t destination_qp, IB_qkey_t q_key)\r
-{\r
- /* Clear all "RESERVED" */ \r
- /* zero out reserved fields, look at wqe_segment_ud_st in MT23108_PRM_append.h */ \r
- segment_p[UD_ST_RESERV0_DWORD_OFFSET] = 0;\r
- segment_p[UD_ST_RESERV1_DWORD_OFFSET] = 0;\r
- segment_p[UD_ST_RESERV2_DWORD_OFFSET] = 0;\r
- segment_p[UD_ST_RESERV2_DWORD_OFFSET1] = 0;\r
- segment_p[UD_ST_RESERV2_DWORD_OFFSET2] = 0;\r
- segment_p[UD_ST_RESERV2_DWORD_OFFSET3] = 0;\r
- \r
- segment_p[UD_ST_RESERV4_DWORD_OFFSET] = 0;\r
- segment_p[UD_ST_RESERV4_DWORD_OFFSET1] = 0;\r
-\r
- segment_p[UD_ST_LKEY_DWORD_OFFSET]= MOSAL_cpu_to_be32(ud_av_memkey);\r
- segment_p[UD_ST_ADDR_63_32_DWORD_OFFSET]= MOSAL_cpu_to_be32((u_int32_t)(ah>>32));\r
- segment_p[UD_ST_ADDR_31_5_DWORD_OFFSET]= MOSAL_cpu_to_be32(((u_int32_t)ah & UD_ST_AH_MASK ));\r
-#ifdef WIN32\r
- segment_p[UD_ST_DESTINATION_DWORD_OFFSET] = destination_qp;\r
- segment_p[UD_ST_QKEY_DWORD_OFFSET]= q_key;\r
-#else\r
- segment_p[UD_ST_DESTINATION_DWORD_OFFSET] = MOSAL_cpu_to_be32(destination_qp);\r
- segment_p[UD_ST_QKEY_DWORD_OFFSET]= MOSAL_cpu_to_be32(q_key);\r
-#endif \r
- return WQE_SEG_SZ_UD;\r
-}\r
-\r
-inline static u_int32_t WQE_pack_rd(u_int32_t *segment_p,\r
- IB_wqpn_t destination_qp, IB_qkey_t q_key)\r
-{\r
- memset(segment_p,0,WQE_SEG_SZ_RD); /* Clear all "RESERVED" */\r
- MT_INSERT_ARRAY32(segment_p,destination_qp,\r
- MT_BIT_OFFSET(wqe_segment_rd_st,destination_qp),\r
- MT_BIT_SIZE(wqe_segment_rd_st,destination_qp));\r
- segment_p[MT_BYTE_OFFSET(wqe_segment_rd_st,q_key)>>2]= q_key;\r
- return WQE_SEG_SZ_RD;\r
-}\r
-\r
-/* Optimized version \r
- * remove memset and pre-calculate offset\r
- */\r
-#define RD_ST_RESERV0_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_rd_st,reserved0)>>2 \r
-#define RD_ST_RESERV1_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_rd_st,reserved1)>>2 \r
-#define RD_ST_RESERV1_DWORD_OFFSET1 ((MT_BYTE_OFFSET(wqe_segment_rd_st,reserved1)>>2)+1) \r
-\r
-#define RD_ST_DESTINATION_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_rd_st,destination_qp)>>2\r
-#define RD_ST_QKEY_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_rd_st,q_key)>>2\r
-\r
-/* Convert into Big Endian version */\r
-inline static u_int32_t WQE_pack_rd_be(u_int32_t *segment_p,\r
- IB_wqpn_t destination_qp, IB_qkey_t q_key)\r
-{\r
- segment_p[RD_ST_RESERV1_DWORD_OFFSET] = 0;\r
- segment_p[RD_ST_RESERV1_DWORD_OFFSET1] = 0;\r
- \r
- segment_p[RD_ST_DESTINATION_DWORD_OFFSET]= MOSAL_cpu_to_be32(destination_qp);\r
- segment_p[RD_ST_QKEY_DWORD_OFFSET]= MOSAL_cpu_to_be32(q_key);\r
-\r
- return WQE_SEG_SZ_RD;\r
-}\r
-\r
-\r
-inline static u_int32_t WQE_pack_remote_addr(u_int32_t *segment_p,\r
- IB_virt_addr_t remote_addr, IB_rkey_t remote_rkey)\r
-{\r
- memset(segment_p,0,WQE_SEG_SZ_RADDR); /* Clear all "RESERVED" */\r
- segment_p[MT_BYTE_OFFSET(wqe_segment_remote_address_st,remote_virt_addr_h)>>2]= \r
- (u_int32_t)(remote_addr >> 32);\r
- segment_p[MT_BYTE_OFFSET(wqe_segment_remote_address_st,remote_virt_addr_l)>>2]= \r
- (u_int32_t)(remote_addr & 0xFFFFFFFF);\r
- segment_p[MT_BYTE_OFFSET(wqe_segment_remote_address_st,rkey)>>2]= remote_rkey;\r
- return WQE_SEG_SZ_RADDR;\r
-}\r
-\r
-\r
-/* Optimized version of WQE_pack_remote_addr\r
- * remove memset and pre-calculaute offset\r
- */\r
-#define REMOTE_ADR_ST_RESERV0_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_remote_address_st,reserved0)>>2 \r
-#define REMOTE_ADR_VIRT_ADDR_H_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_remote_address_st,remote_virt_addr_h)>>2\r
-#define REMOTE_ADR_VIRT_ADDR_L_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_remote_address_st,remote_virt_addr_l)>>2\r
-#define REMOTE_ADR_RKEY_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_remote_address_st,rkey)>>2 \r
-\r
-/* Convert into Big Endian version */\r
-inline static u_int32_t WQE_pack_remote_addr_be(u_int32_t *segment_p,\r
- IB_virt_addr_t remote_addr, IB_rkey_t remote_rkey)\r
-{\r
- segment_p[REMOTE_ADR_ST_RESERV0_DWORD_OFFSET] = 0; \r
- \r
- segment_p[REMOTE_ADR_VIRT_ADDR_H_DWORD_OFFSET]= \r
- MOSAL_cpu_to_be32((u_int32_t)(remote_addr >> 32));\r
- segment_p[REMOTE_ADR_VIRT_ADDR_L_DWORD_OFFSET]= \r
- MOSAL_cpu_to_be32((u_int32_t)(remote_addr));\r
- segment_p[REMOTE_ADR_RKEY_DWORD_OFFSET]= MOSAL_cpu_to_be32(remote_rkey);\r
-\r
- return WQE_SEG_SZ_RADDR;\r
-}\r
-/* this is same as WQE_pack_remote_addr but return number of DWORD(32bits)\r
- * written, instead bytes. \r
- */\r
-inline static u_int32_t WQE_pack_remote_addr_req2(u_int32_t *segment_p,\r
- IB_virt_addr_t remote_addr, IB_rkey_t remote_rkey)\r
-{\r
-#define WQE_SEG_SZ_RADDR_DWORD WQE_SEG_SZ_RADDR>>2 \r
- segment_p[REMOTE_ADR_ST_RESERV0_DWORD_OFFSET] = 0; \r
- \r
- segment_p[REMOTE_ADR_VIRT_ADDR_H_DWORD_OFFSET]= \r
- MOSAL_cpu_to_be32((u_int32_t)(remote_addr >> 32));\r
- segment_p[REMOTE_ADR_VIRT_ADDR_L_DWORD_OFFSET]= \r
- MOSAL_cpu_to_be32((u_int32_t)(remote_addr));\r
- segment_p[REMOTE_ADR_RKEY_DWORD_OFFSET]= MOSAL_cpu_to_be32(remote_rkey);\r
- \r
- return WQE_SEG_SZ_RADDR_DWORD;\r
-}\r
-\r
-inline static u_int32_t qpm_WQE_pack_recv_next(u_int32_t *segment_p, \r
- u_int32_t next_wqe_32lsb, u_int32_t wqe_sz_16B_chunks)\r
-{\r
- memset(segment_p,0,WQE_SEG_SZ_NEXT); /* Clear all "RESERVED" */\r
- segment_p[MT_BYTE_OFFSET(wqe_segment_next_st,nda_31_6)>>2]= ( next_wqe_32lsb & (~MASK32(6)) ) \r
- | 1 ; /* LS-bit is set to work around bug #16159/16160/16161 */;\r
- MT_INSERT_ARRAY32(segment_p,1, /* DBD always '1 for RQ */\r
- MT_BIT_OFFSET(wqe_segment_next_st,dbd),MT_BIT_SIZE(wqe_segment_next_st,dbd));\r
- MT_INSERT_ARRAY32(segment_p,wqe_sz_16B_chunks,\r
- MT_BIT_OFFSET(wqe_segment_next_st,nds),MT_BIT_SIZE(wqe_segment_next_st,nds));\r
- return WQE_SEG_SZ_NEXT;\r
-}\r
-\r
-/* Optimized Version */\r
-/* remove memset */\r
-/* pre calculation for WQE_pack_recv_next */\r
-#define NEXT_ST_NDA_31_6_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_next_st,nda_31_6)>>2\r
-#define NEXT_ST_NDS_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_next_st,nds)>>2\r
-\r
-#define BIT_MASK_FOR_NEXT_WQE_31SB (~MASK32(6)) \r
-\r
-inline static u_int32_t WQE_pack_recv_next_be(u_int32_t *segment_p, \r
- u_int32_t next_wqe_32lsb, u_int32_t wqe_sz_16B_chunks)\r
-{\r
- \r
- segment_p[NEXT_ST_NDA_31_6_DWORD_OFFSET] = MOSAL_cpu_to_be32(0\r
- | (next_wqe_32lsb & BIT_MASK_FOR_NEXT_WQE_31SB ));\r
- segment_p[NEXT_ST_NDS_DWORD_OFFSET] = MOSAL_cpu_to_be32(0 \r
- | (wqe_sz_16B_chunks << NEXT_ST_NDS_BIT_OFFSET ) // specify in 16 byte chunks\r
- | (1 << NEXT_ST_DBD_BIT_OFFSET)\r
- );\r
- \r
- return WQE_SEG_SZ_NEXT;\r
-}\r
-\r
-inline static u_int32_t WQE_pack_atomic_cmpswp(u_int32_t *segment_p,\r
- u_int64_t cmp_data, u_int64_t swap_data)\r
-{\r
- segment_p[MT_BYTE_OFFSET(wqe_segment_atomic_st,swap_add_h)>>2]= (u_int32_t)(swap_data >> 32);\r
- segment_p[MT_BYTE_OFFSET(wqe_segment_atomic_st,swap_add_l)>>2]= (u_int32_t)(swap_data & 0xFFFFFFFF);\r
- segment_p[MT_BYTE_OFFSET(wqe_segment_atomic_st,compare_h)>>2]= (u_int32_t)(cmp_data >> 32);\r
- segment_p[MT_BYTE_OFFSET(wqe_segment_atomic_st,compare_l)>>2]= (u_int32_t)(cmp_data & 0xFFFFFFFF);\r
- return WQE_SEG_SZ_ATOMIC;\r
-}\r
-\r
-#define ATOMIC_ST_SWAP_ADDR_H_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_atomic_st,swap_add_h)>>2\r
-#define ATOMIC_ST_SWAP_ADDR_L_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_atomic_st,swap_add_l)>>2\r
-#define ATOMIC_ST_COMPARE_H_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_atomic_st,compare_h)>>2\r
-#define ATOMIC_ST_CPMPARE_L_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_atomic_st,compare_l)>>2\r
-/* Convert into Big Endian version */\r
-inline static u_int32_t WQE_pack_atomic_cmpswp_be(u_int32_t *segment_p,\r
- u_int64_t cmp_data, u_int64_t swap_data)\r
-{ \r
- segment_p[ATOMIC_ST_SWAP_ADDR_H_DWORD_OFFSET]= MOSAL_cpu_to_be32((u_int32_t)(swap_data >> 32));\r
- segment_p[ATOMIC_ST_SWAP_ADDR_L_DWORD_OFFSET]= MOSAL_cpu_to_be32((u_int32_t)(swap_data ));\r
- segment_p[ATOMIC_ST_COMPARE_H_DWORD_OFFSET]= MOSAL_cpu_to_be32((u_int32_t)(cmp_data >> 32));\r
- segment_p[ATOMIC_ST_CPMPARE_L_DWORD_OFFSET]= MOSAL_cpu_to_be32((u_int32_t)(cmp_data ));\r
-\r
- return WQE_SEG_SZ_ATOMIC;\r
-}\r
-\r
-inline static u_int32_t WQE_pack_atomic_fetchadd(u_int32_t *segment_p,u_int64_t add_data)\r
-{\r
- segment_p[MT_BYTE_OFFSET(wqe_segment_atomic_st,swap_add_h)>>2]= (u_int32_t)(add_data >> 32);\r
- segment_p[MT_BYTE_OFFSET(wqe_segment_atomic_st,swap_add_l)>>2]= (u_int32_t)(add_data & 0xFFFFFFFF);\r
- return WQE_SEG_SZ_ATOMIC;\r
-}\r
-\r
-#define ATOMIC_ST_SWAP_ADDR_H_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_atomic_st,swap_add_h)>>2\r
-#define ATOMIC_ST_SWAP_ADDR_L_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_atomic_st,swap_add_l)>>2\r
-/* Convert into Big Endian version */\r
-inline static u_int32_t WQE_pack_atomic_fetchadd_be(u_int32_t *segment_p,u_int64_t add_data)\r
-{\r
- segment_p[ATOMIC_ST_SWAP_ADDR_H_DWORD_OFFSET]= MOSAL_cpu_to_be32((u_int32_t)(add_data >> 32));\r
- segment_p[ATOMIC_ST_SWAP_ADDR_L_DWORD_OFFSET]= MOSAL_cpu_to_be32((u_int32_t)(add_data & 0xFFFFFFFF));\r
- \r
- return WQE_SEG_SZ_ATOMIC;\r
-}\r
-\r
-/* Build the scatter/gather list (pointer segments) */\r
-#define DATA_PTR_BYTE_COUNT_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_data_ptr_st,byte_count)>>2\r
-#define DATA_PTR_LKEY_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_data_ptr_st,l_key)>>2\r
-#define DATA_PTR_LOCAL_ADDR_H_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_data_ptr_st,local_address_h)>>2\r
-#define DATA_PTR_LOCAL_ADDR_L_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_data_ptr_st,local_address_l)>>2\r
-#define DATA_PTR_LEN_MASK MASK32(31) \r
-\r
-inline static u_int32_t WQE_pack_sg_list(u_int32_t *segment_p,\r
- u_int32_t sg_lst_len,VAPI_sg_lst_entry_t *sg_lst_p)\r
-{\r
- u_int32_t i;\r
- u_int32_t *cur_loc_p= segment_p;\r
-\r
- for (i= 0; i < sg_lst_len; i++ , cur_loc_p+= WQE_SEG_SZ_SG_ENTRY_DW) {\r
- cur_loc_p[MT_BYTE_OFFSET(wqe_segment_data_ptr_st,byte_count)>>2]= \r
- (sg_lst_p[i].len & MASK32(31));\r
- cur_loc_p[MT_BYTE_OFFSET(wqe_segment_data_ptr_st,l_key)>>2]= sg_lst_p[i].lkey;\r
- cur_loc_p[MT_BYTE_OFFSET(wqe_segment_data_ptr_st,local_address_h)>>2]= \r
- (u_int32_t)(sg_lst_p[i].addr >> 32);\r
- cur_loc_p[MT_BYTE_OFFSET(wqe_segment_data_ptr_st,local_address_l)>>2]= \r
- (u_int32_t)(sg_lst_p[i].addr & 0xFFFFFFFF);\r
- }\r
- return (u_int32_t)(((MT_virt_addr_t)cur_loc_p) - ((MT_virt_addr_t)segment_p));\r
-}\r
-\r
-/* Convert into Big Endian version */\r
-inline static u_int32_t WQE_pack_sg_list_be(u_int32_t *segment_p,\r
- u_int32_t sg_lst_len,VAPI_sg_lst_entry_t *sg_lst_p)\r
-{\r
- u_int32_t i;\r
- u_int32_t *cur_loc_p= segment_p;\r
- \r
- for (i= 0; i < sg_lst_len; i++ , cur_loc_p+= WQE_SEG_SZ_SG_ENTRY_DW) {\r
- cur_loc_p[DATA_PTR_BYTE_COUNT_DWORD_OFFSET]= \r
- MOSAL_cpu_to_be32((sg_lst_p[i].len & DATA_PTR_LEN_MASK ));\r
- cur_loc_p[DATA_PTR_LKEY_DWORD_OFFSET]= MOSAL_cpu_to_be32(sg_lst_p[i].lkey);\r
- cur_loc_p[DATA_PTR_LOCAL_ADDR_H_DWORD_OFFSET]= \r
- MOSAL_cpu_to_be32((u_int32_t)(sg_lst_p[i].addr >> 32));\r
- cur_loc_p[DATA_PTR_LOCAL_ADDR_L_DWORD_OFFSET]= \r
- MOSAL_cpu_to_be32((u_int32_t)(sg_lst_p[i].addr));\r
- }\r
- return (u_int32_t)(((MT_ulong_ptr_t)cur_loc_p) - ((MT_ulong_ptr_t)segment_p));\r
-}\r
-\r
-/* Build the WQE in given wqe_buf.\r
- * Return WQE size.\r
- */\r
-inline static u_int32_t WQE_build_send(\r
- THHUL_qp_t qp,\r
- VAPI_sr_desc_t *send_req_p,\r
- u_int32_t *wqe_buf)\r
-{\r
- u_int8_t *cur_loc_p= (u_int8_t*)wqe_buf; /* Current location in the WQE */\r
-\r
- cur_loc_p+= qpm_WQE_init_next((u_int32_t*)cur_loc_p); /* Make "unlinked" "next" segment */\r
- cur_loc_p+= WQE_pack_ctrl_send((u_int32_t*)cur_loc_p, /* Pack Control segment */\r
- send_req_p->comp_type, send_req_p->set_se, 0/*event bit*/,\r
- ((send_req_p->opcode == VAPI_RDMA_WRITE_WITH_IMM) ||\r
- (send_req_p->opcode == VAPI_SEND_WITH_IMM) ) ? send_req_p->imm_data : 0);\r
-\r
- /* Transport type checks: Datagram segment */\r
- switch (qp->ts_type) {\r
- case VAPI_TS_UD: /* Check if UD (UD datagram segment) */\r
- cur_loc_p+= WQE_pack_ud((u_int32_t*)cur_loc_p,\r
- qp->ud_av_memkey,translate_av(qp, (u_int64_t)send_req_p->remote_ah),\r
- send_req_p->remote_qp,send_req_p->remote_qkey);\r
- break;\r
- case VAPI_TS_RD: /* Check if RD (RD datagram segment) */\r
- cur_loc_p+= WQE_pack_rd((u_int32_t*)cur_loc_p,\r
- send_req_p->remote_qp,send_req_p->remote_qkey);\r
- break;\r
- default:\r
- break;\r
- }\r
- \r
- /* Opcode checks Remote-address/Atomic segments */\r
- switch (send_req_p->opcode) {\r
- /* For RDMA operations: only Remote-address segment */\r
- case VAPI_RDMA_READ:\r
- case VAPI_RDMA_WRITE:\r
- case VAPI_RDMA_WRITE_WITH_IMM:\r
- cur_loc_p+= WQE_pack_remote_addr((u_int32_t*)cur_loc_p,\r
- send_req_p->remote_addr,send_req_p->r_key);\r
- break;\r
- \r
- /* Check if Atomic operations (both remote-address and Atomic segments) */\r
- case VAPI_ATOMIC_CMP_AND_SWP:\r
- cur_loc_p+= WQE_pack_remote_addr((u_int32_t*)cur_loc_p,send_req_p->remote_addr,\r
- send_req_p->r_key);\r
- cur_loc_p+= WQE_pack_atomic_cmpswp((u_int32_t*)cur_loc_p,send_req_p->compare_add,\r
- send_req_p->swap);\r
- break;\r
- case VAPI_ATOMIC_FETCH_AND_ADD:\r
- cur_loc_p+= WQE_pack_remote_addr((u_int32_t*)cur_loc_p,send_req_p->remote_addr,\r
- send_req_p->r_key);\r
- cur_loc_p+= WQE_pack_atomic_fetchadd((u_int32_t*)cur_loc_p,send_req_p->compare_add);\r
- break;\r
- default: /*NOP*/\r
- break;\r
- }\r
- \r
- /* Pack scatter/gather list segments */\r
- cur_loc_p+= WQE_pack_sg_list((u_int32_t*)cur_loc_p,send_req_p->sg_lst_len,send_req_p->sg_lst_p);\r
- \r
- return (u_int32_t)(((MT_virt_addr_t)cur_loc_p) - ((MT_virt_addr_t)wqe_buf));\r
-}\r
- \r
- \r
-/* Build Big Endian version of WQE_build_send\r
- * to remove extra copy from wqe_draft to wqe_buf.\r
- */\r
-inline static u_int32_t WQE_build_send_be(\r
- THHUL_qp_t qp,\r
- VAPI_sr_desc_t *send_req_p,\r
- u_int32_t *wqe_buf)\r
-{\r
- u_int8_t *cur_loc_p= (u_int8_t*)wqe_buf; /* Current location in the WQE */\r
-\r
- cur_loc_p+= qpm_WQE_init_next((u_int32_t*)cur_loc_p); /* Make "unlinked" "next" segment */\r
- cur_loc_p+= WQE_pack_ctrl_send_be((u_int32_t*)cur_loc_p, /* Pack Control segment */\r
- send_req_p->comp_type, send_req_p->set_se, 0/*event bit*/,\r
- ((send_req_p->opcode == VAPI_RDMA_WRITE_WITH_IMM) ||\r
- (send_req_p->opcode == VAPI_SEND_WITH_IMM) ) ? send_req_p->imm_data : 0);\r
-\r
- /* Transport type checks: Datagram segment */\r
- switch (qp->ts_type) {\r
- case VAPI_TS_UD: /* Check if UD (UD datagram segment) */\r
- cur_loc_p+= WQE_pack_ud_be((u_int32_t*)cur_loc_p,\r
- qp->ud_av_memkey,translate_av(qp, (u_int64_t)send_req_p->remote_ah),\r
- send_req_p->remote_qp,send_req_p->remote_qkey);\r
- break;\r
- case VAPI_TS_RD: /* Check if RD (RD datagram segment) */\r
- cur_loc_p+= WQE_pack_rd_be((u_int32_t*)cur_loc_p,\r
- send_req_p->remote_qp,send_req_p->remote_qkey);\r
- break;\r
- default:\r
- break;\r
- }\r
- \r
- /* Opcode checks Remote-address/Atomic segments */\r
- switch (send_req_p->opcode) {\r
- /* For RDMA operations: only Remote-address segment */\r
- case VAPI_RDMA_READ:\r
- case VAPI_RDMA_WRITE:\r
- case VAPI_RDMA_WRITE_WITH_IMM:\r
- cur_loc_p+= WQE_pack_remote_addr_be((u_int32_t*)cur_loc_p,\r
- send_req_p->remote_addr,send_req_p->r_key);\r
- break;\r
- \r
- /* Check if Atomic operations (both remote-address and Atomic segments) */\r
- case VAPI_ATOMIC_CMP_AND_SWP:\r
- cur_loc_p+= WQE_pack_remote_addr_be((u_int32_t*)cur_loc_p,send_req_p->remote_addr,\r
- send_req_p->r_key);\r
- cur_loc_p+= WQE_pack_atomic_cmpswp_be((u_int32_t*)cur_loc_p,send_req_p->compare_add,\r
- send_req_p->swap);\r
- break;\r
- case VAPI_ATOMIC_FETCH_AND_ADD:\r
- cur_loc_p+= WQE_pack_remote_addr_be((u_int32_t*)cur_loc_p,send_req_p->remote_addr,\r
- send_req_p->r_key);\r
- cur_loc_p+= WQE_pack_atomic_fetchadd_be((u_int32_t*)cur_loc_p,send_req_p->compare_add);\r
- break;\r
- default: /*NOP*/\r
- break;\r
- }\r
- \r
- /* Pack scatter/gather list segments */\r
- if(MOSAL_EXPECT_FALSE(send_req_p->sg_lst_len == 0 || send_req_p->sg_lst_p->len == 0))\r
- return (u_int32_t)(((MT_ulong_ptr_t)cur_loc_p) - ((MT_ulong_ptr_t)wqe_buf));\r
-\r
- cur_loc_p+= WQE_pack_sg_list_be((u_int32_t*)cur_loc_p,send_req_p->sg_lst_len,send_req_p->sg_lst_p);\r
- \r
- return (u_int32_t)(((MT_ulong_ptr_t)cur_loc_p) - ((MT_ulong_ptr_t)wqe_buf));\r
-}\r
-\r
-\r
-\r
-/* This is optimized version of WQE_build_send \r
- * This fcuntion can eliminate extra code because req2 \r
- * ony support ReliableConnection and UnrliableDatagram.\r
- * sg_list and remote_addr build is done seperate fcuntion,\r
- * which use IbAccess structure directly. See thhul_qpm_iba.h\r
- */\r
-inline static u_int32_t* WQE_build_send_be_req2(\r
- THHUL_qp_t qp, \r
- u_int32_t *wqe_buf,\r
- VAPI_comp_type_t comp_type,\r
- u_int64_t remote_ah,\r
- IB_wqpn_t remote_qp,\r
- IB_qkey_t remote_qkey, \r
- MT_bool set_se,\r
- u_int32_t imm_data \r
- )\r
-{\r
- u_int8_t *cur_loc_p= (u_int8_t*)wqe_buf; /* Current location in the WQE */\r
-\r
- cur_loc_p+= qpm_WQE_init_next((u_int32_t*)cur_loc_p); /* Make "unlinked" "next" segment */\r
- cur_loc_p+= WQE_pack_ctrl_send_be((u_int32_t*)cur_loc_p, /* Pack Control segment */\r
- comp_type, set_se, 0/*event bit*/,\r
- imm_data);\r
-\r
- /* Transport type checks: Datagram segment */\r
- /* Req2 suport only ReliableConnection and UnrliableDatagram */ \r
- if(MOSAL_EXPECT_FALSE(qp->ts_type == VAPI_TS_UD))\r
- {\r
- /* Check if UD (UD datagram segment) */\r
- cur_loc_p+= WQE_pack_ud_be((u_int32_t*)cur_loc_p,\r
- qp->ud_av_memkey,translate_av(qp, (u_int64_t)remote_ah),\r
- remote_qp,remote_qkey);\r
- }\r
- return (u_int32_t*)cur_loc_p;\r
-}\r
-\r
-\r
-\r
-/* This is optimized version of WQE_build_send \r
- * This function can eliminate extra code because req3 \r
- * ony support ReliableConnection and UnrliableDatagram.\r
- * sg_list and remote_addr build is done seperate fcuntion,\r
- * which use IBAL structure directly. See thhul_qpm_ibal.h\r
- */\r
-inline static u_int32_t* WQE_build_send_be_req3(\r
- THHUL_qp_t qp, \r
- u_int32_t *wqe_buf,\r
- VAPI_comp_type_t comp_type,\r
- ib_send_wr_t *p_wr,\r
- MT_bool set_se,\r
- u_int32_t imm_data \r
- )\r
-{\r
- u_int8_t *cur_loc_p= (u_int8_t*)wqe_buf; /* Current location in the WQE */\r
-\r
- cur_loc_p+= qpm_WQE_init_next((u_int32_t*)cur_loc_p); /* Make "unlinked" "next" segment */\r
- cur_loc_p+= WQE_pack_ctrl_send_be((u_int32_t*)cur_loc_p, /* Pack Control segment */\r
- comp_type, set_se, 0/*event bit*/,\r
- imm_data);\r
-\r
- /* Transport type checks: Datagram segment */\r
- /* Req3 suport only ReliableConnection and UnrliableDatagram */ \r
- if(MOSAL_EXPECT_FALSE(qp->ts_type == VAPI_TS_UD))\r
- {\r
- /* Check if UD (UD datagram segment) */\r
- cur_loc_p+= WQE_pack_ud_be((u_int32_t*)cur_loc_p,\r
- qp->ud_av_memkey,\r
- translate_av(qp, (u_int64_t)p_wr->dgrm.ud.h_av->h_av),\r
- p_wr->dgrm.ud.remote_qp, p_wr->dgrm.ud.remote_qkey);\r
- }\r
- return (u_int32_t*)cur_loc_p;\r
-}\r
-\r
-\r
-/* Build UD header as inline data for management QPs over MLX "transport" */\r
-inline static u_int32_t WQE_pack_mlx_ud_header(u_int32_t *segment_p,\r
- THHUL_qp_t qp, VAPI_sr_desc_t *send_req_p, VAPI_ud_av_t *av_p, HH_hca_hndl_t hh_hndl,\r
- VAPI_pkey_ix_t pkey_index /* take this index instead of QP's, if not QP1_PKEY_INDEX */)\r
-{\r
- MPGA_headers_t *hdrs;\r
- IB_LRH_st *LRH_p;\r
- IB_BTH_st *BTH_p;\r
- IB_DETH_st *DETH_p;\r
- u_int8_t *hdrs_buf_p;\r
-#ifdef MT_LITTLE_ENDIAN\r
- u_int32_t *hdrs_buf32_p; /* pointer for endiness swapping */\r
- u_int16_t i;\r
-#endif\r
- u_int16_t hdrs_sz;\r
- MT_bool global= av_p->grh_flag;\r
-#ifdef MT_KERNEL\r
- IB_port_t num_ports;\r
- IB_port_t port= (qp->qpn & 0xf); /* QPN of QP used for port 1 has the even index */\r
- IB_pkey_t cur_pkey= 0;\r
- HH_ret_t rc;\r
- \r
- rc= THH_hob_get_num_ports(hh_hndl,&num_ports);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("Could not get number of HCA ports (%s).\n"),HH_strerror_sym(rc));\r
- return 0;\r
- }\r
- port = (port >= num_ports) ? ((port-num_ports)%num_ports)+1 : (port % num_ports)+1;\r
-#endif\r
-\r
- hdrs_sz= IB_LRH_LEN+IB_BTH_LEN+IB_DETH_LEN;\r
- if (global) hdrs_sz+= IB_GRH_LEN;\r
-\r
- /* Set inline entry control */\r
- *segment_p= ((1<<31) | hdrs_sz) ; /* inline entry | ByteCount */\r
- hdrs_buf_p= ((u_int8_t*)segment_p) + WQE_INLINE_SZ_BCOUNT /* inline ctrl */ + hdrs_sz;\r
-\r
- /* Put headers data into MPGA structures */ \r
- hdrs = &qp->sq_res.wqe_tmp->hdrs;\r
- if (global) {\r
- LRH_p= &(hdrs->MPGA_G_ud_send_only.IB_LRH);\r
- BTH_p= &(hdrs->MPGA_G_ud_send_only.IB_BTH);\r
- DETH_p= &(hdrs->MPGA_G_ud_send_only.IB_DETH);\r
- /* Set GRH fields */\r
- hdrs->MPGA_G_ud_send_only.IB_GRH.IPVer= 6; /* ? */\r
- hdrs->MPGA_G_ud_send_only.IB_GRH.TClass= av_p->traffic_class;\r
- hdrs->MPGA_G_ud_send_only.IB_GRH.FlowLabel= av_p->flow_label;\r
- hdrs->MPGA_G_ud_send_only.IB_GRH.PayLen= IB_BTH_LEN+IB_DETH_LEN+IB_MAD_LEN+IB_ICRC_SZ;\r
- hdrs->MPGA_G_ud_send_only.IB_GRH.NxtHdr= 0x1B; /* IB-spec.: compliancy statement C8-7 */\r
- hdrs->MPGA_G_ud_send_only.IB_GRH.HopLmt= av_p->hop_limit; \r
- memcpy(&(hdrs->MPGA_G_ud_send_only.IB_GRH.DGID),&(av_p->dgid),sizeof(IB_gid_t));\r
-#ifdef MT_KERNEL\r
- /* SGID field is supported only in kernel space, due to limited access to the GID table */\r
- rc= THH_hob_get_sgid(hh_hndl,port,av_p->sgid_index,\r
- &(hdrs->MPGA_G_ud_send_only.IB_GRH.SGID));\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("Error in GID table access (%s).\n"),HH_strerror_sym(rc));\r
- return 0;\r
- }\r
-#endif\r
-\r
- } else { /* local - no GRH */\r
- LRH_p= &(hdrs->MPGA_ud_send_only.IB_LRH);\r
- BTH_p= &(hdrs->MPGA_ud_send_only.IB_BTH);\r
- DETH_p= &(hdrs->MPGA_ud_send_only.IB_DETH);\r
- }\r
- \r
- /* Set LRH fields */\r
- memset(LRH_p,0,sizeof(IB_LRH_st));\r
- /* VL must be set for internal loopback ("vl15" bit is ignored) */\r
- if (qp->sqp_type == VAPI_SMI_QP) LRH_p->VL= 15;\r
- else LRH_p->VL= 0;\r
- LRH_p->LVer= 0;\r
- LRH_p->SL= av_p->sl;\r
- LRH_p->LNH= global ? IBA_GLOBAL : IBA_LOCAL;\r
-\r
- LRH_p->DLID= av_p->dlid;\r
- LRH_p->SLID= (av_p->dlid == PERMIS_LID) ? PERMIS_LID : (IB_lid_t) av_p->src_path_bits;\r
- /* If DLID is permissive LID, we set SLID to the permissive LID too. */\r
- /* Otherwise, we put in the SLID field the source path bits, and SLR=0, so */ \r
- /* the LID is composed of actual port's LID concatenated with given path bits */\r
-\r
- LRH_p->PktLen= (hdrs_sz+IB_MAD_LEN + IB_ICRC_SZ) >> 2;\r
- /* Set BTH fields */\r
- memset(BTH_p,0,sizeof(IB_BTH_st));\r
- BTH_p->OpCode= UD_SEND_ONLY_OP;\r
- BTH_p->SE= send_req_p->set_se;\r
- BTH_p->M= 1;\r
- BTH_p->PadCnt= 0; /* MADs are always 4byte multiple */\r
- BTH_p->TVer= 0; \r
-#ifdef MT_KERNEL\r
- if (qp->sqp_type == VAPI_GSI_QP) {\r
- if (pkey_index == QP1_PKEY_INDEX) { /* use QP's pkey */\r
- rc= THH_hob_get_qp1_pkey(hh_hndl,port,&cur_pkey);\r
- } else {\r
- rc= THH_hob_get_pkey(hh_hndl,port,pkey_index,&cur_pkey);\r
- }\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: Error in P-key table access (%s) - using pkey_index 0x%X.\n"),__func__,\r
- HH_strerror_sym(rc),pkey_index);\r
- return 0;\r
- }\r
- } else {\r
- cur_pkey = DEFAULT_PKEY;\r
- }\r
- BTH_p->P_KEY= cur_pkey; \r
-#else\r
- BTH_p->P_KEY= DEFAULT_PKEY; /* For user space we do not have access to the Pkey table */\r
-#endif\r
- BTH_p->DestQP= send_req_p->remote_qp;\r
- /* AckReq and PSN are meaningless for UD */\r
- /* Set DETH fields */\r
- memset(DETH_p,0,sizeof(IB_DETH_st));\r
- DETH_p->SrcQP= (qp->sqp_type == VAPI_SMI_QP) ? 0 : 1; /* invoked only for SMI or GSI */ \r
- /* Qkey should be set according to IB-Spec. compliancy statement C10-15, But... \r
- * Only QP1/GSI is the special QP which really validates Q-keys and it always uses\r
- * 0x80010000 (C9-49). So for QP1 we always put this if the high-order bit of the Qkey\r
- * is set. */\r
- if (qp->sqp_type == VAPI_GSI_QP) {\r
- DETH_p->Q_Key= (send_req_p->remote_qkey & 0x80000000) ? 0x80010000: send_req_p->remote_qkey;\r
- } else { /* QP0 */\r
- /* For QP0 we don't care (QP0 always sends to another QP0 - none of which validates the Qkey) */\r
- DETH_p->Q_Key= send_req_p->remote_qkey; \r
- }\r
-\r
- /* Build the headers */\r
- if (MPGA_make_headers(hdrs,UD_SEND_ONLY_OP,\r
- LRH_p->LNH,FALSE,IB_MAD_LEN,&hdrs_buf_p) != MT_OK) {\r
- return 0;\r
- }\r
- /* Verify headers size */\r
- if (hdrs_buf_p != (((u_int8_t*)segment_p) + WQE_INLINE_SZ_BCOUNT)) {/*Should be segment begin*/\r
- MTL_ERROR2(MT_FLFMT("Error in headers size (%d instead of %d).\n"),\r
- (unsigned) (hdrs_sz - (hdrs_buf_p - (((u_int8_t*)segment_p) + 4))), hdrs_sz);\r
- return 0;\r
- }\r
-\r
-#ifdef MT_LITTLE_ENDIAN\r
- /* MPGA headers returned in BIG endian. WQE is built in CPU endianess - so swap bytes */\r
- for (i= 0 , hdrs_buf32_p= (u_int32_t*)hdrs_buf_p; i < (hdrs_sz>>2); i++) {\r
- hdrs_buf32_p[i]= MOSAL_cpu_to_be32(hdrs_buf32_p[i]);\r
- }\r
-#endif\r
-\r
- return MT_UP_ALIGNX_U32(WQE_INLINE_SZ_BCOUNT + hdrs_sz , 4); /* Align to WQE segment size */\r
-}\r
-\r
-/* Build UD header as inline data for management QPs over MLX "transport" */\r
-inline static u_int32_t WQE_pack_mlx_ud_header2(u_int32_t *segment_p,\r
- THHUL_qp_t qp, ib_send_wr_t* p_wr, VAPI_ud_av_t *av_p, HH_hca_hndl_t hh_hndl,\r
- VAPI_pkey_ix_t pkey_index /* take this index instead of QP's, if not QP1_PKEY_INDEX */)\r
-{\r
- MPGA_headers_t *hdrs;\r
- IB_LRH_st *LRH_p;\r
- IB_BTH_st *BTH_p;\r
- IB_DETH_st *DETH_p;\r
- u_int8_t *hdrs_buf_p;\r
-#ifdef MT_LITTLE_ENDIAN\r
- u_int32_t *hdrs_buf32_p; /* pointer for endiness swapping */\r
- u_int16_t i;\r
-#endif\r
- u_int16_t hdrs_sz;\r
- MT_bool global= av_p->grh_flag;\r
-#ifdef MT_KERNEL\r
- IB_port_t port= 1 + (qp->qpn & 1); /* QPN of QP used for port 1 has the even index */\r
- IB_pkey_t cur_pkey= 0;\r
- HH_ret_t rc;\r
-#endif\r
-\r
- hdrs_sz= IB_LRH_LEN+IB_BTH_LEN+IB_DETH_LEN;\r
- if (global) hdrs_sz+= IB_GRH_LEN;\r
-\r
- /* Set inline entry control */\r
- *segment_p= ((1<<31) | hdrs_sz) ; /* inline entry | ByteCount */\r
- hdrs_buf_p= ((u_int8_t*)segment_p) + WQE_INLINE_SZ_BCOUNT /* inline ctrl */ + hdrs_sz;\r
-\r
- /* Put headers data into MPGA structures */ \r
- hdrs = &qp->sq_res.wqe_tmp->hdrs;\r
- if (global) {\r
- LRH_p= &(hdrs->MPGA_G_ud_send_only.IB_LRH);\r
- BTH_p= &(hdrs->MPGA_G_ud_send_only.IB_BTH);\r
- DETH_p= &(hdrs->MPGA_G_ud_send_only.IB_DETH);\r
- /* Set GRH fields */\r
- hdrs->MPGA_G_ud_send_only.IB_GRH.IPVer= 6; /* ? */\r
- hdrs->MPGA_G_ud_send_only.IB_GRH.TClass= av_p->traffic_class;\r
- hdrs->MPGA_G_ud_send_only.IB_GRH.FlowLabel= av_p->flow_label;\r
- hdrs->MPGA_G_ud_send_only.IB_GRH.PayLen= IB_BTH_LEN+IB_DETH_LEN+IB_MAD_LEN+IB_ICRC_SZ;\r
- hdrs->MPGA_G_ud_send_only.IB_GRH.NxtHdr= 0x1B; /* IB-spec.: compliancy statement C8-7 */\r
- hdrs->MPGA_G_ud_send_only.IB_GRH.HopLmt= av_p->hop_limit; \r
- memcpy(&(hdrs->MPGA_G_ud_send_only.IB_GRH.DGID),&(av_p->dgid),sizeof(IB_gid_t));\r
-#ifdef MT_KERNEL\r
- /* SGID field is supported only in kernel space, due to limited access to the GID table */\r
- rc= THH_hob_get_sgid(hh_hndl,port,av_p->sgid_index,\r
- &(hdrs->MPGA_G_ud_send_only.IB_GRH.SGID));\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("Error in GID table access (%s).\n"),HH_strerror_sym(rc));\r
- return 0;\r
- }\r
-#endif\r
-\r
- } else { /* local - no GRH */\r
- LRH_p= &(hdrs->MPGA_ud_send_only.IB_LRH);\r
- BTH_p= &(hdrs->MPGA_ud_send_only.IB_BTH);\r
- DETH_p= &(hdrs->MPGA_ud_send_only.IB_DETH);\r
- }\r
- \r
- /* Set LRH fields */\r
- memset(LRH_p,0,sizeof(IB_LRH_st));\r
- /* VL must be set for internal loopback ("vl15" bit is ignored) */\r
- if (qp->sqp_type == VAPI_SMI_QP) LRH_p->VL= 15;\r
- else LRH_p->VL= 0;\r
- LRH_p->LVer= 0;\r
- LRH_p->SL= av_p->sl;\r
- LRH_p->LNH= global ? IBA_GLOBAL : IBA_LOCAL;\r
-\r
- LRH_p->DLID= av_p->dlid;\r
- LRH_p->SLID= (av_p->dlid == PERMIS_LID) ? PERMIS_LID : (IB_lid_t) av_p->src_path_bits;\r
- /* If DLID is permissive LID, we set SLID to the permissive LID too. */\r
- /* Otherwise, we put in the SLID field the source path bits, and SLR=0, so */ \r
- /* the LID is composed of actual port's LID concatenated with given path bits */\r
-\r
- LRH_p->PktLen= (hdrs_sz+IB_MAD_LEN + IB_ICRC_SZ) >> 2;\r
- /* Set BTH fields */\r
- memset(BTH_p,0,sizeof(IB_BTH_st));\r
- BTH_p->OpCode= UD_SEND_ONLY_OP;\r
- BTH_p->SE= ((p_wr->send_opt & IB_SEND_OPT_SOLICITED) == IB_SEND_OPT_SOLICITED);\r
- BTH_p->M= 1;\r
- BTH_p->PadCnt= 0; /* MADs are always 4byte multiple */\r
- BTH_p->TVer= 0; \r
-#ifdef MT_KERNEL\r
- if (qp->sqp_type == VAPI_GSI_QP) {\r
- if (pkey_index == QP1_PKEY_INDEX) { /* use QP's pkey */\r
- rc= THH_hob_get_qp1_pkey(hh_hndl,port,&cur_pkey);\r
- } else {\r
- rc= THH_hob_get_pkey(hh_hndl,port,pkey_index,&cur_pkey);\r
- }\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: Error in P-key table access (%s) - using pkey_index 0x%X.\n"),__func__,\r
- HH_strerror_sym(rc),pkey_index);\r
- return 0;\r
- }\r
- } else {\r
- cur_pkey = DEFAULT_PKEY;\r
- }\r
- BTH_p->P_KEY= cur_pkey; \r
-#else\r
- BTH_p->P_KEY= DEFAULT_PKEY; /* For user space we do not have access to the Pkey table */\r
-#endif\r
- BTH_p->DestQP= cl_hton32( p_wr->dgrm.ud.remote_qp );\r
- /* AckReq and PSN are meaningless for UD */\r
- /* Set DETH fields */\r
- memset(DETH_p,0,sizeof(IB_DETH_st));\r
- DETH_p->SrcQP= (qp->sqp_type == VAPI_SMI_QP) ? 0 : 1; /* invoked only for SMI or GSI */ \r
- /* Qkey should be set according to IB-Spec. compliancy statement C10-15, But... \r
- * Only QP1/GSI is the special QP which really validates Q-keys and it always uses\r
- * 0x80010000 (C9-49). So for QP1 we always put this if the high-order bit of the Qkey\r
- * is set. */\r
- if( (qp->sqp_type == VAPI_GSI_QP) && (p_wr->dgrm.ud.remote_qkey & CL_HTON32(0x80000000)) )\r
- {\r
- DETH_p->Q_Key= 0x80010000;\r
- } else { /* QP0, or QKEY is not well known GSI QKEY */\r
- /* For QP0 we don't care (QP0 always sends to another QP0 - none of which validates the Qkey) */\r
- DETH_p->Q_Key= cl_hton32( p_wr->dgrm.ud.remote_qkey ); \r
- }\r
-\r
- /* Build the headers */\r
- if (MPGA_make_headers(hdrs,UD_SEND_ONLY_OP,\r
- LRH_p->LNH,FALSE,IB_MAD_LEN,&hdrs_buf_p) != MT_OK) {\r
- return 0;\r
- }\r
- /* Verify headers size */\r
- if (hdrs_buf_p != (((u_int8_t*)segment_p) + WQE_INLINE_SZ_BCOUNT)) {/*Should be segment begin*/\r
- MTL_ERROR2(MT_FLFMT("Error in headers size (%d instead of %d).\n"),\r
- (unsigned) (hdrs_sz - (hdrs_buf_p - (((u_int8_t*)segment_p) + 4))), hdrs_sz);\r
- return 0;\r
- }\r
-\r
-#ifdef MT_LITTLE_ENDIAN\r
- /* MPGA headers returned in BIG endian. WQE is built in CPU endianess - so swap bytes */\r
- for (i= 0 , hdrs_buf32_p= (u_int32_t*)hdrs_buf_p; i < (hdrs_sz>>2); i++) {\r
- hdrs_buf32_p[i]= MOSAL_cpu_to_be32(hdrs_buf32_p[i]);\r
- }\r
-#endif\r
-\r
- return MT_UP_ALIGNX_U32(WQE_INLINE_SZ_BCOUNT + hdrs_sz , 4); /* Align to WQE segment size */\r
-}\r
- \r
-/* Build ICRC segment for MLX (UD) */\r
-inline static u_int32_t WQE_pack_mlx_icrc_hw(u_int32_t *segment_p)\r
-{\r
- segment_p[0]= (1<<31) | 4 ; /* Inline ICRC (32 bits = 4 bytes) */\r
- segment_p[1]= 0; /* Hardware generated ICRC */\r
- /* 2 dwords padded for a single Inline Data segment */\r
- return WQE_INLINE_ICRC;\r
-}\r
-\r
-/* Build ICRC segment for MLX (UD) */\r
-inline static u_int32_t WQE_pack_mlx_icrc_hw_be(u_int32_t *segment_p)\r
-{\r
- segment_p[0]= MOSAL_cpu_to_be32( (1<<31) | 4 ); /* Inline ICRC (32 bits = 4 bytes) */\r
- segment_p[1]= 0; /* Hardware generated ICRC */\r
- /* 2 dwords padded for a single Inline Data segment */\r
- return WQE_INLINE_ICRC;\r
-}\r
-\r
-/* Pack Control segment (for mlx-sends) */\r
-inline static u_int32_t WQE_pack_ctrl_mlx(u_int32_t *segment_p, \r
- VAPI_comp_type_t comp_type, MT_bool event_bit,\r
- IB_sl_t sl, IB_static_rate_t max_statrate, MT_bool slr, MT_bool v15,\r
- u_int16_t vcrc, IB_lid_t rlid)\r
-{\r
- memset(segment_p,0,WQE_SEG_SZ_CTRL); /* Clear all "RESERVED" */\r
- MT_INSERT_ARRAY32(segment_p,(comp_type == VAPI_SIGNALED) ? 1 : 0,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_mlx_st,c),MT_BIT_SIZE(wqe_segment_ctrl_mlx_st,c));\r
- MT_INSERT_ARRAY32(segment_p,event_bit ? 1 : 0,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_mlx_st,e),MT_BIT_SIZE(wqe_segment_ctrl_mlx_st,e));\r
- MT_INSERT_ARRAY32(segment_p,sl,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_mlx_st,sl),MT_BIT_SIZE(wqe_segment_ctrl_mlx_st,sl));\r
- MT_INSERT_ARRAY32(segment_p,max_statrate > 0 ? 1 : 0,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_mlx_st,max_statrate),\r
- MT_BIT_SIZE(wqe_segment_ctrl_mlx_st,max_statrate));\r
- MT_INSERT_ARRAY32(segment_p,slr ? 1 : 0,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_mlx_st,slr),MT_BIT_SIZE(wqe_segment_ctrl_mlx_st,slr));\r
- MT_INSERT_ARRAY32(segment_p,v15 ? 1 : 0,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_mlx_st,v15),MT_BIT_SIZE(wqe_segment_ctrl_mlx_st,v15));\r
- MT_INSERT_ARRAY32(segment_p,vcrc,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_mlx_st,vcrc),MT_BIT_SIZE(wqe_segment_ctrl_mlx_st,vcrc));\r
- MT_INSERT_ARRAY32(segment_p,rlid,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_mlx_st,rlid),MT_BIT_SIZE(wqe_segment_ctrl_mlx_st,rlid));\r
- return WQE_SEG_SZ_CTRL;\r
-}\r
-\r
-/* Pack Control segment (for mlx-sends) */\r
-inline static u_int32_t WQE_pack_ctrl_mlx_be(u_int32_t *segment_p, \r
- VAPI_comp_type_t comp_type, MT_bool event_bit,\r
- IB_sl_t sl, IB_static_rate_t max_statrate, MT_bool slr, MT_bool v15,\r
- u_int16_t vcrc, IB_lid_t rlid)\r
-{\r
- memset(segment_p,0,WQE_SEG_SZ_CTRL); /* Clear all "RESERVED" */\r
- MT_INSERT_ARRAY32_BE(segment_p,(comp_type == VAPI_SIGNALED) ? 1 : 0,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_mlx_st,c),MT_BIT_SIZE(wqe_segment_ctrl_mlx_st,c));\r
- MT_INSERT_ARRAY32_BE(segment_p,event_bit ? 1 : 0,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_mlx_st,e),MT_BIT_SIZE(wqe_segment_ctrl_mlx_st,e));\r
- MT_INSERT_ARRAY32_BE(segment_p,sl,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_mlx_st,sl),MT_BIT_SIZE(wqe_segment_ctrl_mlx_st,sl));\r
- MT_INSERT_ARRAY32_BE(segment_p,max_statrate > 0 ? 1 : 0,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_mlx_st,max_statrate),\r
- MT_BIT_SIZE(wqe_segment_ctrl_mlx_st,max_statrate));\r
- MT_INSERT_ARRAY32_BE(segment_p,slr ? 1 : 0,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_mlx_st,slr),MT_BIT_SIZE(wqe_segment_ctrl_mlx_st,slr));\r
- MT_INSERT_ARRAY32_BE(segment_p,v15 ? 1 : 0,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_mlx_st,v15),MT_BIT_SIZE(wqe_segment_ctrl_mlx_st,v15));\r
- MT_INSERT_ARRAY32_BE(segment_p,vcrc,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_mlx_st,vcrc),MT_BIT_SIZE(wqe_segment_ctrl_mlx_st,vcrc));\r
- MT_INSERT_ARRAY32_BE(segment_p,rlid,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_mlx_st,rlid),MT_BIT_SIZE(wqe_segment_ctrl_mlx_st,rlid));\r
- return WQE_SEG_SZ_CTRL;\r
-}\r
-\r
-inline static u_int32_t WQE_build_send_mlx(\r
- HH_hca_hndl_t hh_hndl,\r
- THHUL_qp_t qp,\r
- VAPI_sr_desc_t *send_req_p,\r
- VAPI_pkey_ix_t pkey_index, /* take this index instead of QP's, if not QP1_PKEY_INDEX */\r
- u_int32_t *wqe_buf\r
-) \r
-{\r
- \r
- VAPI_ud_av_t *av = &qp->sq_res.wqe_tmp->av;\r
- u_int8_t *cur_loc_p= (u_int8_t*)wqe_buf; /* Current location in the WQE */\r
- u_int8_t *prev_loc_p;\r
- HH_ret_t rc;\r
-\r
- rc= THH_udavm_parse_udav_entry((u_int32_t*)(send_req_p->remote_ah),av);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("Invalid UD AV handle - %s"),\r
- HH_strerror_sym(rc));\r
- return 0;\r
- }\r
-\r
- \r
- if ((av->dlid == PERMIS_LID) && (qp->sqp_type != VAPI_SMI_QP)) {\r
- MTL_ERROR1(MT_FLFMT("DLID==Permissive-LID while not an SMI QP.\n"));\r
- return 0;\r
- }\r
-\r
- cur_loc_p+= qpm_WQE_init_next((u_int32_t*)cur_loc_p); /* Make "unlinked" "next" segment */\r
- cur_loc_p+= WQE_pack_ctrl_mlx((u_int32_t*)cur_loc_p, /* Pack Control segment */\r
- send_req_p->comp_type, FALSE/*event bit*/,\r
- av->sl,av->static_rate,(av->dlid == PERMIS_LID),(qp->sqp_type == VAPI_SMI_QP),\r
- 0/*VCRC*/,av->dlid);\r
- \r
- \r
- /* Build inline headers */\r
- switch (qp->sqp_type) {\r
- case VAPI_SMI_QP: \r
- case VAPI_GSI_QP: \r
- prev_loc_p= cur_loc_p;\r
- cur_loc_p+= WQE_pack_mlx_ud_header((u_int32_t*)cur_loc_p,qp,send_req_p,av,hh_hndl,pkey_index);\r
- if (cur_loc_p == prev_loc_p) {\r
- return 0;\r
- }\r
- /* Pack scatter/gather list segments */\r
- cur_loc_p+= WQE_pack_sg_list((u_int32_t*)cur_loc_p,send_req_p->sg_lst_len,send_req_p->sg_lst_p);\r
- cur_loc_p+= WQE_pack_mlx_icrc_hw((u_int32_t*)cur_loc_p);\r
- break;\r
- case VAPI_RAW_ETY_QP:\r
- case VAPI_RAW_IPV6_QP:\r
- default:\r
- return 0;\r
- }\r
- \r
- return (u_int32_t)(((MT_virt_addr_t)cur_loc_p) - ((MT_virt_addr_t)wqe_buf));\r
-}\r
-\r
-#ifdef WIN32\r
-#include "thhul_qpm_ibal.h"\r
-\r
-inline static u_int32_t WQE_build_send_mlx2_be(\r
- IN HH_hca_hndl_t hh_hndl,\r
- IN THHUL_qp_t qp,\r
- IN ib_send_wr_t *p_wr,\r
- IN VAPI_pkey_ix_t pkey_index, /* take this index instead of QP's, if not QP1_PKEY_INDEX */\r
- IN OUT u_int32_t *wqe_buf )\r
-{\r
- VAPI_ud_av_t *av = &qp->sq_res.wqe_tmp->av;\r
- u_int8_t *cur_loc_p = (u_int8_t*)wqe_buf; /* Current location in the WQE */\r
- u_int8_t *prev_loc_p;\r
- HH_ret_t rc;\r
-\r
- rc= THH_udavm_parse_udav_entry((u_int32_t*)(p_wr->dgrm.ud.h_av->h_av),av);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("Invalid UD AV handle - %s"),\r
- HH_strerror_sym(rc));\r
- return 0;\r
- }\r
-\r
- if ((av->dlid == PERMIS_LID) && (qp->sqp_type != VAPI_SMI_QP)) {\r
- MTL_ERROR1(MT_FLFMT("DLID==Permissive-LID while not an SMI QP.\n"));\r
- return 0;\r
- }\r
-\r
- cur_loc_p+= qpm_WQE_init_next((u_int32_t*)cur_loc_p); /* Make "unlinked" "next" segment */\r
- cur_loc_p+= WQE_pack_ctrl_mlx_be((u_int32_t*)cur_loc_p, /* Pack Control segment */\r
- (p_wr->send_opt & IB_SEND_OPT_SIGNALED)? VAPI_SIGNALED : VAPI_UNSIGNALED,\r
- FALSE/*event bit*/,av->sl,av->static_rate,(av->dlid == PERMIS_LID),\r
- (qp->sqp_type == VAPI_SMI_QP),0/*VCRC*/,av->dlid);\r
-\r
- /* Build inline headers */\r
- switch( qp->sqp_type )\r
- {\r
- case VAPI_SMI_QP: \r
- case VAPI_GSI_QP: \r
- prev_loc_p= cur_loc_p;\r
- cur_loc_p+= WQE_pack_mlx_ud_header2((u_int32_t*)cur_loc_p,qp,p_wr,av,hh_hndl,pkey_index);\r
- if (cur_loc_p == prev_loc_p) {\r
- return 0;\r
- }\r
-\r
- /* Swap UD header into big-endian. */\r
- for( prev_loc_p; prev_loc_p != cur_loc_p; prev_loc_p += 4 )\r
- *(uint32_t*)prev_loc_p = MOSAL_cpu_to_be32( *(uint32_t*)prev_loc_p );\r
- \r
- /* Pack scatter/gather list segments in BE format */\r
- if( p_wr->send_opt & IB_SEND_OPT_INLINE )\r
- {\r
- if( WQE_pack_inline_sgl_ibal(\r
- p_wr, &(uint32_t*)cur_loc_p, qp->sq_res.max_inline_data ) != HH_OK )\r
- {\r
- return 0;\r
- }\r
- }\r
- else\r
- {\r
- WQE_pack_sgl_ibal( p_wr, &(uint32_t*)cur_loc_p );\r
- }\r
- cur_loc_p+= WQE_pack_mlx_icrc_hw_be((u_int32_t*)cur_loc_p);\r
- break;\r
- case VAPI_RAW_ETY_QP:\r
- case VAPI_RAW_IPV6_QP:\r
- default:\r
- return 0;\r
- }\r
-\r
- return (u_int32_t)(((MT_virt_addr_t)cur_loc_p) - ((MT_virt_addr_t)wqe_buf));\r
-}\r
-#endif\r
-\r
-\r
-/* Pack Control segment (for receive work requests) */\r
-inline static u_int32_t qpm_WQE_pack_ctrl_recv(u_int32_t *segment_p, \r
- VAPI_comp_type_t comp_type, u_int32_t event_bit)\r
-{\r
- memset(segment_p,0,WQE_SEG_SZ_CTRL); /* Clear all "RESERVED" */\r
- MT_INSERT_ARRAY32(segment_p,(comp_type == VAPI_SIGNALED) ? 1 : 0,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_recv_st,c),MT_BIT_SIZE(wqe_segment_ctrl_recv_st,c));\r
- MT_INSERT_ARRAY32(segment_p,event_bit,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_recv_st,e),MT_BIT_SIZE(wqe_segment_ctrl_recv_st,e));\r
- return WQE_SEG_SZ_CTRL;\r
-}\r
-\r
-/* Optimized version of WQE_pack_ctrl_recv\r
- * remove memset and precalculate offset\r
- */\r
-#define CTRL_RECV_C_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_ctrl_recv_st,c)>>2\r
-#define CTRL_RECV_RESERVED2_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_ctrl_recv_st,reserved2)>>2 \r
- \r
-#define CTRL_RECV_C_BIT_OFFSET MT_BIT_OFFSET(wqe_segment_ctrl_recv_st,c)\r
-#define CTRL_RECV_E_BIT_OFFSET MT_BIT_OFFSET(wqe_segment_ctrl_recv_st,e)\r
-/* Convert into Big Endian version */\r
-inline static u_int32_t WQE_pack_ctrl_recv_be(u_int32_t *segment_p, \r
- VAPI_comp_type_t comp_type, u_int32_t event_bit)\r
-{\r
- \r
- segment_p[CTRL_RECV_RESERVED2_DWORD_OFFSET] = 0;\r
- segment_p[CTRL_RECV_C_DWORD_OFFSET] = MOSAL_cpu_to_be32(0\r
- | (((comp_type == VAPI_SIGNALED) ? 1 : 0) << CTRL_RECV_C_BIT_OFFSET)\r
- | ( event_bit << CTRL_RECV_E_BIT_OFFSET)\r
- );\r
- \r
- return WQE_SEG_SZ_CTRL;\r
-}\r
-\r
-inline static u_int32_t qpm_WQE_build_recv(\r
- THHUL_qp_t qp,\r
- VAPI_rr_desc_t *recv_req_p,\r
- u_int32_t *wqe_buf\r
-)\r
-{\r
- u_int8_t *cur_loc_p= (u_int8_t*)wqe_buf; /* Current location in the WQE */\r
-\r
- cur_loc_p+= qpm_WQE_init_next((u_int32_t*)cur_loc_p); /* Make "unlinked" "next" segment */\r
- cur_loc_p+= qpm_WQE_pack_ctrl_recv((u_int32_t*)cur_loc_p,\r
- recv_req_p->comp_type, 0/*event bit*/);\r
- /* Pack scatter/gather list segments */\r
- cur_loc_p+= WQE_pack_sg_list((u_int32_t*)cur_loc_p,recv_req_p->sg_lst_len,recv_req_p->sg_lst_p);\r
- \r
- return (u_int32_t)(((MT_virt_addr_t)cur_loc_p) - ((MT_virt_addr_t)wqe_buf));\r
-}\r
-\r
-/* Build Big Endian version of WQE_build_recv to remove extra copy\r
- * from draft. Optimized version of post_send_recv use wqe_buf directly, so\r
- * should build big endian verison to wqe_buf\r
- */\r
-inline static u_int32_t WQE_build_recv_be(\r
- THHUL_qp_t qp,\r
- VAPI_rr_desc_t *recv_req_p,\r
- u_int32_t *wqe_buf\r
-)\r
-{\r
- u_int8_t *cur_loc_p= (u_int8_t*)wqe_buf; /* Current location in the WQE */\r
-\r
- cur_loc_p+= qpm_WQE_init_next((u_int32_t*)cur_loc_p); /* Make "unlinked" "next" segment */\r
- cur_loc_p+= WQE_pack_ctrl_recv_be((u_int32_t*)cur_loc_p,\r
- recv_req_p->comp_type, 0/*event bit*/);\r
- /* Pack scatter/gather list segments */\r
- cur_loc_p+= WQE_pack_sg_list_be((u_int32_t*)cur_loc_p,recv_req_p->sg_lst_len,recv_req_p->sg_lst_p);\r
- \r
- return (u_int32_t)(((MT_ulong_ptr_t)cur_loc_p) - ((MT_ulong_ptr_t)wqe_buf));\r
-}\r
-\r
-\r
-/* This is for post_send_recv2. sg_list buld directly from IbAccess structure.\r
- */\r
-inline static u_int32_t *WQE_build_recv_be_req2(\r
- THHUL_qp_t qp,\r
- u_int32_t *wqe_buf,\r
- VAPI_comp_type_t comp_type\r
-)\r
-{\r
- u_int8_t *cur_loc_p= (u_int8_t*)wqe_buf; /* Current location in the WQE */\r
-\r
- cur_loc_p+= qpm_WQE_init_next((u_int32_t*)cur_loc_p); /* Make "unlinked" "next" segment */\r
- cur_loc_p+= WQE_pack_ctrl_recv_be((u_int32_t*)cur_loc_p,\r
- comp_type, 0/*event bit*/);\r
- \r
- return (u_int32_t *)cur_loc_p;\r
-}\r
-\r
-\r
-inline static u_int32_t WQE_build_membind(\r
- HHUL_mw_bind_t *bind_props_p,\r
- IB_rkey_t new_rkey,\r
- u_int32_t *wqe_buf\r
-)\r
-{\r
- u_int32_t *cur_loc_p= wqe_buf; /* Current location in the WQE */\r
-\r
- cur_loc_p+= (qpm_WQE_init_next((u_int32_t*)cur_loc_p)>>2); /* Make "unlinked" "next" segment */\r
- cur_loc_p+= (WQE_pack_ctrl_send((u_int32_t*)cur_loc_p, /* Pack Control segment */\r
- bind_props_p->comp_type, 0/*SE bit*/, 0/*event bit*/,0/*Imm. data*/)>>2);\r
-\r
- memset(cur_loc_p,0,8); /* clear reserved bits of first 2 dwords */\r
-\r
- /* Set access bits */\r
- if (bind_props_p->acl & VAPI_EN_REMOTE_READ) {\r
- MT_INSERT_ARRAY32(cur_loc_p,1,\r
- MT_BIT_OFFSET(wqe_segment_bind_st,rr),MT_BIT_SIZE(wqe_segment_bind_st,rr));\r
- }\r
- if (bind_props_p->acl & VAPI_EN_REMOTE_WRITE) {\r
- MT_INSERT_ARRAY32(cur_loc_p,1,\r
- MT_BIT_OFFSET(wqe_segment_bind_st,rw),MT_BIT_SIZE(wqe_segment_bind_st,rw));\r
- }\r
- if (bind_props_p->acl & VAPI_EN_REMOTE_ATOM) {\r
- MT_INSERT_ARRAY32(cur_loc_p,1,\r
- MT_BIT_OFFSET(wqe_segment_bind_st,a),MT_BIT_SIZE(wqe_segment_bind_st,a));\r
- }\r
-\r
- cur_loc_p[MT_BYTE_OFFSET(wqe_segment_bind_st,new_rkey)>>2]= new_rkey;\r
- cur_loc_p[MT_BYTE_OFFSET(wqe_segment_bind_st,region_lkey)>>2]= bind_props_p->mr_lkey;\r
- cur_loc_p[MT_BYTE_OFFSET(wqe_segment_bind_st,start_address_h)>>2]= \r
- (u_int32_t)(bind_props_p->start >> 32);\r
- cur_loc_p[MT_BYTE_OFFSET(wqe_segment_bind_st,start_address_l)>>2]= \r
- (u_int32_t)(bind_props_p->start & 0xFFFFFFFF);\r
- cur_loc_p[MT_BYTE_OFFSET(wqe_segment_bind_st,length_h)>>2]= \r
- (u_int32_t)(bind_props_p->size >> 32);\r
- cur_loc_p[MT_BYTE_OFFSET(wqe_segment_bind_st,length_l)>>2]= \r
- (u_int32_t)(bind_props_p->size & 0xFFFFFFFF);\r
-\r
- return (u_int32_t)(WQE_SEG_SZ_BIND + ((MT_virt_addr_t)cur_loc_p) - ((MT_virt_addr_t)wqe_buf));\r
-}\r
-\r
-/* - Allocate a WQE in given send queue, \r
- - put given WQE in it, \r
- - link to previos WQE and \r
- - ring the doorbell \r
- * q_lock must be acquired before invoking this function (to protect WQEs allocation).\r
- */ \r
-inline static HH_ret_t sq_alloc_wqe_link_and_ring(THHUL_qp_t qp, \r
- u_int32_t* wqe_draft, u_int32_t wqe_sz_dwords, \r
-#ifdef MT_LITTLE_ENDIAN\r
- u_int32_t swap_sz_dwords, \r
-#endif\r
- VAPI_sr_desc_t *send_req_p, tavor_if_nopcode_t nopcode)\r
-{\r
- u_int32_t next_draft[WQE_SEG_SZ_NEXT>>2]; /* Build "next" segment here */\r
- volatile u_int32_t* next_wqe; /* Actual WQE pointer */\r
- u_int32_t i;\r
- THH_uar_sendq_dbell_t sq_dbell;\r
- \r
- /* Check if any WQEs are free to be consumed */\r
- if (qp->sq_res.max_outs == qp->sq_res.cur_outs) {\r
- MTL_ERROR4("THHUL_qpm_post_send_req: Send queue is full (%u requests outstanding).\n",\r
- qp->sq_res.cur_outs);\r
- return HH_E2BIG_WR_NUM;\r
- }\r
- /* Allocate next WQE */\r
- next_wqe= (u_int32_t*)(qp->sq_res.wqe_buf + \r
- (qp->sq_res.next2post_index << qp->sq_res.log2_max_wqe_sz) );\r
- qp->sq_res.wqe_id[qp->sq_res.next2post_index]= send_req_p->id; /* Save WQE ID */\r
- qp->sq_res.next2post_index = (qp->sq_res.next2post_index + 1) % qp->sq_res.max_outs ;\r
- qp->sq_res.cur_outs++;\r
- \r
- /* copy (while swapping,if needed) the wqe_draft to the actual WQE */\r
- /* TBD: for big-endian machines we can optimize here and use memcpy */\r
- MTPERF_TIME_START(SQ_WQE_copy);\r
-#ifdef MT_LITTLE_ENDIAN\r
- for (i= 0; i < swap_sz_dwords; i++) {\r
- next_wqe[i]= MOSAL_cpu_to_be32(wqe_draft[i]);\r
- }\r
- /* The rest of the WQE should be copied as is (inline data) */\r
- for (; i < wqe_sz_dwords; i++) {\r
- next_wqe[i]= wqe_draft[i];\r
- }\r
-#else /* big endian */\r
- for (i= 0; i < wqe_sz_dwords; i++) {\r
- next_wqe[i]= wqe_draft[i];\r
- }\r
-#endif\r
-\r
- MTPERF_TIME_END(SQ_WQE_copy);\r
- \r
- /* Update "next" segment of previous WQE (if any) */\r
- if (qp->sq_res.last_posted_p != NULL) {\r
- /* Build linking "next" segment in last posted WQE*/\r
- qpm_WQE_pack_send_next(next_draft, nopcode, send_req_p->fence,\r
- 1/*DBD*/, (u_int32_t)(MT_ulong_ptr_t) next_wqe, wqe_sz_dwords>>2, \r
- (qp->ts_type==VAPI_TS_RD) ? send_req_p->eecn : 0);\r
- for (i= 0;i < (WQE_SEG_SZ_NEXT>>2) ;i++) { \r
- /* This copy assures big-endian as well as that NDS is written last */\r
- qp->sq_res.last_posted_p[i]= MOSAL_cpu_to_be32(next_draft[i]);\r
- }\r
- }\r
- qp->sq_res.last_posted_p= next_wqe;\r
- \r
- /* Ring doorbell (send or rd-send) */\r
- sq_dbell.qpn= qp->qpn;\r
- sq_dbell.nopcode= nopcode;\r
- sq_dbell.fence= send_req_p->fence;\r
- sq_dbell.next_addr_32lsb= (u_int32_t)((MT_virt_addr_t)next_wqe & 0xFFFFFFFF);\r
- sq_dbell.next_size= wqe_sz_dwords>>2;\r
- if (qp->ts_type == VAPI_TS_RD) {\r
- THH_uar_sendq_rd_dbell(qp->uar,&sq_dbell,send_req_p->eecn);\r
- } else { /* non-RD send request */\r
- MTPERF_TIME_START(THH_uar_sendq_dbell);\r
- THH_uar_sendq_dbell(qp->uar,&sq_dbell);\r
- MTPERF_TIME_END(THH_uar_sendq_dbell);\r
- }\r
-\r
- return HH_OK;\r
-}\r
-\r
-/* Optimized version of sq_alloc_wqe_link_and_ring\r
- * remove devision and call inline version od dbell \r
- * remove extra copy of Update "next" segment\r
- */\r
-#define SEND_DOORBELL_F_BIT_OFFSET MT_BIT_OFFSET(tavorprm_send_doorbell_st,f) \r
-#define SEDN_DOORBELL_QPN_BIT_OFFSET (MT_BIT_OFFSET(tavorprm_send_doorbell_st,qpn) & 0x1f)\r
-inline static HH_ret_t sq_alloc_wqe_link_and_ring_be(THHUL_qp_t qp, \r
- u_int32_t* wqe_draft, u_int32_t wqe_sz_dwords, \r
-#ifdef MT_LITTLE_ENDIAN\r
- u_int32_t swap_sz_dwords, \r
-#endif\r
- VAPI_sr_desc_t *send_req_p, tavor_if_nopcode_t nopcode)\r
-{\r
- //THH_uar_sendq_dbell_t sq_dbell;\r
- volatile u_int32_t chimeWords[4];\r
- THH_uar_t uar;\r
- u_int32_t *cur_loc_p;\r
-\r
- \r
- qp->sq_res.wqe_id[qp->sq_res.next2post_index]= send_req_p->id; /* Save WQE ID */\r
- \r
- ++qp->sq_res.next2post_index; \r
- if (MOSAL_EXPECT_FALSE(qp->sq_res.next2post_index >= qp->sq_res.max_outs))\r
- qp->sq_res.next2post_index = 0;\r
- \r
- qp->sq_res.cur_outs++;\r
-\r
- /* Update "next" segment of previous WQE (if any) */\r
- /* Build linking "next" segment in last posted WQE*/\r
- /* buld dirctly to wqe, so call big endian version */\r
- WQE_pack_send_next_be((u_int32_t*)qp->sq_res.last_posted_p, nopcode, send_req_p->fence,\r
- 1/*DBD*/, (u_int32_t)(MT_long_ptr_t) wqe_draft, wqe_sz_dwords>>2, \r
- (qp->ts_type==VAPI_TS_RD) ? send_req_p->eecn : 0);\r
- \r
- qp->sq_res.last_posted_p= wqe_draft;\r
- \r
- /* Ring doorbell */\r
- \r
- uar = qp->uar;\r
- chimeWords[0] = MOSAL_cpu_to_be32(0\r
- | (u_int32_t)nopcode\r
- | ((send_req_p->fence & 0x1) << SEND_DOORBELL_F_BIT_OFFSET)\r
- | ((u_int32_t)(MT_ulong_ptr_t)wqe_draft & 0xFFFFFFFF));\r
- chimeWords[1] = MOSAL_cpu_to_be32(0\r
- | (u_int32_t)(wqe_sz_dwords >> 2) // specify in 16 byte chunks\r
- | ((u_int32_t)(qp->qpn) << SEDN_DOORBELL_QPN_BIT_OFFSET)\r
- );\r
- \r
- if (MOSAL_EXPECT_FALSE(qp->ts_type == VAPI_TS_RD)) { \r
- cur_loc_p = (u_int32_t *)&uar->uar_base[UAR_SEND_DBELL_OFFSET]; \r
- chimeWords[2] = MOSAL_cpu_to_be32(send_req_p->eecn << 18);\r
- chimeWords[3] = MOSAL_cpu_to_be32((u_int32_t)qp->qpn << 8);\r
- MOSAL_spinlock_dpc_lock(&(uar->uar_lock));\r
- MOSAL_MMAP_IO_WRITE_QWORD( cur_loc_p, *(volatile u_int64_t*)&chimeWords[2]);\r
- MOSAL_MMAP_IO_WRITE_QWORD(&cur_loc_p[2],*(volatile u_int64_t*)chimeWords);\r
- MOSAL_spinlock_unlock(&(uar->uar_lock)); \r
- } else {\r
-#ifdef __MOSAL_MMAP_IO_WRITE_QWORD_ATOMIC__\r
- MOSAL_MMAP_IO_WRITE_QWORD(((u_int32_t *)&uar->uar_base[UAR_SEND_DBELL_OFFSET]),*(volatile u_int64_t*)chimeWords);\r
-#else\r
- MOSAL_spinlock_dpc_lock(&(uar->uar_lock));\r
- MOSAL_MMAP_IO_WRITE_QWORD(((u_int32_t *)&uar->uar_base[UAR_SEND_DBELL_OFFSET]),*(volatile u_int64_t*)chimeWords);\r
- MOSAL_spinlock_unlock(&(uar->uar_lock));\r
-#endif \r
- }\r
- \r
-\r
- return HH_OK;\r
-}\r
-\r
-/* Extract NDS directly from (big-endian) WQE */\r
-inline static u_int8_t qpm_WQE_extract_nds(volatile u_int32_t* wqe)\r
-{\r
-/*** warning C4244: 'return' : conversion from 'unsigned long' to 'u_int8_t', possible loss of data ***/\r
-#if 0\r
- return (u_int8_t)MT_EXTRACT32(MOSAL_be32_to_cpu(wqe[MT_BYTE_OFFSET(wqe_segment_next_st,nds) >> 2]),\r
- MT_BIT_OFFSET(wqe_segment_next_st,nds) & MASK32(5),\r
- MT_BIT_SIZE(wqe_segment_next_st,nds) & MASK32(5));\r
-#endif \r
- \r
-#define NEXT_ST_BIT_MASK MASK32(5)\r
- return (u_int8_t)MT_EXTRACT32(MOSAL_be32_to_cpu(wqe[NEXT_ST_NDS_DWORD_OFFSET]),\r
- MT_BIT_OFFSET(wqe_segment_next_st,nds) & NEXT_ST_BIT_MASK,\r
- MT_BIT_SIZE(wqe_segment_next_st,nds) & NEXT_ST_BIT_MASK);\r
-\r
-}\r
-\r
-/* Extract NDA directly from (big-endian) WQE */\r
-inline static u_int32_t qpm_WQE_extract_nda(volatile u_int32_t* wqe)\r
-{\r
- return (MOSAL_be32_to_cpu(wqe[MT_BYTE_OFFSET(wqe_segment_next_st,nda_31_6) >> 2]) & (~MASK32(6)) );\r
-}\r
-\r
-inline static u_int8_t qpm_WQE_extract_dbd(volatile u_int32_t* wqe)\r
-{\r
-/*** warning C4244: 'return' : conversion from 'unsigned long' to 'u_int8_t', possible loss of data ***/\r
-#if 0 \r
- return (u_int8_t)MT_EXTRACT32(MOSAL_be32_to_cpu(wqe[MT_BYTE_OFFSET(wqe_segment_next_st,dbd) >> 2]),\r
- return (u_int8_t)MT_EXTRACT32(MOSAL_be32_to_cpu(wqe[MT_BYTE_OFFSET(wqe_segment_next_st,dbd) >> 2]),\r
- MT_BIT_OFFSET(wqe_segment_next_st,dbd) & MASK32(5),\r
- MT_BIT_SIZE(wqe_segment_next_st,dbd) & MASK32(5));\r
-#endif\r
-#define NEXT_ST_DBD_DWORD_OFFSET MT_BYTE_OFFSET(wqe_segment_next_st,dbd) >> 2\r
-#define NEXT_ST_DBD_BIT_MASK MASK32(5)\r
- return (u_int8_t)MT_EXTRACT32(MOSAL_be32_to_cpu(wqe[NEXT_ST_DBD_DWORD_OFFSET]),\r
- MT_BIT_OFFSET(wqe_segment_next_st,dbd) & NEXT_ST_DBD_BIT_MASK,\r
- MT_BIT_SIZE(wqe_segment_next_st,dbd) & NEXT_ST_DBD_BIT_MASK); \r
-}\r
-\r
-#ifdef DUMP_SEND_REQ\r
- static void dump_send_req(THHUL_qp_t qp, HHUL_send_req_t *sr);\r
-#endif\r
-\r
-/**********************************************************************************************\r
- * Public API Functions (defined in thhul_hob.h)\r
- **********************************************************************************************/\r
-\r
-HH_ret_t THHUL_qpm_create( \r
- THHUL_hob_t hob, \r
- THHUL_srqm_t srqm,\r
- THHUL_qpm_t *qpm_p \r
-) \r
-{ \r
- int i;\r
-\r
- *qpm_p= (THHUL_qpm_t) MALLOC(sizeof(struct THHUL_qpm_st));\r
- if (*qpm_p == NULL) {\r
- MTL_ERROR1("THHUL_qpm_create: Failed allocating THHUL_qpm_st.\n");\r
- return HH_EAGAIN;\r
- }\r
-\r
- /* init internal data structures */\r
- for (i= 0; i < QP_HASH_TBL_SZ; i++) {\r
- (*qpm_p)->hash_tbl[i]= NULL;\r
-#if QPM_USE_FIXED_QP_ARRAY\r
- (*qpm_p)->array_tbl[i].qp_array[0].qpn = QP_ARRAY_UNUSED;\r
- (*qpm_p)->array_tbl[i].qp_array[QPM_QP_PER_ARRAY].qpn = QP_ARRAY_UNUSED;\r
-#endif\r
- }\r
- (*qpm_p)->qp_cnt= 0;\r
- (*qpm_p)->srqm= srqm;\r
- for (i= THHUL_DPOOL_SZ_MIN_KB; i <= THHUL_DPOOL_SZ_MAX_KB; i++) {\r
- (*qpm_p)->dpool_p[i - THHUL_DPOOL_SZ_MIN_KB]= NULL;\r
- }\r
- MOSAL_mutex_init(&(*qpm_p)->dpool_lock);\r
- MOSAL_spinlock_init(&((*qpm_p)->hash_lock));\r
-\r
- return HH_OK;\r
-}\r
-\r
-\r
-static void THHUL_qpm_qp_destroy(\r
- THHUL_qpm_t qpm,\r
- THHUL_qp_t qp)\r
-{\r
- /* Clean all CQEs which refer to this QP */\r
- THHUL_cqm_cq_cleanup(qp->rq_cq, qp->qpn, qpm->srqm, qp->srq);\r
- if (qp->sq_cq != qp->rq_cq) /* additional cleaning required only if SQ's CQ is different */\r
- THHUL_cqm_cq_cleanup(qp->sq_cq, qp->qpn, qpm->srqm, HHUL_INVAL_SRQ_HNDL);\r
- \r
- /* Free QP resources: Auxilary buffer + WQEs buffer */\r
- if (qp->sq_res.wqe_id != NULL) {\r
- THH_SMART_FREE(qp->sq_res.wqe_id, qp->sq_res.max_outs * sizeof(VAPI_wr_id_t)); \r
- }\r
- if (qp->rq_res.wqe_id != NULL) {\r
- THH_SMART_FREE(qp->rq_res.wqe_id, qp->rq_res.max_outs * sizeof(VAPI_wr_id_t)); \r
- }\r
- if (qp->wqe_buf_orig != NULL) {/* WQEs buffer were allocated in process mem. or by the THH_qpm ? */ \r
- MTL_DEBUG4(MT_FLFMT("Freeing WQEs buffer at 0x%p"),qp->wqe_buf_orig);\r
- if (qp->dpool_p == NULL) { /* direct allocation */\r
- if (qp->used_virt_alloc) \r
- MOSAL_pci_virt_free_consistent(qp->wqe_buf_orig, qp->wqe_buf_orig_size);\r
- else\r
- MOSAL_pci_phys_free_consistent(qp->wqe_buf_orig, qp->wqe_buf_orig_size); \r
- } else { /* used dpool */\r
- dpool_free(qpm, qp->dpool_p, qp->wqe_buf_orig);\r
- }\r
- }\r
- FREE(qp->sq_res.wqe_draft);\r
- if (qp->sq_res.wqe_tmp)\r
- FREE(qp->sq_res.wqe_tmp);\r
- FREE(qp->rq_res.wqe_draft);\r
- FREE(qp);\r
-}\r
-\r
-\r
-HH_ret_t THHUL_qpm_destroy( \r
- THHUL_qpm_t qpm \r
-) \r
-{ \r
- \r
- THHUL_qp_t qp;\r
- qp_hash_entry_t *entry2remove_p;\r
- int i;\r
-\r
-#if QPM_USE_FIXED_QP_ARRAY\r
- /* clean up qp in fixed array */\r
- int j; \r
- for (i= 0; i < QP_HASH_TBL_SZ; i++) {\r
- qp_array_entry_t *qp_array_e = &qpm->array_tbl[i];\r
- j = 0;\r
- while (qp_array_e->qp_array[j].qpn != QP_ARRAY_UNUSED) {\r
- if(qp_array_e->qp_array[j].qpn != QP_ARRAY_REUSE)\r
- { \r
- qp = qp_array_e->qp_array[j].qp;\r
- \r
- /* clean up qp structure */\r
- THHUL_qpm_qp_destroy(qpm, qp);\r
- qp_array_e->qp_array[j].qpn = QP_ARRAY_REUSE;\r
- qp_array_e->qp_array[j].qp = 0; \r
- }\r
- j++;\r
- }/* while (array_tbl[i]...) */\r
- }\r
-#endif\r
- /* clean up qp in hash table */\r
- for (i= 0; i < QP_HASH_TBL_SZ; i++) {\r
- while (qpm->hash_tbl[i]) {\r
- entry2remove_p = qpm->hash_tbl[i];\r
- qpm->hash_tbl[i] = entry2remove_p->next;\r
- qp = entry2remove_p->qp;\r
- FREE(entry2remove_p); \r
-\r
- /* clean up qp structure */\r
- THHUL_qpm_qp_destroy(qpm, qp);\r
-\r
- }/* while (hash_tbl[i]..)*/\r
- }/* for (i.. QP_HASH_TBL_SZ)*/\r
-\r
- \r
- FREE(qpm);\r
- return HH_OK;\r
-}\r
-\r
-\r
-HH_ret_t THHUL_qpm_create_qp_prep( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_qp_init_attr_t *qp_init_attr_p, \r
- HHUL_qp_hndl_t *qp_hndl_p, \r
- VAPI_qp_cap_t *qp_cap_out_p, \r
- void/*THH_qp_ul_resources_t*/ *qp_ul_resources_p \r
-) \r
-{ \r
- return qp_prep(hca,VAPI_REGULAR_QP,qp_init_attr_p,qp_hndl_p,qp_cap_out_p,\r
- (THH_qp_ul_resources_t*)qp_ul_resources_p,\r
- FALSE); /* Default is allocation of WQEs buffer in host's mem. */\r
-}\r
-\r
-HH_ret_t THHUL_qpm_special_qp_prep( \r
- HHUL_hca_hndl_t hca, \r
- VAPI_special_qp_t qp_type, \r
- IB_port_t port, \r
- HHUL_qp_init_attr_t *qp_init_attr_p, \r
- HHUL_qp_hndl_t *qp_hndl_p, \r
- VAPI_qp_cap_t *qp_cap_out_p, \r
- void/*THH_qp_ul_resources_t*/ *qp_ul_resources_p \r
-) \r
-{ \r
- return qp_prep(hca,qp_type,qp_init_attr_p,qp_hndl_p,qp_cap_out_p,\r
- (THH_qp_ul_resources_t*)qp_ul_resources_p,\r
- FALSE); /* For special QPs no performance issue - WQEs in main memory */\r
-}\r
-\r
-\r
-HH_ret_t THHUL_qpm_create_qp_done( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_qp_hndl_t hhul_qp, \r
- IB_wqpn_t hh_qp, \r
- void/*THH_qp_ul_resources_t*/ *qp_ul_resources_p\r
-) \r
-{ \r
- THHUL_qpm_t qpm;\r
- THHUL_qp_t qp= (THHUL_qp_t)hhul_qp;\r
- THH_qp_ul_resources_t *ul_res_p= (THH_qp_ul_resources_t*)qp_ul_resources_p;\r
- HH_ret_t rc;\r
- \r
- rc= THHUL_hob_get_qpm(hca,&qpm);\r
- if (rc != HH_OK) {\r
- MTL_ERROR4("THHUL_qpm_create_qp_done: Invalid HCA handle (%p).",hca);\r
- return HH_EINVAL;\r
- }\r
- if (qp == NULL) {\r
- MTL_ERROR4("THHUL_qpm_create_qp_done: NULL hhul_qp handle.");\r
- return HH_EINVAL;\r
- }\r
- \r
- if ((qp->wqe_buf_orig == NULL) && (qp->wqe_buf_orig_size != 0)) { \r
- /* WQEs buffer allocated in DDR mem. by THH_qpm */\r
- if (ul_res_p->wqes_buf == 0) {\r
- MTL_ERROR1(MT_FLFMT("Got NULL WQEs buffer from qp_ul_res for new qpn=%d.\n"),qp->qpn);\r
- return HH_EINVAL;\r
- }\r
- /* Set the per queue resources */\r
- qp->rq_res.wqe_buf= MT_UP_ALIGNX_VIRT(ul_res_p->wqes_buf,qp->rq_res.log2_max_wqe_sz);\r
- if (qp->rq_res.wqe_buf != ul_res_p->wqes_buf) {\r
- MTL_ERROR1(\r
- "THHUL_qpm_create_qp_done: Buffer allocated by THH_qpm ("VIRT_ADDR_FMT") "\r
- "is not aligned to RQ WQE size (%d bytes).\n",\r
- ul_res_p->wqes_buf,1<<qp->rq_res.log2_max_wqe_sz);\r
- return HH_EINVAL;\r
- }\r
- /* SQ is after RQ - aligned to its WQE size */\r
- qp->sq_res.wqe_buf= MT_UP_ALIGNX_VIRT(qp->rq_res.wqe_buf + \r
- (qp->rq_res.max_outs << qp->rq_res.log2_max_wqe_sz), /* End of RQ WQEs buffer */\r
- qp->sq_res.log2_max_wqe_sz); \r
- }\r
- /* point at the last two 32 bit words in the wqe_buf, \r
- * this allows us to remove an if in VAPI_post_sr path */\r
- qp->sq_res.last_posted_p = (volatile u_int32_t*)(qp->sq_res.wqe_buf + (1 << qp->sq_res.log2_max_wqe_sz));\r
- qp->rq_res.last_posted_p = (volatile u_int32_t*)(qp->rq_res.wqe_buf + (1 << qp->rq_res.log2_max_wqe_sz));\r
- \r
- qp->qpn= hh_qp;\r
- /* Insert QP to the hash table with the given QP number */\r
- rc= insert_to_hash(qpm,qp);\r
- if (rc != HH_OK) {\r
- MTL_ERROR2("THHUL_qpm_create_qp_done: Failed inserting to hash table "\r
- "(QP will remain unusable) !"); \r
- qp->qpn= 0xFFFFFFFF; /* Mark that QP initialization was not completed with invalid QP num. */\r
- return rc;\r
- }\r
-\r
- MTL_DEBUG4(MT_FLFMT("%s: qpn=0x%X rq_res{buf_p=%p, sz=0x%X} sq_res{buf_p=%p, sz=0x%X}"), __func__,\r
- qp->qpn, \r
- (void*)qp->rq_res.wqe_buf, (1 << qp->rq_res.log2_max_wqe_sz) * qp->rq_res.max_outs,\r
- (void*)qp->sq_res.wqe_buf, (1 << qp->sq_res.log2_max_wqe_sz) * qp->sq_res.max_outs);\r
-\r
- return HH_OK;\r
-}\r
-\r
-\r
-HH_ret_t THHUL_qpm_destroy_qp_done( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_qp_hndl_t hhul_qp \r
-) \r
-{ \r
- THHUL_qpm_t qpm;\r
- THHUL_qp_t qp= (THHUL_qp_t)hhul_qp;\r
- HH_ret_t rc;\r
- if ( !qp ) {\r
- MTL_ERROR4("THHUL_qpm_destroy_qp_done: Invalid QP handle (%p).",qp);\r
- return HH_EINVAL;\r
- }\r
- MTL_DEBUG1("THHUL_qpm_destroy_qp_done(hca=%s,hhul_qp=%p) {\n",hca->dev_desc,qp);\r
- rc= THHUL_hob_get_qpm(hca,&qpm);\r
- if (rc != HH_OK) {\r
- MTL_ERROR4("THHUL_qpm_destroy_qp_done: Invalid HCA handle (%p).",hca);\r
- return HH_EINVAL;\r
- }\r
- MTL_DEBUG4(MT_FLFMT("Got qpm with %d QPs"),qpm->qp_cnt);\r
- \r
- if (IS_VALID_QPN(qp->qpn)) { /* QP has completed THHUL_qpm_create_qp_done successfully */\r
- \r
- /* Clean all CQEs which refer to this QP */\r
- THHUL_cqm_cq_cleanup(qp->rq_cq, qp->qpn, qpm->srqm, qp->srq);\r
- if (qp->sq_cq != qp->rq_cq) /* additional cleaning required only if SQ's CQ is different */\r
- THHUL_cqm_cq_cleanup(qp->sq_cq, qp->qpn, qpm->srqm, HHUL_INVAL_SRQ_HNDL);\r
- \r
- /* Remove QP from hash table (after assured no more CQEs of this QP exist) */\r
- rc= remove_from_hash(qpm,qp);\r
- if (rc != HH_OK) {\r
- MTL_ERROR2("THHUL_qpm_destroy_qp_done: Failed removing qp from hash table "\r
- "(assuming invalid QP handle) !"); \r
- return HH_EINVAL_QP_NUM;\r
- }\r
- MTL_DEBUG4(MT_FLFMT("QP %d removed from hash table"),qp->qpn);\r
- \r
- }\r
-\r
- /* Free QP resources: Auxilary buffer + WQEs buffer */\r
- MTL_DEBUG4(MT_FLFMT("Freeing user level WQE-IDs auxilary buffers"));\r
- if (qp->sq_res.wqe_id != NULL) {\r
- THH_SMART_FREE(qp->sq_res.wqe_id, qp->sq_res.max_outs * sizeof(VAPI_wr_id_t)); \r
- }\r
- if (qp->rq_res.wqe_id != NULL) {\r
- THH_SMART_FREE(qp->rq_res.wqe_id, qp->rq_res.max_outs * sizeof(VAPI_wr_id_t)); \r
- }\r
- if (qp->wqe_buf_orig != NULL) {/* WQEs buffer were allocated in process mem. or by the THH_qpm ? */ \r
- MTL_DEBUG4(MT_FLFMT("Freeing WQEs buffer at 0x%p"),qp->wqe_buf_orig);\r
- if (qp->dpool_p == NULL) { /* direct allocation */\r
-#ifdef WIN32\r
- cl_free( qp->wqe_buf_orig );\r
-#else\r
- if (qp->used_virt_alloc) \r
- MOSAL_pci_virt_free_consistent(qp->wqe_buf_orig, qp->wqe_buf_orig_size);\r
- else\r
- MOSAL_pci_phys_free_consistent(qp->wqe_buf_orig, qp->wqe_buf_orig_size); \r
-#endif\r
- } else { /* used dpool */\r
- dpool_free(qpm, qp->dpool_p, qp->wqe_buf_orig);\r
- }\r
- }\r
- if (qp->sq_res.wqe_tmp)\r
- FREE(qp->sq_res.wqe_tmp);\r
- if ( qp->sq_res.wqe_draft ) FREE(qp->sq_res.wqe_draft);\r
- if ( qp->rq_res.wqe_draft ) FREE(qp->rq_res.wqe_draft);\r
- FREE(qp);\r
- /* update QPs counter */\r
- MOSAL_spinlock_dpc_lock(&(qpm->hash_lock));\r
- qpm->qp_cnt--;\r
- MOSAL_spinlock_unlock(&(qpm->hash_lock));\r
- MTL_DEBUG1("} /* THHUL_qpm_destroy_qp_done */ \n");\r
- return HH_OK; \r
-}\r
-\r
-HH_ret_t THHUL_qpm_modify_qp_done( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_qp_hndl_t hhul_qp, \r
- VAPI_qp_state_t cur_state \r
-) \r
-{ \r
- THHUL_qp_t qp= (THHUL_qp_t)hhul_qp;\r
- THHUL_qpm_t qpm;\r
- HH_ret_t rc;\r
- \r
- if (qp == NULL) {\r
- MTL_ERROR1("THHUL_qpm_modify_qp_done: NULL hhul_qp.\n");\r
- return HH_EINVAL;\r
- }\r
-\r
- rc= THHUL_hob_get_qpm(hca,&qpm);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: Failed to get QPM handle (%d=%s)"), __func__, rc, HH_strerror_sym(rc));\r
- return rc;\r
- }\r
-\r
- /* Update in RQ */\r
- if (cur_state == VAPI_RESET) { \r
- /* Cleanup all CQEs of RQ (flush) when moving to reset state */\r
- THHUL_cqm_cq_cleanup(qp->rq_cq, qp->qpn, qpm->srqm, qp->srq);\r
- MOSAL_spinlock_dpc_lock(&(qp->rq_res.q_lock));\r
- qp->rq_res.cur_outs= 0;\r
- qp->rq_res.next2free_index= qp->rq_res.next2post_index= 0;\r
- qp->rq_res.last_posted_p= NULL;\r
- qp->rq_res.qp_state= VAPI_RESET;\r
- \r
- /* point at the last two 32 bit words in the wqe_buf, \r
- * this allows us to remove an if in VAPI_post_sr path */\r
- qp->rq_res.last_posted_p = (volatile u_int32_t*)(qp->rq_res.wqe_buf + (1 << qp->rq_res.log2_max_wqe_sz));\r
- \r
- MOSAL_spinlock_unlock(&(qp->rq_res.q_lock));\r
- } else {\r
- qp->rq_res.qp_state= cur_state;\r
- }\r
- \r
- /* Update in SQ */\r
- if (cur_state == VAPI_RESET) { \r
- /* Cleanup all CQEs of SQ (flush) when moving to reset state */\r
- if (qp->sq_cq != qp->rq_cq) /* additional cleaning required only if SQ's CQ is different */\r
- THHUL_cqm_cq_cleanup(qp->sq_cq, qp->qpn, qpm->srqm, HHUL_INVAL_SRQ_HNDL);\r
- MOSAL_spinlock_dpc_lock(&(qp->sq_res.q_lock));\r
- qp->sq_res.cur_outs= 0;\r
- qp->sq_res.next2free_index= qp->sq_res.next2post_index= 0;\r
- qp->sq_res.last_posted_p= NULL;\r
- qp->sq_res.qp_state= VAPI_RESET;\r
- \r
- /* point at the last two 32 bit words in the wqe_buf, \r
- * this allows us to remove an if in VAPI_post_sr path */\r
- qp->sq_res.last_posted_p = (volatile u_int32_t*)(qp->sq_res.wqe_buf + (1 << qp->sq_res.log2_max_wqe_sz));\r
- \r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock));\r
- } else {\r
- qp->sq_res.qp_state= cur_state;\r
- }\r
-\r
- return HH_OK;\r
-}\r
-\r
-\r
-\r
-#if !(USE_FAST_POST)\r
-/* Original version */\r
-HH_ret_t THHUL_qpm_post_send_req( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_qp_hndl_t hhul_qp, \r
- VAPI_sr_desc_t *send_req_p \r
-) \r
-{ \r
- THHUL_qp_t qp= (THHUL_qp_t)hhul_qp;\r
- u_int32_t* wqe_draft= qp->sq_res.wqe_draft;\r
- u_int32_t wqe_sz_dwords;\r
- HH_hca_hndl_t hca_ul_res_handle;\r
- HH_ret_t rc;\r
-\r
- if (!is_qpstate_valid_2send(qp->sq_res.qp_state)) {\r
- MTL_ERROR1(MT_FLFMT("%s failed: qp state %d not valid to send \n"),__func__,qp->sq_res.qp_state);\r
- return HH_EINVAL_QP_STATE;\r
- }\r
- \r
- if (qp->sq_res.max_sg_sz < send_req_p->sg_lst_len) {\r
- MTL_ERROR2(\r
- "THHUL_qpm_post_send_req: Scatter/Gather list is too large (%d entries > max_sg_sz=%d)\n",\r
- send_req_p->sg_lst_len,qp->sq_res.max_sg_sz);\r
- return HH_EINVAL_SG_NUM;\r
- }\r
- \r
-#ifdef DUMP_SEND_REQ \r
- dump_send_req(qp,send_req_p);\r
-#endif\r
- \r
- MOSAL_spinlock_dpc_lock(&(qp->sq_res.q_lock)); /* protect wqe_draft and WQE allocation/link */\r
- \r
- if (qp->sqp_type == VAPI_REGULAR_QP) {\r
- MTPERF_TIME_START(WQE_build_send);\r
- wqe_sz_dwords= (WQE_build_send(qp,send_req_p,wqe_draft) >> 2);\r
- MTPERF_TIME_END(WQE_build_send);\r
-#ifdef MAX_DEBUG\r
- if ((wqe_sz_dwords<<2) > (1U << qp->sq_res.log2_max_wqe_sz)) {\r
- MTL_ERROR1(MT_FLFMT("QP 0x%X: Send WQE too large (%d > max=%d)"),\r
- qp->qpn,(wqe_sz_dwords<<2),(1U << qp->sq_res.log2_max_wqe_sz));\r
- }\r
-#endif\r
- } else { /* special QP */\r
- if (send_req_p->opcode != VAPI_SEND) {\r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock)); \r
- return HH_EINVAL_OPCODE;\r
- }\r
- send_req_p->fence= FALSE; /* required for MLX requests */\r
- rc= THHUL_hob_get_hca_ul_res_handle(hca,&hca_ul_res_handle);\r
- if (rc != HH_OK) {\r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock)); \r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- wqe_sz_dwords= \r
- (WQE_build_send_mlx(hca_ul_res_handle, qp,send_req_p,QP1_PKEY_INDEX,wqe_draft) >> 2);\r
- if (wqe_sz_dwords == 0) {\r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock)); \r
- MTL_ERROR1(MT_FLFMT("Failed building MLX headers for special QP.\n"));\r
- return HH_EINVAL_WQE;\r
- }\r
- }\r
-\r
- rc= sq_alloc_wqe_link_and_ring(qp,wqe_draft,wqe_sz_dwords,\r
-#ifdef MT_LITTLE_ENDIAN\r
- wqe_sz_dwords,\r
-#endif\r
- send_req_p,encode_nopcode(send_req_p->opcode)); \r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock)); \r
- return rc;\r
-}\r
-\r
-#else /* USE_FAST_POST == 1 */\r
-/* Optimized version of post_send_req\r
- * Remove double copy of building wqe from wqe_draft to wqe_buf, instead\r
- * write driectly to wqe_buf. Conversion to be was done when copy to wqe_buf from\r
- * wqe_draft, now ew have to build big endian version directly. All the function\r
- * with ***_be extention build big_endian version of WQE.\r
- */ \r
-HH_ret_t THHUL_qpm_post_send_req( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_qp_hndl_t hhul_qp, \r
- VAPI_sr_desc_t *send_req_p \r
-) \r
-{ \r
- THHUL_qp_t qp= (THHUL_qp_t)hhul_qp;\r
- u_int32_t wqe_sz_dwords;\r
- THH_hca_ul_resources_t hca_ul_res;\r
- HH_ret_t rc;\r
- volatile u_int32_t* next_wqe; /* Actual WQE pointer */\r
-\r
- \r
- if(MOSAL_EXPECT_FALSE(qp->sq_res.qp_state < VAPI_RTS)) {\r
- MTL_ERROR1(MT_FLFMT("%s failed: qp state %d not valid to send \n"),__func__,qp->sq_res.qp_state);\r
- return HH_EINVAL_QP_STATE;\r
- }\r
- \r
- if (MOSAL_EXPECT_FALSE(qp->sq_res.max_sg_sz < send_req_p->sg_lst_len)) {\r
- MTL_ERROR2(\r
- "THHUL_qpm_post_send_req: Scatter/Gather list is too large (%d entries > max_sg_sz=%d)\n",\r
- send_req_p->sg_lst_len,qp->sq_res.max_sg_sz);\r
- return HH_EINVAL_SG_NUM;\r
- }\r
-\r
-#ifdef DUMP_SEND_REQ \r
- dump_send_req(qp,send_req_p);\r
-#endif\r
- \r
- MOSAL_spinlock_dpc_lock(&(qp->sq_res.q_lock)); /* protect wqe_draft and WQE allocation/link */\r
-\r
- /* Check if any WQEs are free to be consumed */\r
- if (MOSAL_EXPECT_FALSE(qp->sq_res.max_outs == qp->sq_res.cur_outs)) {\r
- MTL_ERROR4("THHUL_qpm_post_send_req: Send queue is full (%u requests outstanding).\n",\r
- qp->sq_res.cur_outs);\r
- return HH_E2BIG_WR_NUM;\r
- }\r
-\r
- /* Allocate next WQE */\r
- /* WQE build directly to wqe_buf, instead of draft, so should call big\r
- * endian version of WQE_build_send \r
- */ \r
- next_wqe= (u_int32_t*)(qp->sq_res.wqe_buf + \r
- (qp->sq_res.next2post_index << qp->sq_res.log2_max_wqe_sz) );\r
-\r
- \r
- if (MOSAL_EXPECT_TRUE(qp->sqp_type == VAPI_REGULAR_QP)) {\r
- /* call big_endian version of WQE_build_send */ \r
- wqe_sz_dwords= (WQE_build_send_be(qp,send_req_p,(u_int32_t*)next_wqe) >> 2);\r
-#ifdef MAX_DEBUG\r
- if ((wqe_sz_dwords<<2) > (1 << qp->sq_res.log2_max_wqe_sz))\r
- MTL_ERROR1(MT_FLFMT("QP 0x%X: Send WQE too large (%d > max=%d)"),\r
- qp->qpn,(wqe_sz_dwords<<2),(1 << qp->sq_res.log2_max_wqe_sz));\r
-#endif\r
- } else { /* special QP */\r
-\r
- u_int32_t* wqe_draft= qp->sq_res.wqe_draft;\r
- unsigned int i; \r
- \r
- if (MOSAL_EXPECT_FALSE(send_req_p->opcode != VAPI_SEND)) {\r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock)); \r
- return HH_EINVAL_WQE;\r
- }\r
- send_req_p->fence= FALSE; /* required for MLX requests */\r
- if(MOSAL_EXPECT_FALSE(THHUL_hob_get_hca_ul_res(hca,&hca_ul_res) != HH_OK))\r
- {\r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock)); \r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- wqe_sz_dwords= (WQE_build_send_mlx(hca_ul_res.hh_hca_hndl,qp,send_req_p,QP1_PKEY_INDEX,wqe_draft) >> 2);\r
- if (MOSAL_EXPECT_FALSE(wqe_sz_dwords == 0)) {\r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock)); \r
- MTL_ERROR1(MT_FLFMT("Failed building MLX headers for special QP.\n"));\r
- return HH_EINVAL_WQE;\r
- }\r
- \r
- /* we used a temporary (draft) memory space, so move it do destination, also\r
- we used the standard routines that don't byte swap each word so byte swap \r
- each word if we are on a little endian cpu */ \r
- for(i = 0; i < wqe_sz_dwords; ++i) { \r
- next_wqe[i] = MOSAL_cpu_to_be32(wqe_draft[i]); \r
- }\r
-\r
- }\r
-\r
- rc= sq_alloc_wqe_link_and_ring_be(qp,(u_int32_t*)next_wqe,wqe_sz_dwords,\r
-#ifdef MT_LITTLE_ENDIAN\r
- wqe_sz_dwords,\r
-#endif\r
- send_req_p,encode_nopcode(send_req_p->opcode)); \r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock)); \r
- return rc;\r
-}\r
-#endif //USE_FAST_POST == 0\r
-\r
-\r
-#if USE_FAST_POST == 0\r
-/* Orignal version of THHUL_qpm_post_inline_send_req */\r
-HH_ret_t THHUL_qpm_post_inline_send_req( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_qp_hndl_t hhul_qp, \r
- VAPI_sr_desc_t *send_req_p \r
-) \r
-{ \r
- THHUL_qp_t qp= (THHUL_qp_t)hhul_qp;\r
- u_int32_t* wqe_draft= qp->sq_res.wqe_draft;\r
- u_int8_t *cur_loc_p= (u_int8_t*)wqe_draft; /* Current location in the WQE */\r
- u_int8_t *wqe_edge_p= ((u_int8_t*)wqe_draft)+(1<<qp->sq_res.log2_max_wqe_sz);\r
- u_int32_t wqe_sz_dwords;\r
- u_int32_t* inline_p; /* inline control word */\r
- u_int32_t i; \r
- HH_ret_t rc;\r
-\r
-#ifdef DUMP_SEND_REQ \r
- dump_send_req(qp,send_req_p);\r
-#endif\r
- \r
- if (!is_qpstate_valid_2send(qp->sq_res.qp_state)) {\r
- MTL_ERROR1(MT_FLFMT("%s failed: qp state %d not valid to send \n"),__func__,qp->sq_res.qp_state);\r
- return HH_EINVAL_QP_STATE;\r
- }\r
-\r
- MOSAL_spinlock_dpc_lock(&(qp->sq_res.q_lock)); /* protect wqe_draft and WQE allocation/link */\r
- \r
- cur_loc_p+= qpm_WQE_init_next((u_int32_t*)cur_loc_p); /* Make "unlinked" "next" segment */\r
- cur_loc_p+= WQE_pack_ctrl_send((u_int32_t*)cur_loc_p, /* Pack Control segment */\r
- send_req_p->comp_type, send_req_p->set_se, 0/*event bit*/,\r
- ((send_req_p->opcode == VAPI_RDMA_WRITE_WITH_IMM) ||\r
- (send_req_p->opcode == VAPI_SEND_WITH_IMM) ) ? send_req_p->imm_data : 0);\r
-\r
- /* Transport type checks: Datagram segment */\r
- switch (qp->ts_type) {\r
- case VAPI_TS_UD: /* Check if UD (UD datagram segment) */\r
- cur_loc_p+= WQE_pack_ud((u_int32_t*)cur_loc_p,\r
- qp->ud_av_memkey,translate_av(qp, (u_int64_t)send_req_p->remote_ah),\r
- send_req_p->remote_qp,send_req_p->remote_qkey);\r
- break;\r
- case VAPI_TS_RD: /* Check if RD (RD datagram segment) */\r
- cur_loc_p+= WQE_pack_rd((u_int32_t*)cur_loc_p,\r
- send_req_p->remote_qp,send_req_p->remote_qkey);\r
- break;\r
- default:\r
- break;\r
- }\r
- \r
- /* Opcode checks + Remote-address/Atomic segments */\r
- switch (send_req_p->opcode) {\r
- /* For RDMA operations: only Remote-address segment */\r
- case VAPI_RDMA_WRITE:\r
- case VAPI_RDMA_WRITE_WITH_IMM:\r
- cur_loc_p+= WQE_pack_remote_addr((u_int32_t*)cur_loc_p,\r
- send_req_p->remote_addr,send_req_p->r_key);\r
- break;\r
- \r
- case VAPI_SEND:\r
- case VAPI_SEND_WITH_IMM:\r
- break; /* Valid opcodes for "inline" but no extra WQE segment */\r
- default: \r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock));\r
- return HH_EINVAL_OPCODE; /* Invalid opcode */\r
- }\r
- \r
- inline_p= (u_int32_t*)cur_loc_p;\r
- cur_loc_p+= WQE_INLINE_SZ_BCOUNT;\r
- /* copy inline data to WQE */\r
- for (i= 0; i < send_req_p->sg_lst_len; i++) {\r
- if ((cur_loc_p+send_req_p->sg_lst_p[i].len) > wqe_edge_p) {\r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock));\r
- MTL_ERROR2(MT_FLFMT("too much inline data for inline send request (qpn=0x%X)"),qp->qpn);\r
- return HH_EINVAL_SG_NUM;\r
- }\r
- if (send_req_p->sg_lst_p[i].addr > (MT_virt_addr_t)MAKE_ULONGLONG(0xFFFFFFFFFFFFFFFF)) {\r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock));\r
- MTL_ERROR2(MT_FLFMT("sg list addr %d has non-zero upper bits (qpn=0x%X, addr="U64_FMT") \n"),\r
- i,qp->qpn,send_req_p->sg_lst_p[i].addr );\r
- return HH_EINVAL_SG_FMT;\r
- }\r
- memcpy(cur_loc_p, (void*)(MT_virt_addr_t)(send_req_p->sg_lst_p[i].addr),\r
- send_req_p->sg_lst_p[i].len); \r
- cur_loc_p+= send_req_p->sg_lst_p[i].len;\r
- }\r
- *inline_p= \r
- (u_int32_t)(0x80000000 | (((MT_virt_addr_t)cur_loc_p) - ((MT_virt_addr_t)inline_p) - 4)); /*inline:size*/\r
-\r
- wqe_sz_dwords= (MT_UP_ALIGNX_U32( (u_int32_t)(((MT_virt_addr_t)cur_loc_p) - ((MT_virt_addr_t)wqe_draft)),\r
- WQE_SZ_MULTIPLE_SHIFT) >> 2); \r
-#ifdef MAX_DEBUG\r
- if ((wqe_sz_dwords<<2) > (1U << qp->sq_res.log2_max_wqe_sz)) {\r
- MTL_ERROR1(MT_FLFMT("QP 0x%X: Send WQE too large (%d > max=%d) !!!!!!!!!"),\r
- qp->qpn,(wqe_sz_dwords<<2),(1U << qp->sq_res.log2_max_wqe_sz));\r
- }\r
-#endif\r
-\r
- rc= sq_alloc_wqe_link_and_ring(qp,wqe_draft,wqe_sz_dwords,\r
-#ifdef MT_LITTLE_ENDIAN\r
- (u_int32_t)(inline_p - wqe_draft + 1), /* swap all up to data */\r
-#endif\r
- send_req_p,encode_nopcode(send_req_p->opcode)); \r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock));\r
- return rc;\r
-}\r
-#else\r
-/* Optimized version of THHUL_qpm_post_inline_send_req.\r
- * Remove extra copy from wqe_draft to wqe, instead driect write to\r
- * Wqe buffer.\r
- */\r
-HH_ret_t THHUL_qpm_post_inline_send_req( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_qp_hndl_t hhul_qp, \r
- VAPI_sr_desc_t *send_req_p \r
-) \r
-{ \r
- THHUL_qp_t qp= (THHUL_qp_t)hhul_qp;\r
- volatile u_int32_t* next_wqe; /* Actual WQE pointer */ \r
- u_int8_t *cur_loc_p; /* Current location in the WQE */\r
- u_int8_t *wqe_edge_p;/* End of Wqe buffer */\r
- u_int32_t wqe_sz_dwords;\r
- u_int32_t* inline_p; /* inline control word */\r
- u_int32_t i; \r
- HH_ret_t rc;\r
-\r
-#ifdef DUMP_SEND_REQ \r
- dump_send_req(qp,send_req_p);\r
-#endif\r
- \r
- if(MOSAL_EXPECT_FALSE(qp->sq_res.qp_state < VAPI_RTS)) {\r
- MTL_ERROR1(MT_FLFMT("%s failed: qp state %d not valid to send \n"),__func__,qp->sq_res.qp_state);\r
- return HH_EINVAL_QP_STATE;\r
- }\r
-\r
- MOSAL_spinlock_dpc_lock(&(qp->sq_res.q_lock)); /* protect wqe_draft and WQE allocation/link */\r
- \r
- /* Allocate next WQE */\r
- /* WQE build directly to wqe_buf, instead of draft, so should call big\r
- * endian version of WQE_build_send \r
- */ \r
- next_wqe= (u_int32_t*)(qp->sq_res.wqe_buf + \r
- (qp->sq_res.next2post_index << qp->sq_res.log2_max_wqe_sz) );\r
- \r
- cur_loc_p = (u_int8_t *)next_wqe; \r
- wqe_edge_p = ((u_int8_t*)next_wqe)+(1<<qp->sq_res.log2_max_wqe_sz); \r
- \r
- cur_loc_p+= qpm_WQE_init_next((u_int32_t*)cur_loc_p); /* Make "unlinked" "next" segment */\r
- cur_loc_p+= WQE_pack_ctrl_send_be((u_int32_t*)cur_loc_p, /* Pack Control segment */\r
- send_req_p->comp_type, send_req_p->set_se, 0/*event bit*/,\r
- ((send_req_p->opcode == VAPI_RDMA_WRITE_WITH_IMM) ||\r
- (send_req_p->opcode == VAPI_SEND_WITH_IMM) ) ? send_req_p->imm_data : 0);\r
-\r
- /* Transport type checks: Datagram segment */\r
- switch (qp->ts_type) {\r
- case VAPI_TS_UD: /* Check if UD (UD datagram segment) */\r
- cur_loc_p+= WQE_pack_ud_be((u_int32_t*)cur_loc_p,\r
- qp->ud_av_memkey,translate_av(qp, (u_int64_t)send_req_p->remote_ah),\r
- send_req_p->remote_qp,send_req_p->remote_qkey);\r
- break;\r
- case VAPI_TS_RD: /* Check if RD (RD datagram segment) */\r
- cur_loc_p+= WQE_pack_rd_be((u_int32_t*)cur_loc_p,\r
- send_req_p->remote_qp,send_req_p->remote_qkey);\r
- break;\r
- default:\r
- break;\r
- }\r
- \r
- /* Opcode checks + Remote-address/Atomic segments */\r
- switch (send_req_p->opcode) {\r
- /* For RDMA operations: only Remote-address segment */\r
- case VAPI_RDMA_WRITE:\r
- case VAPI_RDMA_WRITE_WITH_IMM:\r
- cur_loc_p+= WQE_pack_remote_addr_be((u_int32_t*)cur_loc_p,\r
- send_req_p->remote_addr,send_req_p->r_key);\r
- break;\r
- \r
- case VAPI_SEND:\r
- case VAPI_SEND_WITH_IMM:\r
- break; /* Valid opcodes for "inline" but no extra WQE segment */\r
- default: \r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock));\r
- return HH_EINVAL_OPCODE; /* Invalid opcode */\r
- }\r
- \r
- inline_p= (u_int32_t*)cur_loc_p; \r
- cur_loc_p+= WQE_INLINE_SZ_BCOUNT;\r
- /* copy inline data to WQE */\r
- for (i= 0; i < send_req_p->sg_lst_len; i++) { \r
- if (MOSAL_EXPECT_FALSE((cur_loc_p+send_req_p->sg_lst_p[i].len) > wqe_edge_p)) {\r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock));\r
- MTL_ERROR2(MT_FLFMT("too much inline data for inline send request (qpn=0x%X)"),qp->qpn);\r
- return HH_EINVAL_SG_NUM;\r
- }\r
-//#ifdef MT_64BIT \r
-#if 0 /* TBD: It this needed? */\r
- if (MOSAL_EXPECT_FALSE(send_req_p->sg_lst_p[i].addr > (MT_virt_addr_t)0xFFFFFFFFFFFFFFFF)) {\r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock));\r
- MTL_ERROR2(MT_FLFMT("sg list addr %d has non-zero upper bits (qpn=0x%X, addr="U64_FMT") \n"),\r
- i,qp->qpn,send_req_p->sg_lst_p[i].addr );\r
- return HH_EINVAL_SG_FMT; \r
- }\r
-#endif \r
- memcpy(cur_loc_p, (void*)(MT_virt_addr_t)(send_req_p->sg_lst_p[i].addr),\r
- send_req_p->sg_lst_p[i].len); \r
- cur_loc_p+= send_req_p->sg_lst_p[i].len; \r
- } \r
- *inline_p= \r
- MOSAL_cpu_to_be32(0x80000000 | (u_int32_t)(((MT_ulong_ptr_t)cur_loc_p) - ((MT_ulong_ptr_t)inline_p) - 4)); /*inline:size*/\r
- \r
- wqe_sz_dwords= (MT_UP_ALIGNX( (((MT_virt_addr_t)cur_loc_p) - ((MT_virt_addr_t)next_wqe)),\r
- WQE_SZ_MULTIPLE_SHIFT) >> 2); \r
-\r
-#ifdef MAX_DEBUG\r
- if ((wqe_sz_dwords<<2) > (1 << qp->sq_res.log2_max_wqe_sz)) {\r
- MTL_ERROR1(MT_FLFMT("QP 0x%X: Send WQE too large (%d > max=%d) !!!!!!!!!"),\r
- qp->qpn,(wqe_sz_dwords<<2),(1 << qp->sq_res.log2_max_wqe_sz));\r
- }\r
-#endif\r
-\r
- rc= sq_alloc_wqe_link_and_ring_be(qp,(u_int32_t*)next_wqe,wqe_sz_dwords,\r
-#ifdef MT_LITTLE_ENDIAN\r
- (u_int32_t)(inline_p - next_wqe + 1), /* swap all up to data */\r
-#endif\r
- send_req_p,encode_nopcode(send_req_p->opcode)); \r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock));\r
- return rc;\r
-}\r
-#endif /* USE_FAST_POST == 0 */\r
-\r
-\r
-HH_ret_t THHUL_qpm_post_send_reqs( \r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_qp_hndl_t hhul_qp, \r
- /*IN*/ u_int32_t num_of_requests,\r
- /*IN*/ VAPI_sr_desc_t *send_req_array \r
-)\r
-{\r
- THHUL_qp_t qp= (THHUL_qp_t)hhul_qp;\r
- u_int32_t* wqe_draft= qp->sq_res.wqe_draft;\r
- u_int32_t next_draft[WQE_SEG_SZ_NEXT>>2]; /* Build "next" segment here */\r
- volatile u_int32_t* next_wqe= NULL;\r
- volatile u_int32_t* prev_wqe_p= NULL; \r
- MT_virt_addr_t first_wqe_nda= 0;\r
- u_int32_t first_wqe_nds= 0;\r
- u_int32_t wqe_sz_dwords,i;\r
- u_int32_t next2post_index,reqi;\r
- THH_uar_sendq_dbell_t sq_dbell;\r
-\r
- if (qp->sqp_type != VAPI_REGULAR_QP) {\r
- MTL_ERROR4(MT_FLFMT("THHUL_qpm_post_send_reqs is not supporeted for special QPs"));\r
- return HH_ENOSYS;\r
- }\r
- \r
- if (num_of_requests == 0) {\r
- MTL_ERROR4(MT_FLFMT("THHUL_qpm_post_send_reqs: num_of_requeusts=0 !"));\r
- return HH_EINVAL_PARAM;\r
- }\r
- \r
- if (!is_qpstate_valid_2send(qp->sq_res.qp_state)) {\r
- MTL_ERROR1(MT_FLFMT("%s failed: qp state %d not valid to send \n"),__func__,qp->sq_res.qp_state);\r
- return HH_EINVAL_QP_STATE;\r
- }\r
-\r
- MOSAL_spinlock_dpc_lock(&(qp->sq_res.q_lock)); /* protect wqe_draft as well as WQE allocation/link */\r
- \r
- /* Check for available WQEs */\r
- if (qp->sq_res.max_outs < (qp->sq_res.cur_outs + num_of_requests)) {\r
- MTL_ERROR4("THHUL_qpm_post_send_reqs: Not enough WQEs for %u requests (%u requests outstanding).\n",\r
- num_of_requests,qp->sq_res.cur_outs);\r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock));\r
- return HH_E2BIG_WR_NUM;\r
- }\r
-\r
- /* We hold this value on a seperate var. for easy rollback in case of an error */\r
- next2post_index= qp->sq_res.next2post_index;\r
-\r
- /* Build and link all WQEs */\r
- for (reqi= 0; reqi < num_of_requests; reqi++) {\r
- if (qp->sq_res.max_sg_sz < send_req_array[reqi].sg_lst_len) {\r
- MTL_ERROR2(\r
- "THHUL_qpm_post_send_req: S/G list of request %d is too large (%d entries > max_sg_sz=%d)\n",\r
- reqi,send_req_array[reqi].sg_lst_len,qp->sq_res.max_sg_sz);\r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock));\r
- return HH_EINVAL_SG_NUM;\r
- }\r
-\r
- MTPERF_TIME_START(WQE_build_send);\r
- wqe_sz_dwords= (WQE_build_send(qp,send_req_array+reqi,wqe_draft) >> 2);\r
- MTPERF_TIME_END(WQE_build_send);\r
-#ifdef MAX_DEBUG\r
- if ((wqe_sz_dwords<<2) > (1U << qp->sq_res.log2_max_wqe_sz)) {\r
- MTL_ERROR1(MT_FLFMT("QP 0x%X: Send WQE too large (%d > max=%d)"),\r
- qp->qpn,(wqe_sz_dwords<<2),(1U << qp->sq_res.log2_max_wqe_sz));\r
- }\r
-#endif\r
- /* Allocate next WQE */\r
- next_wqe= (u_int32_t*)(qp->sq_res.wqe_buf + \r
- (next2post_index << qp->sq_res.log2_max_wqe_sz) );\r
- qp->sq_res.wqe_id[next2post_index]= send_req_array[reqi].id; /* Save WQE ID */\r
-// next2post_index = (next2post_index + 1) % qp->sq_res.max_outs ;\r
- if (++next2post_index >= qp->sq_res.max_outs) {\r
- next2post_index = 0;\r
- }\r
- /* copy (while swapping,if needed) the wqe_draft to the actual WQE */\r
- /* TBD: for big-endian machines we can optimize here and use memcpy */\r
- MTPERF_TIME_START(SQ_WQE_copy);\r
- for (i= 0; i < wqe_sz_dwords; i++) {\r
- next_wqe[i]= MOSAL_cpu_to_be32(wqe_draft[i]);\r
- }\r
-\r
- if (reqi == 0) { /* For the first WQE save info for linking it later */\r
- first_wqe_nda= (MT_virt_addr_t)next_wqe;\r
- first_wqe_nds= (wqe_sz_dwords>>2);\r
- \r
- } else { /* Not first - link to previous with DBD=0 */\r
- /* Build linking "next" segment in last posted WQE*/\r
- qpm_WQE_pack_send_next(next_draft, encode_nopcode(send_req_array[reqi].opcode), \r
- send_req_array[reqi].fence,0/*DBD*/, (u_int32_t)(MT_ulong_ptr_t)next_wqe, wqe_sz_dwords>>2, \r
- (qp->ts_type==VAPI_TS_RD) ? send_req_array[reqi].eecn : 0 );\r
- for (i= 0;i < (WQE_SEG_SZ_NEXT>>2) ;i++) { \r
- /* This copy assures big-endian as well as that NDS is written last */\r
- prev_wqe_p[i]= MOSAL_cpu_to_be32(next_draft[i]);\r
- }\r
- }\r
- prev_wqe_p= next_wqe;\r
-\r
- }\r
- \r
- if (qp->sq_res.last_posted_p != NULL) { /* link chain to previous WQE */\r
- /* Build linking "next" segment with DBD set */\r
- qpm_WQE_pack_send_next(next_draft, encode_nopcode(send_req_array[0].opcode), \r
- send_req_array[0].fence,1/*DBD*/, (u_int32_t)first_wqe_nda, first_wqe_nds, \r
- (qp->ts_type==VAPI_TS_RD) ? send_req_array[0].eecn : 0 );\r
- for (i= 0;i < (WQE_SEG_SZ_NEXT>>2) ;i++) { \r
- /* This copy assures big-endian as well as that NDS is written last */\r
- qp->sq_res.last_posted_p[i]= MOSAL_cpu_to_be32(next_draft[i]);\r
- }\r
- }\r
- \r
- /* Update QP status */\r
- qp->sq_res.last_posted_p= next_wqe; \r
- qp->sq_res.next2post_index= next2post_index;\r
- qp->sq_res.cur_outs+= num_of_requests;\r
-\r
- /* Ring doorbell (send or rd-send) */\r
- sq_dbell.qpn= qp->qpn;\r
- sq_dbell.nopcode= encode_nopcode(send_req_array[0].opcode);\r
- sq_dbell.fence= send_req_array[0].fence;\r
- sq_dbell.next_addr_32lsb= (u_int32_t)(first_wqe_nda & 0xFFFFFFFF);\r
- sq_dbell.next_size= first_wqe_nds;\r
- if (qp->ts_type == VAPI_TS_RD) {\r
- THH_uar_sendq_rd_dbell(qp->uar,&sq_dbell,send_req_array[0].eecn);\r
- } else { /* non-RD send request */\r
- MTPERF_TIME_START(THH_uar_sendq_dbell);\r
- THH_uar_sendq_dbell(qp->uar,&sq_dbell);\r
- MTPERF_TIME_END(THH_uar_sendq_dbell);\r
- }\r
-\r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock)); \r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THHUL_qpm_post_gsi_send_req( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_qp_hndl_t hhul_qp, \r
- VAPI_sr_desc_t *send_req_p,\r
- VAPI_pkey_ix_t pkey_index\r
-) \r
-{ \r
- THHUL_qp_t qp= (THHUL_qp_t)hhul_qp;\r
- u_int32_t* wqe_draft= qp->sq_res.wqe_draft;\r
- u_int32_t wqe_sz_dwords;\r
- HH_hca_hndl_t hca_ul_res_handle;\r
- HH_ret_t rc;\r
-\r
- if (MOSAL_EXPECT_FALSE(qp->sqp_type != VAPI_GSI_QP)) {\r
- MTL_ERROR2(MT_FLFMT("Invoked for non-GSI QP (qpn=0x%X)"),qp->qpn);\r
- return HH_EINVAL_QP_NUM;\r
- }\r
- \r
- if (MOSAL_EXPECT_FALSE(qp->sq_res.max_sg_sz < send_req_p->sg_lst_len)) {\r
- MTL_ERROR2(\r
- "%s: Scatter/Gather list is too large (%d entries > max_sg_sz=%d)\n",__func__,\r
- send_req_p->sg_lst_len,qp->sq_res.max_sg_sz);\r
- return HH_EINVAL_SG_NUM;\r
- }\r
- \r
- if (MOSAL_EXPECT_FALSE(!is_qpstate_valid_2send(qp->sq_res.qp_state))) {\r
- MTL_ERROR1(MT_FLFMT("%s failed: qp state %d not valid to send \n"),__func__,qp->sq_res.qp_state);\r
- return HH_EINVAL_QP_STATE;\r
- }\r
-\r
-#ifdef DUMP_SEND_REQ \r
- dump_send_req(qp,send_req_p);\r
-#endif\r
- \r
- send_req_p->fence= FALSE; /* required for MLX requests */\r
- rc= THHUL_hob_get_hca_ul_res_handle(hca,&hca_ul_res_handle);\r
- if (rc != HH_OK) {\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
-\r
- MOSAL_spinlock_dpc_lock(&(qp->sq_res.q_lock)); /* protect wqe_draft and WQE allocation/link */\r
- \r
- wqe_sz_dwords= \r
- (WQE_build_send_mlx(hca_ul_res_handle,qp,send_req_p,pkey_index,wqe_draft) >> 2);\r
- if (wqe_sz_dwords == 0) {\r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock)); \r
- MTL_ERROR1(MT_FLFMT("Failed building MLX headers for special QP.\n"));\r
- return HH_EINVAL_WQE;\r
- }\r
-\r
- rc= sq_alloc_wqe_link_and_ring(qp,wqe_draft,wqe_sz_dwords,\r
-#ifdef MT_LITTLE_ENDIAN\r
- wqe_sz_dwords,\r
-#endif\r
- send_req_p,encode_nopcode(send_req_p->opcode)); \r
- \r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock)); \r
- return rc;\r
-}\r
-\r
-\r
-/* Orignal version of THHUL_qpm_post_recv_req */\r
-#if !(USE_FAST_POST)\r
-HH_ret_t THHUL_qpm_post_recv_req( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_qp_hndl_t hhul_qp, \r
- VAPI_rr_desc_t *recv_req_p \r
-) \r
-{ \r
- THHUL_qp_t qp= (THHUL_qp_t)hhul_qp;\r
- u_int32_t* wqe_draft= qp->rq_res.wqe_draft;\r
- u_int32_t next_draft[WQE_SEG_SZ_NEXT>>2]; /* Build "next" segment here */\r
- volatile u_int32_t* next_wqe; /* Actual WQE pointer */\r
- u_int32_t i, wqe_sz_dwords;\r
- THH_uar_recvq_dbell_t rq_dbell;\r
-\r
- if (qp->srq != HHUL_INVAL_SRQ_HNDL) {\r
- MTL_ERROR1(MT_FLFMT("%s: Used for QP 0x%X which is associated with SRQ handle 0x%p"), __func__,\r
- qp->qpn, qp->srq);\r
- return HH_EINVAL_SRQ_HNDL;\r
- }\r
-\r
- if (!is_qpstate_valid_2recv(qp->rq_res.qp_state)) {\r
- MTL_ERROR1(MT_FLFMT("%s failed: qp state %d not valid to recv \n"),__func__,qp->rq_res.qp_state);\r
- return HH_EINVAL_QP_STATE;\r
- }\r
-\r
- if (qp->rq_res.max_sg_sz < recv_req_p->sg_lst_len) {\r
- MTL_ERROR2(\r
- "THHUL_qpm_post_recv_req: Scatter/Gather list is too large (%d entries > max_sg_sz=%d)\n",\r
- recv_req_p->sg_lst_len,qp->rq_res.max_sg_sz);\r
- return HH_EINVAL_SG_NUM;\r
- }\r
- \r
- MOSAL_spinlock_dpc_lock(&(qp->rq_res.q_lock)); /* protect wqe_draft as well as WQE allocation/link */\r
- \r
- /* Build WQE */\r
- wqe_sz_dwords= (qpm_WQE_build_recv(qp,recv_req_p,wqe_draft) >> 2);\r
-#ifdef MAX_DEBUG\r
- if ((wqe_sz_dwords<<2) > (1U << qp->rq_res.log2_max_wqe_sz)) {\r
- MTL_ERROR1(MT_FLFMT("QP 0x%X: Receive WQE too large (%d > max=%d)"),\r
- qp->qpn,(wqe_sz_dwords<<2),(1U << qp->rq_res.log2_max_wqe_sz));\r
- }\r
-#endif\r
-\r
- /* Check if any WQEs are free to be consumed */\r
- if (qp->rq_res.max_outs == qp->rq_res.cur_outs) {\r
- MOSAL_spinlock_unlock(&(qp->rq_res.q_lock));\r
- MTL_ERROR4("THHUL_qpm_post_recv_req: Receive queue is full (%d requests outstanding).\n",\r
- qp->rq_res.cur_outs);\r
- return HH_E2BIG_WR_NUM;\r
- }\r
- /* Allocate next WQE */\r
- next_wqe= (u_int32_t*) (qp->rq_res.wqe_buf + \r
- (qp->rq_res.next2post_index << qp->rq_res.log2_max_wqe_sz) );\r
- qp->rq_res.wqe_id[qp->rq_res.next2post_index]= recv_req_p->id; /* Save WQE ID */\r
- qp->rq_res.next2post_index = (qp->rq_res.next2post_index + 1) % qp->rq_res.max_outs ;\r
- qp->rq_res.cur_outs++;\r
- \r
- /* copy (while swapping,if needed) the wqe_draft to the actual WQE */\r
- /* TBD: for big-endian machines we can optimize here and use memcpy */\r
- for (i= 0; i < wqe_sz_dwords; i++) {\r
- next_wqe[i]= MOSAL_cpu_to_be32(wqe_draft[i]);\r
- }\r
-\r
- /* Update "next" segment of previous WQE (if any) */\r
- if (qp->rq_res.last_posted_p != NULL) {\r
- /* Build linking "next" segment in last posted WQE */\r
- qpm_WQE_pack_recv_next(next_draft, (u_int32_t)(MT_ulong_ptr_t) next_wqe, wqe_sz_dwords>>2);\r
- for (i= 0;i < (WQE_SEG_SZ_NEXT>>2) ;i++) { \r
- /* This copy assures big-endian as well as that NDS is written last */\r
- qp->rq_res.last_posted_p[i]= MOSAL_cpu_to_be32(next_draft[i]);\r
- }\r
- }\r
- qp->rq_res.last_posted_p= next_wqe;\r
- \r
- /* Ring doorbell */\r
- rq_dbell.qpn= qp->qpn;\r
- rq_dbell.next_addr_32lsb= (u_int32_t)((MT_virt_addr_t)next_wqe & 0xFFFFFFFF);\r
- rq_dbell.next_size= wqe_sz_dwords>>2;\r
- rq_dbell.credits= 1;\r
- THH_uar_recvq_dbell(qp->uar,&rq_dbell);\r
-\r
- MOSAL_spinlock_unlock(&(qp->rq_res.q_lock));\r
- return HH_OK;\r
- \r
-}\r
-#else /* USE_FAST_POST == 1 */\r
-/* Optimized version of post_recv_reqs \r
- * Remove double copy of building wqe from wqe_draft to wqe_buf, instead\r
- * write driectly to wqe_buf. Conversion to be was done when copy to wqe_buf from\r
- * wqe_draft, now ew have to build big endian version directly. All the function\r
- * with ***_be extention build big_endian version of WQE.\r
- */ \r
-HH_ret_t THHUL_qpm_post_recv_req( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_qp_hndl_t hhul_qp, \r
- VAPI_rr_desc_t *recv_req_p \r
-) \r
-{ \r
- THHUL_qp_t qp= (THHUL_qp_t)hhul_qp;\r
- volatile u_int32_t* next_wqe; /* Actual WQE pointer */\r
- u_int32_t wqe_sz_dwords;\r
- CHIME_WORDS_PREFIX u_int32_t chimeWords[2];\r
- THH_uar_t uar;\r
-\r
- if (MOSAL_EXPECT_FALSE(qp->srq != HHUL_INVAL_SRQ_HNDL)) {\r
- MTL_ERROR1(MT_FLFMT("%s: Used for QP 0x%X which is associated with SRQ handle 0x%p"), __func__,\r
- qp->qpn, qp->srq);\r
- return HH_EINVAL_SRQ_HNDL;\r
- }\r
- \r
- if (MOSAL_EXPECT_FALSE(qp->rq_res.qp_state < VAPI_INIT )) {\r
- MTL_ERROR1(MT_FLFMT("%s failed: qp state %d not valid to recv \n"),__func__,qp->rq_res.qp_state);\r
- return HH_EINVAL_QP_STATE;\r
- }\r
-\r
- if (MOSAL_EXPECT_FALSE(qp->rq_res.max_sg_sz < recv_req_p->sg_lst_len)) {\r
- MTL_ERROR2(\r
- "THHUL_qpm_post_recv_req: Scatter/Gather list is too large (%d entries > max_sg_sz=%d)\n",\r
- recv_req_p->sg_lst_len,qp->rq_res.max_sg_sz);\r
- return HH_EINVAL_SG_NUM;\r
- }\r
- \r
- MOSAL_spinlock_dpc_lock(&(qp->rq_res.q_lock)); /* protect wqe_draft as well as WQE allocation/link */\r
- \r
- /* Check if any WQEs are free to be consumed */\r
- if (MOSAL_EXPECT_FALSE(qp->rq_res.max_outs == qp->rq_res.cur_outs)) {\r
- MOSAL_spinlock_unlock(&(qp->rq_res.q_lock));\r
- MTL_ERROR4("THHUL_qpm_post_recv_req: Receive queue is full (%d requests outstanding).\n",\r
- qp->rq_res.cur_outs);\r
- return HH_E2BIG_WR_NUM;\r
- }\r
- /* Allocate next WQE */\r
- /* Build WQE directly to wqe_buf, instead of draft. This will eliminate extra copy, but\r
- * shuold build big endian version */\r
- next_wqe= (u_int32_t*) (qp->rq_res.wqe_buf + \r
- (qp->rq_res.next2post_index << qp->rq_res.log2_max_wqe_sz) );\r
- \r
- /* Build WQE */\r
- /* Call big Endian version of WQE_build_recv */\r
- wqe_sz_dwords= (WQE_build_recv_be(qp,recv_req_p,(u_int32_t*)next_wqe) >> 2);\r
-#ifdef MAX_DEBUG\r
- if ((wqe_sz_dwords<<2) > (1 << qp->rq_res.log2_max_wqe_sz)) {\r
- MTL_ERROR1(MT_FLFMT("QP 0x%X: Receive WQE too large (%d > max=%d)"),\r
- qp->qpn,(wqe_sz_dwords<<2),(1 << qp->rq_res.log2_max_wqe_sz));\r
- }\r
-#endif\r
-\r
- qp->rq_res.wqe_id[qp->rq_res.next2post_index]= recv_req_p->id; /* Save WQE ID */\r
- ++qp->rq_res.next2post_index;\r
- if(MOSAL_EXPECT_FALSE(qp->rq_res.next2post_index >= qp->rq_res.max_outs))\r
- qp->rq_res.next2post_index = 0;\r
- \r
- qp->rq_res.cur_outs++;\r
- \r
- /* Update "next" segment of previous WQE (if any) */\r
- /* Build linking "next" segment in last posted WQE */\r
- WQE_pack_recv_next_be((u_int32_t*)qp->rq_res.last_posted_p, \r
- (u_int32_t)(MT_ulong_ptr_t) next_wqe, wqe_sz_dwords>>2);\r
-\r
- qp->rq_res.last_posted_p= next_wqe;\r
- \r
- /* Ring doorbell */ \r
- uar = qp->uar;\r
-\r
- chimeWords[0] = MOSAL_cpu_to_be32(0\r
- | (u_int32_t)((MT_ulong_ptr_t)next_wqe & 0xFFFFFFFF)\r
- | ((wqe_sz_dwords + 3) >> 2) // specify in 16 byte chunks\r
- );\r
- \r
- chimeWords[1] = MOSAL_cpu_to_be32(0\r
- | 1 // credits\r
- | ((u_int32_t)(qp->qpn) << 8)\r
- );\r
-\r
-#ifdef __MOSAL_MMAP_IO_WRITE_QWORD_ATOMIC__\r
- MOSAL_MMAP_IO_WRITE_QWORD(((u_int32_t *)&uar->uar_base[UAR_RECV_DBELL_OFFSET]),*(volatile u_int64_t*)chimeWords);\r
-#else\r
- MOSAL_spinlock_dpc_lock(&(uar->uar_lock));\r
- MOSAL_MMAP_IO_WRITE_QWORD(((u_int32_t *)&uar->uar_base[UAR_RECV_DBELL_OFFSET]),*(volatile u_int64_t*)chimeWords);\r
- MOSAL_spinlock_unlock(&(uar->uar_lock));\r
-#endif\r
- \r
- MOSAL_spinlock_unlock(&(qp->rq_res.q_lock));\r
- \r
- return HH_OK;\r
-} \r
-#endif\r
-\r
-\r
-HH_ret_t THHUL_qpm_post_recv_reqs(\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_qp_hndl_t hhul_qp, \r
- /*IN*/ u_int32_t num_of_requests,\r
- /*IN*/ VAPI_rr_desc_t *recv_req_array \r
- )\r
-{\r
- THHUL_qp_t qp= (THHUL_qp_t)hhul_qp;\r
- u_int32_t* wqe_draft= qp->rq_res.wqe_draft;\r
- u_int32_t next_draft[WQE_SEG_SZ_NEXT>>2]; /* Build "next" segment here */\r
- volatile u_int32_t* next_wqe= NULL; /* Actual WQE pointer */\r
- volatile u_int32_t* prev_wqe_p= qp->rq_res.last_posted_p; \r
- u_int32_t wqe_sz_dwords= 0;\r
- u_int32_t i,reqi,next2post_index;\r
- THH_uar_recvq_dbell_t rq_dbell;\r
- u_int32_t remaining_reqs;\r
-\r
- if (qp->srq != HHUL_INVAL_SRQ_HNDL) {\r
- MTL_ERROR1(MT_FLFMT("%s: Used for QP 0x%X which is associated with SRQ 0x%p"), __func__,\r
- qp->qpn, qp->srq);\r
- return HH_EINVAL_SRQ_HNDL;\r
- }\r
-\r
- if (!is_qpstate_valid_2recv(qp->rq_res.qp_state)) {\r
- MTL_ERROR1(MT_FLFMT("%s failed: qp state %d not valid to recv \n"),__func__,qp->rq_res.qp_state);\r
- return HH_EINVAL_QP_STATE;\r
- }\r
-\r
- if (num_of_requests == 0) {\r
- MTL_ERROR4(MT_FLFMT("THHUL_qpm_post_recv_reqs: num_of_requeusts=0 !"));\r
- return HH_EINVAL_PARAM;\r
- }\r
-\r
- /* Check parameters of all WQEs first - must assure all posted successfully */\r
- for (reqi= 0; reqi < num_of_requests; reqi++) {\r
- if (qp->rq_res.max_sg_sz < recv_req_array[reqi].sg_lst_len) {\r
- MTL_ERROR2(\r
- "THHUL_qpm_post_recv_reqs: S/G list of req. #%d is too large (%d entries > max_sg_sz=%d)\n",\r
- reqi,recv_req_array[reqi].sg_lst_len,qp->rq_res.max_sg_sz);\r
- return HH_EINVAL_SG_NUM;\r
- }\r
- }\r
-\r
- MOSAL_spinlock_dpc_lock(&(qp->rq_res.q_lock)); /* protect wqe_draft as well as WQE allocation/link */\r
- \r
- /* Check for available WQEs */\r
- if (qp->rq_res.max_outs < (qp->rq_res.cur_outs + num_of_requests)) {\r
- MTL_ERROR4("THHUL_qpm_post_recv_reqs: Not enough WQEs for %d requests (%d requests outstanding).\n",\r
- num_of_requests,qp->rq_res.cur_outs);\r
- MOSAL_spinlock_unlock(&(qp->rq_res.q_lock));\r
- return HH_E2BIG_WR_NUM;\r
- }\r
-\r
- rq_dbell.qpn= qp->qpn; /* Fixed for all doorbells */\r
- rq_dbell.credits= 0; /* During the loop, doorbell is rung every 256 WQEs */\r
- \r
- /* We hold this value on a seperate var. for easy rollback in case of an error */\r
- next2post_index= qp->rq_res.next2post_index;\r
-\r
- /* Build and link and ring all WQEs */\r
- for (reqi= 0; reqi < num_of_requests; reqi++) {\r
- \r
- /* Build WQE */\r
- wqe_sz_dwords= (qpm_WQE_build_recv(qp,recv_req_array+reqi,wqe_draft) >> 2);\r
- #ifdef MAX_DEBUG\r
- if ((wqe_sz_dwords<<2) > (1U << qp->rq_res.log2_max_wqe_sz)) {\r
- MTL_ERROR1(MT_FLFMT("QP 0x%X: Receive WQE too large (%d > max=%d)"),\r
- qp->qpn,(wqe_sz_dwords<<2),(1U << qp->rq_res.log2_max_wqe_sz));\r
- }\r
- #endif\r
- \r
- /* Allocate next WQE */\r
- next_wqe= (u_int32_t*) (qp->rq_res.wqe_buf + \r
- (next2post_index << qp->rq_res.log2_max_wqe_sz) );\r
- qp->rq_res.wqe_id[next2post_index]= recv_req_array[reqi].id; /* Save WQE ID */\r
- next2post_index = (next2post_index + 1) % qp->rq_res.max_outs ;\r
-\r
- /* copy (while swapping,if needed) the wqe_draft to the actual WQE */\r
- /* TBD: for big-endian machines we can optimize here and use memcpy */\r
- for (i= 0; i < wqe_sz_dwords; i++) {\r
- next_wqe[i]= MOSAL_cpu_to_be32(wqe_draft[i]);\r
- }\r
- \r
- if ((reqi & 0xFF) == 0) { \r
- /* save NDA+NDS of first WQE in each 256 WQEs chain for the doorbell */\r
- rq_dbell.next_addr_32lsb= (u_int32_t)((MT_virt_addr_t)next_wqe & 0xFFFFFFFF);\r
- rq_dbell.next_size= wqe_sz_dwords>>2;\r
- }\r
-\r
- if (prev_wqe_p != NULL) { /* first in the chain may be the first since reset */\r
- /* Update "next" segment of previous WQE */\r
- /* Build linking "next" segment in last posted WQE */\r
- qpm_WQE_pack_recv_next(next_draft, (u_int32_t)(MT_ulong_ptr_t)next_wqe, wqe_sz_dwords>>2);\r
- for (i= 0;i < (WQE_SEG_SZ_NEXT>>2) ;i++) {\r
- /* This copy assures big-endian as well as that NDS is written last */\r
- prev_wqe_p[i]= MOSAL_cpu_to_be32(next_draft[i]);\r
- }\r
- }\r
- prev_wqe_p= next_wqe;\r
-\r
- if ((reqi & 0xFF) == 0xFF) { /* last in 256 WQEs chain - ring doorbell */\r
- /* Ring doorbell on the first WQE only */\r
- THH_uar_recvq_dbell(qp->uar,&rq_dbell);\r
- }\r
- }\r
-\r
- if ((reqi & 0xFF) != 0) { /* Doorbel for last WQEs was not rung */\r
- rq_dbell.credits= (reqi & 0xFF);\r
- THH_uar_recvq_dbell(qp->uar,&rq_dbell);\r
- }\r
- \r
- qp->rq_res.last_posted_p= next_wqe;\r
-\r
- /* update producer index + cur. outstanding (now that no error was found) */\r
- qp->rq_res.next2post_index = next2post_index;\r
- qp->rq_res.cur_outs+= num_of_requests;\r
- \r
- MOSAL_spinlock_unlock(&(qp->rq_res.q_lock));\r
- return HH_OK;\r
-}\r
-\r
-\r
-\r
-HH_ret_t THHUL_qpm_post_bind_req(\r
- /*IN*/ HHUL_mw_bind_t *bind_props_p,\r
- /*IN*/ IB_rkey_t new_rkey\r
-)\r
-{\r
- THHUL_qp_t qp= (THHUL_qp_t)bind_props_p->qp;\r
- u_int32_t wqe_draft[BIND_WQE_SZ>>2]; /* Build the WQE here */\r
- u_int32_t wqe_sz_dwords;\r
- VAPI_sr_desc_t send_req;\r
-\r
- if ((qp->sqp_type != VAPI_REGULAR_QP) ||\r
- ((qp->ts_type != VAPI_TS_RC) && (qp->ts_type != VAPI_TS_RD) && (qp->ts_type != VAPI_TS_UC))){\r
- MTL_ERROR1(MT_FLFMT("Invalid QP type for binding memory windows (qpn=0x%X)."),qp->qpn);\r
- return HH_EINVAL_QP_NUM;\r
- }\r
- \r
- \r
- if (!is_qpstate_valid_2send(qp->sq_res.qp_state)) {\r
- MTL_ERROR1(MT_FLFMT("%s failed: qp state %d not valid to send \n"),__func__,qp->sq_res.qp_state);\r
- return HH_EINVAL_QP_STATE;\r
- }\r
-\r
- \r
- wqe_sz_dwords= (WQE_build_membind(bind_props_p,new_rkey,wqe_draft) >> 2);\r
-#ifdef MAX_DEBUG\r
- if ((wqe_sz_dwords<<2) > (1U << qp->sq_res.log2_max_wqe_sz)) {\r
- MTL_ERROR1(MT_FLFMT("QP 0x%X: Send WQE too large (%d > max=%d)"),\r
- qp->qpn,(wqe_sz_dwords<<2),(1U << qp->sq_res.log2_max_wqe_sz));\r
- }\r
-#endif\r
-\r
- send_req.id= bind_props_p->id;\r
- send_req.fence= TRUE; /* just in case, though implicitly fenced */\r
- if (qp->ts_type == VAPI_TS_RD) {\r
- send_req.eecn= RESERVED_MEMBIND_EECN;\r
- }\r
-\r
- return sq_alloc_wqe_link_and_ring(qp,wqe_draft,wqe_sz_dwords,\r
-#ifdef MT_LITTLE_ENDIAN\r
- wqe_sz_dwords,\r
-#endif\r
- &send_req,TAVOR_IF_NOPCODE_BIND_MEMWIN);\r
-}\r
-\r
-\r
-\r
-HH_ret_t THHUL_qpm_comp_ok( \r
- THHUL_qpm_t qpm, \r
- IB_wqpn_t qpn,\r
- u_int32_t wqe_addr_32lsb, \r
- VAPI_special_qp_t *qp_type_p,\r
- IB_ts_t *qp_ts_type_p,\r
- VAPI_wr_id_t *wqe_id_p,\r
- u_int32_t *wqes_released_p\r
-#ifdef IVAPI_THH\r
- , u_int32_t *reserved_p\r
-#endif \r
-) \r
-{ \r
- u_int32_t freed_wqe_index;\r
- queue_res_t *associated_q= NULL;\r
- THHUL_qp_t qp;\r
- HH_ret_t rc;\r
-\r
- rc= find_wqe(qpm,qpn,wqe_addr_32lsb,&qp,&associated_q,&freed_wqe_index,wqe_id_p);\r
- if (MOSAL_EXPECT_FALSE(rc != HH_OK)) {\r
- MTL_ERROR2("%s: Given QPN/WQE is not associated with any queue (qpn=0x%X,wqe=0x%X).\n", \r
- __func__,qpn,wqe_addr_32lsb);\r
- return HH_EINVAL;\r
- }\r
-\r
- if (MOSAL_EXPECT_FALSE( (qp->ts_type == IB_TS_RD) && (qp->sqp_type == VAPI_REGULAR_QP))) {\r
- /* RD is a completely different story due to out of order completion */\r
- MTL_ERROR4("THHUL_qpm_comp_ok: RD WQEs tracking not supported, yet.\n");\r
- return HH_ENOSYS; /* TBD: implement when THH should support RD */\r
- }\r
- \r
- *qp_type_p= qp->sqp_type;\r
- *qp_ts_type_p= qp->ts_type;\r
-\r
- if (associated_q != NULL) { /* Release WQEs (if not from SRQ) */\r
- MOSAL_spinlock_dpc_lock(&(associated_q->q_lock));\r
- *wqes_released_p= \r
- (associated_q->next2free_index <= freed_wqe_index) ? \r
- /* Unsigned computation depends on cycic indecies relation (who is the upper index) */\r
- 1+ freed_wqe_index - associated_q->next2free_index :\r
- 1+ associated_q->max_outs - (associated_q->next2free_index - freed_wqe_index);\r
- /* The +1 results from the fact that next2free_index should be counted as well */\r
-// associated_q->next2free_index= (freed_wqe_index + 1) % associated_q->max_outs;\r
- if (MOSAL_EXPECT_FALSE(++freed_wqe_index >= associated_q->max_outs)) {\r
- freed_wqe_index = 0;\r
- }\r
- associated_q->next2free_index= freed_wqe_index;\r
- associated_q->cur_outs -= *wqes_released_p;\r
- MOSAL_spinlock_unlock(&(associated_q->q_lock));\r
- }\r
-\r
- return HH_OK;\r
-}\r
-\r
-\r
-HH_ret_t THHUL_qpm_comp_err( \r
- THHUL_qpm_t qpm, \r
- IB_wqpn_t qpn, \r
- u_int32_t wqe_addr_32lsb, \r
- VAPI_wr_id_t *wqe_id_p,\r
- u_int32_t *wqes_released_p, \r
- u_int32_t *next_wqe_32lsb_p,\r
- u_int8_t *dbd_bit_p\r
-) \r
-{ \r
- u_int32_t freed_wqe_index;\r
- queue_res_t *associated_q;\r
- THHUL_qp_t qp;\r
- u_int32_t* completed_wqe;\r
- HH_ret_t rc;\r
-\r
- rc= find_wqe(qpm,qpn,wqe_addr_32lsb,&qp,&associated_q,&freed_wqe_index,wqe_id_p);\r
- if (rc != HH_OK) {\r
- MTL_ERROR2(\r
- "%s: Given QPN/WQE is not associated with any queue (qpn=0x%X,wqe=0x%X).\n",__func__,\r
- qpn,wqe_addr_32lsb);\r
- return HH_EINVAL;\r
- }\r
-\r
- if ( (qp->ts_type == IB_TS_RD) && (qp->sqp_type == VAPI_REGULAR_QP) ) {\r
- /* RD is a completely different story due to out of order completion */\r
- MTL_ERROR4("%s: RD WQEs tracking not supported, yet.\n", __func__);\r
- return HH_ENOSYS; /* TBD: implement when THH should support RD */\r
- }\r
-\r
- if (associated_q != NULL) { /* Not from SRQ */\r
- MOSAL_spinlock_dpc_lock(&(associated_q->q_lock));\r
- *wqes_released_p= \r
- (associated_q->next2free_index <= freed_wqe_index) ? \r
- /* Unsigned computation depends on cycic indecies relation (who is the upper index) */\r
- 1+ freed_wqe_index - associated_q->next2free_index :\r
- 1+ associated_q->max_outs - (associated_q->next2free_index - freed_wqe_index);\r
- /* The +1 results from the fact that next2free_index should be counted as well */\r
-// associated_q->next2free_index= (freed_wqe_index + 1) % associated_q->max_outs;\r
- if (++freed_wqe_index >= associated_q->max_outs) {\r
- freed_wqe_index = 0;\r
- }\r
- associated_q->next2free_index= freed_wqe_index;\r
- associated_q->cur_outs -= *wqes_released_p;\r
- if (sizeof(MT_virt_addr_t) <= 4) { /* Optimization for 32bit machines */\r
- completed_wqe= (u_int32_t*)(MT_virt_addr_t) wqe_addr_32lsb;\r
- } else {\r
- completed_wqe= (u_int32_t*)(MT_virt_addr_t)\r
- (((associated_q->wqe_buf) & MAKE_ULONGLONG(0xFFFFFFFF00000000)) | (u_int64_t)wqe_addr_32lsb );\r
- }\r
- if (qpm_WQE_extract_nds(completed_wqe) == 0) {\r
- *next_wqe_32lsb_p= THHUL_QPM_END_OF_WQE_CHAIN; /* Chain end reached */\r
- } else {\r
- *next_wqe_32lsb_p= qpm_WQE_extract_nda(completed_wqe);\r
- }\r
- *dbd_bit_p= qpm_WQE_extract_dbd(completed_wqe);\r
- MOSAL_spinlock_unlock(&(associated_q->q_lock));\r
- \r
- } else { /* SRQ - all WQEs generate CQEs... no need to provide NDA */\r
- *wqes_released_p= 1;\r
- *next_wqe_32lsb_p= THHUL_QPM_END_OF_WQE_CHAIN; /* Chain end reached */\r
- }\r
-\r
- return HH_OK;\r
-}\r
-\r
-u_int32_t THHUL_qpm_wqe_cnt( \r
- /*IN*/THHUL_qpm_t qpm, \r
- /*IN*/IB_wqpn_t qpn, \r
- /*IN*/u_int32_t wqe_addr_32lsb, \r
- /*IN*/u_int16_t dbd_cnt)\r
-{\r
- u_int32_t cur_wqe_index;\r
- queue_res_t *associated_q;\r
- THHUL_qp_t qp;\r
- volatile u_int32_t *cur_wqe_p;\r
- u_int32_t wqe_cntr= 0;\r
- VAPI_wr_id_t wqe_id;\r
- HH_ret_t rc;\r
-\r
- rc= find_wqe(qpm,qpn,wqe_addr_32lsb,&qp,&associated_q,&cur_wqe_index,&wqe_id);\r
- if (rc != HH_OK) {\r
- MTL_ERROR2(\r
- "%s: Given QPN/WQE is not associated with any queue (qpn=%d,wqe=0x%X).\n",__func__,\r
- qpn,wqe_addr_32lsb);\r
- return 0;\r
- }\r
-\r
- if ( (qp->ts_type == IB_TS_RD) && (qp->sqp_type == VAPI_REGULAR_QP) ) {\r
- /* RD is a completely different story due to out of order completion */\r
- MTL_ERROR4("%s: RD WQEs tracking not supported, yet.\n",__func__);\r
- return 0; /* TBD: implement when THH should support RD */\r
- }\r
-\r
- if (associated_q == NULL) { /* SRQ */\r
- /* Only one WQE per CQE for SRQs */\r
- return 1;\r
- }\r
-\r
- dbd_cnt++; /* count down to zero (dbd_cnt==0 when waiting for next dbd bit set) */\r
- MOSAL_spinlock_dpc_lock(&(associated_q->q_lock));\r
- do {\r
- wqe_cntr++;\r
- cur_wqe_p= (u_int32_t*)(associated_q->wqe_buf + \r
- (cur_wqe_index << associated_q->log2_max_wqe_sz) );\r
- dbd_cnt-= qpm_WQE_extract_dbd(cur_wqe_p);\r
-// cur_wqe_index= (cur_wqe_index + 1) % associated_q->max_outs;\r
- if (++cur_wqe_index >= associated_q->max_outs) {\r
- cur_wqe_index=0;\r
- }\r
- } while ((dbd_cnt > 0) && (qpm_WQE_extract_nds(cur_wqe_p) != 0));\r
- MOSAL_spinlock_unlock(&(associated_q->q_lock));\r
-\r
- return wqe_cntr;\r
-}\r
-\r
-/**********************************************************************************************\r
- * Private Functions\r
- **********************************************************************************************/\r
-\r
-/* \r
- * Prepare QP resources before creation.\r
- * To be used by both THH_qpm_create_qp_prep and THH_qpm_special_qp_prep\r
- */\r
-static HH_ret_t qp_prep(\r
- HHUL_hca_hndl_t hca, \r
- VAPI_special_qp_t qp_type, \r
- HHUL_qp_init_attr_t *qp_init_attr_p, \r
- HHUL_qp_hndl_t *qp_hndl_p, \r
- VAPI_qp_cap_t *qp_cap_out_p, \r
- THH_qp_ul_resources_t *qp_ul_resources_p,\r
- MT_bool in_ddr_mem /* WQEs buffer allocated in attached DDR mem. or in main memory */\r
-)\r
-{\r
- THHUL_qpm_t qpm;\r
- THH_hca_ul_resources_t hca_ul_res;\r
- THHUL_qp_t new_qp;\r
- HH_ret_t rc;\r
- THHUL_pdm_t pdm;\r
- MT_bool pd_ok_for_sqp;\r
- VAPI_lkey_t ud_av_memkey; /*irrelevant here */\r
- char* av_ddr_base; /*irrelevant here */\r
- char* av_host_base; /*irrelevant here */\r
- \r
- rc= THHUL_hob_get_qpm(hca,&qpm);\r
- if (rc != HH_OK) {\r
- MTL_ERROR4(MT_FLFMT("qp_prep: Invalid HCA handle (%p)."),hca);\r
- return HH_EINVAL;\r
- }\r
- rc= THHUL_hob_get_hca_ul_res(hca,&hca_ul_res);\r
- if (rc != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("qp_prep: Failed THHUL_hob_get_hca_ul_res (err=%d).\n"),rc);\r
- return rc;\r
- }\r
- \r
- rc= THHUL_hob_get_pdm(hca,&pdm);\r
- if (rc != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("qp_prep: Failed THHUL_hob_get_pdm (err=%d).\n"),rc);\r
- return rc;\r
- }\r
- \r
- rc= THHUL_pdm_get_ud_av_memkey_sqp_ok(pdm,qp_init_attr_p->pd,&pd_ok_for_sqp,&ud_av_memkey, &av_ddr_base, &av_host_base);\r
- if (rc != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("qp_prep: Failed THHUL_pdm_get_ud_av_memkey_sqp_ok (err=%d).\n"),rc);\r
- return rc;\r
- }\r
- \r
- if (qp_type != VAPI_REGULAR_QP && pd_ok_for_sqp == FALSE) {\r
- /* the protection domain uses DDR memory for UDAV's -- not good for sqps */\r
- MTL_ERROR2(MT_FLFMT("***WARNING***: AVs for special QPs should use HOST memory; the provided PD has its AVs in DDR memory.\n"));\r
- //return HH_EINVAL;\r
- }\r
-\r
- (new_qp)= (THHUL_qp_t)MALLOC(sizeof(struct THHUL_qp_st));\r
- if (new_qp == NULL) {\r
- MTL_ERROR1(MT_FLFMT("qp_prep: Failed allocating THHUL_qp_t.\n"));\r
- return HH_EAGAIN;\r
- }\r
- memset(new_qp,0,sizeof(struct THHUL_qp_st));\r
-\r
- new_qp->sqp_type= qp_type;\r
- \r
- rc= init_qp(hca,qp_init_attr_p,new_qp);\r
- if (rc != HH_OK) {\r
- goto failed_init_qp;\r
- }\r
-\r
- rc= qpm_alloc_wqe_buf(qpm, in_ddr_mem,hca_ul_res.max_qp_ous_wr,hca_ul_res.max_num_sg_ent,\r
- new_qp,qp_ul_resources_p);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT(": Failed allocating WQEs buffers.\n"));\r
- goto failed_alloc_wqe;\r
- }\r
-\r
- rc= qpm_alloc_aux_data_buf(new_qp);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT(": Failed allocating auxilary buffers.\n"));\r
- goto failed_alloc_aux;\r
- }\r
- \r
- /* Set output modifiers */\r
- *qp_hndl_p= new_qp;\r
- qp_cap_out_p->max_oust_wr_rq= new_qp->rq_res.max_outs;\r
- qp_cap_out_p->max_oust_wr_sq= new_qp->sq_res.max_outs;\r
- qp_cap_out_p->max_sg_size_rq= new_qp->rq_res.max_sg_sz;\r
- qp_cap_out_p->max_sg_size_sq= new_qp->sq_res.max_sg_sz;\r
- qp_cap_out_p->max_inline_data_sq= new_qp->sq_res.max_inline_data; \r
- rc= THH_uar_get_index(new_qp->uar,&(qp_ul_resources_p->uar_index)); \r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT(": Failed getting UAR index.\n"));\r
- goto failed_uar_index;\r
- }\r
- /* wqe_buf data in qp_ul_resources_p is already set in qpm_alloc_wqe_buf */\r
- \r
- /* update QPs counter */\r
- MOSAL_spinlock_dpc_lock(&(qpm->hash_lock));\r
- qpm->qp_cnt++;\r
- MOSAL_spinlock_unlock(&(qpm->hash_lock));\r
-\r
- return HH_OK;\r
-\r
- /* Error cleanup */\r
- failed_uar_index:\r
- if (new_qp->sq_res.wqe_id != NULL) {\r
- THH_SMART_FREE(new_qp->sq_res.wqe_id, new_qp->sq_res.max_outs * sizeof(VAPI_wr_id_t)); \r
- }\r
- if (new_qp->rq_res.wqe_id != NULL) {\r
- THH_SMART_FREE(new_qp->rq_res.wqe_id, new_qp->rq_res.max_outs * sizeof(VAPI_wr_id_t)); \r
- }\r
- failed_alloc_aux:\r
- if (new_qp->wqe_buf_orig != NULL) {/* WQEs buffer were allocated in process mem. or by the THH_qpm ? */ \r
- /* If allocated here than should be freed */\r
- if (new_qp->dpool_p == NULL) { /* direct allocation */\r
- if (new_qp->used_virt_alloc) \r
- MOSAL_pci_virt_free_consistent(new_qp->wqe_buf_orig, new_qp->wqe_buf_orig_size);\r
- else\r
- MOSAL_pci_phys_free_consistent(new_qp->wqe_buf_orig, new_qp->wqe_buf_orig_size); \r
- } else { /* used dpool */\r
- dpool_free(qpm, new_qp->dpool_p, new_qp->wqe_buf_orig);\r
- }\r
- }\r
- failed_alloc_wqe:\r
- failed_init_qp:\r
- FREE(new_qp);\r
- return rc;\r
-}\r
-\r
-\r
-/* Allocate THHUL_qp_t object and initialize it */\r
-static HH_ret_t init_qp(\r
- HHUL_hca_hndl_t hca, \r
- HHUL_qp_init_attr_t *qp_init_attr_p, \r
- THHUL_qp_t new_qp\r
-)\r
-{\r
- HH_ret_t rc;\r
- THHUL_pdm_t pdm;\r
- MT_bool ok_sqp; /* irrelevant here */\r
-\r
- rc= THHUL_hob_get_uar(hca,&(new_qp->uar));\r
- if (rc != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("init_qp: Failed getting THHUL_hob's UAR (err=%d).\n"),rc);\r
- return rc;\r
- }\r
- rc= THHUL_hob_get_pdm(hca,&pdm);\r
- if (rc != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("init_qp: Failed THHUL_hob_get_pdm (err=%d).\n"),rc);\r
- return rc;\r
- }\r
- rc= THHUL_hob_is_priv_ud_av(hca,&(new_qp->is_priv_ud_av));\r
- if (rc != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("init_qp: Failed THHUL_hob_is_priv_ud_av (err=%d).\n"),rc);\r
- return rc;\r
- }\r
- rc= THHUL_pdm_get_ud_av_memkey_sqp_ok(pdm,qp_init_attr_p->pd,&ok_sqp,&(new_qp->ud_av_memkey),&(new_qp->av_ddr_base),&(new_qp->av_host_base));\r
- if (rc != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("init_qp: Failed THHUL_pdm_get_ud_av_memkey (err=%d).\n"),rc);\r
- return rc;\r
- }\r
- \r
- new_qp->dpool_p= NULL;\r
- new_qp->qpn= 0xFFFFFFFF; /* Init to invalid QP num. until create_qp_done is invoked */\r
- new_qp->pd= qp_init_attr_p->pd;\r
- switch (new_qp->sqp_type) { /* Set transport type appropriate to QP type */\r
- case VAPI_REGULAR_QP:\r
- new_qp->ts_type= qp_init_attr_p->ts_type;\r
- break;\r
- \r
- case VAPI_SMI_QP:\r
- case VAPI_GSI_QP:\r
- new_qp->ts_type= VAPI_TS_UD;\r
- break;\r
- \r
- case VAPI_RAW_IPV6_QP:\r
- case VAPI_RAW_ETY_QP:\r
- new_qp->ts_type= VAPI_TS_RAW;\r
- break;\r
-\r
- default:\r
- MTL_ERROR1(MT_FLFMT("Invalid QP type (sqp_type=%d)"),new_qp->sqp_type);\r
- return HH_EINVAL;\r
- }\r
- \r
- new_qp->srq= qp_init_attr_p->srq;\r
- /* Init RQ */\r
- new_qp->rq_res.qp_state= VAPI_RESET;\r
- if (qp_init_attr_p->srq == HHUL_INVAL_SRQ_HNDL) {\r
- new_qp->rq_res.max_outs= qp_init_attr_p->qp_cap.max_oust_wr_rq;\r
- new_qp->rq_res.max_sg_sz= qp_init_attr_p->qp_cap.max_sg_size_rq;\r
- } else { /* QP associated with SRQ */\r
- MTL_DEBUG4(MT_FLFMT("%s: Ignoring RQ attributes for a SRQ associated QP"), __func__);\r
- new_qp->rq_res.max_outs= 0;\r
- new_qp->rq_res.max_sg_sz= 0;\r
- }\r
- new_qp->rq_res.next2free_index= new_qp->rq_res.next2post_index= 0;\r
- new_qp->rq_res.cur_outs= 0;\r
- new_qp->rq_res.last_posted_p= NULL;\r
- new_qp->rq_cq= qp_init_attr_p->rq_cq;\r
- MOSAL_spinlock_init(&(new_qp->rq_res.q_lock));\r
-\r
- /* Init SQ */\r
- new_qp->sq_res.qp_state= VAPI_RESET;\r
- new_qp->sq_res.max_outs= qp_init_attr_p->qp_cap.max_oust_wr_sq;\r
- new_qp->sq_res.max_sg_sz= qp_init_attr_p->qp_cap.max_sg_size_sq;\r
- new_qp->sq_res.max_inline_data= qp_init_attr_p->qp_cap.max_inline_data_sq;\r
- new_qp->sq_res.cur_outs= 0;\r
- new_qp->sq_res.next2free_index= new_qp->sq_res.next2post_index= 0;\r
- new_qp->sq_res.last_posted_p= NULL;\r
- new_qp->sq_cq= qp_init_attr_p->sq_cq;\r
- MOSAL_spinlock_init(&(new_qp->sq_res.q_lock));\r
-\r
- return HH_OK;\r
-}\r
-\r
-inline static MT_bool qpm_within_4GB(void* base, MT_size_t bsize)\r
-{\r
- u_int64_t start_addr;\r
- u_int64_t end_addr;\r
-\r
- if (sizeof(MT_virt_addr_t) <=4) return TRUE; /* For 32 bits machines no check is required */\r
- start_addr= (u_int64_t)(MT_virt_addr_t)base;\r
- end_addr= start_addr+bsize-1;\r
- return ((start_addr >> 32) == (end_addr >> 32)); /* TRUE if 32 MS-bits equal */\r
-\r
-}\r
-\r
-inline static void* qpm_malloc_within_4GB(MT_size_t bsize, MT_bool *used_virt_alloc_p)\r
-{\r
- void* buf[MAX_ALLOC_RETRY]={NULL};\r
- MT_bool used_virt_alloc[MAX_ALLOC_RETRY];\r
- int i,j;\r
-\r
- for (i= 0; i < MAX_ALLOC_RETRY; i++) { /* Retry to avoid crossing 4GB */\r
-#if defined(MT_KERNEL) && defined(__LINUX__)\r
- /* Consider using low memory (kmalloc) up to WQ_KMALLOC_LIMIT or for small vmalloc area */\r
- if (bsize <= WQ_KMALLOC_LIMIT) {\r
- buf[i]= (void*)MOSAL_pci_phys_alloc_consistent(bsize,0); /* try to use kmalloc */\r
- used_virt_alloc[i]= FALSE;\r
- } \r
- if (buf[i] == NULL) /* failed kmalloc, or did not even try it */\r
-#endif\r
- {\r
- buf[i]=\r
-#ifdef WIN32\r
- /* Use pageable memory, since it gets registered. */\r
- cl_pzalloc( bsize );\r
-#else\r
- (void*)MOSAL_pci_virt_alloc_consistent(bsize, 0); //TODO: must pass proper alignment here. For now thhul_qpm is unused in Darwin.\r
-#endif\r
- used_virt_alloc[i]= TRUE;\r
- }\r
- if (buf[i] == NULL) {\r
- MTL_ERROR3("qpm_malloc_within_4GB: Failed allocating buffer of "SIZE_T_FMT" bytes (iteration %d).\n",\r
- bsize,i);\r
- /* Free previously allocated buffers if any*/\r
- for (j= i; j > 0; j--) {\r
- if (used_virt_alloc[j-1]) {\r
- MOSAL_pci_virt_free_consistent(buf[j-1], bsize);\r
- } else {\r
- MOSAL_pci_phys_free_consistent(buf[j-1], bsize);\r
- }\r
- }\r
- return NULL;\r
- }\r
- if (qpm_within_4GB(buf[i],bsize)) break;\r
- }\r
- if (i == MAX_ALLOC_RETRY) { /* Failed */\r
- MTL_ERROR2("qpm_malloc_within_4GB: Failed allocating buffer of "SIZE_T_FMT" bytes within 4GB boundry "\r
- "(%d retries).\n", bsize, MAX_ALLOC_RETRY); \r
- /* Free all allocated buffers */\r
- for (i= 0; i < MAX_ALLOC_RETRY; i++) {\r
- if (used_virt_alloc[i]) {\r
- MOSAL_pci_virt_free_consistent(buf[i], bsize);\r
- } else {\r
- MOSAL_pci_phys_free_consistent(buf[i], bsize);\r
- }\r
- }\r
- return NULL;\r
- }\r
- /* Free disqualified buffers if any */\r
- for (j= i; j > 0; j--) {\r
- if (used_virt_alloc[j-1]) {\r
- MOSAL_pci_virt_free_consistent(buf[j-1], bsize);\r
- } else {\r
- MOSAL_pci_phys_free_consistent(buf[j-1], bsize);\r
- }\r
- }\r
-\r
- *used_virt_alloc_p= used_virt_alloc[i];\r
- return buf[i]; /* This is the one buffer which does not cross 4GB boundry */\r
-}\r
-\r
-/* Allocate the WQEs buffer for sendQ and recvQ */\r
-/* This function should be invoked after queue properties are set by alloc_init_qp */\r
-static HH_ret_t qpm_alloc_wqe_buf(\r
- /*IN*/ THHUL_qpm_t qpm,\r
- /*IN*/ MT_bool in_ddr_mem, /* Allocation of WQEs buffer is requested in attached DDR mem. */\r
- /*IN*/ u_int32_t max_outs_wqes, /* HCA cap. */\r
- /*IN*/ u_int32_t max_sg_ent, /* HCA cap. of max.s/g entries */\r
- /*IN/OUT*/ THHUL_qp_t new_qp,\r
- /*OUT*/ THH_qp_ul_resources_t *qp_ul_resources_p\r
-)\r
-{\r
- u_int32_t wqe_sz_rq,buf_sz_rq,rq_wqe_base_sz;\r
- u_int32_t wqe_sz_sq,buf_sz_sq,sq_wqe_base_sz;\r
- u_int32_t sq_sg_seg_sz,sq_inline_seg_sz;\r
- u_int8_t log2_wqe_sz_rq,log2_wqe_sz_sq;\r
- HH_ret_t ret;\r
-\r
- /* Check requested capabilities */\r
- if ((new_qp->rq_res.max_outs == 0) && (new_qp->sq_res.max_outs == 0)) {\r
- if (new_qp->srq == HHUL_INVAL_SRQ_HNDL) {\r
- MTL_ERROR3(MT_FLFMT("Got a request for a QP with 0 WQEs on both SQ and RQ - rejecting !"));\r
- return HH_EINVAL_PARAM;\r
- } else { /* QP has no WQEs buffer - uses SRQ only */\r
- new_qp->rq_res.wqe_draft = NULL;\r
- new_qp->sq_res.wqe_draft = NULL;\r
- new_qp->wqe_buf_orig= NULL;\r
- new_qp->wqe_buf_orig_size= 0;\r
- qp_ul_resources_p->wqes_buf= 0; \r
- qp_ul_resources_p->wqes_buf_sz= 0; /* No WQEs buffer to register */\r
- return HH_OK;\r
- }\r
- }\r
- if ((new_qp->rq_res.max_outs > max_outs_wqes) || (new_qp->sq_res.max_outs > max_outs_wqes)) {\r
- MTL_ERROR2(MT_FLFMT(\r
- "QP cap. requested (rq_res.max_outs=%u, sq_res.max_outs=%u) exceeds HCA cap. (max_qp_ous_wr=%u)"),\r
- new_qp->rq_res.max_outs, new_qp->sq_res.max_outs, max_outs_wqes);\r
- return HH_E2BIG_WR_NUM;\r
- }\r
- /* Avoid a work queue of a single WQE (linking a WQE to itself may be problematic) */\r
- if (new_qp->rq_res.max_outs == 1) new_qp->rq_res.max_outs= 2;\r
- if (new_qp->sq_res.max_outs == 1) new_qp->sq_res.max_outs= 2;\r
- \r
- if ((new_qp->rq_res.max_sg_sz > max_sg_ent) || (new_qp->sq_res.max_sg_sz > max_sg_ent)) {\r
- MTL_ERROR2(MT_FLFMT(\r
- "QP cap. requested (rq_res.max_sg_sz=%u, sq_res.max_sg_sz=%u) exceeds HCA cap. (max_sg_ent=%u)"),\r
- new_qp->rq_res.max_sg_sz, new_qp->sq_res.max_sg_sz, max_sg_ent);\r
- return HH_E2BIG_SG_NUM;\r
- }\r
-\r
- /* Compute RQ WQE requirements */\r
- if (new_qp->rq_res.max_outs == 0) {\r
- log2_wqe_sz_rq= 0;\r
- wqe_sz_rq= 0;\r
- buf_sz_rq= 0;\r
- new_qp->rq_res.wqe_draft = NULL;\r
- } else {\r
- rq_wqe_base_sz= WQE_SEG_SZ_NEXT + WQE_SEG_SZ_CTRL; \r
- wqe_sz_rq= rq_wqe_base_sz + (new_qp->rq_res.max_sg_sz * WQE_SEG_SZ_SG_ENTRY);\r
- if (wqe_sz_rq > MAX_WQE_SZ) {\r
- MTL_ERROR2(\r
- MT_FLFMT("required RQ capabilities (max_sg_sz=%d) require a too large WQE (%d bytes)"),\r
- new_qp->rq_res.max_sg_sz, wqe_sz_rq);\r
- return HH_E2BIG_SG_NUM;\r
- }\r
- log2_wqe_sz_rq= ceil_log2(wqe_sz_rq); /* Align to next power of 2 */\r
- /* A WQE must be aligned to 64B (WQE_ALIGN_SHIFT) so we take at least this size */\r
- if (log2_wqe_sz_rq < WQE_ALIGN_SHIFT) log2_wqe_sz_rq= WQE_ALIGN_SHIFT;\r
- wqe_sz_rq= (1<<log2_wqe_sz_rq);\r
- MTL_DEBUG5("qpm_alloc_wqe_buf: Allocating RQ WQE of size %d.\n",wqe_sz_rq);\r
- /* Compute real number of s/g entries based on rounded up WQE size */\r
- new_qp->rq_res.max_sg_sz= (wqe_sz_rq - rq_wqe_base_sz) / WQE_SEG_SZ_SG_ENTRY; \r
- /* Make sure we do not exceed reported HCA cap. */\r
- new_qp->rq_res.max_sg_sz= (new_qp->rq_res.max_sg_sz > max_sg_ent) ? \r
- max_sg_ent : new_qp->rq_res.max_sg_sz;\r
- new_qp->rq_res.wqe_tmp = NULL;\r
- new_qp->rq_res.wqe_draft= (u_int32_t *)MALLOC(wqe_sz_rq);\r
- if (new_qp->rq_res.wqe_draft == NULL) {\r
- MTL_ERROR2(MT_FLFMT("Failed allocating %d bytes for RQ's wqe draft"),wqe_sz_rq);\r
- return HH_EAGAIN;\r
- }\r
- }\r
- \r
- if (new_qp->sq_res.max_outs == 0) {\r
- sq_wqe_base_sz= 0;\r
- log2_wqe_sz_sq= 0;\r
- wqe_sz_sq= 0;\r
- buf_sz_sq= 0;\r
- new_qp->sq_res.wqe_draft = NULL;\r
- } else {\r
- /* Compute SQ WQE requirements */\r
- wqe_sz_sq= /* "next" and "ctrl" are included in the WQE of any transport */\r
- WQE_SEG_SZ_NEXT + WQE_SEG_SZ_CTRL;\r
-\r
- switch (new_qp->sqp_type) {\r
- /* For special QPs additional reservation required for the headers (MLX+inline) */\r
- case VAPI_SMI_QP:\r
- case VAPI_GSI_QP:\r
- /* SMI/GSI ==> UD headers */\r
- wqe_sz_sq+= WQE_INLINE_SZ_UD_HDR;\r
- wqe_sz_sq+= WQE_INLINE_ICRC;\r
- break;\r
- case VAPI_RAW_ETY_QP:\r
- /* Raw-Ethertype ==> LRH+RWH */\r
- wqe_sz_sq+= WQE_INLINE_SZ_RAW_HDR;\r
- break;\r
- case VAPI_RAW_IPV6_QP:\r
- /* IPv6 routing headers are given by the consumer in the gather list (?) */\r
- break;\r
- default: /* Normal QP - add relevant transport WQE segments */\r
- if (new_qp->ts_type == VAPI_TS_UD) {\r
- wqe_sz_sq+= WQE_SEG_SZ_UD;\r
- } else if (new_qp->ts_type == VAPI_TS_RD) {\r
- wqe_sz_sq+= WQE_SEG_SZ_RD;\r
- }\r
- if ((new_qp->ts_type == VAPI_TS_RC) ||\r
- (new_qp->ts_type == VAPI_TS_RD) ||\r
- (new_qp->ts_type == VAPI_TS_UC) ) {\r
- wqe_sz_sq+= WQE_SEG_SZ_BIND_RADDR_ATOMIC;\r
- }\r
- }\r
-\r
- if (wqe_sz_sq > MAX_WQE_SZ) {\r
- MTL_ERROR2(MT_FLFMT("required SQ capabilities(max_sg_sz=%d , max_inline_data=%d) "\r
- "require a too large WQE (%d bytes)"),\r
- new_qp->sq_res.max_sg_sz, new_qp->sq_res.max_inline_data, wqe_sz_sq);\r
- ret= HH_E2BIG_SG_NUM;\r
- goto failed_sq2big;\r
- }\r
-\r
- sq_wqe_base_sz= wqe_sz_sq; /* WQE base without data segments */\r
- /* Compute data segments size for sendQ */\r
- sq_sg_seg_sz= new_qp->sq_res.max_sg_sz * WQE_SEG_SZ_SG_ENTRY; /* data pointers segments */\r
- #ifndef QPM_SUPPORT_INLINE_DATA_SET\r
- /* max_inline_data from create-qp cap. is not supported by default due to backward compat. */\r
- new_qp->sq_res.max_inline_data= 64; /* Current default minimum */\r
- #endif\r
- sq_inline_seg_sz= /* Compute inline data segment size */ \r
- MT_UP_ALIGNX_U32(WQE_INLINE_SZ_BCOUNT + new_qp->sq_res.max_inline_data,WQE_SZ_MULTIPLE_SHIFT);\r
- wqe_sz_sq+= ((sq_inline_seg_sz > sq_sg_seg_sz) ? sq_inline_seg_sz : sq_sg_seg_sz); \r
-\r
- log2_wqe_sz_sq= ceil_log2(wqe_sz_sq); /* Align to next power of 2 */\r
- /* A WQE must be aligned to 64B (WQE_ALIGN_SHIFT) so we take at least this size */\r
- if (log2_wqe_sz_sq < WQE_ALIGN_SHIFT) log2_wqe_sz_sq= WQE_ALIGN_SHIFT;\r
- wqe_sz_sq= (1<<log2_wqe_sz_sq);\r
- MTL_DEBUG5("qpm_alloc_wqe_buf: Allocating SQ WQE of size %d.\n",wqe_sz_sq);\r
- /* Compute real number of s/g entries based on rounded up WQE size */\r
- new_qp->sq_res.max_sg_sz= (wqe_sz_sq - sq_wqe_base_sz) / WQE_SEG_SZ_SG_ENTRY; \r
- /* Make sure we do not exceed reported HCA cap. */\r
- new_qp->sq_res.max_sg_sz= (new_qp->sq_res.max_sg_sz > max_sg_ent) ? \r
- max_sg_ent : new_qp->sq_res.max_sg_sz;\r
- new_qp->sq_res.wqe_tmp = NULL;\r
- if (new_qp->sqp_type == VAPI_SMI_QP || new_qp->sqp_type == VAPI_GSI_QP) {\r
- new_qp->sq_res.wqe_tmp = MALLOC(sizeof(*new_qp->sq_res.wqe_tmp));\r
- if (new_qp->sq_res.wqe_tmp == NULL) {\r
- MTL_ERROR2(MT_FLFMT("Failed allocating "SIZE_T_FMT" bytes for RQ's wqe tmp"),sizeof(*new_qp->sq_res.wqe_tmp));\r
- ret = HH_EAGAIN;\r
- goto failed_wqe_tmp;\r
- }\r
- }\r
- new_qp->sq_res.wqe_draft= (u_int32_t *)MALLOC(wqe_sz_sq);\r
- if (new_qp->sq_res.wqe_draft == NULL) {\r
- MTL_ERROR2(MT_FLFMT("Failed allocating %d bytes for SQ's wqe draft"),wqe_sz_sq);\r
- ret= HH_EAGAIN;\r
- goto failed_sq_draft;\r
- }\r
- }\r
-\r
-\r
- buf_sz_rq= new_qp->rq_res.max_outs * wqe_sz_rq;\r
- buf_sz_sq= new_qp->sq_res.max_outs * wqe_sz_sq;\r
- \r
- \r
- if ((in_ddr_mem) || /* Allocate WQEs buffer by THH_qpm in the attached DDR memory */\r
- (buf_sz_rq+buf_sz_sq == 0)) {/* Or no WQE allocation (possible if SRQ is used) */\r
- new_qp->wqe_buf_orig= NULL;\r
- } else { /* Allocate WQEs buffer in main memory */\r
-#if defined( WIN32 ) || defined (__KERNEL__)\r
-\r
- new_qp->wqe_buf_orig_size = \r
- buf_sz_rq+((wqe_sz_rq != 0) ? (wqe_sz_rq-1):0)+\r
- buf_sz_sq+((wqe_sz_sq != 0) ? (wqe_sz_sq-1):0);\r
- new_qp->wqe_buf_orig= qpm_malloc_within_4GB(new_qp->wqe_buf_orig_size, &new_qp->used_virt_alloc);\r
- /* Make RQ (first WQEs buffer) start at page boundry) */\r
- new_qp->rq_res.wqe_buf= MT_UP_ALIGNX_VIRT((MT_virt_addr_t)(new_qp->wqe_buf_orig),\r
- log2_wqe_sz_rq);\r
-#else \r
-/* In user space we need to take care of pages sharing on memory locks (fork issues) */\r
- /* Allocate one more for each queue in order to make each aligned to its WQE size */\r
- /* (Assures no WQE crosses a page boundry, since we make WQE size a power of 2) */ \r
- new_qp->wqe_buf_orig_size = buf_sz_rq+buf_sz_sq+((wqe_sz_sq != 0) ? (wqe_sz_sq-1):0);\r
-#ifndef WIN32\r
- if (new_qp->wqe_buf_orig_size > (THHUL_DPOOL_SZ_MAX_KB << THHUL_DPOOL_SZ_UNIT_SHIFT)) {\r
-#endif\r
- /* Large WQEs buffer - allocate directly */\r
- /* Assure the buffer covers whole pages (no sharing of locked memory with other data) */\r
- \r
- new_qp->wqe_buf_orig_size = ROUNDUP( new_qp->wqe_buf_orig_size, MOSAL_SYS_PAGE_SIZE );\r
-\r
- /* Prevent other data reside in the last page of the buffer... */\r
- /* cover last page (last WQE can be at last page begin and its size is 64B min.)*/\r
- \r
- new_qp->wqe_buf_orig= cl_zalloc (new_qp->wqe_buf_orig_size );\r
-\r
- /* Make RQ (first WQEs buffer) start at page boundry) */\r
- new_qp->rq_res.wqe_buf= MT_UP_ALIGNX_VIRT((MT_virt_addr_t)(new_qp->wqe_buf_orig),\r
- MOSAL_SYS_PAGE_SHIFT);\r
-#ifndef WIN32\r
- } else { /* small WQEs buffer - use dpool */\r
- /* Round size up to next KB */\r
- new_qp->wqe_buf_orig_size= \r
- MT_UP_ALIGNX_U32(new_qp->wqe_buf_orig_size, THHUL_DPOOL_GRANULARITY_SHIFT);\r
- new_qp->wqe_buf_orig= dpool_alloc(qpm, (u_int8_t)new_qp->wqe_buf_orig_size >> THHUL_DPOOL_SZ_UNIT_SHIFT,\r
- &new_qp->dpool_p);\r
- new_qp->rq_res.wqe_buf= (MT_virt_addr_t)new_qp->wqe_buf_orig; /* no need to align to WQE size */\r
- /* All dpool buffers are aligned to at least 1KB - see comment in dpool_create() */\r
- }\r
-#endif // WIN32\r
-#endif // __KERNEL__\r
-\r
- if (new_qp->wqe_buf_orig == NULL) {\r
- MTL_ERROR2("qpm_alloc_wqe_buf: Failed allocation of WQEs buffer of "SIZE_T_FMT" bytes within "\r
- "4GB boundries.\n",new_qp->wqe_buf_orig_size);\r
- ret= HH_EAGAIN;\r
- goto failed_wqe_buf;\r
- }\r
- }\r
-\r
- /* Set the per queue resources */\r
- new_qp->rq_res.log2_max_wqe_sz= log2_wqe_sz_rq;\r
- /* SQ is after RQ - aligned to its WQE size */\r
- new_qp->sq_res.wqe_buf= MT_UP_ALIGNX_VIRT((new_qp->rq_res.wqe_buf + buf_sz_rq),log2_wqe_sz_sq); \r
- new_qp->sq_res.log2_max_wqe_sz= log2_wqe_sz_sq;\r
- //MTL_DEBUG5(MT_FLFMT("sq_inline_seg_sz=%d sq_sg_seg_sz=%d"),sq_inline_seg_sz,sq_sg_seg_sz);\r
- if (wqe_sz_sq <= MAX_WQE_SZ) { /* update actual space for inline data */\r
- new_qp->sq_res.max_inline_data= wqe_sz_sq - sq_wqe_base_sz - 4; \r
- } else { /* Due to alignment we have a WQE of 1024B, but actual WQE is only MAX_WQE_SZ (1008B)*/\r
- new_qp->sq_res.max_inline_data= MAX_WQE_SZ - sq_wqe_base_sz - 4; \r
- }\r
- \r
- /* Set the qp_ul_resources_p */\r
- if (in_ddr_mem) {\r
- qp_ul_resources_p->wqes_buf= 0; /* Allocate in attached DDR memory */\r
- } else {\r
- /* Actual buffer starts at beginning of the RQ WQEs buffer (if exists) */\r
- qp_ul_resources_p->wqes_buf= (buf_sz_rq != 0) ? new_qp->rq_res.wqe_buf : new_qp->sq_res.wqe_buf;\r
- }\r
- /* Actual buffer size is the difference from the real buffer start to end of SQ buffer */\r
- /* (even if buffer is allocated in DDR mem. and this computation is done from 0 it is valid) */\r
- qp_ul_resources_p->wqes_buf_sz= (new_qp->sq_res.wqe_buf + buf_sz_sq) - \r
- qp_ul_resources_p->wqes_buf;\r
-\r
- return HH_OK;\r
-\r
- failed_wqe_buf:\r
- if ( new_qp->sq_res.wqe_draft ) FREE(new_qp->sq_res.wqe_draft);\r
- failed_sq2big:\r
- failed_sq_draft:\r
- if (new_qp->sq_res.wqe_tmp)\r
- FREE(new_qp->sq_res.wqe_tmp);\r
- failed_wqe_tmp:\r
- if ( new_qp->rq_res.wqe_draft ) FREE(new_qp->rq_res.wqe_draft);\r
- return ret;\r
-}\r
-\r
-\r
-/* Allocate the auxilary WQEs data \r
- * (a software context of a WQE which does not have to be in the registered WQEs buffer) */\r
-static HH_ret_t qpm_alloc_aux_data_buf(\r
- /*IN/OUT*/ THHUL_qp_t new_qp\r
-)\r
-{\r
- /* RQ auxilary buffer: WQE ID per WQE */ \r
- if (new_qp->rq_res.max_outs > 0) {\r
- new_qp->rq_res.wqe_id= (VAPI_wr_id_t*)\r
- THH_SMART_MALLOC(new_qp->rq_res.max_outs * sizeof(VAPI_wr_id_t)); \r
- if (new_qp->rq_res.wqe_id == NULL) {\r
- MTL_ERROR1("qpm_alloc_aux_data_buf: Failed allocating RQ auxilary buffer.\n");\r
- return HH_EAGAIN;\r
- }\r
- }\r
-\r
- /* SQ auxilary buffer: WQE ID per WQE */ \r
- if (new_qp->sq_res.max_outs > 0) {\r
- new_qp->sq_res.wqe_id= (VAPI_wr_id_t*)\r
- THH_SMART_MALLOC(new_qp->sq_res.max_outs * sizeof(VAPI_wr_id_t)); \r
- if (new_qp->sq_res.wqe_id == NULL) {\r
- MTL_ERROR1("qpm_alloc_aux_data_buf: Failed allocating RQ auxilary buffer.\n");\r
- /* Free any memory chunk allocated by this function */\r
- if (new_qp->rq_res.wqe_id != NULL) {\r
- THH_SMART_FREE(new_qp->rq_res.wqe_id,new_qp->rq_res.max_outs * sizeof(VAPI_wr_id_t)); \r
- }\r
- return HH_EAGAIN;\r
- }\r
- }\r
- \r
- return HH_OK;\r
-}\r
-\r
-\r
-#if QPM_USE_FIXED_QP_ARRAY\r
-/* Insert given QP to the QPM fixed array table.\r
- * If table is filled, then go to hash table */\r
-static HH_ret_t insert_to_array(THHUL_qpm_t qpm, THHUL_qp_t qp)\r
-{\r
- u_int32_t hash_index= get_hash_index(qp->qpn);\r
- int i = 0;\r
- MT_bool found = FALSE;\r
- qp_array_entry_t *qp_array_p = &qpm->array_tbl[hash_index];\r
- \r
- MOSAL_spinlock_dpc_lock(&(qpm->hash_lock));\r
-\r
- while(i < QPM_QP_PER_ARRAY)\r
- {\r
- if((qp_array_p->qp_array[i].qpn == QP_ARRAY_REUSE) || \r
- (qp_array_p->qp_array[i].qpn == QP_ARRAY_UNUSED))\r
- {\r
- \r
- /* if entry is QP_ARRAY_UNUSED, then set next entry as QP_ARRAY_UNUSED.\r
- * The last entry(index:QPM_QP_PER_ARRAY) in ther array is always QPM_QP_PER_ARRAY.\r
- */ \r
- if(qp_array_p->qp_array[i].qpn == QP_ARRAY_UNUSED)\r
- qp_array_p->qp_array[i+1].qpn = QP_ARRAY_UNUSED;\r
- \r
- qp_array_p->qp_array[i].qp = qp; \r
- qp_array_p->qp_array[i].qpn = qp->qpn;\r
- found = TRUE;\r
- break;\r
- } \r
- i++;\r
- } \r
- \r
- MOSAL_spinlock_unlock(&(qpm->hash_lock));\r
-\r
- if(found == FALSE)\r
- {\r
- MTL_DEBUG2("insert_to_array: Failed allocating array entry.\n"); \r
- return HH_EINVAL; \r
- }\r
-\r
- return HH_OK;\r
-}\r
-#endif\r
-\r
-\r
-/* Insert given QP to the QPM's hash table */\r
-/* This function assumes this QP is not in hash table */\r
-static HH_ret_t insert_to_hash(THHUL_qpm_t qpm, THHUL_qp_t qp)\r
-{\r
- u_int32_t hash_index= get_hash_index(qp->qpn);\r
- qp_hash_entry_t* new_entry_p;\r
- \r
-#if QPM_USE_FIXED_QP_ARRAY\r
- /* Insert fixed array first, if no space, then use hash tbl */\r
- if(insert_to_array(qpm,qp) == HH_OK)\r
- return HH_OK;\r
-#endif \r
- \r
- /* Allocate hash table entry for the new QP */\r
- new_entry_p= (qp_hash_entry_t*)MALLOC(sizeof(qp_hash_entry_t));\r
- if (new_entry_p == NULL) {\r
- MTL_ERROR2("insert_to_hash: Failed allocating hash table entry.\n");\r
- return HH_EAGAIN;\r
- }\r
- /* Set entry key (QPN) and value (QP pointer) */\r
- new_entry_p->qpn= qp->qpn;\r
- new_entry_p->qp= qp;\r
-\r
- /* Add to the hash bin */\r
- MOSAL_spinlock_dpc_lock(&(qpm->hash_lock));\r
- if (qpm->hash_tbl[hash_index] == NULL) { /* First entry in the bin */\r
- new_entry_p->next= NULL;\r
- qpm->hash_tbl[hash_index]= new_entry_p;\r
- } else { /* Add as first before existing entries in the bin */\r
- new_entry_p->next= qpm->hash_tbl[hash_index];\r
- qpm->hash_tbl[hash_index]= new_entry_p;\r
- }\r
- MOSAL_spinlock_unlock(&(qpm->hash_lock));\r
- \r
- return HH_OK;\r
-}\r
-\r
-#if QPM_USE_FIXED_QP_ARRAY\r
-/* if qp is in fixed array, then remove from array.\r
- * Removing entry means set qpn = 0 for recycle.\r
- */\r
-static HH_ret_t remove_from_array(THHUL_qpm_t qpm, THHUL_qp_t qp)\r
-{\r
- u_int32_t hash_index= get_hash_index(qp->qpn);\r
- \r
- int i = 0;\r
- MT_bool found = FALSE;\r
- qp_array_entry_t *qp_array_p = &qpm->array_tbl[hash_index];\r
- \r
- MOSAL_spinlock_dpc_lock(&(qpm->hash_lock));\r
-\r
- while(i < QPM_QP_PER_ARRAY) \r
- {\r
- /* if qpn is found, then set as QO_ARRAY_REUSE for recycle*/\r
- if(qp_array_p->qp_array[i].qpn == qp->qpn)\r
- {\r
- qp_array_p->qp_array[i].qpn = QP_ARRAY_REUSE;\r
- qp_array_p->qp_array[i].qp = 0;\r
- found = TRUE;\r
- break;\r
- }\r
- if(qp_array_p->qp_array[i].qpn == QP_ARRAY_UNUSED)\r
- break; \r
- i++;\r
- }\r
-\r
- MOSAL_spinlock_unlock(&(qpm->hash_lock));\r
- if(found == FALSE)\r
- {\r
- MTL_DEBUG2("THHUL_qpm::remove_from_array: qpn=%d not found in the array table.\n",\r
- qp->qpn); \r
- return HH_EINVAL;\r
- }\r
-\r
- return HH_OK;\r
-}\r
-#endif\r
-\r
-/* Remove given QP from the QPM's hash table */\r
-static HH_ret_t remove_from_hash(THHUL_qpm_t qpm, THHUL_qp_t qp)\r
-{\r
- u_int32_t hash_index= get_hash_index(qp->qpn);\r
- qp_hash_entry_t *entry2remove_p;\r
- qp_hash_entry_t *prev_p= NULL;\r
- \r
-#if QPM_USE_FIXED_QP_ARRAY\r
- /* Remove from fixed array tbl first, if found */\r
- if(remove_from_array(qpm,qp) == HH_OK)\r
- return HH_OK;\r
-#endif\r
-\r
- MOSAL_spinlock_dpc_lock(&(qpm->hash_lock));\r
-\r
- /* Scan hash bin to find given QP's entry */\r
- for (entry2remove_p= qpm->hash_tbl[hash_index]; entry2remove_p != NULL;\r
- entry2remove_p= entry2remove_p->next) {\r
- if (entry2remove_p->qp == qp) break;\r
- prev_p= entry2remove_p;\r
- }\r
- if (entry2remove_p == NULL) {\r
- MTL_ERROR4("THHUL_qpm::remove_from_hash: qpn=%d not found in the hash table.\n",\r
- qp->qpn);\r
- MOSAL_spinlock_unlock(&(qpm->hash_lock));\r
- return HH_EINVAL;\r
- }\r
- /* Remove entry */\r
- /* prev==NULL ==> next should be put directly in hash array */\r
- if (prev_p == NULL) {\r
- qpm->hash_tbl[hash_index]= entry2remove_p->next;\r
- } else { /* else, attach next to prev */\r
- prev_p->next= entry2remove_p->next;\r
- }\r
-\r
- MOSAL_spinlock_unlock(&(qpm->hash_lock));\r
-\r
- FREE(entry2remove_p); \r
- return HH_OK;\r
-}\r
-\r
-\r
-#ifndef __KERNEL__\r
-/********************************\r
- * Descriptors pool functions - not used in kernel space\r
- ********************************/\r
-\r
-#ifdef THHUL_QPM_DEBUG_DPOOL\r
-\r
-static void dpool_dump_list(THHUL_qpm_t qpm, MT_size_t size_index, \r
- const char *context_text, THHUL_qpm_dpool_t *dpool_context)\r
-{\r
- THHUL_qpm_dpool_t *cur_dpool_p;\r
- unsigned long cntr= 0;\r
- \r
- MTL_ERROR1(MT_FLFMT("[%s - dpool_p=%p] Found inconsistancy in dpool list for buffers of %u KB:"),\r
- context_text, dpool_context, size_index + THHUL_DPOOL_SZ_MIN_KB);\r
- cur_dpool_p= qpm->dpool_p[size_index];\r
- while ((cur_dpool_p != NULL) && (cur_dpool_p->next != qpm->dpool_p[size_index]) &&\r
- (cntr < qpm->dpool_cnt)) {\r
- MTL_ERROR1("(%p <- %p -> %p) ", cur_dpool_p->prev, cur_dpool_p, cur_dpool_p->next);\r
- cntr++;\r
- cur_dpool_p= cur_dpool_p->next;\r
- }\r
- MTL_ERROR1("(End of list)\n");\r
- getchar();\r
-}\r
-\r
-static MT_bool dpool_check_consistancy(THHUL_qpm_t qpm, \r
- const char *context_text, THHUL_qpm_dpool_t *dpool_context)\r
-{\r
- THHUL_qpm_dpool_t *cur_dpool_p;\r
- MT_size_t size_index;\r
- unsigned long cntr= 0;\r
-\r
- for (size_index= 0; \r
- size_index < (THHUL_DPOOL_SZ_MAX_KB - THHUL_DPOOL_SZ_MIN_KB + 1);\r
- size_index++) {\r
- cur_dpool_p= qpm->dpool_p[size_index];\r
- while ((cur_dpool_p != NULL) && (cur_dpool_p->next != qpm->dpool_p[size_index])) {\r
- if ((cur_dpool_p->next == NULL) || \r
- (cur_dpool_p->prev == NULL) ||\r
- (cur_dpool_p->next->prev != cur_dpool_p) ||\r
- (cur_dpool_p->prev->next != cur_dpool_p)) {\r
- dpool_dump_list(qpm, size_index, context_text, dpool_context);\r
- return FALSE;\r
- }\r
- cntr++;\r
- if (cntr > qpm->dpool_cnt) {\r
- MTL_ERROR1(MT_FLFMT("Reading more dpool objects in list than total (%lu)"), \r
- qpm->dpool_cnt);\r
- dpool_dump_list(qpm, size_index, context_text, dpool_context);\r
- return FALSE;\r
- }\r
- cur_dpool_p= cur_dpool_p->next;\r
- }\r
- }\r
- return TRUE;\r
-}\r
-\r
-#endif /*DEBUG_DPOOL*/\r
-\r
-\r
-static THHUL_qpm_dpool_t * dpool_create(THHUL_qpm_t qpm, u_int8_t buf_size_kb)\r
-{\r
- THHUL_qpm_dpool_t *new_dpool_p;\r
- MT_virt_addr_t orig_buf_limit;\r
- MT_virt_addr_t cur_buf;\r
- const MT_size_t size_index= buf_size_kb - THHUL_DPOOL_SZ_MIN_KB;\r
- const MT_size_t buf_size= (buf_size_kb << THHUL_DPOOL_SZ_UNIT_SHIFT);\r
-\r
- new_dpool_p= TMALLOC(THHUL_qpm_dpool_t);\r
- if (new_dpool_p == NULL) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed allocating THHUL_qpm_dpool_t"), __func__);\r
- return NULL;\r
- }\r
- \r
- /* Allocate descriptors pool memory - aligned on page start */\r
- new_dpool_p->orig_size= (THHUL_DPOOL_SZ_BASE_BUF_KB << THHUL_DPOOL_SZ_UNIT_SHIFT) + \r
- (MOSAL_SYS_PAGE_SIZE - 1);\r
- new_dpool_p->orig_buf= qpm_malloc_within_4GB(new_dpool_p->orig_size,\r
- &new_dpool_p->used_virt_alloc) ;\r
- if (new_dpool_p->orig_buf == NULL) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed allocating descriptors pool memory of "SIZE_T_FMT" B"),\r
- __func__, new_dpool_p->orig_size);\r
- goto failed_orig_buf;\r
- }\r
- orig_buf_limit= (MT_virt_addr_t) new_dpool_p->orig_buf + new_dpool_p->orig_size;\r
-\r
- new_dpool_p->free_buf_list= NULL;\r
- /* First buffer starts at page boundry and all buffers are of 1KB size multiples */\r
- /* So all buffers of the dpool are aligned to 1KB, i.e., aligned to any size of our */\r
- /* WQEs which are all (stride) of power of 2 */\r
- for (cur_buf= MT_UP_ALIGNX_VIRT((MT_virt_addr_t)new_dpool_p->orig_buf,MOSAL_SYS_PAGE_SHIFT);\r
- (cur_buf+buf_size) < orig_buf_limit ; \r
- cur_buf+= buf_size ) {\r
- *(void**)cur_buf= new_dpool_p->free_buf_list; /* link before first */\r
- new_dpool_p->free_buf_list= (void*)cur_buf;\r
- }\r
-\r
- new_dpool_p->buf_size_kb= buf_size_kb;\r
- new_dpool_p->ref_cnt= 0;\r
-\r
- if (qpm->dpool_p[size_index] == NULL) { /* first */\r
- new_dpool_p->next= new_dpool_p->prev= new_dpool_p;\r
- } else {\r
- new_dpool_p->next= qpm->dpool_p[size_index]; /* link to first */\r
- new_dpool_p->prev= new_dpool_p->next->prev; /* reverse-link to last */\r
- new_dpool_p->prev->next= new_dpool_p->next->prev= new_dpool_p;\r
- }\r
- qpm->dpool_p[size_index]= new_dpool_p; /* make first */\r
- \r
-#ifdef THHUL_QPM_DEBUG_DPOOL\r
- qpm->dpool_cnt++; \r
- MTL_ERROR1("%s: dpool_cnt=%lu (%p <- %p -> %p) \n", __func__,\r
- qpm->dpool_cnt, new_dpool_p->prev, new_dpool_p, new_dpool_p->next);\r
- dpool_check_consistancy(qpm, "After inserting new dpool", new_dpool_p);\r
-#endif\r
- return new_dpool_p;\r
-\r
- failed_orig_buf:\r
- FREE(new_dpool_p);\r
- return NULL;\r
-}\r
-\r
-static void dpool_destroy(THHUL_qpm_t qpm, THHUL_qpm_dpool_t *dpool_p)\r
-{\r
- const MT_size_t size_index= dpool_p->buf_size_kb - THHUL_DPOOL_SZ_MIN_KB;\r
- \r
- /* Assumes ref_cnt==0 */\r
- /* bypass this item */\r
- dpool_p->prev->next= dpool_p->next;\r
- dpool_p->next->prev= dpool_p->prev;\r
- if (qpm->dpool_p[size_index] == dpool_p) { /* if it was the first */\r
- if (dpool_p->next == dpool_p) { /* and only... */\r
- qpm->dpool_p[size_index]= NULL;\r
- } else { /* else, make next be first */\r
- qpm->dpool_p[size_index]= dpool_p->next;\r
- }\r
- }\r
- \r
-#ifdef THHUL_QPM_DEBUG_DPOOL\r
- qpm->dpool_cnt--; \r
- MTL_ERROR1(MT_FLFMT("%s: dpool_cnt=%lu (%p <- %p -> %p) "), __func__,\r
- qpm->dpool_cnt, dpool_p->prev, dpool_p, dpool_p->next);\r
- dpool_check_consistancy(qpm, "After removing a dpool", dpool_p);\r
-#endif\r
-\r
- if (dpool_p->used_virt_alloc) \r
- MOSAL_pci_virt_free_consistent(dpool_p->orig_buf, dpool_p->orig_size);\r
- else\r
- MOSAL_pci_phys_free_consistent(dpool_p->orig_buf, dpool_p->orig_size); \r
-\r
- FREE(dpool_p);\r
-}\r
-\r
-static void* dpool_alloc(THHUL_qpm_t qpm, u_int8_t buf_size_kb, THHUL_qpm_dpool_t **dpool_pp)\r
-{\r
- THHUL_qpm_dpool_t *dpool_p;\r
- void* alloc_buf;\r
- const MT_size_t size_index= buf_size_kb - THHUL_DPOOL_SZ_MIN_KB;\r
-\r
- if ((buf_size_kb < THHUL_DPOOL_SZ_MIN_KB) || (buf_size_kb > THHUL_DPOOL_SZ_MAX_KB)) {\r
- MTL_ERROR2(MT_FLFMT("%s: Given buf_size_kb=0x%u "\r
- "(THHUL_DPOOL_SZ_MIN_KB=%u , THHUL_DPOOL_SZ_MAX_KB=%u)"), __func__,\r
- buf_size_kb, THHUL_DPOOL_SZ_MIN_KB, THHUL_DPOOL_SZ_MAX_KB);\r
- return NULL;\r
- }\r
-\r
- MOSAL_mutex_acq_ui(&qpm->dpool_lock);\r
- \r
- dpool_p= qpm->dpool_p[size_index];\r
- /* If no dpool for this size or existing dpool is full (empty free list) */\r
- if ((dpool_p == NULL) || (dpool_p->free_buf_list == NULL)) {\r
- dpool_p= dpool_create(qpm, buf_size_kb);\r
- if (dpool_p == NULL) return NULL;\r
- }\r
-\r
- alloc_buf= dpool_p->free_buf_list;\r
- dpool_p->free_buf_list= *(void**)alloc_buf; /* next is embedded in free buffer */\r
- dpool_p->ref_cnt++;\r
-\r
- if ((dpool_p->free_buf_list == NULL) && (dpool_p->prev != dpool_p)) { \r
- /* If emptied and not the only dpool for this size - move to end of dpool list for this size */\r
- qpm->dpool_p[size_index]= dpool_p->next; /* "shift" first */\r
- }\r
-\r
-#ifdef THHUL_QPM_DEBUG_DPOOL\r
- dpool_check_consistancy(qpm, "After moving dpool to end of list", dpool_p);\r
-#endif\r
-\r
- MOSAL_mutex_rel(&qpm->dpool_lock);\r
-\r
- *dpool_pp= dpool_p;\r
- return alloc_buf;\r
-}\r
-\r
-static void dpool_free(THHUL_qpm_t qpm, THHUL_qpm_dpool_t *dpool_p, void* buf)\r
-{\r
- const MT_size_t size_index= dpool_p->buf_size_kb - THHUL_DPOOL_SZ_MIN_KB;\r
- /* no check on this - assumes dpool is trusted (value checked on creation) */\r
- \r
- MOSAL_mutex_acq_ui(&qpm->dpool_lock);\r
- /* put in free list of associated dpool */\r
- *(void**)buf= dpool_p->free_buf_list;\r
- dpool_p->free_buf_list= buf;\r
- dpool_p->ref_cnt--;\r
- if (dpool_p->ref_cnt == 0) {\r
- /* if reached ref_cnt 0, probably not much of this size - compact dpools list */\r
- dpool_destroy(qpm,dpool_p);\r
-\r
- } else if (qpm->dpool_p[size_index] != dpool_p) {\r
- /* if not the first dpool for this size */\r
- /* Move to begining of dpool list for this size - it has what to offer... */\r
- if (dpool_p->next != dpool_p->prev) {\r
- /* more than 2 items - really need to move */\r
- /* first disconnect */\r
- dpool_p->prev->next= dpool_p->next;\r
- dpool_p->next->prev= dpool_p->prev;\r
- /* Now connect between first and last */\r
- dpool_p->next= qpm->dpool_p[size_index]; /* link to first */\r
- dpool_p->prev= dpool_p->next->prev; /* reverse-link to last */\r
- dpool_p->prev->next= dpool_p->next->prev= dpool_p;\r
- }\r
- /* (after moved to new location) make first */\r
- qpm->dpool_p[size_index]= dpool_p; \r
- }\r
- \r
-#ifdef THHUL_QPM_DEBUG_DPOOL\r
- dpool_check_consistancy(qpm, "After moving dpool to start of list", dpool_p);\r
-#endif\r
- \r
- MOSAL_mutex_rel(&qpm->dpool_lock);\r
-}\r
-#endif\r
-#ifdef DUMP_SEND_REQ\r
-static void dump_send_req(THHUL_qp_t qp, HHUL_send_req_t *sr)\r
-{\r
- int i;\r
-\r
- MTL_DEBUG4(MT_FLFMT("QP 0x%X - Send: %d S/G entries"),qp->qpn,sr->sg_lst_len); /* Build WQE */\r
- for (i= 0; i < sr->sg_lst_len; i++) {\r
- MTL_DEBUG4(MT_FLFMT("Entry %d: lkey=0x%X va=0x%X len=%d"),i,\r
- sr->sg_lst_p[i].lkey,(MT_virt_addr_t)sr->sg_lst_p[i].addr,sr->sg_lst_p[i].len);\r
- }\r
-}\r
-#endif\r
-\r
-#if defined(VXWORKS_OS) || defined(LINUX)\r
-//#if 1\r
-#include "thhul_qpm_iba.h"\r
-/* This is second optimized version od post_send_req\r
- * This is to eliminate conversion time of IbAccess, so\r
- * sg_list and remote_addr buld function(WQE_pack_remote_addr_and_sg_list_iba) \r
- * use IbAccess data structure. See thhul_qpm_iba for detail.\r
- *\r
- * This version only supports ReliableConnection and UnrliableDataGRam.\r
- */\r
-\r
-#define SET_SE (MT_bool)work_request->Req.SendRC.Options.s.SolicitedEvent\r
-#define FENCE work_request->Req.SendRC.Options.s.Fence\r
-#define IMM_DATA_FLAG work_request->Req.SendRC.Options.s.ImmediateData\r
-#define IMM_DATA_VALUE work_request->Req.SendRC.ImmediateData\r
-#define REMOTE_QP work_request->Req.SendUD.QPNumber\r
-#define REMOTE_QKEY work_request->Req.SendUD.Qkey\r
-#define IB_OP_CODE work_request->Operation \r
-#define REMOTE_ADDR work_request->Req.SendRC.RemoteDS.Address\r
-#define REMOTE_RKEY work_request->Req.SendRC.RemoteDS.Rkey \r
-#define REQUEST_ID work_request->WorkReqId \r
-#define SG_LST_LEN work_request->DSListDepth\r
-\r
-VAPI_ret_t THHUL_qpm_post_send_req2(\r
- HHUL_hca_hndl_t hca, \r
- HHUL_qp_hndl_t hhul_qp, \r
- VAPI_comp_type_t comp_type,\r
- VAPI_ud_av_hndl_t remote_ah,\r
- void *WorkRequest \r
- )\r
-{\r
- THHUL_qp_t qp= (THHUL_qp_t)hhul_qp;\r
- u_int32_t wqe_sz_dwords;\r
- HH_ret_t rc = HH_OK;\r
- volatile u_int32_t* next_wqe; /* Actual WQE pointer */\r
- u_int32_t *cur_loc_p;\r
- tavor_if_nopcode_t tavorOpCode;\r
- int i;\r
- CHIME_WORDS_PREFIX u_int32_t chimeWords[2]; \r
- THH_uar_t uar;\r
- u_int32_t wqe_sz_dwords_byte;\r
- IB_WORK_REQ *work_request = (IB_WORK_REQ *)WorkRequest;\r
- u_int32_t sg_lst_len = SG_LST_LEN;\r
-\r
- if(MOSAL_EXPECT_FALSE(qp->sq_res.qp_state < VAPI_RTS)) {\r
- MTL_ERROR1(MT_FLFMT("%s failed: qp state %d not valid to send \n"),__func__,qp->sq_res.qp_state);\r
- return HH_EINVAL_QP_STATE;\r
- }\r
- \r
- if (MOSAL_EXPECT_FALSE(qp->sq_res.max_sg_sz < sg_lst_len)) {\r
- MTL_ERROR2(\r
- "THHUL_qpm_post_send_req2: Scatter/Gather list is too large (%d entries > max_sg_sz=%d)\n",\r
- sg_lst_len,qp->sq_res.max_sg_sz);\r
- return HH_EINVAL_SG_NUM;\r
- }\r
-\r
- MOSAL_spinlock_dpc_lock(&(qp->sq_res.q_lock)); /* protect wqe_draft and WQE allocation/link */\r
-\r
- /* Check if any WQEs are free to be consumed */\r
- if (MOSAL_EXPECT_FALSE(qp->sq_res.max_outs == qp->sq_res.cur_outs)) {\r
- MTL_ERROR4("THHUL_qpm_post_send_req2: Send queue is full (%u requests outstanding).\n",\r
- qp->sq_res.cur_outs);\r
- return HH_E2BIG_WR_NUM;\r
- }\r
- /* Allocate next WQE */\r
- next_wqe= (u_int32_t*)(qp->sq_res.wqe_buf + \r
- (qp->sq_res.next2post_index << qp->sq_res.log2_max_wqe_sz) );\r
- \r
- /* build new wqe */\r
- cur_loc_p = WQE_build_send_be_req2(qp,(u_int32_t*)next_wqe,\r
- comp_type,\r
- remote_ah,\r
- REMOTE_QP,\r
- REMOTE_QKEY,\r
- SET_SE,\r
- IMM_DATA_FLAG?IMM_DATA_VALUE:0\r
- );\r
- /* build remote_addr and sg_list field\r
- * This is IbAccess specific and defined thhul_qpm_iba.h.\r
- * This should be maintained every port with new vapi drop\r
- */ \r
- cur_loc_p = WQE_pack_remote_addr_and_sg_list_iba(WorkRequest,\r
- cur_loc_p,sg_lst_len,\r
- IMM_DATA_FLAG,&tavorOpCode);\r
- \r
- \r
- wqe_sz_dwords = (((MT_virt_addr_t)cur_loc_p) - ((MT_virt_addr_t)next_wqe)) >> 2; \r
- \r
- {\r
- \r
- wqe_sz_dwords_byte = wqe_sz_dwords>>2;\r
- \r
- /* Update "next" segment of previous WQE (if any) */\r
- /* this is same as WQE_pack_send_next call */\r
- qp->sq_res.last_posted_p[0] = MOSAL_cpu_to_be32(0\r
- | (u_int32_t)tavorOpCode\r
- | ((u_int32_t)(unsigned long) next_wqe & BIT_MASK_FOR_NEXT_WQE_31SB ));\r
- \r
- qp->sq_res.last_posted_p[1] = MOSAL_cpu_to_be32(0 \r
- | ((wqe_sz_dwords_byte) << NEXT_ST_NDS_BIT_OFFSET ) // specify in 16 byte chunks\r
- | ( FENCE << NEXT_ST_F_BIT_OFFSET )\r
- | (1 << NEXT_ST_DBD_BIT_OFFSET)\r
- );\r
- qp->sq_res.last_posted_p= next_wqe;\r
-\r
- /* Ring doorbell (send or rd-send) */\r
- /* This is same as THH_uar_sendq_dbell_inline */\r
- \r
- uar = qp->uar;\r
-\r
- chimeWords[0] = MOSAL_cpu_to_be32(0\r
- | (u_int32_t)tavorOpCode\r
- | ((FENCE & 0x1)<< SEND_DOORBELL_F_BIT_OFFSET)\r
- | ((MT_virt_addr_t)next_wqe & 0xFFFFFFFF));\r
- chimeWords[1] = MOSAL_cpu_to_be32(0\r
- | (u_int32_t)(wqe_sz_dwords >> 2) // specify in 16 byte chunks\r
- | ((u_int32_t)(qp->qpn) << SEDN_DOORBELL_QPN_BIT_OFFSET)\r
- );\r
-\r
-#ifdef __MOSAL_MMAP_IO_WRITE_QWORD_ATOMIC__\r
- MOSAL_MMAP_IO_WRITE_QWORD(((u_int32_t *)&uar->uar_base[UAR_SEND_DBELL_OFFSET]),*(volatile u_int64_t*)chimeWords);\r
-#else\r
- cur_loc_p = (u_int32_t *)&uar->uar_base[UAR_SEND_DBELL_OFFSET];\r
- MOSAL_spinlock_dpc_lock(&(uar->uar_lock));\r
- MOSAL_MMAP_IO_WRITE_DWORD(&cur_loc_p[0], chimeWords[0]);\r
- MOSAL_MMAP_IO_WRITE_DWORD(&cur_loc_p[1], chimeWords[1]);\r
- MOSAL_spinlock_unlock(&(uar->uar_lock));\r
-#endif\r
-\r
- }\r
-\r
- /* save WorkRequest ID and update index */\r
- qp->sq_res.wqe_id[qp->sq_res.next2post_index]= REQUEST_ID; /* Save WQE ID */\r
- \r
- i = ++qp->sq_res.next2post_index; \r
- if (MOSAL_EXPECT_FALSE(i >= qp->sq_res.max_outs))\r
- qp->sq_res.next2post_index = 0;\r
- \r
- qp->sq_res.cur_outs++;\r
-\r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock)); \r
- return rc;\r
-}\r
- \r
-/* This is second optimized version of THHUL_qpm_post_recv_req to\r
- * eliminate IbAccess conversion time. All parameters needed to build \r
- * WQE is passed from VapiHcaShime layer directly.\r
- */\r
-VAPI_ret_t THHUL_qpm_post_recv_req2( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_qp_hndl_t hhul_qp, \r
- VAPI_comp_type_t comp_type,\r
- u_int32_t sg_lst_len,\r
- VAPI_wr_id_t ReqId,\r
- VAPI_sg_lst_entry_t *sg_lst_p \r
- )\r
-{\r
- THHUL_qp_t qp= (THHUL_qp_t)hhul_qp;\r
- volatile u_int32_t* next_wqe; /* Actual WQE pointer */\r
- u_int32_t wqe_sz_dwords;\r
- CHIME_WORDS_PREFIX u_int32_t chimeWords[2]; \r
- u_int32_t* cur_loc_p;\r
- u_int32_t wqe_sz_dwords_byte;\r
- THH_uar_t uar;\r
- //int i;\r
-\r
- if (MOSAL_EXPECT_FALSE(qp->rq_res.qp_state < VAPI_INIT )) {\r
- MTL_ERROR1(MT_FLFMT("%s failed: qp state %d not valid to recv \n"),__func__,qp->rq_res.qp_state);\r
- return HH_EINVAL_QP_STATE;\r
- }\r
-\r
- if (MOSAL_EXPECT_FALSE(qp->rq_res.max_sg_sz < sg_lst_len)) {\r
- MTL_ERROR2(\r
- "THHUL_qpm_post_recv_req: Scatter/Gather list is too large (%d entries > max_sg_sz=%d)\n",\r
- sg_lst_len,qp->rq_res.max_sg_sz);\r
- return HH_EINVAL_SG_NUM;\r
- }\r
- \r
- MOSAL_spinlock_dpc_lock(&(qp->rq_res.q_lock)); /* protect wqe_draft as well as WQE allocation/link */\r
- \r
- /* Check if any WQEs are free to be consumed */\r
- if (MOSAL_EXPECT_FALSE(qp->rq_res.max_outs == qp->rq_res.cur_outs)) {\r
- MOSAL_spinlock_unlock(&(qp->rq_res.q_lock));\r
- MTL_ERROR4("THHUL_qpm_post_recv_req2: Receive queue is full (%d requests outstanding).\n",\r
- qp->rq_res.cur_outs);\r
- return HH_E2BIG_WR_NUM;\r
- }\r
- /* Allocate next WQE */\r
- next_wqe= (u_int32_t*) (qp->rq_res.wqe_buf + \r
- (qp->rq_res.next2post_index << qp->rq_res.log2_max_wqe_sz) );\r
- \r
- /* Build WQE */\r
- /* WQE_build_recv_be_req2 is same as WQE_build_recv_be but not build\r
- * sg_list.\r
- * Building sg_list is done WQE_pack_sg_list_iba \r
- */ \r
- cur_loc_p = WQE_build_recv_be_req2(qp,(u_int32_t*)next_wqe,comp_type);\r
-\r
- \r
- /* build sg_list */ \r
- /* This is same as calling WQE_build_send_sg_list */ \r
- /* WQE_pack_sg_list_iba build sg_list directly from IbAccess structure.\r
- * See thhul_qpm_iba.h \r
- */ \r
- cur_loc_p = WQE_pack_sg_list_iba(sg_lst_p,cur_loc_p,sg_lst_len);\r
-\r
- wqe_sz_dwords = (((MT_virt_addr_t)cur_loc_p) - ((MT_virt_addr_t)next_wqe)) >> 2;\r
-\r
- qp->rq_res.wqe_id[qp->rq_res.next2post_index]= ReqId; /* Save WQE ID */\r
- ++qp->rq_res.next2post_index;\r
- if(MOSAL_EXPECT_FALSE(qp->rq_res.next2post_index >= qp->rq_res.max_outs))\r
- qp->rq_res.next2post_index = 0;\r
- \r
- qp->rq_res.cur_outs++;\r
- \r
- /* Update "next" segment of previous WQE (if any) */\r
- \r
- wqe_sz_dwords_byte = wqe_sz_dwords>>2;\r
- \r
- qp->rq_res.last_posted_p[NEXT_ST_NDA_31_6_DWORD_OFFSET] = MOSAL_cpu_to_be32(0\r
- | ((u_int32_t)(unsigned long) next_wqe & BIT_MASK_FOR_NEXT_WQE_31SB ));\r
- qp->rq_res.last_posted_p[NEXT_ST_NDS_DWORD_OFFSET] = MOSAL_cpu_to_be32(0 \r
- | (wqe_sz_dwords_byte << NEXT_ST_NDS_BIT_OFFSET ) // specify in 16 byte chunks\r
- | (1 << NEXT_ST_DBD_BIT_OFFSET)\r
- );\r
- \r
-\r
- qp->rq_res.last_posted_p= next_wqe;\r
- \r
- /* Ring doorbell */ \r
- uar = qp->uar;\r
- chimeWords[0] = MOSAL_cpu_to_be32(0\r
- | (u_int32_t)(uintn)next_wqe\r
- | ((wqe_sz_dwords + 3) >> 2) // specify in 16 byte chunks\r
- ); \r
- chimeWords[1] = MOSAL_cpu_to_be32(0\r
- | 1 // credits\r
- | ((u_int32_t)(qp->qpn) << 8)\r
- );\r
- \r
-#ifdef __MOSAL_MMAP_IO_WRITE_QWORD_ATOMIC__\r
- MOSAL_MMAP_IO_WRITE_QWORD(((u_int32_t *)&uar->uar_base[UAR_RECV_DBELL_OFFSET]),*(volatile u_int64_t*)chimeWords);\r
-#else\r
- MOSAL_spinlock_dpc_lock(&(uar->uar_lock));\r
- MOSAL_MMAP_IO_WRITE_QWORD(((u_int32_t *)&uar->uar_base[UAR_RECV_DBELL_OFFSET]),*(volatile u_int64_t*)chimeWords);\r
- MOSAL_spinlock_unlock(&(uar->uar_lock));\r
-#endif\r
-\r
- MOSAL_spinlock_unlock(&(qp->rq_res.q_lock));\r
- \r
- \r
- return HH_OK;\r
-} \r
-\r
-#else /* WIN32 */\r
-/* This is optimized, IB_AL native version of post_send_req\r
- * This is to eliminate conversion time, so\r
- * sg_list and remote_addr buld function(WQE_pack_remote_addr_and_sg_list_ibal) \r
- * use IBAL data structure. See thhul_qpm_ibal.h for detail.\r
- *\r
- * This version only supports ReliableConnection and UnrliableDataGRam.\r
- */\r
-\r
-ib_api_status_t\r
-THHUL_qpm_post_send_wrs(\r
- IN HHUL_hca_hndl_t hca,\r
- IN HHUL_qp_hndl_t hhul_qp,\r
- IN ib_send_wr_t *p_send_wr,\r
- OUT ib_send_wr_t **pp_failed_wr OPTIONAL )\r
-{\r
- THHUL_qp_t qp = (THHUL_qp_t)hhul_qp;\r
- u_int32_t wqe_sz_dwords;\r
- HH_ret_t rc = HH_OK;\r
- u_int32_t* next_wqe; /* Actual WQE pointer */\r
- u_int32_t *cur_loc_p;\r
- tavor_if_nopcode_t opcode;\r
- CHIME_WORDS_PREFIX u_int32_t chimeWords[2]; \r
- THH_uar_t uar;\r
- u_int32_t wqe_sz_dwords_byte;\r
- ib_send_wr_t *p_wr;\r
-\r
- if( MOSAL_EXPECT_FALSE(qp->sq_res.qp_state < VAPI_RTS) )\r
- {\r
- if( pp_failed_wr )\r
- *pp_failed_wr = p_send_wr;\r
- MTL_ERROR1(MT_FLFMT("%s failed: qp state %d not valid to send \n"),__func__,qp->sq_res.qp_state);\r
- return IB_INVALID_QP_STATE;\r
- }\r
-\r
- p_wr = p_send_wr;\r
- MOSAL_spinlock_dpc_lock(&(qp->sq_res.q_lock)); /* protect wqe_draft and WQE allocation/link */\r
- while( p_wr )\r
- {\r
- if( MOSAL_EXPECT_FALSE(qp->sq_res.max_sg_sz < p_wr->num_ds) )\r
- {\r
- MTL_ERROR2(\r
- "THHUL_qpm_post_send_req2: Scatter/Gather list is too large (%d entries > max_sg_sz=%d)\n",\r
- p_wr->num_ds,qp->sq_res.max_sg_sz);\r
- rc = HH_E2BIG_SG_NUM;\r
- break;\r
- }\r
-\r
- /* Check if any WQEs are free to be consumed */\r
- if (MOSAL_EXPECT_FALSE(qp->sq_res.max_outs == qp->sq_res.cur_outs)) {\r
- MTL_ERROR4("THHUL_qpm_post_send_req2: Send queue is full (%u requests outstanding).\n",\r
- qp->sq_res.cur_outs);\r
- rc = HH_E2BIG_WR_NUM;\r
- break;\r
- }\r
-\r
- /* Allocate next WQE */\r
- next_wqe= (u_int32_t*)(qp->sq_res.wqe_buf + \r
- (qp->sq_res.next2post_index << qp->sq_res.log2_max_wqe_sz) );\r
-\r
- if( MOSAL_EXPECT_TRUE( qp->sqp_type == VAPI_REGULAR_QP ) )\r
- {\r
- /* build new wqe */\r
- cur_loc_p = WQE_build_send_be_req3(qp, next_wqe,\r
- p_wr->send_opt & IB_SEND_OPT_SIGNALED? VAPI_SIGNALED : VAPI_UNSIGNALED,\r
- p_wr,\r
- p_wr->send_opt & IB_SEND_OPT_SOLICITED? 1:0,\r
- p_wr->immediate_data\r
- );\r
-\r
- /* build remote_addr and sg_list field\r
- * This is IBAL specific and defined thhul_qpm_ibal.h.\r
- * This should be maintained every port with new vapi drop\r
- */\r
- rc = WQE_pack_rem_addr_and_sgl_ibal( p_wr, &cur_loc_p,\r
- qp->sq_res.max_inline_data, &opcode );\r
- if( rc != HH_OK )\r
- break;\r
-\r
- wqe_sz_dwords = (u_int32_t)((((MT_virt_addr_t)cur_loc_p) - ((MT_virt_addr_t)next_wqe)) >> 2); \r
- }\r
- else\r
- {\r
- THH_hca_ul_resources_t hca_ul_res;\r
- u_int32_t* wqe_draft= qp->sq_res.wqe_draft;\r
- unsigned int i; \r
-\r
- /* Code needs to match behavior of VAPI_SEND support only, that means no imm data. */\r
- if (MOSAL_EXPECT_FALSE(p_wr->wr_type != WR_SEND)) {\r
- rc = HH_EINVAL_WQE;\r
- break;\r
- }\r
- if( MOSAL_EXPECT_FALSE(p_wr->send_opt & IB_SEND_OPT_IMMEDIATE) )\r
- {\r
- rc = HH_EINVAL_WQE;\r
- break;\r
- }\r
- opcode = TAVOR_IF_NOPCODE_SEND;\r
- p_wr->send_opt &= ~IB_SEND_OPT_FENCE;/* required for MLX requests */\r
- if(MOSAL_EXPECT_FALSE(THHUL_hob_get_hca_ul_res(hca,&hca_ul_res) != HH_OK))\r
- {\r
- rc = HH_EINVAL_HCA_HNDL;\r
- break;\r
- }\r
- /*\r
- * Build the WQE in BE format. Note that we must still use the wqe_draft since\r
- * the function still builds part of the WQE in LE and swaps.\r
- */\r
- wqe_sz_dwords= (WQE_build_send_mlx2_be(hca_ul_res.hh_hca_hndl,qp,p_wr,QP1_PKEY_INDEX,wqe_draft) >> 2);\r
- if (MOSAL_EXPECT_FALSE(wqe_sz_dwords == 0)) {\r
- MTL_ERROR1(MT_FLFMT("Failed building MLX headers for special QP.\n"));\r
- rc = HH_EINVAL_WQE;\r
- break;\r
- }\r
-\r
- /* we used a temporary (draft) memory space, so move it do destination */ \r
- for(i = 0; i < wqe_sz_dwords; ++i) { \r
- next_wqe[i] = wqe_draft[i]; \r
- }\r
- }\r
-\r
- /* Save WorkRequest ID */\r
- qp->sq_res.wqe_id[qp->sq_res.next2post_index]= p_wr->wr_id;\r
-\r
- wqe_sz_dwords_byte = wqe_sz_dwords>>2;\r
-\r
- /* Update "next" segment of previous WQE (if any) */\r
- /* this is same as WQE_pack_send_next call */\r
- qp->sq_res.last_posted_p[0] = MOSAL_cpu_to_be32(0\r
- | (u_int32_t)opcode\r
- | ((u_int32_t)(MT_ulong_ptr_t) next_wqe & BIT_MASK_FOR_NEXT_WQE_31SB ));\r
-\r
- qp->sq_res.last_posted_p[1] = MOSAL_cpu_to_be32(0 \r
- | ((wqe_sz_dwords_byte) << NEXT_ST_NDS_BIT_OFFSET ) // specify in 16 byte chunks\r
- | ( ((p_wr->send_opt & IB_SEND_OPT_FENCE)?1:0) << NEXT_ST_F_BIT_OFFSET )\r
- | (1 << NEXT_ST_DBD_BIT_OFFSET)\r
- );\r
- qp->sq_res.last_posted_p= next_wqe;\r
-\r
- /* Ring doorbell (send or rd-send) */\r
- /* This is same as THH_uar_sendq_dbell_inline */\r
-\r
- uar = qp->uar;\r
-\r
- chimeWords[0] = MOSAL_cpu_to_be32(0\r
- | (u_int32_t)opcode\r
- | (((p_wr->send_opt & IB_SEND_OPT_FENCE)?1:0)<< SEND_DOORBELL_F_BIT_OFFSET)\r
- | ((u_int32_t)(MT_ulong_ptr_t)next_wqe & 0xFFFFFFFF));\r
- chimeWords[1] = MOSAL_cpu_to_be32(0\r
- | (u_int32_t)(wqe_sz_dwords >> 2) // specify in 16 byte chunks\r
- | ((u_int32_t)(qp->qpn) << SEDN_DOORBELL_QPN_BIT_OFFSET)\r
- );\r
-\r
-#ifdef __MOSAL_MMAP_IO_WRITE_QWORD_ATOMIC__\r
- MOSAL_MMAP_IO_WRITE_QWORD(((u_int32_t *)&uar->uar_base[UAR_SEND_DBELL_OFFSET]),*(volatile u_int64_t*)chimeWords);\r
-#else\r
- cur_loc_p = (u_int32_t *)&uar->uar_base[UAR_SEND_DBELL_OFFSET];\r
- MOSAL_spinlock_dpc_lock(&(uar->uar_lock));\r
- MOSAL_MMAP_IO_WRITE_DWORD(&cur_loc_p[0], chimeWords[0]);\r
- MOSAL_MMAP_IO_WRITE_DWORD(&cur_loc_p[1], chimeWords[1]);\r
- MOSAL_spinlock_unlock(&(uar->uar_lock));\r
-#endif\r
-\r
- /* Update index */\r
- if( MOSAL_EXPECT_FALSE(\r
- ++qp->sq_res.next2post_index >= qp->sq_res.max_outs ) )\r
- {\r
- qp->sq_res.next2post_index = 0;\r
- }\r
- qp->sq_res.cur_outs++;\r
- p_wr = p_wr->p_next;\r
- }\r
- MOSAL_spinlock_unlock(&(qp->sq_res.q_lock));\r
- /* Set in all cases. If all went well, will be set to NULL. */\r
- if( pp_failed_wr )\r
- *pp_failed_wr = p_wr;\r
- switch( rc )\r
- {\r
- case HH_OK:\r
- return IB_SUCCESS;\r
-\r
- case HH_EAGAIN:\r
- return IB_INSUFFICIENT_RESOURCES;\r
-\r
- case HH_E2BIG_SG_NUM:\r
- return IB_INVALID_MAX_SGE;\r
-\r
- case HH_E2BIG_WR_NUM:\r
- return IB_INSUFFICIENT_RESOURCES;\r
-\r
- default:\r
- return IB_ERROR;\r
- }\r
-}\r
-\r
-/*\r
- * This is an optimized, IB_AL native version of THHUL_qpm_post_recv_req to\r
- * eliminate conversion time.\r
- */\r
-ib_api_status_t\r
-THHUL_qpm_post_recv_wrs(\r
- IN HHUL_hca_hndl_t hca,\r
- IN HHUL_qp_hndl_t hhul_qp,\r
- IN ib_recv_wr_t *p_recv_wr,\r
- OUT ib_recv_wr_t **pp_failed_wr OPTIONAL )\r
-{\r
- THHUL_qp_t qp = (THHUL_qp_t)hhul_qp;\r
- u_int32_t *next_wqe; /* Actual WQE pointer */\r
- u_int32_t wqe_sz_dwords;\r
- CHIME_WORDS_PREFIX u_int32_t chimeWords[2]; \r
- u_int32_t *cur_loc_p;\r
- u_int32_t wqe_sz_dwords_byte;\r
- THH_uar_t uar;\r
- ib_recv_wr_t *p_wr;\r
- HH_ret_t rc = HH_OK;\r
- //int i;\r
-\r
- if (MOSAL_EXPECT_FALSE(qp->rq_res.qp_state < VAPI_INIT ))\r
- {\r
- if( pp_failed_wr )\r
- *pp_failed_wr = p_recv_wr;\r
- MTL_ERROR1(MT_FLFMT("%s failed: qp state %d not valid to recv \n"),__func__,qp->rq_res.qp_state);\r
- return IB_INVALID_QP_STATE;\r
- }\r
-\r
- p_wr = p_recv_wr;\r
- MOSAL_spinlock_dpc_lock(&(qp->rq_res.q_lock)); /* protect wqe_draft as well as WQE allocation/link */\r
- while( p_wr )\r
- {\r
- if( MOSAL_EXPECT_FALSE(qp->rq_res.max_sg_sz < p_wr->num_ds) )\r
- {\r
- MTL_ERROR2(\r
- "THHUL_qpm_post_recv_req: Scatter/Gather list is too large (%d entries > max_sg_sz=%d)\n",\r
- p_wr->num_ds,qp->rq_res.max_sg_sz);\r
- rc = HH_EINVAL_SG_NUM;\r
- break;\r
- }\r
-\r
- /* Check if any WQEs are free to be consumed */\r
- if (MOSAL_EXPECT_FALSE(qp->rq_res.max_outs == qp->rq_res.cur_outs)) {\r
- MTL_ERROR4("THHUL_qpm_post_recv_req2: Receive queue is full (%d requests outstanding).\n",\r
- qp->rq_res.cur_outs);\r
- rc = HH_E2BIG_WR_NUM;\r
- break;\r
- }\r
- /* Allocate next WQE */\r
- next_wqe= (u_int32_t*) (qp->rq_res.wqe_buf + \r
- (qp->rq_res.next2post_index << qp->rq_res.log2_max_wqe_sz) );\r
-\r
- /* Build WQE */\r
- /* WQE_build_recv_be_req2 is same as WQE_build_recv_be but not build\r
- * sg_list.\r
- * Building sg_list is done WQE_pack_sg_list_iba \r
- */ \r
- cur_loc_p = WQE_build_recv_be_req2(qp,next_wqe,VAPI_SIGNALED);\r
-\r
-\r
- /* build sg_list */ \r
- /* This is same as calling WQE_build_send_sg_list */ \r
- /* WQE_pack_sg_list_iba build sg_list directly from IbAccess structure.\r
- * See thhul_qpm_iba.h \r
- */ \r
- cur_loc_p = WQE_pack_sg_list_ibal( p_wr, cur_loc_p );\r
-\r
- wqe_sz_dwords = (u_int32_t)((((MT_virt_addr_t)cur_loc_p) - ((MT_virt_addr_t)next_wqe)) >> 2);\r
-\r
- qp->rq_res.wqe_id[qp->rq_res.next2post_index]= p_wr->wr_id; /* Save WQE ID */\r
- if(MOSAL_EXPECT_FALSE(++qp->rq_res.next2post_index >= qp->rq_res.max_outs))\r
- qp->rq_res.next2post_index = 0;\r
-\r
- qp->rq_res.cur_outs++;\r
-\r
- /* Update "next" segment of previous WQE (if any) */\r
- wqe_sz_dwords_byte = wqe_sz_dwords>>2;\r
-\r
- qp->rq_res.last_posted_p[NEXT_ST_NDA_31_6_DWORD_OFFSET] = MOSAL_cpu_to_be32(0\r
- | ((u_int32_t)(MT_ulong_ptr_t) next_wqe & BIT_MASK_FOR_NEXT_WQE_31SB ));\r
- qp->rq_res.last_posted_p[NEXT_ST_NDS_DWORD_OFFSET] = MOSAL_cpu_to_be32(0 \r
- | (wqe_sz_dwords_byte << NEXT_ST_NDS_BIT_OFFSET ) // specify in 16 byte chunks\r
- | (1 << NEXT_ST_DBD_BIT_OFFSET)\r
- );\r
-\r
- qp->rq_res.last_posted_p= next_wqe;\r
-\r
- /* Ring doorbell */ \r
- uar = qp->uar;\r
- chimeWords[0] = MOSAL_cpu_to_be32(0\r
- | (u_int32_t)(uintn_t)next_wqe\r
- | ((wqe_sz_dwords + 3) >> 2) // specify in 16 byte chunks\r
- ); \r
- chimeWords[1] = MOSAL_cpu_to_be32(0\r
- | 1 // credits\r
- | ((u_int32_t)(qp->qpn) << 8)\r
- );\r
-\r
-#ifdef __MOSAL_MMAP_IO_WRITE_QWORD_ATOMIC__\r
- MOSAL_MMAP_IO_WRITE_QWORD(((u_int32_t *)&uar->uar_base[UAR_RECV_DBELL_OFFSET]),*(volatile u_int64_t*)chimeWords);\r
-#else\r
- MOSAL_spinlock_dpc_lock(&(uar->uar_lock));\r
- MOSAL_MMAP_IO_WRITE_QWORD(((u_int32_t *)&uar->uar_base[UAR_RECV_DBELL_OFFSET]),*(volatile u_int64_t*)chimeWords);\r
- MOSAL_spinlock_unlock(&(uar->uar_lock));\r
-#endif\r
-\r
- p_wr = p_wr->p_next;\r
- }\r
- MOSAL_spinlock_unlock(&(qp->rq_res.q_lock));\r
-\r
- /* Set in all cases. If all went well, will be set to NULL. */\r
- if( pp_failed_wr )\r
- *pp_failed_wr = p_wr;\r
- switch( rc )\r
- {\r
- case HH_OK:\r
- return IB_SUCCESS;\r
-\r
- case HH_EAGAIN:\r
- return IB_INSUFFICIENT_RESOURCES;\r
-\r
- case HH_EINVAL_SG_NUM:\r
- return IB_INVALID_MAX_SGE;\r
-\r
- case HH_E2BIG_WR_NUM:\r
- return IB_INVALID_MAX_WRS;\r
-\r
- default:\r
- return IB_ERROR;\r
- }\r
-}\r
-#endif /* WIN32 */\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_THHUL_QPM_H\r
-#define H_THHUL_QPM_H\r
-\r
-#include <mtl_common.h>\r
-#include <hhul.h>\r
-#include <thhul.h>\r
-\r
-/* The value of completed WQEs 32 ls-bits we return from THHUL_qpm_comp_ok/error \r
- * in case of end of WQEs chain - for synchronizing flush-error CQE recycling flow.\r
- * we use 1 since 0 is a valid value while 1 is not - it is not aligned to 64B */ \r
-#define THHUL_QPM_END_OF_WQE_CHAIN 1\r
-\r
-\r
-DLL_API HH_ret_t THHUL_qpm_create( \r
- /*IN*/ THHUL_hob_t hob, \r
- /*IN*/ THHUL_srqm_t srqm,\r
- /*OUT*/ THHUL_qpm_t *qpm_p \r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_qpm_destroy( \r
- /*IN*/ THHUL_qpm_t qpm \r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_qpm_create_qp_prep( \r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_qp_init_attr_t *qp_init_attr_p, \r
- /*OUT*/ HHUL_qp_hndl_t *qp_hndl_p, \r
- /*OUT*/ VAPI_qp_cap_t *qp_cap_out_p, \r
- /*OUT*/ void/*THH_qp_ul_resources_t*/ *qp_ul_resources_p \r
-);\r
-\r
-DLL_API HH_ret_t THHUL_qpm_special_qp_prep( \r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ VAPI_special_qp_t qp_type, \r
- /*IN*/ IB_port_t port, \r
- /*IN*/ HHUL_qp_init_attr_t *qp_init_attr_p, \r
- /*OUT*/ HHUL_qp_hndl_t *qp_hndl_p, \r
- /*OUT*/ VAPI_qp_cap_t *qp_cap_out_p, \r
- /*OUT*/ void/*THH_qp_ul_resources_t*/ *qp_ul_resources_p \r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_qpm_create_qp_done( \r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_qp_hndl_t hhul_qp, \r
- /*IN*/ IB_wqpn_t hh_qp, \r
- /*IN*/ void/*THH_qp_ul_resources_t*/ *qp_ul_resources_p\r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_qpm_destroy_qp_done( \r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_qp_hndl_t hhul_qp \r
-);\r
-\r
-DLL_API HH_ret_t THHUL_qpm_modify_qp_done( \r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_qp_hndl_t hhul_qp, \r
- /*IN*/ VAPI_qp_state_t cur_state \r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_qpm_post_send_req( \r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_qp_hndl_t hhul_qp, \r
- /*IN*/ VAPI_sr_desc_t *send_req_p \r
-);\r
-\r
-#ifndef WIN32\r
-DLL_API HH_ret_t THHUL_qpm_post_send_req2(\r
- /*IN*/ HHUL_hca_hndl_t hca,\r
- /*IN*/ HHUL_qp_hndl_t hhul_qp,\r
- /*IN*/ VAPI_comp_type_t comp_type,\r
- /*IN*/ VAPI_ud_av_hndl_t remote_ah,\r
- /*IN*/ void* WorkReq\r
-);\r
-#else\r
-#include <iba/ib_ci.h>\r
-DLL_API ib_api_status_t\r
-THHUL_qpm_post_send_wrs(\r
- IN HHUL_hca_hndl_t hca,\r
- IN HHUL_qp_hndl_t hhul_qp,\r
- IN ib_send_wr_t *p_send_wr,\r
- OUT ib_send_wr_t **pp_failed_wr );\r
-#endif\r
-\r
-DLL_API HH_ret_t THHUL_qpm_post_inline_send_req( \r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_qp_hndl_t hhul_qp, \r
- /*IN*/ VAPI_sr_desc_t *send_req_p \r
-);\r
-\r
-DLL_API HH_ret_t THHUL_qpm_post_send_reqs( \r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_qp_hndl_t hhul_qp, \r
- /*IN*/ u_int32_t num_of_requests,\r
- /*IN*/ VAPI_sr_desc_t *send_req_array \r
-);\r
-\r
-DLL_API HH_ret_t THHUL_qpm_post_gsi_send_req( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_qp_hndl_t hhul_qp, \r
- VAPI_sr_desc_t *send_req_p,\r
- VAPI_pkey_ix_t pkey_index\r
-);\r
-\r
-DLL_API HH_ret_t THHUL_qpm_post_recv_req( \r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_qp_hndl_t hhul_qp, \r
- /*IN*/ VAPI_rr_desc_t *recv_req_p \r
-);\r
-\r
-#ifndef WIN32\r
-DLL_API HH_ret_t THHUL_qpm_post_recv_req2(\r
- /*IN*/ HHUL_hca_hndl_t hca,\r
- /*IN*/ HHUL_qp_hndl_t hhul_qp,\r
- /*IN*/ VAPI_comp_type_t comp_type,\r
- /*IN*/ u_int32_t sg_lst_len,\r
- /*IN*/ VAPI_wr_id_t ReqId,\r
- /*IN*/ VAPI_sg_lst_entry_t *sg_lst_p\r
-);\r
-#else\r
-DLL_API ib_api_status_t\r
-THHUL_qpm_post_recv_wrs(\r
- IN HHUL_hca_hndl_t hca,\r
- IN HHUL_qp_hndl_t hhul_qp,\r
- IN ib_recv_wr_t *p_recv_wr,\r
- OUT ib_recv_wr_t **pp_failed_wr );\r
-#endif\r
-\r
-DLL_API HH_ret_t THHUL_qpm_post_recv_reqs( \r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_qp_hndl_t hhul_qp, \r
- /*IN*/ u_int32_t num_of_requests,\r
- /*IN*/ VAPI_rr_desc_t *recv_req_array \r
-);\r
-\r
-DLL_API HH_ret_t THHUL_qpm_post_bind_req(\r
- /*IN*/ HHUL_mw_bind_t *bind_props_p,\r
- /*IN*/ IB_rkey_t new_rkey\r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_qpm_comp_ok( \r
- /*IN*/ THHUL_qpm_t qpm, \r
- /*IN*/ IB_wqpn_t qpn, \r
- /*IN*/ u_int32_t wqe_addr_32lsb,\r
- /*OUT*/ VAPI_special_qp_t *qp_type_p,\r
- /*OUT*/ IB_ts_t *qp_ts_type_p,\r
- /*OUT*/ VAPI_wr_id_t *wqe_id_p,\r
- /*OUT*/ u_int32_t *wqes_released_p\r
-#ifdef IVAPI_THH\r
- , u_int32_t *reserved_p\r
-#endif \r
-);\r
-\r
-\r
-DLL_API HH_ret_t THHUL_qpm_comp_err( \r
- /*IN*/ THHUL_qpm_t qpm, \r
- /*IN*/ IB_wqpn_t qpn, \r
- /*IN*/ u_int32_t wqe_addr_32lsb, \r
- /*OUT*/ VAPI_wr_id_t *wqe_id_p,\r
- /*OUT*/ u_int32_t *wqes_released_p, \r
- /*OUT*/ u_int32_t *next_wqe_32lsb_p,\r
- /*OUT*/ u_int8_t *dbd_bit_p\r
-);\r
-\r
-DLL_API VAPI_cqe_num_t THHUL_qpm_wqe_cnt( \r
- /*IN*/THHUL_qpm_t qpm, \r
- /*IN*/IB_wqpn_t qpn, \r
- /*IN*/u_int32_t wqe_addr_32lsb, \r
- /*IN*/u_int16_t dbd_cnt\r
-);\r
-#endif /* H_THHUL_QPM_H */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_THHUL_QPM_IBAL_H\r
-#define H_THHUL_QPM_IBAL_H\r
-\r
-/********************************************************************************\r
- * This is IbAccess specific function of THHUL_qpm_post_send_req2.\r
- * It build remote_addr based on IbAccess specific opcode and build sg_list\r
- * directly from IB_LOCAL_DATASEGMENT to remove conversion in VapiHcAShim layer.\r
- * THis function supportes only ReliableConnection and ReliableDataGram.\r
- *\r
- * Used IbAccess Specific Data:\r
- * struct _IB_WORK_REQ *work_request;\r
- * IB_LOCAL_DATASEGMENT *sg_lst_entry;\r
- * work_request->Req.SendRC.RemoteDS.Address;\r
- * work_request->Req.SendRC.RemoteDS.Rkey;\r
- *\r
- *********************************************************************************\r
- */\r
-\r
-#include <iba/ib_ci.h>\r
-\r
-\r
-inline int\r
-WQE_pack_inline_sgl_ibal(\r
- IN ib_send_wr_t* const p_wr,\r
- IN u_int32_t **pp_cur_loc,\r
- IN uint32_t max_wqe_inline_size )\r
-{\r
- uint32_t i, len = 0;\r
- uint8_t *p_inline_data = (uint8_t*)( (*pp_cur_loc) + 1 );\r
-\r
-#define WQE_INLINE_FLAG (0x80000000)\r
-#define WQE_INLINE_LENGTH_MASK (0x000003FF)\r
-\r
- for( i = 0; i < p_wr->num_ds; i++ )\r
- {\r
- if( p_wr->ds_array[i].length + len > max_wqe_inline_size )\r
- return HH_EINVAL_SG_NUM;\r
-\r
- cl_memcpy( p_inline_data, (void *)p_wr->ds_array[i].vaddr, p_wr->ds_array[i].length );\r
- p_inline_data += p_wr->ds_array[i].length;\r
- len += p_wr->ds_array[i].length;\r
- }\r
-\r
- if( len )\r
- {\r
- **pp_cur_loc = cl_hton32(( WQE_INLINE_FLAG | ( len & WQE_INLINE_LENGTH_MASK )));\r
- /* Round up to nearest 16 */\r
- if( (uintn_t)p_inline_data & 0x0000000F )\r
- p_inline_data += 16 - ((uintn_t)p_inline_data & 0x0000000F);\r
- *pp_cur_loc = (uint32_t*)p_inline_data;\r
- CL_ASSERT( !((uintn_t)*pp_cur_loc & 0x0000000F) );\r
- }\r
- return HH_OK;\r
-}\r
-\r
-\r
-inline void\r
-WQE_pack_sgl_ibal(\r
- IN ib_send_wr_t* const p_wr,\r
- IN u_int32_t **pp_cur_loc )\r
-{\r
- uint32_t i;\r
-\r
- for( i = 0; i < p_wr->num_ds; i++, (*pp_cur_loc) += 4 )\r
- {\r
- WQE_IO_WRITE( &((*pp_cur_loc)[DATA_PTR_BYTE_COUNT_DWORD_OFFSET]), \r
- MOSAL_cpu_to_be32(p_wr->ds_array[i].length & 0x7fffffff) );\r
- WQE_IO_WRITE( &((*pp_cur_loc)[DATA_PTR_LKEY_DWORD_OFFSET]), \r
- MOSAL_cpu_to_be32(p_wr->ds_array[i].lkey ) );\r
- WQE_IO_WRITE( &((*pp_cur_loc)[DATA_PTR_LOCAL_ADDR_H_DWORD_OFFSET]), \r
- MOSAL_cpu_to_be32((u_int32_t)(p_wr->ds_array[i].vaddr >> 32)) );\r
- WQE_IO_WRITE( &((*pp_cur_loc)[DATA_PTR_LOCAL_ADDR_L_DWORD_OFFSET]), \r
- MOSAL_cpu_to_be32((u_int32_t)p_wr->ds_array[i].vaddr) );\r
- }\r
-}\r
-\r
-\r
-\r
-inline HH_ret_t\r
-WQE_pack_rem_addr_and_sgl_ibal(\r
- IN ib_send_wr_t* const p_wr,\r
- IN u_int32_t **pp_cur_loc,\r
- IN uint32_t max_wqe_inline_size,\r
- OUT tavor_if_nopcode_t* const p_opcode )\r
-{\r
-\r
- /* Req2 support only VAPI_RDMA_READ, VAPI_SEND, and VAPI_RDMA_WRITE */ \r
- switch( p_wr->wr_type )\r
- { \r
- default:\r
- case WR_SEND:\r
- if( p_wr->send_opt & IB_SEND_OPT_IMMEDIATE )\r
- *p_opcode = TAVOR_IF_NOPCODE_SEND_IMM;\r
- else\r
- *p_opcode = TAVOR_IF_NOPCODE_SEND;\r
-\r
- if( p_wr->send_opt & IB_SEND_OPT_INLINE )\r
- return WQE_pack_inline_sgl_ibal( p_wr, pp_cur_loc, max_wqe_inline_size );\r
-\r
- break;\r
-\r
- case WR_RDMA_WRITE:\r
- if( p_wr->send_opt & IB_SEND_OPT_IMMEDIATE )\r
- *p_opcode = TAVOR_IF_NOPCODE_RDMAW_IMM;\r
- else\r
- *p_opcode = TAVOR_IF_NOPCODE_RDMAW;\r
-\r
- *pp_cur_loc += WQE_pack_remote_addr_req2( *pp_cur_loc,\r
- p_wr->remote_ops.vaddr, cl_ntoh32(p_wr->remote_ops.rkey) );\r
-\r
- if( p_wr->send_opt & IB_SEND_OPT_INLINE )\r
- return WQE_pack_inline_sgl_ibal( p_wr, pp_cur_loc, max_wqe_inline_size );\r
- \r
- break;\r
-\r
- case WR_RDMA_READ:\r
- *p_opcode = TAVOR_IF_NOPCODE_RDMAR;\r
-\r
- *pp_cur_loc += WQE_pack_remote_addr_req2( *pp_cur_loc,\r
- p_wr->remote_ops.vaddr, cl_ntoh32(p_wr->remote_ops.rkey) );\r
-\r
- if( p_wr->send_opt & IB_SEND_OPT_INLINE )\r
- return HH_EINVAL_SG_FMT;\r
-\r
- break;\r
-\r
- case WR_COMPARE_SWAP:\r
- *p_opcode = TAVOR_IF_NOPCODE_ATOM_CMPSWP;\r
-\r
- *pp_cur_loc += WQE_pack_remote_addr_req2( *pp_cur_loc,\r
- p_wr->remote_ops.vaddr, cl_ntoh32(p_wr->remote_ops.rkey) );\r
- *pp_cur_loc += WQE_pack_atomic_cmpswp( *pp_cur_loc,\r
- p_wr->remote_ops.atomic1, p_wr->remote_ops.atomic2 );\r
-\r
- if( p_wr->num_ds != 1 )\r
- return HH_EINVAL_SG_NUM;\r
-\r
- if( p_wr->ds_array[0].length != 8 )\r
- return HH_EINVAL_SG_NUM;\r
-\r
- if( p_wr->send_opt & IB_SEND_OPT_INLINE )\r
- return HH_EINVAL_SG_FMT;\r
-\r
- break;\r
-\r
- case WR_FETCH_ADD:\r
- *p_opcode = TAVOR_IF_NOPCODE_ATOM_FTCHADD;\r
-\r
- *pp_cur_loc += WQE_pack_remote_addr_req2( *pp_cur_loc,\r
- p_wr->remote_ops.vaddr, cl_ntoh32(p_wr->remote_ops.rkey) );\r
- *pp_cur_loc += WQE_pack_atomic_fetchadd( *pp_cur_loc,\r
- p_wr->remote_ops.atomic1 );\r
-\r
- if( p_wr->num_ds != 1 )\r
- return HH_EINVAL_SG_NUM;\r
-\r
- if( p_wr->ds_array[0].length != 8 )\r
- return HH_EINVAL_SG_NUM;\r
-\r
- if( p_wr->send_opt & IB_SEND_OPT_INLINE )\r
- return HH_EINVAL_SG_FMT;\r
-\r
- break;\r
- }\r
-\r
- WQE_pack_sgl_ibal( p_wr, pp_cur_loc );\r
- return HH_OK;\r
-}\r
-\r
-\r
-inline u_int32_t *WQE_pack_sg_list_ibal(\r
- IN ib_recv_wr_t* const p_wr,\r
- IN u_int32_t *p_cur_loc )\r
-{\r
- uint32_t i;\r
-\r
- for( i = 0; i < p_wr->num_ds; i++, p_cur_loc += 4 )\r
- {\r
- WQE_IO_WRITE(&p_cur_loc[DATA_PTR_BYTE_COUNT_DWORD_OFFSET], \r
- MOSAL_cpu_to_be32(p_wr->ds_array[i].length & 0x7fffffff));\r
- WQE_IO_WRITE(&p_cur_loc[DATA_PTR_LKEY_DWORD_OFFSET], \r
- MOSAL_cpu_to_be32(p_wr->ds_array[i].lkey));\r
- WQE_IO_WRITE(&p_cur_loc[DATA_PTR_LOCAL_ADDR_H_DWORD_OFFSET], \r
- MOSAL_cpu_to_be32((u_int32_t)(p_wr->ds_array[i].vaddr >> 32)));\r
- WQE_IO_WRITE(&p_cur_loc[DATA_PTR_LOCAL_ADDR_L_DWORD_OFFSET], \r
- MOSAL_cpu_to_be32((u_int32_t)p_wr->ds_array[i].vaddr));\r
- }\r
- return p_cur_loc;\r
-}\r
-\r
-#endif\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#define C_THHUL_SRQM_C\r
-\r
-#include <mosal.h>\r
-#include <ib_defs.h>\r
-#include <vapi.h>\r
-#include <tlog2.h>\r
-#include <MT23108.h>\r
-#include <thh.h>\r
-#include <thhul.h>\r
-#include <uar.h>\r
-#include <thhul_hob.h>\r
-#include <thhul_pdm.h>\r
-#include <vapi_common.h>\r
-\r
-#include "thhul_srqm.h"\r
-\r
-#ifndef MT_KERNEL\r
-/* instead of "ifdef"ing all over the code we define an empty macro */\r
-#define MOSAL_pci_phys_free_consistent(addr,sz) do {} while(0);\r
-#endif\r
-\r
-#define NULL_WQE_BUF_P ((void*)(-1)) /* To mark resize in progress but on shrinking request */\r
-\r
-/* Limit kmalloc to 4 pages */\r
-#define WQ_KMALLOC_LIMIT (4*MOSAL_SYS_PAGE_SIZE)\r
-#define SMALL_VMALLOC_AREA (1<<28) /* VMALLOC area of 256MB or less is considered a scarce resource */\r
-\r
-#define WQE_ALIGN_SHIFT 6 /* WQE address should be aligned to 64 Byte */\r
-#define WQE_SZ_MULTIPLE_SHIFT 4 /* WQE size must be 16 bytes multiple */\r
-/* WQE segments sizes */\r
-#define WQE_SEG_SZ_NEXT (sizeof(struct wqe_segment_next_st)/8) /* NEXT segment */\r
-#define WQE_SEG_SZ_CTRL (sizeof(struct wqe_segment_ctrl_send_st)/8) /* CTRL segment */\r
-#define WQE_SEG_SZ_SG_ENTRY (sizeof(struct wqe_segment_data_ptr_st)/8)/* Scatter/Gather entry(ptr)*/\r
-#define WQE_SEG_SZ_SG_ENTRY_DW (sizeof(struct wqe_segment_data_ptr_st)/32)/* (same in DWORDs) */\r
-#define MAX_WQE_SZ 1008\r
-\r
-#define MAX_ALLOC_RETRY 3 /* Maximum retries to get WQEs buffer which does not cross 4GB boundry */\r
-\r
-#define SRQ_EMPTY_SENTRY_LKEY 1\r
-\r
-typedef struct THHUL_srq_wqe_buf_st {\r
- MT_virt_addr_t wqe_buf; /* The buffer for this queue WQEs - aligned to WQE size */\r
- u_int32_t max_outs; /* Max. outstanding (number of WQEs in buffer) */\r
- /* log2_max_wqe_sz is common to all buffers of a SRQ (no change) */\r
- void* wqe_buf_orig; /* If != NULL then resizing is in progress */\r
- MT_bool used_virt_alloc;\r
- MT_size_t wqe_buf_orig_size;\r
-} THHUL_srq_wqe_buf_t;\r
-\r
-struct THHUL_srq_st { /* SRQ context */\r
- MT_virt_addr_t hca_virt_wqe_buf; /* The WQEs buffer base in HCA's virtual addr space */\r
- /* Note: wqe_buf is in HCA virt. space */ \r
- MT_virt_addr_t real_virt_offset; /* Offset of real (OS) WQE virt. address from HCA's (resize)*/\r
- VAPI_wr_id_t *wqe_id; /* Array of max_outs entries for holding each WQE ID (WQE index based) */\r
- u_int32_t srqn; /* SRQ number/index */\r
- u_int32_t cur_outs; /* Currently outstanding */\r
- u_int32_t max_sentries; /* Max. Scatter list size */\r
- u_int8_t log2_max_wqe_sz; /* WQE size is a power of 2 (software implementation requirement) */\r
- MT_virt_addr_t free_wqes_list; /* "next" of each WQE is put on the WQE beginning */\r
- u_int32_t *wqe_draft;\r
- MT_virt_addr_t last_posted_hca_va; /* Virtual addr of last posted WQE in HCA's addr space */\r
- MOSAL_spinlock_t q_lock; /* Protect concurrent usage of the queue */\r
- HHUL_pd_hndl_t pd;\r
- THH_uar_t uar; /* UAR to use for this QP */\r
- THHUL_srq_wqe_buf_t *cur_buf_p; /* Current WQEs buffer */\r
- THHUL_srq_wqe_buf_t *resized_buf_p; /* Resized WQEs buffer */\r
- MT_bool resize_in_progress; /* When set the resizing is in progress */\r
- /* Note: Resizing may be virtually in progress while resized_buf_p==NULL, when shrinking SRQ */\r
- struct THHUL_srq_st *next; /* SRQs list */\r
-};\r
-typedef struct THHUL_srq_st *THHUL_srq_t;\r
-\r
-struct THHUL_srqm_st { /* THHUL_srqm_t is a pointer to this */\r
- struct THHUL_srq_st* srqs_list;\r
- MOSAL_mutex_t srqm_lock;\r
-};\r
-\r
-/**********************************************************************************************\r
- * Private functions protoypes declarations\r
- **********************************************************************************************/\r
-static HH_ret_t init_srq(\r
- HHUL_hca_hndl_t hca,\r
- HHUL_pd_hndl_t pd,\r
- u_int32_t max_sentries,\r
- THHUL_srq_t new_srq\r
-);\r
-\r
-static HH_ret_t compute_wqe_sz(\r
- /*IN*/ u_int32_t hca_max_sentries, /* HCA cap. of max.scatter entries for SRQs */\r
- /*IN/OUT*/ THHUL_srq_t new_srq\r
-);\r
-\r
-static HH_ret_t alloc_wqe_buf(\r
- /*IN*/ MT_bool in_ddr_mem, /* Allocation of WQEs buffer is requested in attached DDR mem. */\r
- /*IN*/ u_int32_t hca_max_outs, /* HCA cap. */\r
- /*IN*/ u_int32_t req_max_outs, /* Requested capabilities */\r
- /*IN*/ u_int8_t log2_max_wqe_sz,\r
- /*OUT*/ THHUL_srq_wqe_buf_t **buf_pp,\r
- /*OUT*/ THH_srq_ul_resources_t *srq_ul_resources_p\r
-);\r
-\r
-static void free_wqe_buf(/*IN*/THHUL_srq_wqe_buf_t *buf_p);\r
-\r
-/* Append WQEs buffer extention to WQEs free list */\r
-/* Must be invoked with SRQ lock held */\r
-static void append_to_free_list(\r
- /*IN*/ THHUL_srq_t srq,\r
- /*IN*/ MT_virt_addr_t wqes_buf_extention, /* The part of the new WQEs buf above old part */\r
- /*IN*/ MT_size_t extention_sz_in_wqes /* Extention size in WQEs */\r
-);\r
-\r
-static HH_ret_t alloc_aux_data_buf(\r
- /*IN/OUT*/ THHUL_srq_t new_srq\r
-);\r
-\r
-\r
-/**********************************************************************************************\r
- * Private inline functions \r
- **********************************************************************************************/\r
-\r
-/*********** WQE building functions ***********/\r
-\r
-/* Init a not-connected (invalid) "next" segment (i.e. NDS=0) */\r
-inline static u_int32_t srqm_WQE_init_next(u_int32_t *wqe_buf)\r
-{\r
- memset(wqe_buf,0,WQE_SEG_SZ_NEXT);\r
- return WQE_SEG_SZ_NEXT;\r
-}\r
-\r
-inline static u_int32_t srqm_WQE_pack_recv_next(u_int32_t *segment_p,u_int32_t next_wqe_32lsb)\r
-{\r
- memset(segment_p,0,WQE_SEG_SZ_NEXT); /* Clear all "RESERVED" */\r
- segment_p[MT_BYTE_OFFSET(wqe_segment_next_st,nda_31_6)>>2]= ( next_wqe_32lsb & (~MASK32(6)) ) \r
- | 1 ; /* LS-bit is set to work around bug #16159/16160/16161 */;\r
- MT_INSERT_ARRAY32(segment_p,1, /* DBD always '1 for RQ */\r
- MT_BIT_OFFSET(wqe_segment_next_st,dbd),MT_BIT_SIZE(wqe_segment_next_st,dbd));\r
- MT_INSERT_ARRAY32(segment_p,0, /* NDS always 0 for SRQs */\r
- MT_BIT_OFFSET(wqe_segment_next_st,nds),MT_BIT_SIZE(wqe_segment_next_st,nds));\r
- return WQE_SEG_SZ_NEXT;\r
-}\r
-\r
-/* Build the scatter list (pointer segments) */\r
-inline static u_int32_t WQE_pack_slist(u_int32_t *segment_p,\r
- u_int32_t sg_lst_len,VAPI_sg_lst_entry_t *sg_lst_p, u_int32_t desc_sentries)\r
-{\r
- u_int32_t i;\r
- u_int32_t *cur_loc_p= segment_p;\r
-\r
- for (i= 0; i < sg_lst_len; i++ , cur_loc_p+= WQE_SEG_SZ_SG_ENTRY_DW) {\r
- cur_loc_p[MT_BYTE_OFFSET(wqe_segment_data_ptr_st,byte_count)>>2]= \r
- (sg_lst_p[i].len & MASK32(31));\r
- cur_loc_p[MT_BYTE_OFFSET(wqe_segment_data_ptr_st,l_key)>>2]= sg_lst_p[i].lkey;\r
- cur_loc_p[MT_BYTE_OFFSET(wqe_segment_data_ptr_st,local_address_h)>>2]= \r
- (u_int32_t)(sg_lst_p[i].addr >> 32);\r
- cur_loc_p[MT_BYTE_OFFSET(wqe_segment_data_ptr_st,local_address_l)>>2]= \r
- (u_int32_t)(sg_lst_p[i].addr & 0xFFFFFFFF);\r
- }\r
- \r
- for (;i < desc_sentries; i++ , cur_loc_p+= WQE_SEG_SZ_SG_ENTRY_DW) {\r
- cur_loc_p[MT_BYTE_OFFSET(wqe_segment_data_ptr_st,byte_count)>>2]= 0;\r
- cur_loc_p[MT_BYTE_OFFSET(wqe_segment_data_ptr_st,l_key)>>2]= SRQ_EMPTY_SENTRY_LKEY;\r
- }\r
- return (u_int32_t)(((MT_virt_addr_t)cur_loc_p) - ((MT_virt_addr_t)segment_p));\r
-}\r
-\r
-\r
-/* Pack Control segment (for receive work requests) */\r
-inline static u_int32_t WQE_pack_ctrl_recv(u_int32_t *segment_p, \r
- VAPI_comp_type_t comp_type, u_int32_t event_bit)\r
-{\r
- memset(segment_p,0,WQE_SEG_SZ_CTRL); /* Clear all "RESERVED" */\r
- MT_INSERT_ARRAY32(segment_p,(comp_type == VAPI_SIGNALED) ? 1 : 0,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_recv_st,c),MT_BIT_SIZE(wqe_segment_ctrl_recv_st,c));\r
- MT_INSERT_ARRAY32(segment_p,event_bit,\r
- MT_BIT_OFFSET(wqe_segment_ctrl_recv_st,e),MT_BIT_SIZE(wqe_segment_ctrl_recv_st,e));\r
- return WQE_SEG_SZ_CTRL;\r
-}\r
-\r
-inline static u_int32_t srqm_WQE_build_recv(\r
- THHUL_srq_t srq,\r
- VAPI_rr_desc_t *recv_req_p,\r
- u_int32_t *wqe_buf\r
-)\r
-{\r
- u_int8_t *cur_loc_p= (u_int8_t*)wqe_buf; /* Current location in the WQE */\r
-\r
- cur_loc_p+= srqm_WQE_init_next((u_int32_t*)cur_loc_p); /* Make "unlinked" "next" segment */\r
- cur_loc_p+= WQE_pack_ctrl_recv((u_int32_t*)cur_loc_p,\r
- recv_req_p->comp_type, 0/*event bit*/);\r
- /* Pack scatter list segments */\r
- cur_loc_p+= WQE_pack_slist((u_int32_t*)cur_loc_p,recv_req_p->sg_lst_len,recv_req_p->sg_lst_p,\r
- srq->max_sentries);\r
- \r
- return (u_int32_t)(((MT_virt_addr_t)cur_loc_p) - ((MT_virt_addr_t)wqe_buf));\r
-}\r
-\r
-\r
-/* Extract NDS directly from (big-endian) WQE */\r
-inline static u_int8_t srqm_WQE_extract_nds(volatile u_int32_t* wqe)\r
-{\r
-/*** warning C4244: 'return' : conversion from 'unsigned long' to 'u_int8_t', possible loss of data ***/\r
- return (u_int8_t)MT_EXTRACT32(MOSAL_be32_to_cpu(wqe[MT_BYTE_OFFSET(wqe_segment_next_st,nds) >> 2]),\r
- MT_BIT_OFFSET(wqe_segment_next_st,nds) & MASK32(5),\r
- MT_BIT_SIZE(wqe_segment_next_st,nds) & MASK32(5));\r
-}\r
-\r
-/* Extract NDA directly from (big-endian) WQE */\r
-inline static u_int32_t srqm_WQE_extract_nda(volatile u_int32_t* wqe)\r
-{\r
- return (MOSAL_be32_to_cpu(wqe[MT_BYTE_OFFSET(wqe_segment_next_st,nda_31_6) >> 2]) & (~MASK32(6)) );\r
-}\r
-\r
-inline static u_int8_t srqm_WQE_extract_dbd(volatile u_int32_t* wqe)\r
-{\r
-/*** warning C4244: 'return' : conversion from 'unsigned long' to 'u_int8_t', possible loss of data ***/\r
- return (u_int8_t)MT_EXTRACT32(MOSAL_be32_to_cpu(wqe[MT_BYTE_OFFSET(wqe_segment_next_st,dbd) >> 2]),\r
- MT_BIT_OFFSET(wqe_segment_next_st,dbd) & MASK32(5),\r
- MT_BIT_SIZE(wqe_segment_next_st,dbd) & MASK32(5));\r
-}\r
-\r
-/**********************************************************************************************\r
- * Public API Functions (defined in thhul_hob.h)\r
- **********************************************************************************************/\r
-\r
-HH_ret_t THHUL_srqm_create( \r
- THHUL_hob_t hob, \r
- THHUL_srqm_t *srqm_p \r
-) \r
-{ \r
- *srqm_p= (THHUL_srqm_t) MALLOC(sizeof(struct THHUL_srqm_st));\r
- if (*srqm_p == NULL) {\r
- MTL_ERROR1("%s: Failed allocating THHUL_srqm_t.\n", __func__);\r
- return HH_EAGAIN;\r
- }\r
-\r
- (*srqm_p)->srqs_list= NULL;\r
- MOSAL_mutex_init(&((*srqm_p)->srqm_lock));\r
-\r
- return HH_OK;\r
-}\r
-\r
-\r
-HH_ret_t THHUL_srqm_destroy( \r
- THHUL_srqm_t srqm \r
-) \r
-{ \r
- \r
- THHUL_srq_t srq;\r
-\r
- while (srqm->srqs_list) {\r
- srq = srqm->srqs_list;\r
- srqm->srqs_list= srq->next;\r
- MTL_ERROR4(MT_FLFMT("%s: Releasing resource left-overs for SRQ 0x%X"), __func__, srq->srqn);\r
- /* Free QP resources: Auxilary buffer + WQEs buffer */\r
- THH_SMART_FREE(srq->wqe_id, srq->cur_buf_p->max_outs * sizeof(VAPI_wr_id_t));\r
- free_wqe_buf(srq->cur_buf_p);\r
- if (srq->resized_buf_p != NULL) free_wqe_buf(srq->resized_buf_p);\r
- FREE(srq->wqe_draft);\r
- FREE(srq);\r
- }\r
-\r
- MOSAL_mutex_free(&(srqm->srqm_lock));\r
- FREE(srqm);\r
- return HH_OK; \r
-}\r
-\r
-\r
-HH_ret_t THHUL_srqm_create_srq_prep( \r
- /*IN*/\r
- HHUL_hca_hndl_t hca, \r
- HHUL_pd_hndl_t pd,\r
- u_int32_t max_outs,\r
- u_int32_t max_sentries,\r
- /*OUT*/\r
- HHUL_srq_hndl_t *srq_hndl_p,\r
- u_int32_t *actual_max_outs_p,\r
- u_int32_t *actual_max_sentries_p,\r
- void /*THH_srq_ul_resources_t*/ *srq_ul_resources_p\r
-) \r
-{ \r
- THHUL_srqm_t srqm;\r
- THH_hca_ul_resources_t hca_ul_res;\r
- THH_srq_ul_resources_t *ul_res_p= (THH_srq_ul_resources_t*)srq_ul_resources_p;\r
- THHUL_srq_t new_srq;\r
- HH_ret_t rc;\r
- THHUL_pdm_t pdm;\r
- \r
- rc= THHUL_hob_get_srqm(hca,&srqm);\r
- if (rc != HH_OK) {\r
- MTL_ERROR4(MT_FLFMT("%s: Invalid HCA handle (%p)."), __func__, hca);\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- rc= THHUL_hob_get_hca_ul_res(hca,&hca_ul_res);\r
- if (rc != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed THHUL_hob_get_hca_ul_res (%d=%s).\n"), __func__,\r
- rc,HH_strerror_sym(rc));\r
- return rc;\r
- }\r
- \r
- rc= THHUL_hob_get_pdm(hca,&pdm);\r
- if (rc != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed THHUL_hob_get_pdm (%d=%s).\n"), __func__, \r
- rc,HH_strerror_sym(rc));\r
- return rc;\r
- }\r
- \r
- (new_srq)= (THHUL_srq_t)MALLOC(sizeof(struct THHUL_srq_st));\r
- if (new_srq == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: Failed allocating THHUL_srq_t."), __func__);\r
- return HH_EAGAIN;\r
- }\r
-\r
- rc= init_srq(hca,pd,max_sentries,new_srq);\r
- if (rc != HH_OK) {\r
- goto failed_init_srq;\r
- }\r
-\r
- rc= compute_wqe_sz(hca_ul_res.max_num_sg_ent_srq, new_srq);\r
- if (rc != HH_OK) goto failed_compute_wqe_sz;\r
-\r
- rc= alloc_wqe_buf(FALSE/*not in DDR*/,hca_ul_res.max_srq_ous_wr,max_outs,\r
- new_srq->log2_max_wqe_sz,&new_srq->cur_buf_p, srq_ul_resources_p);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: Failed allocating WQEs buffers."), __func__);\r
- goto failed_alloc_wqe;\r
- }\r
- \r
- new_srq->wqe_draft= (u_int32_t *)MALLOC((size_t)1 << new_srq->log2_max_wqe_sz);\r
- if (new_srq->wqe_draft == NULL) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed allocating %u bytes for SRQ's wqe draft"), __func__,\r
- 1 << new_srq->log2_max_wqe_sz);\r
- goto failed_wqe_draft;\r
- }\r
- \r
-\r
- rc= alloc_aux_data_buf(new_srq);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: Failed allocating auxilary buffers."), __func__);\r
- goto failed_alloc_aux;\r
- }\r
- \r
- /* Set output modifiers */\r
- *srq_hndl_p= new_srq;\r
- *actual_max_outs_p= new_srq->cur_buf_p->max_outs;\r
- *actual_max_sentries_p= new_srq->max_sentries;\r
- rc= THH_uar_get_index(new_srq->uar,&(ul_res_p->uar_index)); \r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT(": Failed getting UAR index.\n"));\r
- goto failed_uar_index;\r
- }\r
- /* wqe_buf data in srq_ul_resources_p is already set in alloc_wqe_buf */\r
- \r
- /* update SRQs list */\r
- MOSAL_mutex_acq_ui(&(srqm->srqm_lock));\r
- new_srq->next= srqm->srqs_list;\r
- srqm->srqs_list= new_srq;\r
- MOSAL_mutex_rel(&(srqm->srqm_lock));\r
-\r
- return HH_OK;\r
-\r
- /* Error cleanup */\r
- failed_uar_index:\r
- THH_SMART_FREE(new_srq->wqe_id, new_srq->cur_buf_p->max_outs * sizeof(VAPI_wr_id_t)); \r
- failed_alloc_aux:\r
- FREE(new_srq->wqe_draft);\r
- failed_wqe_draft:\r
- free_wqe_buf(new_srq->cur_buf_p);\r
- failed_alloc_wqe:\r
- failed_compute_wqe_sz:\r
- failed_init_srq:\r
- FREE(new_srq);\r
- return rc;\r
-}\r
-\r
-\r
-HH_ret_t THHUL_srqm_create_srq_done( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_srq_hndl_t hhul_srq, \r
- HH_srq_hndl_t hh_srq, \r
- void/*THH_srq_ul_resources_t*/ *srq_ul_resources_p\r
-) \r
-{ \r
- THHUL_srqm_t srqm;\r
- THHUL_srq_t srq= (THHUL_srq_t)hhul_srq;\r
- THH_srq_ul_resources_t *ul_res_p= (THH_srq_ul_resources_t*)srq_ul_resources_p;\r
- HH_ret_t rc;\r
- \r
- rc= THHUL_hob_get_srqm(hca,&srqm);\r
- if (rc != HH_OK) {\r
- MTL_ERROR4(MT_FLFMT("%s: Invalid HCA handle (%p)."), __func__, hca);\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- if (srq == NULL) {\r
- MTL_ERROR4(MT_FLFMT("%s: NULL hhul_qp handle."), __func__);\r
- return HH_EINVAL;\r
- }\r
- \r
- if (srq->cur_buf_p->wqe_buf_orig == NULL) { /* WQEs buffer allocated in DDR mem. by THH_qpm */\r
- if (ul_res_p->wqes_buf == 0) {\r
- MTL_ERROR1(MT_FLFMT("%s: Got NULL WQEs buffer from qp_ul_res for new srqn=0x%X."), __func__, \r
- hh_srq);\r
- return HH_EINVAL;\r
- }\r
- /* Set the per queue resources */\r
- srq->cur_buf_p->wqe_buf= MT_UP_ALIGNX_VIRT(ul_res_p->wqes_buf,srq->log2_max_wqe_sz);\r
- if (srq->cur_buf_p->wqe_buf != ul_res_p->wqes_buf) {\r
- MTL_ERROR1(\r
- "THHUL_srqm_create_qp_done: Buffer allocated by THH_qpm ("VIRT_ADDR_FMT") "\r
- "is not aligned to RQ WQE size (%d bytes).\n",\r
- ul_res_p->wqes_buf,1<<srq->log2_max_wqe_sz);\r
- return HH_EINVAL;\r
- }\r
- }\r
-\r
- srq->hca_virt_wqe_buf= srq->cur_buf_p->wqe_buf;/* first buffer is the HCA's virt. addr. */\r
-\r
- /* Create free WQEs list of wqe_buf */\r
- append_to_free_list(srq, srq->cur_buf_p->wqe_buf,srq->cur_buf_p->max_outs);\r
- \r
- srq->srqn= hh_srq;\r
-\r
- MTL_DEBUG4(MT_FLFMT("%s: srqn=0x%X buf_p="VIRT_ADDR_FMT" sz=0x%X"), __func__,\r
- srq->srqn, srq->cur_buf_p->wqe_buf, \r
- (1 << srq->log2_max_wqe_sz) * srq->cur_buf_p->max_outs);\r
-\r
- return HH_OK;\r
-}\r
-\r
-HH_ret_t THHUL_srqm_modify_srq_prep(\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/HHUL_srq_hndl_t hhul_srq,\r
- /*IN*/VAPI_srq_attr_t *srq_attr_p,\r
- /*IN*/VAPI_srq_attr_mask_t srq_attr_mask,\r
- /*OUT*/void/*THH_srq_ul_resources_t*/ *srq_ul_resources_p\r
-)\r
-{\r
- THHUL_srqm_t srqm;\r
- THHUL_srq_t srq= (THHUL_srq_t)hhul_srq;\r
- THH_srq_ul_resources_t *srq_ul_res_p= (THH_srq_ul_resources_t*)srq_ul_resources_p;\r
- THH_hca_ul_resources_t hca_ul_res;\r
- THHUL_srq_wqe_buf_t *new_buf_p;\r
- HH_ret_t rc;\r
-\r
- /* Parameters check */\r
- if (srq_attr_mask != VAPI_SRQ_ATTR_MAX_OUTS_WR) {\r
- MTL_ERROR1(MT_FLFMT(\r
- "%s: Only VAPI_SRQ_ATTR_MAX_OUTS_WR flag is supported (got srq_attr_mask=0x%X)"),\r
- __func__, srq_attr_mask);\r
- return HH_ENOSYS;\r
- }\r
- rc= THHUL_hob_get_srqm(hca,&srqm);\r
- if (rc != HH_OK) {\r
- MTL_ERROR4(MT_FLFMT("%s: Invalid HCA handle (%p)."), __func__, hca);\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- if (srq == NULL) {\r
- MTL_ERROR4(MT_FLFMT("%s: NULL hhul_qp handle."), __func__);\r
- return HH_EINVAL;\r
- }\r
- rc= THHUL_hob_get_hca_ul_res(hca,&hca_ul_res);\r
- if (rc != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed THHUL_hob_get_hca_ul_res (%d=%s).\n"), __func__,\r
- rc,HH_strerror_sym(rc));\r
- return rc;\r
- }\r
-\r
- if (srq_attr_p->max_outs_wr > srq->cur_buf_p->max_outs) {\r
- rc= alloc_wqe_buf(FALSE/*not in DDR*/,hca_ul_res.max_srq_ous_wr,srq_attr_p->max_outs_wr,\r
- srq->log2_max_wqe_sz,&new_buf_p, srq_ul_res_p);\r
- if (rc != HH_OK) {\r
- MTL_ERROR1(MT_FLFMT("%s: Failed allocating WQEs buffers."), __func__);\r
- return rc;\r
- }\r
- } else { /* Shrinking implies no change for current implementation */\r
- new_buf_p= NULL;\r
- /* Signal to THH_srqm that there is nothing to change (all fields of ul_res set to 0) */\r
- memset(srq_ul_res_p,0,sizeof(THH_srq_ul_resources_t)); \r
- }\r
- \r
- MOSAL_spinlock_dpc_lock(&(srq->q_lock)); \r
- if (srq->resize_in_progress) {\r
- MOSAL_spinlock_unlock(&(srq->q_lock)); \r
- MTL_ERROR1(MT_FLFMT("%s: Invoked while resize is in progress (SRQn=0x%X)"), __func__,\r
- srq->srqn);\r
- if (new_buf_p != NULL) free_wqe_buf(new_buf_p);\r
- return HH_EBUSY;\r
- }\r
-\r
- srq->resized_buf_p= new_buf_p;\r
- if (srq->resized_buf_p != NULL) {\r
- /* Duplicate WQEs buffer image into resized buffer */\r
- memcpy((void*)srq->resized_buf_p->wqe_buf,(void*)srq->cur_buf_p->wqe_buf,\r
- srq->cur_buf_p->max_outs << srq->log2_max_wqe_sz);\r
- }\r
- srq->resize_in_progress= TRUE;\r
-\r
- MOSAL_spinlock_unlock(&(srq->q_lock)); \r
- \r
- return HH_OK;\r
-}\r
-\r
-\r
-HH_ret_t THHUL_srqm_modify_srq_done( \r
- /*IN*/HHUL_hca_hndl_t hca, \r
- /*IN*/HHUL_srq_hndl_t hhul_srq, \r
- /*IN*/void/*THH_srq_ul_resources_t*/ *srq_ul_resources_p,\r
- /*OUT*/u_int32_t *max_outs_wr_p /* Max. outstanding WQEs */\r
-) \r
-{ \r
- THHUL_srqm_t srqm;\r
- THHUL_srq_t srq= (THHUL_srq_t)hhul_srq;\r
- THH_srq_ul_resources_t *ul_res_p= (THH_srq_ul_resources_t*)srq_ul_resources_p;\r
- HH_ret_t rc= HH_OK;\r
- THHUL_srq_wqe_buf_t *freed_wqe_buf_p= NULL;\r
- VAPI_wr_id_t *new_wqe_id_array,*freed_wqe_id_array= NULL;\r
- \r
- rc= THHUL_hob_get_srqm(hca,&srqm);\r
- if (rc != HH_OK) {\r
- MTL_ERROR4(MT_FLFMT("%s: Invalid HCA handle (%p)."), __func__, hca);\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- if (srq == NULL) {\r
- MTL_ERROR4(MT_FLFMT("%s: NULL hhul_qp handle."), __func__);\r
- return HH_EINVAL_SRQ_HNDL;\r
- }\r
- \r
-\r
- if (! srq->resize_in_progress) {\r
- MOSAL_spinlock_unlock(&(srq->q_lock)); \r
- MTL_ERROR1(MT_FLFMT("%s: Invoked while NO resize in progress (SRQn=0x%X)"), __func__,\r
- srq->srqn);\r
- return HH_EFATAL;\r
- }\r
- \r
- if (srq->resized_buf_p == NULL) { /* Shrinking */\r
- /* When "shrinking" not resources were allocated - nothing to free */\r
- goto clean_exit;\r
- }\r
-\r
- freed_wqe_buf_p= srq->resized_buf_p; /* Clean resized buffer for any of the following errors */\r
-\r
- if (ul_res_p == NULL) { /* Failure - rollback the modify_prep */\r
- MTL_ERROR4(MT_FLFMT("%s: Got failure notification from VIPKL_modify_srq (SRQn=0x%X)"),__func__,\r
- srq->srqn);\r
- rc= HH_OK; /* No problem in rolling back the modify_prep... */\r
- goto clean_exit;\r
- }\r
- \r
- if (srq->resized_buf_p->wqe_buf_orig == NULL) { /* WQEs buffer allocated in DDR mem. by THH_qpm */\r
- if (ul_res_p->wqes_buf == 0) {\r
- MTL_ERROR1(MT_FLFMT("%s: Got NULL WQEs buffer from qp_ul_res for new srqn=0x%X."), __func__, \r
- srq->srqn);\r
- rc= HH_EAGAIN;\r
- goto clean_exit;\r
- }\r
- /* Set the per queue resources */\r
- srq->resized_buf_p->wqe_buf= MT_UP_ALIGNX_VIRT(ul_res_p->wqes_buf,srq->log2_max_wqe_sz);\r
- if (srq->resized_buf_p->wqe_buf != ul_res_p->wqes_buf) {\r
- MTL_ERROR1(\r
- "%s: Buffer allocated by THH_qpm ("VIRT_ADDR_FMT") "\r
- "is not aligned to RQ WQE size (%d bytes).\n", __func__,\r
- ul_res_p->wqes_buf,1<<srq->log2_max_wqe_sz);\r
- return HH_EFATAL; /* Free nothing - inconsistancy problem */\r
- }\r
- }\r
-\r
- new_wqe_id_array= (VAPI_wr_id_t*)\r
- THH_SMART_MALLOC(srq->resized_buf_p->max_outs * sizeof(VAPI_wr_id_t)); \r
- if (new_wqe_id_array == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: Failed allocating SRQ auxilary buffer (for 0x%X WQEs IDs)."), __func__,\r
- srq->resized_buf_p->max_outs);\r
- rc= HH_EAGAIN;\r
- /* Failing to extend the WQEs ID buffer still requires using the new buffer \r
- * (HCA already moved to new buffer). So we define it with the same size as current */\r
- srq->resized_buf_p->max_outs= srq->cur_buf_p->max_outs;\r
- new_wqe_id_array= srq->wqe_id; /* use original */\r
- }\r
-\r
- MOSAL_spinlock_dpc_lock(&(srq->q_lock));\r
- if (new_wqe_id_array != srq->wqe_id) {\r
- /* Copy old WQE IDs to new buffer */\r
- memcpy(new_wqe_id_array, srq->wqe_id, srq->cur_buf_p->max_outs * sizeof(VAPI_wr_id_t));\r
- freed_wqe_id_array= srq->wqe_id; /* save to free outside of spinlock */\r
- srq->wqe_id= new_wqe_id_array;\r
- }\r
- \r
- freed_wqe_buf_p= srq->cur_buf_p; /* save to free outside of spinlock */\r
- srq->cur_buf_p= srq->resized_buf_p; /* Set resized as cur_buf */\r
- srq->real_virt_offset= srq->cur_buf_p->wqe_buf - srq->hca_virt_wqe_buf;\r
-\r
- /* Add to free WQEs the new WQEs */\r
- append_to_free_list(srq, \r
- srq->cur_buf_p->wqe_buf + \r
- (freed_wqe_buf_p->max_outs << srq->log2_max_wqe_sz),\r
- srq->cur_buf_p->max_outs - freed_wqe_buf_p->max_outs);\r
- \r
- MOSAL_spinlock_unlock(&(srq->q_lock)); \r
-\r
- clean_exit:\r
- /* Set output modifier */\r
- if (max_outs_wr_p != NULL) *max_outs_wr_p= srq->cur_buf_p->max_outs;\r
- /* Free unused resources */\r
- if (freed_wqe_id_array != NULL) {\r
- THH_SMART_FREE(freed_wqe_id_array, freed_wqe_buf_p->max_outs * sizeof(VAPI_wr_id_t));\r
- }\r
- if (freed_wqe_buf_p != NULL) {\r
- free_wqe_buf(freed_wqe_buf_p);\r
- }\r
- srq->resized_buf_p= NULL; \r
- srq->resize_in_progress= FALSE;\r
- \r
- MTL_DEBUG4(MT_FLFMT("%s: srqn=0x%X buf_p="VIRT_ADDR_FMT" sz=0x%X"), __func__,\r
- srq->srqn, srq->cur_buf_p->wqe_buf, \r
- (1 << srq->log2_max_wqe_sz) * srq->cur_buf_p->max_outs);\r
- \r
- return rc;\r
-}\r
-\r
-HH_ret_t THHUL_srqm_destroy_srq_done( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_qp_hndl_t hhul_srq \r
-) \r
-{ \r
- THHUL_srqm_t srqm;\r
- THHUL_srq_t srq= (THHUL_srq_t)hhul_srq;\r
- THHUL_srq_t cur_srq,prev_srq;\r
- HH_ret_t rc;\r
- \r
- rc= THHUL_hob_get_srqm(hca,&srqm);\r
- if (rc != HH_OK) {\r
- MTL_ERROR4("%s: Invalid HCA handle (%p).", __func__, hca);\r
- return HH_EINVAL_HCA_HNDL;\r
- }\r
- \r
- /* update SRQs list */\r
- MOSAL_mutex_acq_ui(&(srqm->srqm_lock));\r
- /* find SRQ in SRQs list */\r
- for (prev_srq= NULL, cur_srq= srqm->srqs_list; \r
- (cur_srq != NULL) && (cur_srq != srq); \r
- prev_srq= cur_srq , cur_srq= cur_srq->next);\r
- if (cur_srq == NULL) {\r
- MOSAL_mutex_rel(&(srqm->srqm_lock));\r
- MTL_ERROR2(MT_FLFMT("%s: Could not find given SRQ (hndl=0x%p , srqn=0x%X)"), __func__, \r
- srq, srq->srqn);\r
- return HH_EINVAL_SRQ_HNDL;\r
- }\r
- /* remove SRQ from list */\r
- if (prev_srq != NULL) prev_srq->next= srq->next;\r
- else srqm->srqs_list= srq->next;\r
- MOSAL_mutex_rel(&(srqm->srqm_lock));\r
-\r
- /* Free SRQ resources: Auxilary buffer + WQEs buffer + WQE draft + SRQ object */\r
- MTL_DEBUG4(MT_FLFMT("Freeing user level WQE-IDs auxilary buffers"));\r
- THH_SMART_FREE(srq->wqe_id, srq->cur_buf_p->max_outs * sizeof(VAPI_wr_id_t)); \r
- free_wqe_buf(srq->cur_buf_p);\r
- FREE(srq->wqe_draft);\r
- FREE(srq);\r
- \r
- return HH_OK; \r
-}\r
-\r
-\r
-\r
-HH_ret_t THHUL_srqm_post_recv_reqs(\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_srq_hndl_t hhul_srq, \r
- /*IN*/ u_int32_t num_of_requests,\r
- /*IN*/ VAPI_rr_desc_t *recv_req_array,\r
- /*OUT*/ u_int32_t *posted_requests_p\r
- )\r
-{\r
- THHUL_srq_t srq= (THHUL_srq_t)hhul_srq;\r
- u_int32_t* wqe_draft= srq->wqe_draft;\r
- u_int32_t next_draft[WQE_SEG_SZ_NEXT>>2]; /* Build "next" segment here */\r
- volatile u_int32_t* next_wqe= NULL; /* Actual WQE pointer */\r
- volatile u_int32_t* resized_next_wqe= NULL; \r
- MT_virt_addr_t next_wqe_hca_virt, resized_virt_offset=0;\r
- volatile u_int32_t* prev_wqe_p;\r
- volatile u_int32_t* resized_prev_wqe_p= NULL;\r
- u_int32_t wqe_sz_dwords= 0;\r
- u_int32_t i,reqi,next2post_index;\r
- THH_uar_recvq_dbell_t rq_dbell;\r
- HH_ret_t ret= HH_OK;\r
-\r
- *posted_requests_p= 0;\r
- if (num_of_requests == 0) return HH_OK; /* nothing to do */\r
- \r
- /* Init. invariant RQ doorbell fields */\r
- rq_dbell.qpn= srq->srqn;\r
- rq_dbell.next_size= 0; /* For SRQs, NDS comes from SRQC */\r
- rq_dbell.credits= 0; /* For 256 WQEs quantums */\r
- \r
- MOSAL_spinlock_dpc_lock(&(srq->q_lock)); /* protect wqe_draft as well as WQE allocation/link */\r
- \r
- prev_wqe_p= (srq->last_posted_hca_va == 0) ? \r
- NULL : \r
- (void*)(srq->last_posted_hca_va + srq->real_virt_offset); \r
- rq_dbell.next_addr_32lsb= (u_int32_t)srq->free_wqes_list; /* For first chain */\r
-\r
- if (srq->resized_buf_p != NULL) {\r
- resized_virt_offset= srq->resized_buf_p->wqe_buf - srq->hca_virt_wqe_buf;\r
- resized_prev_wqe_p= (srq->last_posted_hca_va == 0) ? \r
- NULL : \r
- (void*)(srq->last_posted_hca_va + resized_virt_offset);\r
- }\r
-\r
- /* Build and link all WQEs */\r
- for (reqi= 0; (reqi < num_of_requests) ; reqi++) {\r
- \r
- if (srq->free_wqes_list == 0) {\r
- MTL_ERROR2(MT_FLFMT(\r
- "%s: Posting only %u requests out of %u"), __func__, *posted_requests_p, num_of_requests);\r
- ret= HH_EAGAIN;\r
- break;\r
- }\r
- \r
- if (srq->max_sentries < recv_req_array[reqi].sg_lst_len) {\r
- MTL_ERROR2(MT_FLFMT(\r
- "%s: Scatter list of req. #%u is too large (%u entries > max_sg_sz=%u)"), __func__,\r
- reqi,recv_req_array[reqi].sg_lst_len,srq->max_sentries);\r
- ret= HH_EINVAL_SG_NUM;\r
- break;\r
- }\r
-\r
- if (recv_req_array[reqi].opcode != VAPI_RECEIVE) {\r
- MTL_ERROR2(MT_FLFMT(\r
- "%s: Invalid opcode (%d=%s)in request #%d"), __func__,\r
- recv_req_array[reqi].opcode, VAPI_wr_opcode_sym(recv_req_array[reqi].opcode), reqi);\r
- ret= HH_EINVAL_OPCODE;\r
- break;\r
- }\r
-\r
- /* Build WQE */\r
- wqe_sz_dwords= (srqm_WQE_build_recv(srq,recv_req_array+reqi,wqe_draft) >> 2);\r
- #ifdef MAX_DEBUG\r
- if ((wqe_sz_dwords<<2) > (1U << srq->log2_max_wqe_sz)) {\r
- MTL_ERROR1(MT_FLFMT("%s: SRQ 0x%X: WQE too large (%d > max=%d)"), __func__,\r
- srq->srqn,(wqe_sz_dwords<<2),(1U << srq->log2_max_wqe_sz));\r
- }\r
- #endif\r
- \r
- /* Allocate next WQE */\r
- next_wqe_hca_virt= srq->free_wqes_list ;\r
- next_wqe= (volatile u_int32_t*)(next_wqe_hca_virt + srq->real_virt_offset);\r
- srq->free_wqes_list= *((MT_virt_addr_t*)next_wqe);/* next WQE is in the WQE (when free) */\r
- /* Save WQE ID */\r
- next2post_index= (u_int32_t)(((u_int8_t*)next_wqe - (u_int8_t*)srq->cur_buf_p->wqe_buf) >> \r
- srq->log2_max_wqe_sz);\r
- MTL_DEBUG6(MT_FLFMT("%s: SRQ 0x%X posting WQE at index %u (real_va=%p, hca_va="\r
- VIRT_ADDR_FMT")"), __func__, \r
- srq->srqn, next2post_index, next_wqe, next_wqe_hca_virt); //DEBUG\r
- srq->wqe_id[next2post_index]= recv_req_array[reqi].id; /* Save WQE ID */\r
-\r
- /* copy (while swapping,if needed) the wqe_draft to the actual WQE */\r
- /* TBD: for big-endian machines we can optimize here and use memcpy */\r
- for (i= 0; i < wqe_sz_dwords; i++) {\r
- next_wqe[i]= MOSAL_cpu_to_be32(wqe_draft[i]);\r
- }\r
- \r
- if (srq->resized_buf_p != NULL) {\r
- resized_next_wqe= (volatile u_int32_t*)(next_wqe_hca_virt + resized_virt_offset);\r
- for (i= 0; i < wqe_sz_dwords; i++) { /* Copy WQE to resized buffer */\r
- resized_next_wqe[i]= MOSAL_cpu_to_be32(wqe_draft[i]);\r
- }\r
- }\r
-\r
- if (prev_wqe_p != NULL) { \r
- /* Update "next" segment of previous WQE */\r
- /* Build linking "next" segment in last posted WQE */\r
- srqm_WQE_pack_recv_next(next_draft, (u_int32_t)next_wqe_hca_virt);\r
- for (i= 0;i < (WQE_SEG_SZ_NEXT>>2) ;i++) {\r
- /* This copy assures big-endian as well as that DBD/NDS is written last */\r
- prev_wqe_p[i]= MOSAL_cpu_to_be32(next_draft[i]);\r
- }\r
- if (srq->resized_buf_p != NULL) {\r
- for (i= 0;i < (WQE_SEG_SZ_NEXT>>2) ;i++) { /* Link in resized buffer, too */\r
- resized_prev_wqe_p[i]= MOSAL_cpu_to_be32(next_draft[i]);\r
- }\r
- }\r
- }\r
-\r
- prev_wqe_p= next_wqe;\r
- resized_prev_wqe_p= resized_next_wqe;\r
-\r
- (*posted_requests_p)++;\r
-\r
- if (((*posted_requests_p) & 0xFF) == 0) { /* ring RQ doorbell every 256 WQEs */\r
- THH_uar_recvq_dbell(srq->uar,&rq_dbell);\r
- rq_dbell.next_addr_32lsb= (u_int32_t)srq->free_wqes_list; /* For next chain */\r
- }\r
- }\r
- \r
- if (((*posted_requests_p) & 0xFF) != 0) { /* left-overs (less than 256 WQEs) */\r
- rq_dbell.credits= (*posted_requests_p) & 0xFF;\r
- THH_uar_recvq_dbell(srq->uar,&rq_dbell);\r
- }\r
- \r
- srq->last_posted_hca_va= ((MT_virt_addr_t)prev_wqe_p) - srq->real_virt_offset;\r
- srq->cur_outs+= *posted_requests_p; /* redundant info - for debug */\r
- \r
- MOSAL_spinlock_unlock(&(srq->q_lock));\r
- return ret;\r
-\r
-}\r
-\r
-\r
-\r
-/* Release this WQE only and return its WQE ID */\r
-HH_ret_t THHUL_srqm_comp( \r
- THHUL_srqm_t srqm, \r
- HHUL_srq_hndl_t hhul_srq,\r
- u_int32_t wqe_addr_32lsb, \r
- VAPI_wr_id_t *wqe_id_p\r
-) \r
-{ \r
- THHUL_srq_t srq= (THHUL_srq_t)hhul_srq;\r
- u_int32_t wqes_base_32lsb= (u_int32_t)(srq->hca_virt_wqe_buf & 0xFFFFFFFF) ;\r
- u_int32_t freed_wqe_index;\r
- MT_virt_addr_t wqe_buf_h= sizeof(u_int32_t*) > 4 ? (srq->hca_virt_wqe_buf >> 32) << 32 : 0;\r
- MT_virt_addr_t wqe_addr= wqe_buf_h | wqe_addr_32lsb;\r
-\r
- if (wqe_addr_32lsb < wqes_base_32lsb) {\r
- MTL_ERROR1(MT_FLFMT("%s: Got wqe_addr_32lsb=0x%X < wqes_base_32lsb=0x%X"), __func__,\r
- wqe_addr_32lsb, wqes_base_32lsb);\r
- return HH_EINVAL;\r
- }\r
- if (wqe_addr_32lsb & MASK32(srq->log2_max_wqe_sz)) {\r
- MTL_ERROR1(MT_FLFMT(\r
- "%s: Got wqe_addr_32lsb=0x%X which is not aligned to WQE size/stride 2^%u"),\r
- __func__, wqe_addr_32lsb, srq->log2_max_wqe_sz);\r
- return HH_EINVAL;\r
- }\r
-\r
- freed_wqe_index= (wqe_addr_32lsb - wqes_base_32lsb) >> srq->log2_max_wqe_sz;\r
- \r
- MOSAL_spinlock_dpc_lock(&(srq->q_lock));\r
- if (freed_wqe_index > srq->cur_buf_p->max_outs) {\r
- MTL_ERROR1(MT_FLFMT("%s: Got wqe_addr_32lsb=0x%X which is WQE index 0x%X "\r
- "(max_outs=0x%X , wqes_base_32lsb=0x%X , log2_max_wqe_sz=0x%X)"), \r
- __func__, wqe_addr_32lsb, freed_wqe_index, \r
- srq->cur_buf_p->max_outs, wqes_base_32lsb, srq->log2_max_wqe_sz);\r
- MOSAL_spinlock_unlock(&(srq->q_lock));\r
- return HH_EINVAL;\r
- }\r
-\r
- /* Get WQE ID from auxilary buffer */\r
- *wqe_id_p= srq->wqe_id[freed_wqe_index]; \r
-\r
- /* Return WQE to free list */\r
- *((MT_virt_addr_t*)(wqe_addr+srq->real_virt_offset))= \r
- srq->free_wqes_list; /* Link WQE to first in free list */\r
- srq->free_wqes_list= wqe_addr; /* Put as first in free list */\r
- srq->cur_outs --; /* (for debug purpose) */\r
- if (wqe_addr == srq->last_posted_hca_va) {\r
- /* After WQE put in the free list, we should not link it to next WQE */\r
- srq->last_posted_hca_va= 0;\r
- }\r
- MOSAL_spinlock_unlock(&(srq->q_lock));\r
-\r
- return HH_OK;\r
-}\r
-\r
-\r
-\r
-/**********************************************************************************************\r
- * Private Functions\r
- **********************************************************************************************/\r
-\r
-\r
-/* Allocate THHUL_srq_t object and initialize it */\r
-static HH_ret_t init_srq(\r
- HHUL_hca_hndl_t hca,\r
- HHUL_pd_hndl_t pd,\r
- u_int32_t max_sentries,\r
- THHUL_srq_t new_srq\r
-)\r
-{\r
- HH_ret_t rc;\r
- THHUL_pdm_t pdm;\r
-\r
- memset(new_srq,0,sizeof(struct THHUL_srq_st));\r
- \r
- rc= THHUL_hob_get_uar(hca,&(new_srq->uar));\r
- if (rc != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed getting THHUL_hob's UAR (%d=%s)."),\r
- __func__,rc,HH_strerror_sym(rc));\r
- return rc;\r
- }\r
- rc= THHUL_hob_get_pdm(hca,&pdm);\r
- if (rc != HH_OK) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed getting THHUL_hob_get_pdm's UAR (%d=%s)."),\r
- __func__,rc,HH_strerror_sym(rc));\r
- return rc;\r
- }\r
- \r
- new_srq->srqn= 0xFFFFFFFF; /* Init to invalid SRQ num. until create_qp_done is invoked */\r
- new_srq->pd= pd;\r
- new_srq->max_sentries= max_sentries;\r
- MOSAL_spinlock_init(&(new_srq->q_lock));\r
-\r
- return HH_OK;\r
-}\r
-\r
-inline static MT_bool srqm_within_4GB(void* base, MT_size_t bsize)\r
-{\r
- u_int64_t start_addr;\r
- u_int64_t end_addr;\r
-\r
- if (sizeof(MT_virt_addr_t) <=4) return TRUE; /* For 32 bits machines no check is required */\r
- start_addr= (u_int64_t)(MT_virt_addr_t)base;\r
- end_addr= start_addr+bsize-1;\r
- return ((start_addr >> 32) == (end_addr >> 32)); /* TRUE if 32 MS-bits equal */\r
-\r
-}\r
-\r
-inline static void* srqm_malloc_within_4GB(MT_size_t bsize, MT_bool *used_virt_alloc_p)\r
-{\r
- void* buf[MAX_ALLOC_RETRY]={NULL};\r
- MT_bool used_virt_alloc[MAX_ALLOC_RETRY];\r
- int i,j;\r
-\r
- for (i= 0; i < MAX_ALLOC_RETRY; i++) { /* Retry to avoid crossing 4GB */\r
-#if defined(MT_KERNEL) && defined(__LINUX__)\r
- /* Consider using low memory (kmalloc) up to WQ_KMALLOC_LIMIT or for small vmalloc area */\r
- if (bsize <= WQ_KMALLOC_LIMIT) {\r
- buf[i]= (void*)MOSAL_pci_phys_alloc_consistent(bsize,0); /* try to use kmalloc */\r
- used_virt_alloc[i]= FALSE;\r
- } \r
- if (buf[i] == NULL) /* failed kmalloc, or did not even try it */\r
-#endif\r
- {\r
- buf[i]= (void*)MOSAL_pci_virt_alloc_consistent(bsize, 0); //TODO: must pass proper alignment here. For now thhul_qpm is unused in Darwin.\r
- used_virt_alloc[i]= TRUE;\r
- }\r
- if (buf[i] == NULL) {\r
- MTL_ERROR3("srqm_malloc_within_4GB: Failed allocating buffer of "SIZE_T_FMT" bytes (iteration %d).\n",\r
- bsize,i);\r
- /* Free previously allocated buffers if any*/\r
- for (j= i; j > 0; j--) {\r
- if (used_virt_alloc[j-1]) {\r
- MOSAL_pci_virt_free_consistent(buf[j-1], bsize);\r
- } else {\r
- MOSAL_pci_phys_free_consistent(buf[j-1], bsize);\r
- }\r
- }\r
- return NULL;\r
- }\r
- if (srqm_within_4GB(buf[i],bsize)) break;\r
- }\r
- if (i == MAX_ALLOC_RETRY) { /* Failed */\r
- MTL_ERROR2("srqm_malloc_within_4GB: Failed allocating buffer of "SIZE_T_FMT" bytes within 4GB boundry "\r
- "(%d retries).\n", bsize, MAX_ALLOC_RETRY); \r
- /* Free all allocated buffers */\r
- for (i= 0; i < MAX_ALLOC_RETRY; i++) {\r
- if (used_virt_alloc[i]) {\r
- MOSAL_pci_virt_free_consistent(buf[i], bsize);\r
- } else {\r
- MOSAL_pci_phys_free_consistent(buf[i], bsize);\r
- }\r
- }\r
- return NULL;\r
- }\r
- /* Free disqualified buffers if any */\r
- for (j= i; j > 0; j--) {\r
- if (used_virt_alloc[j-1]) {\r
- MOSAL_pci_virt_free_consistent(buf[j-1], bsize);\r
- } else {\r
- MOSAL_pci_phys_free_consistent(buf[j-1], bsize);\r
- }\r
- }\r
-\r
- *used_virt_alloc_p= used_virt_alloc[i];\r
- return buf[i]; /* This is the one buffer which does not cross 4GB boundry */\r
-}\r
-\r
-/* Compute needed WQE size and set new_srq->log2_wqe_sz */\r
-static HH_ret_t compute_wqe_sz(\r
- /*IN*/ u_int32_t hca_max_sentries, /* HCA cap. of max.scatter entries for SRQs */\r
- /*IN/OUT*/ THHUL_srq_t new_srq\r
-)\r
-{\r
- u_int32_t wqe_sz,wqe_base_sz;\r
-\r
- /* Check requested capabilities */\r
- if (new_srq->max_sentries > hca_max_sentries) {\r
- MTL_ERROR2(MT_FLFMT(\r
- "%s: Got request for %u scatter entries (HCA cap. for SRQ is %u scatter entries)"),\r
- __func__, new_srq->max_sentries, hca_max_sentries);\r
- return HH_E2BIG_SG_NUM;\r
- }\r
-\r
- /* Compute RQ WQE requirements */\r
- wqe_base_sz= WQE_SEG_SZ_NEXT + WQE_SEG_SZ_CTRL; \r
- wqe_sz= wqe_base_sz + (new_srq->max_sentries * WQE_SEG_SZ_SG_ENTRY);\r
- if (wqe_sz > MAX_WQE_SZ) {\r
- MTL_ERROR2(\r
- MT_FLFMT("required SRQ capabilities (max_sentries=%d) require a too large WQE (%u bytes)"),\r
- new_srq->max_sentries, wqe_sz);\r
- return HH_E2BIG_SG_NUM;\r
- }\r
- new_srq->log2_max_wqe_sz= ceil_log2(wqe_sz); /* Align to next power of 2 */\r
- /* A WQE must be aligned to 64B (WQE_ALIGN_SHIFT) so we take at least this size */\r
- if (new_srq->log2_max_wqe_sz < WQE_ALIGN_SHIFT) \r
- new_srq->log2_max_wqe_sz= WQE_ALIGN_SHIFT;\r
- \r
- wqe_sz= (1 << new_srq->log2_max_wqe_sz);\r
- MTL_DEBUG4(MT_FLFMT("%s: Allocating SRQ WQE of size %d."), __func__, wqe_sz);\r
- \r
- /* Compute real number of s/g entries based on rounded up WQE size */\r
- new_srq->max_sentries= (wqe_sz - wqe_base_sz) / WQE_SEG_SZ_SG_ENTRY; \r
- /* Make sure we do not exceed reported HCA cap. */\r
- new_srq->max_sentries= (new_srq->max_sentries > hca_max_sentries) ? \r
- hca_max_sentries : new_srq->max_sentries;\r
- \r
- return HH_OK;\r
-}\r
-\r
-\r
-/* Allocate the WQEs buffer for sendQ and recvQ */\r
-/* This function should be invoked after queue properties are set by alloc_init_qp */\r
-static HH_ret_t alloc_wqe_buf(\r
- /*IN*/ MT_bool in_ddr_mem, /* Allocation of WQEs buffer is requested in attached DDR mem. */\r
- /*IN*/ u_int32_t hca_max_outs, /* HCA cap. */\r
- /*IN*/ u_int32_t req_max_outs, /* Requested capabilities */\r
- /*IN*/ u_int8_t log2_max_wqe_sz,\r
- /*OUT*/ THHUL_srq_wqe_buf_t **buf_pp,\r
- /*OUT*/ THH_srq_ul_resources_t *srq_ul_resources_p\r
-)\r
-{\r
- u_int32_t wqe_sz= 1 << log2_max_wqe_sz;\r
- u_int32_t buf_sz= req_max_outs << log2_max_wqe_sz;\r
- THHUL_srq_wqe_buf_t *new_buf_p;\r
-\r
- /* Check requested capabilities */\r
- if ((req_max_outs == 0) || (req_max_outs > hca_max_outs)) {\r
- MTL_ERROR3(MT_FLFMT("%s: Got a request for a SRQ with %u WQEs - rejecting !"), __func__,\r
- req_max_outs);\r
- return HH_E2BIG_WR_NUM;\r
- }\r
-\r
- new_buf_p= TMALLOC(THHUL_srq_wqe_buf_t);\r
- if (new_buf_p == NULL) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed allocating new WQEs buffer context"), __func__);\r
- return HH_EAGAIN;\r
- }\r
- \r
- if (in_ddr_mem) { /* Allocate WQEs buffer by THH_srqm in the attached DDR memory */\r
- new_buf_p->wqe_buf_orig= NULL;\r
- srq_ul_resources_p->wqes_buf= 0; /* Allocate in attached DDR memory */\r
- } else { /* Allocate WQEs buffer in main memory */\r
- /* Assure the buffer covers whole pages (no sharing of locked memory with other date) */\r
- new_buf_p->wqe_buf_orig_size = \r
- (MOSAL_SYS_PAGE_SIZE-1)/* For alignment */+MT_UP_ALIGNX_U32(buf_sz, MOSAL_SYS_PAGE_SHIFT);\r
- /* Prevent other data reside in the last page of the buffer... */\r
- /* cover last page (last WQE can be at last page begin and its size is 64B min.)*/\r
-\r
- new_buf_p->wqe_buf_orig= srqm_malloc_within_4GB(new_buf_p->wqe_buf_orig_size,&new_buf_p->used_virt_alloc);\r
- if (new_buf_p->wqe_buf_orig == NULL) {\r
- MTL_ERROR2(MT_FLFMT("%s: Failed allocation of WQEs buffer of "SIZE_T_FMT" bytes within "\r
- "4GB boundries."), __func__, new_buf_p->wqe_buf_orig_size);\r
- FREE(new_buf_p);\r
- return HH_EAGAIN;\r
- }\r
- \r
- /* Page alignment assures that the WQE buffer is aligned to WQE size.\r
- * In addition, after resizing the SRQ the new wqe_buf has the same alignment\r
- * in the page (to retain original virtual addresses) \r
- */\r
- new_buf_p->wqe_buf= MT_UP_ALIGNX_VIRT((MT_virt_addr_t)(new_buf_p->wqe_buf_orig),\r
- MOSAL_SYS_PAGE_SHIFT);\r
- \r
- srq_ul_resources_p->wqes_buf= new_buf_p->wqe_buf;\r
- }\r
- new_buf_p->max_outs= req_max_outs; /* Allocated exactly as requested */\r
-\r
- srq_ul_resources_p->wqes_buf_sz= buf_sz;\r
- srq_ul_resources_p->wqe_sz= wqe_sz;\r
- \r
- *buf_pp= new_buf_p;\r
- return HH_OK;\r
-}\r
-\r
-static void free_wqe_buf(THHUL_srq_wqe_buf_t *buf_p)\r
-{\r
- if (buf_p->wqe_buf_orig != NULL) {/* WQEs buffer were allocated in process mem. */ \r
- if (buf_p->used_virt_alloc) \r
- MOSAL_pci_virt_free_consistent(buf_p->wqe_buf_orig, buf_p->wqe_buf_orig_size);\r
- else\r
- MOSAL_pci_phys_free_consistent(buf_p->wqe_buf_orig, buf_p->wqe_buf_orig_size); \r
- }\r
- FREE(buf_p);\r
-}\r
-\r
-/* Append WQEs buffer extention to WQEs free list */\r
-/* Must be invoked with SRQ lock held */\r
-static void append_to_free_list(\r
- /*IN*/ THHUL_srq_t srq,\r
- /*IN*/ MT_virt_addr_t wqes_buf_extention, /* The part of the new WQEs buf above old part */\r
- /*IN*/ MT_size_t extention_sz_in_wqes /* Extention size in WQEs */\r
-)\r
-{\r
- u_int32_t i;\r
- MT_virt_addr_t cur_wqe;\r
- const u_int32_t wqe_sz= 1<<srq->log2_max_wqe_sz;\r
-\r
- MTL_TRACE2(\r
- MT_FLFMT("%s(srq=%p SRQn=0x%X , wqe_buf_extention="VIRT_ADDR_FMT\r
- ", extention_sz_in_wqes="SIZE_T_DFMT),\r
- __func__, srq, srq->srqn, wqes_buf_extention, extention_sz_in_wqes);\r
- /* Create free WQEs list of wqe_buf */\r
- for (i= 0 , cur_wqe= wqes_buf_extention; i < extention_sz_in_wqes; i++) {\r
- *((MT_virt_addr_t*)cur_wqe)= srq->free_wqes_list; /* Link WQE to first in free list */\r
- srq->free_wqes_list= cur_wqe - srq->real_virt_offset; /* Put as first in free list */\r
- /* Note that real_virt_offset reduction puts in the free_list the next virt in HCA's space */\r
- MTL_DEBUG4(MT_FLFMT("%s: Added srq->free_wqes_list a WQE at "VIRT_ADDR_FMT),__func__,\r
- srq->free_wqes_list);\r
- cur_wqe+= wqe_sz; \r
- }\r
-}\r
-\r
-/* Allocate the auxilary WQEs data \r
- * (a software context of a WQE which does not have to be in the registered WQEs buffer) */\r
-static HH_ret_t alloc_aux_data_buf(\r
- /*IN/OUT*/ THHUL_srq_t new_srq\r
-)\r
-{\r
- /* RQ auxilary buffer: WQE ID per WQE */ \r
- new_srq->wqe_id= (VAPI_wr_id_t*)\r
- THH_SMART_MALLOC(new_srq->cur_buf_p->max_outs * sizeof(VAPI_wr_id_t)); \r
- if (new_srq->wqe_id == NULL) {\r
- MTL_ERROR1(MT_FLFMT("%s: Failed allocating SRQ auxilary buffer (for 0x%X WQEs IDs)."), __func__,\r
- new_srq->cur_buf_p->max_outs);\r
- return HH_EAGAIN;\r
- }\r
- \r
- return HH_OK;\r
-}\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_THHUL_SRQM_H\r
-#define H_THHUL_SRQM_H\r
-\r
-#include <thhul.h>\r
-\r
-\r
-HH_ret_t THHUL_srqm_create( \r
- THHUL_hob_t hob, \r
- THHUL_srqm_t *srqm_p \r
-);\r
-\r
-\r
-HH_ret_t THHUL_srqm_destroy( \r
- THHUL_srqm_t srqm \r
-); \r
-\r
-HH_ret_t THHUL_srqm_create_srq_prep( \r
- /*IN*/\r
- HHUL_hca_hndl_t hca, \r
- HHUL_pd_hndl_t pd,\r
- u_int32_t max_outs,\r
- u_int32_t max_sentries,\r
- /*OUT*/\r
- HHUL_srq_hndl_t *srq_hndl_p,\r
- u_int32_t *actual_max_outs_p,\r
- u_int32_t *actual_max_sentries_p,\r
- void /*THH_srq_ul_resources_t*/ *srq_ul_resources_p \r
-);\r
-\r
-HH_ret_t THHUL_srqm_create_srq_done( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_srq_hndl_t hhul_srq, \r
- HH_srq_hndl_t hh_srq, \r
- void/*THH_srq_ul_resources_t*/ *srq_ul_resources_p\r
-);\r
-\r
-HH_ret_t THHUL_srqm_modify_srq_prep(\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/HHUL_srq_hndl_t hhul_srq,\r
- /*IN*/VAPI_srq_attr_t *srq_attr_p,\r
- /*IN*/VAPI_srq_attr_mask_t srq_attr_mask,\r
- /*OUT*/void/*THH_srq_ul_resources_t*/ *srq_ul_resources_p\r
-);\r
-\r
-HH_ret_t THHUL_srqm_modify_srq_done( \r
- /*IN*/HHUL_hca_hndl_t hca, \r
- /*IN*/HHUL_srq_hndl_t hhul_srq, \r
- /*IN*/void/*THH_srq_ul_resources_t*/ *srq_ul_resources_p,\r
- /*OUT*/u_int32_t *max_outs_wr_p /* Max. outstanding WQEs */\r
-); \r
-\r
-HH_ret_t THHUL_srqm_destroy_srq_done( \r
- HHUL_hca_hndl_t hca, \r
- HHUL_qp_hndl_t hhul_srq \r
-);\r
-\r
-HH_ret_t THHUL_srqm_post_recv_reqs(\r
- /*IN*/ HHUL_hca_hndl_t hca, \r
- /*IN*/ HHUL_srq_hndl_t hhul_srq, \r
- /*IN*/ u_int32_t num_of_requests,\r
- /*IN*/ VAPI_rr_desc_t *recv_req_array,\r
- /*OUT*/ u_int32_t *posted_requests_p\r
- );\r
-\r
-/* Release this WQE only and return its WQE ID */\r
-HH_ret_t THHUL_srqm_comp( \r
- THHUL_srqm_t srqm, \r
- HHUL_srq_hndl_t hhul_srq,\r
- u_int32_t wqe_addr_32lsb, \r
- VAPI_wr_id_t *wqe_id_p\r
-);\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#define C_UAR_C\r
-#include "uar.h"\r
-#include <MT23108.h>\r
-\r
-#if 0 // move to uar.h\r
-struct THH_uar_st {\r
- THH_ver_info_t ver_info;\r
- THH_uar_index_t uar_index;\r
- volatile u_int32_t *uar_base;\r
- MOSAL_spinlock_t uar_lock;\r
-} /* *THH_uar_t */;\r
-\r
-/* Doorbells dword offsets */\r
-#define UAR_RD_SEND_DBELL_OFFSET (MT_BYTE_OFFSET(tavorprm_uar_st,rd_send_doorbell)>>2)\r
-#define UAR_SEND_DBELL_OFFSET (MT_BYTE_OFFSET(tavorprm_uar_st,send_doorbell)>>2)\r
-#define UAR_RECV_DBELL_OFFSET (MT_BYTE_OFFSET(tavorprm_uar_st,receive_doorbell)>>2)\r
-#define UAR_CQ_DBELL_OFFSET (MT_BYTE_OFFSET(tavorprm_uar_st,cq_command_doorbell)>>2)\r
-#define UAR_EQ_DBELL_OFFSET (MT_BYTE_OFFSET(tavorprm_uar_st,eq_command_doorbell)>>2)\r
-/* Doorbells dword offsets */\r
-#define UAR_RD_SEND_DBELL_SZ (MT_BYTE_SIZE(tavorprm_uar_st,rd_send_doorbell)>>2)\r
-#define UAR_SEND_DBELL_SZ (MT_BYTE_SIZE(tavorprm_uar_st,send_doorbell)>>2)\r
-#define UAR_RECV_DBELL_SZ (MT_BYTE_SIZE(tavorprm_uar_st,receive_doorbell)>>2)\r
-#define UAR_CQ_DBELL_SZ (MT_BYTE_SIZE(tavorprm_uar_st,cq_command_doorbell)>>2)\r
-#define UAR_EQ_DBELL_SZ (MT_BYTE_SIZE(tavorprm_uar_st,eq_command_doorbell)>>2)\r
-#endif\r
-\r
-/* doorbell ringing for 2 dwords */\r
-#ifdef __MOSAL_MMAP_IO_WRITE_QWORD_ATOMIC__\r
-/* If Qword write is assured to be atomic (MMX or a 64-bit arch) - no need for the spinlock */\r
-#define RING_DBELL_2DW(uar,dword_offset,dbell_draft) \\r
- dbell_draft[0]= MOSAL_cpu_to_be32(dbell_draft[0]); \\r
- dbell_draft[1]= MOSAL_cpu_to_be32(dbell_draft[1]); \\r
- MOSAL_MMAP_IO_WRITE_QWORD(uar->uar_base+dword_offset,*(volatile u_int64_t*)dbell_draft); \r
-#else\r
-#define RING_DBELL_2DW(uar,dword_offset,dbell_draft) \\r
- MOSAL_spinlock_dpc_lock(&(uar->uar_lock)); \\r
- MOSAL_MMAP_IO_WRITE_DWORD(uar->uar_base+dword_offset,MOSAL_cpu_to_be32(dbell_draft[0])); \\r
- MOSAL_MMAP_IO_WRITE_DWORD(uar->uar_base+dword_offset+1,MOSAL_cpu_to_be32(dbell_draft[1])); \\r
- MOSAL_spinlock_unlock(&(uar->uar_lock));\r
-#endif /* Atomic Qword write */\r
-\r
-#define RING_DBELL_4DW(uar,dword_offset,dbell_draft) \\r
- dbell_draft[0]= MOSAL_cpu_to_be32(dbell_draft[0]); \\r
- dbell_draft[1]= MOSAL_cpu_to_be32(dbell_draft[1]); \\r
- dbell_draft[2]= MOSAL_cpu_to_be32(dbell_draft[2]); \\r
- dbell_draft[3]= MOSAL_cpu_to_be32(dbell_draft[3]); \\r
- MOSAL_spinlock_dpc_lock(&(uar->uar_lock)); \\r
- MOSAL_MMAP_IO_WRITE_QWORD(uar->uar_base+dword_offset,((u_int64_t*)dbell_draft)[0]); \\r
- MOSAL_MMAP_IO_WRITE_QWORD(uar->uar_base+dword_offset+2,((u_int64_t*)dbell_draft)[1]); \\r
- MOSAL_spinlock_unlock(&(uar->uar_lock));\r
-\r
-\r
-\r
-/************************************************************************/\r
-/* Public functions */ \r
-/************************************************************************/\r
-\r
-HH_ret_t THH_uar_create(\r
- /*IN*/ THH_ver_info_t *version_p, \r
- /*IN*/ THH_uar_index_t uar_index, \r
- /*IN*/ void *uar_base, \r
- /*OUT*/ THH_uar_t *uar_p\r
-)\r
-{\r
- THH_uar_t new_uar;\r
-\r
- new_uar= (THH_uar_t)MALLOC(sizeof(struct THH_uar_st));\r
- if (new_uar == NULL) {\r
- MTL_ERROR1("THH_uar_create: Failed allocating object memory.\n");\r
- return HH_EAGAIN;\r
- }\r
- new_uar->uar_index= uar_index;\r
- new_uar->uar_base= (volatile u_int32_t*)uar_base;\r
- memcpy(&(new_uar->ver_info),version_p,sizeof(THH_ver_info_t));\r
- MOSAL_spinlock_init(&(new_uar->uar_lock));\r
- \r
- *uar_p= new_uar;\r
- return HH_OK;\r
-} /* THH_uar_create */\r
-\r
-\r
-HH_ret_t THH_uar_destroy(THH_uar_t uar /* IN */)\r
-{\r
- FREE(uar);\r
- return HH_OK;\r
-} /* THH_uar_destroy */\r
-\r
-\r
-HH_ret_t THH_uar_get_index(\r
- /*IN*/ THH_uar_t uar, \r
- /*OUT*/ THH_uar_index_t *uar_index_p\r
-)\r
-{\r
- if (uar == NULL) return HH_EINVAL;\r
- *uar_index_p= uar->uar_index;\r
- return HH_OK;\r
-}\r
-\r
-\r
-HH_ret_t THH_uar_sendq_dbell(\r
- THH_uar_t uar, /* IN */\r
- THH_uar_sendq_dbell_t* sendq_dbell_p /* IN */ )\r
-{\r
- volatile u_int32_t dbell_draft[UAR_SEND_DBELL_SZ]= {0};\r
-\r
-// MTL_DEBUG4(MT_FLFMT("SendQ Dbell: qpn=0x%X nda=0x%X nds=0x%X nopcode=0x%X"),\r
-// sendq_dbell_p->qpn, sendq_dbell_p->next_addr_32lsb,\r
-// sendq_dbell_p->next_size, sendq_dbell_p->nopcode);\r
-\r
- dbell_draft[MT_BYTE_OFFSET(tavorprm_send_doorbell_st,nda)>>2]=\r
- sendq_dbell_p->next_addr_32lsb; /* 6 ls-bits will be masked anyway by f and nopcode */\r
- MT_INSERT_ARRAY32(dbell_draft, sendq_dbell_p->fence ? 1 : 0,\r
- MT_BIT_OFFSET(tavorprm_send_doorbell_st,f),\r
- MT_BIT_SIZE(tavorprm_send_doorbell_st,f));\r
- MT_INSERT_ARRAY32(dbell_draft, sendq_dbell_p->nopcode,\r
- MT_BIT_OFFSET(tavorprm_send_doorbell_st,nopcode),\r
- MT_BIT_SIZE(tavorprm_send_doorbell_st,nopcode));\r
- MT_INSERT_ARRAY32(dbell_draft, sendq_dbell_p->qpn,\r
- MT_BIT_OFFSET(tavorprm_send_doorbell_st,qpn),\r
- MT_BIT_SIZE(tavorprm_send_doorbell_st,qpn));\r
- MT_INSERT_ARRAY32(dbell_draft, sendq_dbell_p->next_size,\r
- MT_BIT_OFFSET(tavorprm_send_doorbell_st,nds),\r
- MT_BIT_SIZE(tavorprm_send_doorbell_st,nds));\r
-\r
- RING_DBELL_2DW(uar,UAR_SEND_DBELL_OFFSET,dbell_draft);\r
-\r
- return HH_OK;\r
-} /* THH_uar_sendq_dbell */\r
-\r
-\r
-HH_ret_t THH_uar_sendq_rd_dbell(\r
- THH_uar_t uar, /* IN */\r
- THH_uar_sendq_dbell_t* sendq_dbell_p, /* IN */\r
- IB_eecn_t een /* IN */)\r
-{\r
- volatile u_int32_t dbell_draft[UAR_RD_SEND_DBELL_SZ]= {0};\r
- \r
- MT_INSERT_ARRAY32(dbell_draft, een,\r
- MT_BIT_OFFSET(tavorprm_rd_send_doorbell_st,een),\r
- MT_BIT_SIZE(tavorprm_rd_send_doorbell_st,qpn));\r
- MT_INSERT_ARRAY32(dbell_draft, sendq_dbell_p->qpn,\r
- MT_BIT_OFFSET(tavorprm_rd_send_doorbell_st,qpn),\r
- MT_BIT_SIZE(tavorprm_rd_send_doorbell_st,qpn));\r
- dbell_draft[MT_BYTE_OFFSET(tavorprm_rd_send_doorbell_st,snd_params.nda)>>2]=\r
- sendq_dbell_p->next_addr_32lsb; /* 6 ls-bits will be masked anyway by f and nopcode */\r
- MT_INSERT_ARRAY32(dbell_draft, sendq_dbell_p->fence ? 1 : 0,\r
- MT_BIT_OFFSET(tavorprm_rd_send_doorbell_st,snd_params.f),\r
- MT_BIT_SIZE(tavorprm_rd_send_doorbell_st,snd_params.f));\r
- MT_INSERT_ARRAY32(dbell_draft, sendq_dbell_p->nopcode,\r
- MT_BIT_OFFSET(tavorprm_rd_send_doorbell_st,snd_params.nopcode),\r
- MT_BIT_SIZE(tavorprm_rd_send_doorbell_st,snd_params.nopcode));\r
- MT_INSERT_ARRAY32(dbell_draft, sendq_dbell_p->qpn,\r
- MT_BIT_OFFSET(tavorprm_rd_send_doorbell_st,snd_params.qpn),\r
- MT_BIT_SIZE(tavorprm_rd_send_doorbell_st,snd_params.qpn));\r
- MT_INSERT_ARRAY32(dbell_draft, sendq_dbell_p->next_size,\r
- MT_BIT_OFFSET(tavorprm_rd_send_doorbell_st,snd_params.nds),\r
- MT_BIT_SIZE(tavorprm_rd_send_doorbell_st,snd_params.nds));\r
-\r
- RING_DBELL_4DW(uar,UAR_RD_SEND_DBELL_OFFSET,dbell_draft);\r
-\r
- return HH_OK;\r
-} /* THH_uar_sendq_rd_dbell */\r
-\r
-\r
-HH_ret_t THH_uar_recvq_dbell(\r
- THH_uar_t uar, /* IN */\r
- THH_uar_recvq_dbell_t* recvq_dbell_p /* IN */)\r
-{\r
- volatile u_int32_t dbell_draft[UAR_RECV_DBELL_SZ]= {0};\r
- \r
- /* nda field in the Doorbell is actually nda[31:6] - so we must shift it right before inse*/\r
- dbell_draft[MT_BYTE_OFFSET(tavorprm_receive_doorbell_st,nda) >> 2]= \r
- ( recvq_dbell_p->next_addr_32lsb & (~MASK32(6)) ) |\r
- ( recvq_dbell_p->next_size & MASK32(6) );\r
- dbell_draft[MT_BYTE_OFFSET(tavorprm_receive_doorbell_st,qpn) >> 2]= \r
- ( recvq_dbell_p->qpn << (MT_BIT_OFFSET(tavorprm_receive_doorbell_st,qpn) & MASK32(5)) ) |\r
- recvq_dbell_p->credits;\r
-\r
- RING_DBELL_2DW(uar,UAR_RECV_DBELL_OFFSET,dbell_draft);\r
-\r
- return HH_OK;\r
-} /* THH_uar_recvq_dbell */\r
-\r
-\r
-HH_ret_t THH_uar_cq_cmd(\r
- THH_uar_t uar, /* IN */\r
- THH_uar_cq_cmd_t cmd, /* IN */\r
- HH_cq_hndl_t cqn, /* IN */\r
- u_int32_t param /* IN */)\r
-{\r
- volatile u_int32_t dbell_draft[UAR_CQ_DBELL_SZ]= {0};\r
- \r
- MT_INSERT_ARRAY32(dbell_draft, cmd,\r
- MT_BIT_OFFSET(tavorprm_cq_cmd_doorbell_st,cq_cmd),\r
- MT_BIT_SIZE(tavorprm_cq_cmd_doorbell_st,cq_cmd));\r
- MT_INSERT_ARRAY32(dbell_draft, cqn,\r
- MT_BIT_OFFSET(tavorprm_cq_cmd_doorbell_st,cqn),\r
- MT_BIT_SIZE(tavorprm_cq_cmd_doorbell_st,cqn));\r
- MT_INSERT_ARRAY32(dbell_draft, param,\r
- MT_BIT_OFFSET(tavorprm_cq_cmd_doorbell_st,cq_param),\r
- MT_BIT_SIZE(tavorprm_cq_cmd_doorbell_st,cq_param));\r
-\r
- RING_DBELL_2DW(uar,UAR_CQ_DBELL_OFFSET,dbell_draft);\r
-\r
- return HH_OK;\r
-} /* THH_uar_cq_cmd */\r
-\r
-\r
-HH_ret_t THH_uar_eq_cmd(\r
- THH_uar_t uar, /* IN */\r
- THH_uar_eq_cmd_t cmd, /* IN */\r
- THH_eqn_t eqn, /* IN */\r
- u_int32_t param /* IN */)\r
-{\r
- volatile u_int32_t dbell_draft[UAR_EQ_DBELL_SZ]= {0};\r
- \r
- MT_INSERT_ARRAY32(dbell_draft, cmd,\r
- MT_BIT_OFFSET(tavorprm_eq_cmd_doorbell_st,eq_cmd),\r
- MT_BIT_SIZE(tavorprm_eq_cmd_doorbell_st,eq_cmd));\r
- MT_INSERT_ARRAY32(dbell_draft, eqn,\r
- MT_BIT_OFFSET(tavorprm_eq_cmd_doorbell_st,eqn),\r
- MT_BIT_SIZE(tavorprm_eq_cmd_doorbell_st,eqn));\r
- MT_INSERT_ARRAY32(dbell_draft, param,\r
- MT_BIT_OFFSET(tavorprm_eq_cmd_doorbell_st,eq_param),\r
- MT_BIT_SIZE(tavorprm_eq_cmd_doorbell_st,eq_param));\r
-#if 2 <= MAX_DEBUG\r
- { u_int32_t i;\r
- for (i=0;i<UAR_EQ_DBELL_SZ;i=+2) {\r
- MTL_DEBUG2("%s EQ DB: %08X %08X \n", __func__, dbell_draft[i],dbell_draft[i+1] ); \r
- }\r
- }\r
-#endif\r
- RING_DBELL_2DW(uar,UAR_EQ_DBELL_OFFSET,dbell_draft);\r
-\r
- return HH_OK;\r
-} /* THH_uar_eq_cmd */\r
-\r
-\r
-HH_ret_t THH_uar_blast( \r
- THH_uar_t uar, /* IN */\r
- void* wqe_p, /* IN */\r
- MT_size_t wqe_sz, /* IN */\r
- THH_uar_sendq_dbell_t *sendq_dbell_p, /* IN */\r
- IB_eecn_t een /* IN */)\r
-{\r
- return HH_ENOSYS; /* Not supported */\r
-} /* THH_uar_bf */\r
-\r
-\r
- \r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_UAR_H\r
-#define H_UAR_H\r
-\r
-#include <mtl_common.h>\r
-#include <ib_defs.h>\r
-#include <vapi_types.h>\r
-#include <mosal.h>\r
-#include <hh.h>\r
-#include <thh_common.h>\r
-#include <tavor_if_defs.h>\r
-\r
-\r
-\r
-typedef struct {\r
- \r
- IB_wqpn_t qpn; /* QP number */\r
- tavor_if_nopcode_t nopcode; /* Next Send descriptor opcode (encoded) */\r
- MT_bool fence; /* Fence bit set */\r
- u_int32_t next_addr_32lsb; /* Address of next WQE (the one linked) */\r
- u_int32_t next_size ; /* Size of next WQE (16-byte chunks) */\r
-\r
-} THH_uar_sendq_dbell_t;\r
-\r
-typedef struct {\r
- \r
- IB_wqpn_t qpn; /* QP number */\r
- u_int32_t next_addr_32lsb; /* Address of next WQE (the one linked) */\r
- u_int32_t next_size ; /* Size of next WQE (16-byte chunks) */\r
- u_int8_t credits; /* Number of WQEs attached with this doorbell (255 max.) */\r
-\r
-} THH_uar_recvq_dbell_t;\r
-\r
-typedef tavor_if_uar_cq_cmd_t THH_uar_cq_cmd_t;\r
-typedef tavor_if_uar_eq_cmd_t THH_uar_eq_cmd_t;\r
-\r
-struct THH_uar_st {\r
- THH_ver_info_t ver_info;\r
- THH_uar_index_t uar_index;\r
- volatile u_int32_t *uar_base;\r
- MOSAL_spinlock_t uar_lock;\r
-} /* *THH_uar_t */;\r
-\r
-/* Doorbells dword offsets */\r
-#define UAR_RD_SEND_DBELL_OFFSET (MT_BYTE_OFFSET(tavorprm_uar_st,rd_send_doorbell)>>2)\r
-#define UAR_SEND_DBELL_OFFSET (MT_BYTE_OFFSET(tavorprm_uar_st,send_doorbell)>>2)\r
-#define UAR_RECV_DBELL_OFFSET (MT_BYTE_OFFSET(tavorprm_uar_st,receive_doorbell)>>2)\r
-#define UAR_CQ_DBELL_OFFSET (MT_BYTE_OFFSET(tavorprm_uar_st,cq_command_doorbell)>>2)\r
-#define UAR_EQ_DBELL_OFFSET (MT_BYTE_OFFSET(tavorprm_uar_st,eq_command_doorbell)>>2)\r
-/* Doorbells dword offsets */\r
-#define UAR_RD_SEND_DBELL_SZ (MT_BYTE_SIZE(tavorprm_uar_st,rd_send_doorbell)>>2)\r
-#define UAR_SEND_DBELL_SZ (MT_BYTE_SIZE(tavorprm_uar_st,send_doorbell)>>2)\r
-#define UAR_RECV_DBELL_SZ (MT_BYTE_SIZE(tavorprm_uar_st,receive_doorbell)>>2)\r
-#define UAR_CQ_DBELL_SZ (MT_BYTE_SIZE(tavorprm_uar_st,cq_command_doorbell)>>2)\r
-#define UAR_EQ_DBELL_SZ (MT_BYTE_SIZE(tavorprm_uar_st,eq_command_doorbell)>>2)\r
-\r
-/************************************************************************\r
- * Function: THH_uar_create\r
- *\r
- * Arguments:\r
- * version_p \r
- * uar_index\r
- * uar_base - Virtual address mapped to associated UAR\r
- * uar_p - Created THH_uar object handle\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EAGAIN - Not enough resources to create object\r
- * HH_EINVAL - Invalid parameters (NULL ptrs.etc.)\r
- *\r
- * Description: Create the THH_uar object.\r
- */\r
-HH_ret_t THH_uar_create(\r
- /*IN*/ THH_ver_info_t *version_p, \r
- /*IN*/ THH_uar_index_t uar_index, \r
- /*IN*/ void *uar_base, \r
- /*OUT*/ THH_uar_t *uar_p\r
- );\r
-\r
-\r
-/************************************************************************\r
- *\r
- * Function: THH_uar_destroy\r
- *\r
- * Arguments:\r
- * uar - Object handle\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid handle\r
- *\r
- * Description: Free UAR object context.\r
- */\r
-HH_ret_t THH_uar_destroy(/*IN*/ THH_uar_t uar);\r
-\r
-\r
-/************************************************************************\r
- *\r
- * Function: THH_uar_get_index\r
- *\r
- * Arguments:\r
- * uar - Object handle\r
- * uar_index_p - Returned UAR page index of UAR associated with this object\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL \r
- *\r
- * Description: Get associated UAR page index.\r
- */\r
-HH_ret_t THH_uar_get_index(\r
- /*IN*/ THH_uar_t uar, \r
- /*OUT*/ THH_uar_index_t *uar_index_p\r
- );\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_uar_sendq_dbell\r
- *\r
- * Arguments:\r
- * uar - The THH_uar object handle\r
- * sendq_dbell_p - Send queue doorbel data\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL -Invalid handles or NULL pointer\r
- *\r
- * Description:\r
- * Ring the send section of the UAR.\r
- */\r
-HH_ret_t THH_uar_sendq_dbell(\r
- /*IN*/ THH_uar_t uar, \r
- /*IN*/ THH_uar_sendq_dbell_t* sendq_dbell_p\r
- );\r
-\r
-#define SEND_DBELL_NDA_BYTE_OFFSET (MT_BYTE_OFFSET(tavorprm_send_doorbell_st,nda)>>2)\r
-#define SEND_DBELL_QPN_BYTE_OFFSET (MT_BYTE_OFFSET(tavorprm_send_doorbell_st,qpn)>>2)\r
-#define SEND_DBELL_F_BIT_OFFSET (MT_BIT_OFFSET(tavorprm_send_doorbell_st,f) & 0x1f)\r
-#define SEND_DBELL_QPN_BIT_OFFSET (MT_BIT_OFFSET(tavorprm_send_doorbell_st,qpn) & 0x1f)\r
-#define SEND_DBELL_NEXT_ADDR_BIT_MASK (~MASK32(6))\r
-#define SEND_DBELL_NOPCODE_BIT_MASK (MASK32(MT_BIT_SIZE(tavorprm_send_doorbell_st,nopcode)))\r
-#define SEND_DBELL_NDA_BIT_MASK (MASK32(MT_BIT_SIZE(tavorprm_send_doorbell_st,nds)))\r
-\r
-/************************************************************************\r
- * Function: THH_uar_sendq_rd_dbell\r
- *\r
- * Arguments:\r
- * uar - The THH_uar object handle\r
- * sendq_dbell_p - Send queue doorbell data\r
- * een - The EE context number for posted request\r
- *\r
- * Returns:\r
- * HH_OK HH_EINVAL -Invalid handles or NULL pointer\r
- * Description:\r
- * Ring the rdd-send section of the UAR.\r
- */\r
-HH_ret_t THH_uar_sendq_rd_dbell(\r
- /*IN*/ THH_uar_t uar, \r
- /*IN*/ THH_uar_sendq_dbell_t* sendq_dbell_p, \r
- /*IN*/ IB_eecn_t een \r
- );\r
-\r
-#define SEND_RD_DBELL_EEN_BYTE_OFFSET (MT_BYTE_OFFSET(tavorprm_rd_send_doorbell_st,een) >> 2)\r
-#define SEND_RD_DBELL_QPN_BYTE_OFFSET (MT_BYTE_OFFSET(tavorprm_rd_send_doorbell_st,qpn) >> 2)\r
-#define SEND_RD_DBELL_NDA_PARAM_BYTE_OFFSET (MT_BYTE_OFFSET(tavorprm_rd_send_doorbell_st,snd_params.nda)>>2)\r
-#define SEND_RD_DBELL_QPN_PARAM_BYTE_OFFSET (MT_BYTE_OFFSET(tavorprm_rd_send_doorbell_st,snd_params.qpn)>>2)\r
-#define SEND_RD_DBELL_EEN_BIT_OFFSET (MT_BIT_OFFSET(tavorprm_rd_send_doorbell_st,een) & 0x1f)\r
-#define SEND_RD_DBELL_QPN_BIT_OFFSET (MT_BIT_OFFSET(tavorprm_rd_send_doorbell_st,qpn) & 0x1f)\r
-\r
-#define THH_UAR_SENDQ_RD_DBELL(uar,dbell_draft,next_addr,next_size,fence,nopcode,qpn,een) \\r
- dbell_draft[SEND_RD_DBELL_EEN_BYTE_OFFSET] = MOSAL_cpu_to_be32( \\r
- een <<SEND_RD_DBELL_EEN_BIT_OFFSET); \\r
- dbell_draft[SEND_RD_DBELL_QPN_BYTE_OFFSET] = MOSAL_cpu_to_be32( \\r
- qpn << SEND_RD_DBELL_QPN_BIT_OFFSET); \\r
- dbell_draft[SEND_RD_DBELL_NDA_PARAM_BYTE_OFFSET] = MOSAL_cpu_to_be32( \\r
- (next_addr & SEND_DBELL_NEXT_ADDR_BIT_MASK) | \\r
- ((fence & 0x1) << SEND_DOORBELL_F_BIT_OFFSET)| \\r
- (nopcode & SEND_DBELL_NOPCODE_BIT_MASK) ); \\r
- dbell_draft[SEND_RD_DBELL_QPN_PARAM_BYTE_OFFSET] = MOSAL_cpu_to_be32( \\r
- (next_size & SEND_DBELL_NDA_BIT_MASK) | \\r
- (qpn << SEND_DBELL_QPN_BIT_OFFSET)); \\r
- RING_DBELL_4DW_BE(uar,UAR_RD_SEND_DBELL_OFFSET,dbell_draft); \r
-\r
-/************************************************************************\r
- * Function: THH_uar_recvq_dbell\r
- *\r
- * Arguments:\r
- * uar - The THH_uar object handle\r
- * recvq_dbell_p - Receive queue doorbell data\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL -Invalid handles\r
- *\r
- * Description:\r
- * Ring the receive section of the UAR for posting receive WQEs..\r
- */\r
-HH_ret_t THH_uar_recvq_dbell(\r
- /*IN*/ THH_uar_t uar, \r
- /*IN*/ THH_uar_recvq_dbell_t* recvq_dbell_p \r
- );\r
-\r
-#define RECV_DBELL_NDA_BYTE_OFFSET (MT_BYTE_OFFSET(tavorprm_receive_doorbell_st,nda) >> 2)\r
-#define RECV_DBELL_QPN_BYTE_OFFSET (MT_BYTE_OFFSET(tavorprm_receive_doorbell_st,qpn) >> 2)\r
-#define RECV_DBELL_QPN_BIT_SHIFT (MT_BIT_OFFSET(tavorprm_receive_doorbell_st,qpn) & MASK32(5))\r
-#define RECV_DBELL_NEXT_ADDR_BIT_MASK (~MASK32(6))\r
-#define RECV_DBELL_NEXT_SIZE_BIT_MASK (MASK32(6))\r
-\r
-/************************************************************************\r
- * Function: THH_uar_cq_cmd\r
- *\r
- * Arguments:\r
- * uar - The THH_uar object handle\r
- * cmd - The CQ command code\r
- * cqn - The CQC index of the CQ to perform command on\r
- * param - The 32 bit parameter (local CPU endianess)\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL -Invalid handles\r
- *\r
- * Description:\r
- * Invoke a CQ context update through the CQ_cmd section of the UAR.\r
- */\r
-HH_ret_t THH_uar_cq_cmd(\r
- THH_uar_t uar, /* IN */\r
- THH_uar_cq_cmd_t cmd, /* IN */\r
- HH_cq_hndl_t cqn, /* IN */\r
- u_int32_t param /* IN */);\r
-\r
-#define CQ_CMD_DBELL_BYTE_OFFSET (MT_BYTE_OFFSET(tavorprm_cq_cmd_doorbell_st,cq_cmd) >> 2)\r
-#define CQ_PARAM_DBELL_BYTE_OFFSET (MT_BYTE_OFFSET(tavorprm_cq_cmd_doorbell_st,cq_param) >> 2)\r
-#define CQ_CMD_DBELL_BIT_OFFSET (MT_BIT_OFFSET(tavorprm_cq_cmd_doorbell_st,cq_cmd))\r
-\r
-/************************************************************************\r
- * Function: THH_uar_eq_cmd\r
- *\r
- * Arguments:\r
- * uar - The THH_uar object handle\r
- * cmd - The EQ command code\r
- * eqn - The EQC index of the CQ to perform command on\r
- * param - The 32 bit parameter\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL -Invalid handles\r
- *\r
- * Description:\r
- * Invoke a EQ context update through the EQ_cmd section of the UAR.\r
- */\r
-HH_ret_t THH_uar_eq_cmd(\r
- THH_uar_t uar, /* IN */\r
- THH_uar_eq_cmd_t cmd, /* IN */\r
- THH_eqn_t eqn, /* IN */\r
- u_int32_t param /* IN */);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_uar_blast\r
- *\r
- * Arguments:\r
- * uar - The THH_uar object handle\r
- * wqe_p - A pointer to the WQE structure to push to the "flame"\r
- * wqe_sz - WQE size\r
- * sendq_dbell_p Send queue doorbell data\r
- * een The EE context number for posted request (valid for RD-send)\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid handles or NULL pointer\r
- *\r
- * Description:\r
- *\r
- * This function pushes the given WQE descriptor to the InfiniBlast(tm)\r
- * buffer through the infini_blast section of the UAR, and then rings the\r
- * "send" doorbell (in order to assure atomicity between the writing of the \r
- * InfiniBlast buffer and the ringing of the "send" doorbell.\r
- * If given een is valid (0-0xFFFFFF) the "rd-send" doorbell is used.\r
- */\r
-HH_ret_t THH_uar_blast(\r
- THH_uar_t uar, /* IN */\r
- void* wqe_p, /* IN */\r
- MT_size_t wqe_sz, /* IN */\r
- THH_uar_sendq_dbell_t *sendq_dbell_p, /* IN */\r
- IB_eecn_t een /* IN */\r
-);\r
-\r
-#endif /* H_UAR_H */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include <mosal.h>\r
-#include <MT23108.h>\r
-#include <udavm.h>\r
-#include <epool.h>\r
-#include <tlog2.h>\r
-#include <vip_array.h>\r
-#include <vip_common.h>\r
-\r
-#define UD_AV_ENTRY_SIZE (sizeof(struct tavorprm_ud_address_vector_st) / 8)\r
-#define UD_AV_ENTRY_DWORD_SIZE (sizeof(struct tavorprm_ud_address_vector_st) / 32)\r
-#define UD_AV_ENTRY_SIZE_LOG2 5\r
-#define UD_AV_ALIGNMENT_MASK (UD_AV_ENTRY_SIZE - 1)\r
-/*================ macro definitions ===============================================*/\r
-/* check that ud_av_p is in the av table range and that it is aligned to entry size */\r
-#define IS_INVALID_AV_MEMBER(udavm, ud_av_p) \\r
- (((ud_av_p) < udavm->ud_av_table) || \\r
- (((MT_virt_addr_t)ud_av_p) >= ((MT_virt_addr_t)(udavm->ud_av_table))+(udavm->ud_av_table_sz)) )\r
-#define IS_INVALID_AV_ALIGN(ud_av_p) \\r
- (((MT_virt_addr_t)(ud_av_p)) & UD_AV_ALIGNMENT_MASK)\r
-\r
-#define IS_INVALID_AV(udavm, ud_av_host_p) \\r
- (((ud_av_host_p) < udavm->ud_av_table_host) || \\r
- (((MT_ulong_ptr_t)ud_av_host_p) >= ((MT_ulong_ptr_t)(udavm->ud_av_table_host))+(udavm->ud_av_table_sz)) || \\r
- (((((MT_ulong_ptr_t)udavm->ud_av_table_host) - ((MT_ulong_ptr_t)(ud_av_host_p))) & UD_AV_ALIGNMENT_MASK)) )\r
- \r
-#define RGID_OFFSET (MT_BIT_OFFSET(tavorprm_ud_address_vector_st, rgid_127_96) >> 5) /* in DWORDS */\r
-#define LOG2_PORT_GID_TABLE_SIZE 5 /* 32 GID entries per port */\r
-//#define HANDLE_2_INDEX(udavm, ah) (((MT_ulong_ptr_t)ah - ((MT_ulong_ptr_t)(udavm)->ud_av_table)) >> UD_AV_ENTRY_SIZE_LOG2)\r
-#define HANDLE_2_INDEX(udavm, ah) (((MT_ulong_ptr_t)ah - ((MT_ulong_ptr_t)(udavm)->ud_av_table_host)) >> UD_AV_ENTRY_SIZE_LOG2)\r
-\r
-/*================ type definitions ================================================*/\r
-\r
-\r
-/* The main UDAV-manager structure */\r
-struct THH_udavm_st {\r
- u_int32_t* ud_av_table_ddr; /* the actual table of UDAV*/\r
- u_int32_t* ud_av_table_host; // == ud_av_table_ddr if av_in_host_mem \r
- u_int32_t max_av; /* number of entries in table */\r
- u_int32_t used_avs_counter;\r
- MT_size_t ud_av_table_sz; /* total table size in bytes */\r
- VAPI_lkey_t table_memkey; \r
- VIP_array_p_t udavs_array; /* the array which holds the free list of AV entries */\r
- MOSAL_spinlock_t table_spinlock; /* protect on the table from destroying UDAV and modifying at the same time */\r
-}THH_udavm_int_t;\r
-\r
-\r
-/*================ global variables definitions ====================================*/\r
-\r
-\r
-\r
-/*================ static functions prototypes =====================================*/\r
-\r
-static void fill_udav_entry(/*IN */ HH_pd_hndl_t pd, \r
- /*IN */ MT_bool is_new_pd,\r
- /*IN */ VAPI_ud_av_t *av_p, \r
- /*IN */ u_int32_t *av_entry_p);\r
-\r
-\r
-\r
-#ifdef MAX_DEBUG\r
-static void print_udav(VAPI_ud_av_t *av_p);\r
-#endif\r
-\r
-/*================ global functions definitions ====================================*/\r
-\r
-\r
-HH_ret_t THH_udavm_create( /*IN */ THH_ver_info_t *version_p, \r
- /*IN */ VAPI_lkey_t ud_av_table_memkey, \r
- /*IN */ MT_virt_addr_t ud_av_table, \r
- /*IN */ MT_size_t ud_av_table_sz,\r
- /*IN */ MT_bool av_in_host_mem,\r
- /*OUT*/ THH_udavm_t *udavm_p,\r
- /*OUT*/ char **av_ddr_base,\r
- /*OUT*/ char **av_host_base) \r
-\r
-{\r
- THH_udavm_t new_udavm_p = NULL;\r
- u_int32_t* ud_av_table_host;\r
- HH_ret_t ret;\r
- \r
- FUNC_IN;\r
-\r
- /* allocation of object structure */\r
- new_udavm_p = (THH_udavm_t)MALLOC(sizeof(THH_udavm_int_t));\r
- if (!new_udavm_p) {\r
- MTL_ERROR4("%s: Cannot allocate UDAVM object.\n", __func__);\r
- MT_RETURN( HH_EAGAIN);\r
- }\r
-\r
- memset(new_udavm_p,0,sizeof(THH_udavm_int_t));\r
- \r
- if (av_in_host_mem) {\r
- ud_av_table_host = (u_int32_t*)ud_av_table;\r
- } else {\r
- ud_av_table_host = (u_int32_t*)VMALLOC(ud_av_table_sz);\r
- if (ud_av_table_host == NULL) {\r
- FREE(new_udavm_p);\r
- MTL_ERROR4("%s: Cannot allocate UDAV host table.\n", __func__);\r
- MT_RETURN( HH_EAGAIN);\r
- }\r
- memset(ud_av_table_host,0,ud_av_table_sz);\r
- }\r
- new_udavm_p->ud_av_table_host = ud_av_table_host;\r
- \r
- /* filling the of UDAV struct */\r
- if (MOSAL_spinlock_init(&(new_udavm_p->table_spinlock)) != MT_OK){\r
- MTL_ERROR4("%s: Failed to initializing spinlocks.\n", __func__);\r
- ret= HH_ERR;\r
- goto err_free_mem;\r
- } \r
- new_udavm_p->ud_av_table_ddr = (u_int32_t*)ud_av_table;\r
- memset(new_udavm_p->ud_av_table_ddr,0,ud_av_table_sz);\r
- new_udavm_p->max_av = (u_int32_t)(ud_av_table_sz/UD_AV_ENTRY_SIZE);\r
- new_udavm_p->ud_av_table_sz = ud_av_table_sz;\r
- new_udavm_p->used_avs_counter = 0;\r
- new_udavm_p->table_memkey = ud_av_table_memkey;\r
- /* init the free list */\r
- ret = VIP_array_create_maxsize(new_udavm_p->max_av,new_udavm_p->max_av,&(new_udavm_p->udavs_array));\r
- if ( ret != VIP_OK ) {\r
- MTL_ERROR1("%s: VIP_array_create_maxsize failed, ret=%d \n", __func__, ret);\r
- goto err_free_mem;\r
- }\r
-\r
- /* succeeded to create object - return params: */\r
-\r
- *udavm_p = new_udavm_p;\r
- *av_ddr_base = (char *)new_udavm_p->ud_av_table_ddr;\r
- *av_host_base = (char *)new_udavm_p->ud_av_table_host;\r
-\r
- MT_RETURN(HH_OK);\r
-\r
- /* error handling cleanup */\r
-err_free_mem:\r
- VFREE(new_udavm_p);\r
- VFREE(ud_av_table_host);\r
-\r
- MT_RETURN(ret);\r
-\r
-}\r
-\r
-\r
-/************************************************************************************/\r
-\r
-HH_ret_t THH_udavm_destroy( /*IN */ THH_udavm_t udavm )\r
-{\r
- \r
- FUNC_IN;\r
- if (udavm == NULL) {\r
- MTL_ERROR4("%s: udavm is NULL.\n", __func__);\r
- MT_RETURN(HH_EINVAL);\r
- }\r
-\r
- /* destroy the handlers array */\r
- if (VIP_array_destroy(udavm->udavs_array, NULL) != VIP_OK) {\r
- MTL_ERROR1("%s: VIP_array_destroy failed \n", __func__);\r
- }\r
- \r
- if (udavm->ud_av_table_host != NULL\r
- && udavm->ud_av_table_host != udavm->ud_av_table_ddr) {\r
- VFREE(udavm->ud_av_table_host);\r
- udavm->ud_av_table_host = NULL;\r
- }\r
-\r
- FREE(udavm);\r
- MT_RETURN(HH_OK);\r
-}\r
-\r
-\r
-\r
-/************************************************************************************/\r
-\r
-HH_ret_t THH_udavm_get_memkey( /*IN */ THH_udavm_t udavm, \r
- /*IN */ VAPI_lkey_t *table_memkey_p )\r
-{\r
- FUNC_IN;\r
- if ((udavm != NULL) && (table_memkey_p !=NULL)) {\r
- *table_memkey_p = udavm->table_memkey;\r
- MT_RETURN(HH_OK);\r
- }\r
-\r
- MT_RETURN(HH_EINVAL);\r
-\r
-}\r
-\r
-/************************************************************************************/\r
-HH_ret_t THH_udavm_create_av( /*IN */ THH_udavm_t udavm, \r
- /*IN */ HH_pd_hndl_t pd, \r
- /*IN */ VAPI_ud_av_t *av_p, \r
- /*OUT*/ HH_ud_av_hndl_t *ah_p)\r
-{\r
- u_int32_t* av_entry_host_p;\r
- u_int32_t ah_index=0;\r
- VIP_common_ret_t ret;\r
- \r
- FUNC_IN;\r
- \r
- if (udavm == NULL) {\r
- MTL_ERROR4("THH_udavm_create_av: udavm is NULL.\n");\r
- MT_RETURN(HH_EINVAL);\r
- }\r
-\r
- if (av_p == NULL) {\r
- MTL_ERROR4("THH_udavm_create_av: av_p is NULL.\n");\r
- MT_RETURN(HH_EINVAL);\r
- }\r
-\r
- if (ah_p == NULL) {\r
- MTL_ERROR4("THH_udavm_create_av: ah_p is NULL.\n");\r
- MT_RETURN(HH_EINVAL);\r
- }\r
-\r
- if (av_p->dlid == 0) {\r
- MTL_ERROR4("THH_udavm_create_av: invalid dlid (ZERO).\n");\r
- MT_RETURN(HH_EINVAL);\r
- }\r
- \r
- /* check if max entries acceded */\r
- MOSAL_spinlock_dpc_lock(&(udavm->table_spinlock));\r
- if (udavm->max_av == udavm->used_avs_counter) {\r
- MOSAL_spinlock_unlock(&(udavm->table_spinlock));\r
- MTL_ERROR4("THH_udavm_create_av: No free entries in UDAV table.\n");\r
- MT_RETURN(HH_EAGAIN);\r
- }\r
- else{\r
- udavm->used_avs_counter++;\r
- }\r
- MOSAL_spinlock_unlock(&(udavm->table_spinlock));\r
-\r
- /* get a free index for the udav */\r
- ret = VIP_array_insert(udavm->udavs_array, NULL, &ah_index);\r
- if (ret != VIP_OK) {\r
- MTL_ERROR4("THH_udavm_create_av: Not enough resources.\n");\r
- /* decrement used AVs since this is failed */\r
- MOSAL_spinlock_dpc_lock(&(udavm->table_spinlock));\r
- udavm->used_avs_counter--;\r
- MOSAL_spinlock_unlock(&(udavm->table_spinlock));\r
- MT_RETURN(HH_EAGAIN);\r
- }\r
-\r
- /* fill out the host copy */\r
- av_entry_host_p = (u_int32_t*) (((MT_ulong_ptr_t)((udavm)->ud_av_table_host)) + \r
- ((ah_index)*UD_AV_ENTRY_SIZE)); \r
- memset(av_entry_host_p, 0, UD_AV_ENTRY_SIZE);\r
- fill_udav_entry(pd, TRUE, av_p, av_entry_host_p);\r
- \r
- if (udavm->ud_av_table_host != udavm->ud_av_table_ddr) {\r
- /* filling the DDR entry */\r
- u_int32_t* av_entry_ddr_p;\r
- av_entry_ddr_p = (u_int32_t*) (((MT_ulong_ptr_t)((udavm)->ud_av_table_ddr)) +\r
- ((ah_index)*UD_AV_ENTRY_SIZE));\r
- memcpy(av_entry_ddr_p, av_entry_host_p, UD_AV_ENTRY_SIZE);\r
- }\r
-\r
- *ah_p = (HH_ud_av_hndl_t)av_entry_host_p; \r
- MTL_DEBUG4(MT_FLFMT("Allocated address handle = " MT_ULONG_PTR_FMT ", entry index=%d"),*ah_p, ah_index);\r
- MT_RETURN(HH_OK);\r
-}\r
-\r
-/************************************************************************************/\r
-HH_ret_t THH_udavm_modify_av( /*IN */ THH_udavm_t udavm, \r
- /*IN */ HH_ud_av_hndl_t ah, \r
- /*IN */ VAPI_ud_av_t *av_p )\r
-{\r
- u_int32_t *ud_av_host_p= (u_int32_t*)(MT_ulong_ptr_t)ah;\r
- HH_ret_t hh_ret;\r
- u_int32_t ah_index;\r
- VIP_common_ret_t ret=VIP_OK;\r
-\r
- FUNC_IN;\r
- \r
- if (udavm == NULL) {\r
- MTL_ERROR4("THH_udavm_modify_av: udavm is NULL.\n");\r
- MT_RETURN(HH_EINVAL);\r
- }\r
-\r
- if (av_p == NULL) {\r
- MTL_ERROR4("THH_udavm_modify_av: av_p is NULL.\n");\r
- MT_RETURN(HH_EINVAL);\r
- }\r
-\r
- if (av_p->dlid == 0) {\r
- MTL_ERROR4("THH_udavm_modify_av: invalid dlid (ZERO).\n");\r
- MT_RETURN(HH_EINVAL);\r
- }\r
-\r
- /* Check that ah within the table and aligned to entry beginning */\r
- if (IS_INVALID_AV(udavm, ud_av_host_p) || ud_av_host_p[0] == 0) {\r
- MTL_DEBUG4("THH_udavm_modify_av: invalid ah (0x%lX).\n",ah);\r
- //MTL_ERROR1("THH_udavm_modify_av: invalid ah=%p table=%p\n",ud_av_host_p, udavm->ud_av_table_host);\r
- MT_RETURN(HH_EINVAL_AV_HNDL);\r
- }\r
-#if 0 /* new vapi 3.0 code */\r
- /* Check that ah within the table and aligned to entry beginning */\r
- if (IS_INVALID_AV_ALIGN(ud_av_p)) {\r
- MTL_ERROR4("THH_udavm_modify_av: invalid av alignment.\n");\r
- MT_RETURN(HH_EINVAL);\r
- }\r
- if (IS_INVALID_AV_MEMBER(udavm, ud_av_p)) {\r
- MTL_DEBUG4("THH_udavm_modify_av: invalid ah (" MT_ULONG_PTR_FMT ").\n",ah);\r
- MT_RETURN(HH_EINVAL_AV_HNDL);\r
- }\r
-#endif \r
- \r
- /* check that ah is a valid (allocated) handle */\r
- ah_index = (u_int32_t)HANDLE_2_INDEX(udavm, ud_av_host_p); \r
- ret = VIP_array_find_hold(udavm->udavs_array, ah_index, NULL);\r
- MTL_DEBUG3(MT_FLFMT("Calling VIP_array_find_hold, ah_index=%d, ret=%d\n"), ah_index, ret);\r
- if ( ret!=VIP_OK ) {\r
- MTL_ERROR4("THH_udavm_modify_av: handle is not valid.\n");\r
- hh_ret = HH_EINVAL_AV_HNDL;\r
- } else {\r
- MOSAL_spinlock_dpc_lock(&(udavm->table_spinlock));\r
- fill_udav_entry(0, FALSE, av_p, ud_av_host_p);\r
- if (udavm->ud_av_table_host != udavm->ud_av_table_ddr) {\r
- // TBD - take advantage of ah_index and avoid pointer math\r
- u_int32_t *ud_av_ddr_p = &udavm->ud_av_table_ddr[ud_av_host_p - udavm->ud_av_table_host];\r
- // follow actual DDR modification rules\r
- ud_av_ddr_p[0] = 0;\r
- memcpy(&ud_av_ddr_p[1], &ud_av_host_p[1], UD_AV_ENTRY_SIZE - sizeof(ud_av_ddr_p[0]));\r
- ud_av_ddr_p[0] = ud_av_host_p[0];\r
- }\r
- hh_ret = HH_OK;\r
- MOSAL_spinlock_unlock(&(udavm->table_spinlock));\r
- }\r
- ret = VIP_array_find_release(udavm->udavs_array, ah_index);\r
- MTL_DEBUG3(MT_FLFMT("Calling VIP_array_find_release ret=%d"), ret);\r
- if ( ret!=VIP_OK ) {\r
- MTL_ERROR1("%s: Internal mismatch - hv_index (%d) is not in array\n", __func__,ah_index);\r
- hh_ret = ret;\r
- }\r
- MTL_DEBUG4(MT_FLFMT("THH_udavm_modify_av: address handle = " MT_ULONG_PTR_FMT ", entry index=%d"),ah, ah_index);\r
- MT_RETURN(hh_ret);\r
-}\r
-\r
-/************************************************************************************/\r
-HH_ret_t THH_udavm_query_av( /*IN */ THH_udavm_t udavm, \r
- /*IN */ HH_ud_av_hndl_t ah, \r
- /*OUT*/ VAPI_ud_av_t *av_p )\r
-{\r
- HH_ret_t hh_ret;\r
- u_int32_t ah_index;\r
- VIP_common_ret_t ret=VIP_OK;\r
- u_int32_t *ud_av_host_p= (u_int32_t*)(MT_ulong_ptr_t)ah;\r
- \r
- FUNC_IN;\r
- \r
- if (udavm == NULL) {\r
- MTL_ERROR4("THH_udavm_query_av: udavm is NULL.\n");\r
- MT_RETURN(HH_EINVAL);\r
- }\r
-\r
- if (av_p == NULL) {\r
- MTL_ERROR4("THH_udavm_query_av: av_p is NULL.\n");\r
- MT_RETURN(HH_EINVAL);\r
- }\r
-\r
-#if 0 /* ??? new vapi 3.0 code */ \r
- /* Check that ah within the table and aligned to entry beginning */\r
- if (IS_INVALID_AV_ALIGN(ud_av_p)) {\r
- MTL_ERROR4("THH_udavm_query_av: invalid av alignment.\n");\r
- MT_RETURN(HH_EINVAL);\r
- }\r
- if (IS_INVALID_AV_MEMBER(udavm, ud_av_p)) {\r
- MTL_DEBUG4("THH_udavm_query_av: invalid ah (" MT_ULONG_PTR_FMT ").\n",ah);\r
- MT_RETURN(HH_EINVAL_AV_HNDL);\r
- }\r
-#endif\r
- \r
- /* Check that ah within the table and aligned to entry beginning */\r
- if (IS_INVALID_AV(udavm, ud_av_host_p) || ud_av_host_p[0] == 0) {\r
- MTL_DEBUG4("THH_udavm_query_av: invalid ah (0x%lX).\n",ah);\r
- //MTL_ERROR1("THH_udavm_query_av: invalid ah=%p table=%p\n",ud_av_host_p, udavm->ud_av_table_host);\r
- MT_RETURN(HH_EINVAL_AV_HNDL);\r
- }\r
-\r
- /* check that ah is a valid (allocated) handle */\r
- ah_index = (u_int32_t)HANDLE_2_INDEX(udavm, ud_av_host_p); \r
- ret = VIP_array_find_hold(udavm->udavs_array, ah_index, NULL);\r
- MTL_DEBUG3(MT_FLFMT("Calling VIP_array_find_hold, hv_index=%d, ret=%d\n"), ah_index, ret);\r
- if ( ret!=VIP_OK ) {\r
- MTL_ERROR4("THH_udavm_query_av: handle is not valid.\n");\r
- hh_ret = HH_EINVAL_AV_HNDL;\r
- } else { /* DO IT */\r
- MOSAL_spinlock_dpc_lock(&(udavm->table_spinlock));\r
- hh_ret = THH_udavm_parse_udav_entry(ud_av_host_p, av_p);\r
- MOSAL_spinlock_unlock(&(udavm->table_spinlock));\r
- }\r
- ret = VIP_array_find_release(udavm->udavs_array, ah_index);\r
- MTL_DEBUG3(MT_FLFMT("Calling VIP_array_find_release ret=%d"), ret);\r
- if ( ret!=VIP_OK ) {\r
- MTL_ERROR1("%s: Internal mismatch - hv_index (%d) is not in array\n", __func__, ah_index);\r
- hh_ret = ret;\r
- }\r
-\r
- MTL_DEBUG4(MT_FLFMT("THH_udavm_query_av: address handle = " MT_ULONG_PTR_FMT ", entry index=%d"),ah, ah_index);\r
-#if 1 <= MAX_DEBUG\r
- print_udav(av_p);\r
-#endif\r
- MT_RETURN(hh_ret);\r
- \r
-}\r
-\r
-/************************************************************************************/\r
-HH_ret_t THH_udavm_destroy_av( /*IN */ THH_udavm_t udavm, \r
- /*IN */ HH_ud_av_hndl_t ah )\r
-{\r
- u_int32_t ah_index;\r
- VIP_common_ret_t ret=VIP_OK;\r
- u_int32_t *ud_av_host_p= (u_int32_t*)(MT_ulong_ptr_t)ah;\r
- HH_ret_t hh_ret = HH_OK;\r
- \r
- FUNC_IN;\r
- \r
- if (udavm == NULL) {\r
- MTL_ERROR4("THH_udavm_destroy_av: udavm is NULL.\n");\r
- MT_RETURN(HH_EINVAL);\r
- }\r
-\r
-#if 0 /* ??? new vapi_3.0 code */\r
- /* Check that given ah is within the table and aligned to entry size */\r
- if (IS_INVALID_AV_ALIGN(ud_av_p)) {\r
- MTL_ERROR4("THH_udavm_destroy_av: invalid av alignment.\n");\r
- MT_RETURN(HH_EINVAL);\r
- }\r
- if (IS_INVALID_AV_MEMBER(udavm, ud_av_p)) {\r
- MTL_DEBUG4("THH_udavm_destroy_av: invalid ah (" MT_ULONG_PTR_FMT ").\n",ah);\r
- MT_RETURN(HH_EINVAL_AV_HNDL);\r
- }\r
-#endif\r
-\r
- /* Check that given ah is within the table and aligned to entry size */\r
- if (IS_INVALID_AV(udavm, ud_av_host_p) || ud_av_host_p[0] == 0) {\r
- MTL_DEBUG4("THH_udavm_destroy_av: invalid ah (0x%lX).\n",ah);\r
- //MTL_ERROR1("THH_udavm_destroy_av: invalid ah=%p table=%p\n",ud_av_host_p, udavm->ud_av_table_host);\r
- MT_RETURN(HH_EINVAL_AV_HNDL);\r
- }\r
- \r
- /* check that ah is a valid (allocated) handle and release it */\r
- ah_index = (u_int32_t)HANDLE_2_INDEX(udavm, ud_av_host_p); \r
- ret = VIP_array_erase_prepare(udavm->udavs_array, ah_index, NULL);\r
- MTL_DEBUG3(MT_FLFMT("Calling VIP_array_erase_prepare, hv_index=%d, ret=%d\n"), ah_index, ret);\r
- if ( ret==VIP_OK ) { /* DO IT */\r
- /* Use the knowledge that PD is in the first Dword of UDAV entry - so only put zeros there */\r
- ud_av_host_p[0] = 0;\r
- if (udavm->ud_av_table_host != udavm->ud_av_table_ddr) {\r
- // TBD - take advantage of ah_index and avoid pointer math\r
- u_int32_t *ud_av_ddr_p = &udavm->ud_av_table_ddr[ud_av_host_p - udavm->ud_av_table_host];\r
- ud_av_ddr_p[0] = 0;\r
- }\r
- ret = VIP_array_erase_done(udavm->udavs_array, ah_index, NULL);\r
- if ( ret!=VIP_OK ) { \r
- MTL_ERROR4("THH_udavm_destroy_av: internal error VIP_array_erase_done failed.\n");\r
- }\r
- /* decrement used AVs*/\r
- MOSAL_spinlock_dpc_lock(&(udavm->table_spinlock));\r
- udavm->used_avs_counter--;\r
- MOSAL_spinlock_unlock(&(udavm->table_spinlock));\r
- } else if ( ret==VIP_EBUSY ) {\r
- MTL_ERROR4("THH_udavm_destroy_av: handle is busy (in modify or query).\n");\r
- hh_ret = HH_EBUSY;\r
- } else if (ret == VIP_EINVAL_HNDL) {\r
- MTL_ERROR4("THH_udavm_destroy_av: Invalid handle.\n");\r
- hh_ret = HH_EINVAL_AV_HNDL;\r
- }\r
-\r
- MTL_DEBUG4(MT_FLFMT("THH_udavm_destroy_av: address handle = " MT_ULONG_PTR_FMT ", entry index=%d"),ah, ah_index);\r
- MT_RETURN(ret);\r
-}\r
-\r
-\r
-\r
-\r
-/************ LOCAL FUNCTIONS ************************************************************************/\r
-\r
-static void fill_udav_entry(/*IN */ HH_pd_hndl_t pd, \r
- /*IN */ MT_bool is_new_pd,\r
- /*IN */ VAPI_ud_av_t *av_p, \r
- /*IN */ u_int32_t *av_entry_p)\r
-{\r
-\r
- int i;\r
- u_int32_t new_av_arr[8] = {0,0,0,0,0,0,0,0}; /* entry size is 32 bytes */\r
- HH_pd_hndl_t pd_tmp;\r
- u_int32_t pd_word = 0;\r
- \r
- FUNC_IN;\r
- /*print_udav(av_p);*/\r
- \r
- /* if not new PD the we have to clear PD so entry will not considered valid by HW while we modify it*/\r
- /* need to save the current PD and write it back at the end */\r
- if (!is_new_pd) {\r
- pd_word = MOSAL_be32_to_cpu(*av_entry_p);\r
- pd_tmp = MT_EXTRACT32(pd_word, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, pd),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, pd));\r
- av_entry_p[0] = 0;\r
- }\r
- else {\r
- pd_tmp = pd;\r
- }\r
- \r
- /* PD */\r
- MT_INSERT_ARRAY32(new_av_arr, pd_tmp, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, pd),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, pd));\r
-\r
- /* port */\r
- MT_INSERT_ARRAY32(new_av_arr, av_p->port, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, port_number),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, port_number));\r
- \r
- /* rlid */\r
- MT_INSERT_ARRAY32(new_av_arr, av_p->dlid, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, rlid),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, rlid));\r
-\r
- /* mylid_path_bits */\r
- MT_INSERT_ARRAY32(new_av_arr, av_p->src_path_bits, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, my_lid_path_bits),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, my_lid_path_bits));\r
- /* grh enable */\r
- MT_INSERT_ARRAY32(new_av_arr, av_p->grh_flag, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, g),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, g));\r
- /* hop_limit */\r
- MT_INSERT_ARRAY32(new_av_arr, av_p->hop_limit, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, hop_limit),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, hop_limit));\r
-\r
- /* max_stat_rate */\r
- /* 0 - Suited for matched links no flow control\r
- All other values are transmitted to 1 since this is the only flow control of Tavor */\r
- MT_INSERT_ARRAY32(new_av_arr, ((av_p->static_rate ==0) ? 0:1), MT_BIT_OFFSET(tavorprm_ud_address_vector_st, max_stat_rate),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, max_stat_rate));\r
- \r
- /* msg size - we put allays the max value */\r
- MT_INSERT_ARRAY32(new_av_arr, 3, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, msg),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, msg));\r
- \r
- /* mgid_index (index to port GID table) - 6th (LOG2_PORT_GID_TABLE_SIZE+1) bit is (port-1) */\r
- MT_INSERT_ARRAY32(new_av_arr, \r
- (av_p->sgid_index & MASK32(LOG2_PORT_GID_TABLE_SIZE)) | \r
- ((av_p->port - 1) << LOG2_PORT_GID_TABLE_SIZE), \r
- MT_BIT_OFFSET(tavorprm_ud_address_vector_st, mgid_index), \r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, mgid_index));\r
- \r
- /* flow_label */\r
- MT_INSERT_ARRAY32(new_av_arr, av_p->flow_label, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, flow_label),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, flow_label));\r
- \r
- /* tclass */\r
- MT_INSERT_ARRAY32(new_av_arr, av_p->traffic_class, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, tclass),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, tclass));\r
- \r
- /* sl */\r
- MT_INSERT_ARRAY32(new_av_arr, av_p->sl, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, sl),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, sl));\r
- \r
- \r
- /* the gid is coming in BE format so we can insert it directly to the av_entry */\r
- /* need to fill it only if GRH bit is set */\r
- if (av_p->grh_flag) {\r
- /* rgid_127_96 */\r
- MT_INSERT_ARRAY32(av_entry_p, ((u_int32_t*)(av_p->dgid))[0], MT_BIT_OFFSET(tavorprm_ud_address_vector_st, rgid_127_96),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, rgid_127_96));\r
- \r
- /* rgid_95_64 */\r
- MT_INSERT_ARRAY32(av_entry_p, ((u_int32_t*)(av_p->dgid))[1], MT_BIT_OFFSET(tavorprm_ud_address_vector_st, rgid_95_64),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, rgid_95_64));\r
- \r
- /* rgid_63_32 */\r
- MT_INSERT_ARRAY32(av_entry_p, ((u_int32_t*)(av_p->dgid))[2], MT_BIT_OFFSET(tavorprm_ud_address_vector_st, rgid_63_32),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, rgid_63_32));\r
- \r
- /* rgid_31_0 */\r
- MT_INSERT_ARRAY32(av_entry_p, ((u_int32_t*)(av_p->dgid))[3], MT_BIT_OFFSET(tavorprm_ud_address_vector_st, rgid_31_0),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, rgid_31_0));\r
- }\r
- else { /* Arbel mode workaround - must give GRH >1 in lowest bits*/\r
- /* rgid_31_0 */\r
- MT_INSERT_ARRAY32(av_entry_p, 2, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, rgid_31_0),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, rgid_31_0));\r
-\r
- }\r
- \r
- /* now copy to the entry in the table with correct endianess */\r
- /* need to write the first DWORDs last since this is the PD that indicates \r
- to HW that this entry is valid */\r
- \r
- for (i = RGID_OFFSET-1; i >= 0; i--) {\r
- /*MTL_DEBUG1(MT_FLFMT("(i=%d) %p <- 0x%X"),i,av_entry_p+i,new_av_arr[i]);*/\r
- MOSAL_MMAP_IO_WRITE_DWORD(av_entry_p+i,MOSAL_cpu_to_be32(new_av_arr[i])); \r
- }\r
- \r
- FUNC_OUT;\r
-\r
-}\r
-\r
-/************************************************************************************/\r
-\r
-HH_ret_t THH_udavm_parse_udav_entry(u_int32_t *ud_av_p, \r
- VAPI_ud_av_t *av_p)\r
-{\r
- u_int32_t i;\r
- u_int32_t tmp_av_arr[8] = {0,0,0,0,0,0,0,0}; /* entry size is 32 bytes */\r
- HH_pd_hndl_t pd_tmp = 0;\r
- \r
- FUNC_IN;\r
- /* read entry to tmp area */\r
- /* the gid should stay in BE format so we don't change its endianess */\r
- for (i=0; i<RGID_OFFSET; i++) {\r
- tmp_av_arr[i] = MOSAL_be32_to_cpu(MOSAL_MMAP_IO_READ_DWORD(ud_av_p+i)); \r
- }\r
-\r
- /* PD */\r
- pd_tmp = MT_EXTRACT_ARRAY32(tmp_av_arr, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, pd),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, pd));\r
-\r
- /* if PD is zero it means that the entry is not valid */\r
- if (pd_tmp == 0) {\r
- MT_RETURN(HH_EINVAL);\r
- }\r
-\r
- /* port */\r
- av_p->port = MT_EXTRACT_ARRAY32(tmp_av_arr, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, port_number),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, port_number));\r
- \r
- /* rlid */\r
- av_p->dlid = MT_EXTRACT_ARRAY32(tmp_av_arr, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, rlid),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, rlid));\r
-\r
- /* mylid_path_bits */\r
- av_p->src_path_bits = MT_EXTRACT_ARRAY32(tmp_av_arr, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, my_lid_path_bits),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, my_lid_path_bits));\r
- /* grh enable */\r
- av_p->grh_flag = MT_EXTRACT_ARRAY32(tmp_av_arr, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, g),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, g));\r
- /* hop_limit */\r
- av_p->hop_limit = MT_EXTRACT_ARRAY32(tmp_av_arr, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, hop_limit),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, hop_limit));\r
-\r
- /* max_stat_rate */\r
- /* 0 - stay 0, 1 transmitted to 3 as defined in IPD encoding: IB-spec. 9.11.1, table 63 */\r
- i = MT_EXTRACT_ARRAY32(tmp_av_arr, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, max_stat_rate),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, max_stat_rate));\r
- av_p->static_rate = (i ? 3:0);\r
- \r
- /* msg size - not needed for the av info */\r
- \r
- /* mgid_index (index to port GID table)*/\r
- av_p->sgid_index = MT_EXTRACT_ARRAY32(tmp_av_arr, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, mgid_index),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, mgid_index)) & MASK32(LOG2_PORT_GID_TABLE_SIZE);\r
- /* TBD: sanity check that 6th bit of mgid_index matches port field (-1) */\r
- \r
- /* flow_label */\r
- av_p->flow_label = MT_EXTRACT_ARRAY32(tmp_av_arr, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, flow_label),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, flow_label));\r
- \r
- /* tclass */\r
- av_p->traffic_class = MT_EXTRACT_ARRAY32(tmp_av_arr, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, tclass),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, tclass));\r
- \r
- /* sl */\r
- av_p->sl = MT_EXTRACT_ARRAY32(tmp_av_arr, MT_BIT_OFFSET(tavorprm_ud_address_vector_st, sl),\r
- MT_BIT_SIZE(tavorprm_ud_address_vector_st, sl));\r
- \r
- /* gid stays in BE so it is extracted directly from the ud_av_p */\r
- /* rgid_127_96 */\r
- memcpy(av_p->dgid,ud_av_p+(MT_BYTE_OFFSET(tavorprm_ud_address_vector_st, rgid_127_96) >> 2),\r
- sizeof(av_p->dgid));\r
-\r
- \r
-#if 1 <= MAX_DEBUG\r
- print_udav(av_p);\r
-#endif \r
- MT_RETURN(HH_OK);\r
-\r
- \r
-} \r
-\r
-/************************************************************************************/\r
-#ifdef MAX_DEBUG\r
-\r
-static void print_udav(VAPI_ud_av_t *av_p)\r
-{\r
- FUNC_IN;\r
- MTL_DEBUG1("UDAV values:\n==================\n sl = %d \n dlid = %d\n src_path_bits = %d\n static_rate = %d\n grh_flag = %d\n traffic_class = %d\n"\r
- " flow_label = %d\n hop_limit = %d\n sgid_index = %d\n port = %d\n, dgid = %d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d.%d\n",\r
- av_p->sl, av_p->dlid, av_p->src_path_bits, av_p->static_rate, av_p->grh_flag, av_p->traffic_class, av_p->flow_label,\r
- av_p->hop_limit, av_p->sgid_index, av_p->port, av_p->dgid[0],av_p->dgid[1],av_p->dgid[2],av_p->dgid[3],av_p->dgid[4],av_p->dgid[5],\r
- av_p->dgid[6],av_p->dgid[7],av_p->dgid[8],av_p->dgid[9],av_p->dgid[10],av_p->dgid[11],\r
- av_p->dgid[12],av_p->dgid[13],av_p->dgid[14],av_p->dgid[15]);\r
- FUNC_OUT;\r
-}\r
-\r
-\r
-#endif\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#if !defined(H_TUDAV_H)\r
-#define H_TUDAV_H\r
-\r
-#include <mtl_common.h>\r
-#include <vapi_types.h>\r
-#include <mosal.h>\r
-#include <hh.h>\r
-#include <thh.h>\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_udavm_create\r
- * \r
- * Arguments:\r
- * version_p - Version information (see ...) \r
- * ud_av_table_memkey\r
- * ud_av_table \r
- * ud_av_table ud_av_table_sz\r
- * uadvm_p - Allocated object \r
- * \r
- * Returns:\r
- * HH_OK \r
- * HH_EINVAL -Invalid parameters (NULLs) \r
- * HH_EAGAIN -Not enough resources to allocate object \r
- *\r
- * Description: \r
- * Create the THH_udavm_t class instance. \r
- ************************************************************************/\r
- \r
-extern HH_ret_t THH_udavm_create( /*IN */ THH_ver_info_t *version_p, \r
- /*IN */ VAPI_lkey_t ud_av_table_memkey, \r
- /*IN */ MT_virt_addr_t ud_av_table, \r
- /*IN */ MT_size_t ud_av_table_sz,\r
- /*IN */ MT_bool av_in_host_mem,\r
- /*OUT*/ THH_udavm_t *udavm_p,\r
- /*OUT*/ char **av_ddr_base,\r
- /*OUT*/ char **av_host_base);\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_udavm_destroy\r
- * \r
- Arguments:\r
- udavm - object to destroy\r
-\r
- Returns:\r
- HH_OK \r
- HH_EINVAL - Unknown object \r
-\r
- Description: \r
- Free associated memory resources of this object. \r
- ************************************************************************/\r
-\r
-extern HH_ret_t THH_udavm_destroy( /*IN */ THH_udavm_t udavm );\r
-\r
-\r
- \r
-\r
-/************************************************************************\r
- * Function: THH_udavm_get_memkey\r
- * \r
- Arguments:\r
- udavm - the object to work\r
- table_memkey_p - pointer to place the memory key of the registered table \r
-\r
- Returns:\r
- HH_OK \r
- HH_EINVAL - Memory key was not set yet (or NULL ptr.) or Unknown object \r
-\r
- Description: \r
- Return the memory key associated with UD AVs of this object. \r
- ************************************************************************/\r
-\r
-extern HH_ret_t THH_udavm_get_memkey( /*IN */ THH_udavm_t udavm, \r
- /*IN */ VAPI_lkey_t *table_memkey_p );\r
-\r
-\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_udavm_create_av\r
- * \r
- Arguments:\r
- udavm -\r
- pd - PD of given UD AV \r
- av_p - The address vector \r
- ah_p - Returned address handle \r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL - Invalid parameters \r
- HH_EAGAIN - No available resources (UD AV entries) \r
- \r
- Description: Create address handle for given UD address vector. \r
- \r
- ************************************************************************/\r
-\r
-extern HH_ret_t THH_udavm_create_av( /*IN */ THH_udavm_t udavm, \r
- /*IN */ HH_pd_hndl_t pd, \r
- /*IN */ VAPI_ud_av_t *av_p, \r
- /*OUT*/ HH_ud_av_hndl_t *ah_p );\r
-\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_udavm_modify_av\r
- * \r
- Arguments:\r
- udavm \r
- ah - The address handle of UD AV to modify \r
- av_p - The updated UD AV \r
-\r
- Returns:\r
- HH_OK \r
- HH_EINVAL - Invalid parameters \r
- HH_EINVAL_AV_HNDL - Invalid address handle (no such handle) \r
-\r
- Description: \r
- Modify the UD AV entry associated with given address handle. \r
- \r
- ************************************************************************/\r
-\r
-extern HH_ret_t THH_udavm_modify_av( /*IN */ THH_udavm_t udavm, \r
- /*IN */ HH_ud_av_hndl_t ah, \r
- /*IN */ VAPI_ud_av_t *av_p );\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_udavm_query_av\r
- * \r
-\r
- Arguments:\r
- udavm \r
- ah - The address handle of UD AV to query \r
- av_p - The UD AV associated with given handle \r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL - Invalid parameters \r
- HH_EINVAL_AV_HNDL - Invalid address handle (no such handle) \r
- \r
- Description: \r
- Get the UD AV associated with given address handle.\r
-\r
- ************************************************************************/\r
-extern HH_ret_t THH_udavm_query_av( /*IN */ THH_udavm_t udavm, \r
- /*IN */ HH_ud_av_hndl_t ah, \r
- /*OUT*/ VAPI_ud_av_t *av_p );\r
-\r
-\r
-/************************************************************************\r
- * Function: THH_udavm_destroy_av\r
- * \r
- Arguments:\r
- udavm \r
- ah - The address handle of UD AV to destroy \r
- \r
- Returns:\r
- HH_OK \r
- HH_EINVAL - Invalid udavm \r
- HH_EINVAL_AV_HNDL - Invalid address handle (no such handle) \r
- \r
- Description: \r
- Free UD AV entry associated with given address handle. \r
- **************************************************************************/\r
-extern HH_ret_t THH_udavm_destroy_av( /*IN */ THH_udavm_t udavm, \r
- /*IN */ HH_ud_av_hndl_t ah );\r
-\r
-\r
-extern HH_ret_t THH_udavm_parse_udav_entry(u_int32_t *ud_av_p, \r
- VAPI_ud_av_t *av_p);\r
-\r
-\r
-\r
-#endif /* H_TUDAV_H */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include <thh_uldm_priv.h>\r
-\r
-/******************************************************************************\r
- * Function: THH_uldm_create\r
- *****************************************************************************/\r
-HH_ret_t THH_uldm_create( /*IN*/ THH_hob_t hob, \r
- /*IN*/ MT_phys_addr_t uar_base, \r
- /*IN*/ u_int8_t log2_max_uar, \r
- /*IN*/ u_int8_t log2_uar_pg_sz,\r
- /*IN*/ u_int32_t max_pd, \r
- /*OUT*/ THH_uldm_t *uldm_p )\r
-{\r
- u_int32_t max_uar;\r
- THH_uldm_t new_uldm_obj;\r
-\r
- MTL_DEBUG4("ENTERING THH_uldm_create: uar_base = " PHYS_ADDR_FMT ", log2_max_uar = %d\nlog2_uar_pg_sz=%d, max_pd=%d\n",\r
- uar_base, log2_max_uar, log2_uar_pg_sz, max_pd);\r
- /* create new uldm object */\r
- new_uldm_obj = (THH_uldm_t) MALLOC(sizeof(THH_uldm_obj_t));\r
- if (!new_uldm_obj) {\r
- MTL_ERROR1("THH_uldm_create: MALLOC of new_uldm_obj failed\n");\r
- return HH_ENOMEM;\r
- }\r
- memset(new_uldm_obj, 0, sizeof(THH_uldm_obj_t));\r
-\r
- max_uar = (1 << log2_max_uar);\r
- new_uldm_obj->max_uar = max_uar;\r
-\r
-\r
- /* create UAR free pool */\r
- new_uldm_obj->uldm_uar_table = (THH_uldm_uar_entry_t *) VMALLOC(max_uar * sizeof(THH_uldm_uar_entry_t));\r
- if (!new_uldm_obj->uldm_uar_table) {\r
- FREE(new_uldm_obj);\r
- MTL_ERROR1("THH_uldm_create: VMALLOC of uldm_uar_table failed\n");\r
- return HH_ENOMEM;\r
- }\r
- MTL_DEBUG4("THH_uldm_create: allocated uar table: addr = %p, size=%d\n",\r
- (void *) (new_uldm_obj->uldm_uar_table), max_uar);\r
-\r
- memset(new_uldm_obj->uldm_uar_table, 0, max_uar * sizeof(THH_uldm_uar_entry_t));\r
-\r
- MTL_TRACE4("THH_uldm_create: creating UAR pool\n");\r
- new_uldm_obj->uar_list.entries = new_uldm_obj->uldm_uar_table;\r
- new_uldm_obj->uar_list.size = max_uar ; /* list size is number of ENTRIES */\r
- new_uldm_obj->uar_list.head = 0;\r
- new_uldm_obj->uar_list.meta = &(new_uldm_obj->uar_meta);\r
-\r
- new_uldm_obj->uar_meta.entry_size = sizeof(THH_uldm_uar_entry_t);\r
- new_uldm_obj->uar_meta.prev_struct_offset = (MT_ulong_ptr_t) &(((THH_uldm_uar_entry_t *) (NULL))->u1.epool.prev);\r
- new_uldm_obj->uar_meta.next_struct_offset = (MT_ulong_ptr_t) &(((THH_uldm_uar_entry_t *) (NULL))->u1.epool.next);\r
-\r
- MTL_DEBUG4("THH_uldm_create: calling epool_init: entries = %p, size=%lu, head=%lu\nentry_size=%d, prev_offs=%d, next_offs=%d\n",\r
- new_uldm_obj->uar_list.entries, new_uldm_obj->uar_list.size, new_uldm_obj->uar_list.head,\r
- new_uldm_obj->uar_meta.entry_size, new_uldm_obj->uar_meta.prev_struct_offset,\r
- new_uldm_obj->uar_meta.next_struct_offset);\r
- epool_init(&(new_uldm_obj->uar_list));\r
-\r
- /* set uar's 0 and 1 to unavailable */\r
- MTL_TRACE4("THH_uldm_create: Reserving UARs 0 and 1\n");\r
- epool_reserve(&(new_uldm_obj->uar_list), 0, 2);\r
-\r
- /* create PD free pool */\r
- MTL_TRACE4("THH_uldm_create: creating PD pool\n");\r
- new_uldm_obj->uldm_pd_table = (THH_uldm_pd_entry_t *) VMALLOC(max_pd * sizeof(THH_uldm_pd_entry_t));\r
- if (!new_uldm_obj->uldm_pd_table) {\r
- VFREE(new_uldm_obj->uldm_uar_table);\r
- FREE(new_uldm_obj);\r
- return HH_ENOMEM;\r
- }\r
- memset(new_uldm_obj->uldm_pd_table, 0, max_pd * sizeof(THH_uldm_pd_entry_t));\r
-\r
-\r
- new_uldm_obj->pd_list.entries = new_uldm_obj->uldm_pd_table;\r
- new_uldm_obj->pd_list.size = max_pd; /* list size is number of ENTRIES */\r
- new_uldm_obj->pd_list.head = 0;\r
- new_uldm_obj->pd_list.meta = &(new_uldm_obj->pd_meta);\r
-\r
- new_uldm_obj->pd_meta.entry_size = sizeof(THH_uldm_pd_entry_t);\r
- new_uldm_obj->pd_meta.prev_struct_offset = (MT_ulong_ptr_t) &(((THH_uldm_pd_entry_t *) (NULL))->u1.epool.prev);\r
- new_uldm_obj->pd_meta.next_struct_offset = (MT_ulong_ptr_t) &(((THH_uldm_pd_entry_t *) (NULL))->u1.epool.next);\r
-\r
- MTL_DEBUG4("THH_uldm_create: calling epool_init: entries = %p, size=%lu, head=%lu\nentry_size=%d, prev_offs=%d, next_offs=%d\n",\r
- new_uldm_obj->pd_list.entries, new_uldm_obj->pd_list.size, new_uldm_obj->pd_list.head,\r
- new_uldm_obj->pd_meta.entry_size, new_uldm_obj->pd_meta.prev_struct_offset,\r
- new_uldm_obj->pd_meta.next_struct_offset);\r
- epool_init(&(new_uldm_obj->pd_list));\r
-\r
- /* set pd's 0 and 1 to unavailable */\r
- MTL_TRACE4("THH_uldm_create: Reserving PDs 0 and 1\n");\r
- epool_reserve(&(new_uldm_obj->pd_list), 0, THH_NUM_RSVD_PD);\r
-\r
- new_uldm_obj->uar_base = uar_base;\r
- new_uldm_obj->log2_max_uar = log2_max_uar;\r
- new_uldm_obj->log2_uar_pg_sz = log2_uar_pg_sz;\r
- new_uldm_obj->max_pd = max_pd;\r
- \r
- /* save HOB handle */\r
- new_uldm_obj->hob = hob;\r
-\r
- /* return the object handle */\r
- *uldm_p = new_uldm_obj;\r
-\r
- MTL_DEBUG4("LEAVING THH_uldm_create - OK\n");\r
-\r
- return HH_OK;\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_uldm_destroy\r
- *****************************************************************************/\r
-HH_ret_t THH_uldm_destroy( /*IN*/ THH_uldm_t uldm )\r
-{\r
- u_int32_t i;\r
-\r
- MTL_DEBUG4("==> THH_uldm_destroy\n");\r
- for (i=0; i< uldm->max_uar; i++) {\r
- if (uldm->uldm_uar_table[i].valid) {\r
- /* is uar valid check is within this function */\r
- THH_uldm_free_uar(uldm,i);\r
- }\r
- }\r
- VFREE(uldm->uldm_uar_table);\r
- VFREE(uldm->uldm_pd_table);\r
-\r
- epool_cleanup(&uldm->pd_list);\r
- epool_cleanup(&uldm->uar_list);\r
- FREE(uldm);\r
- MTL_DEBUG4("<== THH_uldm_destroy\n");\r
- return HH_OK;\r
-}\r
-\r
-/*************************************************************************\r
- * Function: THH_uldm_alloc_ul_res\r
- *************************************************************************/ \r
-HH_ret_t THH_uldm_alloc_ul_res( /*IN*/ THH_uldm_t uldm, \r
- /*IN*/ MOSAL_protection_ctx_t prot_ctx, \r
- /*OUT*/ THH_hca_ul_resources_t *hca_ul_resources_p )\r
-{\r
- u_int32_t uar_index;\r
- MT_virt_addr_t uar_map;\r
- HH_ret_t ret = HH_OK;\r
-\r
-#ifndef __DARWIN__\r
- MTL_DEBUG4("==> THH_uldm_alloc_ul_res. prot_ctx = 0x%x\n", prot_ctx);\r
-#else\r
- MTL_DEBUG4("==> THH_uldm_alloc_ul_res.\n");\r
-#endif\r
-\r
- ret = THH_uldm_alloc_uar(uldm,prot_ctx, &uar_index, &uar_map);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("%s: failed allocating UAR. ERROR = %d\n", __func__, ret);\r
- goto uldm_err;\r
- }\r
-\r
- hca_ul_resources_p->uar_index = uar_index;\r
- hca_ul_resources_p->uar_map = uar_map;\r
-\r
-uldm_err:\r
- MTL_DEBUG4("<== THH_uldm_alloc_ul_res. ret = %d\n", ret);\r
- return ret;\r
-}\r
-\r
-/*************************************************************************\r
- * Function: THH_uldm_free_ul_res\r
- *************************************************************************/ \r
-HH_ret_t THH_uldm_free_ul_res( /*IN*/ THH_uldm_t uldm, \r
- /*IN*/ THH_hca_ul_resources_t *hca_ul_resources_p)\r
-{\r
- HH_ret_t ret = HH_OK;\r
-\r
- MTL_DEBUG4("==> THH_uldm_free_ul_res. resources ptr = %p\n", (void *) hca_ul_resources_p);\r
- if (hca_ul_resources_p->uar_index > 1) {\r
- ret = THH_uldm_free_uar(uldm, hca_ul_resources_p->uar_index);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("%s: failed freeing UAR index %d. ERROR = %d\n", __func__, hca_ul_resources_p->uar_index, ret);\r
- goto uldm_err;\r
- }\r
- }\r
-\r
- hca_ul_resources_p->uar_index = 0;\r
- hca_ul_resources_p->uar_map = 0;\r
-\r
-uldm_err:\r
- MTL_DEBUG4("<== THH_uldm_free_ul_res. ret = %d\n", ret);\r
- return ret;\r
-}\r
-\r
-/*************************************************************************\r
- * Function: THH_uldm_alloc_uar\r
- *************************************************************************/\r
-HH_ret_t THH_uldm_alloc_uar( /*IN*/ THH_uldm_t uldm, \r
- /*IN*/ MOSAL_protection_ctx_t prot_ctx, \r
- /*OUT*/ u_int32_t *uar_index, \r
- /*OUT*/ MT_virt_addr_t *uar_map )\r
-{\r
- unsigned long i;\r
- HH_ret_t ret = HH_OK;\r
- \r
-#ifndef __DARWIN__\r
- MTL_DEBUG4("==> THH_uldm_alloc_uar. prot_ctx = 0x%x\n", prot_ctx);\r
-#else\r
- MTL_DEBUG4("==> THH_uldm_alloc_uar.\n");\r
-#endif\r
- \r
- if (uldm == (THH_uldm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_uldm_alloc_uar: ERROR : HCA device has not yet been opened\n");\r
- ret = HH_EINVAL;\r
- goto uldm_err;\r
- }\r
-\r
- i = epool_alloc(&(uldm->uar_list)) ;\r
- if (i == EPOOL_NULL) {\r
- MTL_ERROR1("THH_uldm_alloc_uar: ERROR : Could not allocate a UAR from pool\n");\r
- ret = HH_EINVAL;\r
- goto uldm_err;\r
- } else {\r
- *uar_index = i;\r
- memset(&uldm->uldm_uar_table[i], 0, sizeof(THH_uldm_uar_entry_t));\r
- uldm->uldm_uar_table[i].u1.uar.prot_ctx = prot_ctx;\r
- uldm->uldm_uar_table[i].valid = TRUE;\r
- *uar_map = (MT_virt_addr_t) MOSAL_map_phys_addr(/* phys addr */ uldm->uar_base + (i * (1 << uldm->log2_uar_pg_sz)),\r
- ((MT_size_t)1 << uldm->log2_uar_pg_sz),\r
- MOSAL_MEM_FLAGS_NO_CACHE | MOSAL_MEM_FLAGS_PERM_WRITE, \r
- prot_ctx);\r
- if (*uar_map == (MT_virt_addr_t) NULL) {\r
-#ifndef __DARWIN__\r
- MTL_ERROR1("THH_uldm_alloc_uar: MOSAL_map_phys_addr failed for prot ctx %d, addr " PHYS_ADDR_FMT ", size %d\n",\r
- prot_ctx,\r
- (MT_phys_addr_t) (uldm->uar_base + (i * (1 << uldm->log2_uar_pg_sz))),\r
- (1U << uldm->log2_uar_pg_sz));\r
-#else\r
- MTL_ERROR1("THH_uldm_alloc_uar: MOSAL_map_phys_addr failed, addr " PHYS_ADDR_FMT ", size %d\n",\r
- (MT_phys_addr_t) (uldm->uar_base + (i * (1 << uldm->log2_uar_pg_sz))),\r
- (1U << uldm->log2_uar_pg_sz));\r
-#endif\r
- return HH_EINVAL;\r
- }\r
- uldm->uldm_uar_table[i].u1.uar.virt_addr = *uar_map;\r
- MTL_DEBUG4("THH_uldm_alloc_uar: index = %d, addr = " VIRT_ADDR_FMT "\n", *uar_index, *uar_map);\r
- ret = HH_OK;\r
- }\r
-\r
-uldm_err:\r
- MTL_DEBUG4("<== THH_uldm_alloc_uar. ret = %d\n", ret);\r
- return ret;\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_uldm_free_uar\r
- *****************************************************************************/\r
-HH_ret_t THH_uldm_free_uar( /*IN*/ THH_uldm_t uldm, \r
- /*IN*/ u_int32_t uar_index )\r
-{\r
- call_result_t rc;\r
- HH_ret_t ret = HH_OK;\r
-\r
- /* check that index is valid */\r
- MTL_DEBUG4("==> THH_uldm_free_uar. uar_index = %d\n", uar_index);\r
- if (uldm == (THH_uldm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_uldm_free_uar: ERROR : HCA device has not yet been opened\n");\r
- ret = HH_EINVAL;\r
- goto err;\r
- }\r
-\r
- if (uar_index > uldm->max_uar ) {\r
- MTL_ERROR1("THH_uldm_free_uar: uar_index out of range (%d)\n", uar_index);\r
- ret = HH_EINVAL;\r
- goto err;\r
- }\r
-\r
- if (!(uldm->uldm_uar_table[uar_index].valid)) {\r
- MTL_ERROR1("THH_uldm_free_uar: uar_index was not allocated (%d)\n", uar_index);\r
- ret = HH_EINVAL;\r
- goto err;\r
- }\r
- /* Unmap previously mapped physical (will be page aligned, of course) */\r
-\r
- rc = MOSAL_unmap_phys_addr(uldm->uldm_uar_table[uar_index].u1.uar.prot_ctx, \r
- (MT_virt_addr_t) /* (void *) <ER/> */ uldm->uldm_uar_table[uar_index].u1.uar.virt_addr, \r
- ((MT_size_t)1 << uldm->log2_uar_pg_sz));\r
-\r
- if (rc != MT_OK) {\r
-#ifndef __DARWIN__\r
- MTL_ERROR1("THH_uldm_free_uar: MOSAL_unmap_phys_addr failed for prot ctx %d, addr %p, size %d\n",\r
- uldm->uldm_uar_table[uar_index].u1.uar.prot_ctx,\r
- (void *)uldm->uldm_uar_table[uar_index].u1.uar.virt_addr,\r
- (1 << uldm->log2_uar_pg_sz));\r
-#else\r
- MTL_ERROR1("THH_uldm_free_uar: MOSAL_unmap_phys_addr failed, addr %p, size %d\n",\r
- (void *)uldm->uldm_uar_table[uar_index].u1.uar.virt_addr,\r
- (1 << uldm->log2_uar_pg_sz));\r
-#endif\r
- ret = HH_EINVAL;\r
- goto err;\r
- }\r
- \r
- uldm->uldm_uar_table[uar_index].valid = FALSE;\r
- epool_free(&(uldm->uar_list), uar_index);\r
- \r
-err:\r
- MTL_DEBUG4("<== THH_uldm_free_uar. ret = %d\n", ret);\r
- return ret;\r
-\r
-}\r
-\r
-#pragma optimize( "g", off )\r
-/******************************************************************************\r
- * Function: THH_uldm_alloc_pd\r
- *****************************************************************************/\r
-HH_ret_t THH_uldm_alloc_pd( /*IN*/ THH_uldm_t uldm, \r
- /*IN*/ MOSAL_protection_ctx_t prot_ctx, \r
- /*IN-OUT*/ THH_pd_ul_resources_t *pd_ul_resources_p, \r
- /*OUT*/ HH_pd_hndl_t *pd_p )\r
-{ \r
- unsigned long i;\r
- HH_ret_t ret = HH_OK;\r
- THH_internal_mr_t mr_data;\r
- VAPI_lkey_t lkey;\r
- THH_mrwm_t mrwm;\r
- THH_ddrmm_t ddrmm;\r
- THH_udavm_t udavm;\r
- MT_size_t adj_ud_av_table_sz = 0;\r
- MT_virt_addr_t udav_virt_addr = 0;\r
- MT_phys_addr_t udav_phys_addr = 0;\r
- VAPI_size_t udav_phys_buf_size = 0;\r
- MT_bool use_priv_udav, av_in_host_mem, hide_ddr;\r
- u_int32_t pd_index;\r
- u_int32_t max_ah_num = 0, max_requested_avs = 0;\r
- unsigned int page_size;\r
- call_result_t rc;\r
-\r
-#ifndef __DARWIN__\r
- MTL_DEBUG4("==> THH_uldm_alloc_pd. uldm = %p, prot_ctx = 0x%x, resources_p = %p\n", (void *) uldm, prot_ctx, (void *) pd_ul_resources_p);\r
-#else\r
- MTL_DEBUG4("==> THH_uldm_alloc_pd. uldm = %p, resources_p = %p\n", (void *) uldm, (void *) pd_ul_resources_p);\r
-#endif\r
- \r
- if (uldm == (THH_uldm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("<==THH_uldm_alloc_pd: ERROR : HCA device has not yet been opened\n");\r
- return HH_EINVAL;\r
- }\r
-\r
-\r
- ret = THH_hob_get_udavm_info (uldm->hob, &udavm, &use_priv_udav, &av_in_host_mem, \r
- &lkey, &max_ah_num, &hide_ddr );\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("<==THH_uldm_alloc_pd: ERROR: could not acquire udavm information (%d)\n", ret);\r
- return ret;\r
- }\r
-\r
- rc = MOSAL_get_page_size(prot_ctx, pd_ul_resources_p->udavm_buf, &page_size);\r
- if ( rc != MT_OK ) {\r
- MTL_ERROR1(MT_FLFMT("%s: could not obtain page size of address="VIRT_ADDR_FMT), __func__,\r
- pd_ul_resources_p->udavm_buf);\r
- return HH_ENOMEM;\r
- }\r
- \r
- if (use_priv_udav && (((pd_ul_resources_p->udavm_buf_sz) & (page_size - 1)) != 0)){\r
- MTL_ERROR1("<==THH_uldm_alloc_pd: ERROR : udavm_buf_size ("SIZE_T_FMT") is not a multiple of the page size\n",\r
- pd_ul_resources_p->udavm_buf_sz);\r
- return HH_EINVAL;\r
- }\r
-\r
- if (!use_priv_udav) {\r
- /* check to see that we are not trying to allocate space for more AVs than max reported in HCA capabilities */\r
- max_requested_avs = (u_int32_t)((pd_ul_resources_p->udavm_buf_sz) / (sizeof(struct tavorprm_ud_address_vector_st) / 8));\r
- if (max_requested_avs > max_ah_num) {\r
- MTL_ERROR1("<==THH_uldm_alloc_pd: max AVs too large: requested %d, max available=%d\n",\r
- max_requested_avs, max_ah_num);\r
- return HH_EINVAL;\r
- }\r
- }\r
-\r
- i = epool_alloc(&uldm->pd_list) ;\r
- if (i == EPOOL_NULL) {\r
- MTL_ERROR1("<==THH_uldm_alloc_pd: could not allocate a PD from pool\n");\r
- return HH_EAGAIN;\r
- } else {\r
- pd_index = (u_int32_t) i;\r
- memset(&uldm->uldm_pd_table[pd_index], 0, sizeof(THH_uldm_pd_entry_t));\r
- uldm->uldm_pd_table[pd_index].u1.pd.prot_ctx = prot_ctx;\r
- *pd_p = (HH_pd_hndl_t) i;\r
-\r
- if (use_priv_udav) {\r
- pd_ul_resources_p->udavm_buf_memkey = lkey;\r
- } else {\r
- ret = THH_hob_get_mrwm(uldm->hob,&mrwm);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_uldm_alloc_pd: could not acquire MRWM handle (%d)\n", ret);\r
- goto udavm_get_mwrm_err;\r
- }\r
- /* Use DDR resources if appropriate flag set at module initialization,\r
- or if Tavor firmware indicates that should not hide DDR memory, or if not a PD for a SQP\r
- */\r
- if ((hide_ddr == FALSE) && (av_in_host_mem == FALSE) && (pd_ul_resources_p->pd_flags != PD_FOR_SQP)) {\r
- ret = THH_hob_get_ddrmm(uldm->hob,&ddrmm);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_uldm_alloc_pd: could not acquire DDRMM handle (%d)\n", ret);\r
- } else {\r
- \r
- /* get memory in DDR. If cannot, then use regular memory allocated in */\r
- /* call to THHUL_uldm_alloc_pd_prep */\r
- adj_ud_av_table_sz = MT_UP_ALIGNX_SIZE((pd_ul_resources_p->udavm_buf_sz), MOSAL_SYS_PAGE_SHIFT);\r
- udav_phys_buf_size = adj_ud_av_table_sz;\r
- ret = THH_ddrmm_alloc(ddrmm, \r
- adj_ud_av_table_sz, \r
- MOSAL_SYS_PAGE_SHIFT,\r
- &udav_phys_addr);\r
- if (ret != HH_OK) {\r
- MTL_DEBUG1("THH_uldm_alloc_pd: could not allocate protected udavm area in DDR(err = %d)\n", ret);\r
- udav_phys_addr = (MT_phys_addr_t) 0;\r
- } else {\r
-#ifndef __DARWIN__\r
- MTL_DEBUG4("THH_uldm_alloc_pd. prot_ctx = 0x%x, phys_addr = " PHYS_ADDR_FMT \r
- ", buf_size="SIZE_T_FMT", adj_size="SIZE_T_FMT"\n",\r
- prot_ctx,\r
- udav_phys_addr, pd_ul_resources_p->udavm_buf_sz,\r
- adj_ud_av_table_sz);\r
-#else\r
- MTL_DEBUG4("THH_uldm_alloc_pd. phys_addr = " PHYS_ADDR_FMT \r
- ", buf_size="SIZE_T_FMT", adj_size="SIZE_T_FMT"\n",\r
- udav_phys_addr, pd_ul_resources_p->udavm_buf_sz,\r
- adj_ud_av_table_sz);\r
-#endif\r
- udav_virt_addr = (MT_virt_addr_t) MOSAL_map_phys_addr( udav_phys_addr , \r
-/*** warning C4242: 'function' : conversion from 'VAPI_size_t' to 'MT_size_t', possible loss of data ***/\r
- (MT_size_t)udav_phys_buf_size,\r
- MOSAL_MEM_FLAGS_NO_CACHE | \r
- MOSAL_MEM_FLAGS_PERM_WRITE | \r
- MOSAL_MEM_FLAGS_PERM_READ , \r
- prot_ctx);\r
- MTL_DEBUG4("THH_uldm_alloc_pd. udav virt_addr = " VIRT_ADDR_FMT "\n", udav_virt_addr);\r
- if (udav_virt_addr == (MT_virt_addr_t) NULL) {\r
- MTL_ERROR1("THH_uldm_alloc_pd: could not map physical address " PHYS_ADDR_FMT " to virtual\n", \r
- udav_phys_addr);\r
-/*** warning C4242: 'function' : conversion from 'VAPI_size_t' to 'MT_size_t', possible loss of data ***/\r
- ret = THH_ddrmm_free(ddrmm,udav_phys_addr,(MT_size_t)udav_phys_buf_size);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_uldm_alloc_pd: could not free protected udavm area in DDR(err = %d)\n", ret);\r
- }\r
- udav_phys_addr = (MT_phys_addr_t) 0;\r
- } else {\r
- /* substitute DDR-allocated region for the one passed by pd_ul_resources_p */\r
- pd_ul_resources_p->udavm_buf = udav_virt_addr;\r
- }\r
- }\r
- }\r
- }\r
- /* check if have a buffer allocated for udav table */\r
- if (pd_ul_resources_p->udavm_buf == (MT_virt_addr_t) NULL) {\r
- MTL_ERROR1("THH_uldm_alloc_pd: no udavm area allocated.\n");\r
- /*value of ret was set above by some failure */\r
- goto no_udavm_area;\r
- }\r
-\r
- memset(&mr_data, 0, sizeof(mr_data));\r
- mr_data.force_memkey = FALSE;\r
- mr_data.memkey = 0;\r
- mr_data.pd = (HH_pd_hndl_t) pd_index;\r
- mr_data.size = pd_ul_resources_p->udavm_buf_sz;\r
- mr_data.vm_ctx = prot_ctx;\r
- if (udav_phys_addr) {\r
- VAPI_phy_addr_t udav_phy = udav_phys_addr;\r
- mr_data.num_bufs = 1; /* != 0 iff physical buffesrs supplied */\r
- mr_data.phys_buf_lst = &udav_phy; /* size = num_bufs */\r
- mr_data.buf_sz_lst = &udav_phys_buf_size; /* [num_bufs], corresponds to phys_buf_lst */\r
- mr_data.start = pd_ul_resources_p->udavm_buf;\r
- } else {\r
- /* using user-level buffer: check that buffer address is aligned to entry size; */\r
- if (pd_ul_resources_p->udavm_buf != \r
- (MT_UP_ALIGNX_VIRT((pd_ul_resources_p->udavm_buf), \r
- ceil_log2((sizeof(struct tavorprm_ud_address_vector_st) / 8))))) {\r
- MTL_ERROR1("THH_uldm_alloc_pd: provided HOST MEM buffer not properly aligned.\n");\r
- /*value of ret was set above by some failure */\r
- ret = HH_EINVAL;\r
- goto no_udavm_area;\r
- }\r
- mr_data.start = (IB_virt_addr_t)pd_ul_resources_p->udavm_buf;\r
- MTL_DEBUG1(MT_FLFMT("%s: User level UDAV tbl = " U64_FMT), __func__, mr_data.start);\r
- }\r
- uldm->uldm_pd_table[pd_index].valid = TRUE; /* set to valid here, so that THH_uldm_get_protection_ctx will work */\r
- ret = THH_mrwm_register_internal(mrwm, &mr_data, &lkey);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_uldm_alloc_pd: could not register udavm table (%d)\n", ret);\r
- uldm->uldm_pd_table[pd_index].valid = FALSE;\r
- goto udavm_table_register_err;\r
- }\r
- pd_ul_resources_p->udavm_buf_memkey = lkey;\r
- uldm->uldm_pd_table[pd_index].u1.pd.lkey = lkey;\r
- uldm->uldm_pd_table[pd_index].u1.pd.udav_table_ddr_phys_addr = udav_phys_addr;\r
- uldm->uldm_pd_table[pd_index].u1.pd.udav_table_ddr_virt_addr = udav_virt_addr;\r
-/*** warning C4242: '=' : conversion from 'VAPI_size_t' to 'MT_size_t', possible loss of data ***/\r
- uldm->uldm_pd_table[pd_index].u1.pd.udav_table_size = (udav_phys_addr ? (MT_size_t)udav_phys_buf_size : 0);\r
- MTL_DEBUG4("THH_uldm_alloc_pd: PD %u: saving phys addr = " PHYS_ADDR_FMT ", virt addr = " VIRT_ADDR_FMT ", size="SIZE_T_FMT"\n",\r
- pd_index, udav_phys_addr, udav_virt_addr, uldm->uldm_pd_table[pd_index].u1.pd.udav_table_size );\r
- }\r
- /* set VALID flag only if successful */\r
- uldm->uldm_pd_table[pd_index].valid = TRUE;\r
- ret = HH_OK;\r
- MTL_DEBUG4("THH_uldm_alloc_pd. PD = %u\n", pd_index);\r
- goto ok_retn;\r
- }\r
-\r
-no_udavm_area:\r
-udavm_get_mwrm_err:\r
-udavm_table_register_err:\r
- epool_free(&(uldm->pd_list),i);\r
-ok_retn:\r
- MTL_DEBUG4("<== THH_uldm_alloc_pd. ret = %d\n", ret);\r
- return ret;\r
-\r
-}\r
-#pragma optimize( "", on )\r
-\r
-/******************************************************************************\r
- * Function: THH_uldm_free_pd \r
- *****************************************************************************/\r
-HH_ret_t THH_uldm_free_pd( /*IN*/ THH_uldm_t uldm, \r
- /*IN*/ HH_pd_hndl_t pd )\r
-{\r
-\r
- HH_ret_t ret = HH_OK;\r
- VAPI_lkey_t lkey;\r
- THH_mrwm_t mrwm;\r
- THH_udavm_t udavm;\r
- THH_ddrmm_t ddrmm;\r
- MT_virt_addr_t udav_virt_addr = 0;\r
- MT_phys_addr_t udav_phys_addr = 0;\r
- MT_size_t udav_size = 0;\r
- MT_bool use_priv_udav, av_in_host_mem, hide_ddr;\r
- call_result_t res;\r
- u_int32_t max_ah_num = 0;\r
- \r
- MTL_DEBUG4("==> THH_uldm_free_pd\n");\r
- if (uldm == (THH_uldm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_uldm_free_pd: ERROR : HCA device has not yet been opened\n");\r
- ret = HH_EINVAL;\r
- goto err_retn;\r
- }\r
- \r
- if (pd >= uldm->max_pd ) {\r
- MTL_ERROR1("THH_uldm_free_pd: pd out of range (%d)\n", pd);\r
- ret = HH_EINVAL;\r
- goto err_retn;\r
- }\r
-\r
- if (!(uldm->uldm_pd_table[pd].valid)) {\r
- MTL_ERROR1("THH_uldm_free_pd: pd was not allocated (%d)\n", pd);\r
- ret = HH_EINVAL;\r
- goto err_retn;\r
- }\r
-\r
- ret = THH_hob_get_udavm_info (uldm->hob, &udavm, &use_priv_udav, &av_in_host_mem, \r
- &lkey, &max_ah_num, &hide_ddr );\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_uldm_free_pd: could not acquire udavm information (%d)\n", ret);\r
- goto get_udavm_info_err;\r
- }\r
- MTL_DEBUG4("THH_uldm_free_pd: udavm=%p, use_priv_udav = %s, lkey = 0x%x\n", \r
- udavm, (use_priv_udav ? "TRUE" : "FALSE"), lkey);\r
- if (!use_priv_udav) {\r
-\r
- ret = THH_hob_get_mrwm(uldm->hob,&mrwm);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_uldm_free_pd: could not acquire MRWM handle (%d)\n", ret);\r
- ret = HH_OK;\r
- goto udavm_get_mwrm_err;\r
- }\r
- \r
- lkey = uldm->uldm_pd_table[pd].u1.pd.lkey; /* get lkey saved with this PD */\r
- MTL_DEBUG4("THH_uldm_free_pd: DEREGISTERING mem region with lkey = 0x%x\n", lkey); \r
- ret = THH_mrwm_deregister_mr(mrwm, lkey);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_uldm_free_pd: THH_mrwm_deregister_mr error (%d)\n", ret);\r
- ret = HH_OK;\r
- goto mrwm_unregister_err;\r
- }\r
- \r
- udav_virt_addr = uldm->uldm_pd_table[pd].u1.pd.udav_table_ddr_virt_addr;\r
- udav_phys_addr = uldm->uldm_pd_table[pd].u1.pd.udav_table_ddr_phys_addr;\r
- udav_size = uldm->uldm_pd_table[pd].u1.pd.udav_table_size;\r
- \r
- MTL_DEBUG4("THH_uldm_free_pd: PD %d: udav_phys_addr =" PHYS_ADDR_FMT ", udav_virt_addr = " VIRT_ADDR_FMT ", udav_size = "SIZE_T_FMT"\n", \r
- pd, udav_phys_addr, udav_virt_addr, udav_size);\r
- /* If UDAV was allocated in DDR, free up the DDR memory here */\r
- if (udav_phys_addr != (MT_phys_addr_t) 0) {\r
- ret = THH_hob_get_ddrmm(uldm->hob,&ddrmm);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_uldm_free_pd: could not acquire DDRMM handle (%d)\n", ret);\r
- ret = HH_OK;\r
- goto udavm_get_ddrmm_err;\r
- }\r
- \r
- if ((res = MOSAL_unmap_phys_addr( uldm->uldm_pd_table[pd].u1.pd.prot_ctx, \r
- (MT_virt_addr_t) udav_virt_addr, \r
- udav_size )) != MT_OK) {\r
- MTL_ERROR1("THH_uldm_free_pd: MOSAL_unmap_phys_addr error for udavm:%d\n", res);\r
- ret = HH_OK;\r
- goto unmap_phys_addr_err;\r
- }\r
- ret = THH_ddrmm_free(ddrmm, udav_phys_addr, udav_size);\r
- if (ret != HH_OK) {\r
- MTL_ERROR1("THH_uldm_free_pd: THH_ddrmm_free error (%d)\n", ret);\r
- ret = HH_OK;\r
- goto ddrmm_free_err;\r
- }\r
- }\r
- }\r
- ret = HH_OK;\r
- goto ok_retn;\r
-\r
-ddrmm_free_err:\r
- unmap_phys_addr_err:\r
-udavm_get_ddrmm_err:\r
-mrwm_unregister_err:\r
-udavm_get_mwrm_err:\r
-ok_retn:\r
- /* make resource inaccessible */\r
- uldm->uldm_pd_table[pd].valid = FALSE;\r
- epool_free(&(uldm->pd_list), pd);\r
-\r
-get_udavm_info_err:\r
-err_retn:\r
- MTL_DEBUG4("<== THH_uldm_free_pd. ret = %d\n", ret);\r
- return ret;\r
-}\r
-\r
-/******************************************************************************\r
- * Function: THH_uldm_get_protection_ctx \r
- *****************************************************************************/\r
-HH_ret_t THH_uldm_get_protection_ctx( /*IN*/ THH_uldm_t uldm, \r
- /*IN*/ HH_pd_hndl_t pd, \r
- /*OUT*/ MOSAL_protection_ctx_t *prot_ctx_p )\r
-{\r
- HH_ret_t ret = HH_OK;\r
-\r
- MTL_DEBUG4("==> THH_uldm_get_protection_ctx. uldm = %p, pd = %d, prot_ctx_p = %p\n", \r
- (void *) uldm, pd, (void *)prot_ctx_p);\r
- if (uldm == (THH_uldm_t)THH_INVALID_HNDL) {\r
- MTL_ERROR1("THH_uldm_get_protection_ctx: ERROR : HCA device has not yet been opened\n");\r
- ret = HH_EINVAL;\r
- goto err_retn;\r
- }\r
- \r
- /* protect against bad calls */\r
- if (uldm == (THH_uldm_t)0) {\r
- MTL_ERROR1("THH_uldm_get_protection_ctx: ERROR : uldm handle is ZERO\n");\r
- ret = HH_EINVAL;\r
- goto err_retn;\r
-}\r
-\r
- if (pd >= uldm->max_pd ) {\r
- MTL_ERROR1("THH_uldm_get_protection_ctx: pd out of range (%d)\n", pd);\r
- ret = HH_EINVAL;\r
- goto err_retn;\r
- }\r
-\r
- if (!(uldm->uldm_pd_table[pd].valid)) {\r
- if (pd != THH_RESERVED_PD) {\r
- MTL_ERROR1("THH_uldm_get_protection_ctx: pd was not allocated (%d)\n", pd);\r
- }\r
- ret = HH_EINVAL;\r
- goto err_retn;\r
- }\r
-\r
- *prot_ctx_p = uldm->uldm_pd_table[pd].u1.pd.prot_ctx;\r
-#ifndef __DARWIN__\r
- MTL_DEBUG4("THH_uldm_get_protection_ctx. ctx = %d\n", *prot_ctx_p);\r
-#else\r
- MTL_DEBUG4("THH_uldm_get_protection_ctx\n");\r
-#endif\r
-\r
-err_retn:\r
- MTL_DEBUG4("<== THH_uldm_get_protection_ctx. ret = %d\n", ret);\r
- return ret;\r
-}\r
-\r
-HH_ret_t THH_uldm_get_num_objs( /*IN*/ THH_uldm_t uldm, u_int32_t *num_alloc_us_res_p,\r
- u_int32_t *num_alloc_pds_p)\r
-{\r
- u_int32_t i;\r
- u_int32_t alloc_res = 0;\r
-\r
- MTL_DEBUG4("==> THH_uldm_get_num_objs\n");\r
- if ((uldm == (THH_uldm_t)THH_INVALID_HNDL) ||\r
- (uldm == (THH_uldm_t)0) ||\r
- (!num_alloc_us_res_p && !num_alloc_pds_p)){\r
- MTL_ERROR1("THH_uldm_get_num_objs: Invalid uldm handle, or all return params are NULL\n");\r
- return HH_EINVAL;\r
- }\r
- \r
- for (i=0; i< uldm->max_uar; i++) {\r
- if (uldm->uldm_uar_table[i].valid) {\r
- /* is uar valid check is within this function */\r
- alloc_res++;\r
- }\r
- }\r
- if (num_alloc_us_res_p) {\r
- *num_alloc_us_res_p=alloc_res;\r
- }\r
-\r
- alloc_res = 0;\r
- for (i=0; i< uldm->max_pd; i++) {\r
- if (uldm->uldm_pd_table[i].valid) {\r
- /* is uar valid check is within this function */\r
- alloc_res++;\r
- }\r
- }\r
- if (num_alloc_pds_p) {\r
- *num_alloc_pds_p=alloc_res;\r
- }\r
- \r
- return HH_OK;\r
-}\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_THH_ULDM_H\r
-#define H_THH_ULDM_H\r
-\r
-#include <mtl_common.h>\r
-#include <mosal.h>\r
-#include <hh.h>\r
-#include <thh.h>\r
-#include <thh_hob.h>\r
-\r
-\r
-/******************************************************************************\r
- * Function: THH_uldm_create\r
- *\r
- * Arguments:\r
- * hob - The THH_hob object in which this object will be included\r
- * uar_base - Physical base address of UARs (address of UAR0)\r
- * log2_max_uar - Log2 of number of UARs (including 0 and 1)\r
- * log2_uar_pg_sz - UAR page size as set in INIT_HCA\r
- * max_pd - Maximum PDs allowed to be allocated\r
- * uldm_p - Allocated THH_uldm object\r
- \r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameter\r
- * HH_EAGAIN - Not enough resources for creating this object\r
- *\r
- * Description:\r
- * Create object context which manages the UAR and PD resources.\r
- */\r
-HH_ret_t THH_uldm_create( /*IN*/ THH_hob_t hob, \r
- /*IN*/ MT_phys_addr_t uar_base, \r
- /*IN*/ u_int8_t log2_max_uar, \r
- /*IN*/ u_int8_t log2_uar_pg_sz,\r
- /*IN*/ u_int32_t max_pd, \r
- /*OUT*/ THH_uldm_t *uldm_p );\r
-\r
-/******************************************************************************\r
- * Function: THH_uldm_destroy\r
- *\r
- * Arguments:\r
- * uldm - THH_uldm object to destroy\r
- \r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameter\r
- *\r
- * Description:\r
- * Free resources of the THH_uldm object.\r
- */\r
-HH_ret_t THH_uldm_destroy( /*IN*/ THH_uldm_t uldm );\r
-\r
-/*************************************************************************\r
- * Function: THH_uldm_alloc_ul_res\r
- *\r
- * Arguments:\r
- * uldm \r
- * prot_ctx - Protection context of user level\r
- * hca_ul_resources_p - Returned user level resources\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameter\r
- * HH_EAGAIN - No available resources to allocate\r
- *\r
- * Description:\r
- * Allocate user level resources (UAR).\r
- */\r
-HH_ret_t THH_uldm_alloc_ul_res( /*IN*/ THH_uldm_t uldm, \r
- /*IN*/ MOSAL_protection_ctx_t prot_ctx, \r
- /*OUT*/ THH_hca_ul_resources_t *hca_ul_resources_p );\r
-\r
-/*************************************************************************\r
- * Function: THH_uldm_free_ul_res\r
- *\r
- * Arguments:\r
- * uldm \r
- * hca_ul_resources_p - A copy of resources structure returned on\r
- * resources allocation\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameter\r
- *\r
- * Description:\r
- * Free the resources allocated using THH_uldm_alloc_ul_res()\r
- */\r
-HH_ret_t THH_uldm_free_ul_res( /*IN*/ THH_uldm_t uldm, \r
- /*IN*/ THH_hca_ul_resources_t *hca_ul_resources_p);\r
-\r
-/*************************************************************************\r
- * Function: THH_uldm_alloc_uar\r
- *\r
- * Arguments:\r
- * uldm\r
- * prot_ctx - User level protection context to map UAR to \r
- * uar_index - Returned index of allocated UAR\r
- * uar_map - Virtual address in user level context to which the\r
- * allocated UAR is mapped\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameter\r
- * HH_EAGAIN - No available UAR\r
- *\r
- * Description:\r
- * Allocate an available UAR and map it to user level memory space.\r
- */\r
-HH_ret_t THH_uldm_alloc_uar( /*IN*/ THH_uldm_t uldm, \r
- /*IN*/ MOSAL_protection_ctx_t prot_ctx, \r
- /*OUT*/ u_int32_t *uar_index, \r
- /*OUT*/ MT_virt_addr_t *uar_map );\r
-\r
-/******************************************************************************\r
- * Function: THH_uldm_free_uar\r
- *\r
- * Arguments:\r
- * uldm\r
- * uar_index - Index of UAR to free\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameter\r
- *\r
- * Description:\r
- * Unmap given UAR from user level memory space and return it to free UARs pool.\r
- */\r
-HH_ret_t THH_uldm_free_uar( /*IN*/ THH_uldm_t uldm, \r
- /*IN*/ u_int32_t uar_index );\r
-\r
-/******************************************************************************\r
- * Function: THH_uldm_alloc_pd\r
- *\r
- * Arguments:\r
- * uldm\r
- * prot_ctx - Protection context of user asking for this PD\r
- * pd_ul_resources_p - Mostly UD AV table memory to register \r
- * pd_p - Allocated PD handle\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameter\r
- * HH_EAGAIN - No free PDs to allocate\r
- *\r
- * Description:\r
- * Allocate a PD for given protection context.\r
- */\r
-HH_ret_t THH_uldm_alloc_pd( /*IN*/ THH_uldm_t uldm, \r
- /*IN*/ MOSAL_protection_ctx_t prot_ctx, \r
- /*IN*/ THH_pd_ul_resources_t *pd_ul_resources_p, \r
- /*OUT*/ HH_pd_hndl_t *pd_p );\r
-\r
-/******************************************************************************\r
- * Function: THH_uldm_free_pd \r
- *\r
- * Arguments:\r
- * uldm\r
- * pd - PD to free\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameter\r
- *\r
- * Description:\r
- * Free the PD.\r
- */\r
-HH_ret_t THH_uldm_free_pd( /*IN*/ THH_uldm_t uldm, \r
- /*IN*/ HH_pd_hndl_t pd ) ;\r
-\r
-/******************************************************************************\r
- * Function: THH_uldm_get_protection_ctx \r
- *\r
- * Arguments:\r
- * uldm\r
- * pd - PD for which the protection context is required\r
- * prot_ctx_p - Returned protection context \r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameter\r
- *\r
- * Description:\r
- * This function returns the protection context associated with a PD. It is used by\r
- * THH_mrwm_register_internal() in memory locking and mapping of WQE buffers to physical\r
- * pages. (the mrwm is given a PD handle, and needs to retrieve the associated protection\r
- * context).\r
- */\r
-HH_ret_t THH_uldm_get_protection_ctx( /*IN*/ THH_uldm_t uldm, \r
- /*IN*/ HH_pd_hndl_t pd, \r
- /*OUT*/ MOSAL_protection_ctx_t *prot_ctx_p );\r
-\r
-/******************************************************************************\r
- * Function: THH_uldm_get_num_objs \r
- *\r
- * Arguments:\r
- * uldm\r
- * num_alloc_us_res_p - allocated resource count\r
- * num_alloc_pds_p - allocated PDs count\r
- *\r
- * Returns:\r
- * HH_OK\r
- * HH_EINVAL - Invalid parameter (bad handle, or both return value ptrs are NULL\r
- *\r
- * Description:\r
- * For debugging -- returns allocated resource count and/or number of allocated PDs.\r
- * either num_alloc_us_res_p or num_alloc_pds_p (but not both) may be NULL;\r
- */\r
-HH_ret_t THH_uldm_get_num_objs( /*IN*/ THH_uldm_t uldm, u_int32_t *num_alloc_us_res_p,\r
- u_int32_t *num_alloc_pds_p);\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_THH_ULDM_PRIV_H\r
-#define H_THH_ULDM_PRIV_H\r
-\r
-#include <mtl_common.h>\r
-#include <cr_types.h>\r
-#include <MT23108_PRM.h>\r
-#include <thh_uldm.h>\r
-#include <tmrwm.h>\r
-#include <tddrmm.h>\r
-#include <udavm.h>\r
-#include <thh_hob.h>\r
-#include <epool.h>\r
-#include <tlog2.h>\r
-\r
-typedef struct __THH_uldm_epool_st {\r
- unsigned long next;\r
- unsigned long prev;\r
-} __THH_uldm_epool_t;\r
-\r
-typedef struct __THH_uldm_uar_data_st {\r
- MOSAL_protection_ctx_t prot_ctx;\r
- MT_virt_addr_t virt_addr;\r
-} __THH_uldm_uar_data_t;\r
-\r
-\r
-typedef struct __THH_uldm_pd_data_st {\r
- MOSAL_protection_ctx_t prot_ctx;\r
- VAPI_lkey_t lkey; /* for freeing non-privileged UDAV table with a PD */\r
- MT_virt_addr_t udav_table_ddr_virt_addr;\r
- MT_phys_addr_t udav_table_ddr_phys_addr;\r
- MT_size_t udav_table_size;\r
-} __THH_uldm_pd_data_t;\r
-\r
-typedef struct THH_uldm_uar_entry_st {\r
- union {\r
- __THH_uldm_epool_t epool;\r
- __THH_uldm_uar_data_t uar;\r
- } u1;\r
- u_int8_t valid;\r
-} THH_uldm_uar_entry_t;\r
-\r
-typedef struct THH_uldm_pd_entry_st {\r
- union {\r
- __THH_uldm_epool_t epool;\r
- __THH_uldm_pd_data_t pd;\r
- } u1;\r
- u_int8_t valid;\r
-} THH_uldm_pd_entry_t;\r
-\r
-typedef struct THH_uldm_st {\r
- THH_hob_t hob; /* saved during uldm create */\r
- MT_phys_addr_t uar_base; \r
- u_int8_t log2_max_uar;\r
- u_int32_t max_uar;\r
- u_int8_t log2_uar_pg_sz;\r
- u_int32_t max_pd; \r
- THH_uldm_uar_entry_t *uldm_uar_table;\r
- THH_uldm_pd_entry_t *uldm_pd_table;\r
- EPool_t uar_list;\r
- EPool_t pd_list;\r
- EPool_meta_t uar_meta;\r
- EPool_meta_t pd_meta;\r
-} THH_uldm_obj_t;\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include <epool.h>\r
-#include <mtl_common.h>\r
-\r
-typedef unsigned long Index_t;\r
-\r
-#if EPOOL_FIFO\r
-#define EPOOL_STATE_DEBUG4(s, epool, index) \\r
- MTL_DEBUG4("%s: %p index=%lu allocs=%lu deallocs=%lu head=%lu tail=%lu\n", \\r
- s, epool, index, epool->allocations, epool->deallocations, \\r
- epool->head, epool->tail)\r
-#else\r
-#define EPOOL_STATE_DEBUG4(s, epool, index) \\r
- MTL_DEBUG4("%s: %p index=%lu allocs=%lu deallocs=%lu head=%lu\n", \\r
- s, epool, index, epool->allocations, epool->deallocations, \\r
- epool->head)\r
-#endif\r
-\r
-static Index_t get_next(EPool_t* epool, Index_t index) {\r
- Index_t next;\r
-\r
- if (index >= epool->size) {\r
- MTL_ERROR1("epool get_next invalid parameter epool=%p index=%lu\n", epool, index);\r
- return EPOOL_NULL;\r
- }\r
- next = epool->list[index];\r
- MTL_DEBUG4("get_next ep=%p index=%lu list=%p next=%lu\n",\r
- epool, index, epool->list, next);\r
- \r
- if ((next != EPOOL_NULL) && (next >= epool->size)) {\r
- MTL_ERROR1("epool get_next corruption epool=%p index=%lu next=%lu\n", epool, index, next);\r
- return EPOOL_NULL;\r
- }\r
- return next;\r
-}\r
-\r
-static void set_next(EPool_t* epool, Index_t index, Index_t next) {\r
- if (index >= epool->size) {\r
- MTL_ERROR1("epool set_next invalid parameter epool=%p index=%lu\n", epool, index);\r
- return;\r
- }\r
- if ((next != EPOOL_NULL) && (next >= epool->size)) {\r
- MTL_ERROR1("epool set_next invalid parameter epool=%p index=%lu next=%lu\n", epool, index, next);\r
- return;\r
- }\r
- \r
- epool->list[index] = next;\r
- MTL_DEBUG4("set_next ep=%p index=%lu list=%p next=%lu\n",\r
- epool, index, epool->list, next);\r
-}\r
-\r
-/************************************************************************/\r
-/************************************************************************/\r
-/* interface functions */\r
-\r
-/************************************************************************/\r
-void epool_init(EPool_t* epool) {\r
- unsigned int i;\r
-\r
- MTL_TRACE1(MT_FLFMT("{ epool_init: epool=%p size=0x%lx"), epool, epool->size);\r
- MOSAL_spinlock_init(&epool->spinlock);\r
- epool->head = EPOOL_NULL;\r
-#if EPOOL_FIFO\r
- epool->tail = EPOOL_NULL;\r
-#endif\r
- epool->allocations = 0;\r
- epool->deallocations = 0;\r
- i = epool->size * sizeof(Index_t);\r
-\r
- if (i > PAGE_SIZE) {\r
- epool->list = VMALLOC(i);\r
- } else\r
- epool->list = MALLOC(i);\r
-\r
- if (epool->list == NULL) {\r
- MTL_ERROR1("%s memory allocation failed size=%d\n", __func__, i);\r
- return;\r
- }\r
- for(i = epool->size; i;) {\r
- epool_free(epool, --i);\r
- }\r
- // reset this for consistency, since epool_free incremented it\r
- epool->deallocations = 0;\r
- MTL_TRACE1(MT_FLFMT("} epool_init: epool=%p"), epool);\r
-}\r
-\r
-/************************************************************************/\r
-void epool_cleanup(EPool_t* epool) {\r
- if (epool->list != NULL) {\r
- if (epool->size * sizeof(Index_t) > PAGE_SIZE) {\r
- VFREE(epool->list);\r
- } else\r
- FREE(epool->list);\r
- epool->list = NULL;\r
- }\r
-}\r
-\r
-/************************************************************************/\r
-Index_t epool_alloc(EPool_t* epool) {\r
- Index_t index;\r
-\r
- MTL_TRACE4(MT_FLFMT("{ epool_alloc: epool=%p"), epool);\r
-\r
- MOSAL_spinlock_dpc_lock(&epool->spinlock);\r
- if ((index = epool->head) != EPOOL_NULL) {\r
- epool->head = get_next(epool, index);\r
- ++epool->allocations;\r
- }\r
- MOSAL_spinlock_unlock(&epool->spinlock);\r
- EPOOL_STATE_DEBUG4("epool_alloc", epool, index);\r
- return index;\r
-}\r
-\r
-/************************************************************************/\r
-void epool_free(EPool_t* epool, Index_t index) {\r
-\r
-#if EPOOL_FIFO\r
- set_next(epool, index, EPOOL_NULL);\r
- MOSAL_spinlock_dpc_lock(&epool->spinlock);\r
- if (epool->head == EPOOL_NULL) {\r
- epool->head = index;\r
- } else {\r
- Index_t check;\r
- check = get_next(epool, epool->tail);\r
- if (check != EPOOL_NULL) {\r
- MTL_ERROR1("epool_free check next failed tail=%lu check=%lu\n", epool->tail, check);\r
- MTL_ERROR1("epool_free ignoring bad tail for now");\r
- }\r
-\r
- set_next(epool, epool->tail, index);\r
- check = get_next(epool, epool->tail);\r
- if (check != index) {\r
- MTL_ERROR1("epool_free check tail failed tail=%lu check=%lu\n", epool->tail, check);\r
- MTL_ERROR1("epool_free ignoring bad set for now");\r
- }\r
- }\r
- epool->tail = index;\r
-#else /* EPOOL_FIFO */\r
- MOSAL_spinlock_dpc_lock(&epool->spinlock);\r
- set_next(epool, index, epool->head);\r
- epool->head = index;\r
-#endif /* EPOOL_FIFO */\r
- ++epool->deallocations;\r
- MOSAL_spinlock_unlock(&epool->spinlock);\r
- EPOOL_STATE_DEBUG4("epool_free", epool, index);\r
-}\r
-\r
-/************************************************************************/\r
-// Note on failure returns number not reserved, however no indication\r
-// of which were actually reserved. Ok for now, callers mostly ignore\r
-// return value and always reserve immediately after init\r
-unsigned long epool_reserve(EPool_t *epool, unsigned long start_index, unsigned long res_size) {\r
-#if EPOOL_FIFO\r
- unsigned long i;\r
- unsigned long j;\r
- unsigned long unreserved = 0;\r
- Index_t index;\r
- MT_bool found;\r
-\r
- MTL_DEBUG4(MT_FLFMT("{ epool_reserve: epool=%p, start=0x%lx, sz=0x%lx"), \r
- epool, start_index, res_size);\r
- for(i = start_index; i < start_index + res_size; ++i) {\r
- found = FALSE;\r
- for(j = 0; j < epool->size; ++j) {\r
- index = epool_alloc(epool);\r
- if (index == EPOOL_NULL)\r
- break;\r
- if (index == i) {\r
- found = TRUE;\r
- break;\r
- }\r
- epool_free(epool, index); // take advantage of fifo behavior of list now\r
- }\r
- if (!found) {\r
- ++unreserved;\r
- MTL_ERROR1("epool reserve failure epool=%p index=%lu\n", epool, i);\r
- }\r
- }\r
- MTL_DEBUG4(MT_FLFMT("} epool_reserve unreserved=%lu"), unreserved);\r
- return unreserved;\r
-#else /* EPOOL_FIFO */\r
- Index_t end_index = start_index + res_size;\r
- Index_t index;\r
- Index_t prev;\r
-\r
- MTL_DEBUG4(MT_FLFMT("{ epool_reserve: epool=%p, start=0x%lx, sz=0x%lx"), \r
- epool, start_index, res_size);\r
- MOSAL_spinlock_dpc_lock(&epool->spinlock);\r
- index = epool->head;\r
- prev = EPOOL_NULL; // indicates at head\r
- while ((index != EPOOL_NULL) && (res_size)) {\r
- if ((start_index <= index) && (index < end_index))\r
- {\r
- // allocate index\r
- if (prev == EPOOL_NULL) {\r
- epool->head = get_next(epool, index);\r
- } else {\r
- set_next(epool, prev, get_next(epool, index));\r
- }\r
- ++epool->allocations;\r
- EPOOL_STATE_DEBUG4("epool_reserve", epool, index);\r
- index = get_next(epool, index);\r
- } else {\r
- // skip index\r
- prev = index;\r
- index = get_next(epool, index);\r
- }\r
- }\r
- MOSAL_spinlock_unlock(&epool->spinlock);\r
- MTL_DEBUG4(MT_FLFMT("} epool_reserve unreserved=%lu"), res_size);\r
- return res_size;\r
-#endif /* EPOOL_FIFO */\r
-}\r
-\r
-/************************************************************************/\r
-void epool_unreserve(EPool_t *epool, unsigned long start_index, unsigned long res_size) {\r
- MTL_DEBUG4(MT_FLFMT("{ epool_unreserve: epool=%p, start=0x%lx, sz=0x%lx"), \r
- epool, start_index, res_size);\r
-\r
- while(res_size--) {\r
- epool_free(epool, start_index + res_size);\r
- }\r
- MTL_DEBUG4(MT_FLFMT("} epool_unreserve"));\r
-}\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#if !defined(_EPOOL_H)\r
-#define _EPOOL_H\r
-\r
-#if !defined(EPOOL_TEST)\r
-# include <mosal.h>\r
-#endif\r
-\r
-\r
-#define EPOOL_NULL ((const u_int32_t) ~0ul)\r
-\r
-#define EPOOL_FIFO 0\r
-\r
-typedef struct\r
-{ \r
- /* all in bytes */\r
- // these fields are no longer used, but are retained for backward\r
- // compatibility with existing callers of epool functions\r
- unsigned int entry_size; /* size of user entry structure */\r
- /* offsets within user entry to: */\r
- unsigned int prev_struct_offset; /* unsigned long 'prev' index */\r
- unsigned int next_struct_offset; /* unsigned long 'next' index */\r
-} EPool_meta_t;\r
-\r
-typedef struct\r
-{ \r
- void* entries; /* allocated by user */\r
- unsigned long size; /* number of entries */\r
- const EPool_meta_t* meta; /* can be shared */\r
- unsigned long head; /* used internally */\r
-#if EPOOL_FIFO\r
- unsigned long tail; /* used internally */\r
-#endif\r
- unsigned long *list;\r
- unsigned long allocations;\r
- unsigned long deallocations;\r
- MOSAL_spinlock_t spinlock; /* used internally */\r
-} EPool_t;\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Notes:\r
- * \r
- * + The complexity of \r
- * epool_alloc(.), epool_free(..)\r
- * is constant O(1).\r
- * + The complexity of epool_reserve(...) is\r
- * O(res_size) where n is the size of the free list\r
- * + The complexity of epool_unreserve(...) is O(res_size).\r
- */ \r
-\r
-/* Function: epool_init\r
- * Arguments:\r
- * l - EPool_t to initialize. User is reponsible to pre-allocate\r
- * l->entries, and set l->size and l->meta accordingly.\r
- * Return:\r
- * None.\r
- */\r
-extern void epool_init(EPool_t* l);\r
-\r
-/* Function: epool_cleanup\r
- * Arguments:\r
- * l - EPool_t to clean. Note that entries are not freed.\r
- * Return:\r
- * None.\r
- * Currently does noting.\r
- */\r
-extern void epool_cleanup(EPool_t* l);\r
-\r
-/* Function: epool_alloc\r
- * Arguments:\r
- * l - EPool_t to get a free index from.\r
- * Return:\r
- * An index within l->entries, or EPOOL_NULL.\r
- */\r
-extern unsigned long epool_alloc(EPool_t* l); /* EPOOL_NULL iff fail */\r
-\r
-/* Function: epool_free\r
- * Arguments:\r
- * l - EPool_t to free an index to.\r
- * index - Index to free.\r
- * Return:\r
- * None.\r
- */\r
-extern void epool_free(EPool_t* l, unsigned long index);\r
-\r
-/* Function: epool_reserve\r
- * Arguments:\r
- * l - EPool_t from which to reserve range of indices.\r
- * start_index - start of indices range.\r
- * size - size of range.\r
- * Return:\r
- * 0 for success, or number of un-reserved indices.\r
- */\r
-extern unsigned long epool_reserve(\r
- EPool_t* l,\r
- unsigned long start_index,\r
- unsigned long res_size);\r
-\r
-/* Function: epool_unreserve\r
- * Arguments:\r
- * l - EPool_t from which to unreserve range of indices.\r
- * start_index - start of indices range.\r
- * size - size of range.\r
- * Return:\r
- * None.\r
- *\r
- * Notes: It is the responsiblity of the caller to provide valid range.\r
- */\r
-extern void epool_unreserve(\r
- EPool_t* l,\r
- unsigned long start_index,\r
- unsigned long res_size);\r
-\r
-#ifdef __cplusplus\r
- }\r
-#endif\r
-\r
-#endif /* _EPOOL_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "extbuddy.h"\r
-#include <vip_hashp.h>\r
-#include <tlog2.h>\r
-\r
-typedef struct Extbuddy_st\r
-{\r
- u_int8_t log2_min;\r
- u_int8_t log2_max;\r
- VIP_hashp_p_t freelist[32];\r
- u_int32_t available_size;\r
-} Extbuddy_t;\r
-\r
-typedef struct\r
-{\r
- unsigned int curr_size;\r
- unsigned int ptrs_buff_sz;\r
- u_int32_t* ptrs_buff;\r
-} Query_Filler;\r
-\r
-\r
-typedef struct\r
-{\r
- u_int32_t boundary_begin;\r
- u_int32_t boundary_end;\r
- u_int32_t target_size;\r
- u_int32_t* pp; /* address of desired pointer to return*/\r
- u_int32_t chunk_start;\r
- u_int8_t chunk_log2sz;\r
- u_int32_t chunk_size; /* 1ul << chunk_log2sz --- cahced */\r
-} Bound_Ptr;\r
-\r
-\r
-/* The following structure serves the reserve routines callbacks.\r
- * It is designed for simple cached values rather than compactness.\r
- */\r
-typedef struct\r
-{\r
- Extbuddy_t* xbdy;\r
- u_int32_t res_begin;\r
- u_int32_t res_size;\r
- u_int32_t res_end; /* = begin + size */\r
- u_int32_t total_intersection; /* should reach size */\r
- unsigned long n_segments[32];\r
- unsigned long n_segments_total;\r
- u_int32_t* currseg;\r
- u_int32_t* currseg_end;\r
- int8_t curr_log2sz;\r
-} Reserve_Segments;\r
-\r
-\r
-\r
-/************************************************************************/\r
-/************************************************************************/\r
-/* private functions */\r
-\r
-\r
-/************************************************************************/\r
-/* $$ [a_0,a_1) \cap [b_0,b_1) $$ %% (TeX format) */\r
-/* Note the half open segments: $ [m,n) = [m, n-1] $ */\r
-static MT_bool intersects(\r
- u_int32_t a0, u_int32_t a1,\r
- u_int32_t b0, u_int32_t b1\r
-)\r
-{\r
- return ((b0 < a1) && (a0 < b1));\r
-} /* intersects */\r
-\r
-\r
-/************************************************************************/\r
-static u_int32_t intersection_size(\r
- u_int32_t a0, u_int32_t a1,\r
- u_int32_t b0, u_int32_t b1\r
-)\r
-{\r
- u_int32_t x = (intersects(a0, a1, b0, b1)\r
- ? (a1 < b1 ? a1 : b1) - (a0 < b0 ? b0 : a0) /* min(right) - max(left) */\r
- : 0);\r
- return x;\r
-} /* intersection_size */\r
-\r
-\r
-/************************************************************************/\r
-/* Fix given log2_sz to minimal size */\r
-static u_int8_t fix_log2(Extbuddy_t* xbdy, u_int8_t* log2_sz_p)\r
-{\r
- if (*log2_sz_p < xbdy->log2_min)\r
- {\r
- *log2_sz_p = xbdy->log2_min;\r
- }\r
- return *log2_sz_p;\r
-} /* fix_log2 */\r
-\r
-\r
-/************************************************************************/\r
-static MT_bool create_lists(Extbuddy_t* xbdy)\r
-{\r
- MT_bool ok = TRUE;\r
- int clg2;\r
- for (clg2 = xbdy->log2_min; ok && (clg2 <= xbdy->log2_max); ++clg2)\r
- {\r
- if (VIP_hashp_create(0, &(xbdy->freelist[clg2])) != VIP_OK)\r
- {\r
- ok = FALSE;\r
- }\r
- }\r
- return ok;\r
-} /* create_lists */\r
-\r
-\r
-/************************************************************************/\r
-static void destroy_lists(Extbuddy_t* xbdy)\r
-{\r
- int clg2;\r
- for (clg2 = xbdy->log2_min; clg2 <= xbdy->log2_max; ++clg2)\r
- {\r
- VIP_hashp_p_t ph = xbdy->freelist[clg2];\r
- if (ph)\r
- {\r
- (void)VIP_hashp_destroy(ph, 0, 0);\r
- xbdy->freelist[clg2] = NULL;\r
- }\r
- }\r
-} /* destroy_lists */\r
-\r
-\r
-/************************************************************************/\r
-static MT_bool init_lists(Extbuddy_t* xbdy)\r
-{\r
- MT_bool ok = create_lists(xbdy);\r
- MTL_DEBUG4(MT_FLFMT("ok=%d"), ok);\r
- if (ok)\r
- {\r
- int chunk = xbdy->log2_max;\r
- u_int32_t chunk_size = 1ul << chunk;\r
- u_int32_t offset = 0, next = offset + chunk_size;\r
- while (ok && (next <= xbdy->available_size) && (chunk > xbdy->log2_min))\r
- {\r
- //MTL_DEBUG4(MT_FLFMT("chunk=%d, offset=0x%x"), chunk, offset);\r
- ok = (VIP_hashp_insert(xbdy->freelist[chunk], offset, 0) == VIP_OK);\r
- offset = next;\r
- do\r
- {\r
- --chunk;\r
- chunk_size >>= 1;\r
- next = offset + chunk_size;\r
- } while ((next > xbdy->available_size) && (chunk > xbdy->log2_min));\r
- }\r
- /* sub divide the rest to the segments of minimum chunks */\r
- while (ok && (next <= xbdy->available_size))\r
- {\r
- offset = next;\r
- //MTL_DEBUG4(MT_FLFMT("chunk=%d, offset=0x%x"), chunk, offset);\r
- ok = (VIP_hashp_insert(xbdy->freelist[chunk], offset, 0) == VIP_OK);\r
- next += chunk_size;\r
- }\r
- }\r
- if (!ok)\r
- {\r
- destroy_lists(xbdy);\r
- }\r
- return ok;\r
-} /* init_lists */\r
-\r
-\r
-/************************************************************************/\r
-static int get1p(VIP_hashp_key_t key, VIP_hashp_value_t val, void* vp)\r
-{\r
- u_int32_t p = key;\r
- u_int32_t* pp = (u_int32_t*)vp;\r
- *pp = p;\r
- return 0; /* just one call, and stop traverse */\r
-} /* get1p */\r
-\r
-\r
-/************************************************************************/\r
-static int get1p_bound(VIP_hashp_key_t key, VIP_hashp_value_t val, void* vp)\r
-{\r
- u_int32_t p = key;\r
- Bound_Ptr* bp = (Bound_Ptr*)vp;\r
- u_int32_t xsize = intersection_size(bp->boundary_begin, bp->boundary_end,\r
- p, p + bp->chunk_size);\r
- int found = (bp->target_size <= xsize);\r
- if (found)\r
- {\r
- *bp->pp = (p < bp->boundary_begin ? bp->boundary_begin : p);\r
- bp->chunk_start = p;\r
- }\r
- return !found;\r
-} /* get1p_bound */\r
-\r
-\r
-/************************************************************************/\r
-static int query_fill(VIP_hashp_key_t key, VIP_hashp_value_t val, void* vp)\r
-{\r
- u_int32_t p = key;\r
- Query_Filler* filler_p = (Query_Filler*)vp;\r
- int go_on = (filler_p->curr_size < filler_p->ptrs_buff_sz);\r
- if (go_on)\r
- {\r
- filler_p->ptrs_buff[filler_p->curr_size++] = p;\r
- /* go_on = (filler_p->curr_size < filler_p->ptrs_buff_sz);, no real need */\r
- }\r
- return go_on;\r
-} /* query_fill */\r
-\r
-\r
-/************************************************************************/\r
-/* Reserve related functions */\r
-\r
-\r
-/************************************************************************/\r
-static int reserve_pass1(VIP_hashp_key_t key, VIP_hashp_value_t val, void* vp)\r
-{\r
- MT_bool more;\r
- u_int32_t p = key;\r
- Reserve_Segments* rs = (Reserve_Segments*)vp;\r
- u_int8_t log2sz = rs->curr_log2sz;\r
- u_int32_t xsize = intersection_size(rs->res_begin, rs->res_end,\r
- p, p + (1ul << log2sz));\r
- if (xsize != 0)\r
- {\r
- rs->total_intersection += xsize;\r
- ++rs->n_segments_total;\r
- ++rs->n_segments[log2sz];\r
- }\r
- more = (rs->total_intersection < rs->res_size);\r
- return more;\r
-} /* reserve_pass1 */\r
-\r
-\r
-/************************************************************************/\r
-static int reserve_pass2(VIP_hashp_key_t key, VIP_hashp_value_t val, void* vp)\r
-{\r
- MT_bool more;\r
- u_int32_t p = key;\r
- Reserve_Segments* rs = (Reserve_Segments*)vp;\r
- u_int8_t log2sz = rs->curr_log2sz;\r
- if (intersects(rs->res_begin, rs->res_end, p, p + (1ul << log2sz)))\r
- {\r
- *rs->currseg++ = p;\r
- }\r
- more = (rs->currseg != rs->currseg_end);\r
- return more;\r
-} /* reserve_pass2 */\r
-\r
-\r
-/************************************************************************/\r
-/* Recursive. Maximal depth is by log2sz */\r
-static MT_bool reserve_breaks_insert(\r
- Reserve_Segments* rs, \r
- u_int32_t p, \r
- u_int8_t log2sz\r
-)\r
-{\r
- MT_bool ok = TRUE;\r
- MTL_DEBUG4(MT_FLFMT("{breaks_insert: p=0x%x, log2sz=%d"), p, log2sz);\r
- if (log2sz > rs->xbdy->log2_min)\r
- {\r
- unsigned int i2 = 0;\r
- u_int32_t half = (1ul << --log2sz);\r
- for (i2 = 0; i2 != 2; ++i2, p += half)\r
- {\r
- u_int32_t xsize = intersection_size(rs->res_begin, rs->res_end, \r
- p, p + half);\r
- // MTL_DEBUG4(MT_FLFMT("p=0x%x, xsize=0x%x"), p, xsize);\r
- if (xsize == 0) /* we can use the whole half */\r
- {\r
- VIP_common_ret_t \r
- vrc = VIP_hashp_insert(rs->xbdy->freelist[log2sz], p, 0);\r
- ok = (vrc == VIP_OK);\r
- if (ok)\r
- {\r
- rs->xbdy->available_size += 1ul << log2sz;\r
- }\r
- }\r
- else\r
- {\r
- if (xsize != half) /* we can use part of the half */\r
- {\r
- ok = reserve_breaks_insert(rs, p, log2sz) && ok; /* recursive */\r
- //MTL_DEBUG4(MT_FLFMT("ok=%d"), ok);\r
- }\r
- }\r
- }\r
- } \r
- MTL_DEBUG4(MT_FLFMT("}breaks_insert ok=%d"), (int)ok);\r
- return ok;\r
-} /* reserve_breaks_insert */\r
-\r
-\r
-/************************************************************************/\r
-static MT_bool reserve_break(Reserve_Segments* rs)\r
-{\r
- MT_bool ok = TRUE;\r
- u_int32_t p = *rs->currseg;\r
- u_int8_t log2sz = rs->curr_log2sz;\r
- ok = (VIP_hashp_erase(rs->xbdy->freelist[log2sz], p, 0) == VIP_OK);\r
- if (ok)\r
- {\r
- rs->xbdy->available_size -= 1ul << log2sz;\r
- ok = reserve_breaks_insert(rs, p, log2sz);\r
- }\r
- return ok;\r
-} /* reserve_break */\r
-\r
-\r
-/************************************************************************/\r
-/************************************************************************/\r
-/* interface functions */\r
-\r
-\r
-/************************************************************************/\r
-Extbuddy_hndl extbuddy_create(u_int32_t size, u_int8_t log2_min_chunk)\r
-{\r
- u_int8_t log2_max = floor_log2(size);\r
- Extbuddy_t* xbdy = NULL;\r
- if (log2_min_chunk <= log2_max)\r
- {\r
- xbdy = TMALLOC(Extbuddy_t);\r
- }\r
- if (xbdy)\r
- {\r
- u_int32_t mask = (1ul << log2_min_chunk) - 1;\r
- memset(xbdy, 0, sizeof(Extbuddy_t)); /* in particular, null hash lists */\r
- xbdy->log2_min = log2_min_chunk;\r
- xbdy->log2_max = log2_max;\r
- xbdy->available_size = size & ~mask;\r
- MTL_DEBUG4(MT_FLFMT("log2_min=%u, log2_max=%u, avail_size=%u"),\r
- xbdy->log2_min, xbdy->log2_max,xbdy->available_size);\r
- if (!init_lists(xbdy))\r
- {\r
- FREE(xbdy);\r
- xbdy = NULL;\r
- }\r
- }\r
- return xbdy;\r
-} /* extbuddy_create */\r
-\r
-\r
-/************************************************************************/\r
-void extbuddy_destroy(Extbuddy_hndl xbdy)\r
-{\r
- destroy_lists(xbdy);\r
- FREE(xbdy);\r
-} /* extbuddy_destroy */\r
-\r
-\r
-/************************************************************************/\r
-u_int32_t extbuddy_alloc(Extbuddy_hndl xbdy, u_int8_t log2_sz)\r
-{\r
- u_int32_t p = EXTBUDDY_NULL;\r
- u_int32_t log2_max = xbdy->log2_max;\r
- u_int8_t sz = fix_log2(xbdy, &log2_sz);\r
- for ( ; (sz <= log2_max) && !extbuddy_chunks_available(xbdy, sz); ++sz);\r
- if (sz <= xbdy->log2_max) /* we found a sufficient chunk */\r
- {\r
- u_int8_t split_sz = log2_sz;\r
- VIP_hashp_traverse(xbdy->freelist[sz], &get1p, &p);\r
- VIP_hashp_erase(xbdy->freelist[sz], p, 0); /* can't fail */\r
-\r
- /* If bigger than we need, we split chunk of 2^{split_sz} by halves,\r
- * inserting chunks to free lists.\r
- */\r
- while (split_sz != sz)\r
- {\r
- u_int32_t split = p + (1ul << split_sz);\r
- if (VIP_hashp_insert(xbdy->freelist[split_sz], split, 0) != VIP_OK)\r
- {\r
- xbdy->available_size -= (1ul << split_sz); /* :)bad:(. */\r
- }\r
- ++split_sz;\r
- }\r
- xbdy->available_size -= (1ul << log2_sz);\r
- }\r
- return p;\r
-} /* extbuddy_alloc */\r
-\r
-\r
-/************************************************************************/\r
-u_int32_t extbuddy_alloc_bound(\r
- Extbuddy_t* xbdy,\r
- u_int8_t log2_sz,\r
- u_int32_t area_start,\r
- u_int32_t area_size\r
-)\r
-{\r
- u_int32_t p = EXTBUDDY_NULL;\r
- u_int32_t log2_max = xbdy->log2_max;\r
- u_int8_t sz = fix_log2(xbdy, &log2_sz);\r
- u_int32_t target_size = (1ul << log2_sz);\r
- Bound_Ptr bp;\r
-\r
- // Align the boundary beginning to the target size */\r
- bp.boundary_begin = area_start & ~(target_size - 1);\r
- if (bp.boundary_begin != area_start) { bp.boundary_begin += target_size; }\r
- bp.boundary_end = area_start + area_size;\r
- bp.target_size = 1ul << log2_sz;\r
- bp.pp = &p;\r
-\r
- for (; (p == EXTBUDDY_NULL) && (sz <= log2_max); ++sz)\r
- {\r
- if (extbuddy_chunks_available(xbdy, sz) != 0)\r
- {\r
- bp.chunk_log2sz = sz;\r
- bp.chunk_size = 1ul << sz;\r
- VIP_hashp_traverse(xbdy->freelist[sz], &get1p_bound, &bp);\r
- if (p != EXTBUDDY_NULL)\r
- {\r
- u_int32_t buddy = p;\r
- u_int8_t split_sz = log2_sz;\r
- VIP_hashp_erase(xbdy->freelist[sz], bp.chunk_start, 0); /* can't fail */\r
-\r
- /* If bigger than we need, we split chunk of 2^{split_sz} by halves,\r
- * inserting chunks to free lists. This is more complicated than\r
- * the above (non bound) extbuddy_alloc(...), since we keep\r
- * the returned p, which is not necessarily chunk_start.\r
- * So we use the buddy trick again.\r
- */\r
- while (split_sz != sz)\r
- {\r
- u_int32_t buddy_bit = 1ul << split_sz;\r
- buddy ^= buddy_bit;\r
- if (VIP_hashp_insert(xbdy->freelist[split_sz], buddy, 0) != VIP_OK)\r
- {\r
- xbdy->available_size -= (1ul << split_sz); /* :)bad:(. */\r
- }\r
- buddy &= ~buddy_bit;\r
- ++split_sz;\r
- }\r
- xbdy->available_size -= (1ul << log2_sz);\r
- }\r
- }\r
- }\r
- return p;\r
-} /* extbuddy_alloc_bound */\r
-\r
-\r
-/************************************************************************/\r
-/* p is assumed to be alligned to 1<<log2sz */\r
-MT_bool extbuddy_free(Extbuddy_t* xbdy, u_int32_t p, u_int8_t log2sz)\r
-{\r
- MT_bool ok = TRUE;\r
- u_int8_t slot = fix_log2(xbdy, &log2sz);\r
- u_int32_t buddy = p ^ (1ul << slot); /* it is buddy system after all */\r
- if (slot > xbdy->log2_max) {\r
- MTL_ERROR1(MT_FLFMT("extbuddy_free: slot too large: %d (max is %d"), slot, xbdy->log2_max);\r
- return FALSE;\r
- }\r
- while ((slot <= xbdy->log2_max) &&\r
- VIP_hashp_erase(xbdy->freelist[slot], buddy, 0) == VIP_OK)\r
- {\r
- p &= ~(1ul << slot); /* unite with buddy */\r
- ++slot;\r
- buddy = p ^ (1ul << slot);\r
- }\r
- ok = (VIP_hashp_insert(xbdy->freelist[slot], p, 0) == VIP_OK);\r
- if (ok)\r
- {\r
- xbdy->available_size += (1ul << log2sz);\r
- }\r
- return ok;\r
-} /* extbuddy_free */\r
-\r
-\r
-/************************************************************************/\r
-unsigned int extbuddy_chunks_available(Extbuddy_t* xbdy, u_int8_t log2sz)\r
-{\r
- unsigned int n = 0;\r
- if (xbdy->log2_min <= log2sz && log2sz <= xbdy->log2_max)\r
- {\r
- n = VIP_hashp_get_num_of_objects(xbdy->freelist[log2sz]);\r
- }\r
- return n;\r
-} /* extbuddy_chunks_available */\r
-\r
-\r
-/************************************************************************/\r
-u_int32_t extbuddy_total_available(Extbuddy_t* xbdy)\r
-{\r
- return xbdy->available_size;\r
-} /* extbuddy_total_available */\r
-\r
-\r
-/************************************************************************/\r
-u_int8_t extbuddy_log2_max_available(Extbuddy_t* xbdy)\r
-{\r
- u_int8_t log2max = -1;\r
- u_int8_t chunk = xbdy->log2_max + 1;\r
- while ((log2max == -1) && (--chunk >= (int)xbdy->log2_min))\r
- {\r
- if (VIP_hashp_get_num_of_objects(xbdy->freelist[chunk]) > 0)\r
- {\r
- log2max = chunk;\r
- }\r
- }\r
- return log2max;\r
-} /* extbuddy_log2_max_available */\r
-\r
-\r
-/************************************************************************/\r
-void extbuddy_query_chunks(\r
- Extbuddy_t* xbdy,\r
- u_int8_t log2sz,\r
- unsigned int ptrs_buff_sz,\r
- u_int32_t* ptrs_buff\r
-)\r
-{\r
- Query_Filler filler;\r
- filler.curr_size = 0;\r
- filler.ptrs_buff_sz = ptrs_buff_sz;\r
- filler.ptrs_buff = ptrs_buff;\r
- VIP_hashp_traverse(xbdy->freelist[log2sz], &query_fill, &filler);\r
-} /* extbuddy_query_chunks */\r
-\r
-\r
-/************************************************************************/\r
-/* We go through the free lists, break free segments that intersect the\r
- * reserved area and insert the non reserved sub-segments into smaller\r
- * chunk lists.\r
- *\r
- * Three passes:\r
- * 1. See if reservation is possible and count the number of\r
- * free segments involved.\r
- * 2. Collect the involved segments.\r
- * 3. Go thru the involved segments.\r
- * Break each segment by calling a recursive function.\r
- *\r
- * Note that the first two passes traverse the underlying hash tables.\r
- * These tables are not modified until the third pass.\r
- */\r
-MT_bool extbuddy_reserve(Extbuddy_t* xbdy, u_int32_t p, u_int32_t size)\r
-{\r
- MT_bool ok = TRUE;\r
- Reserve_Segments rs;\r
- u_int32_t* segs = NULL;\r
- u_int8_t log2_min_used = xbdy->log2_max;\r
-\r
- memset(&rs, 0, sizeof(rs)); /* clumsy but simple initialization */\r
- rs.xbdy = xbdy;\r
- rs.res_begin = p;\r
- rs.res_size = size;\r
- rs.res_end = p + size;\r
-\r
- /* 1st pass */\r
- MTL_DEBUG4(MT_FLFMT("1st pass"));\r
- for (rs.curr_log2sz = xbdy->log2_max;\r
- (rs.curr_log2sz >= xbdy->log2_min) && (rs.total_intersection < size);\r
- --rs.curr_log2sz)\r
- {\r
- VIP_hashp_traverse(xbdy->freelist[rs.curr_log2sz], &reserve_pass1, &rs);\r
- if (rs.n_segments[rs.curr_log2sz])\r
- {\r
- log2_min_used = rs.curr_log2sz;\r
- }\r
- }\r
-\r
-\r
- ok = (rs.total_intersection == size);\r
- segs = (ok ? TNVMALLOC(u_int32_t, rs.n_segments_total) : NULL);\r
- ok = (segs != NULL);\r
-\r
- if (ok)\r
- {\r
- /* 2nd pass */\r
- MTL_DEBUG4(MT_FLFMT("2nd pass"));\r
- rs.currseg = segs;\r
- for (rs.curr_log2sz = xbdy->log2_max; rs.curr_log2sz >= log2_min_used;\r
- --rs.curr_log2sz)\r
- {\r
- if (rs.n_segments[rs.curr_log2sz])\r
- {\r
- rs.currseg_end = rs.currseg + rs.n_segments[rs.curr_log2sz];\r
- VIP_hashp_traverse(xbdy->freelist[rs.curr_log2sz], &reserve_pass2, &rs);\r
- }\r
- }\r
-\r
- /* 3rd pass */\r
- MTL_DEBUG4(MT_FLFMT("3rd pass"));\r
- rs.currseg = segs;\r
- for (rs.curr_log2sz = xbdy->log2_max; rs.curr_log2sz >= log2_min_used;\r
- --rs.curr_log2sz)\r
- {\r
- //MTL_DEBUG4(MT_FLFMT("curr_log2sz=%d"), rs.curr_log2sz);\r
- rs.currseg_end = rs.currseg + rs.n_segments[rs.curr_log2sz];\r
- for (; rs.currseg != rs.currseg_end; ++rs.currseg)\r
- {\r
- ok = reserve_break(&rs) && ok;\r
- }\r
- }\r
- }\r
-\r
- if (segs) { VFREE(segs); }\r
- return ok;\r
-} /* extbuddy_reserve */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#if !defined(_ExtBuddy_H)\r
-#define _ExtBuddy_H\r
-\r
-#include <mtl_common.h>\r
-\r
-typedef struct Extbuddy_st* Extbuddy_hndl;\r
-#define EXTBUDDY_NULL ((const u_int32_t) ~0ul)\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-extern Extbuddy_hndl extbuddy_create(u_int32_t size, u_int8_t log2_min_chunk);\r
-extern void extbuddy_destroy(Extbuddy_hndl handle);\r
-extern u_int32_t extbuddy_alloc(Extbuddy_hndl handle, u_int8_t log2_sz);\r
-extern u_int32_t extbuddy_alloc_bound(\r
- Extbuddy_hndl handle, \r
- u_int8_t log2_sz,\r
- u_int32_t area_start,\r
- u_int32_t area_size\r
- );\r
-extern MT_bool extbuddy_free(\r
- Extbuddy_hndl handle,\r
- u_int32_t p, \r
- u_int8_t log2_sz);\r
-extern unsigned int extbuddy_chunks_available(\r
- Extbuddy_hndl handle, \r
- u_int8_t log2_sz);\r
-extern unsigned int extbuddy_total_available(Extbuddy_hndl handle);\r
-extern u_int8_t extbuddy_log2_max_available(Extbuddy_hndl handle);\r
-extern void extbuddy_query_chunks(\r
- Extbuddy_hndl handle,\r
- u_int8_t log2_sz,\r
- unsigned int ptrs_buff_sz,\r
- u_int32_t* ptrs_buff);\r
-\r
-/* reserve interface */\r
-extern MT_bool extbuddy_reserve( /* Only before any allocation */\r
- Extbuddy_hndl handle,\r
- u_int32_t p,\r
- u_int32_t size /* here, not a log2 */); \r
-\r
-#ifdef __cplusplus\r
- }\r
-#endif\r
-\r
-\r
-#endif /* _ExtBuddy_H */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include <sm_mad.h>\r
-\r
-//--------------------------------------------------------------------------------------------------\r
-//#define FUNCTION_NAME "MyMemCopy"\r
-//--------------------------------------------------------------------------------------------------\r
-static void MyMemCopy(u_int8_t *pDst,u_int8_t *pSrc, u_int16_t nLen)\r
-{\r
-#ifndef MT_BIG_ENDIAN\r
- for(pSrc+=nLen;nLen--;*(pDst++)=*(--pSrc));\r
-#else\r
- for(;nLen--;*(pDst++)=*(pSrc++));\r
-\r
-#endif\r
-}\r
-//--------------------------------------------------------------------------------------------------\r
-\r
-void MadBufPrint( void *madbuf)\r
-{\r
- int i;\r
- u_int8_t *iterator;\r
- iterator = (u_int8_t *)madbuf;\r
-\r
- MTL_DEBUG3("MadBufPrint START\n");\r
- for (i = 0; i < 16; i++) {\r
- MTL_DEBUG3("%02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x\n",\r
- *iterator, *(iterator+1), *(iterator+2), *(iterator+3), \r
- *(iterator+4), *(iterator+5), *(iterator+6), *(iterator+7),\r
- *(iterator+8), *(iterator+9), *(iterator+10), *(iterator+11),\r
- *(iterator+12), *(iterator+13), *(iterator+14), *(iterator+15));\r
- iterator += 16;\r
- }\r
- MTL_DEBUG3("MadBufPrint END\n");\r
-\r
-}\r
-//--------------------------------------------------------------------------------------------------\r
-//#define FUNCTION_NAME "FieldToBuf"\r
-//--------------------------------------------------------------------------------------------------\r
-static void FieldToBuf(u_int8_t cField, u_int8_t *pBuf, u_int16_t nOffset, u_int16_t nLen)\r
-{\r
- pBuf[(nOffset>>3)] &= ~(((0x1<<nLen)-1)<<(8-nLen-(nOffset & 0x7)));\r
- pBuf[(nOffset>>3)] |= ((cField & ((0x1<<nLen)-1))<<(8-nLen-(nOffset & 0x7)));\r
-}\r
-//--------------------------------------------------------------------------------------------------\r
-\r
-//--------------------------------------------------------------------------------------------------\r
-//#define FUNCTION_NAME "BufToField"\r
-//--------------------------------------------------------------------------------------------------\r
-static u_int8_t BufToField(u_int8_t *pBuf,u_int16_t nOffset, u_int16_t nLen)\r
-{\r
- return((pBuf[(nOffset>>3)]>>(8-nLen-(nOffset & 0x7))) & ((0x1<<nLen)-1));\r
-}\r
-//--------------------------------------------------------------------------------------------------\r
-\r
-//--------------------------------------------------------------------------------------------------\r
-//#define FUNCTION_NAME "ZeroToBuf"\r
-//--------------------------------------------------------------------------------------------------\r
-static void ZeroToBuf(u_int8_t *pBuf,u_int16_t nOffset, u_int16_t nLen)\r
-{\r
- pBuf[(nOffset>>3)] &= ~(((0x1<<nLen)-1)<<(8-nLen-(nOffset & 0x7)));\r
-}\r
-//--------------------------------------------------------------------------------------------------\r
-\r
-//--------------------------------------------------------------------------------------------------\r
-//#define FUNCTION_NAME "MADHeaderBuild"\r
-//--------------------------------------------------------------------------------------------------\r
-void MADHeaderBuild(u_int8_t cMgtClass, \r
- u_int16_t wClSp,\r
- u_int8_t cMethod,\r
- u_int16_t wAttrib,\r
- u_int32_t dwModif,\r
- u_int8_t *pSMPBuf)\r
-{\r
- u_int64_t qwMKey;\r
- u_int16_t i;\r
- u_int16_t wDrSLID,wDrDLID;\r
- u_int16_t start_null_index = 32;\r
-\r
- qwMKey=0; //REV\r
- wDrSLID=IB_PERMISSIVE_LID; //REV\r
- wDrDLID=IB_PERMISSIVE_LID; //REV\r
-\r
- pSMPBuf[0]=0x1; //Base Version\r
- pSMPBuf[1]=cMgtClass; //Management Class\r
- pSMPBuf[2]=0x1; //Class Version\r
- pSMPBuf[3]=cMethod; //Method (MSb is 0 - request)\r
- pSMPBuf[5]=pSMPBuf[4]=0; //Status\r
- MyMemCopy((u_int8_t *)pSMPBuf+6,(u_int8_t *)&wClSp,2); //Class Specific\r
- //Transaction ID is filled by packet sending function\r
- MyMemCopy(pSMPBuf+16,(u_int8_t *)&wAttrib,2); //Attribute\r
- pSMPBuf[18]=pSMPBuf[19]=0;\r
- MyMemCopy(pSMPBuf+20,(u_int8_t *)&dwModif,4); //Attribute Modifier\r
- MyMemCopy(pSMPBuf+24,(u_int8_t *)&qwMKey,8); //MKEY\r
- if (cMgtClass == IB_CLASS_DIR_ROUTE) {\r
- MyMemCopy(pSMPBuf+32,(u_int8_t *)&wDrSLID,2); //DrSLID\r
- MyMemCopy(pSMPBuf+34,(u_int8_t *)&wDrDLID,2); //DrDLID\r
- start_null_index = 36;\r
- } \r
-\r
- MTL_DEBUG4(MT_FLFMT("MADHeaderBuild: Class = 0x%02x, Method=0x%02x, Attrib=0x%02x%02x, Attr Mod= 0x%02x%02x%02x%02x"),\r
- cMgtClass,cMethod, *(pSMPBuf+16), *(pSMPBuf+17),*(pSMPBuf+20), \r
- *(pSMPBuf+21), *(pSMPBuf+22), *(pSMPBuf+23));\r
- for (i=start_null_index;i<IB_SMP_DATA_START;pSMPBuf[i++]=0); //Reserved3\r
-}\r
-//--------------------------------------------------------------------------------------------------\r
-\r
-//--------------------------------------------------------------------------------------------------\r
-//#define FUNCTION_NAME "NodeInfoStToMAD"\r
-//--------------------------------------------------------------------------------------------------\r
-void NodeInfoStToMAD(SM_MAD_NodeInfo_t *pNodeInfo,u_int8_t *pSMPBuf)\r
-{\r
- pSMPBuf[IB_SMP_DATA_START]=pNodeInfo->cBaseVersion;\r
- pSMPBuf[IB_SMP_DATA_START+1]=pNodeInfo->cClassVersion;\r
- pSMPBuf[IB_SMP_DATA_START+2]=pNodeInfo->cNodeType;\r
- pSMPBuf[IB_SMP_DATA_START+3]=pNodeInfo->cNumPorts;\r
- //reserved 64 bit\r
- memset(pSMPBuf+4,(u_int8_t)0,8);\r
- memcpy(pSMPBuf+IB_SMP_DATA_START+12,(u_int8_t *)&(pNodeInfo->qwNodeGUID),8);\r
- memcpy(pSMPBuf+IB_SMP_DATA_START+20,(u_int8_t *)&(pNodeInfo->qwPortGUID),8);\r
- MyMemCopy(pSMPBuf+IB_SMP_DATA_START+28,(u_int8_t *)&(pNodeInfo->wPartCap),2);\r
- MyMemCopy(pSMPBuf+IB_SMP_DATA_START+30,(u_int8_t *)&(pNodeInfo->wDeviceID),2);\r
- MyMemCopy(pSMPBuf+IB_SMP_DATA_START+32,(u_int8_t *)&(pNodeInfo->dwRevision),4);\r
- pSMPBuf[IB_SMP_DATA_START+36]=pNodeInfo->cLocalPortNum;\r
- MyMemCopy(pSMPBuf+IB_SMP_DATA_START+37,(u_int8_t *)&(pNodeInfo->dwVendorID),3); //REV will not work when BIG_ENDIAN\r
- memset(pSMPBuf+40,(u_int8_t)0,216);\r
-}\r
-//--------------------------------------------------------------------------------------------------\r
-\r
-\r
-//--------------------------------------------------------------------------------------------------\r
-//#define FUNCTION_NAME "NodeInfoMADToSt"\r
-//--------------------------------------------------------------------------------------------------\r
-void NodeInfoMADToSt(SM_MAD_NodeInfo_t *pNodeInfo,u_int8_t *pSMPBuf)\r
-{\r
- pNodeInfo->cBaseVersion=pSMPBuf[IB_SMP_DATA_START];\r
- pNodeInfo->cClassVersion=pSMPBuf[IB_SMP_DATA_START+1];\r
- pNodeInfo->cNodeType=(IB_node_type_t)pSMPBuf[IB_SMP_DATA_START+2];\r
- pNodeInfo->cNumPorts=pSMPBuf[IB_SMP_DATA_START+3];\r
- //reserved 64 bit\r
- memcpy((u_int8_t *)&(pNodeInfo->qwNodeGUID),pSMPBuf+IB_SMP_DATA_START+12,8);\r
- memcpy((u_int8_t *)&(pNodeInfo->qwPortGUID),pSMPBuf+IB_SMP_DATA_START+20,8);\r
- MyMemCopy((u_int8_t *)&(pNodeInfo->wPartCap),pSMPBuf+IB_SMP_DATA_START+28,2);\r
- MyMemCopy((u_int8_t *)&(pNodeInfo->wDeviceID),pSMPBuf+IB_SMP_DATA_START+30,2);\r
- MyMemCopy((u_int8_t *)&(pNodeInfo->dwRevision),pSMPBuf+IB_SMP_DATA_START+32,4);\r
- pNodeInfo->cLocalPortNum=pSMPBuf[IB_SMP_DATA_START+36];\r
- MyMemCopy((u_int8_t *)&(pNodeInfo->dwVendorID),pSMPBuf+IB_SMP_DATA_START+37,3); //REV will not work when BIG_ENDIAN\r
-}\r
-//--------------------------------------------------------------------------------------------------\r
-\r
-//--------------------------------------------------------------------------------------------------\r
-//#define FUNCTION_NAME "NodeInfoPrint"\r
-//--------------------------------------------------------------------------------------------------\r
-void NodeInfoPrint(SM_MAD_NodeInfo_t *pNodeInfo)\r
-{\r
- MTL_DEBUG3(MT_FLFMT("cBaseVersion: 0x%02X"),pNodeInfo->cBaseVersion);\r
- MTL_DEBUG3(MT_FLFMT("cClassVersion: 0x%02X"),pNodeInfo->cClassVersion);\r
- MTL_DEBUG3(MT_FLFMT("cNodeType: 0x%02X"),pNodeInfo->cNodeType);\r
- MTL_DEBUG3(MT_FLFMT("cNumPorts: 0x%02X"),pNodeInfo->cNumPorts);\r
- MTL_DEBUG3(MT_FLFMT("qwNodeGUID = 0x%02x%02x%02x%02x%02x%02x%02x%02x"), \r
- pNodeInfo->qwNodeGUID[0],pNodeInfo->qwNodeGUID[1],pNodeInfo->qwNodeGUID[2],pNodeInfo->qwNodeGUID[3],\r
- pNodeInfo->qwNodeGUID[4],pNodeInfo->qwNodeGUID[5],pNodeInfo->qwNodeGUID[6],pNodeInfo->qwNodeGUID[7]); //REV show all bytes\r
- MTL_DEBUG3(MT_FLFMT("qwPortGUID = 0x%02x%02x%02x%02x%02x%02x%02x%02x"), \r
- pNodeInfo->qwPortGUID[0],pNodeInfo->qwPortGUID[1],pNodeInfo->qwPortGUID[2],pNodeInfo->qwPortGUID[3],\r
- pNodeInfo->qwPortGUID[4],pNodeInfo->qwPortGUID[5],pNodeInfo->qwPortGUID[6],pNodeInfo->qwPortGUID[7]); //REV show all bytes\r
- MTL_DEBUG3(MT_FLFMT("wPartCap: 0x%04X"),pNodeInfo->wPartCap);\r
- MTL_DEBUG3(MT_FLFMT("wDeviceID: 0x%04X"),pNodeInfo->wDeviceID);\r
- MTL_DEBUG3(MT_FLFMT("dwRevision: 0x%08X"),pNodeInfo->dwRevision);\r
- MTL_DEBUG3(MT_FLFMT("cLocalPortNum: 0x%02X"),pNodeInfo->cLocalPortNum);\r
- MTL_DEBUG3(MT_FLFMT("dwVendorID: 0x%08X"),pNodeInfo->dwVendorID);\r
-}\r
-//--------------------------------------------------------------------------------------------------\r
-\r
-//--------------------------------------------------------------------------------------------------\r
-//#define FUNCTION_NAME "GUIDInfoMADToSt"\r
-//--------------------------------------------------------------------------------------------------\r
-void GUIDInfoMADToSt(SM_MAD_GUIDInfo_t *pGuidTable,u_int8_t *pSMPBuf)\r
-{\r
- u_int16_t i;\r
-\r
- for (i=0;i<8;i++)\r
- memcpy((u_int8_t *)&(pGuidTable->guid[i]), pSMPBuf+IB_SMP_DATA_START + (i*8), 8);\r
-}\r
-//--------------------------------------------------------------------------------------------------\r
-\r
-\r
-//--------------------------------------------------------------------------------------------------\r
-//#define FUNCTION_NAME "NodeDescPrint"\r
-//--------------------------------------------------------------------------------------------------\r
-void GUIDInfoPrint(SM_MAD_GUIDInfo_t *pGuidTable)\r
-{\r
- u_int16_t i;\r
-\r
- for (i=0;i<8;i++) {\r
- MTL_DEBUG3(MT_FLFMT("GUID[%d] = 0x%02x%02x%02x%02x%02x%02x%02x%02x"), i, \r
- pGuidTable->guid[i][0],pGuidTable->guid[i][1],pGuidTable->guid[i][2],pGuidTable->guid[i][3],\r
- pGuidTable->guid[i][4],pGuidTable->guid[i][5],pGuidTable->guid[i][6],pGuidTable->guid[i][7]); //REV show all bytes\r
- }\r
-}\r
-//--------------------------------------------------------------------------------------------------\r
-\r
-\r
-//--------------------------------------------------------------------------------------------------\r
-//#define FUNCTION_NAME "PKeyTableMADToSt"\r
-//--------------------------------------------------------------------------------------------------\r
-void PKeyTableMADToSt(SM_MAD_Pkey_table_t *pKeyTable,u_int8_t *pSMPBuf)\r
-{\r
- u_int16_t i;\r
-\r
- for (i=0;i<32;i++)\r
- MyMemCopy((u_int8_t *)&(pKeyTable->pkey[i]), pSMPBuf+IB_SMP_DATA_START + (i*2), 2);\r
-}\r
-//--------------------------------------------------------------------------------------------------\r
-\r
-\r
-//--------------------------------------------------------------------------------------------------\r
-//#define FUNCTION_NAME "PKeyTablePrint"\r
-//--------------------------------------------------------------------------------------------------\r
-void PKeyTablePrint(SM_MAD_Pkey_table_t *pKeyTable)\r
-{\r
- u_int16_t i;\r
-\r
- for (i=0;i<32;i++) {\r
- MTL_DEBUG3(MT_FLFMT("PKey[%d] = 0x%X"), i, pKeyTable->pkey[i]); //REV show all bytes\r
- }\r
-}\r
-//--------------------------------------------------------------------------------------------------\r
-\r
-\r
-//--------------------------------------------------------------------------------------------------\r
-//#define FUNCTION_NAME "PortInfoStToMAD"\r
-//--------------------------------------------------------------------------------------------------\r
-void PortInfoStToMAD(SM_MAD_PortInfo_t *pPortInfo,u_int8_t *pSMPBuf)\r
-{\r
- MyMemCopy(pSMPBuf+IB_SMP_DATA_START,(u_int8_t *)&(pPortInfo->qwMKey),8);\r
- memcpy(pSMPBuf+IB_SMP_DATA_START+8,(u_int8_t *)&(pPortInfo->qwGIDPrefix),8);\r
- MyMemCopy(pSMPBuf+IB_SMP_DATA_START+16,(u_int8_t *)&(pPortInfo->wLID),2);\r
- MyMemCopy(pSMPBuf+IB_SMP_DATA_START+18,(u_int8_t *)&(pPortInfo->wMasterSMLID),2);\r
- MyMemCopy(pSMPBuf+IB_SMP_DATA_START+20,(u_int8_t *)&(pPortInfo->dwCapMask),4);\r
- MyMemCopy(pSMPBuf+IB_SMP_DATA_START+24,(u_int8_t *)&(pPortInfo->wDiagCode),2);\r
- MyMemCopy(pSMPBuf+IB_SMP_DATA_START+26,(u_int8_t *)&(pPortInfo->wMKLease),2);\r
- FieldToBuf(pPortInfo->cLocalPortNum,pSMPBuf+IB_SMP_DATA_START,224,8);\r
- FieldToBuf(pPortInfo->cLinkWidthEna,pSMPBuf+IB_SMP_DATA_START,232,8);\r
- FieldToBuf(pPortInfo->cLinkWidthSup,pSMPBuf+IB_SMP_DATA_START,240,8);\r
- FieldToBuf(pPortInfo->cLinkWidthAct,pSMPBuf+IB_SMP_DATA_START,248,8);\r
- FieldToBuf(pPortInfo->cLinkSpeedSup,pSMPBuf+IB_SMP_DATA_START,256,4);\r
- FieldToBuf((u_int8_t)pPortInfo->cPortState,pSMPBuf+IB_SMP_DATA_START,260,4);\r
- FieldToBuf(pPortInfo->cPhyState,pSMPBuf+IB_SMP_DATA_START,264,4);\r
- FieldToBuf(pPortInfo->cDownDefState,pSMPBuf+IB_SMP_DATA_START,268,4);\r
- FieldToBuf(pPortInfo->cMKProtect,pSMPBuf+IB_SMP_DATA_START,272,2);\r
- ZeroToBuf(pSMPBuf+IB_SMP_DATA_START,274,3);\r
- FieldToBuf(pPortInfo->cLMC,pSMPBuf+IB_SMP_DATA_START,277,3);\r
- FieldToBuf(pPortInfo->cLinkSpeedAct,pSMPBuf+IB_SMP_DATA_START,280,4);\r
- FieldToBuf(pPortInfo->cLinkSpeedEna,pSMPBuf+IB_SMP_DATA_START,284,4);\r
- FieldToBuf(pPortInfo->cNbMTU,pSMPBuf+IB_SMP_DATA_START,288,4);\r
- FieldToBuf(pPortInfo->cMasterSMSL,pSMPBuf+IB_SMP_DATA_START,292,4);\r
- FieldToBuf(pPortInfo->cVLCap,pSMPBuf+IB_SMP_DATA_START,296,4);\r
- ZeroToBuf(pSMPBuf+IB_SMP_DATA_START,300,4);\r
- FieldToBuf(pPortInfo->cVLHighLimit,pSMPBuf+IB_SMP_DATA_START,304,8);\r
- FieldToBuf(pPortInfo->cVLArbHighCap,pSMPBuf+IB_SMP_DATA_START,312,8);\r
- FieldToBuf(pPortInfo->cVLArbLowCap,pSMPBuf+IB_SMP_DATA_START,320,8);\r
- ZeroToBuf(pSMPBuf+IB_SMP_DATA_START,328,4);\r
- FieldToBuf(pPortInfo->cMTUCap,pSMPBuf+IB_SMP_DATA_START,332,4);\r
- FieldToBuf(pPortInfo->cVLStallCnt,pSMPBuf+IB_SMP_DATA_START,336,3);\r
- FieldToBuf(pPortInfo->cHOQLife,pSMPBuf+IB_SMP_DATA_START,339,5);\r
- FieldToBuf(pPortInfo->cOperVL,pSMPBuf+IB_SMP_DATA_START,344,4);\r
- FieldToBuf(pPortInfo->cPartEnfIn,pSMPBuf+IB_SMP_DATA_START,348,1);\r
- FieldToBuf(pPortInfo->cPartEnfOut,pSMPBuf+IB_SMP_DATA_START,349,1);\r
- FieldToBuf(pPortInfo->cFilterRawIn,pSMPBuf+IB_SMP_DATA_START,350,1);\r
- FieldToBuf(pPortInfo->cFilterRawOut,pSMPBuf+IB_SMP_DATA_START,351,1);\r
- MyMemCopy(pSMPBuf+IB_SMP_DATA_START+44,(u_int8_t *)&(pPortInfo->wMKViolations),2);\r
- MyMemCopy(pSMPBuf+IB_SMP_DATA_START+46,(u_int8_t *)&(pPortInfo->wPKViolations),2);\r
- MyMemCopy(pSMPBuf+IB_SMP_DATA_START+48,(u_int8_t *)&(pPortInfo->wQKViolations),2);\r
- FieldToBuf(pPortInfo->bGUIDCap,pSMPBuf+IB_SMP_DATA_START,400,8);\r
- ZeroToBuf(pSMPBuf+IB_SMP_DATA_START,408,3);\r
- FieldToBuf(pPortInfo->cSubnetTO,pSMPBuf+IB_SMP_DATA_START,411,5);\r
- ZeroToBuf(pSMPBuf+IB_SMP_DATA_START,416,3);\r
- FieldToBuf(pPortInfo->cRespTimeValue,pSMPBuf+IB_SMP_DATA_START,419,5);\r
- FieldToBuf(pPortInfo->cLocalPhyErr,pSMPBuf+IB_SMP_DATA_START,424,4);\r
- FieldToBuf(pPortInfo->cOverrunErr,pSMPBuf+IB_SMP_DATA_START,428,4);\r
-}\r
-//--------------------------------------------------------------------------------------------------\r
-\r
-\r
-//--------------------------------------------------------------------------------------------------\r
-//#define FUNCTION_NAME "PortInfoMADToSt"\r
-//--------------------------------------------------------------------------------------------------\r
-void PortInfoMADToSt(SM_MAD_PortInfo_t *pPortInfo,u_int8_t *pSMPBuf)\r
-{\r
- //parse pSMPBuf into PortInfo struct\r
- MyMemCopy((u_int8_t *)&(pPortInfo->qwMKey),pSMPBuf+IB_SMP_DATA_START,8);\r
- memcpy((u_int8_t *)&(pPortInfo->qwGIDPrefix),pSMPBuf+IB_SMP_DATA_START+8,8);\r
- MyMemCopy((u_int8_t *)&(pPortInfo->wLID),pSMPBuf+IB_SMP_DATA_START+16,2);\r
- MyMemCopy((u_int8_t *)&(pPortInfo->wMasterSMLID),pSMPBuf+IB_SMP_DATA_START+18,2);\r
- MyMemCopy((u_int8_t *)&(pPortInfo->dwCapMask),pSMPBuf+IB_SMP_DATA_START+20,4);\r
- MyMemCopy((u_int8_t *)&(pPortInfo->wDiagCode),pSMPBuf+IB_SMP_DATA_START+24,2);\r
- MyMemCopy((u_int8_t *)&(pPortInfo->wMKLease),pSMPBuf+IB_SMP_DATA_START+26,2);\r
- pPortInfo->cLocalPortNum=BufToField(pSMPBuf+IB_SMP_DATA_START,224,8);\r
- pPortInfo->cLinkWidthEna=BufToField(pSMPBuf+IB_SMP_DATA_START,232,8);\r
- pPortInfo->cLinkWidthSup=BufToField(pSMPBuf+IB_SMP_DATA_START,240,8);\r
- pPortInfo->cLinkWidthAct=BufToField(pSMPBuf+IB_SMP_DATA_START,248,8);\r
- pPortInfo->cLinkSpeedSup=BufToField(pSMPBuf+IB_SMP_DATA_START,256,4);\r
- pPortInfo->cPortState=(IB_port_state_t)BufToField(pSMPBuf+IB_SMP_DATA_START,260,4);\r
- pPortInfo->cPhyState=BufToField(pSMPBuf+IB_SMP_DATA_START,264,4);\r
- pPortInfo->cDownDefState=BufToField(pSMPBuf+IB_SMP_DATA_START,268,4);\r
- pPortInfo->cMKProtect=BufToField(pSMPBuf+IB_SMP_DATA_START,272,2);\r
- pPortInfo->cReserved1=BufToField(pSMPBuf+IB_SMP_DATA_START,274,3);\r
- pPortInfo->cLMC=BufToField(pSMPBuf+IB_SMP_DATA_START,277,3);\r
- pPortInfo->cLinkSpeedAct=BufToField(pSMPBuf+IB_SMP_DATA_START,280,4);\r
- pPortInfo->cLinkSpeedEna=BufToField(pSMPBuf+IB_SMP_DATA_START,284,4);\r
- pPortInfo->cNbMTU=BufToField(pSMPBuf+IB_SMP_DATA_START,288,4);\r
- pPortInfo->cMasterSMSL=BufToField(pSMPBuf+IB_SMP_DATA_START,292,4);\r
- pPortInfo->cVLCap=BufToField(pSMPBuf+IB_SMP_DATA_START,296,4);\r
- pPortInfo->cReserved2=BufToField(pSMPBuf+IB_SMP_DATA_START,300,4);\r
- pPortInfo->cVLHighLimit=BufToField(pSMPBuf+IB_SMP_DATA_START,304,8);\r
- pPortInfo->cVLArbHighCap=BufToField(pSMPBuf+IB_SMP_DATA_START,312,8);\r
- pPortInfo->cVLArbLowCap=BufToField(pSMPBuf+IB_SMP_DATA_START,320,8);\r
- pPortInfo->cReserved3=BufToField(pSMPBuf+IB_SMP_DATA_START,328,4);\r
- pPortInfo->cMTUCap=BufToField(pSMPBuf+IB_SMP_DATA_START,332,4);\r
- pPortInfo->cVLStallCnt=BufToField(pSMPBuf+IB_SMP_DATA_START,336,3);\r
- pPortInfo->cHOQLife=BufToField(pSMPBuf+IB_SMP_DATA_START,339,5);\r
- pPortInfo->cOperVL=BufToField(pSMPBuf+IB_SMP_DATA_START,344,4);\r
- pPortInfo->cPartEnfIn=BufToField(pSMPBuf+IB_SMP_DATA_START,348,1);\r
- pPortInfo->cPartEnfOut=BufToField(pSMPBuf+IB_SMP_DATA_START,349,1);\r
- pPortInfo->cFilterRawIn=BufToField(pSMPBuf+IB_SMP_DATA_START,350,1);\r
- pPortInfo->cFilterRawOut=BufToField(pSMPBuf+IB_SMP_DATA_START,351,1);\r
- MyMemCopy((u_int8_t *)&(pPortInfo->wMKViolations),pSMPBuf+IB_SMP_DATA_START+44,2);\r
- MyMemCopy((u_int8_t *)&(pPortInfo->wPKViolations),pSMPBuf+IB_SMP_DATA_START+46,2);\r
- MyMemCopy((u_int8_t *)&(pPortInfo->wQKViolations),pSMPBuf+IB_SMP_DATA_START+48,2);\r
- pPortInfo->bGUIDCap=BufToField(pSMPBuf+IB_SMP_DATA_START,400,8);\r
- pPortInfo->cReserved4=BufToField(pSMPBuf+IB_SMP_DATA_START,408,3);\r
- pPortInfo->cSubnetTO=BufToField(pSMPBuf+IB_SMP_DATA_START,411,5);\r
- pPortInfo->cReserved5=BufToField(pSMPBuf+IB_SMP_DATA_START,416,3);\r
- pPortInfo->cRespTimeValue=BufToField(pSMPBuf+IB_SMP_DATA_START,419,5);\r
- pPortInfo->cLocalPhyErr=BufToField(pSMPBuf+IB_SMP_DATA_START,424,4);\r
- pPortInfo->cOverrunErr=BufToField(pSMPBuf+IB_SMP_DATA_START,428,4);\r
-}\r
-//--------------------------------------------------------------------------------------------------\r
-\r
-//--------------------------------------------------------------------------------------------------\r
-//#define FUNCTION_NAME "PortInfoPrint"\r
-//--------------------------------------------------------------------------------------------------\r
-void PortInfoPrint(SM_MAD_PortInfo_t *pPortInfo)\r
-{\r
-#ifndef VXWORKS_OS // vxworks doesn't printf 64 bits int right.\r
- //MTL_DEBUG3(" qwMKey: 0x"U64_FMT" \n",pPortInfo->qwMKey);\r
-#else\r
- MTL_DEBUG3(MT_FLFMT("qwMKey: %08lX%08lX"),*(unsigned long *)&pPortInfo->qwMKey,*(((unsigned long *)&pPortInfo->qwMKey +1)));\r
-#endif //VXWORKS_OS\r
- MTL_DEBUG3(MT_FLFMT("qwGIDPrefix = 0x%02x%02x%02x%02x%02x%02x%02x%02x"), \r
- pPortInfo->qwGIDPrefix[0],pPortInfo->qwGIDPrefix[1],pPortInfo->qwGIDPrefix[2],pPortInfo->qwGIDPrefix[3],\r
- pPortInfo->qwGIDPrefix[4],pPortInfo->qwGIDPrefix[5],pPortInfo->qwGIDPrefix[6],pPortInfo->qwGIDPrefix[7]); //REV show all bytes\r
- MTL_DEBUG3(MT_FLFMT("wLID:0x%04X"),pPortInfo->wLID);\r
- MTL_DEBUG3(MT_FLFMT("wMasterSMLID:0x%04X"),pPortInfo->wMasterSMLID);\r
- MTL_DEBUG3(MT_FLFMT("dwCapMask:0x%08X"),pPortInfo->dwCapMask);\r
- MTL_DEBUG3(MT_FLFMT("wDiagCode:0x%04X"),pPortInfo->wDiagCode);\r
- MTL_DEBUG3(MT_FLFMT("wMKLease:0x%04X"),pPortInfo->wMKLease);\r
- MTL_DEBUG3(MT_FLFMT("cLocalPortNum:0x%02X"),pPortInfo->cLocalPortNum);\r
- MTL_DEBUG3(MT_FLFMT("cLinkWidthEna:0x%02X"),pPortInfo->cLinkWidthEna);\r
- MTL_DEBUG3(MT_FLFMT("cLinkWidthSup:0x%02X"),pPortInfo->cLinkWidthSup);\r
- MTL_DEBUG3(MT_FLFMT("cLinkWidthAct:0x%02X"),pPortInfo->cLinkWidthAct);\r
- MTL_DEBUG3(MT_FLFMT("cLinkSpeedSup:0x%02X"),pPortInfo->cLinkSpeedSup);\r
- MTL_DEBUG3(MT_FLFMT("cPortState:0x%02X"),pPortInfo->cPortState);\r
- MTL_DEBUG3(MT_FLFMT("cPhyState:0x%02X"),pPortInfo->cPhyState);\r
- MTL_DEBUG3(MT_FLFMT("cDownDefState:0x%02X"),pPortInfo->cDownDefState);\r
- MTL_DEBUG3(MT_FLFMT("cMKProtect:0x%02X"),pPortInfo->cMKProtect);\r
- MTL_DEBUG3(MT_FLFMT("cReserved1:0x%02X"),pPortInfo->cReserved1);\r
- MTL_DEBUG3(MT_FLFMT("cLMC:0x%02X"),pPortInfo->cLMC);\r
- MTL_DEBUG3(MT_FLFMT("cLinkSpeedAct:0x%02X"),pPortInfo->cLinkSpeedAct);\r
- MTL_DEBUG3(MT_FLFMT("cLinkSpeedEna:0x%02X"),pPortInfo->cLinkSpeedEna);\r
- MTL_DEBUG3(MT_FLFMT("cNbMTU:0x%02X"),pPortInfo->cNbMTU);\r
- MTL_DEBUG3(MT_FLFMT("cMasterSMSL:0x%02X"),pPortInfo->cMasterSMSL);\r
- MTL_DEBUG3(MT_FLFMT("cVLCap:0x%02X"),pPortInfo->cVLCap);\r
- MTL_DEBUG3(MT_FLFMT("cReserved2:0x%02X"),pPortInfo->cReserved2);\r
- MTL_DEBUG3(MT_FLFMT("cVLHighLimit:0x%02X"),pPortInfo->cVLHighLimit);\r
- MTL_DEBUG3(MT_FLFMT("cVLArbHighCap:0x%02X"),pPortInfo->cVLArbHighCap);\r
- MTL_DEBUG3(MT_FLFMT("cVLArbLowCap:0x%02X"),pPortInfo->cVLArbLowCap);\r
- MTL_DEBUG3(MT_FLFMT("cReserved3:0x%02X"),pPortInfo->cReserved3);\r
- MTL_DEBUG3(MT_FLFMT("cMTUCap:0x%02X"),pPortInfo->cMTUCap);\r
- MTL_DEBUG3(MT_FLFMT("cVLStallCnt:0x%02X"),pPortInfo->cVLStallCnt);\r
- MTL_DEBUG3(MT_FLFMT("cHOQLife:0x%02X"),pPortInfo->cHOQLife);\r
- MTL_DEBUG3(MT_FLFMT("cOperVL:0x%02X"),pPortInfo->cOperVL);\r
- MTL_DEBUG3(MT_FLFMT("cPartEnfIn:0x%02X"),pPortInfo->cPartEnfIn);\r
- MTL_DEBUG3(MT_FLFMT("cPartEnfOut:0x%02X"),pPortInfo->cPartEnfOut);\r
- MTL_DEBUG3(MT_FLFMT("cFilterRawIn:0x%02X"),pPortInfo->cFilterRawIn);\r
- MTL_DEBUG3(MT_FLFMT("cFilterRawOut:0x%02X"),pPortInfo->cFilterRawOut);\r
- MTL_DEBUG3(MT_FLFMT("wMKViolations:0x%04X"),pPortInfo->wMKViolations);\r
- MTL_DEBUG3(MT_FLFMT("wPKViolations:0x%04X"),pPortInfo->wPKViolations);\r
- MTL_DEBUG3(MT_FLFMT("wQKViolations:0x%04X"),pPortInfo->wQKViolations);\r
- MTL_DEBUG3(MT_FLFMT("bGUIDCap:0x%02X"),pPortInfo->bGUIDCap);\r
- MTL_DEBUG3(MT_FLFMT("cReserved4:0x%02X"),pPortInfo->cReserved4);\r
- MTL_DEBUG3(MT_FLFMT("cSubnetTO:0x%02X"),pPortInfo->cSubnetTO);\r
- MTL_DEBUG3(MT_FLFMT("cReserved5:0x%02X"),pPortInfo->cReserved5);\r
- MTL_DEBUG3(MT_FLFMT("cRespTimeValue:0x%02X"),pPortInfo->cRespTimeValue);\r
- MTL_DEBUG3(MT_FLFMT("cLocalPhyErr:0x%02X"),pPortInfo->cLocalPhyErr);\r
- MTL_DEBUG3(MT_FLFMT("cOverrunErr:0x%02X"),pPortInfo->cOverrunErr);\r
-}\r
-//--------------------------------------------------------------------------------------------------\r
-\r
-//--------------------------------------------------------------------------------------------------\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_SM_MAD_H\r
-#define H_SM_MAD_H\r
-/* -------------------------------------------------------------------------------------------------- */\r
-/* IB structures and parameters */\r
-/* -------------------------------------------------------------------------------------------------- */\r
-#include <mtl_common.h>\r
-#include <ib_defs.h>\r
-\r
-/* -------------------------------------------------------------------------------------------------- */\r
-/* PORTINFO */\r
-/* -------------------------------------------------------------------------------------------------- */\r
-typedef struct SM_MAD_PortInfo_st {\r
- u_int64_t qwMKey; /* 0,64 */\r
- IB_gid_prefix_t qwGIDPrefix; /* 64,64 */\r
- IB_lid_t wLID; /* 128,16 */\r
- IB_lid_t wMasterSMLID; /* 144,16 */\r
- u_int32_t dwCapMask; /* 160,32 */\r
- u_int16_t wDiagCode; /* 192,16 */\r
- u_int16_t wMKLease; /* 208,16 */\r
- u_int8_t cLocalPortNum; /* 224,8 */\r
- u_int8_t cLinkWidthEna; /* 232,8 */\r
- u_int8_t cLinkWidthSup; /* 240,8 */\r
- u_int8_t cLinkWidthAct; /* 248,8 */\r
- u_int8_t cLinkSpeedSup; /* 256,4 */\r
- IB_port_state_t cPortState; /* 260,4 */\r
- u_int8_t cPhyState; /* 264,4 */\r
- u_int8_t cDownDefState; /* 268,4 */\r
- u_int8_t cMKProtect; /* 272,2 */\r
- u_int8_t cReserved1; /* 274,3 */\r
- u_int8_t cLMC; /* 277,2 */\r
- u_int8_t cLinkSpeedAct; /* 280,4 */\r
- u_int8_t cLinkSpeedEna; /* 284,4 */\r
- u_int8_t cNbMTU; /* 288,4 */\r
- u_int8_t cMasterSMSL; /* 292,4 */\r
- u_int8_t cVLCap; /* 296,4 */\r
- u_int8_t cReserved2; /* 300,4 */\r
- u_int8_t cVLHighLimit; /* 304,8 */\r
- u_int8_t cVLArbHighCap; /* 312,8 */\r
- u_int8_t cVLArbLowCap; /* 320,8 */\r
- u_int8_t cReserved3; /* 328,4 */\r
- u_int8_t cMTUCap; /* 332,4 */\r
- u_int8_t cVLStallCnt; /* 336,3 */\r
- u_int8_t cHOQLife; /* 339,5 */\r
- u_int8_t cOperVL; /* 344,4 */\r
- u_int8_t cPartEnfIn; /* 348,1 */\r
- u_int8_t cPartEnfOut; /* 349,1 */\r
- u_int8_t cFilterRawIn; /* 350,1 */\r
- u_int8_t cFilterRawOut; /* 351,1 */\r
- u_int16_t wMKViolations; /* 352,16 */\r
- u_int16_t wPKViolations; /* 368,16 */\r
- u_int16_t wQKViolations; /* 384,16 */\r
- u_int8_t bGUIDCap; /* 400,8 */\r
- u_int8_t cReserved4; /* 408,3 */\r
- u_int8_t cSubnetTO; /* 411,5 */\r
- u_int8_t cReserved5; /* 416,3 */\r
- u_int8_t cRespTimeValue; /* 419,5 */\r
- u_int8_t cLocalPhyErr; /* 424,4 */\r
- u_int8_t cOverrunErr; /* 428,4 */\r
-} SM_MAD_PortInfo_t;\r
-\r
-#define IB_PORTINFO_PORTSTATE_DOWN 1\r
-\r
-/* -------------------------------------------------------------------------------------------------- */\r
-\r
-\r
-/* -------------------------------------------------------------------------------------------------- */\r
-/* NODEINFO */\r
-/* -------------------------------------------------------------------------------------------------- */\r
-typedef struct SM_MAD_NodeInfo_st {\r
- u_int8_t cBaseVersion;\r
- u_int8_t cClassVersion;\r
- IB_node_type_t cNodeType;\r
- u_int8_t cNumPorts;\r
- IB_guid_t qwNodeGUID;\r
- IB_guid_t qwPortGUID;\r
- u_int16_t wPartCap;\r
- u_int16_t wDeviceID;\r
- u_int32_t dwRevision;\r
- u_int8_t cLocalPortNum;\r
- u_int32_t dwVendorID;\r
-} SM_MAD_NodeInfo_t;\r
-\r
-typedef struct SM_MAD_GUIDInfo_st {\r
- IB_guid_t guid[8];\r
-} SM_MAD_GUIDInfo_t;\r
-\r
-typedef struct SM_MAD_Pkey_table_st {\r
- u_int16_t pkey[32];\r
-} SM_MAD_Pkey_table_t;\r
-\r
-/* -------------------------------------------------------------------------------------------------- */\r
-\r
-\r
-/* -------------------------------------------------------------------------------------------------- */\r
-/* NODEDESC */\r
-/* -------------------------------------------------------------------------------------------------- */\r
-typedef struct NodeDesc {\r
- char szNodeDesc[64];\r
-} NODEDESC;\r
-\r
-\r
-\r
-/* -------------------------------------------------------------------------------------------------- */\r
-#define GUID_DUMMY MAKE_ULONGLONG(0xFFFFFFFFFFFFFFFF)\r
-#define GUID_INVALID MAKE_ULONGLONG(0x0000000000000000)\r
-\r
-/* -------------------------------------------------------------------------------------------------- */\r
-\r
-#define IB_INVALID_LID 0x0000\r
-#define IB_PERMISSIVE_LID 0xFFFF\r
-\r
-#define IB_MAD_SIZE 256\r
-#define IB_SMP_DATA_START 64 \r
-\r
-/* REV convert to enum */\r
-#define IB_CLASS_SMP 0x01\r
-#define IB_CLASS_DIR_ROUTE 0x81\r
-\r
-#define IB_METHOD_GET 0x01\r
-#define IB_METHOD_SET 0x02\r
-\r
-typedef enum {\r
- IB_SMP_ATTRIB_NODEINFO= 0x0011,\r
- IB_SMP_ATTRIB_GUIDINFO= 0x0014,\r
- IB_SMP_ATTRIB_PORTINFO= 0x0015,\r
- IB_SMP_ATTRIB_PARTTABLE= 0x0016\r
-} SM_MAD_attrib_t;\r
-\r
-void MADHeaderBuild(u_int8_t cMgtClass, \r
- u_int16_t wClSp,\r
- u_int8_t cMethod,\r
- u_int16_t wAttrib,\r
- u_int32_t dwModif,\r
- u_int8_t *pSMPBuf) ;\r
-\r
-void MadBufPrint(void *madbuf);\r
-void NodeInfoStToMAD(SM_MAD_NodeInfo_t *pNodeInfo,u_int8_t *pSMPBuf);\r
-void NodeInfoMADToSt(SM_MAD_NodeInfo_t *pNodeInfo,u_int8_t *pSMPBuf);\r
-void NodeInfoPrint(SM_MAD_NodeInfo_t *pNodeInfo);\r
-void GUIDInfoMADToSt(SM_MAD_GUIDInfo_t *pGuidTable,u_int8_t *pSMPBuf);\r
-void GUIDInfoPrint(SM_MAD_GUIDInfo_t *pGuidTable);\r
-void PKeyTableMADToSt(SM_MAD_Pkey_table_t *pKeyTable,u_int8_t *pSMPBuf);\r
-void PKeyTablePrint(SM_MAD_Pkey_table_t *pKeyTable);\r
-void PortInfoStToMAD(SM_MAD_PortInfo_t *pPortInfo,u_int8_t *pSMPBuf);\r
-void PortInfoMADToSt(SM_MAD_PortInfo_t *pPortInfo,u_int8_t *pSMPBuf);\r
-void PortInfoPrint(SM_MAD_PortInfo_t *pPortInfo);\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include <tlog2.h>\r
-\r
-/************************************************************************\r
- * Divide and conquer to find the highest bits.\r
- * But when getting within 8 bits, just a lookup into a \r
- * static constant table. This also serves a quick optimization\r
- * when x < 2^8 = 256. The constant table is set on compile time,\r
- * and was generated by the help of our Python friend.\r
- * Very efficient, if I may say so -- yotam\r
- */\r
-u_int8_t floor_log2(u_int64_t x)\r
-{\r
- enum { nLowBits = 8 };\r
- static const u_int64_t \r
- highMask = ~(((u_int64_t)1 << nLowBits) - (u_int64_t)1);\r
- static const unsigned char lowlog2[1<<nLowBits] =\r
- {\r
- 0, /* special case (not -infinity) */\r
-/*** The following Python script, generates the rest of the values:\r
-#!/usr/bin/env python\r
-import sys;\r
-txt = '';\r
-nLowBits = 8;\r
-indent = ' ';\r
-for p in range(0,nLowBits):\r
- n = 1 << p;\r
- elem = " %d," % p;\r
- nRows = int(n / 10);\r
- residue = n % 10;\r
- row = indent + 10 * elem + "\n";\r
- txt = txt + nRows * row;\r
- if residue:\r
- txt = txt + indent + residue * elem + "\n";\r
-txt = txt[:-2] + "\n"; # delete last comma\r
-sys.stdout.write(txt);\r
-sys.exit(0);\r
-***/\r
- 0,\r
- 1, 1,\r
- 2, 2, 2, 2,\r
- 3, 3, 3, 3, 3, 3, 3, 3,\r
- 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,\r
- 4, 4, 4, 4, 4, 4,\r
- 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,\r
- 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,\r
- 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,\r
- 5, 5,\r
- 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,\r
- 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,\r
- 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,\r
- 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,\r
- 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,\r
- 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,\r
- 6, 6, 6, 6,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7\r
- };\r
- \r
- unsigned step = 8*sizeof(u_int64_t);\r
- u_int8_t p = 0;\r
- while (x & highMask)\r
- {\r
- u_int64_t high;\r
- step >>= 1; /* /= 2 */\r
- high = (x >> step);\r
- if (high)\r
- {\r
- p |= step;\r
- x = high;\r
- }\r
- else\r
- {\r
- u_int64_t mask = ((u_int64_t)1 << step) - 1;\r
- x &= mask;\r
- }\r
- }\r
- \r
- p |= lowlog2[x];\r
- return p;\r
-} /* floor_log2 */\r
-\r
-\r
-/************************************************************************/\r
-u_int8_t ceil_log2(u_int64_t x)\r
-{\r
- u_int8_t p = floor_log2(x);\r
- if (((u_int64_t)1 << p) < x)\r
- {\r
- p += 1;\r
- }\r
- return p;\r
-} /* ceil_log2 */\r
-\r
-\r
-/************************************************************************\r
- * Divide and conquer to find the lowest bit.\r
- * But when getting within 8 bits, just a lookup into a \r
- * static constant table. This also serves a quick optimization\r
- * when x < 2^8 = 256. The constant table is set on compile time,\r
- * and was generated by the help of our Python friend.\r
- * Very efficient, if I may say so -- yotam\r
- */\r
-u_int8_t lowest_bit(u_int64_t x)\r
-{\r
- enum { nLowBits = 8 };\r
- static const u_int64_t one_64 = 1;\r
- static const u_int64_t lowMask = ((u_int64_t)1 << nLowBits) - (u_int64_t)1;\r
- static const unsigned char lowest_bit8[1<<nLowBits] =\r
- {\r
- 64, /* special case (not +infinity) - but actually unused */\r
-/*** The following Python script, generates the rest of the values:\r
-#!/usr/bin/env python\r
-import sys;\r
-nLowBits = 8; N = 1<<nLowBits;\r
-indent = ' ';\r
-txt = indent;\r
-for n in range(1,N):\r
- b = 0;\r
- while (1<<b & n) == 0:\r
- b = b + 1;\r
- if (n > 1) and (((1<<b) == n) or (n % 10 == 0)):\r
- txt = txt + "\n" + indent;\r
- txt = txt + (" %d," % b);\r
-txt = txt[:-2] + "\n"; # delete last comma\r
-sys.stdout.write(txt);\r
-sys.exit(0);\r
-***/\r
- 0,\r
- 1, 0,\r
- 2, 0, 1, 0,\r
- 3, 0,\r
- 1, 0, 2, 0, 1, 0,\r
- 4, 0, 1, 0,\r
- 2, 0, 1, 0, 3, 0, 1, 0, 2, 0,\r
- 1, 0,\r
- 5, 0, 1, 0, 2, 0, 1, 0,\r
- 3, 0, 1, 0, 2, 0, 1, 0, 4, 0,\r
- 1, 0, 2, 0, 1, 0, 3, 0, 1, 0,\r
- 2, 0, 1, 0,\r
- 6, 0, 1, 0, 2, 0,\r
- 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,\r
- 4, 0, 1, 0, 2, 0, 1, 0, 3, 0,\r
- 1, 0, 2, 0, 1, 0, 5, 0, 1, 0,\r
- 2, 0, 1, 0, 3, 0, 1, 0, 2, 0,\r
- 1, 0, 4, 0, 1, 0, 2, 0, 1, 0,\r
- 3, 0, 1, 0, 2, 0, 1, 0,\r
- 7, 0,\r
- 1, 0, 2, 0, 1, 0, 3, 0, 1, 0,\r
- 2, 0, 1, 0, 4, 0, 1, 0, 2, 0,\r
- 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,\r
- 5, 0, 1, 0, 2, 0, 1, 0, 3, 0,\r
- 1, 0, 2, 0, 1, 0, 4, 0, 1, 0,\r
- 2, 0, 1, 0, 3, 0, 1, 0, 2, 0,\r
- 1, 0, 6, 0, 1, 0, 2, 0, 1, 0,\r
- 3, 0, 1, 0, 2, 0, 1, 0, 4, 0,\r
- 1, 0, 2, 0, 1, 0, 3, 0, 1, 0,\r
- 2, 0, 1, 0, 5, 0, 1, 0, 2, 0,\r
- 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,\r
- 4, 0, 1, 0, 2, 0, 1, 0, 3, 0,\r
- 1, 0, 2, 0, 1, \r
- };\r
- \r
- unsigned step = 8*sizeof(u_int64_t);\r
- u_int8_t p = 64;\r
- if (x)\r
- {\r
- u_int64_t xLow;\r
- p = 0;\r
- while ((xLow = (x & lowMask)) == 0)\r
- {\r
- u_int64_t low;\r
- step >>= 1; /* /= 2 */\r
- low = x & ((one_64 << step) - 1);\r
- if (low)\r
- {\r
- x = low;\r
- }\r
- else\r
- {\r
- p |= step;\r
- x >>= step;\r
- }\r
- }\r
- p |= lowest_bit8[xLow];\r
- }\r
- \r
- return p;\r
-} /* lowest_bit */\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#if !defined(_TLOG2_H)\r
-#define _TLOG2_H\r
-\r
-#include <mtl_common.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-\r
-/************************************************************************\r
- * Function: floor_log2(n)\r
- * floor_log2(0) = 0 if n=0\r
- * floor_log2(n) = floor(log_2(n)) if n>=1\r
- *\r
- * Better than formal description:\r
- *\r
- * floor_log2(0) = 0\r
- * floor_log2(1) = 0\r
- * floor_log2(2) = 1\r
- * floor_log2(3) = 1\r
- * floor_log2(4) = 2\r
- * floor_log2(5) = 2\r
- * ...\r
- * floor_log2(15) = 3\r
- * floor_log2(16) = 4\r
- * floor_log2(17) = 4\r
- * ...\r
- */\r
-extern u_int8_t floor_log2(u_int64_t x);\r
-/* extern unsigned int tlog2(u_int64_t x); / * obsolete, use floor_log2 */\r
-\r
-/************************************************************************\r
- * Function: ceil_log2(n) \r
- *\r
- * Minimal p>=0, such that x <= 2^p.\r
- * ceil_log2(0) = 0 if n=0\r
- * ceil_log2(n) = ceil(log_2(n)) if n>=1\r
- *\r
- * Better than formal description:\r
- *\r
- * ceil_log2(0) = 0\r
- * ceil_log2(1) = 0\r
- * ceil_log2(2) = 1\r
- * ceil_log2(3) = 2\r
- * ceil_log2(4) = 2\r
- * ceil_log2(5) = 3\r
- * ...\r
- * ceil_log2(15) = 4\r
- * ceil_log2(16) = 4\r
- * ceil_log2(17) = 5\r
- * ...\r
- */\r
-extern u_int8_t ceil_log2(u_int64_t x);\r
-\r
-/************************************************************************\r
- * Function: lowest_bit(x) \r
- * \r
- * If x=0 return 64. Otherwise return minimal b such that ((1<<b) & x) != 0.\r
- *\r
- * Intuitively, a mirror of floor_log2, which picks the highest bit.\r
- * Better than formal description:\r
- * \r
- * lowest_bit(0x0) = 64\r
- * lowest_bit(0x1) = 0\r
- * lowest_bit(0x2) = 1\r
- * lowest_bit(0x3) = 0\r
- * lowest_bit(0x4) = 2\r
- * lowest_bit(0x5) = 0\r
- * lowest_bit(0x6) = 1\r
- * lowest_bit(0x7) = 0\r
- * lowest_bit(0x8) = 3\r
- * lowest_bit(0x9) = 0\r
- * ...\r
- * lowest_bit(0xf) = 0\r
- * lowest_bit(0x10) = 4\r
- * lowest_bit(0x11) = 0\r
- * ...\r
- * lowest_bit(0x1f) = 0\r
- * lowest_bit(0x20) = 5\r
- *\r
- */\r
-extern u_int8_t lowest_bit(u_int64_t x);\r
-\r
-#ifdef __cplusplus\r
- }\r
-#endif\r
-\r
-#endif /* _TLOG2_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id:$\r
- */\r
-\r
-\r
-static HH_ret_t zombie_open_hca(\r
- HH_hca_hndl_t hca_hndl,\r
- EVAPI_hca_profile_t *profile_p,\r
- EVAPI_hca_profile_t *sugg_profile_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_close_hca(\r
- HH_hca_hndl_t hca_hndl\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_alloc_ul_resources(\r
- HH_hca_hndl_t hca_hndl,\r
- MOSAL_protection_ctx_t user_protection_context,\r
- void* hca_ul_resources_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_free_ul_resources(\r
- HH_hca_hndl_t hca_hndl,\r
- void* hca_ul_resources_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_query_hca(\r
- HH_hca_hndl_t hca_hndl,\r
- VAPI_hca_cap_t* hca_cap_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_modify_hca(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- VAPI_hca_attr_t* hca_attr_p,\r
- VAPI_hca_attr_mask_t* hca_attr_mask_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_query_port_prop(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- VAPI_hca_port_t* hca_port_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_get_pkey_tbl(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- u_int16_t tbl_len_in,\r
- u_int16_t* tbl_len_out,\r
- IB_pkey_t* pkey_tbl_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_get_gid_tbl(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- u_int16_t tbl_len_in,\r
- u_int16_t* tbl_len_out,\r
- IB_gid_t* pkey_tbl_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_get_lid(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port,\r
- IB_lid_t* lid_p,\r
- u_int8_t* lmc_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_alloc_pd(\r
- HH_hca_hndl_t hca_hndl, \r
- MOSAL_protection_ctx_t prot_ctx, \r
- void * pd_ul_resources_p, \r
- HH_pd_hndl_t *pd_num_p\r
-) \r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_free_pd(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_pd_hndl_t pd\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_alloc_rdd(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_rdd_hndl_t* rdd_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_free_rdd(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_rdd_hndl_t rdd\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_create_priv_ud_av(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_pd_hndl_t pd,\r
- VAPI_ud_av_t* av_p,\r
- HH_ud_av_hndl_t* ah_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_modify_priv_ud_av(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_ud_av_hndl_t ah,\r
- VAPI_ud_av_t* av_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_query_priv_ud_av(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_ud_av_hndl_t ah,\r
- VAPI_ud_av_t* av_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_destroy_priv_ud_av(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_ud_av_hndl_t ah\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_register_mr(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_mr_t* mr_props_p,\r
- VAPI_lkey_t* lkey_p,\r
- VAPI_rkey_t* rkey_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_reregister_mr(\r
- HH_hca_hndl_t hca_hndl,\r
- VAPI_lkey_t lkey,\r
- VAPI_mr_change_t change_mask,\r
- HH_mr_t* mr_props_p,\r
- VAPI_lkey_t* lkey_p,\r
- VAPI_rkey_t* rkey_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_register_smr(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_smr_t* smr_props_p,\r
- VAPI_lkey_t* lkey_p,\r
- VAPI_rkey_t* rkey_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_deregister_mr(\r
- HH_hca_hndl_t hca_hndl,\r
- VAPI_lkey_t lkey\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_query_mr(\r
- HH_hca_hndl_t hca_hndl,\r
- VAPI_lkey_t lkey,\r
- HH_mr_info_t* mr_info_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_alloc_mw(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_pd_hndl_t pd,\r
- VAPI_rkey_t* initial_rkey_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_free_mw(\r
- HH_hca_hndl_t hca_hndl,\r
- VAPI_rkey_t initial_rkey\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_create_cq(\r
- HH_hca_hndl_t hca_hndl,\r
- MOSAL_protection_ctx_t user_protection_context,\r
- void* cq_ul_resources_p,\r
- HH_cq_hndl_t* cq\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_resize_cq(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_cq_hndl_t cq,\r
- void* cq_ul_resources_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_query_cq(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_cq_hndl_t cq,\r
- VAPI_cqe_num_t* num_o_cqes_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_destroy_cq(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_cq_hndl_t cq\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_create_qp(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_qp_init_attr_t* init_attr_p,\r
- void* qp_ul_resources_p,\r
- IB_wqpn_t* qpn_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_get_special_qp(\r
- HH_hca_hndl_t hca_hndl,\r
- VAPI_special_qp_t qp_type,\r
- IB_port_t port,\r
- HH_qp_init_attr_t* init_attr_p,\r
- void* qp_ul_resources_p,\r
- IB_wqpn_t* sqp_hndl_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_modify_qp(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_wqpn_t qp_num,\r
- VAPI_qp_state_t cur_qp_state,\r
- VAPI_qp_attr_t* qp_attr_p,\r
- VAPI_qp_attr_mask_t* qp_attr_mask_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_query_qp(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_wqpn_t qp_num,\r
- VAPI_qp_attr_t* qp_attr_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_destroy_qp(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_wqpn_t qp_num\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_create_eec(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_rdd_hndl_t rdd,\r
- IB_eecn_t* eecn_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_modify_eec(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_eecn_t eecn,\r
- VAPI_qp_state_t cur_ee_state,\r
- VAPI_qp_attr_t* ee_attr_p,\r
- VAPI_qp_attr_mask_t* ee_attr_mask_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_query_eec(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_eecn_t eecn,\r
- VAPI_qp_attr_t* ee_attr_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_destroy_eec(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_eecn_t eecn\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_set_async_eventh(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_async_eventh_t handler,\r
- void* private_data\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_set_comp_eventh(\r
- HH_hca_hndl_t hca_hndl,\r
- HH_comp_eventh_t handler,\r
- void* private_data\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_attach_to_multicast(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_wqpn_t qpn,\r
- IB_gid_t dgid\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-static HH_ret_t zombie_detach_from_multicast(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_wqpn_t qpn,\r
- IB_gid_t dgid\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-\r
-static HH_ret_t zombie_process_local_mad(\r
- HH_hca_hndl_t hca_hndl,\r
- IB_port_t port_num,\r
- IB_lid_t slid,\r
- EVAPI_proc_mad_opt_t proc_mad_opts,\r
- void* mad_in_p,\r
- void* mad_out_p\r
-)\r
-{\r
- return HH_HCA_STATUS_ZOMBIE;\r
-}\r
-\r
-\r
-static void zombie_init(HH_if_ops_t* p)\r
-{\r
- p->HHIF_open_hca = &zombie_open_hca;\r
- p->HHIF_close_hca = &zombie_close_hca;\r
- p->HHIF_alloc_ul_resources = &zombie_alloc_ul_resources;\r
- p->HHIF_free_ul_resources = &zombie_free_ul_resources;\r
- p->HHIF_query_hca = &zombie_query_hca;\r
- p->HHIF_modify_hca = &zombie_modify_hca;\r
- p->HHIF_query_port_prop = &zombie_query_port_prop;\r
- p->HHIF_get_pkey_tbl = &zombie_get_pkey_tbl;\r
- p->HHIF_get_gid_tbl = &zombie_get_gid_tbl;\r
- p->HHIF_get_lid = &zombie_get_lid;\r
- p->HHIF_alloc_pd = &zombie_alloc_pd;\r
- p->HHIF_free_pd = &zombie_free_pd;\r
- p->HHIF_alloc_rdd = &zombie_alloc_rdd;\r
- p->HHIF_free_rdd = &zombie_free_rdd;\r
- p->HHIF_create_priv_ud_av = &zombie_create_priv_ud_av;\r
- p->HHIF_modify_priv_ud_av = &zombie_modify_priv_ud_av;\r
- p->HHIF_query_priv_ud_av = &zombie_query_priv_ud_av;\r
- p->HHIF_destroy_priv_ud_av = &zombie_destroy_priv_ud_av;\r
- p->HHIF_register_mr = &zombie_register_mr;\r
- p->HHIF_reregister_mr = &zombie_reregister_mr;\r
- p->HHIF_register_smr = &zombie_register_smr;\r
- p->HHIF_deregister_mr = &zombie_deregister_mr;\r
- p->HHIF_query_mr = &zombie_query_mr;\r
- p->HHIF_alloc_mw = &zombie_alloc_mw;\r
- p->HHIF_free_mw = &zombie_free_mw;\r
- p->HHIF_create_cq = &zombie_create_cq;\r
- p->HHIF_resize_cq = &zombie_resize_cq;\r
- p->HHIF_query_cq = &zombie_query_cq;\r
- p->HHIF_destroy_cq = &zombie_destroy_cq;\r
- p->HHIF_create_qp = &zombie_create_qp;\r
- p->HHIF_get_special_qp = &zombie_get_special_qp;\r
- p->HHIF_modify_qp = &zombie_modify_qp;\r
- p->HHIF_query_qp = &zombie_query_qp;\r
- p->HHIF_destroy_qp = &zombie_destroy_qp;\r
- p->HHIF_create_eec = &zombie_create_eec;\r
- p->HHIF_modify_eec = &zombie_modify_eec;\r
- p->HHIF_query_eec = &zombie_query_eec;\r
- p->HHIF_destroy_eec = &zombie_destroy_eec;\r
- p->HHIF_set_async_eventh = &zombie_set_async_eventh;\r
- p->HHIF_set_comp_eventh = &zombie_set_comp_eventh;\r
- p->HHIF_attach_to_multicast = &zombie_attach_to_multicast;\r
- p->HHIF_detach_from_multicast = &zombie_detach_from_multicast;\r
- p->HHIF_process_local_mad = &zombie_process_local_mad;\r
-} /* zombie_init */\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
- \r
-\r
-#ifndef VIP_ALLOCATOR_H\r
-#define VIP_ALLOCATOR_H\r
-\r
-#include <mtl_common.h>\r
-#include "vip_common.h"\r
-\r
-#ifdef VIP_ENABLE_MALLOC\r
-/* Most code only uses pointer to free.\r
- * Avoid unused function warning for them */\r
-static VIP_allocator_malloc_t VIP_malloc;\r
-static void* VIP_malloc(size_t size) {\r
- return MALLOC(size);\r
-}\r
-#endif\r
-\r
-static void VIP_free(void* p) {\r
- FREE(p);\r
-}\r
-\r
-#endif\r
-EXPORTS\r
- ; ------------------------------\r
- ; vip_array.c\r
- ; ------------------------------\r
- VIP_array_create\r
- VIP_array_create_maxsize\r
- VIP_array_destroy\r
- VIP_array_insert\r
- VIP_array_insert2hndl\r
- VIP_array_insert_ptr\r
- VIP_array_erase\r
- VIP_array_erase_prepare\r
- VIP_array_erase_undo\r
- VIP_array_erase_done\r
- VIP_array_find\r
- VIP_array_find_release\r
- VIP_array_find_release_erase\r
- VIP_array_find_release_erase_prepare\r
- VIP_array_find_hold\r
- VIP_array_get_num_of_objects\r
- VIP_array_get_first_handle\r
- VIP_array_get_next_handle\r
- VIP_array_get_first_handle_hold\r
- VIP_array_get_next_handle_hold\r
- ; ------------------------------\r
- ; vip_hash.c\r
- ; ------------------------------\r
- ; vip_hash.h\r
- VIP_hash_create\r
- VIP_hash_create_maxsize\r
- VIP_hash_destroy\r
- VIP_hash_insert\r
- VIP_hash_insert_ptr\r
- VIP_hash_erase\r
- VIP_hash_find\r
- VIP_hash_find_ptr\r
- VIP_hash_may_grow\r
- VIP_hash_traverse\r
- VIP_hash_get_num_of_buckets\r
- VIP_hash_get_num_of_objects\r
- ; vip_hashp.h\r
- VIP_hashp_create\r
- VIP_hashp_create_maxsize\r
- VIP_hashp_destroy\r
- VIP_hashp_insert\r
- VIP_hashp_insert_ptr\r
- VIP_hashp_erase\r
- VIP_hashp_find\r
- VIP_hashp_find_ptr\r
- VIP_hashp_get_num_of_buckets\r
- VIP_hashp_get_num_of_objects\r
- VIP_hashp_may_grow\r
- VIP_hashp_traverse\r
- ; vip_hashp2p.h\r
- VIP_hashp2p_create\r
- VIP_hashp2p_create_maxsize\r
- VIP_hashp2p_destroy\r
- VIP_hashp2p_insert\r
- VIP_hashp2p_insert_ptr\r
- VIP_hashp2p_erase\r
- VIP_hashp2p_find\r
- VIP_hashp2p_find_ptr\r
- VIP_hashp2p_get_num_of_buckets\r
- VIP_hashp2p_get_num_of_objects\r
- VIP_hashp2p_may_grow\r
- VIP_hashp2p_traverse\r
- ; vip_hash64p.h\r
- VIP_hash64p_create\r
- VIP_hash64p_create_maxsize\r
- VIP_hash64p_destroy\r
- VIP_hash64p_insert\r
- VIP_hash64p_insert_ptr\r
- VIP_hash64p_erase\r
- VIP_hash64p_find\r
- VIP_hash64p_find_ptr\r
- VIP_hash64p_get_num_of_buckets\r
- VIP_hash64p_get_num_of_objects\r
- VIP_hash64p_may_grow\r
- VIP_hash64p_traverse\r
- ; ------------------------------\r
- ; vapi_common.c\r
- ; ------------------------------\r
- VAPI_strerror\r
- VAPI_strerror_sym\r
- VAPI_hca_cap_sym\r
- VAPI_hca_attr_mask_sym\r
- VAPI_qp_attr_mask_sym\r
- VAPI_mrw_acl_mask_sym\r
- VAPI_mr_change_mask_sym\r
- VAPI_rdma_atom_acl_mask_sym\r
- VAPI_atomic_cap_sym\r
- VAPI_sig_type_sym\r
- VAPI_ts_type_sym\r
- VAPI_qp_state_sym\r
- VAPI_mig_state_sym\r
- VAPI_special_qp_sym\r
- VAPI_mrw_type_sym\r
- VAPI_remote_node_addr_sym\r
- VAPI_wr_opcode_sym\r
- VAPI_cqe_opcode_sym\r
- VAPI_wc_status_sym\r
- VAPI_comp_type_sym\r
- VAPI_cq_notif_sym\r
- VAPI_event_record_sym\r
- VAPI_event_syndrome_sym\r
- ; ------------------------------\r
- ; VIP_cirq.c\r
- ; ------------------------------\r
-; VIP_cirq_stats_print\r
-; VIP_cirq_create\r
-; VIP_cirq_add\r
-; VIP_cirq_peek\r
-; VIP_cirq_remove\r
-; VIP_cirq_empty\r
-; VIP_cirq_destroy\r
- \r
-EXPORTS\r
- ; for OS only\r
- DllInitialize private\r
- DllUnload private\r
- ; ------------------------------\r
- ; vip_array.c\r
- ; ------------------------------\r
- VIP_array_create\r
- VIP_array_create_maxsize\r
- VIP_array_destroy\r
- VIP_array_insert\r
- VIP_array_insert2hndl\r
- VIP_array_insert_ptr\r
- VIP_array_erase\r
- VIP_array_erase_prepare\r
- VIP_array_erase_undo\r
- VIP_array_erase_done\r
- VIP_array_find\r
- VIP_array_find_release\r
- VIP_array_find_release_erase\r
- VIP_array_find_release_erase_prepare\r
- VIP_array_find_hold\r
- VIP_array_get_num_of_objects\r
- VIP_array_get_first_handle\r
- VIP_array_get_next_handle\r
- VIP_array_get_first_handle_hold\r
- VIP_array_get_next_handle_hold\r
-\r
- ; ------------------------------\r
- ; vip_hash.c\r
- ; ------------------------------\r
- ; vip_hash.h\r
- VIP_hash_create\r
- VIP_hash_create_maxsize\r
- VIP_hash_destroy\r
- VIP_hash_insert\r
- VIP_hash_insert_ptr\r
- VIP_hash_erase\r
- VIP_hash_find\r
- VIP_hash_find_ptr\r
- VIP_hash_may_grow\r
- VIP_hash_traverse\r
- VIP_hash_get_num_of_buckets\r
- VIP_hash_get_num_of_objects\r
- ; vip_hashp.h\r
- VIP_hashp_create\r
- VIP_hashp_create_maxsize\r
- VIP_hashp_destroy\r
- VIP_hashp_insert\r
- VIP_hashp_insert_ptr\r
- VIP_hashp_erase\r
- VIP_hashp_find\r
- VIP_hashp_find_ptr\r
- VIP_hashp_get_num_of_buckets\r
- VIP_hashp_get_num_of_objects\r
- VIP_hashp_may_grow\r
- VIP_hashp_traverse\r
- ; vip_hashp2p.h\r
- VIP_hashp2p_create\r
- VIP_hashp2p_create_maxsize\r
- VIP_hashp2p_destroy\r
- VIP_hashp2p_insert\r
- VIP_hashp2p_insert_ptr\r
- VIP_hashp2p_erase\r
- VIP_hashp2p_find\r
- VIP_hashp2p_find_ptr\r
- VIP_hashp2p_get_num_of_buckets\r
- VIP_hashp2p_get_num_of_objects\r
- VIP_hashp2p_may_grow\r
- VIP_hashp2p_traverse\r
- ; vip_hash64p.h\r
- VIP_hash64p_create\r
- VIP_hash64p_create_maxsize\r
- VIP_hash64p_destroy\r
- VIP_hash64p_insert\r
- VIP_hash64p_insert_ptr\r
- VIP_hash64p_erase\r
- VIP_hash64p_find\r
- VIP_hash64p_find_ptr\r
- VIP_hash64p_get_num_of_buckets\r
- VIP_hash64p_get_num_of_objects\r
- VIP_hash64p_may_grow\r
- VIP_hash64p_traverse\r
- ; ------------------------------\r
- ; vapi_common.c\r
- ; ------------------------------\r
- VAPI_strerror\r
- VAPI_strerror_sym\r
- VAPI_hca_cap_sym\r
- VAPI_hca_attr_mask_sym\r
- VAPI_qp_attr_mask_sym\r
- VAPI_mrw_acl_mask_sym\r
- VAPI_mr_change_mask_sym\r
- VAPI_rdma_atom_acl_mask_sym\r
- VAPI_atomic_cap_sym\r
- VAPI_sig_type_sym\r
- VAPI_ts_type_sym\r
- VAPI_qp_state_sym\r
- VAPI_mig_state_sym\r
- VAPI_special_qp_sym\r
- VAPI_mrw_type_sym\r
- VAPI_remote_node_addr_sym\r
- VAPI_wr_opcode_sym\r
- VAPI_cqe_opcode_sym\r
- VAPI_wc_status_sym\r
- VAPI_comp_type_sym\r
- VAPI_cq_notif_sym\r
- VAPI_event_record_sym\r
- VAPI_event_syndrome_sym\r
- ; ------------------------------\r
- ; VIP_cirq.c\r
- ; ------------------------------\r
- VIP_cirq_stats_print\r
- VIP_cirq_create\r
- VIP_cirq_add\r
- VIP_cirq_peek\r
- VIP_cirq_remove\r
- VIP_cirq_empty\r
- VIP_cirq_destroy\r
- ; ------------------------------\r
- ; VIP_delay_unlock.c\r
- ; ------------------------------\r
- VIP_delay_unlock_create\r
- VIP_delay_unlock_insert\r
- VIP_delay_unlock_destroy\r
- \r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifdef MT_KERNEL\r
-#include "mtl_types.h"\r
-NTSTATUS \r
-DriverEntry(\r
- IN PDRIVER_OBJECT pi_pDriverObject,\r
- IN PUNICODE_STRING pi_pRegistryPath\r
- )\r
-{ /* DriverEntry */\r
-\r
- DbgPrint("\n***** VAPI_COMMON_KL: DriverEntry()");\r
- return STATUS_SUCCESS;\r
-\r
-} /* DriverEntry */\r
-\r
-NTSTATUS DllInitialize(PUNICODE_STRING RegistryPath)\r
-{\r
- DbgPrint("\n***** VAPI_COMMON_KL: DllInitialize()");\r
- return STATUS_SUCCESS;\r
-}\r
-\r
-NTSTATUS DllUnload()\r
-{\r
- DbgPrint("\n***** VAPI_COMMON_KL DllUnload()");\r
- return STATUS_SUCCESS;\r
-}\r
-#endif\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
- \r
-\r
-#ifndef VIP_IMP_H\r
-#define VIP_IMP_H\r
-\r
-#include <string.h>\r
-\r
-#endif\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifdef MT_KERNEL\r
- /* Taken care via vapi_common.h -> mtl_common.h -> ... ->\r
- * -> /lib/modules/N.N.N/build/include/linux/string.h\r
- * extern int strlen(const char*);\r
- * extern char* (char*, const char*);\r
- */\r
-#else\r
-# include <string.h>\r
-#endif\r
-#include "vapi_common.h"\r
-\r
-const char* VAPI_strerror( VAPI_ret_t errnum)\r
-{\r
- switch (errnum) {\r
-#define VAPI_ERROR_INFO(A, B, C) case A: return C;\r
- VAPI_ERROR_LIST\r
-#undef VAPI_ERROR_INFO\r
- default: return "VAPI_UNKNOWN_ERROR";\r
- }\r
-\r
-}\r
-const char* VAPI_strerror_sym( VAPI_ret_t errnum)\r
-{\r
- switch (errnum) {\r
-#define VAPI_ERROR_INFO(A, B, C) case A: return #A;\r
- VAPI_ERROR_LIST\r
-#undef VAPI_ERROR_INFO\r
- default: return "VAPI_UNKNOWN_ERROR";\r
- }\r
-}\r
-\r
-\r
-\r
-static char* safe_append(\r
- char* cbuf,\r
- char* buf_end,\r
- u_int32_t mask,\r
- u_int32_t flag,\r
- const char* flag_sym\r
-)\r
-{\r
- if (mask & flag)\r
- {\r
- int l = (int)strlen(flag_sym);\r
- if (cbuf + l + 2 < buf_end)\r
- {\r
- strcpy(cbuf, flag_sym);\r
- cbuf += l;\r
- *cbuf++ = '+';\r
- *cbuf = '\0';\r
- }\r
- else\r
- {\r
- cbuf = NULL;\r
- }\r
- }\r
- return cbuf;\r
-} /* safe_append */\r
-\r
-\r
-static void end_mask_sym(char* buf, char* cbuf, int bufsz)\r
-{\r
- if (bufsz > 0)\r
- {\r
- if (buf == cbuf)\r
- {\r
- *cbuf = '\0'; /* empty string */\r
- }\r
- else if (cbuf == 0) /* was truncated */\r
- {\r
- int l = (int)strlen(buf);\r
- buf[l - 1] = '>';\r
- }\r
- }\r
-} /* end_mask_sym */\r
-\r
-\r
-#define INIT_BUF_SKIP(skipped_pfx) \\r
- int skip = (int)strlen(skipped_pfx); \\r
- char* cbuf = buf; \\r
- char* buf_end = buf + bufsz; \\r
- *buf = '\0';\r
-\r
-\r
-#define SAFE_APPEND(e) \\r
- if (cbuf) { cbuf = safe_append(cbuf, buf_end, mask, e, #e + skip); }\r
-\r
-const char* VAPI_hca_cap_sym(char* buf, int bufsz, u_int32_t mask)\r
-{\r
- INIT_BUF_SKIP("VAPI_")\r
-\r
- SAFE_APPEND(VAPI_RESIZE_OUS_WQE_CAP)\r
- SAFE_APPEND(VAPI_BAD_PKEY_COUNT_CAP)\r
- SAFE_APPEND(VAPI_BAD_QKEY_COUNT_CAP)\r
- SAFE_APPEND(VAPI_RAW_MULTI_CAP)\r
- SAFE_APPEND(VAPI_AUTO_PATH_MIG_CAP)\r
- SAFE_APPEND(VAPI_CHANGE_PHY_PORT_CAP)\r
- SAFE_APPEND(VAPI_UD_AV_PORT_ENFORCE_CAP)\r
- SAFE_APPEND(VAPI_CURR_QP_STATE_MOD_CAP)\r
- SAFE_APPEND(VAPI_SHUTDOWN_PORT_CAP)\r
- SAFE_APPEND(VAPI_INIT_TYPE_CAP)\r
- SAFE_APPEND(VAPI_PORT_ACTIVE_EV_CAP)\r
- SAFE_APPEND(VAPI_SYS_IMG_GUID_CAP)\r
- SAFE_APPEND(VAPI_RC_RNR_NAK_GEN_CAP)\r
-\r
- end_mask_sym(buf, cbuf, bufsz);\r
- return buf;\r
-} /* VAPI_hca_cap_sym */\r
-\r
-\r
-const char* VAPI_hca_attr_mask_sym(char* buf, int bufsz, u_int32_t mask)\r
-{\r
- INIT_BUF_SKIP("HCA_ATTR_")\r
- SAFE_APPEND(HCA_ATTR_IS_SM)\r
- SAFE_APPEND(HCA_ATTR_IS_SNMP_TUN_SUP)\r
- SAFE_APPEND(HCA_ATTR_IS_DEV_MGT_SUP)\r
- SAFE_APPEND(HCA_ATTR_IS_VENDOR_CLS_SUP)\r
- SAFE_APPEND(HCA_ATTR_IS_CLIENT_REREGISTRATION_SUP)\r
- SAFE_APPEND(HCA_ATTR_MAX)\r
- end_mask_sym(buf, cbuf, bufsz);\r
- return buf;\r
-} /* VAPI_hca_attr_mask_sym */\r
-\r
-\r
-const char* VAPI_qp_attr_mask_sym(char* buf, int bufsz, u_int32_t mask)\r
-{\r
- INIT_BUF_SKIP("QP_ATTR_")\r
-\r
- SAFE_APPEND(QP_ATTR_QP_STATE)\r
- SAFE_APPEND(QP_ATTR_EN_SQD_ASYN_NOTIF)\r
- SAFE_APPEND(QP_ATTR_QP_NUM)\r
- SAFE_APPEND(QP_ATTR_REMOTE_ATOMIC_FLAGS)\r
- SAFE_APPEND(QP_ATTR_PKEY_IX)\r
- SAFE_APPEND(QP_ATTR_PORT)\r
- SAFE_APPEND(QP_ATTR_QKEY)\r
- SAFE_APPEND(QP_ATTR_AV)\r
- SAFE_APPEND(QP_ATTR_PATH_MTU)\r
- SAFE_APPEND(QP_ATTR_TIMEOUT)\r
- SAFE_APPEND(QP_ATTR_RETRY_COUNT)\r
- SAFE_APPEND(QP_ATTR_RNR_RETRY)\r
- SAFE_APPEND(QP_ATTR_RQ_PSN)\r
- SAFE_APPEND(QP_ATTR_QP_OUS_RD_ATOM)\r
- SAFE_APPEND(QP_ATTR_ALT_PATH)\r
- SAFE_APPEND(QP_ATTR_RSRV_1)\r
- SAFE_APPEND(QP_ATTR_RSRV_2)\r
- SAFE_APPEND(QP_ATTR_RSRV_3)\r
- SAFE_APPEND(QP_ATTR_RSRV_4)\r
- SAFE_APPEND(QP_ATTR_RSRV_5)\r
- SAFE_APPEND(QP_ATTR_RSRV_6)\r
- //SAFE_APPEND(QP_ATTR_ALT_TIMEOUT)\r
- //SAFE_APPEND(QP_ATTR_ALT_RETRY_COUNT)\r
- //SAFE_APPEND(QP_ATTR_ALT_RNR_RETRY)\r
- //SAFE_APPEND(QP_ATTR_ALT_PKEY_IX)\r
- //SAFE_APPEND(QP_ATTR_ALT_PORT)\r
- SAFE_APPEND(QP_ATTR_MIN_RNR_TIMER)\r
- SAFE_APPEND(QP_ATTR_SQ_PSN)\r
- SAFE_APPEND(QP_ATTR_OUS_DST_RD_ATOM)\r
- SAFE_APPEND(QP_ATTR_PATH_MIG_STATE)\r
- SAFE_APPEND(QP_ATTR_CAP)\r
- SAFE_APPEND(QP_ATTR_DEST_QP_NUM)\r
- end_mask_sym(buf, cbuf, bufsz);\r
- return buf;\r
-} /* VAPI_qp_attr_mask_sym */\r
-\r
-\r
-const char* VAPI_mrw_acl_mask_sym(char* buf, int bufsz, u_int32_t mask)\r
-{\r
- INIT_BUF_SKIP("VAPI_EN_")\r
-\r
- SAFE_APPEND(VAPI_EN_LOCAL_WRITE)\r
- SAFE_APPEND(VAPI_EN_REMOTE_WRITE)\r
- SAFE_APPEND(VAPI_EN_REMOTE_READ)\r
- SAFE_APPEND(VAPI_EN_REMOTE_ATOM)\r
- SAFE_APPEND(VAPI_EN_MEMREG_BIND)\r
- end_mask_sym(buf, cbuf, bufsz);\r
- return buf;\r
-} /* VAPI_mrw_acl_mask_sym */\r
-\r
-\r
-const char* VAPI_mr_change_mask_sym(char* buf, int bufsz, u_int32_t mask)\r
-{\r
- INIT_BUF_SKIP("VAPI_MR_")\r
-\r
- SAFE_APPEND(VAPI_MR_CHANGE_TRANS)\r
- SAFE_APPEND(VAPI_MR_CHANGE_PD)\r
- SAFE_APPEND(VAPI_MR_CHANGE_ACL)\r
- end_mask_sym(buf, cbuf, bufsz);\r
- return buf;\r
-} /* VAPI_mr_change_mask_sym */\r
-\r
-\r
-const char* VAPI_rdma_atom_acl_mask_sym(char* buf, int bufsz, u_int32_t mask)\r
-{\r
- INIT_BUF_SKIP("VAPI_EN_REM_")\r
- SAFE_APPEND(VAPI_EN_REM_WRITE)\r
- SAFE_APPEND(VAPI_EN_REM_READ)\r
- SAFE_APPEND(VAPI_EN_REM_ATOMIC_OP)\r
- end_mask_sym(buf, cbuf, bufsz);\r
- return buf;\r
-} /* VAPI_rdma_atom_acl_sym */\r
-\r
-\r
-#define CASE_SETSTR(e) case e: s = #e; break;\r
-static const char* UnKnown = "UnKnown";\r
-\r
-const char* VAPI_atomic_cap_sym(VAPI_atomic_cap_t e)\r
-{\r
- const char* s = UnKnown;\r
- switch (e)\r
- {\r
- CASE_SETSTR(VAPI_ATOMIC_CAP_NONE)\r
- CASE_SETSTR(VAPI_ATOMIC_CAP_HCA)\r
- CASE_SETSTR(VAPI_ATOMIC_CAP_GLOB)\r
- default: ;\r
- }\r
- return s;\r
-} /* VAPI_atomic_cap_sym */\r
-\r
-\r
-const char* VAPI_sig_type_sym(VAPI_sig_type_t e)\r
-{\r
- const char* s = UnKnown;\r
- switch (e)\r
- {\r
- CASE_SETSTR(VAPI_SIGNAL_ALL_WR)\r
- CASE_SETSTR(VAPI_SIGNAL_REQ_WR)\r
- default: ;\r
- }\r
- return s;\r
-} /* VAPI_sig_type_sym */\r
-\r
-\r
-const char* VAPI_ts_type_sym(VAPI_ts_type_t e)\r
-{\r
- const char* s = UnKnown;\r
- switch (e)\r
- {\r
- CASE_SETSTR(VAPI_TS_RC)\r
- CASE_SETSTR(VAPI_TS_RD)\r
- CASE_SETSTR(VAPI_TS_UC)\r
- CASE_SETSTR(VAPI_TS_UD)\r
- CASE_SETSTR(VAPI_TS_RAW)\r
- default: ;\r
- }\r
- return s;\r
-} /* VAPI_ts_type_sym */\r
-\r
-\r
-const char* VAPI_qp_state_sym(VAPI_qp_state_t e)\r
-{\r
- const char* s = UnKnown;\r
- switch (e)\r
- {\r
- CASE_SETSTR(VAPI_RESET)\r
- CASE_SETSTR(VAPI_INIT)\r
- CASE_SETSTR(VAPI_RTR)\r
- CASE_SETSTR(VAPI_RTS)\r
- CASE_SETSTR(VAPI_SQD)\r
- CASE_SETSTR(VAPI_SQE)\r
- CASE_SETSTR(VAPI_ERR)\r
- default: ;\r
- }\r
- return s;\r
-} /* VAPI_qp_state_sym */\r
-\r
-\r
-const char* VAPI_mig_state_sym(VAPI_mig_state_t e)\r
-{\r
- const char* s = UnKnown;\r
- switch (e)\r
- {\r
- CASE_SETSTR(VAPI_MIGRATED)\r
- CASE_SETSTR(VAPI_REARM)\r
- CASE_SETSTR(VAPI_ARMED)\r
- default: ;\r
- }\r
- return s;\r
-} /* VAPI_mig_state_sym */\r
-\r
-\r
-const char* VAPI_special_qp_sym(VAPI_special_qp_t e)\r
-{\r
- const char* s = UnKnown;\r
- switch (e)\r
- {\r
- CASE_SETSTR(VAPI_REGULAR_QP)\r
- CASE_SETSTR(VAPI_SMI_QP)\r
- CASE_SETSTR(VAPI_GSI_QP)\r
- CASE_SETSTR(VAPI_RAW_IPV6_QP)\r
- CASE_SETSTR(VAPI_RAW_ETY_QP)\r
- default: ;\r
- }\r
- return s;\r
-} /* VAPI_special_qp_sym */\r
-\r
-\r
-const char* VAPI_mrw_type_sym(VAPI_mrw_type_t e)\r
-{\r
- const char* s = UnKnown;\r
- switch (e)\r
- {\r
- CASE_SETSTR(VAPI_MR)\r
- CASE_SETSTR(VAPI_MW)\r
- CASE_SETSTR(VAPI_MPR)\r
- CASE_SETSTR(VAPI_MSHAR)\r
- default: ;\r
- }\r
- return s;\r
-} /* VAPI_mrw_type_sym */\r
-\r
-\r
-const char* VAPI_remote_node_addr_sym(VAPI_remote_node_addr_type_t e)\r
-{\r
- const char* s = UnKnown;\r
- switch (e)\r
- {\r
- CASE_SETSTR(VAPI_RNA_RD)\r
- CASE_SETSTR(VAPI_RNA_UD)\r
- CASE_SETSTR(VAPI_RNA_RAW_ETY)\r
- CASE_SETSTR(VAPI_RNA_RAW_IPV6)\r
- default: ;\r
- }\r
- return s;\r
-} /* VAPI_remote_node_addr_sym */\r
-\r
-\r
-const char* VAPI_wr_opcode_sym(VAPI_wr_opcode_t e)\r
-{\r
- const char* s = UnKnown;\r
- switch (e)\r
- {\r
- CASE_SETSTR(VAPI_RDMA_WRITE)\r
- CASE_SETSTR(VAPI_RDMA_WRITE_WITH_IMM)\r
- CASE_SETSTR(VAPI_SEND)\r
- CASE_SETSTR(VAPI_SEND_WITH_IMM)\r
- CASE_SETSTR(VAPI_RDMA_READ)\r
- CASE_SETSTR(VAPI_ATOMIC_CMP_AND_SWP)\r
- CASE_SETSTR(VAPI_ATOMIC_FETCH_AND_ADD)\r
- CASE_SETSTR(VAPI_RECEIVE)\r
- default: ;\r
- }\r
- return s;\r
-} /* VAPI_wr_opcode_sym */\r
-\r
-\r
-const char* VAPI_cqe_opcode_sym(VAPI_cqe_opcode_t e)\r
-{\r
- const char* s = UnKnown;\r
- switch (e)\r
- {\r
- CASE_SETSTR(VAPI_CQE_SQ_SEND_DATA)\r
- CASE_SETSTR(VAPI_CQE_SQ_RDMA_WRITE)\r
- CASE_SETSTR(VAPI_CQE_SQ_RDMA_READ)\r
- CASE_SETSTR(VAPI_CQE_SQ_COMP_SWAP)\r
- CASE_SETSTR(VAPI_CQE_SQ_FETCH_ADD)\r
- CASE_SETSTR(VAPI_CQE_SQ_BIND_MRW)\r
- CASE_SETSTR(VAPI_CQE_RQ_SEND_DATA)\r
- CASE_SETSTR(VAPI_CQE_RQ_RDMA_WITH_IMM)\r
- default: ;\r
- }\r
- return s;\r
-} /* VAPI_cqe_opcode_sym */\r
-\r
-\r
-const char* VAPI_wc_status_sym(VAPI_wc_status_t e)\r
-{\r
- const char* s = UnKnown;\r
- switch (e)\r
- {\r
- CASE_SETSTR(VAPI_SUCCESS)\r
- CASE_SETSTR(VAPI_LOC_LEN_ERR)\r
- CASE_SETSTR(VAPI_LOC_QP_OP_ERR)\r
- CASE_SETSTR(VAPI_LOC_EE_OP_ERR)\r
- CASE_SETSTR(VAPI_LOC_PROT_ERR)\r
- CASE_SETSTR(VAPI_WR_FLUSH_ERR)\r
- CASE_SETSTR(VAPI_MW_BIND_ERR)\r
- CASE_SETSTR(VAPI_BAD_RESP_ERR)\r
- CASE_SETSTR(VAPI_LOC_ACCS_ERR)\r
- CASE_SETSTR(VAPI_REM_INV_REQ_ERR)\r
- CASE_SETSTR(VAPI_REM_ACCESS_ERR)\r
- CASE_SETSTR(VAPI_REM_OP_ERR)\r
- CASE_SETSTR(VAPI_RETRY_EXC_ERR)\r
- CASE_SETSTR(VAPI_RNR_RETRY_EXC_ERR)\r
- CASE_SETSTR(VAPI_LOC_RDD_VIOL_ERR)\r
- CASE_SETSTR(VAPI_REM_INV_RD_REQ_ERR)\r
- CASE_SETSTR(VAPI_REM_ABORT_ERR)\r
- CASE_SETSTR(VAPI_INV_EECN_ERR)\r
- CASE_SETSTR(VAPI_INV_EEC_STATE_ERR)\r
- CASE_SETSTR(VAPI_COMP_FATAL_ERR)\r
- CASE_SETSTR(VAPI_COMP_GENERAL_ERR)\r
- default: ;\r
- }\r
- return s;\r
-} /* VAPI_wc_status_sym */\r
-\r
-\r
-const char* VAPI_comp_type_sym(VAPI_comp_type_t e)\r
-{\r
- const char* s = UnKnown;\r
- switch (e)\r
- {\r
- CASE_SETSTR(VAPI_SIGNALED)\r
- CASE_SETSTR(VAPI_UNSIGNALED)\r
- default: ;\r
- }\r
- return s;\r
-} /* VAPI_comp_type_sym */\r
-\r
-\r
-const char* VAPI_cq_notif_sym(VAPI_cq_notif_type_t e)\r
-{\r
- const char* s = UnKnown;\r
- switch (e)\r
- {\r
- CASE_SETSTR(VAPI_NOTIF_NONE)\r
- CASE_SETSTR(VAPI_SOLIC_COMP)\r
- CASE_SETSTR(VAPI_NEXT_COMP)\r
- default: ;\r
- }\r
- return s;\r
-} /* VAPI_cq_notif_sym */\r
-\r
-\r
-const char* VAPI_event_record_sym(VAPI_event_record_type_t e)\r
-{\r
- const char* s = UnKnown;\r
- switch (e)\r
- {\r
- CASE_SETSTR(VAPI_QP_PATH_MIGRATED)\r
- CASE_SETSTR(VAPI_EEC_PATH_MIGRATED)\r
- CASE_SETSTR(VAPI_QP_COMM_ESTABLISHED)\r
- CASE_SETSTR(VAPI_EEC_COMM_ESTABLISHED)\r
- CASE_SETSTR(VAPI_SEND_QUEUE_DRAINED)\r
- CASE_SETSTR(VAPI_CQ_ERROR)\r
- CASE_SETSTR(VAPI_LOCAL_WQ_INV_REQUEST_ERROR)\r
- CASE_SETSTR(VAPI_LOCAL_WQ_ACCESS_VIOL_ERROR)\r
- CASE_SETSTR(VAPI_LOCAL_WQ_CATASTROPHIC_ERROR)\r
- CASE_SETSTR(VAPI_PATH_MIG_REQ_ERROR)\r
- CASE_SETSTR(VAPI_LOCAL_EEC_CATASTROPHIC_ERROR)\r
- CASE_SETSTR(VAPI_LOCAL_CATASTROPHIC_ERROR)\r
- CASE_SETSTR(VAPI_PORT_ERROR)\r
- CASE_SETSTR(VAPI_PORT_ACTIVE)\r
- CASE_SETSTR(VAPI_RECEIVE_QUEUE_DRAINED)\r
- CASE_SETSTR(VAPI_SRQ_LIMIT_REACHED)\r
- CASE_SETSTR(VAPI_SRQ_CATASTROPHIC_ERROR)\r
- default: ;\r
- }\r
- return s;\r
-} /* VAPI_event_record_sym */\r
-\r
-const char* VAPI_event_syndrome_sym(VAPI_event_syndrome_t e)\r
-{\r
- const char* s = UnKnown;\r
- switch (e)\r
- {\r
- CASE_SETSTR(VAPI_EV_SYNDROME_NONE)\r
- CASE_SETSTR(VAPI_CATAS_ERR_FW_INTERNAL)\r
- CASE_SETSTR(VAPI_CATAS_ERR_EQ_OVERFLOW)\r
- CASE_SETSTR(VAPI_CATAS_ERR_MISBEHAVED_UAR_PAGE)\r
- CASE_SETSTR(VAPI_CATAS_ERR_UPLINK_BUS_ERR)\r
- CASE_SETSTR(VAPI_CATAS_ERR_HCA_DDR_DATA_ERR)\r
- CASE_SETSTR(VAPI_CATAS_ERR_INTERNAL_PARITY_ERR)\r
- CASE_SETSTR(VAPI_CATAS_ERR_MASTER_ABORT)\r
- CASE_SETSTR(VAPI_CATAS_ERR_GO_BIT)\r
- CASE_SETSTR(VAPI_CATAS_ERR_CMD_TIMEOUT)\r
- CASE_SETSTR(VAPI_CATAS_ERR_FATAL_CR)\r
- CASE_SETSTR(VAPI_CATAS_ERR_FATAL_TOKEN)\r
- CASE_SETSTR(VAPI_CATAS_ERR_GENERAL)\r
- CASE_SETSTR(VAPI_CQ_ERR_OVERRUN)\r
- CASE_SETSTR(VAPI_CQ_ERR_ACCESS_VIOL)\r
- CASE_SETSTR(VAPI_CATAS_ERR_FATAL_EXTERNAL)\r
- default: ;\r
- }\r
- return s;\r
-}\r
-\r
-\r
-#if defined(TEST_VAPI_COMMON)\r
-/* compile via:\r
- gcc -g -DTEST_VAPI_COMMON -I.. -I$MTHOME/include -o /tmp/x vapi_common.c\r
- */\r
-int main(int argc, char** argv)\r
-{\r
- char buffer[100];\r
- char* cbuffer = &buffer[0];\r
- u_int32_t m = VAPI_BAD_PKEY_COUNT_CAP | VAPI_AUTO_PATH_MIG_CAP;\r
- printf("m=%s\n", VAPI_hca_cap_sym(buffer, sizeof(buffer), m));\r
- printf("trunc1: m=%s\n", VAPI_hca_cap_sym(buffer, 1, m));\r
- printf("trunc10: m=%s\n", VAPI_hca_cap_sym(buffer, 10, m));\r
-\r
- return 0;\r
-}\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_VAPI_COMMON_H\r
-#define H_VAPI_COMMON_H\r
-\r
-#include <vapi_types.h>\r
-\r
-extern const char* VAPI_strerror( VAPI_ret_t errnum);\r
-extern const char* VAPI_strerror_sym( VAPI_ret_t errnum);\r
-\r
-/* Mask to symbol function. User supplies buffer (buf) which is ensured\r
- * not to overflow beyond bufsz. The buf pointer is conveniently returned.\r
- */\r
-extern const char* VAPI_hca_cap_sym(char* buf, int bufsz, u_int32_t mask);\r
-extern const char* VAPI_hca_attr_mask_sym(char* buf, int bufsz, u_int32_t mask);\r
-extern const char* VAPI_qp_attr_mask_sym(char* buf, int bufsz, u_int32_t mask);\r
-extern const char* VAPI_mrw_acl_mask_sym(char* buf, int bufsz, u_int32_t mask);\r
-extern const char* VAPI_mr_change_mask_sym(char* buf, int bufsz, u_int32_t msk);\r
-extern const char* VAPI_rdma_atom_acl_mask_sym(char*, int, u_int32_t);\r
-\r
-extern const char* VAPI_atomic_cap_sym(VAPI_atomic_cap_t e);\r
-extern const char* VAPI_sig_type_sym(VAPI_sig_type_t e);\r
-extern const char* VAPI_ts_type_sym(VAPI_ts_type_t e);\r
-extern const char* VAPI_qp_state_sym(VAPI_qp_state_t e);\r
-extern const char* VAPI_mig_state_sym(VAPI_mig_state_t e);\r
-extern const char* VAPI_special_qp_sym(VAPI_special_qp_t e);\r
-extern const char* VAPI_mrw_type_sym(VAPI_mrw_type_t e);\r
-extern const char* VAPI_remote_node_addr_sym(VAPI_remote_node_addr_type_t e);\r
-extern const char* VAPI_wr_opcode_sym(VAPI_wr_opcode_t e);\r
-extern const char* VAPI_cqe_opcode_sym(VAPI_cqe_opcode_t e);\r
-extern const char* VAPI_wc_status_sym(VAPI_wc_status_t e);\r
-extern const char* VAPI_comp_type_sym(VAPI_comp_type_t e);\r
-extern const char* VAPI_cq_notif_sym(VAPI_cq_notif_type_t e);\r
-extern const char* VAPI_event_record_sym(VAPI_event_record_type_t e);\r
-extern const char* VAPI_event_syndrome_sym(VAPI_event_syndrome_t e);\r
-\r
-\r
-#define VAPI_RET_PRINT(ret) { MTL_ERROR1("%s: %d : %s (%s).\n", __func__, __LINE__,VAPI_strerror(ret),VAPI_strerror_sym(ret));} \r
-#define VAPI_CHECK if ( ret != VAPI_OK) VAPI_RET_PRINT(ret);\r
-#define VAPI_CHECK_RET if ( ret != VAPI_OK) { VAPI_RET_PRINT(ret); return(ret); } \r
- \r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include <mosal.h>\r
-#include <vapi_common.h>\r
-\r
-#include "vip_array.h"\r
-\r
-#define ARRAY_INIT_NUM_ENTRIES (1<<16) /*16K initial size */\r
-#define ARRAY_INCR_NUM_ENTRIES (1<<16) /*16K increment size */\r
-#define ARRAY_MIN_SIZE 2 \r
-#define ARRAY_MAX_SIZE 0xFFFFFFFE\r
-#define ARRAY_RESIZE_ERR 0xFFFFFFFF\r
-#define ARRAY_DEFAULT_MAXSIZE (1 << 24) /* default max size is 16M entries */\r
-#define ARRAY_2ND_LVL_BLOCK_SIZE (2*MOSAL_SYS_PAGE_SIZE)\r
-#define ARRAY_2ND_LVL_ENTRIES_PER_BLOCK (ARRAY_2ND_LVL_BLOCK_SIZE / sizeof(VIP_array_internal_obj_t))\r
-#define ARRAY_2ND_LVL_ENTRY_SIZE (sizeof(VIP_array_internal_obj_t))\r
-\r
-#define CALCULATE_NEW_SIZE(curr_size, max_size, array) ((max_size - curr_size < ARRAY_INCR_NUM_ENTRIES) ? max_size : \\r
- curr_size + ARRAY_INCR_NUM_ENTRIES)\r
-#define AT_MAX_SIZE(curr_size, max_size) ((max_size == curr_size ) ? TRUE : FALSE)\r
- \r
-#define CALC_MAX_2ND_LVL_BLOCKS(array) ((array->max_size + (array->sec_lvl_entries_per_blk_m_1)) / (array->sec_lvl_entries_per_blk))\r
-#define CALC_NUM_2ND_LVL_BLOCKS(size, array) ((size + (array->sec_lvl_entries_per_blk_m_1)) / (array->sec_lvl_entries_per_blk))\r
-#define KMALLOC_1ST_LVL_MAX (1<<15) /* max 32K for first level kmalloc */\r
-\r
-typedef MT_size_t VIP_array_ref_cnt_t;\r
-\r
-typedef struct VIP_array_internal_obj_t {\r
- MT_ulong_ptr_t array_obj;\r
- VIP_array_ref_cnt_t ref_count; /* Handle reference count. (-1) if invalid. */\r
-} VIP_array_internal_obj_t;\r
-\r
-typedef VIP_array_internal_obj_t * VIP_array_1st_lvl_t;\r
-\r
-typedef struct VIP_array_t {\r
- VIP_array_1st_lvl_t *begin;\r
- VIP_array_ref_cnt_t first_invalid;\r
- u_int32_t size; \r
- u_int32_t watermark;\r
- u_int32_t size_allocated;\r
- u_int32_t max_size;\r
- u_int32_t sec_lvl_entries_per_blk_m_1; /* number of second level entries - 1 per block*/\r
- u_int32_t sec_lvl_entries_per_blk; /* number of second level entries per block*/\r
- u_int32_t size_2nd_lvl_block; /* number of bytes per second level block */\r
- u_int8_t log2_2nd_lvl_entries_per_blk; /* log2 of number of second level entries per blk*/\r
- MT_bool first_level_uses_vmalloc;\r
-\r
- MOSAL_spinlock_t array_lock;\r
- MOSAL_mutex_t resize_lock; //held while resize is in progress\r
-} VIP_array_t;\r
-\r
-#define INVALID_REF_VAL ((unsigned long)-1) /* Value to put in "ref_cnt" to mark invalid entry */\r
-#define PREP_ERASE_VAL ((unsigned long)-2) /* Value to put in "ref_cnt" to mark status: prepare to erase */\r
-\r
-#define GET_OBJ_BY_HNDL(array, handle) ((VIP_array_internal_obj_t *) &((*(array->begin+((handle) >> array->log2_2nd_lvl_entries_per_blk)))[(handle) & (array->sec_lvl_entries_per_blk_m_1)]))\r
-#define GET_OBJ_ARR_OBJ_BY_HNDL(array, handle) (GET_OBJ_BY_HNDL(array,handle))->array_obj\r
-#define GET_OBJ_REF_CNT_BY_HNDL(array, handle) (GET_OBJ_BY_HNDL(array,handle))->ref_count\r
-#define IS_INVALID_ASSIGN(vip_array_p,obj,i) (((obj = GET_OBJ_BY_HNDL(vip_array_p,i))==NULL) || (obj->ref_count == INVALID_REF_VAL)||(obj->ref_count == PREP_ERASE_VAL))\r
-#define IS_INVALID_OBJ(obj) ((obj->ref_count == INVALID_REF_VAL)||(obj->ref_count == PREP_ERASE_VAL))\r
-#define SET_INVALID_OBJ(obj) (obj->ref_count = INVALID_REF_VAL)\r
-#define SET_VALID_OBJ(obj) (obj->ref_count = 0)\r
-#define RESIZE_REQUIRED(array_obj) (array_obj->watermark >= array_obj->size_allocated))\r
-#define IS_NOT_BUSY_OBJ(obj,fl) (IS_INVALID_OBJ(obj) || ((fl == TRUE) && (obj->ref_count ==0)))\r
-\r
-static unsigned int floor_log2(u_int64_t x)\r
-{\r
- enum { nLowBits = 8 };\r
- static const u_int64_t \r
- highMask = ~(((u_int64_t)1 << nLowBits) - (u_int64_t)1);\r
- static const unsigned char lowlog2[1<<nLowBits] =\r
- {\r
- 0, /* special case (not -infinity) */\r
- 0,\r
- 1, 1,\r
- 2, 2, 2, 2,\r
- 3, 3, 3, 3, 3, 3, 3, 3,\r
- 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,\r
- 4, 4, 4, 4, 4, 4,\r
- 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,\r
- 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,\r
- 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,\r
- 5, 5,\r
- 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,\r
- 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,\r
- 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,\r
- 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,\r
- 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,\r
- 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,\r
- 6, 6, 6, 6,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 7, 7, 7, 7, 7, 7, 7, 7\r
- };\r
- \r
- unsigned step = 8*sizeof(u_int64_t);\r
- unsigned p = 0;\r
- while (x & highMask)\r
- {\r
- u_int64_t high;\r
- step >>= 1; /* /= 2 */\r
- high = (x >> step);\r
- if (high)\r
- {\r
- p |= step;\r
- x = high;\r
- }\r
- else\r
- {\r
- u_int64_t mask = ((u_int64_t)1 << step) - 1;\r
- x &= mask;\r
- }\r
- }\r
- \r
- p |= lowlog2[x];\r
- return p;\r
-} /* floor_log2 */\r
-\r
-\r
-/************************************************************************/\r
-static unsigned int ceil_log2(u_int64_t x)\r
-{\r
- unsigned int p = floor_log2(x);\r
- if (((u_int64_t)1 << p) < x)\r
- {\r
- p += 1;\r
- }\r
- return p;\r
-} /* ceil_log2 */\r
-\r
-/********************************************************************************/\r
-/* Resize array to given size_to_alloc entries */\r
-static VIP_common_ret_t resize_array(VIP_array_p_t a,u_int32_t size_to_alloc)\r
-{\r
- /* We can sample the value above with no lock, since there is only one thread\r
- * which can perform resize at one time \r
- */\r
- u_int32_t blocks_needed = 0, max_num_blocks = 0, curr_blocks = 0, block_size_to_allocate = 0;\r
- int i,j;\r
-\r
- MTL_DEBUG4(MT_FLFMT("realloc: watermark=%d, size_to_alloc=%d, size allocated = 0x%x, max_size=0x%x"), \r
- a->watermark, size_to_alloc, a->size_allocated, a->max_size);\r
- /* now, insert second level blocks until initial size is reached. If this is also the max size,\r
- * make sure that the last block allocation is only until the max number of entries needed. \r
- * Note that do not need special protection when adding new blocks to the array, since we have\r
- * not yet changed the allocated size for the array -- so the new blocks are not yet visible.\r
- */\r
-\r
- MOSAL_spinlock_dpc_lock(&(a->array_lock));\r
- if (size_to_alloc > a->max_size) {\r
- MOSAL_spinlock_unlock(&(a->array_lock));\r
- MTL_ERROR1(MT_FLFMT("resize_array: requested new size (0x%x)greater than max (0x%x)"), \r
- size_to_alloc, a->max_size);\r
- return VIP_EINVAL_PARAM;\r
- }\r
- max_num_blocks = CALC_MAX_2ND_LVL_BLOCKS(a);\r
- blocks_needed = CALC_NUM_2ND_LVL_BLOCKS(size_to_alloc,a);\r
- curr_blocks = CALC_NUM_2ND_LVL_BLOCKS(a->size_allocated,a);\r
- block_size_to_allocate = a->size_2nd_lvl_block;\r
- MOSAL_spinlock_unlock(&(a->array_lock));\r
- \r
- for (i = (int)curr_blocks; i < (int)blocks_needed; i++) {\r
- if (i == (int)max_num_blocks - 1) {\r
- block_size_to_allocate = (a->max_size - ((max_num_blocks-1)*(a->sec_lvl_entries_per_blk)))\r
- * ARRAY_2ND_LVL_ENTRY_SIZE;\r
- }\r
- a->begin[i] = (VIP_array_internal_obj_t*)MALLOC(block_size_to_allocate);\r
- if (a->begin[i] == NULL) {\r
- MTL_ERROR1(MT_FLFMT("VIP_array_create_maxsize: malloc failure at 2nd level block %d"), i);\r
- for (j = curr_blocks; j < i; j++) {\r
- FREE(a->begin[j]);\r
- a->begin[j] = NULL;\r
- }\r
- return VIP_EAGAIN;\r
- } else {\r
- memset(a->begin[i], 0xFF, block_size_to_allocate);\r
- }\r
- }\r
-\r
- /* adjust vip array object parameters */\r
- MOSAL_spinlock_dpc_lock(&(a->array_lock));\r
- a->size_allocated = size_to_alloc;\r
- MOSAL_spinlock_unlock(&(a->array_lock));\r
-\r
- return VIP_OK;\r
-} /* resize_array */\r
- \r
-\r
-/* This function either initiates a resize or wait for another thread to complete it */\r
-/* The function must be called with array's lock held\r
- */\r
-static VIP_common_ret_t resize_or_waitfor(VIP_array_p_t VIP_array, u_int32_t new_sz)\r
-{\r
- call_result_t mt_rc;\r
- VIP_common_ret_t rc;\r
-\r
- MTL_DEBUG4(MT_FLFMT("%s: Entering. new size = %d"),__func__, new_sz);\r
- MOSAL_spinlock_unlock(&(VIP_array->array_lock));\r
-\r
-\r
- mt_rc = MOSAL_mutex_acq(&(VIP_array->resize_lock),TRUE);\r
- if (mt_rc != MT_OK)\r
- {\r
- //assume MT_EINTR\r
- rc= VIP_EINTR;\r
- goto mutex_acq_lbl;\r
- }\r
-\r
- if (new_sz <= VIP_array->size_allocated)\r
- {\r
- rc = VIP_OK;\r
- goto size_check_lbl;\r
- }\r
-\r
- rc= resize_array(VIP_array,new_sz);\r
- if (rc) goto resize_lbl;\r
- \r
-resize_lbl:\r
-\r
-size_check_lbl:\r
- MOSAL_mutex_rel(&(VIP_array->resize_lock));\r
-\r
-mutex_acq_lbl:\r
- MOSAL_spinlock_dpc_lock(&(VIP_array->array_lock));\r
- return rc;\r
-}\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_create_maxsize\r
- *\r
- * Arguments:\r
- * VIP_array_p (OUT) - Return new VIP_array object here\r
- * maxsize - max number of entries in the array.\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EAGAIN: Not enough resources\r
- * VIP_EINVAL_PARAM: requested an array larger than max permitted size\r
- *\r
- * Description:\r
- * Create a new VIP_array table\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_create_maxsize(u_int32_t size, u_int32_t maxsize, VIP_array_p_t* VIP_array_p)\r
-{\r
- VIP_common_ret_t rc = VIP_EAGAIN;\r
- VIP_array_p_t array;\r
- u_int32_t max_num_blocks = 0, size_1st_lvl = 0;\r
-\r
- MTL_DEBUG4(MT_FLFMT("VIP_array_create_maxsize: size=0x%x, maxsize=0x%x"), size, maxsize);\r
- \r
- if ( size > maxsize) {\r
- MTL_ERROR1(MT_FLFMT("VIP_array_create_maxsize: requested size (0x%x) greater than supplied max size (0x%x"),\r
- size, maxsize);\r
- return VIP_EINVAL_PARAM;\r
- }\r
- if (size > ARRAY_MAX_SIZE) {\r
- MTL_ERROR1(MT_FLFMT("VIP_array_create: requested size (0x%x) greater than max permitted"), size);\r
- return VIP_EINVAL_PARAM;\r
- }\r
- array = TMALLOC(VIP_array_t);\r
- if (array == NULL) {\r
- MTL_ERROR1(MT_FLFMT("VIP_array_create: malloc failure"));\r
- return VIP_EAGAIN;\r
- }\r
-\r
- if (maxsize < ARRAY_MIN_SIZE) {maxsize = ARRAY_MIN_SIZE;}\r
-\r
- memset(array, 0, sizeof(VIP_array_t));\r
- array->max_size = maxsize;\r
- array->sec_lvl_entries_per_blk_m_1 = ARRAY_2ND_LVL_ENTRIES_PER_BLOCK-1;\r
- array->sec_lvl_entries_per_blk = ARRAY_2ND_LVL_ENTRIES_PER_BLOCK;\r
- array->size_2nd_lvl_block = ARRAY_2ND_LVL_BLOCK_SIZE;\r
-/*** warning C4242: '=' : conversion from 'unsigned int' to 'u_int8_t', possible loss of data ***/\r
- array->log2_2nd_lvl_entries_per_blk = (u_int8_t)ceil_log2(ARRAY_2ND_LVL_ENTRIES_PER_BLOCK);\r
- \r
- /* make sure that the first block set is always allocated in total -- unless max array size is less than entries\r
- per second level block\r
- */\r
-\r
- if (maxsize <= ARRAY_INIT_NUM_ENTRIES) { \r
- if (size < maxsize) {size = maxsize;}\r
- } else {\r
- if (size < ARRAY_INIT_NUM_ENTRIES) {\r
- size = ARRAY_INIT_NUM_ENTRIES;\r
- }\r
- }\r
-\r
- /* compute size of and allocate first-level allocation */\r
- max_num_blocks = CALC_MAX_2ND_LVL_BLOCKS(array);\r
- size_1st_lvl = sizeof(VIP_array_1st_lvl_t) * max_num_blocks;\r
-\r
- /* use KMALLOC if first level size is smaller than 32K */\r
- array->begin = (size_1st_lvl <= KMALLOC_1ST_LVL_MAX) ? TNMALLOC(VIP_array_1st_lvl_t, max_num_blocks) : NULL;\r
- if (array->begin == NULL) {\r
- array->first_level_uses_vmalloc = TRUE;\r
- array->begin = TNVMALLOC(VIP_array_1st_lvl_t, max_num_blocks);\r
- if (array->begin == NULL) {\r
- MTL_ERROR1(MT_FLFMT("VIP_array_create: malloc failure for size 0x%x"), (u_int32_t)(size_1st_lvl));\r
- rc = VIP_EAGAIN;\r
- goto first_lvl_fail;\r
- }\r
- }\r
-\r
- memset(array->begin, 0, size_1st_lvl);\r
- array->first_invalid = INVALID_REF_VAL;\r
- array->size = 0;\r
- array->watermark = 0;\r
- array->size_allocated = 0;\r
- MOSAL_spinlock_init(&(array->array_lock));\r
-\r
- rc = resize_array(array,size);\r
- if (rc != VIP_OK) {\r
- MTL_ERROR1(MT_FLFMT("VIP_array_create_maxsize: 2nd level alloc failure for size 0x%x"),\r
- (u_int32_t)(sizeof(VIP_array_1st_lvl_t)* maxsize));\r
- goto second_lvl_fail;\r
- }\r
- MOSAL_mutex_init(&(array->resize_lock));\r
- *VIP_array_p = array;\r
- rc = VIP_OK;\r
- \r
- MTL_DEBUG4(MT_FLFMT("VIP_array_create: rc=%d"), rc);\r
- return rc;\r
-\r
-second_lvl_fail:\r
- if (array->first_level_uses_vmalloc) {\r
- VFREE(array->begin);\r
- } else {\r
- FREE(array->begin);\r
- }\r
-first_lvl_fail:\r
- FREE(array);\r
- return rc;\r
-} /* VIP_array_create_maxsize */\r
-\r
-VIP_common_ret_t VIP_array_create(u_int32_t size, VIP_array_p_t* VIP_array_p)\r
-{\r
- return VIP_array_create_maxsize(size,ARRAY_DEFAULT_MAXSIZE,VIP_array_p);\r
-}\r
-\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_destroy\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - Object to destroy\r
- * force (IN) - If false do not destroy VIP_array that is not empty\r
- * FREE_objects (IN) - If true destroy objects pointed from the array\r
- *\r
- * Returns:\r
- * VIP_OK\r
- *\r
- * Description:\r
- * cleanup resources for a VIP_array table\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_destroy(VIP_array_p_t VIP_array,\r
- VIP_allocator_free_t free_objects_fun)\r
-{\r
- VIP_common_ret_t ret=VIP_OK;\r
- VIP_array_handle_t hdl;\r
- VIP_array_obj_t obj;\r
- u_int32_t max_num_blocks;\r
- int i;\r
- call_result_t mt_rc = MT_OK;\r
- \r
- if (VIP_array == NULL) return VIP_EINVAL_HNDL;\r
- MTL_DEBUG4("Inside " "%s:Array size %d\n", __func__, VIP_array->size);\r
- \r
-\r
-\r
- if (VIP_array->size != 0 && free_objects_fun) {\r
- ret = VIP_array_get_first_handle(VIP_array, &hdl, &obj);\r
- while (ret == VIP_OK) {\r
- free_objects_fun(obj);\r
- ret= VIP_array_get_next_handle(VIP_array,&hdl, &obj);\r
- }\r
- }\r
- /*free second level allocations */\r
-\r
- max_num_blocks = CALC_MAX_2ND_LVL_BLOCKS(VIP_array);\r
- for (i = 0; i < (int)max_num_blocks; i++) {\r
- if (VIP_array->begin[i] == NULL) {break;}\r
- FREE(VIP_array->begin[i]);\r
- }\r
-\r
- /* now, free first level allocation */\r
- if (VIP_array->first_level_uses_vmalloc) {\r
- VFREE(VIP_array->begin);\r
- } else {\r
- FREE(VIP_array->begin);\r
- }\r
- mt_rc = MOSAL_mutex_free(&(VIP_array->resize_lock));\r
- if (mt_rc != MT_OK) {\r
- MTL_ERROR2(MT_FLFMT("Failed MOSAL_syncobj_free (%s)"),mtl_strerror_sym(mt_rc));\r
- }\r
- FREE(VIP_array);\r
- return VIP_OK;\r
-}\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_insert\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - Insert in this table\r
- * obj (IN) - object to insert\r
- * handle_p (OUT) - handle for this object\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EAGAIN: not enough resources\r
- *\r
- * Description:\r
- * Associate this object with this handle.\r
- * Return the object associated with this handle.\r
- * Note: No check is done that the object is not already\r
- * in the array.\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_insert(VIP_array_p_t VIP_array, VIP_array_obj_t obj,\r
- VIP_array_handle_t* handle_p ) \r
-{\r
- VIP_common_ret_t rc;\r
- register VIP_array_internal_obj_t *itl_obj_p = NULL;\r
- \r
- MTL_DEBUG4(MT_FLFMT("VIP_array_insert: %p"), obj);\r
- if (VIP_array == NULL) return VIP_EINVAL_HNDL;\r
- /* First, try to use the list of invalid */\r
- MOSAL_spinlock_dpc_lock(&(VIP_array->array_lock));\r
-\r
- while (1) { \r
- /* Try allocating free entry. In case of "resize", a retry is required\r
- * since during spinlock release a lot could happen.\r
- */\r
- if (VIP_array->first_invalid != INVALID_REF_VAL) { /* Check on free list */\r
- *handle_p = (VIP_array_handle_t)VIP_array->first_invalid;\r
- /* Move the list head to point to the next invalid handle */\r
- itl_obj_p = GET_OBJ_BY_HNDL(VIP_array,(*handle_p));\r
- VIP_array->first_invalid = itl_obj_p->array_obj;\r
- break;\r
- } else { /* If free list is empty, take next free pointed by "watermark" */\r
- /* check for allocation: "watermark" is valid only if it does not exceeds array size */\r
- if (VIP_array->watermark >= VIP_array->size_allocated) {/* resize required ? */ \r
- if (AT_MAX_SIZE(VIP_array->size_allocated, VIP_array->max_size)) {\r
- MOSAL_spinlock_unlock(&(VIP_array->array_lock));\r
- MTL_ERROR1(MT_FLFMT("%s: Array size already at maximum (0x%x)"),__func__,VIP_array->max_size);\r
- return VIP_EAGAIN;\r
- }\r
- rc= resize_or_waitfor(VIP_array, CALCULATE_NEW_SIZE(VIP_array->size_allocated, VIP_array->max_size, VIP_array));\r
- if (rc != VIP_OK) { /* Fatal error */\r
- MOSAL_spinlock_unlock(&(VIP_array->array_lock));\r
- MTL_ERROR1(MT_FLFMT("%s: Failed resizing array (%s %d)"),__func__,VAPI_strerror_sym((VAPI_ret_t)rc),rc);\r
- return rc;\r
- }\r
- continue; \r
- /* Retry all process - maybe some "frees" were done while spinlock was unlocked */\r
- } else { /* There are free entries at "watermark" */\r
- *handle_p = VIP_array->watermark++;\r
- itl_obj_p = GET_OBJ_BY_HNDL(VIP_array,*handle_p);\r
- break;\r
- } /* if "watermark" */\r
- } /* if "free list" */\r
- } /* while */\r
-\r
- /* Reaching this point means "*handle_p" and "itl_obj_p" are valid */\r
- itl_obj_p->array_obj = (MT_ulong_ptr_t) obj; /* Put object in entry */\r
- SET_VALID_OBJ(itl_obj_p); /* implies ref_cnt=0 */\r
- ++VIP_array->size;\r
-\r
- MOSAL_spinlock_unlock(&(VIP_array->array_lock));\r
-\r
- return VIP_OK; /* If reached here, allocation was successful */\r
-} /* VIP_array_insert */\r
-\r
-\r
-\r
-VIP_common_ret_t VIP_array_insert2hndl(VIP_array_p_t VIP_array, VIP_array_obj_t obj,\r
- VIP_array_handle_t hndl )\r
-{\r
- VIP_common_ret_t rc;\r
- MT_ulong_ptr_t prev_hndl,cur_hndl;\r
- u_int32_t required_size= 0;\r
- register VIP_array_internal_obj_t *itl_obj_p = NULL;\r
-\r
- \r
- MTL_DEBUG4(MT_FLFMT("VIP_array_insert: %p"), obj);\r
- if (VIP_array == NULL) return VIP_EINVAL_HNDL;\r
- if (VIP_array->max_size < hndl) {\r
- MTL_ERROR1(MT_FLFMT("%s: requested handle (0x%x) greater than array maximum"),__func__,hndl);\r
- return VIP_EINVAL_PARAM;\r
- }\r
- required_size = VIP_array->size_allocated;\r
- while (required_size <= VIP_array->max_size) {\r
- if (required_size >= hndl+1) {break;}\r
- if (required_size == VIP_array->max_size) {\r
- MTL_ERROR1(MT_FLFMT("%s: requested handle (0x%x) greater than array maximum"),__func__,hndl);\r
- return VIP_EINVAL_PARAM;\r
- }\r
- //MTL_DEBUG3(MT_FLFMT("%s: loop: new required size = %d"),__func__, required_size );\r
- required_size = CALCULATE_NEW_SIZE(required_size, VIP_array->max_size, VIP_array);\r
- }\r
- \r
- MTL_DEBUG3(MT_FLFMT("%s: new array size = %d"),__func__, required_size );\r
-\r
- /* First, try to use the list of invalid */\r
- MOSAL_spinlock_dpc_lock(&(VIP_array->array_lock));\r
- /* retry resize until requested size is reached */ \r
- while (required_size > (VIP_array->size_allocated)) {\r
- rc= resize_or_waitfor(VIP_array,required_size);\r
- if (rc != VIP_OK) { /* Fatal error */\r
- MOSAL_spinlock_unlock(&(VIP_array->array_lock));\r
- MTL_ERROR1(MT_FLFMT("%s: Failed resizing array (%s %d)"),__func__,VAPI_strerror_sym((VAPI_ret_t)rc),rc);\r
- return rc;\r
- }\r
- } /* while resize_or_waitfor */\r
-\r
- itl_obj_p = GET_OBJ_BY_HNDL(VIP_array, hndl);\r
- if (!IS_INVALID_OBJ(itl_obj_p)) {\r
- MOSAL_spinlock_unlock(&(VIP_array->array_lock));\r
- MTL_ERROR1(MT_FLFMT("%s: Handle %d is already in use"),__func__,hndl);\r
- return VIP_EBUSY;\r
- }\r
- \r
- if (VIP_array->watermark <= hndl) { /* taking a hndl above (or at) watermark */\r
- /* Insert handles up to requested to free list */\r
- while (VIP_array->watermark < hndl) {\r
- VIP_array_internal_obj_t *loop_obj_p = GET_OBJ_BY_HNDL(VIP_array,VIP_array->watermark);\r
- /* Attach to "free list" */\r
- loop_obj_p->array_obj = (MT_ulong_ptr_t) VIP_array->first_invalid;\r
- loop_obj_p->ref_count = INVALID_REF_VAL;\r
- VIP_array->first_invalid = VIP_array->watermark;\r
- VIP_array->watermark++;\r
- }\r
- VIP_array->watermark++; /* Allocate entry at "hndl" */\r
- } else { /* Requested handle is in the free list */\r
- /* Look for the entry and remove from free list */\r
- for (prev_hndl= INVALID_REF_VAL, cur_hndl= VIP_array->first_invalid;\r
- cur_hndl != INVALID_REF_VAL; \r
- prev_hndl= cur_hndl, cur_hndl= GET_OBJ_ARR_OBJ_BY_HNDL(VIP_array, cur_hndl)) {\r
- if (cur_hndl == (MT_ulong_ptr_t)hndl) break; /* handle found */\r
- }\r
- if (cur_hndl == INVALID_REF_VAL) {\r
- MOSAL_spinlock_unlock(&(VIP_array->array_lock));\r
- MTL_ERROR3(MT_FLFMT("%s: Unexpected error - could not find handle %d in free list"),__func__,\r
- hndl);\r
- return VIP_EFATAL;\r
- }\r
- /* Requested handle's entry found - removing from free list */\r
- if (prev_hndl != INVALID_REF_VAL) {\r
- GET_OBJ_ARR_OBJ_BY_HNDL(VIP_array,prev_hndl)= GET_OBJ_ARR_OBJ_BY_HNDL(VIP_array,cur_hndl); /* connect next to prev. */\r
- } else {\r
- VIP_array->first_invalid= GET_OBJ_ARR_OBJ_BY_HNDL(VIP_array,cur_hndl); /* next to first */\r
- }\r
- }\r
- \r
- /* Reaching this point means given hndl was found */\r
- itl_obj_p->array_obj = (MT_ulong_ptr_t) obj; /* Put object in entry */\r
- SET_VALID_OBJ(itl_obj_p); /* implies ref_cnt=0 */\r
- ++VIP_array->size;\r
-\r
- MOSAL_spinlock_unlock(&(VIP_array->array_lock));\r
-\r
- return VIP_OK; /* If reached here, allocation was successful */\r
-}\r
-\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_insert_ptr\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - Insert in this table\r
- * handle_p (OUT) - handle for this object\r
- * obj (OUT) - pointer to new object\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EAGAIN: not enough resources\r
- *\r
- * Description:\r
- * Associate a new object with this handle.\r
- * This is like VIP_array_insert, but it returns\r
- * a pointer into the array through which the pointer \r
- * to the object can be set later\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_insert_ptr(\r
- VIP_array_p_t a,\r
- VIP_array_handle_t* handle_p,\r
- VIP_array_obj_t** obj\r
-)\r
-{\r
- VIP_common_ret_t rc = VIP_EAGAIN;\r
-\r
- MTL_DEBUG4(MT_FLFMT("VIP_array_insert_ptr"));\r
- rc= VIP_array_insert(a,0,handle_p);\r
- if ((rc == VIP_OK) && (obj)) *obj = (VIP_array_obj_t *)&(GET_OBJ_ARR_OBJ_BY_HNDL(a,(MT_ulong_ptr_t)*handle_p));\r
- return rc;\r
-} /* VIP_array_insert_ptr */\r
-\r
-\r
-/* selector for erase_handle() operation */\r
-typedef enum {\r
- VIP_ARRAY_ERASE,\r
- VIP_ARRAY_REL_ERASE,\r
- VIP_ARRAY_ERASE_PREP,\r
- VIP_ARRAY_REL_ERASE_PREP\r
-} VIP_array_erase_type_t;\r
-\r
-/* erase VIP_array handle on if only_this_obj is the object at that handle. */\r
-/* If only_this_obj==NULL, no check is done */\r
-static VIP_common_ret_t erase_handle(VIP_array_erase_type_t etype,\r
- VIP_array_p_t a, VIP_array_handle_t handle, \r
- VIP_array_obj_t* obj_p)\r
-{\r
- register VIP_array_internal_obj_t * itl_obj_p = NULL;\r
- if (a == NULL) return VIP_EINVAL_HNDL;\r
-\r
- MTL_DEBUG4(MT_FLFMT("VIP_array_erase: handle=%d, wmark=%d"), \r
- handle, a->watermark);\r
- \r
- MOSAL_spinlock_dpc_lock(&(a->array_lock));\r
- \r
- if (handle >= a->watermark || IS_INVALID_ASSIGN(a,itl_obj_p,handle) ) { /* Invalid handle */\r
- if (obj_p != NULL) *obj_p = NULL; /* Just "cosmetics" */\r
- MOSAL_spinlock_unlock(&(a->array_lock));\r
- return VIP_EINVAL_HNDL;\r
- }\r
-\r
- if ((etype == VIP_ARRAY_REL_ERASE) || (etype == VIP_ARRAY_REL_ERASE_PREP)) {\r
- itl_obj_p->ref_count--; /* Handle is release anyway */\r
- }\r
- \r
- if (itl_obj_p->ref_count > 0) {\r
- MTL_DEBUG1(MT_FLFMT("%s: handle=%d ref_cnt="SIZE_T_FMT), __func__, \r
- handle, itl_obj_p->ref_count);\r
- MOSAL_spinlock_unlock(&(a->array_lock));\r
- return VIP_EBUSY;\r
- }\r
-\r
-\r
- if (obj_p != NULL) {*obj_p = (VIP_array_obj_t)(itl_obj_p->array_obj);}\r
- switch (etype) {\r
- case VIP_ARRAY_ERASE:\r
- case VIP_ARRAY_REL_ERASE:\r
- SET_INVALID_OBJ(itl_obj_p);\r
- /* Attach to "free list" */\r
- itl_obj_p->array_obj = a->first_invalid;\r
- a->first_invalid = (MT_ulong_ptr_t) handle;\r
- --a->size;\r
- break;\r
- case VIP_ARRAY_ERASE_PREP:\r
- case VIP_ARRAY_REL_ERASE_PREP:\r
- itl_obj_p->ref_count = PREP_ERASE_VAL;\r
- break;\r
- default:\r
- MOSAL_spinlock_unlock(&(a->array_lock));\r
- MTL_ERROR1(MT_FLFMT("%s: function used with invalid erase type (%d)"),__func__,etype);\r
- return VIP_EINVAL_PARAM;\r
- }\r
- \r
- MOSAL_spinlock_unlock(&(a->array_lock));\r
- return VIP_OK;\r
-}\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_erase\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - this table\r
- * handle (IN) - remove object by this handle\r
- * obj (OUT) - if non zero, returns the object by this handle here\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EINVAL_HNDL: handle is not in the VIP_array\r
- * VIP_EBUSY\r
- *\r
- * Description:\r
- * Remove the object associated with this handle\r
- * Note: fails if handle is not already in the VIP_array\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_erase(VIP_array_p_t a, VIP_array_handle_t handle, \r
- VIP_array_obj_t* obj_p )\r
-{\r
- return erase_handle(VIP_ARRAY_ERASE,a,handle,obj_p);\r
-}\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_find_release_erase\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - this table\r
- * handle (IN) - remove object by this handle\r
- * obj (OUT) - if non zero, returns the object by this handle here\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EINVAL_HNDL: handle is not in the VIP_array, or only_this_obj don't match object at handle\r
- * VIP_EBUSY: Handle is still busy (ref_cnt > 0 , after dec.). ref_cnt is updated anyway.\r
- *\r
- * Description:\r
- * This function is a combination of VIP_array_find_release and VIP_array_erase.\r
- * The function atomically decrements the handle's reference count and check if it reached 0.\r
- * Only if the ref_cnt is 0, the object is erased. Otherwise, VIP_EBUSY is returned.\r
- * Note: The reference count is decrement by 1 even on VIP_EBUSY error.\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_find_release_erase(VIP_array_p_t a, VIP_array_handle_t handle, \r
- VIP_array_obj_t* obj_p )\r
-{\r
- return erase_handle(VIP_ARRAY_REL_ERASE,a,handle,obj_p);\r
-}\r
-\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_erase_prepare\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - Insert in this table\r
- * handle (IN) - remove object by this handle\r
- * obj (OUT) - if non zero, returns the object by this handle here\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EINVAL_HNDL: handle is not in the VIP_array\r
- * VIP_EBUSY: Handle's reference count > 0\r
- *\r
- * Description:\r
- * invalidate the object in the array, not yet removing the object associated with this handle\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_erase_prepare(VIP_array_p_t a, VIP_array_handle_t handle, \r
- VIP_array_obj_t* obj_p)\r
-{\r
- return erase_handle(VIP_ARRAY_ERASE_PREP,a,handle,obj_p);\r
-}\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_find_release_erase_prepare\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - this table\r
- * handle (IN) - remove object by this handle\r
- * obj (OUT) - if non zero, returns the object by this handle here\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EINVAL_HNDL: handle is not in the VIP_array, or only_this_obj don't match object at handle\r
- * VIP_EBUSY: Handle is still busy (ref_cnt > 0 , after dec.). ref_cnt is updated anyway.\r
- *\r
- * Description:\r
- * This function is a combination of VIP_array_find_release and VIP_array_erase_prepare.\r
- * The function atomically decrements the handle's reference count and check if it reached 0.\r
- * Only if the ref_cnt is 0, the object is erased (prep.). Otherwise, VIP_EBUSY is returned.\r
- * Note: The reference count is decrement by 1 even on VIP_EBUSY error.\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_find_release_erase_prepare(VIP_array_p_t a, VIP_array_handle_t handle, \r
- VIP_array_obj_t* obj_p )\r
-{\r
- return erase_handle(VIP_ARRAY_REL_ERASE_PREP,a,handle,obj_p);\r
-}\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_erase_undo\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - Insert in this table\r
- * handle (IN) - object by this handle\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EINVAL_HNDL: handle is not in the VIP_array or not was "erase prepare".\r
- *\r
- * Description:\r
- * revalidates the object of this handle, undo the erasing operation\r
- * see: VIP_array_erase_prepare\r
- * \r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_erase_undo(VIP_array_p_t a, VIP_array_handle_t handle)\r
-{\r
- register VIP_array_internal_obj_t *itl_obj_p = NULL;\r
- if (a == NULL) return VIP_EINVAL_HNDL;\r
- MTL_DEBUG4(MT_FLFMT("VIP_array_erase_roll: handle=%d, wmark=%d"), \r
- handle, a->watermark);\r
-\r
- MOSAL_spinlock_dpc_lock(&(a->array_lock));\r
-\r
- if ((handle >= a->watermark) || ((itl_obj_p = GET_OBJ_BY_HNDL(a,handle)) == NULL) || (itl_obj_p->ref_count!= PREP_ERASE_VAL)) { /* Invalid handle */\r
- MOSAL_spinlock_unlock(&(a->array_lock));\r
- return VIP_EINVAL_HNDL;\r
- }\r
- SET_VALID_OBJ(itl_obj_p);\r
-\r
- MOSAL_spinlock_unlock(&(a->array_lock));\r
- return VIP_OK;\r
-}\r
-\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_erase_done\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - Insert in this table\r
- * handle (IN) - remove object by this handle\r
- * obj (OUT) - if non zero, returns the object by this handle here\r
- * \r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EINVAL_HNDL: handle is not in the VIP_array or not was "erase prepare".\r
- *\r
- * Description:\r
- * removes the object associated with this handle\r
- * see: VIP_array_erase_prepare\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_erase_done(VIP_array_p_t a, VIP_array_handle_t handle, VIP_array_obj_t *obj)\r
-{\r
- register VIP_array_internal_obj_t *itl_obj_p = NULL;\r
- if (a == NULL) return VIP_EINVAL_HNDL;\r
-\r
- MTL_DEBUG4(MT_FLFMT("VIP_array_erase: handle=%d, wmark=%d"), \r
- handle, a->watermark);\r
- \r
- MOSAL_spinlock_dpc_lock(&(a->array_lock));\r
-\r
- if ((handle >= a->watermark) || ((itl_obj_p = GET_OBJ_BY_HNDL(a,handle)) == NULL) || (itl_obj_p->ref_count!= PREP_ERASE_VAL)) { /* Invalid handle */\r
- if (obj != NULL) *obj = NULL; /* Just "cosmetics" */\r
- MOSAL_spinlock_unlock(&(a->array_lock));\r
- return VIP_EINVAL_HNDL;\r
- }\r
-\r
- if (obj != NULL) {*obj = (VIP_array_obj_t)(itl_obj_p->array_obj);}\r
- SET_INVALID_OBJ(itl_obj_p);\r
- /* Attach to "free list" */\r
- itl_obj_p->array_obj = a->first_invalid;\r
- a->first_invalid = (MT_ulong_ptr_t) handle;\r
- --a->size;\r
- \r
- MOSAL_spinlock_unlock(&(a->array_lock));\r
- return VIP_OK;\r
-}\r
-\r
-\r
-VIP_common_ret_t VIP_array_find(VIP_array_p_t a, VIP_array_handle_t handle,\r
- VIP_array_obj_t* obj )\r
-{\r
- register VIP_array_internal_obj_t *itl_obj_p = NULL;\r
- if (a == NULL) return VIP_EINVAL_HNDL;\r
- MOSAL_spinlock_dpc_lock(&(a->array_lock));\r
- \r
- if (handle >= a->watermark || IS_INVALID_ASSIGN(a,itl_obj_p,handle) ) { /* Invalid handle */\r
- MOSAL_spinlock_unlock(&(a->array_lock));\r
- if (obj != NULL) *obj= NULL;\r
- return VIP_EINVAL_HNDL;\r
- }\r
- if (obj != NULL) *obj=(VIP_array_obj_t)(itl_obj_p->array_obj);\r
- \r
- MOSAL_spinlock_unlock(&(a->array_lock));\r
- return VIP_OK;\r
-}\r
-\r
-VIP_common_ret_t VIP_array_find_hold(VIP_array_p_t a, VIP_array_handle_t handle,\r
- VIP_array_obj_t* obj )\r
-{\r
- VIP_common_ret_t rc= VIP_OK;\r
- register VIP_array_internal_obj_t *itl_obj_p = NULL;\r
-\r
- if (a == NULL) return VIP_EINVAL_HNDL;\r
- MOSAL_spinlock_dpc_lock(&(a->array_lock));\r
- if (handle >= a->watermark || IS_INVALID_ASSIGN(a,itl_obj_p,handle)) { /* Invalid handle */\r
- if (obj != NULL) *obj= NULL;\r
- rc= VIP_EINVAL_HNDL;\r
- } else if ( itl_obj_p->ref_count == INVALID_REF_VAL-1) { /* protect from overflow */\r
- rc= VIP_EAGAIN; /* Try again later - when ref. cnt. will be smaller */\r
- } else {\r
- (itl_obj_p->ref_count)++;\r
- if (obj != NULL) *obj=(VIP_array_obj_t)(itl_obj_p->array_obj);\r
- }\r
-\r
- MOSAL_spinlock_unlock(&(a->array_lock));\r
- return rc;\r
-}\r
-\r
-VIP_common_ret_t VIP_array_find_release(VIP_array_p_t a, VIP_array_handle_t handle)\r
-{\r
- VIP_common_ret_t rc= VIP_OK;\r
- register VIP_array_internal_obj_t *itl_obj_p = NULL;\r
-\r
- if (a == NULL) return VIP_EINVAL_HNDL;\r
- MOSAL_spinlock_dpc_lock(&(a->array_lock));\r
- \r
- if (handle >= a->watermark || IS_INVALID_ASSIGN(a,itl_obj_p,handle)) { /* Invalid handle */\r
- rc= VIP_EINVAL_HNDL;\r
- } else if (itl_obj_p->ref_count == 0) { /* Caller did not invoke VIP_array_find_hold for this handle */\r
- rc= VIP_EINVAL_HNDL;\r
- } else {\r
- (itl_obj_p->ref_count)--;\r
- MTL_DEBUG6(MT_FLFMT("%s: handle=0x%X ref_count="SIZE_T_DFMT"->"SIZE_T_DFMT), __func__, handle,\r
- itl_obj_p->ref_count+1 , itl_obj_p->ref_count);\r
- }\r
- \r
- MOSAL_spinlock_unlock(&(a->array_lock));\r
- return rc;\r
-}\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_get_allocated_size\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - table\r
- *\r
- * Returns:\r
- * current allocated size of the array\r
- *\r
- * Description:\r
- * allocated size of the arrays\r
- *\r
- ********************************************************************************/\r
-u_int32_t VIP_array_get_allocated_size(VIP_array_p_t VIP_array)\r
-{\r
- if (VIP_array == NULL) return VIP_EINVAL_HNDL;\r
- return VIP_array->size_allocated;\r
-}\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_get_num_of_objects\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - table\r
- *\r
- * Returns:\r
- * number of objects in the array\r
- *\r
- * Description:\r
- * Get number of objects\r
- *\r
- ********************************************************************************/\r
-u_int32_t VIP_array_get_num_of_objects(VIP_array_p_t VIP_array)\r
-{\r
- if (VIP_array == NULL) return VIP_EINVAL_HNDL;\r
- return VIP_array->size;\r
-}\r
-\r
-/********************************************************************************\r
- * Functions: VIP_array_get_first/next_handle\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - Go over this table \r
- * hdl (OUT) - if non zero, returns the next valid handle here\r
- *\r
- * Returns:\r
- * VIP_OK - this code was returned for all objects\r
- * VIP_EINVAL_HNDL: no more valid handles in this array\r
- *\r
- * Description:\r
- * These can be used to iterate over the array, and get all valid\r
- * handles. Initialise handle with first_handle, then call next.\r
- * VIP_EINVAL_HNDL is returned when there are no more handles.\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_get_first_handle(VIP_array_p_t VIP_array, \r
- VIP_array_handle_t* hdl,VIP_array_obj_t* obj)\r
-{\r
- VIP_array_handle_t i;\r
- register VIP_array_internal_obj_t *itl_obj_p = NULL;\r
- \r
- if (VIP_array == NULL) return VIP_EINVAL_HNDL;\r
- MOSAL_spinlock_dpc_lock(&(VIP_array->array_lock));\r
-\r
- for (i=0;i<VIP_array->watermark;++i) {\r
- itl_obj_p = GET_OBJ_BY_HNDL(VIP_array, i);\r
- if (itl_obj_p == NULL || IS_INVALID_OBJ(itl_obj_p))\r
- continue;\r
- if (hdl) *hdl=i;\r
- if (obj) *obj=(VIP_array_obj_t)(itl_obj_p->array_obj);\r
- MOSAL_spinlock_unlock(&(VIP_array->array_lock));\r
- return VIP_OK;\r
- }\r
- MOSAL_spinlock_unlock(&(VIP_array->array_lock));\r
- return VIP_EINVAL_HNDL;\r
-}\r
-\r
-VIP_common_ret_t VIP_array_get_next_handle(VIP_array_p_t VIP_array, \r
- VIP_array_handle_t* hdl, VIP_array_obj_t* obj)\r
-{\r
- VIP_array_handle_t i;\r
- VIP_array_internal_obj_t *itl_obj_p = NULL;\r
- \r
- if (VIP_array == NULL) return VIP_EINVAL_HNDL;\r
- if (!hdl) return VIP_EINVAL_HNDL;\r
-\r
- MOSAL_spinlock_dpc_lock(&(VIP_array->array_lock));\r
- \r
- for (i=*hdl+1;i<VIP_array->watermark;++i) {\r
- itl_obj_p = GET_OBJ_BY_HNDL(VIP_array, i);\r
- if (itl_obj_p == NULL || IS_INVALID_OBJ(itl_obj_p))\r
- continue;\r
- *hdl=i;\r
- if (obj) *obj=(VIP_array_obj_t)(itl_obj_p->array_obj);\r
- MOSAL_spinlock_unlock(&(VIP_array->array_lock));\r
- return VIP_OK;\r
- }\r
- MOSAL_spinlock_unlock(&(VIP_array->array_lock));\r
- return VIP_EINVAL_HNDL;\r
-}\r
-\r
-VIP_common_ret_t VIP_array_get_first_handle_hold(VIP_array_p_t VIP_array, \r
- VIP_array_handle_t* hdl,VIP_array_obj_t* obj, MT_bool busy_only)\r
-{\r
- VIP_common_ret_t rc= VIP_OK;\r
- VIP_array_handle_t i;\r
- register VIP_array_internal_obj_t *itl_obj_p = NULL;\r
- \r
- if (VIP_array == NULL) return VIP_EINVAL_HNDL;\r
- if (!hdl) return VIP_EINVAL_HNDL;\r
- MOSAL_spinlock_dpc_lock(&(VIP_array->array_lock));\r
-\r
- for (i=0;i<VIP_array->watermark;++i) {\r
- itl_obj_p = GET_OBJ_BY_HNDL(VIP_array, i);\r
- if ((itl_obj_p == NULL) || IS_NOT_BUSY_OBJ(itl_obj_p, busy_only)) {continue;}\r
- if (itl_obj_p->ref_count == INVALID_REF_VAL-1) { /* protect from overflow */\r
- rc= VIP_EAGAIN; /* ref. cnt. is at max for this item */\r
- } else {\r
- (itl_obj_p->ref_count)++;\r
- }\r
- if (hdl) *hdl=i;\r
- if (obj) *obj=(VIP_array_obj_t)(itl_obj_p->array_obj);\r
- MOSAL_spinlock_unlock(&(VIP_array->array_lock));\r
- return rc;\r
- }\r
- MOSAL_spinlock_unlock(&(VIP_array->array_lock));\r
- return VIP_EINVAL_HNDL;\r
-}\r
-\r
-VIP_common_ret_t VIP_array_get_next_handle_hold(VIP_array_p_t VIP_array, \r
- VIP_array_handle_t* hdl, VIP_array_obj_t* obj, MT_bool busy_only)\r
-{\r
- VIP_common_ret_t rc= VIP_OK;\r
- VIP_array_handle_t i;\r
- register VIP_array_internal_obj_t *itl_obj_p = NULL;\r
- \r
- if (VIP_array == NULL) return VIP_EINVAL_HNDL;\r
- if (!hdl) return VIP_EINVAL_HNDL;\r
-\r
- MOSAL_spinlock_dpc_lock(&(VIP_array->array_lock));\r
- for (i=*hdl+1;i<VIP_array->watermark;++i) {\r
- itl_obj_p = GET_OBJ_BY_HNDL(VIP_array, i);\r
- if ((itl_obj_p == NULL) || IS_NOT_BUSY_OBJ(itl_obj_p, busy_only)) {continue;}\r
- if (itl_obj_p->ref_count == INVALID_REF_VAL-1) { /* protect from overflow */\r
- rc= VIP_EAGAIN; /* ref. cnt. is at max for this item */\r
- } else {\r
- (itl_obj_p->ref_count)++;\r
- }\r
- *hdl=i;\r
- if (obj) *obj=(VIP_array_obj_t)(itl_obj_p->array_obj);\r
- MOSAL_spinlock_unlock(&(VIP_array->array_lock));\r
- return rc;\r
- }\r
- MOSAL_spinlock_unlock(&(VIP_array->array_lock));\r
- return VIP_EINVAL_HNDL;\r
-}\r
-\r
-u_int32_t VIP_array_get_max_size(VIP_array_p_t VIP_array)\r
-{\r
- if (VIP_array == NULL) return VIP_EINVAL_HNDL;\r
- return VIP_array->max_size;\r
-}\r
-\r
-u_int32_t VIP_array_get_watermark(VIP_array_p_t VIP_array)\r
-{\r
- if (VIP_array == NULL) return VIP_EINVAL_HNDL;\r
- return VIP_array->watermark;\r
-}\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
- \r
-\r
-#ifndef VIP_COMMON_VIP_ARRAY_H\r
-#define VIP_COMMON_VIP_ARRAY_H\r
-\r
-#include <mtl_common.h>\r
-#include "vip_common.h"\r
-\r
-typedef u_int32_t VIP_array_handle_t;\r
-typedef void* VIP_array_obj_t;\r
-\r
-struct VIP_array_t;\r
-typedef struct VIP_array_t* VIP_array_p_t;\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_create_maxsize\r
- *\r
- * Arguments:\r
- * \r
- * size (IN) - initial size. Must be multiple of 8.\r
- * maxsize (IN) - max number of elements that the array will hold\r
- *\r
- * VIP_array_p (OUT) - Return new VIP_array object here\r
- * Set to NULL in case of an error\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_AGAIN: Not enough resources\r
- *\r
- * Description:\r
- * Create a new VIP_array table\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_create_maxsize(u_int32_t size, u_int32_t maxsize, VIP_array_p_t* VIP_array_p);\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_create\r
- *\r
- * Arguments:\r
- * \r
- * size (IN) - initial size. Must be multiple of 8.\r
- *\r
- * VIP_array_p (OUT) - Return new VIP_array object here\r
- * Set to NULL in case of an error\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_AGAIN: Not enough resources\r
- *\r
- * Description:\r
- * Create a new VIP_array table\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_create(u_int32_t size, VIP_array_p_t* VIP_array_p);\r
-\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_destroy\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - Object to destroy\r
- * free_objects_fun (IN) - If non zero, call this function\r
- * for each object in the array (can be used\r
- * e.g. to deallocate memory).\r
- * Even if zero, the array is still deallocated.\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- *\r
- * Description:\r
- * cleanup resources for a VIP_array table\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_destroy(VIP_array_p_t VIP_array, \r
- VIP_allocator_free_t free_objects_fun);\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_insert\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - Insert in this table\r
- * obj (IN) - object to insert\r
- * handle_p (OUT) - handle for this object\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EAGAIN: not enough resources\r
- *\r
- * Description:\r
- * Inset given object to array\r
- * Return the handle associated with this object.\r
- * Note: No check is done that the object is not already\r
- * in the array.\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_insert(VIP_array_p_t VIP_array, VIP_array_obj_t obj,\r
- VIP_array_handle_t* handle_p );\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_insert2hndl\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - Insert in this table\r
- * obj (IN) - object to insert\r
- * hndl (IN) - Requested handle for this object\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EBUSY: Given handle is already in use\r
- * VIP_EAGAIN: not enough resources\r
- *\r
- * Description:\r
- * Associate this object with given handle in the array (if handle not already used).\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_insert2hndl(VIP_array_p_t VIP_array, VIP_array_obj_t obj,\r
- VIP_array_handle_t hndl );\r
-\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_insert_ptr\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - Insert in this table\r
- * handle_p (OUT) - handle for this object\r
- * obj (OUT) - pointer to new object\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EAGAIN: not enough resources\r
- *\r
- * Description:\r
- * Associate a new object with this handle.\r
- * This is like VIP_array_insert, but it returns\r
- * a pointer into the array through which the pointer \r
- * to the object can be set later.\r
- *\r
- * NOTE: the pointer returned is only valid until the next\r
- * call to insert/erase! After this you must use the handle\r
- * to access the value.\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_insert_ptr(VIP_array_p_t VIP_array, \r
- VIP_array_handle_t* handle_p , VIP_array_obj_t** obj);\r
-\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_erase\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - this table\r
- * handle (IN) - remove object by this handle\r
- * obj (OUT) - if non zero, returns the object by this handle here\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EINVAL_HNDL: handle is not in the VIP_array\r
- * VIP_EBUSY\r
- *\r
- * Description:\r
- * Remove the object associated with this handle\r
- * Note: fails if handle is not already in the VIP_array\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_erase(VIP_array_p_t a, VIP_array_handle_t handle, \r
- VIP_array_obj_t* obj_p );\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_find_release_erase\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - this table\r
- * handle (IN) - remove object by this handle\r
- * obj (OUT) - if non zero, returns the object by this handle here\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EINVAL_HNDL: handle is not in the VIP_array, or only_this_obj don't match object at handle\r
- * VIP_EBUSY: Handle is still busy (ref_cnt > 0 , after dec.). ref_cnt is updated anyway.\r
- *\r
- * Description:\r
- * This function is a combination of VIP_array_find_release and VIP_array_erase.\r
- * The function atomically decrements the handle's reference count and check if it reached 0.\r
- * Only if the ref_cnt is 0, the object is erased. Otherwise, VIP_EBUSY is returned.\r
- * Note: The reference count is decrement by 1 even on VIP_EBUSY error.\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_find_release_erase(VIP_array_p_t a, VIP_array_handle_t handle, \r
- VIP_array_obj_t* obj_p );\r
-\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_erase_prepare\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - Insert in this table\r
- * handle (IN) - remove object by this handle\r
- * obj (OUT) - if non zero, returns the object by this handle here\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EINVAL_HNDL: handle is not in the VIP_array\r
- * VIP_EBUSY: Handle's reference count > 0\r
- *\r
- * Description:\r
- * invalidate the object in the array, not yet removing the object associated with this handle\r
- * see: VIP_array_erase_done , VIP_array_erase_undo\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_erase_prepare(VIP_array_p_t VIP_array, VIP_array_handle_t handle, \r
- VIP_array_obj_t* obj );\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_find_release_erase_prepare\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - this table\r
- * handle (IN) - remove object by this handle\r
- * obj (OUT) - if non zero, returns the object by this handle here\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EINVAL_HNDL: handle is not in the VIP_array, or only_this_obj don't match object at handle\r
- * VIP_EBUSY: Handle is still busy (ref_cnt > 0 , after dec.). ref_cnt is updated anyway.\r
- *\r
- * Description:\r
- * This function is a combination of VIP_array_find_release and VIP_array_erase_prepare.\r
- * The function atomically decrements the handle's reference count and check if it reached 0.\r
- * Only if the ref_cnt is 0, the object is erased (prep.). Otherwise, VIP_EBUSY is returned.\r
- * Note: The reference count is decrement by 1 even on VIP_EBUSY error.\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_find_release_erase_prepare(VIP_array_p_t a, VIP_array_handle_t handle, \r
- VIP_array_obj_t* obj_p );\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_erase_undo\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - Insert in this table\r
- * handle (IN) - object by this handle\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EINVAL_HNDL: handle is not in the VIP_array or not was "erase prepare".\r
- *\r
- * Description:\r
- * revalidates the object of this handle, undo the erasing operation\r
- * see: VIP_array_erase_prepare\r
- * \r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_erase_undo(VIP_array_p_t VIP_array, VIP_array_handle_t handl);\r
-\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_erase_done\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - Insert in this table\r
- * handle (IN) - remove object by this handle\r
- * obj (OUT) - if non zero, returns the object by this handle here\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EINVAL_HNDL: handle is not in the VIP_array or not was "erase prepare".\r
- *\r
- * Description:\r
- * removes the object associated with this handle\r
- * see: VIP_array_erase_prepare\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_erase_done(VIP_array_p_t a, VIP_array_handle_t handle, VIP_array_obj_t *obj);\r
-\r
-\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_find\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - Insert in this table\r
- * handle (IN) - get object by this handle\r
- * obj (OUT) - if non zero, returns the object by this handle here\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EINVAL_HNDL: handle is not in the VIP_array\r
- *\r
- * Description:\r
- * Find the object associated with this handle\r
- * Note: fails if handle is illegal in the VIP_array\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_find(VIP_array_p_t VIP_array, VIP_array_handle_t handle,\r
- VIP_array_obj_t* obj );\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_find_hold\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - Insert in this table\r
- * handle (IN) - get object by this handle\r
- * obj (OUT) - if non zero, returns the object by this handle here\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EINVAL_HNDL: handle is not in the VIP_array\r
- *\r
- * Description:\r
- * Same as VIP_array_find, but also updates object's reference count.\r
- * VIP_array_erase will fail if reference count > 0 .\r
- * Handle must be released with VIP_array_find_release\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_find_hold(VIP_array_p_t VIP_array, VIP_array_handle_t handle,\r
- VIP_array_obj_t* obj );\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_find_release\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - Insert in this table\r
- * handle (IN) - remove object by this handle\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EINVAL_HNDL: handle is not in the VIP_array\r
- *\r
- * Description:\r
- * Decrement handle's reference count.\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_find_release(VIP_array_p_t VIP_array, VIP_array_handle_t handle);\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_get_num_of_objects\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - table\r
- *\r
- * Returns:\r
- * number of objects in the array\r
- *\r
- * Description:\r
- * Get number of objects\r
- *\r
- ********************************************************************************/\r
-u_int32_t VIP_array_get_num_of_objects(VIP_array_p_t VIP_array);\r
-\r
-/********************************************************************************\r
- * Function: VIP_array_get_allocated_size\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - table\r
- *\r
- * Returns:\r
- * current allocated size of the array\r
- *\r
- * Description:\r
- * allocated size of the arrays\r
- *\r
- ********************************************************************************/\r
-u_int32_t VIP_array_get_allocated_size(VIP_array_p_t VIP_array);\r
-u_int32_t VIP_array_get_max_size(VIP_array_p_t VIP_array);\r
-u_int32_t VIP_array_get_watermark(VIP_array_p_t VIP_array);\r
-\r
-/********************************************************************************\r
- * Functions: VIP_array_get_first/next_handle\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - Go over this table \r
- * hdl (OUT) - if non zero, returns the next valid handle here\r
- * obj (OUT) - if non zero, returns the object of this handle \r
- *\r
- * Returns:\r
- * VIP_OK - this code was returned for all objects\r
- * VIP_EINVAL_HNDL: no more valid handles in this array\r
- *\r
- * Description:\r
- * These can be used to iterate over the array, and get all valid\r
- * handles. Initialise handle with get_first, then call get_next.\r
- * VIP_EINVAL_HNDL is returned when there are no more handles.\r
- * Usage example:\r
- * VIP_array_handle_t hdl;\r
- * for(ret=VIP_array_get_first_handle(VIP_array, &hdl, NULL);\r
- * ret == VIP_OK; ret=VIP_array_get_next_handle(VIP_array,&hdl, NULL)) {\r
- * }\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_get_first_handle(VIP_array_p_t VIP_array, \r
- VIP_array_handle_t* hdl, VIP_array_obj_t* obj);\r
-\r
-VIP_common_ret_t VIP_array_get_next_handle(VIP_array_p_t VIP_array, \r
- VIP_array_handle_t* hdl, VIP_array_obj_t* obj );\r
-\r
-/********************************************************************************\r
- * Functions: VIP_array_get_first_handle_hold/next_handle_hold\r
- *\r
- * Arguments:\r
- * VIP_array (IN) - Go over this table \r
- * hdl (OUT) - returns the next valid busy handle here (MUST be non-zero)\r
- * obj (OUT) - if non zero, returns the object of this handle \r
- * busy_only (IN) - if TRUE, only returns busy valid items in the scan\r
- *\r
- * Returns:\r
- * VIP_OK - this code was returned for all objects\r
- * VIP_EAGAIN: reference count already at max. Info returned, but user must not release\r
- * when done with item\r
- * VIP_EINVAL_HNDL: no more valid/busy handles in this array\r
- *\r
- * Description:\r
- * These can be used to iterate over the array, and get all valid/busy\r
- * handles, updating ref count for items returned. \r
- * Initialise handle with get_first_hold, then call get_next_hold.\r
- * VIP_EINVAL_HNDL is returned when there are no more handles.\r
- * When done with a given handle, user must call VIP_array_find_release on the returned\r
- * handle to decrement its reference count.\r
- *\r
- * Usage example (for getting and holding all valid items):\r
- * VIP_array_handle_t hdl;\r
- * for(ret=VIP_array_get_next_handle_hold(VIP_array, &hdl, NULL, FALSE);\r
- * ret == VIP_OK; ret=VIP_array_get_next_busy_handle(VIP_array,&hdl, NULL, FALSE)) {\r
- * }\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t VIP_array_get_first_handle_hold(VIP_array_p_t VIP_array, \r
- VIP_array_handle_t* hdl, VIP_array_obj_t* obj, MT_bool busy_only);\r
-\r
-VIP_common_ret_t VIP_array_get_next_handle_hold(VIP_array_p_t VIP_array, \r
- VIP_array_handle_t* hdl, VIP_array_obj_t* obj, MT_bool busy_only );\r
-/********************************************************************************\r
- * Macro: VIP_ARRAY_FOREACH\r
- *\r
- * Arguments:\r
- * VIP_array_p_t VIP_array (IN) - Go over this table \r
- * VIP_common_ret_t ret (OUT) - variable (lvalue) to hold the current return code\r
- * VIP_array_handle_t hdl (OUT) - variable (lvalue) to hold current object handle\r
- * VIP_array_obj_t* obj_p (OUT) - if non zero, returns the object of this handle \r
- *\r
- * Returns:\r
- *\r
- * Description:\r
- * This macro can be used to iterate over the array.\r
- * Only valid handles are returned.\r
- * If you are not interested in objects but only in handles pass\r
- * NULL instead of obj_p.\r
- *\r
- * Usage example (erase all object from the array, and free them):\r
- *\r
- * VIP_array_handle_t hdl;\r
- * VIP_common_ret_t ret;\r
- * VIP_array_obj_t obj;\r
- *\r
- * VIP_ARRAY_FOREACH(VIP_array, ret, hdl, &obj) {\r
- * VIP_array_erase(VIP_array, hdl, NULL);\r
- * FREE(obj);\r
- * }\r
- *\r
- ********************************************************************************/\r
-#define VIP_ARRAY_FOREACH(VIP_array, ret, hdl, obj_p) \\r
- for(ret=VIP_array_get_first_handle(VIP_array, &hdl, obj_p);\\r
- ret == VIP_OK; ret=VIP_array_get_next_handle(VIP_array,&hdl, obj_p)) \r
-\r
-/********************************************************************************\r
- * Macro: VIP_ARRAY_FOREACH_HOLD\r
- *\r
- * Arguments:\r
- * VIP_array_p_t VIP_array (IN) - Go over this table \r
- * VIP_common_ret_t ret (OUT) - variable (lvalue) to hold the current return code\r
- * VIP_array_handle_t hdl (OUT) - variable (lvalue) to hold current object handle\r
- * VIP_array_obj_t* obj_p (OUT) - if non zero, returns the object of this handle \r
- * busy_only -- if TRUE, return only items already busy (i.e., nonzero ref count)\r
- *\r
- * Returns:\r
- *\r
- * Description:\r
- * This macro can be used to iterate over the array, holding each item returned.\r
- * Only valid handles are returned. If the busy_only flag is TRUE, the item must\r
- * already have a non-zero reference count to be returned.\r
- * If you are not interested in objects but only in handles pass\r
- * NULL instead of obj_p.\r
- *\r
- * When you are done with a returned handle, you MUST call VIP_array_find_release() on\r
- * that handle (or the item will not be deletable).\r
- *\r
- * Usage example (erase all object from the array, and free them):\r
- *\r
- * VIP_array_handle_t hdl;\r
- * VIP_common_ret_t ret;\r
- * VIP_array_obj_t obj;\r
- *\r
- * VIP_ARRAY_FOREACH_HOLD(VIP_array, ret, hdl, &obj, TRUE) {\r
- * ... do something with returned object ...\r
- * if (ret == VIP_OK) VIP_array_find_release(VIP_array, hdl);\r
- * }\r
- *\r
- ********************************************************************************/\r
-#define VIP_ARRAY_FOREACH_HOLD(VIP_array, ret, hdl, obj_p, busy_only) \\r
- for(ret=VIP_array_get_first_handle_hold(VIP_array, &hdl, obj_p, busy_only);\\r
- ((ret == VIP_OK) || (ret == VIP_EAGAIN)); ret=VIP_array_get_next_handle_hold(VIP_array,&hdl, obj_p, busy_only)) \r
-\r
-#ifdef __cplusplus\r
- }\r
-#endif\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "vip_cirq.h"\r
-\r
-void VIP_cirq_stats_print(VIP_cirq_t *cirq_p)\r
-{\r
- MTL_DEBUG4("%s: cirq 0x%p stats:\n", __func__, cirq_p->queue);\r
- MTL_DEBUG4("%s: queue size: %d\n", __func__, cirq_p->q_size);\r
- MTL_DEBUG4("%s: elt size: %d\n", __func__, cirq_p->element_size);\r
- MTL_DEBUG4("%s: producer: %d\n", __func__, cirq_p->producer);\r
- MTL_DEBUG4("%s: consumer: %d\n", __func__, cirq_p->consumer);\r
- MTL_DEBUG4("%s: full flag: %s\n", __func__, (cirq_p->full == TRUE ? "TRUE" : "FALSE"));\r
-}\r
-\r
-static int VIP_cirq_empty_no_mtx(VIP_cirq_t *cirq_p)\r
-{\r
- int retval = FALSE;\r
- if(cirq_p->consumer==cirq_p->producer && !(cirq_p->full))\r
- retval = TRUE;\r
- return retval;\r
-}\r
- \r
-\r
-int VIP_cirq_create(int q_size, int element_size, VIP_cirq_t **cirq_p)\r
-{\r
- VIP_cirq_t *new_cirq;\r
-\r
- MTL_DEBUG4(MT_FLFMT("VIP_cirq_create: queue size = %d, elt size = %d"),q_size,element_size);\r
- new_cirq = (VIP_cirq_t *)MALLOC(sizeof(VIP_cirq_t));\r
- if (new_cirq == NULL) {\r
- MTL_ERROR1(MT_FLFMT("VIP_cirq_create: MALLOC failure"));\r
- return -1;\r
- }\r
-\r
- new_cirq->queue = (void*)VMALLOC( element_size * q_size);\r
- if (new_cirq == NULL) {\r
- MTL_ERROR1(MT_FLFMT("VIP_cirq_create: VMALLOC failure"));\r
- FREE(new_cirq);\r
- return -1;\r
- }\r
- new_cirq->full = FALSE;\r
- new_cirq->producer = new_cirq->consumer = 0;\r
- new_cirq->q_size = q_size;\r
- new_cirq->element_size = element_size;\r
- MOSAL_mutex_init(&(new_cirq->cirq_access_mtx));\r
- *cirq_p = new_cirq;\r
- return 0;\r
-}\r
-\r
-\r
-int VIP_cirq_add(VIP_cirq_t *cirq_p, void * elt)\r
-{\r
- int retval = 0;\r
- MTL_DEBUG4(MT_FLFMT("VIP_cirq_add, cirq=0x%p"), cirq_p);\r
- MOSAL_mutex_acq(&(cirq_p->cirq_access_mtx), TRUE);\r
- \r
- if (cirq_p->full == TRUE || elt == NULL) {\r
- MTL_ERROR1(MT_FLFMT("VIP_cirq_add: queue 0x%p full or element to add (0x%p)is null"), cirq_p->queue, elt);\r
- retval = -1;\r
- } else { \r
- /* insert at the producer end */\r
- memcpy(((u_int8_t *)(cirq_p->queue)) + (cirq_p->producer * cirq_p->element_size), elt, cirq_p->element_size);\r
- (cirq_p->producer)++;\r
- if(cirq_p->producer==cirq_p->q_size)\r
- cirq_p->producer=0;\r
- if(cirq_p->producer==cirq_p->consumer)\r
- {\r
- cirq_p->full=1;\r
- }\r
- }\r
- \r
- // VIP_cirq_stats_print(cirq_p); \r
- MOSAL_mutex_rel(&(cirq_p->cirq_access_mtx));\r
- return (retval);\r
-}\r
-\r
-int VIP_cirq_peek(VIP_cirq_t *cirq_p, void * elt)\r
-{\r
- int retval = 0;\r
- MTL_DEBUG4(MT_FLFMT("VIP_cirq_peek"));\r
- MOSAL_mutex_acq(&(cirq_p->cirq_access_mtx), TRUE);\r
- \r
- /* check that elt is not null and queue not empty */\r
- if (VIP_cirq_empty_no_mtx(cirq_p) || elt == NULL) {\r
- MTL_DEBUG1(MT_FLFMT("VIP_cirq_peek: queue 0x%p is empty or element (0x%p) is NULL"), cirq_p->queue,elt);\r
- retval = -1;\r
- } else {\r
- memcpy(elt, ((u_int8_t *)(cirq_p->queue)) + (cirq_p->consumer * cirq_p->element_size), cirq_p->element_size);\r
- }\r
- \r
- MOSAL_mutex_rel(&(cirq_p->cirq_access_mtx));\r
- return retval;\r
-}\r
-\r
-int VIP_cirq_peek_ptr(VIP_cirq_t *cirq_p, void **elt)\r
-{\r
- int retval = 0;\r
- MTL_DEBUG4(MT_FLFMT("VIP_cirq_peek_ptr"));\r
- MOSAL_mutex_acq(&(cirq_p->cirq_access_mtx), TRUE);\r
- \r
- /* check that *elt is not null and queue not empty */\r
- if (VIP_cirq_empty_no_mtx(cirq_p) || elt == NULL) {\r
- MTL_DEBUG1(MT_FLFMT("VIP_cirq_peek_ptr: queue 0x%p is empty or element (0x%p) is NULL"), cirq_p->queue, elt);\r
- retval = -1;\r
- } else {\r
- *elt = ((u_int8_t *)(cirq_p->queue)) + (cirq_p->consumer * cirq_p->element_size);\r
- }\r
- \r
- MOSAL_mutex_rel(&(cirq_p->cirq_access_mtx));\r
- return retval;\r
-}\r
-\r
-\r
-int VIP_cirq_remove(VIP_cirq_t *cirq_p, void * elt)\r
-{\r
- int retval = 0;\r
- \r
-\r
- MTL_DEBUG4(MT_FLFMT("VIP_cirq_remove, cirq=0x%p"), cirq_p);\r
- MOSAL_mutex_acq(&(cirq_p->cirq_access_mtx), TRUE);\r
- \r
- if(VIP_cirq_empty_no_mtx(cirq_p)) {\r
- MTL_DEBUG1(MT_FLFMT("VIP_cirq_remove: queue 0x%p is empty"), cirq_p->queue);\r
- retval = -1;\r
- } else {\r
- /* remove(read) at the consumer end */\r
- if(elt != NULL){\r
- memcpy(elt, ((u_int8_t *)(cirq_p->queue)) + (cirq_p->consumer * cirq_p->element_size),\r
- cirq_p->element_size);\r
- }\r
- (cirq_p->consumer)++;\r
- cirq_p->full=0;\r
- if(cirq_p->consumer==cirq_p->q_size)\r
- cirq_p->consumer=0;\r
- if(cirq_p->consumer==cirq_p->producer) {\r
- MTL_DEBUG4(MT_FLFMT("VIP_cirq_add: queue 0x%p is empty"), cirq_p->queue);\r
- cirq_p->consumer=cirq_p->producer=0;\r
- cirq_p->full=0;\r
- }\r
- }\r
- //VIP_cirq_stats_print(cirq_p); \r
- MOSAL_mutex_rel(&(cirq_p->cirq_access_mtx));\r
- return(retval); \r
-}\r
-\r
-int VIP_cirq_empty(VIP_cirq_t *cirq_p)\r
-{\r
- int retval = FALSE;\r
- MOSAL_mutex_acq(&(cirq_p->cirq_access_mtx), TRUE);\r
- if(cirq_p->consumer==cirq_p->producer && !(cirq_p->full))\r
- retval = TRUE;\r
- MOSAL_mutex_rel(&(cirq_p->cirq_access_mtx));\r
- return retval;\r
-}\r
- \r
-\r
-int VIP_cirq_destroy(VIP_cirq_t *cirq_p)\r
-{\r
- call_result_t mt_rc;\r
-\r
- MTL_DEBUG4(MT_FLFMT("VIP_cirq_destroy, cirq=0x%p"), cirq_p);\r
- MOSAL_mutex_acq(&(cirq_p->cirq_access_mtx), TRUE);\r
- VFREE(cirq_p->queue);\r
- MOSAL_mutex_rel(&(cirq_p->cirq_access_mtx));\r
- mt_rc = MOSAL_mutex_free(&(cirq_p->cirq_access_mtx));\r
- if (mt_rc != MT_OK) {\r
- MTL_ERROR2(MT_FLFMT("Failed MOSAL_mutex_free (%s)"),mtl_strerror_sym(mt_rc));\r
- }\r
- FREE(cirq_p);\r
- return(0);\r
-}\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef VIP_COMMON_VIP_CIRQ_H\r
-#define VIP_COMMON_VIP_CIRQ_H\r
-\r
-\r
-#include <vapi_types.h>\r
-#include <mosal.h>\r
-\r
-typedef struct VIP_cirq_st {\r
- int consumer;\r
- int producer;\r
- int q_size;\r
- MT_bool full;\r
- void* queue;\r
- int element_size;\r
- MOSAL_mutex_t cirq_access_mtx;\r
-} VIP_cirq_t;\r
-\r
-int VIP_cirq_create(int q_size, int element_size, VIP_cirq_t **cirq);\r
-int VIP_cirq_remove(VIP_cirq_t *cirq_p, void * elt);\r
-int VIP_cirq_add(VIP_cirq_t *cirq_p, void * elt);\r
-void VIP_cirq_stats_print(VIP_cirq_t *cirq_p);\r
-int VIP_cirq_peek(VIP_cirq_t *cirq_p, void *elt);\r
-int VIP_cirq_peek_ptr(VIP_cirq_t *cirq_p, void **elt);\r
-int VIP_cirq_destroy(VIP_cirq_t *cirq_p);\r
-int VIP_cirq_empty(VIP_cirq_t *cirq_p);\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_VIP_COMMON_H\r
-#define H_VIP_COMMON_H\r
-\r
-#include <mtl_common.h>\r
-#include <vapi_types.h>\r
-\r
-enum VIP_common_ret {\r
- /* Remap VAPI return codes */\r
-\r
- /* Non error return values */\r
- VIP_OK = VAPI_OK,\r
-\r
- /* General errors */\r
- VIP_EGEN = VAPI_EGEN, /* general error for entire stack */\r
- VIP_EAGAIN = VAPI_EAGAIN, /* Not enough resources (try again later...) */\r
- VIP_EBUSY = VAPI_EBUSY, /* Resource is in use */\r
- VIP_ETIMEDOUT = VAPI_ETIMEOUT, /* Operation timedout */\r
- VIP_EINTR = VAPI_EINTR, /* Interrupted blocking function (operation not completed) */\r
- VIP_EFATAL = VAPI_EFATAL, /* catastrophic error */\r
- VIP_ENOMEM = VAPI_ENOMEM, /* Invalid address of exhausted physical memory quota */\r
- VIP_EPERM = VAPI_EPERM, /* Not enough permissions */\r
- VIP_ENOSYS = VAPI_ENOSYS,/* Operation/option not supported */\r
- VIP_ESYSCALL = VAPI_ESYSCALL, /* Error in underlying O/S call */\r
- VIP_EINVAL_PARAM = VAPI_EINVAL_PARAM, /* invalid parameter*/\r
- \r
- /*******************************************************/\r
- /* VIP specific errors */\r
-\r
- VIP_COMMON_ERROR_MIN = VAPI_ERROR_MAX, /* Dummy error code: put this VIP error code first */\r
-\r
- /* General errors */\r
- VIP_EINVAL_HNDL, /* Invalid (no such) handle */\r
-\r
- VIP_COMMON_ERROR_MAX /* Dummy max error code : put all error codes before this */\r
-};\r
-\r
-typedef int32_t VIP_common_ret_t;\r
-\r
-/* Memory mgmt functions */\r
-\r
-/********************************************************************************\r
- * Function type: VIP_allocator_malloc_t (not used for now)\r
- *\r
- * Arguments:\r
- * size (IN) - allocate this number of bytes on the heap\r
- *\r
- * Returns:\r
- * pointer to allocated memory.\r
- * 0 if resources were unavailable\r
- *\r
- * Description:\r
- * allocate given amount of bytes memory\r
- *\r
- ********************************************************************************/\r
-typedef void* (VIP_allocator_malloc_t)(size_t size);\r
-/********************************************************************************\r
- * Function type: VIP_allocator_free_t\r
- *\r
- * Arguments:\r
- * void* (IN) - deallocate memory at this location\r
- *\r
- * Returns:\r
- * void\r
- *\r
- * Description:\r
- * deallocate memory at a given location\r
- *\r
- ********************************************************************************/\r
-typedef void (*VIP_allocator_free_t)(void *);\r
-\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
- #include <mosal.h>\r
- #include <vip_delay_unlock_priv.h>\r
- \r
- int VIP_delay_unlock_create(VIP_delay_unlock_t * delay_unlock_obj_p)\r
- {\r
- VIP_delay_unlock_t new_obj = NULL;\r
-\r
- new_obj = (VIP_delay_unlock_t )MALLOC(sizeof(struct VIP_delay_unlock_st));\r
- if (new_obj == NULL) {\r
- * delay_unlock_obj_p = NULL;\r
- /* malloc failure */\r
- return -3;\r
- }\r
- new_obj->list_start = NULL;\r
- new_obj->is_valid = TRUE; /* sets list to valid */\r
- MOSAL_spinlock_init(&new_obj->spl);\r
- *delay_unlock_obj_p = new_obj;\r
- return 0;\r
- }\r
-\r
- int VIP_delay_unlock_insert(VIP_delay_unlock_t delay_unlock_obj,\r
- MOSAL_iobuf_t iobuf) \r
- {\r
-\r
- VIP_delay_unlock_elem_t * new_elt = NULL;\r
- VIP_delay_unlock_elem_t * temp_next = NULL;\r
-\r
- if (delay_unlock_obj == NULL) {\r
- return -1; /* invalid argument */\r
- }\r
-\r
- /* allocate a new stack element */\r
- new_elt = TMALLOC(VIP_delay_unlock_elem_t);\r
- if (new_elt == NULL) {\r
- /* malloc failure */\r
- MTL_ERROR1("%s: MALLOC failure. cannot defer delete of iobuf=0x%p\n",\r
- __func__, (void *) iobuf);\r
- return -3;\r
- }\r
- new_elt->iobuf = iobuf;\r
- MTL_DEBUG1("%s: DEFERRING unlock of iobuf=0x%p \n",\r
- __func__, (void *) iobuf);\r
- MOSAL_spinlock_dpc_lock(&delay_unlock_obj->spl);\r
- if (delay_unlock_obj->is_valid == FALSE) {\r
- /* list has been deleted */\r
- MOSAL_spinlock_unlock(&delay_unlock_obj->spl);\r
- MTL_ERROR1("%s: DEFERRED LIST has been deleted. FAIL deferring delete of iobuf=0x%p\n",\r
- __func__, (void *) iobuf);\r
- FREE(new_elt);\r
- return -2;\r
- }\r
- temp_next = delay_unlock_obj->list_start;\r
- delay_unlock_obj->list_start = new_elt;\r
- new_elt->next = temp_next;\r
- MOSAL_spinlock_unlock(&delay_unlock_obj->spl);\r
- \r
- return 0;\r
- }\r
-\r
- int VIP_delay_unlock_destroy(VIP_delay_unlock_t delay_unlock_obj)\r
- {\r
- VIP_delay_unlock_elem_t * found_elt = NULL;\r
- VIP_delay_unlock_elem_t * next_elt = NULL;\r
-\r
- if (delay_unlock_obj == NULL) {\r
- return -1; /* invalid argument */\r
- }\r
- /* make list invalid */\r
- MOSAL_spinlock_dpc_lock(&delay_unlock_obj->spl);\r
- if (delay_unlock_obj->is_valid == FALSE) {\r
- /* list has been deleted */\r
- MOSAL_spinlock_unlock(&delay_unlock_obj->spl);\r
- return -2;\r
- }\r
- delay_unlock_obj->is_valid = FALSE;\r
- found_elt = delay_unlock_obj->list_start;\r
- MOSAL_spinlock_unlock(&delay_unlock_obj->spl);\r
-\r
- /* need no more spinlocks */\r
- while(found_elt != NULL) {\r
- next_elt = found_elt->next;\r
- MOSAL_iobuf_deregister(found_elt->iobuf);\r
- MTL_DEBUG1("%s: DEFERRED unlock iobuf=0x%p\n", \r
- __func__, found_elt->iobuf );\r
- FREE(found_elt);\r
- found_elt = next_elt;\r
- }\r
- FREE(delay_unlock_obj);\r
-\r
- return 0;\r
- }\r
-\r
-\r
-\r
-\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef VIP_COMMON_VIP_DELAY_UNLOCK_H\r
-#define VIP_COMMON_VIP_DELAY_UNLOCK_H\r
-\r
-\r
-#include <vapi_types.h>\r
-#include <mosal.h>\r
- \r
-\r
-typedef struct VIP_delay_unlock_st * VIP_delay_unlock_t;\r
-\r
-\r
-int VIP_delay_unlock_create(VIP_delay_unlock_t * delay_unlock_obj_p);\r
-\r
-int VIP_delay_unlock_insert(VIP_delay_unlock_t delay_unlock_obj,MOSAL_iobuf_t iobuf);\r
-int VIP_delay_unlock_destroy(VIP_delay_unlock_t delay_unlock_obj);\r
-\r
-\r
-#endif\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef VIP_COMMON_VIP_DELAY_UNLOCK_PRIV_H\r
-#define VIP_COMMON_VIP_DELAY_UNLOCK_PRIV_H\r
-\r
-#include <vapi_types.h>\r
-#include <mosal.h>\r
-#include <vip_delay_unlock.h>\r
- \r
-typedef struct VIP_delay_unlock_elem_st {\r
- MOSAL_iobuf_t iobuf;\r
- struct VIP_delay_unlock_elem_st * next;\r
-} VIP_delay_unlock_elem_t;\r
-\r
- \r
-struct VIP_delay_unlock_st {\r
- struct VIP_delay_unlock_elem_st * list_start;\r
- MT_bool is_valid;\r
- MOSAL_spinlock_t spl;\r
-};\r
- \r
-#endif\r
-\r
-\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include <mtl_types.h>\r
-\r
-#define VIP_HASH_PRIME 0 // 1-> prime number, 0-> power of 2\r
-\r
-#if VIP_HASH_PRIME\r
-static const unsigned long prime_list[] =\r
-{\r
- /*approx 100% table size growth per resize (except for 1st entry)*/\r
- 7ul, 53ul, 97ul, 193ul, 389ul,\r
- 769ul, 1543ul, 3079ul, 6151ul,\r
-\r
- /*approx 20% table size growth per resize */\r
- 12289ul, 14747ul, 17707ul, 21269ul, 25523ul,\r
- 30631ul, 36761ul, 44119ul, 52951ul, 63559ul,\r
- 76283ul, 91541ul, 109859ul, 131837ul, 158209ul,\r
- 189851ul, 227827ul, 273433ul, 328121ul, 393749ul,\r
- 472523ul, 567031ul, 680441ul, 816539ul, 979873ul,\r
- 1175849ul, 1411021ul, 1693249ul, 2031907ul, 2438309ul,\r
- 2925973ul, 3511171ul, 4194301ul, 5056133ul, 6067361ul,\r
- 7280863ul, 8737039ul, 10484471ul, 12581407ul, 15097711ul, 16777213ul,\r
- 18117271ul, 21740729ul, 26088911ul, 31306697ul, 37568051ul,\r
- 45081683ul, 54098059ul, 64917691ul, 77901247ul, 93481541ul,\r
- 112177873ul, 134613491ul, 161536217ul, 193843493ul, 232612217ul,\r
- 279134677ul, 334961647ul, 401953999ul, 482344801ul, 578813771ul,\r
- 694576537ul, 833491849ul, 1000190263ul, 1200228319ul, 1440273997ul,\r
- 1728328807ul, 2073994579ul, 2488793497ul, 2986552201ul, 3583862647ul,\r
- 4294967291ul\r
-};\r
-static const int n_primes = sizeof(prime_list)/sizeof(prime_list[0]);\r
-\r
-static unsigned long mtl_find_prime(unsigned long size) {\r
- int i;\r
- for (i = 0 ; (i != n_primes-1) && (size >= prime_list[i]) ;++i);\r
- return prime_list[i];\r
-}\r
-\r
-#define VIP_HASH_BUCKET(key, num_buckets) ((key) % (num_buckets))\r
-\r
-#else // VIP_HASH_PRIME\r
-\r
-static unsigned long mtl_find_power2(unsigned long size) {\r
- unsigned long p2;\r
- for (p2=8; p2 < 65536 && (size >= p2) ;p2 <<= 1);\r
- return p2;\r
-}\r
-#define VIP_HASH_BUCKET(key, num_buckets) ((key) & ((num_buckets)-1))\r
-\r
-#endif // VIP_HASH_PRIME\r
-\r
-\r
-/************************************************************************/\r
-static inline u_int32_t hash_u64tou32(u_int64_t u64)\r
-{\r
- u_int32_t high = (u_int32_t) (u64 >> 32);\r
- u_int32_t low = (u_int32_t) (u64 & ~(u_int32_t)0);\r
- u_int32_t h = high ^ low;\r
- return h;\r
-} /* hash_u64tou32 */\r
-\r
-\r
-/************************************************************************/\r
-static inline u_int32_t hash_uv4tou32(u_int32_t *uv4)\r
-{\r
- u_int32_t h = uv4[0] ^ uv4[1] ^ uv4[2] ^ uv4[3];\r
- return h;\r
-} /* hash_u64tou32 */\r
-\r
-\r
-#include "vip_hash.h"\r
-#include "vip_hash.ic" /* 1st time, now __VIP_HASH_VARIANT == 0 */\r
-\r
-#include "vip_hashp.h"\r
-#include "vip_hash.ic" /* 2nd time, now __VIP_HASH_VARIANT == 1 */\r
-\r
-#include "vip_hashp2p.h"\r
-#include "vip_hash.ic" /* 3rd time, now __VIP_HASH_VARIANT == 2 */\r
-\r
-#include "vip_hash64p.h"\r
-#include "vip_hash.ic" /* 4th time, now __VIP_HASH_VARIANT == 3 */\r
-\r
-#include "vip_hashv4p.h"\r
-#include "vip_hash.ic" /* 5th time, now __VIP_HASH_VARIANT == 4 */\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#ifndef VIP_COMMON_VIP_HASH_H\r
-#define VIP_COMMON_VIP_HASH_H\r
-\r
-#include <mtl_types.h>\r
-#include "vip_common.h"\r
-#include "vip_array.h"\r
-\r
-typedef VIP_array_handle_t VIP_hash_value_t;\r
-typedef struct VIP_hash_t* VIP_hash_p_t;\r
-\r
-#undef __VIP_HASH_VARIANT\r
-#define __VIP_HASH_VARIANT 0\r
-#include "vip_hash.ih"\r
-\r
-#endif /* VIP_COMMON_VIP_HASH_H */\r
-/*\r
- * Copyright (c) 2005 InfiniCon Systems. All rights reserved.\r
- * Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id:$\r
- */\r
- \r
-\r
-# undef __VIP_HASH_NODE_T \r
-# undef __VIP_HASH_NODE_P_T \r
-# undef __VIP_HASH_TBL_T \r
-# undef __VIP_HASH_FUNC\r
-\r
-#if __VIP_HASH_VARIANT == 0\r
-# define __VIP_HASH_NODE_T VIP_hash_node_t\r
-# define __VIP_HASH_NODE_P_T VIP_hash_node_p_t\r
-# define __VIP_HASH_TBL_T VIP_hash_t\r
-# define __VIP_HASH_FUNC(k) (k)\r
-# undef resize\r
-# define resize32\r
-#elif __VIP_HASH_VARIANT == 1\r
-# define __VIP_HASH_NODE_T VIP_hashp_node_t\r
-# define __VIP_HASH_NODE_P_T VIP_hashp_node_p_t\r
-# define __VIP_HASH_TBL_T VIP_hashp_t\r
-# define __VIP_HASH_FUNC(k) (k)\r
-# undef resize\r
-# define resize resizep\r
-#elif __VIP_HASH_VARIANT == 2\r
-# define __VIP_HASH_NODE_T VIP_hashp2p_node_t\r
-# define __VIP_HASH_NODE_P_T VIP_hashp2p_node_p_t\r
-# define __VIP_HASH_TBL_T VIP_hashp2p_t\r
-# ifdef MT_64BIT\r
-# define __VIP_HASH_FUNC(pkey) hash_u64tou32((u_int64_t) (pkey))\r
-# else\r
-# define __VIP_HASH_FUNC(pkey) ((u_int32_t)(u_intn_t)(pkey))\r
-# endif\r
-# undef resize\r
-# define resize resizep2p\r
-#elif __VIP_HASH_VARIANT == 3\r
-# define __VIP_HASH_NODE_T VIP_hash64p_node_t\r
-# define __VIP_HASH_NODE_P_T VIP_hash64p_node_p_t\r
-# define __VIP_HASH_TBL_T VIP_hash64p_t\r
-# define __VIP_HASH_FUNC(pkey) hash_u64tou32((u_int64_t) (pkey))\r
-# undef resize\r
-# define resize resize64p\r
-#elif __VIP_HASH_VARIANT == 4\r
-# define __VIP_HASH_NODE_T VIP_hashv4p_node_t\r
-# define __VIP_HASH_NODE_P_T VIP_hashv4p_node_p_t\r
-# define __VIP_HASH_TBL_T VIP_hashv4p_t\r
-# define __VIP_HASH_FUNC(pkey) hash_uv4tou32((pkey))\r
-# undef resize\r
-# define resize resizev4p\r
-#else\r
-# error Unsupported __VIP_HASH_VARIANT variant\r
-#endif\r
-\r
-#include <mosal.h>\r
-\r
-typedef struct __VIP_HASH_NODE_T {\r
- __VIP_HASH_KEY_T key;\r
- __VIP_HASH_VAL_T val;\r
- struct __VIP_HASH_NODE_T* next;\r
-} __VIP_HASH_NODE_T;\r
-typedef __VIP_HASH_NODE_T* __VIP_HASH_NODE_P_T;\r
-\r
-\r
-typedef struct __VIP_HASH_TBL_T {\r
- __VIP_HASH_NODE_P_T** nodes_1st_lvl_begin;\r
- u_int32_t size; \r
- u_int32_t buckets;\r
- MT_bool may_grow;\r
- MOSAL_spinlock_t hash_lock;\r
- u_int32_t max_size;\r
- u_int32_t max_buckets;\r
- u_int32_t max_2nd_lvl_blocks;\r
- u_int32_t sec_lvl_buckets_per_blk;\r
- u_int32_t sec_lvl_buckets_per_blk_m_1;\r
- u_int32_t size_2nd_lvl_block;\r
- u_int32_t log2_2nd_lvl_entries_per_blk;\r
- MT_bool resize_in_progress; /* Notify other threads of an ongoing resize */\r
-} __VIP_HASH_TBL_T;\r
-\r
-#define HASH_DEFAULT_MAXSIZE (16777212ul) /* default max size is 16M entries */\r
-#define HASH_LOG_PTR_SIZE ((sizeof(void *) == 8) ? 3 : 2)\r
-#define HASH_LOG_2ND_LVL_BUCKETS_PER_BLOCK (MOSAL_SYS_PAGE_SHIFT + 1 - HASH_LOG_PTR_SIZE)\r
-#define HASH_2ND_LVL_BLOCK_SIZE (2*MOSAL_SYS_PAGE_SIZE)\r
-#define HASH_2ND_LVL_BUCKETS_PER_BLOCK (HASH_2ND_LVL_BLOCK_SIZE / sizeof(__VIP_HASH_NODE_P_T*))\r
-#define HASH_2ND_LVL_ENTRY_SIZE (sizeof(__VIP_HASH_NODE_P_T*))\r
-\r
-#define HASH_CALC_MAX_2ND_LVL_BLOCKS(hash) ((hash->max_buckets + (hash->sec_lvl_buckets_per_blk_m_1)) / (hash->sec_lvl_buckets_per_blk))\r
-#define HASH_CALC_NUM_2ND_LVL_BLOCKS(buckets, hash) ((buckets + (hash->sec_lvl_buckets_per_blk_m_1)) / (hash->sec_lvl_buckets_per_blk))\r
-#define GET_BUCKET_BY_IX(hash, ix) ((__VIP_HASH_NODE_P_T*) &((*(hash->nodes_1st_lvl_begin+((ix) >> hash_tbl->log2_2nd_lvl_entries_per_blk))\\r
- )[(ix) & (hash->sec_lvl_buckets_per_blk_m_1)]))\r
-\r
-\r
-/******************************************************************************/\r
-static call_result_t resize(__VIP_HASH_T hash_tbl, u_int32_t reserve)\r
-{\r
-// if (hash_tbl->buckets < reserve)\r
-// {\r
-// } \r
- u_int32_t blocks_needed = 0, curr_blocks = 0, block_size_to_allocate = 0;\r
- u_int32_t old_last_allocated_blocksize = 0, new_first_allocated_blocksize = 0;\r
- u_int32_t buckets_per_blk = hash_tbl->sec_lvl_buckets_per_blk;\r
- int i,j;\r
- u_int32_t old_buckets = hash_tbl->buckets;\r
- u_int32_t old_bucket_ix;\r
-#if VIP_HASH_PRIME\r
- u_int32_t new_buckets = (u_int32_t) mtl_find_prime((unsigned long) reserve);\r
-#else\r
- u_int32_t new_buckets = (u_int32_t) mtl_find_power2((unsigned long) reserve);\r
-#endif\r
- \r
- if (hash_tbl->buckets >= hash_tbl->max_buckets) {\r
- /* we already have the max number of buckets allocated */\r
- hash_tbl->may_grow = FALSE;\r
- return MT_EAGAIN;\r
- } else if (new_buckets > hash_tbl->max_buckets) {\r
- new_buckets = hash_tbl->max_buckets;\r
- }\r
- /* We may read the values below with no lock since only one thread will enter this\r
- * function at one time (based on resize_in_progress flag), so these value cannot\r
- * be modified at this time (here is the only location for such changes).\r
- */\r
- \r
- /* allocate extension of table. This extension is still invisible to users, because\r
- * hash_tbl->buckets is not modified until after all the allocations succeed */\r
- blocks_needed = HASH_CALC_NUM_2ND_LVL_BLOCKS(new_buckets, hash_tbl);\r
- curr_blocks = HASH_CALC_NUM_2ND_LVL_BLOCKS(hash_tbl->buckets,hash_tbl);\r
- if (blocks_needed > curr_blocks) {\r
- /* Need a larger first level structure */\r
- __VIP_HASH_NODE_P_T** new_1st_level;\r
- __VIP_HASH_NODE_P_T** old_1st_level;\r
- u_int32_t new_1st_lvl_size = sizeof(__VIP_HASH_NODE_P_T**)*(blocks_needed);\r
- new_1st_level = (__VIP_HASH_NODE_P_T**)MALLOC(new_1st_lvl_size);\r
- if (new_1st_level == NULL) {\r
- hash_tbl->may_grow = FALSE;\r
- MTL_ERROR1(MT_FLFMT("%s failed: cannot allocate memory for first level"), __func__ );\r
- return MT_EAGAIN;\r
- }\r
- memset(new_1st_level, 0, new_1st_lvl_size);\r
- MOSAL_spinlock_dpc_lock(&(hash_tbl->hash_lock));\r
- if (hash_tbl->nodes_1st_lvl_begin != NULL) {\r
- memcpy(new_1st_level, hash_tbl->nodes_1st_lvl_begin, sizeof(__VIP_HASH_NODE_P_T**)*(curr_blocks));\r
- old_1st_level = hash_tbl->nodes_1st_lvl_begin;\r
- hash_tbl->nodes_1st_lvl_begin = new_1st_level;\r
- MOSAL_spinlock_unlock(&(hash_tbl->hash_lock));\r
- FREE(old_1st_level);\r
- }else {\r
- hash_tbl->nodes_1st_lvl_begin = new_1st_level;\r
- MOSAL_spinlock_unlock(&(hash_tbl->hash_lock));\r
- }\r
- }\r
- block_size_to_allocate = hash_tbl->size_2nd_lvl_block;\r
-\r
- /* adjust previous last block for new number of buckets. Need spinlock when adjust\r
- * the last second level block in the current table. */\r
- if (curr_blocks > 0) {\r
- __VIP_HASH_NODE_P_T* new_2nd_lvl_block;\r
- __VIP_HASH_NODE_P_T* old_2nd_lvl_block;\r
- old_last_allocated_blocksize =\r
- (hash_tbl->buckets - ((curr_blocks-1)*(hash_tbl->sec_lvl_buckets_per_blk)))*HASH_2ND_LVL_ENTRY_SIZE;\r
- if (curr_blocks == blocks_needed) {\r
- /* just allocate a new short block */\r
- new_first_allocated_blocksize = (new_buckets - \r
- ((blocks_needed-1)*(hash_tbl->sec_lvl_buckets_per_blk))\r
- ) * HASH_2ND_LVL_ENTRY_SIZE;\r
- } else {\r
- new_first_allocated_blocksize = block_size_to_allocate;\r
- }\r
-\r
- new_2nd_lvl_block = (__VIP_HASH_NODE_P_T*)MALLOC(new_first_allocated_blocksize);\r
- if (new_2nd_lvl_block == NULL) {\r
- hash_tbl->may_grow = FALSE;\r
- MTL_ERROR1(MT_FLFMT("%s failed: cannot allocate memory for second level"), __func__ );\r
- return MT_EAGAIN;\r
- }\r
- memset(new_2nd_lvl_block, 0, new_first_allocated_blocksize);\r
- MOSAL_spinlock_dpc_lock(&(hash_tbl->hash_lock));\r
- old_2nd_lvl_block = hash_tbl->nodes_1st_lvl_begin[curr_blocks-1];\r
- memcpy(new_2nd_lvl_block,old_2nd_lvl_block,old_last_allocated_blocksize);\r
- hash_tbl->nodes_1st_lvl_begin[curr_blocks-1] = new_2nd_lvl_block;\r
- MOSAL_spinlock_unlock(&(hash_tbl->hash_lock));\r
- FREE(old_2nd_lvl_block);\r
- }\r
- \r
- for (i = curr_blocks; i < (int) blocks_needed; i++) {\r
- if (i == (int)blocks_needed - 1) {\r
- /* allocate a smaller block for the last 2nd level block */\r
- block_size_to_allocate = (new_buckets - \r
- ((blocks_needed-1)*(hash_tbl->sec_lvl_buckets_per_blk))\r
- ) * HASH_2ND_LVL_ENTRY_SIZE;\r
- }\r
- hash_tbl->nodes_1st_lvl_begin[i] = (__VIP_HASH_NODE_P_T*)MALLOC(block_size_to_allocate);\r
- if (hash_tbl->nodes_1st_lvl_begin[i] == NULL) {\r
- MTL_ERROR1(MT_FLFMT("hash resize: malloc failure at 2nd level block %d"), i);\r
- for (j = curr_blocks; j < i; j++) {\r
- FREE(hash_tbl->nodes_1st_lvl_begin[j]);\r
- hash_tbl->nodes_1st_lvl_begin[j]=NULL;\r
- }\r
- hash_tbl->may_grow = FALSE;\r
- return MT_EAGAIN;\r
- } else {\r
- memset(hash_tbl->nodes_1st_lvl_begin[i], 0, block_size_to_allocate);\r
- }\r
- }\r
-\r
- /* adjust vip array object parameters */\r
- \r
- /* add required n */\r
- /* Rehash all nodes from buckets table to new positions */\r
- MOSAL_spinlock_dpc_lock(&(hash_tbl->hash_lock));\r
- hash_tbl->buckets = new_buckets;\r
-\r
- old_bucket_ix = 0;\r
- for (i = 0; i < (int)curr_blocks; i++)\r
- {\r
- __VIP_HASH_NODE_P_T* sec_lvl_block;\r
- if (i == (int)curr_blocks-1) {\r
- buckets_per_blk = old_buckets - (i * buckets_per_blk);\r
- }\r
- sec_lvl_block = hash_tbl->nodes_1st_lvl_begin[i];\r
- for (j = 0; j < (int)buckets_per_blk; old_bucket_ix++,j++) {\r
-\r
- __VIP_HASH_NODE_P_T* new_bucket;\r
- __VIP_HASH_NODE_P_T node;\r
- __VIP_HASH_NODE_P_T* prev = (sec_lvl_block+j);\r
- node = *prev;\r
- while (node != NULL) \r
- {\r
- u_int32_t new_bucket_idx;\r
- new_bucket_idx = VIP_HASH_BUCKET(__VIP_HASH_FUNC(node->key), new_buckets);\r
- if (old_bucket_ix == new_bucket_idx) {\r
- /* rehashes to same bucket. just continue, updating prev pointer */\r
- prev = &(node->next);\r
- node = node->next;\r
- continue;\r
- }\r
- /* need to move entry to another bucket */\r
- /* a. remove from old */\r
- *prev = node->next;\r
- /* b. insert node into a different bucket. done here without spinlocks, since\r
- * entire table is currently locked\r
- */\r
- new_bucket = GET_BUCKET_BY_IX(hash_tbl,new_bucket_idx);\r
- node->next = *new_bucket;\r
- *new_bucket = node;\r
- /* go to next link in old bucket. prev guaranteed not null */\r
- node = *prev;\r
- }\r
- }\r
- }\r
- \r
- MOSAL_spinlock_unlock(&(hash_tbl->hash_lock));\r
- return MT_OK;\r
-} /* resize[p] */\r
- \r
-\r
-/*******************************************************************************\r
- * Function: VIP_hash[p]_create\r
- *\r
- * Arguments:\r
- * size (IN) - Approximate initial size. \r
- * VIP_hash[p]_p (OUT) - Return new hash_tbl object here\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EAGAIN: Not enough resources\r
- *\r
- * Description:\r
- * Create a new hash_tbl table\r
- *\r
- ******************************************************************************/\r
-VIP_common_ret_t __VIP_HASH_PICK(VIP_hash_create_maxsize, \r
- VIP_hashp_create_maxsize,\r
- VIP_hashp2p_create_maxsize,\r
- VIP_hash64p_create_maxsize,\r
- VIP_hashv4p_create_maxsize)\r
-(u_int32_t reserve, u_int32_t max_size, __VIP_HASH_T* hash_p)\r
-{\r
- __VIP_HASH_T hash_tbl = NULL;\r
-\r
- if (max_size == 0) {max_size = HASH_DEFAULT_MAXSIZE;}\r
- if ( reserve > max_size) {\r
- MTL_ERROR1(MT_FLFMT("%s: requested size (0x%x) greater than supplied max size (0x%x"), __func__,\r
- reserve, max_size);\r
- return VIP_EINVAL_PARAM;\r
-}\r
-if (reserve > HASH_DEFAULT_MAXSIZE) {\r
- MTL_ERROR1(MT_FLFMT("%s: requested size (0x%x) greater than max permitted"), __func__, reserve);\r
- return VIP_EINVAL_PARAM;\r
-}\r
- \r
- hash_tbl = TMALLOC(__VIP_HASH_TBL_T);\r
- if (hash_tbl == NULL) { \r
- MTL_ERROR1(MT_FLFMT("%s failed: cannot allocate memory"), __func__ );\r
- return VIP_EAGAIN;\r
- }\r
-\r
- *hash_p = hash_tbl;\r
-\r
- memset(hash_tbl, 0, sizeof(__VIP_HASH_TBL_T));\r
- hash_tbl->size = 0;\r
- hash_tbl->buckets = 0;\r
- hash_tbl->may_grow = TRUE;\r
- hash_tbl->resize_in_progress= FALSE;\r
- hash_tbl->max_size = max_size;\r
-#if VIP_HASH_PRIME\r
- hash_tbl->max_buckets = (u_int32_t) mtl_find_prime((unsigned long) max_size);\r
-#else\r
- hash_tbl->max_buckets = (u_int32_t) mtl_find_power2((unsigned long) max_size);\r
-#endif\r
- hash_tbl->sec_lvl_buckets_per_blk = HASH_2ND_LVL_BUCKETS_PER_BLOCK;\r
- hash_tbl->sec_lvl_buckets_per_blk_m_1 = hash_tbl->sec_lvl_buckets_per_blk - 1;\r
- hash_tbl->size_2nd_lvl_block = HASH_2ND_LVL_BLOCK_SIZE;\r
- hash_tbl->log2_2nd_lvl_entries_per_blk = HASH_LOG_2ND_LVL_BUCKETS_PER_BLOCK; \r
- hash_tbl->max_2nd_lvl_blocks = HASH_CALC_MAX_2ND_LVL_BLOCKS(hash_tbl);\r
-\r
- MOSAL_spinlock_init(&(hash_tbl->hash_lock));\r
- /* Allocate hash table of given "reserve" size (will be at least the minimum > 0)*/\r
- // MTL_DEBUG4(MT_FLFMT("going to call resize"));\r
- if (resize(hash_tbl, reserve ) != MT_OK)\r
- { /* nodes_begin should never be NULL */\r
- if (hash_tbl->nodes_1st_lvl_begin != NULL) {\r
- FREE(hash_tbl->nodes_1st_lvl_begin);\r
- }\r
- FREE(hash_tbl);\r
- return VIP_EAGAIN;\r
- }\r
-\r
- return VIP_OK;\r
-} /* VIP_hash[p]_create */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Function: VIP_hash[p]_create\r
- *\r
- * Arguments:\r
- * size (IN) - Approximate initial size. \r
- * VIP_hash[p]_p (OUT) - Return new hash_tbl object here\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EAGAIN: Not enough resources\r
- *\r
- * Description:\r
- * Create a new hash_tbl table\r
- *\r
- ******************************************************************************/\r
-VIP_common_ret_t __VIP_HASH_PICK(VIP_hash_create, \r
- VIP_hashp_create,\r
- VIP_hashp2p_create,\r
- VIP_hash64p_create,\r
- VIP_hashv4p_create)\r
-(u_int32_t reserve, __VIP_HASH_T* hash_p)\r
-{\r
- return __VIP_HASH_PICK(VIP_hash_create_maxsize, \r
- VIP_hashp_create_maxsize,\r
- VIP_hashp2p_create_maxsize,\r
- VIP_hash64p_create_maxsize,\r
- VIP_hashv4p_create_maxsize) (reserve, HASH_DEFAULT_MAXSIZE, hash_p);\r
-} /* VIP_hash[p]_create */\r
-\r
-\r
-/*******************************************************************************\r
- * Function: VIP_hash[p]_destroy\r
- *\r
- * Arguments:\r
- * hash_tbl (IN) - Object to destroy\r
- *\r
- * Returns:\r
- * VIP_OK\r
- *\r
- * Description:\r
- * cleanup resources for a hash_tbl table\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t\r
-#if __VIP_HASH_VARIANT != 1 && __VIP_HASH_VARIANT != 2 && __VIP_HASH_VARIANT != 3 && __VIP_HASH_VARIANT != 4\r
- __VIP_HASH_PICK(VIP_hash_destroy,\r
- VIP_hashp_destroy BUTNOTUSEDHERE,\r
- VIP_hashp2p_destroy BUTNOTUSEDHERE,\r
- VIP_hash64p_destroy BUTNOTUSEDHERE,\r
- VIP_hashv4p_destroy BUTNOTUSEDHERE)\r
- (__VIP_HASH_T hash_tbl)\r
-#else /* __VIP_HASH_VARIANT == 1||2||3 | 4 */\r
- __VIP_HASH_PICK(VIP_hash_destroy BUTNOTUSEDHERE,\r
- VIP_hashp_destroy,\r
- VIP_hashp2p_destroy ,\r
- VIP_hash64p_destroy,\r
- VIP_hashv4p_destroy) (\r
- __VIP_HASH_T hash_tbl,\r
- void (*free_objects_fun)(__VIP_HASH_KEY_T key, __VIP_HASH_VAL_T val, void* priv_data),\r
- void* priv_data\r
- )\r
-#endif\r
-{\r
-\r
- int i,j;\r
- register u_int32_t buckets_per_blk=0; \r
- register u_int32_t curr_blocks;\r
- register __VIP_HASH_NODE_P_T* sec_lvl_block;\r
- register __VIP_HASH_NODE_P_T node;\r
- register __VIP_HASH_NODE_P_T next;\r
-\r
- if (hash_tbl == NULL) return VIP_OK;\r
- curr_blocks = HASH_CALC_NUM_2ND_LVL_BLOCKS(hash_tbl->buckets,hash_tbl);\r
- buckets_per_blk = hash_tbl->sec_lvl_buckets_per_blk;\r
-\r
- /* No lock because: \r
- * 1) process is not suppose to use the object at this stage \r
- * 2) "free_objects_fun" may invoke "free" function\r
- */\r
- /*MOSAL_spinlock_dpc_lock(&(hash_tbl->hash_lock));*/\r
- \r
- for (i = 0; i < (int)curr_blocks; i++)\r
- {\r
- if (i == (int)curr_blocks-1) {\r
- /* adjust for last 2nd level block having fewer entries */\r
- buckets_per_blk = hash_tbl->buckets - (i * buckets_per_blk);\r
- }\r
- sec_lvl_block = hash_tbl->nodes_1st_lvl_begin[i];\r
- for (j = 0; j < (int)buckets_per_blk; j++) {\r
- for (node = *(sec_lvl_block+j); node ; node = next) \r
- {\r
- next=node->next;\r
-#if __VIP_HASH_VARIANT == 1 || __VIP_HASH_VARIANT == 2 || __VIP_HASH_VARIANT == 3 || __VIP_HASH_VARIANT == 4\r
- if (free_objects_fun) free_objects_fun(node->key,node->val,priv_data);\r
-#endif\r
- FREE(node);\r
- }\r
- }\r
- FREE(sec_lvl_block);\r
- }\r
-\r
- FREE(hash_tbl->nodes_1st_lvl_begin);\r
- FREE(hash_tbl);\r
- \r
- return VIP_OK;\r
-}\r
-\r
-/********************************************************************************\r
- * Function: VIP_hash[p]_insert\r
- *\r
- * Arguments:\r
- * hash_tbl (IN) - Insert in this table\r
- * key (IN) - Key to insert\r
- * val (IN) - Value to insert\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EBUSY: the key is already in the hash_tbl\r
- * VIP_EAGAIN: not enough resources\r
- *\r
- * Description:\r
- * Associate this value with this key.\r
- * Return the value associated with this key.\r
- * Note: if the key is in the hash_tbl, table is not changed, and so \r
- * the returned value in tval_p may differ from val.\r
- *\r
- ******************************************************************************/\r
-VIP_common_ret_t __VIP_HASH_PICK(VIP_hash_insert, \r
- VIP_hashp_insert,\r
- VIP_hashp2p_insert,\r
- VIP_hash64p_insert,\r
- VIP_hashv4p_insert)\r
-(\r
- __VIP_HASH_T hash_tbl, \r
- __VIP_HASH_KEY_T key, \r
- __VIP_HASH_VAL_T val)\r
-{\r
- __VIP_HASH_VAL_T* val_p;\r
- VIP_common_ret_t rc = \r
- __VIP_HASH_PICK(VIP_hash_insert_ptr, \r
- VIP_hashp_insert_ptr,\r
- VIP_hashp2p_insert_ptr,\r
- VIP_hash64p_insert_ptr,\r
- VIP_hashv4p_insert_ptr)(\r
- hash_tbl, key, &val_p);\r
- if (rc == VIP_OK)\r
- {\r
- *val_p = val;\r
- }\r
- return rc;\r
-} /* VIP_hash[p]_insert */\r
-\r
-\r
-/********************************************************************************\r
- * Function: VIP_hash[p]_insert_ptr\r
- *\r
- * Arguments:\r
- * hash_tbl (IN) - Insert in this table\r
- * key (IN) - Key to insert\r
- * tval_p (OUT) - Value associated with the key\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EBUSY: the key is already in the hash_tbl\r
- * VIP_EAGAIN: not enough resources\r
- *\r
- * Description:\r
- * Associate a new value with this key.\r
- * This is like VIP_hash[p]_insert, but outputs a pointer\r
- * to the value field, through which the value may be set later.\r
- *\r
- * Note: if the key is already in the hash_tbl, \r
- * the returned value in tval_p points to the existing entry\r
- *\r
- ******************************************************************************/\r
-VIP_common_ret_t __VIP_HASH_PICK(VIP_hash_insert_ptr, \r
- VIP_hashp_insert_ptr,\r
- VIP_hashp2p_insert_ptr,\r
- VIP_hash64p_insert_ptr,\r
- VIP_hashv4p_insert_ptr)\r
-(\r
- __VIP_HASH_T hash_tbl, \r
- __VIP_HASH_KEY_T key, \r
- __VIP_HASH_VAL_T** tval_p)\r
-{\r
- u_int32_t bucket_n; \r
- __VIP_HASH_NODE_P_T* bucket = NULL; /* init to silent warning */\r
- __VIP_HASH_NODE_P_T node;\r
- __VIP_HASH_NODE_P_T new_node;\r
-\r
- if (hash_tbl == NULL) return VIP_EINVAL_HNDL;\r
- /* Try to allocate new hash node before locking spinlock */\r
- new_node = TMALLOC(__VIP_HASH_NODE_T);\r
- if (new_node == NULL) {\r
- MTL_ERROR1(MT_FLFMT("VIP_hash_insert failed to allocate new node"));\r
- return VIP_EAGAIN;\r
- }\r
- \r
- MOSAL_spinlock_dpc_lock(&(hash_tbl->hash_lock));\r
- \r
- /* Check if resize is required */\r
- if ((hash_tbl->size >= hash_tbl->buckets) && (hash_tbl->may_grow) &&\r
- (! hash_tbl->resize_in_progress) ) { /* Only one resize at a time */\r
- hash_tbl->resize_in_progress= TRUE;\r
- MOSAL_spinlock_unlock(&(hash_tbl->hash_lock));\r
- resize(hash_tbl, hash_tbl->size + 1); \r
- /* It will be nice if resize succeeds, but we can continue anyway */\r
- MOSAL_spinlock_dpc_lock(&(hash_tbl->hash_lock));\r
- hash_tbl->resize_in_progress= FALSE;\r
- }\r
- \r
- bucket_n = VIP_HASH_BUCKET( __VIP_HASH_FUNC(key), hash_tbl->buckets);\r
- bucket = GET_BUCKET_BY_IX(hash_tbl,bucket_n);\r
- /* First check if givenkey is not already in use */\r
- for (node=*bucket;node;node=node->next) {\r
-#if __VIP_HASH_VARIANT == 4\r
- if (!memcmp((const void *)&node->key[0], (const void *)&key[0], sizeof(__VIP_HASH_KEY_T))) {\r
-#else\r
- if (node->key == key) {\r
-#endif \r
- if (tval_p) { *tval_p=&(node->val); }\r
- MOSAL_spinlock_unlock(&(hash_tbl->hash_lock));\r
- FREE(new_node);\r
- return VIP_EBUSY;\r
- }\r
- }\r
- \r
- /* Now insert */\r
-#if __VIP_HASH_VARIANT == 4\r
- memcpy((void *)&new_node->key[0], (const void *)&key[0], sizeof(__VIP_HASH_KEY_T));\r
-#else\r
- new_node->key = key;\r
-#endif\r
- new_node->next = *bucket; /* Insert as first in bucket */\r
- *bucket= new_node;\r
- ++hash_tbl->size;\r
- \r
- MOSAL_spinlock_unlock(&(hash_tbl->hash_lock));\r
- \r
- if (tval_p) { *tval_p = &(new_node->val); }\r
-\r
- return VIP_OK;\r
-} /* VIP_hash[p]_insert_ptr */\r
-\r
-/*******************************************************************************\r
- * Function: VIP_hash[p]_erase\r
- *\r
- * Arguments:\r
- * hash_tbl (IN) - Insert in this table\r
- * key (IN) - remove value by this key\r
- * val (OUT) - if non zero, returns the value by this key here\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EINVAL_HNDL: key is not in the hash_tbl\r
- *\r
- * Description:\r
- * Remove the value associated with this key\r
- * Note: fails if key is not already in the hash_tbl\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t __VIP_HASH_PICK(VIP_hash_erase, \r
- VIP_hashp_erase,\r
- VIP_hashp2p_erase,\r
- VIP_hash64p_erase,\r
- VIP_hashv4p_erase)\r
-(\r
- __VIP_HASH_T hash_tbl,\r
- __VIP_HASH_KEY_T key,\r
- __VIP_HASH_VAL_T* val)\r
-{\r
- u_int32_t bucket_n;\r
- __VIP_HASH_NODE_P_T* bucket;\r
- __VIP_HASH_NODE_P_T node;\r
- /*pointer in previous node to this one */\r
- __VIP_HASH_NODE_P_T* prev;\r
-\r
- if (hash_tbl == NULL) return VIP_EINVAL_HNDL;\r
- \r
- MOSAL_spinlock_dpc_lock(&(hash_tbl->hash_lock));\r
-\r
- bucket_n = VIP_HASH_BUCKET(__VIP_HASH_FUNC(key), hash_tbl->buckets);\r
- bucket = GET_BUCKET_BY_IX(hash_tbl,bucket_n);\r
- prev= bucket;\r
- \r
- /* Try to find */\r
- for (node=*bucket; node; prev=&(node->next), node= node->next) {\r
-#if __VIP_HASH_VARIANT == 4\r
- if (!memcmp((const void *)&node->key[0], (const void *)&key[0], sizeof(__VIP_HASH_KEY_T))) {\r
-#else\r
- if (node->key == key) {\r
-#endif \r
- *prev= node->next; /* take out of bucket */\r
- --hash_tbl->size;\r
- MOSAL_spinlock_unlock(&(hash_tbl->hash_lock));\r
- if (val) { *val= node->val; } /* return last value before freeing node */\r
- FREE(node);\r
- return VIP_OK;\r
- }\r
- }\r
- \r
- MOSAL_spinlock_unlock(&(hash_tbl->hash_lock));\r
- return VIP_EINVAL_HNDL;\r
-} /* VIP_hash[p]_erase */\r
-\r
-/********************************************************************************\r
- * Function: VIP_hash[p]_find\r
- *\r
- * Arguments:\r
- * hash_tbl (IN) - Insert in this table\r
- * key (IN) - remove value by this key\r
- * val (OUT) - if non zero, returns the value by this key here\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EINVAL_HNDL: key is not in the hash_tbl\r
- *\r
- * Description:\r
- * Find the value associated with this key\r
- * Note: fails if key is not already in the hash_tbl\r
- *\r
- ******************************************************************************/\r
-VIP_common_ret_t __VIP_HASH_PICK(VIP_hash_find, \r
- VIP_hashp_find,\r
- VIP_hashp2p_find,\r
- VIP_hash64p_find,\r
- VIP_hashv4p_find)\r
-(\r
- __VIP_HASH_T hash_tbl,\r
- __VIP_HASH_KEY_T key,\r
- __VIP_HASH_VAL_T* val)\r
-{\r
- u_int32_t bucket_n;\r
- __VIP_HASH_NODE_P_T* bucket;\r
- __VIP_HASH_NODE_P_T node;\r
- \r
- if (hash_tbl == NULL) return VIP_EINVAL_HNDL;\r
- \r
- MOSAL_spinlock_dpc_lock(&(hash_tbl->hash_lock));\r
- \r
- bucket_n = VIP_HASH_BUCKET(__VIP_HASH_FUNC(key), hash_tbl->buckets);\r
- bucket = GET_BUCKET_BY_IX(hash_tbl,bucket_n);\r
-\r
- /* Try to find */\r
- for (node=*bucket;node;node=node->next) {\r
-#if __VIP_HASH_VARIANT == 4\r
- if (!memcmp((const void *)&node->key[0], (const void *)&key[0], sizeof(__VIP_HASH_KEY_T))) {\r
-#else\r
- if (node->key == key) {\r
-#endif \r
- if (val) *val=node->val;\r
- MOSAL_spinlock_unlock(&(hash_tbl->hash_lock));\r
- return VIP_OK;\r
- }\r
- }\r
- \r
- MOSAL_spinlock_unlock(&(hash_tbl->hash_lock));\r
- return VIP_EINVAL_HNDL;\r
-} /* VIP_hash[p]_find */\r
-\r
-\r
-/******************************************************************************\r
- * Function: VIP_hash[p]_find_ptr\r
- *\r
- * Arguments:\r
- * hash_tbl (IN) - Insert in this table\r
- * key (IN) - remove value by this key\r
- * val_p (OUT) - if non zero, contains the pointer to the entry\r
- * coresponding to given key\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EINVAL_HNDL: key is not in the hash_tbl\r
- *\r
- * Description:\r
- * Find the value associated with this key\r
- * This is like hashp_find, but returns pointer to the\r
- * value field, which makes it possible to modify\r
- * the value stored by this key.\r
- *\r
- * Note: fails if key is not already in the hash_tbl\r
- *\r
- ******************************************************************************/\r
-VIP_common_ret_t __VIP_HASH_PICK(VIP_hash_find_ptr, \r
- VIP_hashp_find_ptr,\r
- VIP_hashp2p_find_ptr,\r
- VIP_hash64p_find_ptr,\r
- VIP_hashv4p_find_ptr)\r
-(\r
- __VIP_HASH_T hash_tbl,\r
- __VIP_HASH_KEY_T key,\r
- __VIP_HASH_VAL_T** val_p )\r
-{\r
- u_int32_t bucket_n;\r
- __VIP_HASH_NODE_P_T* bucket;\r
- __VIP_HASH_NODE_P_T node;\r
-\r
- if (hash_tbl == NULL) return VIP_EINVAL_HNDL;\r
-\r
- MOSAL_spinlock_dpc_lock(&(hash_tbl->hash_lock));\r
-\r
- bucket_n = __VIP_HASH_FUNC(key) % hash_tbl->buckets;\r
- bucket = GET_BUCKET_BY_IX(hash_tbl,bucket_n);\r
- \r
- /* Try to find */\r
- for (node=*bucket;node;node=node->next) {\r
-#if __VIP_HASH_VARIANT == 4\r
- if (!memcmp((const void *)&node->key[0], (const void *)&key[0], sizeof(__VIP_HASH_KEY_T))) {\r
-#else\r
- if (node->key == key) {\r
-#endif \r
- if (val_p) *val_p=&(node->val);\r
- MOSAL_spinlock_unlock(&(hash_tbl->hash_lock));\r
- return VIP_OK;\r
- }\r
- }\r
- \r
- MOSAL_spinlock_unlock(&(hash_tbl->hash_lock));\r
- return VIP_EINVAL_HNDL;\r
-} /* VIP_hash[p]_find_ptr */\r
-\r
-\r
-/********************************************************************************\r
- * Function: VIP_hash[p]_get_num_of_objects\r
- *\r
- * Arguments:\r
- * hash_tbl (IN) - table\r
- *\r
- * Returns:\r
- * number of objects in the array\r
- *\r
- * Description:\r
- * Get number of objects\r
- *\r
- ********************************************************************************/\r
-u_int32_t\r
-__VIP_HASH_PICK(VIP_hash_get_num_of_objects, \r
- VIP_hashp_get_num_of_objects,\r
- VIP_hashp2p_get_num_of_objects,\r
- VIP_hash64p_get_num_of_objects,\r
- VIP_hashv4p_get_num_of_objects)\r
-(\r
- __VIP_HASH_T hash_tbl)\r
-{\r
- return hash_tbl->size;\r
-} /* VIP_hash[p]_get_num_of_objects */\r
-\r
-/********************************************************************************\r
- * Function: VIP_hash[p]_get_num_of_buckets\r
- *\r
- * Arguments:\r
- * hash_tbl (IN) - table\r
- *\r
- * Returns:\r
- * number of buckets in the array\r
- *\r
- * Description:\r
- * Get number of buckets\r
- *\r
- ********************************************************************************/\r
-u_int32_t\r
-__VIP_HASH_PICK(VIP_hash_get_num_of_buckets, \r
- VIP_hashp_get_num_of_buckets,\r
- VIP_hashp2p_get_num_of_buckets,\r
- VIP_hash64p_get_num_of_buckets,\r
- VIP_hashv4p_get_num_of_buckets)\r
-(\r
- __VIP_HASH_T hash_tbl)\r
-{\r
- return hash_tbl->buckets;\r
-} /* VIP_hash[p]_get_num_of_objects */\r
-\r
-/************************************************************************/\r
-MT_bool __VIP_HASH_PICK(VIP_hash_may_grow, \r
- VIP_hashp_may_grow,\r
- VIP_hashp2p_may_grow,\r
- VIP_hash64p_may_grow,\r
- VIP_hashv4p_may_grow)\r
-(\r
- __VIP_HASH_T hash_tbl, \r
- MT_bool flag)\r
-{\r
- MT_bool old = hash_tbl->may_grow;\r
- hash_tbl->may_grow = flag;\r
- return old;\r
-} /* VIP_hash[p]_may_grow */\r
-\r
-\r
-/************************************************************************/\r
-void __VIP_HASH_PICK(VIP_hash_traverse, \r
- VIP_hashp_traverse,\r
- VIP_hashp2p_traverse,\r
- VIP_hash64p_traverse,\r
- VIP_hashv4p_traverse)\r
-(\r
- __VIP_HASH_T hash_tbl,\r
- int (*ufunc)(__VIP_HASH_KEY_T key, __VIP_HASH_VAL_T val, void* vp),\r
- void* udata\r
-)\r
-{\r
- int i,j,go = 1;\r
- register u_int32_t buckets_per_blk=0; \r
- register u_int32_t curr_blocks; \r
- register __VIP_HASH_NODE_P_T* sec_lvl_block;\r
- register __VIP_HASH_NODE_P_T node;\r
- register __VIP_HASH_NODE_P_T next;\r
- \r
- if (hash_tbl == NULL) return;\r
-\r
- curr_blocks = HASH_CALC_NUM_2ND_LVL_BLOCKS(hash_tbl->buckets,hash_tbl);\r
- buckets_per_blk = hash_tbl->sec_lvl_buckets_per_blk;\r
-\r
- MOSAL_spinlock_dpc_lock(&(hash_tbl->hash_lock));\r
-\r
- for (i = 0; go && (i < (int)curr_blocks); i++)\r
- {\r
- if (i == (int)curr_blocks-1) {\r
- /* adjust for last 2nd level block having fewer entries */\r
- buckets_per_blk = hash_tbl->buckets - (i * buckets_per_blk);\r
- }\r
- sec_lvl_block = hash_tbl->nodes_1st_lvl_begin[i];\r
- for (j = 0; go && (j < (int)buckets_per_blk); j++) {\r
- for (node = *(sec_lvl_block+j); node && go; node = next) \r
- {\r
- next = node->next;\r
- go = (*ufunc)(node->key, node->val, udata);\r
- }\r
- }\r
- }\r
- \r
- MOSAL_spinlock_unlock(&(hash_tbl->hash_lock));\r
-} /* VIP_hash[p]_traverse */\r
\r
-/*\r
- * Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id:$\r
- */\r
-\r
-\r
-/*\r
- * Description: Common header for vip_hash{,p}.h\r
- *\r
- * For the sake of unifying functionality and implementation,\r
- * we use here (and so in vip_hash.ic) magic macros that do\r
- * "Manual C++-like template functions".\r
- * Thus the function come in (currently two) flavors:\r
- * VIP_hash_foo(...) - where entry's value is VIP_array_handle_t\r
- * VIP_hashp_foo(...) - where entry's value is void*\r
- * \r
- * Notes:\r
- * This 'inline' header file\r
- * + must NOT be included directly by clients.\r
- * + is intentionally not guarded with {#ifndef foo, #define foo, #endif},\r
- *\r
- * Version: $Id$\r
- *\r
- * Authors:\r
- * MST - mtsirkin@mellanox.co.il\r
- * yotam - yotamm@mellanox.co.il\r
- *\r
- * Changes:\r
- */ \r
- \r
-\r
-#if !defined(__VIP_HASH_VARIANT)\r
-# error __VIP_HASH_VARIANT undefined\r
-#endif\r
-\r
-#if !defined(__VIP_hash_key_t_DEFINED)\r
-#define __VIP_hash_key_t_DEFINED\r
-\r
- typedef u_int32_t VIP_hash_key_t;\r
- typedef VIP_hash_key_t VIP_hashp_key_t;\r
- typedef void* VIP_hashp2p_key_t;\r
- typedef u_int64_t VIP_hash64p_key_t;\r
- typedef u_int32_t VIP_hashv4p_key_t[4];\r
-\r
-#endif /* __VIP_hash_key_t_DEFINED */\r
-\r
-\r
-/* Pseudo C++ template for poor C */\r
-# undef __VIP_HASH_KEY_T\r
-# undef __VIP_HASH_VAL_T \r
-# undef __VIP_HASH_T \r
-# undef __VIP_HASH_PICK\r
-\r
-#if __VIP_HASH_VARIANT == 0\r
-# define __VIP_HASH_KEY_T VIP_hash_key_t\r
-# define __VIP_HASH_VAL_T VIP_hash_value_t\r
-# define __VIP_HASH_T VIP_hash_p_t\r
-# define __VIP_HASH_PICK(id, idp, idp2p, id64p, idv4p) id\r
-#elif __VIP_HASH_VARIANT == 1\r
-# define __VIP_HASH_KEY_T VIP_hash_key_t\r
-# define __VIP_HASH_VAL_T VIP_hashp_value_t\r
-# define __VIP_HASH_T VIP_hashp_p_t\r
-# define __VIP_HASH_PICK(id1, idp, idp2p, id64p, idv4p) idp\r
-#elif __VIP_HASH_VARIANT == 2\r
-# define __VIP_HASH_KEY_T VIP_hashp2p_key_t\r
-# define __VIP_HASH_VAL_T VIP_hashp2p_value_t\r
-# define __VIP_HASH_T VIP_hashp2p_p_t\r
-# define __VIP_HASH_PICK(id1, idp, idp2p, id64p, idv4p) idp2p\r
-#elif __VIP_HASH_VARIANT == 3\r
-# define __VIP_HASH_KEY_T VIP_hash64p_key_t\r
-# define __VIP_HASH_VAL_T VIP_hash64p_value_t\r
-# define __VIP_HASH_T VIP_hash64p_p_t\r
-# define __VIP_HASH_PICK(id1, idp, idp2p, id64p, idv4p) id64p\r
-#elif __VIP_HASH_VARIANT == 4\r
-# define __VIP_HASH_KEY_T VIP_hashv4p_key_t\r
-# define __VIP_HASH_VAL_T VIP_hashv4p_value_t\r
-# define __VIP_HASH_T VIP_hashv4p_p_t\r
-# define __VIP_HASH_PICK(id1, idp, idp2p, id64p, idv4p) idv4p\r
-#else\r
-# error Unsupported __VIP_HASH_VARIANT variant\r
-#endif\r
-\r
- /********************************************************************************\r
- * Function: VIP_hash<v>_create_maxsize\r
- *\r
- * Arguments:\r
- * reserve (IN) - (Approximate) initial size of the table. \r
- * Specify 0 for empty initialization that may grow.\r
- *\r
- * max_size(IN) - Approximate Maximum allowed number of buckets in table. The\r
- * true number will be the next larger prime number in the table of\r
- * primes in file vip_hash.c\r
- *\r
- * VIP_hash<v>_p (OUT) - Return new VIP_hash<v> object here\r
- * Set to NULL in case of an error\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EAGAIN: Not enough resources\r
- *\r
- * Description:\r
- * Create a new VIP_hash<v> table.\r
- * The table maintans a logical flag controlling whether\r
- * its buckets-size may grow. This can be set later with\r
- * the VIP_hash<v>_may_grow(flag) function (see later).\r
- * This may_grow flag is initialized with TRUE. When the allocated number of\r
- * buckets reaches the maximum value, the may_grow flag is set FALSE.\r
- *\r
- * When may_grow is TRUE, the table will try to set \r
- * the internal buckets size to some prime larger than the \r
- * the content size of the table. The buckets may grows\r
- * upon insert. Insertion can succeed even when failing to grow.\r
- * In such cases, buckets list will simply get longer.\r
- *\r
- ******************************************************************************/\r
-VIP_common_ret_t __VIP_HASH_PICK(VIP_hash_create_maxsize, \r
- VIP_hashp_create_maxsize, \r
- VIP_hashp2p_create_maxsize,\r
- VIP_hash64p_create_maxsize,\r
- VIP_hashv4p_create_maxsize)\r
-(u_int32_t reserve, u_int32_t max_size, __VIP_HASH_T* hash_p);\r
-\r
-\r
-/********************************************************************************\r
- * Function: VIP_hash<v>_create\r
- *\r
- * Arguments:\r
- * reserve (IN) - (Approximate) initial size of the table. \r
- * Specify 0 for empty initialization that may grow.\r
- *\r
- * VIP_hash<v>_p (OUT) - Return new VIP_hash<v> object here\r
- * Set to NULL in case of an error\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EAGAIN: Not enough resources\r
- *\r
- * Description:\r
- * Create a new VIP_hash<v> table.\r
- * The table maintans a logical flag controlling whether\r
- * its buckets-size may grow. This can be set later with\r
- * the VIP_hash<v>_may_grow(flag) function (see later).\r
- * This may_grow flag is initialized with TRUE.\r
- *\r
- * When may_grow is TRUE, the table will try to set \r
- * the internal buckets size to some prime larger than the \r
- * the content size of the table. The buckets may grows\r
- * upon insert. Insertion can succeed even when failing to grow.\r
- * In such cases, buckets list will simply get longer.\r
- *\r
- ******************************************************************************/\r
-VIP_common_ret_t __VIP_HASH_PICK(VIP_hash_create, \r
- VIP_hashp_create, \r
- VIP_hashp2p_create,\r
- VIP_hash64p_create,\r
- VIP_hashv4p_create)\r
-(u_int32_t reserve, __VIP_HASH_T* hash_p);\r
-\r
-\r
-/********************************************************************************\r
- * Function: VIP_hash<v>_destroy\r
- *\r
- * Arguments:\r
- * hash_tbl (IN) - Object to destroy\r
- * For the 'hashp' variant:\r
- * free_objects_fun (IN) - If non zero, call this function\r
- * for each object in the array (can be used\r
- * e.g. to deallocate memory).\r
- * Even if zero, the table is still deallocated.\r
- * priv_data (IN) - Private date (e.g., object context) common to all objects\r
- * (valid on if free_objects_fun != NULL)\r
- *\r
- * Returns:\r
- * VIP_OK\r
- *\r
- * Description:\r
- * cleanup resources for a hash_tbl table\r
- *\r
- * NOTE:\r
- * given free_objects_fun is invoked in DPC level.\r
- * It may not "go to sleep" and may not invoke VIP_hash functions for this table\r
- *\r
- ******************************************************************************/\r
-VIP_common_ret_t\r
-#if __VIP_HASH_VARIANT != 1 && __VIP_HASH_VARIANT != 2 && __VIP_HASH_VARIANT != 3 && __VIP_HASH_VARIANT != 4\r
- __VIP_HASH_PICK(VIP_hash_destroy,\r
- VIP_hashp_destroy BUTNOTUSEDHERE,\r
- VIP_hashp2p_destroy BUTNOTUSEDHERE,\r
- VIP_hash64p_destroy BUTNOTUSEDHERE,\r
- VIP_hashv4p_destroy BUTNOTUSEDHERE)\r
- (__VIP_HASH_T hash_tbl)\r
-#else /* __VIP_HASH_VARIANT == 1 */\r
- __VIP_HASH_PICK(VIP_hash_destroy BUTNOTUSEDHERE,\r
- VIP_hashp_destroy,\r
- VIP_hashp2p_destroy ,\r
- VIP_hash64p_destroy,\r
- VIP_hashv4p_destroy) (\r
- __VIP_HASH_T hash_tbl,\r
- void (*free_objects_fun)(__VIP_HASH_KEY_T key, __VIP_HASH_VAL_T val, void* priv_data),\r
- void* priv_data\r
- )\r
-#endif\r
-;\r
-\r
-/********************************************************************************\r
- * Function: VIP_hash<v>_insert\r
- *\r
- * Arguments:\r
- * hash_tbl (IN) - Insert in this table\r
- * key (IN) - Key to insert\r
- * val (IN) - Value to insert\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EBUSY: the key is already in the hash_tbl\r
- * VIP_EAGAIN: not enough resources\r
- *\r
- * Description:\r
- * Associate this value with this key.\r
- *\r
- ********************************************************************************/\r
-VIP_common_ret_t __VIP_HASH_PICK(VIP_hash_insert, \r
- VIP_hashp_insert,\r
- VIP_hashp2p_insert,\r
- VIP_hash64p_insert,\r
- VIP_hashv4p_insert)(\r
- __VIP_HASH_T hash_tbl, \r
- __VIP_HASH_KEY_T key, \r
- __VIP_HASH_VAL_T val);\r
-\r
-/********************************************************************************\r
- * Function: VIP_hash<v>_insert_ptr\r
- *\r
- * Arguments:\r
- * hash_tbl (IN) - Insert in this table\r
- * key (IN) - Key to insert\r
- * tval_p (OUT) - Value associated with the key\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EBUSY: the key is already in the hash_tbl\r
- * VIP_EAGAIN: not enough resources\r
- *\r
- * Description:\r
- * Associate a new value with this key.\r
- * This is like VIP_hash<v>_insert, but outputs a pointer\r
- * to the value field, through which the value may be set later.\r
- *\r
- * Note: if the key is already in the hash_tbl, \r
- * the returned value in tval_p points to the existing entry\r
- *\r
- *****************************************************************************/\r
-VIP_common_ret_t __VIP_HASH_PICK(VIP_hash_insert_ptr, \r
- VIP_hashp_insert_ptr,\r
- VIP_hashp2p_insert_ptr,\r
- VIP_hash64p_insert_ptr,\r
- VIP_hashv4p_insert_ptr)(\r
- __VIP_HASH_T hash_tbl, \r
- __VIP_HASH_KEY_T key,\r
- __VIP_HASH_VAL_T** tval_p);\r
-\r
-/******************************************************************************\r
- * Function: VIP_hash<v>_erase\r
- *\r
- * Arguments:\r
- * hash_tbl (IN) - Erase in this table\r
- * key (IN) - remove value by this key\r
- * val (OUT) - if non zero, returns the value by this key here\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EINVAL_HNDL: key is not in the hash_tbl\r
- *\r
- * Description:\r
- * Remove the value associated with this key\r
- * Note: fails if key is not already in the hash_tbl\r
- *\r
- ******************************************************************************/\r
-VIP_common_ret_t __VIP_HASH_PICK(VIP_hash_erase, \r
- VIP_hashp_erase,\r
- VIP_hashp2p_erase,\r
- VIP_hash64p_erase,\r
- VIP_hashv4p_erase)(\r
- __VIP_HASH_T hash_tbl,\r
- __VIP_HASH_KEY_T key,\r
- __VIP_HASH_VAL_T* val);\r
-\r
-/******************************************************************************\r
- * Function: VIP_hash<v>_find\r
- *\r
- * Arguments:\r
- * hash_tbl (IN) - Insert in this table\r
- * key (IN) - remove value by this key\r
- * val (OUT) - if non zero, returns the value by this key here\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EINVAL_HNDL: key is not in the hash_tbl\r
- *\r
- * Description:\r
- * Find the value associated with this key\r
- * Note: fails if key is not already in the hash_tbl\r
- *\r
- ******************************************************************************/\r
-VIP_common_ret_t __VIP_HASH_PICK(VIP_hash_find, \r
- VIP_hashp_find,\r
- VIP_hashp2p_find,\r
- VIP_hash64p_find,\r
- VIP_hashv4p_find)(\r
- __VIP_HASH_T hash_tbl,\r
- __VIP_HASH_KEY_T key,\r
- __VIP_HASH_VAL_T* val);\r
-\r
-/******************************************************************************\r
- * Function: VIP_hash<v>_find_ptr\r
- *\r
- * Arguments:\r
- * hash_tbl (IN) - Find in this table\r
- * key (IN) - remove value by this key\r
- * val_p (OUT) - if non zero, contains the pointer to the entry\r
- * coresponding to given key\r
- *\r
- * Returns:\r
- * VIP_OK, \r
- * VIP_EINVAL_HNDL: key is not in the hash_tbl\r
- *\r
- * Description:\r
- * Find the value associated with this key\r
- * This is like hashp_find, but returns pointer to the\r
- * value field, which makes it possible to modify\r
- * the value stored by this key.\r
- *\r
- * Note: fails if key is not already in the hash_tbl\r
- *\r
- ******************************************************************************/\r
-VIP_common_ret_t __VIP_HASH_PICK(VIP_hash_find_ptr, \r
- VIP_hashp_find_ptr,\r
- VIP_hashp2p_find_ptr,\r
- VIP_hash64p_find_ptr,\r
- VIP_hashv4p_find_ptr)(\r
- __VIP_HASH_T hash_tbl,\r
- __VIP_HASH_KEY_T key,\r
- __VIP_HASH_VAL_T** val_p );\r
-\r
-/********************************************************************************\r
- * Function: VIP_hash[p]_get_num_of_buckets\r
- *\r
- * Arguments:\r
- * hash_tbl (IN) - table\r
- *\r
- * Returns:\r
- * number of buckets in the array\r
- *\r
- * Description:\r
- * Get number of buckets\r
- *\r
- ********************************************************************************/\r
-u_int32_t\r
-__VIP_HASH_PICK(VIP_hash_get_num_of_buckets, \r
- VIP_hashp_get_num_of_buckets,\r
- VIP_hashp2p_get_num_of_buckets,\r
- VIP_hash64p_get_num_of_buckets,\r
- VIP_hashv4p_get_num_of_buckets)(\r
- __VIP_HASH_T hash_tbl);\r
-\r
-/*******************************************************************************\r
- * Function: VIP_hash<v>_get_num_of_objects\r
- *\r
- * Arguments:\r
- * hash_tbl (IN) - table\r
- *\r
- * Returns:\r
- * number of objects in the array\r
- *\r
- * Description:\r
- * Get number of objects\r
- *\r
- ******************************************************************************/\r
-u_int32_t\r
-__VIP_HASH_PICK(VIP_hash_get_num_of_objects, \r
- VIP_hashp_get_num_of_objects,\r
- VIP_hashp2p_get_num_of_objects,\r
- VIP_hash64p_get_num_of_objects,\r
- VIP_hashv4p_get_num_of_objects)(\r
- __VIP_HASH_T hash_tbl);\r
-\r
-/*******************************************************************************\r
- * Function: VIP_hash<v>_may_grow\r
- *\r
- * Arguments:\r
- * hash_tbl (IN) - The table handler.\r
- * flag (IN) - Boolean value determining, whether the buckets table\r
- * can grow in size. See VIP_hash<v>_create(...)\r
- * Returns:\r
- * Current (old) setting.\r
- *\r
- * Description:\r
- * Set the 'may_grow' flag to allow resizing of the buckets \r
- * to some prime larger than the logical size upon insertion.\r
- * Note, if the buckets are (still since initialized) are empty,\r
- * this may_grow flag will remain TRUE, and the call will be ignored.\r
- */\r
-\r
-MT_bool __VIP_HASH_PICK(VIP_hash_may_grow, \r
- VIP_hashp_may_grow,\r
- VIP_hashp2p_may_grow,\r
- VIP_hash64p_may_grow,\r
- VIP_hashv4p_may_grow)(\r
- __VIP_HASH_T hash_tbl, \r
- MT_bool flag);\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Function: VIP_hash<v>_traverse\r
- *\r
- * Arguments:\r
- * hash_tbl (IN) - table\r
- * ufunc (IN) - function of given prototype.\r
- * Traverse will continue as long as ufunc(...)\r
- * returns non zero.\r
- * udata (IN - client data pointer, to be passed to ufunc.\r
- *\r
- * Returns:\r
- * None\r
- *\r
- * Description:\r
- * Traverse the buckets, and call ufunc with all entries.\r
- * Stops at end, or when user function returns 0.\r
- * Could be significantly imporved, if we would keep\r
- * a linked list of actually used buckets.\r
- *\r
- * Note:\r
- * Given ufunc is invoked in DPC level.\r
- * The given ufunc may NOT invoke any of VIP_hash functions (for this hash table).\r
- * (it WILL cause a deadlock !)\r
- *\r
- ******************************************************************************/\r
-void __VIP_HASH_PICK(VIP_hash_traverse, \r
- VIP_hashp_traverse,\r
- VIP_hashp2p_traverse,\r
- VIP_hash64p_traverse,\r
- VIP_hashv4p_traverse)(\r
- __VIP_HASH_T hash_tbl,\r
- int (*ufunc)(__VIP_HASH_KEY_T key, __VIP_HASH_VAL_T val, void* vp),\r
- void* udata\r
-);\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
- \r
-\r
-#ifndef VIP_COMMON_VIP_hash64p_H\r
-#define VIP_COMMON_VIP_hash64p_H\r
-\r
-#include <mtl_types.h>\r
-#include "vip_common.h"\r
-\r
-typedef void* VIP_hash64p_value_t;\r
-typedef struct VIP_hash64p_t* VIP_hash64p_p_t;\r
-\r
-#undef __VIP_HASH_VARIANT \r
-#define __VIP_HASH_VARIANT 3\r
-#include "vip_hash.ih"\r
-\r
-#endif /* VIP_COMMON_VIP_hash64p_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#ifndef VIP_COMMON_VIP_hashp_H\r
-#define VIP_COMMON_VIP_hashp_H\r
-\r
-#include <mtl_types.h>\r
-#include "vip_common.h"\r
-\r
-typedef void* VIP_hashp_value_t;\r
-typedef struct VIP_hashp_t* VIP_hashp_p_t;\r
-\r
-#undef __VIP_HASH_VARIANT \r
-#define __VIP_HASH_VARIANT 1\r
-#include "vip_hash.ih"\r
-\r
-#endif /* VIP_COMMON_VIP_hashp_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
- \r
-\r
-#ifndef VIP_COMMON_VIP_hashp2p_H\r
-#define VIP_COMMON_VIP_hashp2p_H\r
-\r
-#include <mtl_types.h>\r
-#include "vip_common.h"\r
-\r
-typedef void* VIP_hashp2p_value_t;\r
-typedef struct VIP_hashp2p_t* VIP_hashp2p_p_t;\r
-\r
-#undef __VIP_HASH_VARIANT \r
-#define __VIP_HASH_VARIANT 2\r
-#include "vip_hash.ih"\r
-\r
-#endif /* VIP_COMMON_VIP_hashp2p_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#ifndef VIP_COMMON_VIP_hashv4p_H\r
-#define VIP_COMMON_VIP_hashv4p_H\r
-\r
-#include <mtl_types.h>\r
-#include "vip_common.h"\r
-\r
-typedef void* VIP_hashv4p_value_t;\r
-typedef struct VIP_hashv4p_t* VIP_hashv4p_p_t;\r
-\r
-#undef __VIP_HASH_VARIANT \r
-#define __VIP_HASH_VARIANT 4\r
-#include "vip_hash.ih"\r
-\r
-#endif /* VIP_COMMON_VIP_hashv4p_H */\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_EVAPI_H\r
-#define H_EVAPI_H\r
-\r
-#include <mtl_common.h>\r
-#include <vapi.h>\r
-\r
-\r
-/**********************************************************\r
- * \r
- * Function: EVAPI_get_hca_hndl\r
- *\r
- * Arguments:\r
- * hca_id : HCA ID to get handle for\r
- * hca_hndl_p : Returned handle\r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_ID : No such opened HCA.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (open device file or ioctl) \r
- * has returned an error.\r
- *\r
- * Description:\r
- * Get handle of an already opened HCA.\r
- *\r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_get_hca_hndl(\r
- IN VAPI_hca_id_t hca_id,\r
- OUT VAPI_hca_hndl_t *hca_hndl_p\r
-);\r
-\r
-/**********************************************************\r
- * \r
- * Function: EVAPI_release_hca_hndl\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA handle to for which to release process resources\r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL : No such opened HCA.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- *\r
- * Description:\r
- * Release all resources used by this process for an opened HCA.\r
- *\r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_release_hca_hndl(\r
- IN VAPI_hca_hndl_t hca_hndl\r
-);\r
-\r
-\r
-\r
-/**********************************************************\r
- * \r
- * Function: EVAPI_k_get_cq_hndl\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA handle\r
- * cq_hndl : VAPI cq handle\r
- * k_cq_hndl_p: pointer to kernel level handle for the cq\r
- *\r
- * Returns:\r
- * VIP_OK\r
- * VIP_EINVAL_HCA_HNDL : No such opened HCA.\r
- * VIP_EINVAL_CQ_HNDL : No such CQ.\r
- *\r
- * Description:\r
- * Get the vipkl cq handle for the cq. This may be used by a user level process\r
- * to pass this handle to another kernel driver which may then use\r
- * EVAPI_k_set/clear_comp_eventh() to attach/detach kernel handlers\r
- *\r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_k_get_cq_hndl( IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_cq_hndl_t cq_hndl,\r
- OUT VAPI_k_cq_hndl_t *k_cq_hndl_p);\r
-\r
-\r
-#ifdef __KERNEL__\r
-/**********************************************************\r
- * \r
- * Function: EVAPI_k_set_comp_eventh (kernel space only)\r
- *\r
- * Arguments:\r
- * k_hca_hndl : HCA handle\r
- * k_cq_hndl : cq handle\r
- * completion_handler : handler to call for completions on\r
- * Completion Queue cq_hndl\r
- * private_data : pointer to data for completion handler\r
- * completion_handler_hndl: returned handle to use for clearing this\r
- * completion handler\r
- *\r
- * Returns:\r
- * VIP_OK\r
- * VIP_EINVAL_HCA_HNDL : No such opened HCA.\r
- * VIP_EINVAL_CQ_HNDL : No such CQ.\r
- *\r
- * Description:\r
- * Registers a specific completion handler to handle completions \r
- * for a specific completion queue. The private data give here\r
- * is provided to the completion callback when a completion occurs\r
- * on the given CQ. If the private data is a pointer, it should point\r
- * to static or "malloc'ed" data; The private data must be available \r
- * until this completion handler instance is cleared (with \r
- * EVAPI_k_clear_comp_eventh).\r
- *\r
- * Note:\r
- * This function is exposed to kernel modules only.\r
- *\r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_k_set_comp_eventh(\r
- IN VAPI_hca_hndl_t k_hca_hndl,\r
- IN VAPI_k_cq_hndl_t k_cq_hndl,\r
- IN VAPI_completion_event_handler_t completion_handler,\r
- IN void * private_data,\r
- OUT EVAPI_compl_handler_hndl_t *completion_handler_hndl );\r
-\r
-\r
-/**********************************************************\r
- * \r
- * Function: EVAPI_k_clear_comp_eventh\r
- *\r
- * Arguments:\r
- * k_hca_hndl : HCA handle\r
- * completion_handler_hndl: handle to use for clearing this\r
- * completion handler\r
- *\r
- * Returns:\r
- * VIP_OK\r
- * VIP_EINVAL_HCA_HNDL : No such opened HCA.\r
- * VIP_EINVAL_CQ_HNDL : No such CQ.\r
- *\r
- * Description:\r
- * Clears a completion handler which was registered \r
- * to handle completions for a specific completion queue.\r
- * If a handler was not registered, returns OK anyway.\r
- *\r
- * Note:\r
- * This function is exposed to kernel modules only.\r
- *\r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_k_clear_comp_eventh(\r
- IN VAPI_hca_hndl_t k_hca_hndl,\r
- IN EVAPI_compl_handler_hndl_t completion_handler_hndl);\r
-\r
-\r
-/**********************************************************\r
- * \r
- * Function: EVAPI_k_set_destroy_cq_cbk\r
- *\r
- * Arguments:\r
- * k_hca_hndl : HCA handle\r
- * k_cq_hndl: Kernel level CQ handle as known from EVAPI_k_get_cq_hndl()\r
- * cbk_func: Callback function to invoke when the CQ is destroyed\r
- * private_data: Caller's context to be used when invoking the callback\r
- *\r
- * Returns:\r
- * VIP_OK\r
- * VIP_EINVAL_HCA_HNDL : No such opened HCA.\r
- * VIP_EINVAL_CQ_HNDL : No such CQ.\r
- * VAPI_EBUSY: A destroy_cq callback is already set for this CQ\r
- * \r
- *\r
- * Description:\r
- * Set a callback function that notifies the caller (a kernel module that\r
- * uses EVAPI_k_set_comp_eventh ) when a CQ is destroyed.\r
- * The function is meant to be used in order to clean the kernel module's\r
- * context for that resource, and not in order to clear the completion handler.\r
- * The callback is invoked after the CQ handle is already invalid\r
- * so EVAPI_k_clear_comp_eventh is not suppose to be called for the \r
- * obsolete CQ (the completion_handler_hndl is already invalid).\r
- * This callback is implicitly cleared after it is called.\r
- *\r
- * Note: Only a single context in kernel may invoke this function per CQ.\r
- * Simultanous invocation by more than one kernel context,\r
- * for the same CQ, will result in unexpected behavior.\r
- *\r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_k_set_destroy_cq_cbk(\r
- IN VAPI_hca_hndl_t k_hca_hndl,\r
- IN VAPI_k_cq_hndl_t k_cq_hndl,\r
- IN EVAPI_destroy_cq_cbk_t cbk_func,\r
- IN void* private_data\r
-);\r
- \r
-/**********************************************************\r
- * \r
- * Function: EVAPI_k_clear_destroy_cq_cbk\r
- *\r
- * Arguments:\r
- * k_hca_hndl : HCA handle\r
- * k_cq_hndl: Kernel level CQ handle as known from EVAPI_k_get_cq_hndl()\r
- *\r
- * Returns:\r
- * VIP_OK\r
- * VIP_EINVAL_HCA_HNDL : No such opened HCA.\r
- * VIP_EINVAL_CQ_HNDL : No such CQ.\r
- *\r
- * Description:\r
- * Clear the callback function set in EVAPI_k_set_destroy_cq_cbk().\r
- * Use this function when the kernel module stops using the given k_cq_hndl.\r
- *\r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_k_clear_destroy_cq_cbk(\r
- IN VAPI_hca_hndl_t k_hca_hndl,\r
- IN VAPI_k_cq_hndl_t k_cq_hndl\r
-);\r
- \r
- \r
-#endif /* __KERNEL__ */\r
-\r
-\r
-/**********************************************************\r
- * \r
- * Function: EVAPI_set_comp_eventh\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA handle\r
- * cq_hndl : cq handle\r
- * completion_handler : handler to call for completions on\r
- * Completion Queue cq_hndl\r
- * private_data : pointer to data for completion handler\r
- * completion_handler_hndl: returned handle to use for clearing this\r
- * completion handler\r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL : No such opened HCA.\r
- * VAPI_EINVAL_CQ_HNDL : No such CQ.\r
- * VAPI_EINVAL_PARAM: Event handler is NULL\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- *\r
- * Description:\r
- * Registers a specific completion handler to handle completions \r
- * for a specific completion queue. The private data give here\r
- * is provided to the completion callback when a completion occurs\r
- * on the given CQ. If the private data is a pointer, it should point\r
- * to static or "malloc'ed" data; The private data must be available \r
- * until this completion handler instance is cleared (with \r
- * EVAPI_clear_comp_eventh).\r
- *\r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_set_comp_eventh(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_cq_hndl_t cq_hndl,\r
- IN VAPI_completion_event_handler_t completion_handler,\r
- IN void * private_data,\r
- OUT EVAPI_compl_handler_hndl_t *completion_handler_hndl );\r
-\r
-\r
-/**********************************************************\r
- * \r
- * Function: EVAPI_clear_comp_eventh\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA handle\r
- * completion_handler_hndl: handle to use for clearing this\r
- * completion handler\r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL : No such opened HCA.\r
- * VAPI_EINVAL_CQ_HNDL : No such CQ.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- *\r
- * Description:\r
- * Clears a completion handler which was registered \r
- * to handle completions for a specific completion queue.\r
- * If a handler was not registered, returns OK anyway.\r
- *\r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_clear_comp_eventh(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN EVAPI_compl_handler_hndl_t completion_handler_hndl ); \r
-\r
-#define EVAPI_POLL_CQ_UNBLOCK_HANDLER ((VAPI_completion_event_handler_t)(-2))\r
-/**********************************************************\r
- * \r
- * Function: EVAPI_poll_cq_block\r
- *\r
- * Arguments:\r
- * hca_hndl: Handle to HCA.\r
- * cq_hndl: CQ Handle.\r
- * timeout_usec: Timeout of blocking in micro-seconds (0 = infinite timeout)\r
- * comp_desc_p: Pointer to work completion descriptor structure.\r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_CQ_HNDL: invalid CQ handle\r
- * VAPI_EINVAL_PARAM: Event handler not initialized with EVAPI_POLL_CQ_UNBLOCK_HANDLER\r
- * VAPI_ETIMEOUT: Blocking timed out (and got no completion event).\r
- * VAPI_CQ_EMPTY: Blocking interrupted due to EVAPI_poll_cq_unblock() call OR\r
- * got a completion event due to a previous call to this function or\r
- * another request for completion notification.\r
- * VAPI_EINTR: Operation interrupted (OS signal)\r
- *\r
- * Description:\r
- * Poll given CQ and if empty, request completion notification event and\r
- * then sleep until event received, then poll again and return result\r
- * (even if still empty - to allow cancelling of blocking, e.g. on signals).\r
- *\r
- * Notes:\r
- * 1) This function will block only if EVAPI_set_comp_eventh was invoked for this\r
- * CQ with completion_handler=EVAPI_POLL_CQ_UNBLOCK_HANDLER.\r
- * (EVAPI_clear_comp_eventh should be invoked for cleanup, as for regular callback)\r
- * 2) One cannot set another completion event handler for this CQ \r
- * (handler is bounded to CQ unblocking handler).\r
- * 3) VAPI_req_comp_notif should not be invoked explicitly for a CQ using this facility.\r
- * 4) One may still use (non-blocking) VAPI_poll_cq() for this CQ.\r
- *\r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_poll_cq_block(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_cq_hndl_t cq_hndl,\r
- IN MT_size_t timeout_usec,\r
- OUT VAPI_wc_desc_t *comp_desc_p\r
- );\r
-\r
-/**********************************************************\r
- * \r
- * Function: EVAPI_poll_cq_unblock\r
- *\r
- * Arguments:\r
- * hca_hndl: Handle to HCA.\r
- * cq_hndl: CQ Handle.\r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_CQ_HNDL: invalid CQ handle\r
- *\r
- * Description:\r
- * Signal a thread blocked with EVAPI_poll_cq_block() to "wake-up".\r
- * ("waked-up" thread will poll the CQ again anyway and return result/completion)\r
- *\r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_poll_cq_unblock(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_cq_hndl_t cq_hndl\r
- );\r
-\r
-\r
-/**********************************************************\r
- * \r
- * Function: EVAPI_peek_cq\r
- *\r
- * Arguments:\r
- * hca_hndl: Handle to HCA.\r
- * cq_hndl: CQ Handle.\r
- * cqe_num: Number of CQE to peek to (next CQE is #1)\r
- *\r
- * Returns:\r
- * VAPI_OK: At least cqe_num CQEs outstanding in given CQ\r
- * VAPI_CQ_EMPTY: Less than cqe_num CQEs are outstanding in given CQ\r
- * VAPI_E2BIG_CQ_NUM: cqe_index is beyond CQ size (or 0)\r
- * VAPI_EINVAL_CQ_HNDL: invalid CQ handle\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- *\r
- * Description:\r
- * Check if there are at least cqe_num CQEs outstanding in the CQ.\r
- * (i.e., peek into the cqe_num CQE in the given CQ). \r
- * No CQE is consumed from the CQ.\r
- *\r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_peek_cq(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_cq_hndl_t cq_hndl,\r
- IN VAPI_cqe_num_t cqe_num\r
-);\r
-\r
-/*************************************************************************\r
- * Function: EVAPI_req_ncomp_notif\r
- *\r
- * Arguments:\r
- * hca_hndl: Handle to HCA.\r
- * cq_hndl: CQ Handle.\r
- * cqe_num: Number of outstanding CQEs which trigger this notification \r
- * This may be 1 up to CQ size, limited by HCA capability (0x7FFF for InfiniHost)\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_CQ_HNDL: invalid CQ handle\r
- * VAPI_E2BIG_CQ_NUM: cqe_index is beyond CQ size or beyond HCA notification capability (or 0)\r
- * For InfiniHost cqe_num is limited to 0x7FFF.\r
- * VAPI_EPERM: not enough permissions.\r
- * \r
- * \r
- *\r
- * Description:\r
- * Request notification when CQ holds at least N (non-polled) CQEs\r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API EVAPI_req_ncomp_notif(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_cq_hndl_t cq_hndl,\r
- IN VAPI_cqe_num_t cqe_num\r
- );\r
-\r
-\r
-/*****************************************************************************\r
- * Function: EVAPI_list_hcas\r
- *\r
- * Arguments:\r
- * hca_id_buf_sz(IN) : Number of entries in supplied array 'hca_id_buf_p',\r
- * num_of_hcas_p(OUT) : Actual number of currently available HCAs\r
- * hca_id_buf_p(OUT) : points to an\n array allocated by the caller of \r
- * 'VAPI_hca_id_t' items, able to hold 'hca_id_buf_sz' \r
- * entries of that item.\r
-\r
- *\r
- * Returns: VAPI_OK : operation successful.\r
- * VAPI_EINVAL_PARAM : Invalid parameter.\r
- * VAPI_EAGAIN : hca_id_buf_sz is smaller than num_of_hcas. In this case, NO hca_ids\r
- * are returned in the provided array.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (open device file, or ioctl) \r
- * has returned an error.\r
- *\r
- * Description:\r
- * Used to get a list of the device IDs of the available devices.\r
- * These names can then be used in VAPI_open_hca to open each\r
- * device in turn.\r
- *\r
- * If the size of the supplied buffer is too small, the number of available devices\r
- * is still returned in the num_of_hcas parameter, but the return code is set to\r
- * HH_EAGAIN. In this case, NO device IDs are returned; the user must simply supply\r
- * a larger array and call this procedure again. (The user may call this function\r
- * with hca_id_buf_sz = 0 and hca_id_buf_p = NULL to get the number of hcas currently\r
- * available).\r
- *****************************************************************************/\r
-\r
-VAPI_ret_t MT_API EVAPI_list_hcas(/* IN*/ u_int32_t hca_id_buf_sz,\r
- /*OUT*/ u_int32_t* num_of_hcas_p,\r
- /*OUT*/ VAPI_hca_id_t* hca_id_buf_p);\r
-\r
-/**********************************************************\r
- * Function: EVAPI_process_local_mad\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA handle\r
- * port : port which received the MAD packet\r
- * slid : Source LID of incoming MAD. Required Mkey violation trap genenration.\r
- * (this parameter is ignored if EVAPI_MAD_IGNORE_MKEY flag is set)\r
- * proc_mad_opts: Modifiers to MAD processing.\r
- * currently, only modifier is : EVAPI_MAD_IGNORE_MKEY\r
- * mad_in_p: pointer to MAD packet received\r
- * mad_out_p: pointer to response MAD packet, if any\r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL : No such opened HCA.\r
- * VAPI_EINVAL_PORT : No such port.\r
- * VAPI_EINVAL_PARAM : invalid parameter (error in mad_in packet)\r
- * VAPI_EGEN\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- *\r
- * Description:\r
- * submits a MAD packet to the local HCA for processing.\r
- * Obtains the response MAD. mad_out_p must be a buffer of\r
- * size 256 (IB_MAD_LEN) allocated by caller.\r
- *\r
- * for the proc_mad_opts argument, if EVAPI_MAD_IGNORE_MKEY is given, MKEY\r
- * will be ignored when processing the MAD. If zero is given for this argument\r
- * MKEY validation will be performed (this is the default), and the given slid\r
- * may be used to generate a trap in case of Mkey violation, as defined in IB-spec.\r
- *\r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_process_local_mad(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN IB_port_t port,\r
- IN IB_lid_t slid, /* ignored on EVAPI_MAD_IGNORE_MKEY */\r
- IN EVAPI_proc_mad_opt_t proc_mad_opts,\r
- IN const void * mad_in_p,\r
- OUT void * mad_out_p); \r
-\r
-\r
-/**********************************************************\r
- * Function: EVAPI_set/get_priv_context4qp/cq\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA handle\r
- * qp/cq : QP/CQ for which the private context refers\r
- * priv_context : Set/Returned private context associated with given QP/CQ\r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL : No such opened HCA.\r
- * VAPI_EINVAL_QP_HNDL/VAPI_EINVAL_CQ_HNDL : Unknown QP/CQ within current context\r
- *\r
- * Description:\r
- * Set/Get private context for QP/CQ.\r
- *\r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_set_priv_context4qp(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_qp_hndl_t qp,\r
- IN void * priv_context);\r
-\r
-VAPI_ret_t MT_API EVAPI_get_priv_context4qp(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_qp_hndl_t qp,\r
- OUT void ** priv_context_p);\r
-\r
-VAPI_ret_t MT_API EVAPI_set_priv_context4cq(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_cq_hndl_t cq,\r
- IN void * priv_context);\r
-\r
-VAPI_ret_t MT_API EVAPI_get_priv_context4cq(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_cq_hndl_t cq,\r
- OUT void ** priv_context_p);\r
- \r
-\r
-#ifdef __KERNEL__\r
-/* FMRs are not allowed in user-space */\r
-\r
-/*************************************************************************\r
- * Function: EVAPI_alloc_fmr\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * fmr_props_p: Pointer to the requested fast memory region properties.\r
- * fmr_hndl_p: Pointer to the fast memory region handle.\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EAGAIN: out of resources\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_PD_HNDL: invalid PD handle\r
- * VAPI_EINVAL_LEN: invalid length\r
- * VAPI_EINVAL_ACL: invalid ACL specifier (e.g. VAPI_EN_MEMREG_BIND)\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- *\r
- * Description:\r
- * Allocate a fast memory region resource, to be used with EVAPI_map_fmr/EVAPI_unmap_fmr\r
- * \r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_alloc_fmr(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN EVAPI_fmr_t *fmr_props_p,\r
- OUT EVAPI_fmr_hndl_t *fmr_hndl_p\r
-);\r
-\r
-/*************************************************************************\r
- * Function: EVAPI_map_fmr\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * fmr_hndl: The fast memory region handle.\r
- * map_p: Properties of mapping request\r
- * l_key_p: Allocated L-Key for the new mapping \r
- * (may be different than prev. mapping of the same FMR)\r
- * r_key_p: Allocated R-Key for the new mapping\r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EAGAIN: out of resources (invoke EVAPI_unmap_fmr for this region and then retry)\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_MR_HNDL: invalid memory region handle (e.g. not a FMR region)\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * Description:\r
- * Map given memory block to this fast memory region resource.\r
- * Upon a return from this function, the new L-key/R-key may be used in regard to CI operations\r
- * over given memory block.\r
- * \r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_map_fmr(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN EVAPI_fmr_hndl_t fmr_hndl,\r
- IN EVAPI_fmr_map_t *map_p,\r
- OUT VAPI_lkey_t *l_key_p,\r
- OUT VAPI_rkey_t *r_key_p\r
-);\r
-\r
-\r
-/*************************************************************************\r
- * Function: EVAPI_unmap_fmr\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * num_of_fmrs_to_unmap: Number of memory regions handles in given array\r
- * fmr_hndls_array: Array of num_of_fmrs_to_unmap FMR handles to unmap.(!max limit: 2000 handles)\r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EAGAIN: out of resources\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_MR_HNDL: invalid memory region handle (e.g. not a FMR region)\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * Description:\r
- * Unmap given FMRs.\r
- * In case of a failure other than VAPI_EINVAL_HCA_HNDL or VAPI_ESYSCALL,\r
- * the state of the FMRs is undefined (some may still be mapped while others umapped).\r
- * \r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_unmap_fmr(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN MT_size_t num_of_fmrs_to_unmap,\r
- IN EVAPI_fmr_hndl_t *fmr_hndls_array\r
-);\r
-\r
-/*************************************************************************\r
- * Function: EVAPI_free_fmr\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * fmr_hndl: The fast memory region handle.\r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EAGAIN: out of resources\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_MR_HNDL: invalid memory region handle (e.g. not a FMR region, or an u)\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * Description:\r
- * Free given FMR resource.\r
- * \r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_free_fmr(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN EVAPI_fmr_hndl_t mr_hndl\r
-);\r
-\r
-#endif /* FMRs in kernel only */\r
-\r
-/* *************************************************************************\r
- * Function: EVAPI_post_inline_sr\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * qp_hndl: QP Handle.\r
- * sr_desc_p: Pointer to the send request descriptor attributes structure.\r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_QP_HNDL: invalid QP handle\r
- * VAPI_E2BIG_WR_NUM: Too many posted work requests.\r
- * VAPI_EINVAL_OP: invalid operation\r
- * VAPI_EINVAL_QP_STATE: invalid QP state\r
- * VAPI_EINVAL_NOTIF_TYPE: invalid completion notification type\r
- * VAPI_EINVAL_SG_FMT: invalid scatter/gather list format \r
- * VAPI_EINVAL_SG_NUM: invalid scatter/gather list length\r
- * (too much data for inline send with this QP) \r
- * VAPI_EINVAL_AH: invalid address handle\r
- * VAPI_EPERM: not enough permissions.\r
- *\r
- * Description:\r
- * Post data in given gather list as inline data in a send WQE.\r
- * (Only for Sends and RDMA-writes, with optional immediate)\r
- *\r
- * Note:\r
- * 1) No L-key checks are done. Data is copied to WQE from given virtual address in \r
- * this process memory space.\r
- * 2) Maximum data is limited by maximum WQE size for this QP's \r
- * send queue. Information on this limitation may be queried via VAPI_query_qp\r
- * (property max_inline_data_sq in QP capabilities).\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API EVAPI_post_inline_sr(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_qp_hndl_t qp_hndl,\r
- IN VAPI_sr_desc_t *sr_desc_p\r
-);\r
-\r
-/* *************************************************************************\r
- * Function: EVAPI_post_sr_list\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * qp_hndl: QP Handle.\r
- * num_of_requests: Number of send requests in the given array\r
- * sr_desc_array: Pointer to an array of num_of_requests send requests\r
- * \r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_QP_HNDL: invalid QP handle\r
- * VAPI_E2BIG_WR_NUM: Too many posted work requests.\r
- * VAPI_EINVAL_OP: invalid operation\r
- * VAPI_EINVAL_QP_STATE: invlaid QP state\r
- * VAPI_EINVAL_NOTIF_TYPE: invalid completion notification \r
- * type\r
- * VAPI_EINVAL_SG_FMT: invalid scatter/gather list format\r
- * VAPI_EINVAL_SG_NUM: invalid scatter/gather list length\r
- * VAPI_EINVAL_AH: invalid address handle\r
- * VAPI_EAGAIN: not enough resources to complete operation (not enough WQEs)\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_EINVAL_PARAM: num_of_requests is 0 or sr_desc_array is NULL\r
- * \r
- * Description:\r
- * The verb posts num_of_requests send queue work requests, as given in the sr_desc_array\r
- * In case of a failure none of the requests is posted ("all or nothing").\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API EVAPI_post_sr_list(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_qp_hndl_t qp_hndl,\r
- IN u_int32_t num_of_requests,\r
- IN VAPI_sr_desc_t *sr_desc_array\r
- );\r
-\r
-/* *************************************************************************\r
- * Function: EVAPI_post_gsi_sr\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * qp_hndl : QP Handle.\r
- * sr_desc_p : Pointer to the send request descriptor attributes structure.\r
- * pkey_index: P-Key index in Pkey table of the port of the QP to put in BTH of sent GMP\r
- * \r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_QP_HNDL: invalid QP handle (or not a GSI QP)\r
- * VAPI_E2BIG_WR_NUM: Too many posted work requests.\r
- * VAPI_EINVAL_OP: invalid operation\r
- * VAPI_EINVAL_QP_STATE: invlaid QP state\r
- * VAPI_EINVAL_SG_NUM: invalid scatter/gather list length\r
- * VAPI_EINVAL_AH: invalid address handle\r
- * VAPI_EPERM: not enough permissions.\r
- * \r
- * Description:\r
- * The verb posts a send queue work request to the given GSI QP, with given P-key index\r
- * used in the GMP's BTH, instead of the QP's P-key.\r
- * This function has identical sematics to VAPI_post_sr, but for the overriden P-Key index.\r
- * Using this function allows one to change P-key used by the given GSI QP without having\r
- * to modify to SQD state first.\r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API EVAPI_post_gsi_sr(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_qp_hndl_t qp_hndl,\r
- IN VAPI_sr_desc_t *sr_desc_p,\r
- IN VAPI_pkey_ix_t pkey_index\r
- );\r
-\r
-/************************************************************************\r
- * Function: EVAPI_post_rr_list\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * qp_hndl: QP Handle.\r
- * num_of_requests: Number of receive requests in the given array\r
- * rr_desc_array: Pointer to an array of num_of_requests receive requests\r
- * \r
- * returns: \r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_QP_HNDL: invalid QP handle\r
- * VAPI_EINVAL_SRQ_HNDL: QP handle used for a QP associted with a SRQ (use VAPI_post_srq)\r
- * VAPI_E2BIG_WR_NUM: Too many posted work requests.\r
- * VAPI_EINVAL_OP: invalid operation\r
- * VAPI_EINVAL_QP_STATE: invlaid QP state\r
- * VAPI_EINVAL_SG_NUM: invalid scatter/gather list length\r
- * VAPI_EAGAIN: Not enough resources to complete operation (not enough WQEs)\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_EINVAL_PARAM: num_of_requests is 0 or rr_desc_array is NULL\r
- * \r
- * Description:\r
- * The verb posts all the given receive requests to the receive queue. \r
- * Given QP must have num_of_requests available WQEs in its receive queue.\r
- * In case of a failure none of the requests is posted ("all or nothing").\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API EVAPI_post_rr_list(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_qp_hndl_t qp_hndl,\r
- IN u_int32_t num_of_requests,\r
- IN VAPI_rr_desc_t *rr_desc_array\r
- );\r
-\r
-\r
-/* *************************************************************************\r
- * Function: EVAPI_k_get_qp_hndl\r
- *\r
- * Arguments:\r
- * 1) hca_hndl : HCA Handle.\r
- * 2) qp_ul_hndl: user level QP Handle.\r
- * 3) qp_kl_hndl_p: Pointer to the kernel level handle of the QP requested in argument 2.\r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_QP_HNDL: invalid QP handle\r
- *\r
- * Description:\r
- * Retrieve the kernel level handle of a QP in user level. Should be invoked in user level\r
- * to get a handle to be used by a kernel level code. This handle is valid only for special\r
- * verbs as described below. \r
- *\r
- * Note:\r
- * The kernel QP handle is passed to the kernel module by the application. It should use\r
- * some IOCTL path to this kernel module.\r
- *\r
- *************************************************************************/ \r
-\r
-VAPI_ret_t MT_API EVAPI_k_get_qp_hndl(\r
- /*IN*/ VAPI_hca_hndl_t hca_hndl,\r
- /*IN*/ VAPI_qp_hndl_t qp_ul_hndl,\r
- /*OUT*/ VAPI_k_qp_hndl_t *qp_kl_hndl);\r
-\r
-\r
-#ifdef __KERNEL__\r
-\r
-/* *************************************************************************\r
- * Function: EVAPI_k_modify_qp\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * qp_kl_hndl: QP kernel level handle.\r
- * qp_attr_p: Pointer to QP attributes to be modified.\r
- * qp_attr_mask_p: Pointer to the attributes mask to be modified.\r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_QP_HNDL: invalid QP handle\r
- * VAPI_EAGAIN: out of resources.\r
- * VAPI_EINVAL_QP_HNDL: invalid QP handle.\r
- * VAPI_ENOSYS_ATTR: QP attribute is not supported.\r
- * VAPI_EINVAL_ATTR: can not change QP attribute.\r
- * VAPI_EINVAL_PKEY_IX: PKey index out of range.\r
- * VAPI_EINVAL_PKEY_TBL_ENTRY: Pkey index points to an invalid entry in pkey table. \r
- * VAPI_EINVAL_QP_STATE: invalid QP state.\r
- * VAPI_EINVAL_RDD_HNDL: invalid RDD domain handle.\r
- * VAPI_EINVAL_MIG_STATE: invalid path migration state.\r
- * VAPI_E2BIG_MTU: MTU exceeds HCA port capabilities\r
- * VAPI_EINVAL_PORT: invalid port\r
- * VAPI_EINVAL_SERVICE_TYPE: invalid service type\r
- * VAPI_E2BIG_WR_NUM: maximum number of WR requested exceeds HCA capabilities\r
- * VAPI_EINVAL_RNR_NAK_TIMER: invalid RNR NAK timer value\r
- * VAPI_EPERM: not enough permissions.\r
- *\r
- * Description:\r
- * Modify QP state of the user level QP by using the kernel level QP handle.\r
- *\r
- * Note:\r
- * Supported only in kernel modules.\r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API EVAPI_k_modify_qp(\r
- /*IN*/ VAPI_hca_hndl_t hca_hndl,\r
- /*IN*/ VAPI_k_qp_hndl_t qp_kl_hndl,\r
- /*IN*/ VAPI_qp_attr_t *qp_attr_p,\r
- /*IN*/ VAPI_qp_attr_mask_t *qp_attr_mask_p\r
-);\r
-\r
-/**********************************************************\r
- * \r
- * Function: EVAPI_k_set_destroy_qp_cbk\r
- *\r
- * Arguments:\r
- * k_hca_hndl : HCA handle\r
- * k_qp_hndl: Kernel level QP handle as known from EVAPI_k_get_qp_hndl()\r
- * cbk_func: Callback function to invoke when the QP is destroyed\r
- * private_data: Caller's context to be used when invoking the callback\r
- *\r
- * Returns:\r
- * VIP_OK\r
- * VIP_EINVAL_HCA_HNDL : No such opened HCA.\r
- * VIP_EINVAL_QP_HNDL : No such QP\r
- * VAPI_EBUSY: A destroy_cq callback is already set for this QP\r
- * \r
- *\r
- * Description:\r
- * Set a callback function that notifies the caller (a kernel module that\r
- * uses EVAPI_k_set_comp_eventh ) when a QP is destroyed.\r
- * The function is meant to be used in order to clean the kernel module's\r
- * context for that resource.\r
- * This callback is implicitly cleared after it is called.\r
- *\r
- * Note: Only a single context in kernel may invoke this function per QP.\r
- * Simultanous invocation by more than one kernel context,\r
- * for the same QP, will result in unexpected behavior.\r
- *\r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_k_set_destroy_qp_cbk(\r
- IN VAPI_hca_hndl_t k_hca_hndl,\r
- IN VAPI_k_qp_hndl_t k_qp_hndl,\r
- IN EVAPI_destroy_qp_cbk_t cbk_func,\r
- IN void* private_data\r
-);\r
- \r
-/**********************************************************\r
- * \r
- * Function: EVAPI_k_clear_destroy_qp_cbk\r
- *\r
- * Arguments:\r
- * k_hca_hndl : HCA handle\r
- * k_qp_hndl: Kernel level QP handle as known from EVAPI_k_get_qp_hndl()\r
- *\r
- * Returns:\r
- * VIP_OK\r
- * VIP_EINVAL_HCA_HNDL : No such opened HCA.\r
- * VIP_EINVAL_QP_HNDL : No such QP.\r
- *\r
- * Description:\r
- * Clear the callback function set in EVAPI_k_set_destroy_qp_cbk().\r
- * Use this function when the kernel module stops using the given k_qp_hndl.\r
- *\r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_k_clear_destroy_qp_cbk(\r
- IN VAPI_hca_hndl_t k_hca_hndl,\r
- IN VAPI_k_qp_hndl_t k_qp_hndl\r
-);\r
- \r
-#endif /*__KERNEL__ */\r
-\r
-/**************************************************************************\r
- * Function: EVAPI_k_sync_qp_state\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * qp_ul_hndl: user level QP Handle.\r
- * curr_state: The state that should be synch to\r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_QP_HNDL: invalid QP handle\r
- *\r
- * Description:\r
- * This function synchronized the user level QP with a QP state which was modified \r
- * by kernel level agent (as returned from the kernel agent via it's IOCTL). \r
- *\r
- * Note:\r
- * Failing to synch the QP state correctly may result in unexpected behavior for \r
- * this QP as well as to other QPs which use the same CQ. There is no need \r
- * to synch upon each QP state change, but application must synch when going back to RESET, \r
- * and for any other state when user level application is going to use that QP in regard \r
- * to that new state (e.g., user level will not allow posting requests to the send \r
- * queue if it was not synch with a transition to RTS state).\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API EVAPI_k_sync_qp_state(\r
- /*IN*/ VAPI_hca_hndl_t hca_hndl,\r
- /*IN*/ VAPI_qp_hndl_t qp_ul_hndl,\r
- /*IN*/ VAPI_qp_state_t curr_state\r
-);\r
-\r
-/**************************************************************************\r
- * Function: EVAPI_alloc_map_devmem\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * mem_type: Type of attached device memory \r
- * bsize: Size in bytes of required memory buffer\r
- * align_shift: log2 of alignment requirement\r
- * note: in DDR: chunk should be aligned to its size\r
- * buf_p: Returned physical address of allocated buffer\r
- * virt_addr_p: pointer to virt. adrs mapped to phys adrs (if not NULL, io_remap is done).\r
- * dm_hndl: device memory handle\r
- \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_ENOSYS: Given memory type is not supported in given HCA device\r
- * VAPI_EAGAIN: Not enough resources (memory) to satisfy request\r
- * VAPI_EINVAL_PARAM: Invalid memory type or invalid alignment requirement\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- *\r
- * Description:\r
- * Allocate (and map) device attached memory resources (e.g. in InfiniHost's: attached DDR-SDRAM)\r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API EVAPI_alloc_map_devmem(\r
- VAPI_hca_hndl_t hca_hndl,\r
- EVAPI_devmem_type_t mem_type,\r
- VAPI_size_t bsize,\r
- u_int8_t align_shift, \r
- VAPI_phy_addr_t* buf_p,\r
- void** virt_addr_p,\r
- VAPI_devmem_hndl_t* dm_hndl\r
-\r
-);\r
-\r
-/**************************************************************************\r
- * Function: EVAPI_query_devmem\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * mem_type: Type of attached device memory \r
- * align shift\r
- * devmem_info_p: pointer to info structure\r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_ENOSYS: Given memory type is not supported in given HCA device\r
- * VAPI_EINVAL_PARAM: Invalid memory type or invalid alignment requirement\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- *\r
- * Description:\r
- * query device attached memory resources (e.g. in InfiniHost's attached DDR-SDRAM)\r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API EVAPI_query_devmem(\r
- /* IN */ VAPI_hca_hndl_t hca_hndl, \r
- /* IN */ EVAPI_devmem_type_t mem_type, \r
- u_int8_t align_shift,\r
- /* OUT */ EVAPI_devmem_info_t *devmem_info_p); \r
-\r
-\r
-/**************************************************************************\r
- * Function: EVAPI_free_unmap_devmem\r
- *\r
- * Arguments:\r
- * hca_hndl HCA Handle.\r
- * dm_hndl: device memory handle\r
- *\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_ENOSYS: Given memory type is not supported in given HCA device\r
- * VAPI_EINVAL_PARAM: Invalid memory type or invalid alignment requirement\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- *\r
- * Description:\r
- * Free device attached memory buffer allocated with EVAPI_alloc_devmem.\r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API EVAPI_free_unmap_devmem(\r
- VAPI_hca_hndl_t hca_hndl,\r
- VAPI_devmem_hndl_t dm_hndl\r
-);\r
-\r
-\r
-/*************************************************************************\r
- * Function: EVAPI_alloc_pd\r
- *\r
- * Arguments:\r
- * hca_hndl: Handle to HCA.\r
- * max_num_avs: max number of AVs which can be allocated for this PD\r
- * pd_hndl_p: Pointer to Handle to Protection Domain object.\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EAGAIN: not enough resources.\r
- * VAPI_EINVAL_PARAM : invalid parameter\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * This call is identical to VAPI_alloc_pd, except that the caller may specify the max \r
- * number of AVs which will be allocatable for this PD. If the system default value is\r
- * desired, the caller can specify EVAPI_DEFAULT_AVS_PER_PD for the requested_num_avs.\r
- *\r
- * Note that max_num_avs may not be zero. Furthermore, the minimum number of AVs allocated is\r
- * 2, so if you ask for only 1 AV as the max, the actual maximum will be 2. For all other values\r
- * (up to the maximum supported by the channel adapter) the maximum avs requested will be the\r
- * maximum avs obtained.\r
- * \r
- *************************************************************************/ \r
-VAPI_ret_t MT_API EVAPI_alloc_pd(\r
- /*IN*/ VAPI_hca_hndl_t hca_hndl,\r
- /*IN*/ u_int32_t max_num_avs, \r
- /*OUT*/ VAPI_pd_hndl_t *pd_hndl_p\r
- );\r
-\r
-/*************************************************************************\r
- * Function: EVAPI_alloc_pd_sqp\r
- *\r
- * Arguments:\r
- * hca_hndl: Handle to HCA.\r
- * max_num_avs: max number of AVs which can be allocated for this PD\r
- * pd_hndl_p: Pointer to Handle to Protection Domain object.\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EAGAIN: not enough resources.\r
- * VAPI_EINVAL_PARAM : invalid parameter\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * Description:\r
- * \r
- * This call is identical to EVAPI_alloc_pd, except that it should be used.\r
- * when allocating a protection domain for a special QP. If the caller wishes\r
- * that the default number of AVs be used for this PD, use EVAPI_DEFAULT_AVS_PER_PD\r
- * for the max_num_avs parameter. Using this function is highly recommended in order\r
- * to prevent reads from DDR and to enhance performance of special QPs\r
- *\r
- * Note that max_num_avs may not be zero.\r
- * \r
- *************************************************************************/ \r
-VAPI_ret_t MT_API EVAPI_alloc_pd_sqp(\r
- /*IN*/ VAPI_hca_hndl_t hca_hndl,\r
- /*IN*/ u_int32_t max_num_avs, \r
- /*OUT*/ VAPI_pd_hndl_t *pd_hndl_p\r
- );\r
-/**********************************************************\r
- * \r
- * Function: EVAPI_open_hca\r
- *\r
- * Arguments:\r
- * hca_id : HCA ID to open\r
- * profile_p : pointer to desired profile\r
- * sugg_profile_p : pointer to returned actual values, or suggested values when\r
- * a failure is due to parameter values that are too large.\r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EBUSY : This HCA has already been opened.\r
- * VAPI_EINVAL_PARAM : profile does not pass sanity checks\r
- * VAPI_EINVAL_HCA_ID : No such HCA.\r
- * VAPI_EAGAIN : Max number of supported HCAs on this host already open.\r
- * VAPI_ENOMEM: some of the parameter values provided in the profile are too large\r
- * in the case where the 'require' flag in the profile is set to TRUE.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (open device file, or ioctl) \r
- * has returned an error.\r
- *\r
- * Description:\r
- * Opens a registered HCA using the given profile. If profile is NULL, the default\r
- * (internal, compiled) profile is used. If the sugg_profile_p is NULL, no profile data\r
- * is returned.\r
- * \r
- * If sugg_profile_p is non-NULL:\r
- * If the open succeeds, the profile data with which the HCA was opened is returned. \r
- * If a profile structure was provided, and the require flag was false, these values \r
- * may be smaller than the ones provided in the profile.\r
- *\r
- * If the open fails with VAPI_ENOMEM, a suggested set of values is returned sugg_profile_p.\r
- * Otherwise the values given in profile_p (which may not be valid) are returned.\r
- *\r
- * In all cases, the returned value of the require flag is the value that was passed in \r
- * profile_p.\r
- *\r
- * 'require' flag in the EVAPI_hca_profile_t structure:\r
- * if this flag is set to FALSE, and the profile passes sanity checks, and the given\r
- * parameter values use too many Tavor resources, the driver will attempt to reduce the \r
- * given values until a set is found which does meet Tavor resource requirements. The HCA\r
- * will be opened using thes reduced set of values. The reduced set of values is returned \r
- * in the sugg_profile_p structure, if it is non-NULL.\r
- *\r
- * If the 'require' flag is set to TRUE, and the profile passes sanity checks, and the\r
- * given set of parameter values use too many Tavor resources, this function will return\r
- * VAPI_ENOMEM. If sugg_profile_p is non-NULL, a set of values will be returned in that\r
- * structure which can be used to successfully open the HCA.\r
- *\r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_open_hca(/*IN*/ VAPI_hca_id_t hca_id,\r
- /*IN*/ EVAPI_hca_profile_t *profile_p,\r
- /*OUT*/ EVAPI_hca_profile_t *sugg_profile_p\r
- );\r
-\r
-/**********************************************************\r
- * \r
- * Function: EVAPI_close_hca\r
- *\r
- * Arguments:\r
- * hca_id : HCA ID to close\r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_ID : No such HCA.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- *\r
- * Description:\r
- * closes an open HCA. This procedure is meant for administrative use only.\r
- * User Level Apps should use EVAPI_release_hca_handle.\r
- *\r
- **********************************************************/\r
-VAPI_ret_t MT_API EVAPI_close_hca(\r
- /*IN*/ VAPI_hca_id_t hca_id\r
- );\r
-\r
-\r
-/***********************************************************************\r
- * Asynchronous events functions\r
- ***********************************************************************/\r
-\r
-/*************************************************************************\r
- * Function: EVAPI_set_async_event_handler\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA Handle \r
- * handler: Async Event Handler function address.\r
- * private_data: Pointer to handler context (handler specific).\r
- * async_handler_hndl: The handle to the registered handler function. Used in the clear function.\r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_PARAM: handler given is NULL\r
- * VAPI_EAGAIN: No enough system resources (e.g. memory)\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- *\r
- * Description:\r
- * \r
- * Registers an asynch event handler to get all asynch events for this process. (affiliated and non-affiliated)\r
- * Notes: \r
- * 1. All non affiliated events are being "broadcast" to all registered handlers. \r
- * 2. Affiliated events will be send only to the callback of the process that the resources (e.g. QP) are belong to. \r
- * However, all kernel modules are treated as one process thus all of them will get all affiliated events of all \r
- * kernel modules.\r
- * 3. Multiple registration of handlers is allowed.\r
- *\r
- * The event handler function prototype is as follows:\r
- * \r
- * void\r
- * VAPI_async_event_handler\r
- * (\r
- * IN VAPI_hca_hndl_t hca_hndl,\r
- * IN VAPI_event_record_t *event_record_p,\r
- * IN void *private_data\r
- * )\r
- * \r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
- \r
-VAPI_ret_t MT_API EVAPI_set_async_event_handler(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_async_event_handler_t handler,\r
- IN void* private_data,\r
- OUT EVAPI_async_handler_hndl_t *async_handler_hndl_p\r
- );\r
-\r
-\r
-/**********************************************************\r
- * \r
- * Function: EVAPI_clear_async_event_handler\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA Handle \r
- * async_handler_hndl: The handle to the registered handler function.\r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_PARAM: invalid async_handler_hndl\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- *\r
- * Description:\r
- * Function which clears a previously registered by EVAPI_set_async_event_handler. \r
- * This function must be called before calling to EVAPI_release_hca_hndl\r
- *\r
- ***********************************************************/\r
-\r
-\r
-VAPI_ret_t MT_API EVAPI_clear_async_event_handler(\r
- /*IN*/ VAPI_hca_hndl_t hca_hndl, \r
- /*IN*/ EVAPI_async_handler_hndl_t async_handler_hndl);\r
-\r
-\r
-\r
-\r
-/**********************************************************\r
- * \r
- * Function: EVAPI_register_thread\r
- *\r
- * Arguments:\r
- *\r
- * Returns:\r
- * VIP_OK success\r
- * VIP_EAGAIN not enough resources\r
- * VIP_ERROR error registering signals\r
- *\r
- * Description:\r
- * This function register the thread in a data structure so that\r
- * when forking all these threads are stopped until all fork\r
- * support actions are carried out.\r
- *\r
- ***********************************************************/\r
-VAPI_ret_t EVAPI_register_thread(void);\r
-\r
-\r
-/**********************************************************\r
- * \r
- * Function: EVAPI_deregister_thread\r
- *\r
- * Arguments:\r
- * pid(in) The pid of the thread to be registered\r
- *\r
- * Returns:\r
- * VIP_OK pid was succesfully deregistered\r
- * VIP_EINVAL_PARAM pid not found\r
- *\r
- ***********************************************************/\r
-VAPI_ret_t EVAPI_deregister_thread(void);\r
-\r
-#if defined(MT_SUSPEND_QP)\r
-/* *************************************************************************\r
- * Function: EVAPI_suspend_qp\r
- *\r
- * Arguments:\r
- * 1) hca_hndl : HCA Handle.\r
- * 2) qp_ul_hndl: user level QP Handle.\r
- * 3) suspend_flag: TRUE--suspend, FALSE--unsuspend\r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_QP_HNDL: invalid QP handle\r
- * VAPI_EINVAL_QP_STATE: QP is in RESET or INIT state for suspend, \r
- * not in SUSPEND state for unsuspend \r
- * VAPI_EAGAIN: QP is currently executing another command (busy)\r
- * VAPI_ENOSYS: Operation not supported on channel adapter\r
- * VAPI_EINTR Could not grab qp-modification mutex\r
- * VAPI_EGEN: operation failed (internal error)\r
- *\r
- * Description:\r
- * suspend_flag = TRUE:\r
- * Suspends operation of the given QP (i.e., places it in the SUSPENDED state).\r
- * The operation is valid only if the QP is currently NOT in RESET state,\r
- * and NOT in INIT state.\r
- *\r
- * suspend_flag = FALSE:\r
- * Transitions the given QP from the SUSPENDED to the state it was in \r
- * when suspended.\r
- *\r
- *************************************************************************/ \r
-\r
-VAPI_ret_t EVAPI_suspend_qp(\r
- /*IN*/ VAPI_hca_hndl_t hca_hndl,\r
- /*IN*/ VAPI_qp_hndl_t qp_ul_hndl,\r
- /*IN*/ MT_bool suspend_flag);\r
-\r
-/* *************************************************************************\r
- * Function: EVAPI_suspend_CQ\r
- *\r
- * Arguments:\r
- * 1) hca_hndl : HCA Handle.\r
- * 2) qp_ul_hndl: user level CQ Handle.\r
- * 3) do_suspend: TRUE--suspend, FALSE--unsuspend\r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_CQ_HNDL: invalid QP handle\r
- * VAPI_EAGAIN: QP is currently executing another command (busy)\r
- * VAPI_EGEN: operation failed (internal error)\r
- *\r
- * Description:\r
- * do_suspend = TRUE:\r
- * releases locking of CQ cookies region.\r
- *\r
- * do_suspend = FALSE:\r
- * Locks the CQE internal mr again.\r
- *\r
- * NOTE: NO safety checks are performed. If there is an unsuspended QP which is\r
- * currently using the cq, the results are not predictable (but will NOT be\r
- * good).\r
- *\r
- *************************************************************************/ \r
-\r
-VAPI_ret_t EVAPI_suspend_cq(\r
- /*IN*/ VAPI_hca_hndl_t hca_hndl,\r
- /*IN*/ VAPI_cq_hndl_t cq_ul_hndl,\r
- /*IN*/ MT_bool do_suspend);\r
-#endif\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_VAPI_H\r
-#define H_VAPI_H\r
-\r
-#include <mtl_common.h>\r
-#include <vapi_types.h>\r
-#include <evapi.h>\r
-#include <vapi_features.h>\r
-\r
-\r
-/********************************************************************************************\r
- * VAPI Calls Declarations\r
- *\r
- *\r
- ********************************************************************************************/\r
-\r
-/*******************************************\r
- * 11.2.1 HCA\r
- *\r
- *******************************************/\r
-/*************************************************************************\r
- * Function: VAPI_open_hca\r
- *\r
- * Arguments:\r
- * hca_id: HCA identifier.\r
- * hca_hndl_p: Pointer to the HCA object handle.\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EAGAIN: not enough resources.\r
- * VAPI_EINVAL_HCA_ID: invalid HCA identifier.\r
- * VAPI_EBUSY: HCA already in use\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (open device file, or ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * Creates a new HCA Object.\r
- * \r
- * The creation of an HCA Object will call HH_get_dev_prop in order to find out the \r
- * device capabilities and so allocate enough resource.\r
- * \r
- * After the resource allocation is completed a call to HH_open_hca will be made in order \r
- * to prepare the device for consumer use.\r
- * This call will also create and CIO (Channel Interface Object) which is a container for \r
- * any object related to the opened HCA.\r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_open_hca(\r
- IN VAPI_hca_id_t hca_id,\r
- OUT VAPI_hca_hndl_t *hca_hndl_p\r
- ); \r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_query_hca_cap\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA object handle.\r
- * hca_vendor_p: Pointer to HCA vendor specific information object.\r
- * hca_cap_p: Pointer to HCA capabilities object\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EAGAIN: not enough resources.\r
- * VAPI_EPERM: not enough permissions. \r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * Query HCA capabilities retrieves a structure of type VAPI_hca_vendor_t providing a \r
- * list of the vendor specific information about the HCA, and a structure of type \r
- * VAPI_hca_cap_t providing a detailed list of the HCA capabilities. Further informtion \r
- * on the hca ports can be retrieved using the verb VAPI_query_hca_port_prop and \r
- * VAPI_query_hca_port_tbl.\r
- * \r
- * \r
- * This used to be AV, but it should be Add Handl\r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_query_hca_cap(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- OUT VAPI_hca_vendor_t *hca_vendor_p,\r
- OUT VAPI_hca_cap_t *hca_cap_p\r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_query_hca_port_prop\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA object handle.\r
- * port_num: Port number\r
- * hca_port_p: HCA port object describing the port properties.\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EINVAL_PORT: invalid port number\r
- * VAPI_EAGAIN: not enough resources.\r
- * VAPI_EPERM: not enough permissions. \r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * Query HCA port properties retrieves a structure of type VAPI_hca_port_t for the port \r
- * specified in port_num. The number of the HCA physical ports ca be obtained using the \r
- * verb VAPI_query_hca_cap. Further information about the port p-key table and gid \r
- * table can be obtained using the verb VAPI_query_hca_port_tbl.\r
- * \r
- * Upon successful completion, the verb returns in hca_port_p structure of type \r
- * VAPI_hca_port_t, which is described in the following table:\r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_query_hca_port_prop(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN IB_port_t port_num,\r
- OUT VAPI_hca_port_t *hca_port_p /* set to NULL if not interested */\r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_query_hca_gid_tbl\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA object handle.\r
- * port_num: Port number\r
- * tbl_len_in: Number of entries in given gid_tbl_p buffer.\r
- * tbl_len_out: Actual number of entries in this port GID table\r
- * gid_tbl_p: The GID table buffer to return result in.\r
- * \r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EINVAL_PORT: invalid port number\r
- * VAPI_EAGAIN: tbl_len_out > tbl_len_in.\r
- * VAPI_EINVAL_PARAM: .invalid port number. \r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * GID table of given port in returned in gid_tbl_p.\r
- * If tbl_len_out (actual number of entries) is more than tbl_len_in, the function should be \r
- * called again with a larger buffer.\r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_query_hca_gid_tbl(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN IB_port_t port_num,\r
- IN u_int16_t tbl_len_in,\r
- OUT u_int16_t *tbl_len_out,\r
- OUT IB_gid_t *gid_tbl_p \r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_query_hca_pkey_tbl\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA object handle.\r
- * port_num: Port number\r
- * tbl_len_in: Number of entries in given pkey_tbl_p buffer.\r
- * tbl_len_out: Actual number of entries in this port PKEY table\r
- * pkey_tbl_p: The PKEY table buffer to return result in.\r
- * \r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EINVAL_PORT: invalid port number\r
- * VAPI_EAGAIN: tbl_len_out > tbl_len_in.\r
- * VAPI_EINVAL_PARAM: .invalid port number. \r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * * Description:\r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_query_hca_pkey_tbl(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN IB_port_t port_num,\r
- IN u_int16_t tbl_len_in,\r
- OUT u_int16_t *tbl_len_out,\r
- OUT VAPI_pkey_t *pkey_tbl_p\r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_modify_hca_attr \r
- *\r
- * Arguments:\r
- * hca_hndl: Handle to HCA.\r
- * port_num: Port number\r
- * hca_attr_p: Pointer to the HCA attributes structure\r
- * hca_attr_mask_p: Pointer to the HCA attributes mask\r
- * \r
- * \r
- * Returns: VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EINVAL_PORT: Invalid port number\r
- * VAPI_EAGAIN: failed on resource allocation\r
- * VAPI_EGEN: function called not from user level context\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- *\r
- * Description:\r
- * \r
- * Sets the HCA attributes specified in hca_attr_p to port number port_num. Only the \r
- * values specified in hca_attr_mask_p are being modified. hca_attr_p is a pointer to a \r
- * structure of type VAPI_hca_attr_t, which is specified in the following table:\r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_modify_hca_attr(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN IB_port_t port_num,\r
- IN VAPI_hca_attr_t *hca_attr_p,\r
- IN VAPI_hca_attr_mask_t *hca_attr_mask_p\r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_close_hca \r
- *\r
- * Arguments:\r
- * hca_hndl: Handle to HCA.\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * This call will deallocate all the structures allocated during the called to \r
- * VAPI_open_hca and any other resource in the domain of the CI. \r
- * \r
- * It is the responsibility of the consumers to free resources allocated for the HCA that are \r
- * under its scope.\r
- * \r
- * VAPI will call HH_VClose_HCA in order to instruct the device to stop processing new \r
- * requests and close in-process ones. This will be done before releasing any resource \r
- * belonging to the CI.\r
- * \r
- * \r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_close_hca(\r
- IN VAPI_hca_hndl_t hca_hndl\r
- );\r
-\r
-\r
-/* Protection Domain Verbs */\r
-\r
-/*************************************************************************\r
- * Function: VAPI_alloc_pd\r
- *\r
- * Arguments:\r
- * hca_hndl: Handle to HCA.\r
- * pd_hndl_p: Pointer to Handle to Protection Domain object.\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EAGAIN: not enough resources.\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * This call register a new protection domain by calling VIP_Register_PD. Into the VIP \r
- * layer it is the responsibility of the PDA to keep track of the different Protection \r
- * Domains and the object associated to it.\r
- * \r
- * After registering the new allocated PD in the PDA. The VIP will call HH_register_PD. \r
- * Some HCA HW implementation do not keep track of any Protection Domain Object \r
- * internally turning the call to HH_register_PD into a dummy call.\r
- * \r
- * \r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_alloc_pd(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- OUT VAPI_pd_hndl_t *pd_hndl_p\r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_dealloc_pd\r
- *\r
- * Arguments:\r
- * hca_hndl: Handle to HCA.\r
- * pd_hndl: Handle to Protection Domain Object.\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: Invalid HCA handle.\r
- * VAPI_EINVAL_PD_HNDL: Invalid Protection Domain\r
- * VAPI_EBUSY: Protection Domain in use.\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * Deregister the Protection Domain from the PDA. The PDA is responsible to validate \r
- * that there are no objects associated to the Protection Domain being deallocated.\r
- * \r
- * After deregistering the allocated PD from the PDA the VIP will call \r
- * HH_deregister_PD. Some HCA HW implementation do not keep track of any Protec-\r
- * tion Domain Object internally turning the call to HH_deregister_PD into a dummy call.\r
- * \r
- * \r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_dealloc_pd(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_pd_hndl_t pd_hndl\r
- );\r
-\r
-\r
-/* RD Are not supported at this rev */\r
-#if 0\r
-\r
-/* Reliable Datagram Domain Verbs */\r
-\r
-/*************************************************************************\r
- * Function: VAPI_alloc_rdd\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA Handle.\r
- * rdd_hndl_p: Pointer to Reliable Datagram Domain object handle.\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EAGAIN: out of resources.\r
- * VAPI_EINVAL_RD_UNSUPPORTED: RD is not supported\r
- * VAPI_EPERM: not enough permissions.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * Allocates an RD domain\r
- * \r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_alloc_rdd (\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- OUT VAPI_rdd_hndl_t *rdd_hndl_p\r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_dealloc_rdd\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA Handle.\r
- * rdd_hndl : Reliable Datagram Domain object handle.\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EAGAIN: out of resources.\r
- * VAPI_EINVAL_RD_UNSUPPORTED: RD is not supported\r
- * VAPI_EPERM: not enough permissions.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * DeAllocates an RD domain\r
- * \r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_dealloc_rdd(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_rdd_hndl_t rdd_hndl\r
- );\r
-#endif\r
-\r
-/*******************************************\r
- * 11.2.2 Address Management Verbs\r
- *\r
- *******************************************/\r
- /*************************************************************************\r
- * Function: VAPI_create_addr_hndl \r
- *\r
- * Arguments:\r
- * hca_hndl: Handle to HCA.\r
- * pd_hndl: Protection domain handle \r
- * av_p: Pointer to Address Vector structure.\r
- * av_hndl_p: Handle of Address Vector.\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: Invalid HCA handle.\r
- * VAPI_EINVAL_PD_HNDL: Invalid Protection Domain handle.\r
- * VAPI_EAGAIN: Not enough resources.\r
- * VAPI_EPERM: Not enough permissions.\r
- * VAPI_EINVAL_PARAM: Invalid parameter\r
- * VAPI_EINVAL_PORT: Invalid port number\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * Creates a new Address Vector Handle that can be used later when posting a WR to a \r
- * UD QP.\r
- * The AVL (Address Vector Library) does the accounting of the different Address Vec-\r
- * tor the user creates, and responses to the JOD when the last posts descriptors to the \r
- * device. The fields of the address vector are specified in the following table:\r
- * \r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_create_addr_hndl(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_pd_hndl_t pd_hndl,\r
- IN VAPI_ud_av_t *av_p,\r
- OUT VAPI_ud_av_hndl_t *av_hndl_p\r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_modify_addr_hndl \r
- *\r
- * Arguments:\r
- * hca_hndl: Handle to HCA. \r
- * av_hndl : Handle of Address Vector Handle\r
- * av_p: Pointer to Address Vector structure. \r
- * \r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK \r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EINVAL_AV_HNDL: invalid Address Vector handle.\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_EINVAL_PORT: Invalid port number\r
- * \r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * Modify existent address vector handle to a new address vector. For address vector \r
- * fields, refer to Table 6, \93VAPI_av_t,\94 on page 20.\r
- * \r
- * \r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_modify_addr_hndl(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_ud_av_hndl_t av_hndl,\r
- IN VAPI_ud_av_t *av_p\r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_query_addr_hndl \r
- *\r
- * Arguments:\r
- * hca_hndl: Handle to HCA. \r
- * av_hndl : Handle of Address Vector \r
- * av_p: Pointer to Address Vector structure. \r
- * \r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK \r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EINVAL_AV_HNDL: invalid address vector handle.\r
- * VAPI_EPERM: not enough permission.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * Returns pointer to ADDR_VECP with information of the UD Address Vector repre-\r
- * sented by AddrVecHandle. For address vector fields, refer to Table 6, \93VAPI_av_t,\94 on \r
- * page 20.\r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_query_addr_hndl(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_ud_av_hndl_t av_hndl,\r
- OUT VAPI_ud_av_t *av_p\r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_destroy_addr_hndl \r
- *\r
- * Arguments:\r
- * hca_hndl: Handle to HCA. \r
- * av_hndl : Handle of Address Vector \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK \r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EINVAL_AV_HNDL: invalid address vector handle.\r
- * VAPI_EPERM: not enough permission.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * Removes address handle.\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_destroy_addr_hndl(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_ud_av_hndl_t av_hndl\r
- );\r
-\r
-\r
-/*******************************************\r
- * 11.2.3 Queue Pair\r
- *\r
- *******************************************/\r
-\r
- /*************************************************************************\r
- * Function: VAPI_create_qp \r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * qp_init_attr_p: Pointer to QP attribute to used for initialization.\r
- * qp_hndl_p: Pointer to returned QP Handle number.\r
- * qp_prop_p: Pointer to properties of created QP.\r
- * \r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EAGAIN: not enough resources.\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EINVAL_CQ_HNDL: invalid CQ handle.\r
- * VAPI_E2BIG_WR_NUM: number of WR exceeds HCA cap.\r
- * VAPI_E2BIG_SG_NUM: number of SG exceeds HCA cap.\r
- * VAPI_EINVAL_PD_HNDL: invalid protection domain handle.\r
- * VAPI_EINVAL_SERVICE_TYPE: invalid service type for this QP.\r
- * VAPI_EINVAL_RDD: Invalid RD domain handle.\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- *\r
- * Description:\r
- * Create a QP resource (in the reset state).\r
- * \r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_create_qp(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_qp_init_attr_t *qp_init_attr_p,\r
- OUT VAPI_qp_hndl_t *qp_hndl_p,\r
- OUT VAPI_qp_prop_t *qp_prop_p\r
- );\r
-\r
- /*************************************************************************\r
- * Function: VAPI_create_qp_ext \r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * qp_init_attr_p: Pointer to QP attribute to used for initialization.\r
- * qp_ext_attr_p: Extended QP attributes (take care to init. with VAPI_QP_INIT_ATTR_EXT_T_INIT)\r
- * qp_hndl_p: Pointer to returned QP Handle number.\r
- * qp_prop_p: Pointer to properties of created QP.\r
- * \r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EAGAIN: not enough resources.\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EINVAL_CQ_HNDL: invalid CQ handle.\r
- * VAPI_EINVAL_SRQ_HNDL: Given SRQ handle does not exist (when srq_handle!=VAPI_SRQ_INVAL_HNDL)\r
- * VAPI_EINVAL_PD_HNDL: invalid protection domain handle \r
- * OR (When SRQ is associated with this QP and HCA requires SRQ's PD to be as QP's) \r
- * Given PD is different than associated SRQ's.\r
- * VAPI_E2BIG_WR_NUM: number of WR exceeds HCA cap.\r
- * VAPI_E2BIG_SG_NUM: number of SG exceeds HCA cap.\r
- * VAPI_EINVAL_SERVICE_TYPE: invalid service type for this QP.\r
- * VAPI_EINVAL_RDD: Invalid RD domain handle.\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * Description:\r
- * Create a QP resource in the reset state - extended version.\r
- * \r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_create_qp_ext(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_qp_init_attr_t *qp_init_attr_p,\r
- IN VAPI_qp_init_attr_ext_t *qp_ext_attr_p,\r
- OUT VAPI_qp_hndl_t *qp_hndl_p,\r
- OUT VAPI_qp_prop_t *qp_prop_p\r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_modify_qp \r
- *\r
- * Arguments:\r
- * hca_hndl: HCA handle.\r
- * qp_hndl: QP handle\r
- * qp_attr_p: Pointer to QP attributes to be modified.\r
- * qp_attr_mask_p: Pointer to the attributes mask to be modified.\r
- * qp_cap_p: Pointer to QP actual capabilities returned.\r
- * \r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EAGAIN: out of resources.\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EINVAL_QP_HNDL: invalid QP handle.\r
- * VAPI_ENOSYS_ATTR: QP attribute is not supported.\r
- * VAPI_EINVAL_ATTR: can not change QP attribute.\r
- * VAPI_EINVAL_PKEY_IX: PKey index out of range.\r
- * VAPI_EINVAL_PKEY_TBL_ENTRY: Pkey index points to an invalid entry in pkey table. \r
- * VAPI_EINVAL_QP_STATE: invalid QP state.\r
- * VAPI_EINVAL_RDD_HNDL: invalid RDD domain handle.\r
- * VAPI_EINVAL_MIG_STATE: invalid path migration state.\r
- * VAPI_EINVAL_MTU: MTU exceeds HCA port capabilities\r
- * VAPI_EINVAL_PORT: invalid port\r
- * VAPI_EINVAL_SERVICE_TYPE: invalid service type\r
- * VAPI_E2BIG_WR_NUM: maximum number of WR requested exceeds HCA capabilities\r
- * VAPI_EINVAL_RNR_NAK_TIMER: invalid RNR NAK timer value\r
- * VAPI_EINVAL_LOCAL_ACK_TIMEOUT: invalid Local ACK timeout value (either primary or alt)\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * Modify the QP attributes and transition into a new state. Note that only a subset of all \r
- * the attributes can be modified in during a certain transition into a QP state. The \r
- * qp_attr_mask_p specifies the actual attributes to be modified. \r
- * \r
- * The QP attributes specified are of type VAPI_qp_attr_t and are specified in the follow-\r
- * ing table:\r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_modify_qp(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_qp_hndl_t qp_hndl,\r
- IN VAPI_qp_attr_t *qp_attr_p,\r
- IN VAPI_qp_attr_mask_t *qp_attr_mask_p,\r
- OUT VAPI_qp_cap_t *qp_cap_p\r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_query_qp\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA Handle.\r
- * qp_hndl: QP Handle.\r
- * qp_attr_p: Pointer to QP attributes. \r
- * qp_attr_mask_p: Pointer to QP attributes mask. \r
- * qp_init_attr_p: Pointer to init attributes\r
- * \r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EINVAL_QP_HNDL: invalid QP handle.\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- *\r
- * Description:\r
- * \r
- * Returns a VAPI_qp_attr_t structure to the application with all the relevant information \r
- * that applies to the QP matching qp_hndl.\r
- * Note that only the relevant fields in qp_attr_p and qp_init_attr_p are valid. The valid \r
- * fields in qp_attr_p are marked in the mask returned by qp_attr_mask_p.\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_query_qp(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_qp_hndl_t qp_hndl,\r
- OUT VAPI_qp_attr_t *qp_attr_p,\r
- OUT VAPI_qp_attr_mask_t *qp_attr_mask_p,\r
- OUT VAPI_qp_init_attr_t *qp_init_attr_p\r
- );\r
-\r
-/*************************************************************************\r
- * Function: VAPI_query_qp_ext\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA Handle.\r
- * qp_hndl: QP Handle.\r
- * qp_attr_p: Pointer to QP attributes. \r
- * qp_attr_mask_p: Pointer to QP attributes mask. \r
- * qp_init_attr_p: Pointer to init attributes\r
- * qp_init_attr_ext_p: Pointer to extended init attributes\r
- * \r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EINVAL_QP_HNDL: invalid QP handle.\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- *\r
- * Description:\r
- * Same as VAPI_query_qp() but includes extended init. attributes.\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_query_qp_ext( \r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_qp_hndl_t qp_hndl,\r
- OUT VAPI_qp_attr_t *qp_attr_p,\r
- OUT VAPI_qp_attr_mask_t *qp_attr_mask_p,\r
- OUT VAPI_qp_init_attr_t *qp_init_attr_p,\r
- OUT VAPI_qp_init_attr_ext_t *qp_init_attr_ext_p\r
- );\r
-\r
-/*************************************************************************\r
- * Function: VAPI_destroy_qp\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA Handle.\r
- * qp_hndl: QP Handle.\r
- * \r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EINVAL_QP_HNDL: invalid QP handle.\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_EBUSY: QP is in use\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- *\r
- * Description:\r
- * releases all resources allocated by the CI to the qp\r
-\r
- *************************************************************************/\r
- VAPI_ret_t MT_API VAPI_destroy_qp(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_qp_hndl_t qp_hndl\r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_get_special_qp\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA Handle.\r
- * port: Physical port (valid only for QP0 and QP1\r
- * qp: the qp type\r
- * qp_init_attr_p: pointer to init attribute struct.\r
- * qp_hndl: QP Handle.\r
- * qp_cap_p: pointer to qp capabilities struct \r
- *\r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EINVAL_QP_HNDL: invalid QP handle.\r
- * VAPI_EINVAL_PORT: invalid port\r
- * VAPI_EINVAL_PD_HNDL: invalid PD\r
- * VAPI_EINVAL_CQ_HNDL: invalid CQ\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_EAGAIN: not enough resources\r
- * VAPI_EGEN: general error\r
- * VAPI_EINVAL_PARAM : invalid parameter\r
- * VAPI_EBUSY: resource is busy/in-use\r
- * VAPI_ENOSYS: not supported (legacy mode only)\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- *\r
- * Description: this call creates a special qp that can generate MADs, \r
- * RAW IPV6 or ethertype packets\r
- * \r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_get_special_qp(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN IB_port_t port,\r
- IN VAPI_special_qp_t qp,\r
- IN VAPI_qp_init_attr_t *qp_init_attr_p,\r
- OUT VAPI_qp_hndl_t *qp_hndl_p,\r
- OUT VAPI_qp_cap_t *qp_cap_p\r
- );\r
-\r
-\r
-\r
-/*******************************************\r
- * Shared Receive Queue (SRQ)\r
- *\r
- *******************************************/\r
-/*************************************************************************\r
- * Function: VAPI_create_srq \r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * srq_attr_p : Requested SRQ's attributes\r
- * srq_hndl_p : Returned SRQ handle\r
- * actual_attr_p : Actual SRQ attributes \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EINVAL_PD_HNDL: invalid protection domain handle.\r
- * VAPI_E2BIG_WR_NUM: max_outs_wr exceeds HCA cap.\r
- * VAPI_E2BIG_SG_NUM: max_sentries exceeds HCA cap.\r
- * VAPI_EAGAIN: not enough resources.\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: Kernel trap (IOCTL/system-call) failure.\r
- * VAPI_ENOSYS: HCA does not support SRQs\r
- * \r
- * Description:\r
- * Create a shared RQ with given attributes.\r
- * \r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_create_srq(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_srq_attr_t *srq_props_p,\r
- OUT VAPI_srq_hndl_t *srq_hndl_p,\r
- OUT VAPI_srq_attr_t *actual_srq_props_p\r
- );\r
- \r
-\r
-/*************************************************************************\r
- * Function: VAPI_query_srq \r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * srq_hndl : SRQ to query\r
- * srq_attr_p : Returned SRQ attributes\r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EINVAL_SRQ_HNDL: invalid SRQ handle.\r
- * VAPI_ESRQ: SRQ in error state\r
- * VAPI_ESYSCALL: Kernel trap (IOCTL/system-call) failure.\r
- * VAPI_ENOSYS: HCA does not support SRQs\r
- * \r
- * Description:\r
- * Query a shared RQ.\r
- * \r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_query_srq(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_srq_hndl_t srq_hndl,\r
- OUT VAPI_srq_attr_t *srq_attr_p\r
- );\r
- \r
-\r
-/*************************************************************************\r
- * Function: VAPI_modify_srq\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * srq_hndl : SRQ to modify\r
- * srq_attr_p : Requested SRQ's new attributes\r
- * srq_attr_mask : Mask of valid attributes in *srq_attr_p (attr. to modify)\r
- * actual_attr_p : Actual SRQ attributes \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EINVAL_SRQ_HNDL: invalid SRQ handle.\r
- * VAPI_E2BIG_WR_NUM: max_outs_wr exceeds HCA cap. \r
- * OR smaller than number of currently outstanding WQEs\r
- * VAPI_E2BIG_SRQ_LIMIT : Requested SRQ limit is larger than actual new size \r
- * VAPI_ESRQ: SRQ in error state\r
- * VAPI_EAGAIN: not enough resources.\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: Kernel trap (IOCTL/system-call) failure.\r
- * VAPI_ENOSYS: HCA does not support requested SRQ modifications.\r
- * \r
- * Description:\r
- * Modify a shared RQ with given attributes.\r
- * \r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_modify_srq(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_srq_hndl_t srq_hndl,\r
- IN VAPI_srq_attr_t *srq_attr_p,\r
- IN VAPI_srq_attr_mask_t srq_attr_mask,\r
- OUT u_int32_t *max_outs_wr_p \r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_destroy_srq \r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * srq_hndl : SRQ to destroy\r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle.\r
- * VAPI_EINVAL_SRQ_HNDL: invalid SRQ handle.\r
- * VAPI_EBUSY: SRQ still has QPs associated with it.\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: Kernel trap (IOCTL/system-call) failure.\r
- * VAPI_ENOSYS: HCA does not support SRQs\r
- * \r
- * Description:\r
- * Destroy a shared RQ.\r
- * \r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_destroy_srq(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_srq_hndl_t srq_hndl\r
- );\r
-\r
-\r
-/************************************************************************\r
- * Function: VAPI_post_srq\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * srq_hndl : SRQ Handle.\r
- * rwqe_num : Number of posted receive WQEs\r
- * rwqe_array: Pointer to an array of rwqe_num receive work requests.\r
- * rwqe_posted_p: Returned actual number of posted WQEs.\r
- * \r
- * returns: \r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_SRQ_HNDL: invalid SRQ handle\r
- * VAPI_E2BIG_WR_NUM: Too many posted work requests.\r
- * VAPI_EINVAL_SG_NUM: invalid scatter list length\r
- * VAPI_EINVAL_OP: invalid operation\r
- * VAPI_EPERM: not enough permissions.\r
- * \r
- * Description:\r
- * Post a receive request descriptor to the shared receive queue.\r
- * An error refers only to the first WQE that was not posted (index *rwqe_posted_p).\r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_post_srq(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_srq_hndl_t srq_hndl,\r
- IN u_int32_t rwqe_num,\r
- IN VAPI_rr_desc_t *rwqe_array,\r
- OUT u_int32_t *rwqe_posted_p);\r
-\r
-\r
-\r
-\r
-/*******************************************\r
- * 11.2.5 Compeletion Queue\r
- *\r
- *******************************************/\r
-/*************************************************************************\r
- * Function: VAPI_create_cq\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA Handle.\r
- * cqe_num: Minimum required number of entries in CQ.\r
- * cq_hndl_p: Pointer to the created CQ handle\r
- * num_of_entries_p: Actual number of entries in CQ\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EAGAIN: out of resources\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_E2BIG_CQ_NUM: number of entries in CQ exceeds HCA \r
- * capabilities \r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * Allocate the required data structures for the administration of a completion queue \r
- * including completion queue buffer space which has to be large enough to be adequate to \r
- * the maximum number of entries in the completion.\r
- * \r
- * Completion queue entries are accessed directly by the application.\r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_create_cq(\r
- IN VAPI_hca_hndl_t hca_hndl, \r
- IN VAPI_cqe_num_t cqe_num,\r
- OUT VAPI_cq_hndl_t *cq_hndl_p,\r
- OUT VAPI_cqe_num_t *num_of_entries_p\r
- ); \r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_query_cq\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA handle.\r
- * cq_hndl: Completion Queue Handle.\r
- * num_of_entries_p: Pointer to actual number of entries in CQ.\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_CQ_HNDL: invalid CQ handle. \r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * Retrieves the number of entries in the CQ.\r
- * \r
- * \r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_query_cq(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_cq_hndl_t cq_hndl,\r
- OUT VAPI_cqe_num_t *num_of_entries_p\r
- ); \r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_resize_cq\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA Handle.\r
- * cq_hndl: CQ Handle.\r
- * cqe_num: Minimum entries required in resized CQ.\r
- * num_of_entries_p: Pointer to actual number of entries in resized CQ.\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EAGAIN: out of resources\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_CQ_HNDL: invalid CQ handle or the given CQ is in invalid state to resize (CQ error). \r
- * VAPI_E2BIG_CQ_NUM: number of entries in CQ exceeds HCA \r
- * capabilities or number of currently outstanding entries \r
- * in CQ exceeds required size. \r
- * VAPI_EBUSY: Another VAPI_resize_cq invocation for the same CQ is in progress\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- *\r
- * Description:\r
- * Resize given CQ.\r
- * Number of curretly outstanding CQEs in the CQ should be no more than the size of the new CQ.\r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_resize_cq(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_cq_hndl_t cq_hndl,\r
- IN VAPI_cqe_num_t cqe_num,\r
- OUT VAPI_cqe_num_t *num_of_entries_p\r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_destroy_cq\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA Handle.\r
- * cq_hndl: CQ Handle.\r
- *\r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_CQ_HNDL: invalid CQ handle. \r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_EBUSY.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- *\r
- * Description:\r
- * destroys cq and releases all resources associated to it. \r
- *\r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_destroy_cq(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_cq_hndl_t cq_hndl\r
- );\r
-\r
-\r
-\r
-/*******************************************\r
- * 11.2.6 EE Context\r
- *\r
- *******************************************/\r
-/************ EEC is not supported on this revision ********************/\r
-#if 0\r
-\r
-/*************************************************************************\r
- * Function: VAPI_create_eec\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA Handle. \r
- * rdd: RD domain.\r
- * eec_hndl_p: Pointer to EE returned Context Handle. \r
- * \r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EAGAIN: out of resources\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle \r
- * VAPI_EPERM: not enough permissions.\r
- * \r
- * \r
- *\r
- * Description: creates an ee context\r
- * \r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_create_eec(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_rdd_t rdd,\r
- OUT VAPI_eec_hndl_t *eec_hndl_p\r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_modify_eec_attr\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA Handle.\r
- * eec_hndl: EE Context Handle\r
- * eec_attr_p: Pointer to EE Context Attributes Structure.\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EAGAIN: out of resources\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_EEC_HNDL: invalid EEC handle\r
- * CANNOT_CHANGE_EE_CONTEXT_ATTR\r
- * VAPI_EINVAL_EEC_STATE: invalid EEC state\r
- * VAPI_EINVAL_RDD: invalid RD domain\r
- * INVALID_CHANNEL_MIGRATION_STATE\r
- * VAPI_EPERM: not enough permissions.\r
- * \r
- * \r
- *\r
- * Description: modifies ee attributes\r
- * \r
- * \r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_modify_eec_attr(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_eec_hndl_t eec_hndl,\r
- IN VAPI_eec_attr_t *eec_attr_p \r
- ); \r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_query_eec_attr \r
- *\r
- * Arguments:\r
- * hca_hndl: HCA Handle.\r
- * eec_hndl: EE context handle.\r
- * eec_attr_p: Pointer to EE Context Attributes Structure.\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_EEC_HNDL: invalid EEC handle\r
- * VAPI_EPERM: not enough permissions.\r
- * \r
- * \r
- *\r
- * Description: submits a query on eec attributes\r
- * \r
- * \r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_query_eec_attr(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_eec_hndl_t eec_hndl,\r
- OUT VAPI_eec_attr_t *eec_attr_p\r
- );\r
- \r
-\r
-/*************************************************************************\r
- * Function: VAPI_destroy_eec \r
- *\r
- * Arguments:\r
- * hca_hndl: HCA Handle.\r
- * eec_hndl: EE context handle.\r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_EEC_HNDL: invalid EEC handle\r
- * VAPI_EPERM: not enough permissions.\r
- * \r
- * \r
- *\r
- * Description: destroys an eec context\r
- * \r
- * \r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_destroy_eec (\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_eec_hndl_t eec_hndl,\r
- );\r
-\r
-#endif\r
-\r
-/*******************************************\r
- * 11.2.7 Memory Managemnet\r
- *\r
- *******************************************/\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_register_mr\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * req_mrw_p: Pointer to the requested memory region properties.\r
- * mr_hndl_p: Pointer to the memory region handle.\r
- * rep_mrw: Pointer to the responded memory region properties.\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EAGAIN: out of resources\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_PD_HNDL: invalid PD handle\r
- * VAPI_EINVAL_VA: invalid virtual address\r
- * VAPI_EINVAL_LEN: invalid length\r
- * VAPI_EINVAL_ACL: invalid ACL specifier (remote write or atomic , without local write)\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * The MMU administrates a list of memory regions/windows. The current version of the \r
- * VIP supports only pinned buffers. In the future an extension of the MMU a support for \r
- * pageable buffer will be considered.\r
- * \r
- * Memory Translation and protection tables are not store on the VIP but at the device \r
- * driver due to their device specific orientation.\r
- * \r
- * The caller should fill the req_mrw_p structure fields with the type(VAPI_MR, VAPI_MPR), virtual start \r
- * address, size, protection domain handle (pd_hndl) and the access control list (acl). \r
- * for registration of physical mr, the caller should also fill the fields iova offset (offset \r
- * of virt. start adrs from page start), pbuf_list_p (list of physical buffers) and pbuf_list_len. \r
- *\r
- * Upon successfull completion, the rep_mrw_p will include the l_key, the r_key (if \r
- * remote access was requested). The memory region handle is returned in mr_hndl_p. \r
- * VAPI_mr_t is described in the following table: \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_register_mr(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_mr_t *req_mrw_p,\r
- OUT VAPI_mr_hndl_t *mr_hndl_p,\r
- OUT VAPI_mr_t *rep_mrw_p\r
- );\r
-\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_query_mr\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA handle.\r
- * mr_hndl: Memory Region Handle.\r
- * rep_mrw_p: Pointer to Memory Region Attributes \r
- * remote_start_p: Pointer to the remotly start address returned value\r
- * remote_size_p: Pointer to the remotely size of the region returned \r
- * value\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_MR_HNDL: invalid Memory Region handle\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * Queries a memory region handle and returns a VAPI_mr_t. Upon successful comple-\r
- * tion, the structure includes all the memory region properties: protection domain handle, \r
- * ACL, LKey, RKey and actual protection bounds. The protection bounds returned in \r
- * rep_mrw_p are the local protection bounds enforced by the HCA. The remote protec-\r
- * tion bounds are returned in remote_start_p and remote_size_p and are valid only \r
- * when remote access was requested.\r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_query_mr(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_mr_hndl_t mr_hndl,\r
- OUT VAPI_mr_t *rep_mrw_p,\r
- OUT VAPI_virt_addr_t *remote_start_p,\r
- OUT VAPI_virt_addr_t *remote_size_p\r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_deregister_mr\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA handle.\r
- * mr_hndl: Memory Region Handle\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_MR_HNDL: invalid memory region handle\r
- * VAPI_EBUSY: memory region still has bound window(s)\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * Destroy a registered memory region. The memory region deregistering has to be invali-\r
- * dated from the CI. \r
- * \r
- * It is the roll of the MMU to validate that there are no bounded memory windows in \r
- * order to allow the de-registration of the memory region.\r
- * \r
- * After the deregistration takes place is under the scope of the MMU to unpin all those \r
- * memory pages that were not pinned before the memory registration was done.\r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_deregister_mr(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_mr_hndl_t mr_hndl\r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_reregister_mr \r
- *\r
- * Arguments:\r
- * hca_hndl: HCA Handle.\r
- * mr_hndl: Old Memory Region Handle.\r
- * change_type: requested change type.\r
- * req_mrw_p: Pointer to the requested memory region properties.\r
- * rep_mr_hndl_p: Pointer to the returned new memory region handle\r
- * rep_mrw_p: Pointer to the returned memory region properties.\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EAGAIN: out of resources\r
- * VAPI_EINVAL_PARAM: invalid change type\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_MR_HNDL: invalid memory region handle\r
- * VAPI_EINVAL_VA: invalid virtual address\r
- * VAPI_EINVAL_LEN: invalid length\r
- * VAPI_EINVAL_PD_HNDL: invalid protection domain handle\r
- * VAPI_EINVAL_ACL: invalid ACL specifier\r
- * VAPI_EBUSY: memory region still has bound window(s)\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * Reregisters the memory region associated with the mr_hndl. The changes to be applied \r
- * to the memory region are any combination of the following three flags, specified in the \r
- * change_type input modifier:\r
- * \r
- * MR_CHANGE_TRANS - Change translation. The req_mr_p should contain the \r
- * new start and size of the region as well as the new mr type:in mr_type (VAPI_MR,VAPI_MSHAR, VAPI_MPR ).\r
- * \r
- * MR_CHANGE_PD - Change the PD associated with this region. The req_mr_p \r
- * should contain the new PD.\r
- * \r
- * MR_CHANGE_ACL - Change the ACL. The req_mr_p should contain the new \r
- * ACL for this region.\r
- * \r
- * for registration of physical mr, the caller should also fill the fields iova offset (offset \r
- * of virt. start adrs from page start), pbuf_list_p (list of physical buffers) and pbuf_list_len. \r
- * \r
- * Upon successful completion, the verb returns the new handle for this memory region, \r
- * which may or may be not identical to the original one, but must be used for further ref-\r
- * erences to this region. The LKey and the RKey (only when remote access permission \r
- * was granted) are returned in the rep_mr_p.\r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_reregister_mr(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_mr_hndl_t mr_hndl,\r
- IN VAPI_mr_change_t change_type,\r
- IN VAPI_mr_t *req_mrw_p,\r
- OUT VAPI_mr_hndl_t *rep_mr_hndl_p,\r
- OUT VAPI_mr_t *rep_mrw_p\r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_register_smr\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA handle.\r
- * orig_mr_hndl: Original memory region handle.\r
- * req_mrw_p: Pointer to the requested memory region properties (valid fields:pd,ACL,start virt adrs)\r
- * mr_hndl_p: Pointer to the responded memory region handle.\r
- * rep_mrw: Pointer to the responded memory region properties.\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EAGAIN: out of resources\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_VA: invalid virtual address\r
- * VAPI_EINVAL_MR_HNDL: invlalid MR handle\r
- * VAPI_EINVAL_PD_HNDL: invalid PD handle\r
- * VAPI_EINVAL_ACL: invalid ACL specifier\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * Registers a shared memory region associated with the same physical buffers of an exist-\r
- * ing memory region referenced by orig_mr_hndl. The req_mrw_p is a pointer to the \r
- * requested memory region properties.the struct should contain the \r
- * requested start virtual address (start field), the protection domain handle and the ACL.\r
- * \r
- * Upon successful completion, the new memory region handle is returned in mr_hndl_p \r
- * and a struct rep_mrw_p of type VAPI_mr_t contains the actually assigned virtual \r
- * address (start field), the LKey and the RKey (only if remote access rights were \r
- * requested).\r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_register_smr(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_mr_hndl_t orig_mr_hndl,\r
- IN VAPI_mr_t *req_mrw_p,\r
- OUT VAPI_mr_hndl_t *mr_hndl_p,\r
- OUT VAPI_mr_t *rep_mrw_p\r
- );\r
-\r
-\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_alloc_mw \r
- *\r
- * Arguments:\r
- * hca_hnd: HCA Handle.\r
- * pd_hndl: Protection Domain Handle.\r
- * mw_hndl_p: Pointer to new allocated windows handle.\r
- * rkey_p: Pointer to Windows unbounded Rkey\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EAGAIN\r
- * VAPI_EINVAL_HCA_HNDL\r
- * VAPI_EINVAL_PD_HNDL\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * Allocate a MWO object than can be later bound to an RKey.\r
- * \r
- * The MMU will validate that there enough resources available for this allocations.\r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_alloc_mw(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_pd_hndl_t pd,\r
- OUT VAPI_mw_hndl_t *mw_hndl_p,\r
- OUT VAPI_rkey_t *rkey_p\r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_query_mw\r
- *\r
- * Arguments:\r
- * hca_window: HCA Handle.\r
- * mw_hndl: Windows Handle.\r
- * r_key_p: pointer to Rkey of Window.\r
- * pd: pointer to rotection Domain Handle of Window.\r
- * \r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL\r
- * VAPI_EINVAL_MW_HNDL\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * This call will return the current PD associated with the memory domain which will be \r
- * retrieved from the PDA (no access to HW required).\r
- * \r
- * \r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_query_mw(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_mw_hndl_t mw_hndl,\r
- OUT VAPI_rkey_t *rkey_p,\r
- OUT VAPI_pd_hndl_t *pd_p\r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_bind_mw\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA Handle.\r
- * mw_hndl: Handle of memory windows.\r
- * bind_prop_p: Binding properties.\r
- * qp: QP to use for posting this binding request \r
- * id: Work request ID to be used in this binding request \r
- * comp_type Create CQE or not (for QPs set to singaling per request) \r
- * new_rkey_p: pointer to RKey of bound windows.\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL\r
- * VAPI_EINVAL_MW_HNDL\r
- * VAPI_EINVAL_PARAM\r
- * VAPI_EAGAIN\r
- *\r
- * \r
- *\r
- * Description:\r
- * \r
- * This called is performed completely in user mode. The posted descriptor will return on \r
- * completion an RKey that can be used in subsequent remote access to the bounded mem-\r
- * ory region.\r
- * \r
- * Success of the operation is receive through any one of the immediate errors specified \r
- * about or through the completion entry of the bind windows operation.\r
- * \r
- * The VAPI_bind_mw call is equivalent to the posting of descriptors. The implication of \r
- * this is that both the MMU and the JOD will have to be involved in this call.\r
- * \r
- * \r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_bind_mw(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_mw_hndl_t mw_hndl,\r
- IN const VAPI_mw_bind_t* bind_prop_p,\r
- IN VAPI_qp_hndl_t qp,\r
- IN VAPI_wr_id_t id,\r
- IN VAPI_comp_type_t comp_type,\r
- /* IN MT_bool fence, - This should be added in order to be IB 1.1 compliant */\r
- OUT VAPI_rkey_t* new_rkey_p\r
- );\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_dealloc_mw \r
- *\r
- * Arguments:\r
- * hca_hnd: HCA Handle.\r
- * mw_hndl: New allocated windows handle.\r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EAGAIN\r
- * VAPI_EINVAL_HCA_HNDL\r
- * VAPI_EINVAL_MW_HNDL\r
- * VAPI_EPERM: not enough permissions.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * DeAllocate a MWO object. \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_dealloc_mw(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_mw_hndl_t mw_hndl\r
- );\r
-\r
-/*******************************************\r
- * 11.3 Multicast Group\r
- *******************************************/\r
-\r
-\r
- /*************************************************************************\r
- * Function: VAPI_attach_to_multicast\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA Handle.\r
- * mcg_dgid: gid address of multicast group\r
- * qp_hndl: QP Handle\r
- * mcg_lid: lid of MCG. Currently ignored\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EAGAIN - Insufficient resources to complete request\r
- * VAPI_E2BIG_MCG_SIZE - Number of QPs attached to multicast groups exceeded.\r
- * VAPI_EINVAL_MCG_GID - Invalid multicast DGID\r
- * VAPI_EINVAL_QP_HNDL - Invalid QP handle\r
- * VAPI_EINVAL_HCA_HNDL - Invalid HCA handle\r
- * VAPI_EINVAL_SERVICE_TYPE - Invalid Service Type for this QP.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- *\r
- * Description:\r
- * \r
- * Attaches qp to multicast group..\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_attach_to_multicast(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN IB_gid_t mcg_dgid,\r
- IN VAPI_qp_hndl_t qp_hndl,\r
- IN IB_lid_t mcg_dlid);\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_detach_from_multicast\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA Handle.\r
- * mcg_dgid: multicast group -GID\r
- * qp_hndl: QP Handle\r
- * mcg_dlid: DLID of MCG. Currently ignored\r
- * \r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL - Invalid HCA handle\r
- * VAPI_EINVAL_MCG_GID - Invalid multicast DGID\r
- * VAPI_EINVAL_QP_HNDL - Invalid QP handle\r
- * VAPI_EINVAL_SERVICE_TYPE - Invalid Service Type for this QP.\r
- * VAPI_ESYSCALL: A procedure call to the underlying O/S (ioctl) \r
- * has returned an error.\r
- * \r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * Detaches qp from multicast group..\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_detach_from_multicast(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN IB_gid_t mcg_dgid,\r
- IN VAPI_qp_hndl_t qp_hndl,\r
- IN IB_lid_t mcg_dlid);\r
- \r
-/*******************************************\r
- * 11.4 Work Request Processing\r
- *******************************************/\r
-\r
-/* Queue Pair Operations */\r
-\r
-/* *************************************************************************\r
- * Function: VAPI_post_sr\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * qp_hndl: QP Handle.\r
- * sr_desc_p: Pointer to the send request descriptor attributes structure.\r
- * \r
- * \r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_QP_HNDL: invalid QP handle\r
- * VAPI_E2BIG_WR_NUM: Too many posted work requests.\r
- * VAPI_EINVAL_OP: invalid operation\r
- * VAPI_EINVAL_QP_STATE: invlaid QP state\r
- * VAPI_EINVAL_SG_FMT: invalid scatter/gather list format\r
- * VAPI_EINVAL_SG_NUM: invalid scatter/gather list length\r
- * VAPI_EINVAL_AH: invalid address handle\r
- * VAPI_EPERM: not enough permissions.\r
- * \r
- * Description:\r
- * The verb posts a send queue work request, the properties of which are specified in the \r
- * structure pointed by sr_desc_p, which is of type VAPI_sr_desc_t:\r
- * The sg_lst_p points to a gather list, the length of which is sg_lst_len, which is an array \r
- * of local buffers used as the source of the data to be transmited in this Work Request. \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_post_sr(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_qp_hndl_t qp_hndl,\r
- IN VAPI_sr_desc_t *sr_desc_p\r
- );\r
-\r
-\r
-/* *************************************************************************\r
- * Function: VAPI_post_sr2\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * qp_hndl: QP Handle.\r
- * sr_desc_p: Pointer to the send request descriptor attributes structure.\r
- * \r
- * \r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_QP_HNDL: invalid QP handle\r
- * VAPI_E2BIG_WR_NUM: Too many posted work requests.\r
- * VAPI_EINVAL_OP: invalid operation\r
- * VAPI_EINVAL_QP_STATE: invlaid QP state\r
- * VAPI_EINVAL_NOTIF_TYPE: invalid completion notification \r
- * type\r
- * VAPI_EINVAL_SG_FMT: invalid scatter/gather list format\r
- * VAPI_EINVAL_SG_NUM: invalid scatter/gather list length\r
- * VAPI_EINVAL_AH: invalid address handle\r
- * VAPI_EPERM: not enough permissions.\r
- * \r
- * Each one of the descriptor post will cause the JOD to prepare and PS_IDF (Post Send \r
- * Independent Descriptor Format) which will be delivered to the HCAHAL using \r
- * HH_Post_SR. The HCAHAL will be responsible for the translation of PS_IDF into \r
- * PS_DDF (Post Send Dependent Descriptor Format).\r
- * \r
- * The verb posts a send queue work request, the properties of which are specified in the \r
- * structure pointed by sr_desc_p, which is of type VAPI_sr_desc_t:\r
- * \r
- * \r
- * The sg_lst_p points to a gather list, the length of which is sg_lst_len, which is an array \r
- * of local buffers used as the source of the data to be transmited in this Work Request. \r
- * Each entry in this array has the following format.\r
- * \r
- *\r
- *************************************************************************/ \r
-\r
-VAPI_ret_t VAPI_post_sr2(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_qp_hndl_t qp_hndl,\r
- IN VAPI_comp_type_t comp_type,\r
- IN VAPI_ud_av_hndl_t remote_ah,\r
- IN void* WorkReq\r
- );\r
-\r
-/************************************************************************\r
- * Function: VAPI_post_rr\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * qp_hndl: QP Handle.\r
- * rr_desc_p: Pointer to the receive request descriptor attributes structure.\r
- * \r
- * returns: \r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_QP_HNDL: invalid QP handle\r
- * VAPI_EINVAL_SRQ_HNDL: QP handle used for a QP associted with a SRQ (use VAPI_post_srq)\r
- * VAPI_E2BIG_WR_NUM: Too many posted work requests.\r
- * VAPI_EINVAL_OP: invalid operation\r
- * VAPI_EINVAL_QP_STATE: invlaid QP state\r
- * VAPI_EINVAL_SG_NUM: invalid scatter/gather list length\r
- * VAPI_EPERM: not enough permissions.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * The verb posts a receive request descriptor to the receive queue.\r
- */ \r
- VAPI_ret_t MT_API VAPI_post_rr(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_qp_hndl_t qp_hndl,\r
- IN VAPI_rr_desc_t *rr_desc_p\r
- );\r
-\r
-/************************************************************************\r
- * Function: VAPI_post_rr2\r
- *\r
- * Arguments:\r
- * hca_hndl : HCA Handle.\r
- * qp_hndl: QP Handle.\r
- * work_request: Pointer to the IB work request describing the receive operation\r
- * \r
- * returns: \r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_QP_HNDL: invalid QP handle\r
- * VAPI_E2BIG_WR_NUM: Too many posted work requests.\r
- * VAPI_EINVAL_OP: invalid operation\r
- * VAPI_EINVAL_QP_STATE: invlaid QP state\r
- * VAPI_EINVAL_SG_NUM: invalid scatter/gather list length\r
- * VAPI_EPERM: not enough permissions.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * Each one of the descriptor post will cause the JOD to prepare and PR_IDF (Post \r
- * Receive Independent Descriptor Format) which will be delivered to the HCAHAL using \r
- * HH_Post_RR. The HCAHAL will be responsible for the translation of PR_IDF into \r
- * PR_DDF (Post Receive Dependent Descriptor Format).\r
- * \r
- * The verb posts a receive request descriptor to the receive queue. The receive request \r
- * descriptor is of type VAPI_rr_desc_t and is described in the following table:\r
- */\r
-\r
-VAPI_ret_t VAPI_post_rr2(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_qp_hndl_t qp_hndl,\r
- IN VAPI_comp_type_t comp_type,\r
- IN u_int32_t sg_lst_len,\r
- IN VAPI_wr_id_t ReqId,\r
- IN VAPI_sg_lst_entry_t *sg_lst_p\r
- );\r
-\r
-/* Completion Queue Operations */\r
-\r
-\r
-/*************************************************************************\r
- * Function: VAPI_poll_cq\r
- *\r
- * Arguments:\r
- * hca_hndl: Handle to HCA.\r
- * cq_hndl: CQ Handle.\r
- * wc_desc_p: Pointer to work completion descriptor structure.\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_CQ_HNDL: invalid CQ handle\r
- * VAPI_CQ_EMPTY: CQ is empty \r
- * VAPI_EPERM: not enough permissions.\r
- *\r
- * Description:\r
- * \r
- * This call will retrieve an ICQE (Independent Completion Queue Entry), which is a \r
- * device independent structure used to retrieve completion status of WR posted to the \r
- * Send/Receive Queue including VAPI_bind_mw. \r
- * \r
- * The verb retrieves a completion queue entry into the descriptor pointed by wc_desc_p \r
- * which is of type VAPI_wc_desc_t and described in the following table:\r
- * \r
- * \r
- * \r
- * The remote_node_address is of type VAPI_remote_node_addr_t and is valid only for \r
- * Datagram services. \r
- * \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_poll_cq(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_cq_hndl_t cq_hndl,\r
- OUT VAPI_wc_desc_t *comp_desc_p\r
- );\r
-\r
-/*************************************************************************\r
- * Function: VAPI_poll_and_rearm_cq\r
- * \r
- * Arguments:\r
- * hca_hndl: Handle to HCA.\r
- * cq_hndl: CQ Handle. \r
- * wc_desc_p: Pointer to work completion descriptor structure.\r
- * \r
- *\r
- *\r
- * Returns:\r
- * VAPI_OK: cqe is valid, cq has been rearmed, no more polling required\r
- * VAPI_EAGAIN: cqe is valid, cq has not been rearmed, service cqe then poll again\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_CQ_HNDL: invalid CQ handle\r
- * VAPI_CQ_EMPTY: cqe is not valid, cq has been rearmed, no more polling required\r
- * VAPI_EPERM: not enough permissions.\r
- *\r
- * Description:\r
- *\r
- * This call will retrieve an ICQE (Independent Completion Queue Entry), which is a\r
- * device independent structure used to retrieve completion status of WR posted to the\r
- * Send/Receive Queue including VAPI_bind_mw.\r
- *\r
- * The verb retrieves a completion queue entry into the descriptor pointed by wc_desc_p\r
- * which is of type VAPI_wc_desc_t and described in the following table:\r
- *\r
- *\r
- *\r
- * The remote_node_address is of type VAPI_remote_node_addr_t and is valid only for\r
- * Datagram services.\r
- *\r
- *\r
- *************************************************************************/\r
-VAPI_ret_t VAPI_poll_and_rearm_cq(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_cq_hndl_t cq_hndl,\r
- IN int solicitedNotification, /* false = next notification */\r
- OUT VAPI_wc_desc_t *comp_desc_p\r
- );\r
-\r
-/*************************************************************************\r
- * Function: VAPI_req_comp_notif\r
- *\r
- * Arguments:\r
- * hca_hndl: Handle to HCA.\r
- * cq_hndl: CQ Handle.\r
- * notif_type: CQ Notification type.\r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EINVAL_CQ_HNDL: invalid CQ handle\r
- * VAPI_EINVAL_NOTIF_TYPE: invalid notify type\r
- * VAPI_EPERM: not enough permissions.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * the verb request a type specified in notif_type. \r
- *\r
- *************************************************************************/ \r
-VAPI_ret_t MT_API VAPI_req_comp_notif(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_cq_hndl_t cq_hndl,\r
- IN VAPI_cq_notif_type_t notif_type\r
- );\r
-\r
-/* TK - only later #ifdef __KERNEL__ */\r
-\r
-/*******************************************\r
- * 11.5 Event Handling - the global functions exposed only to kernel modules \r
- * See evapi.h for the user level functions\r
- *******************************************/\r
-/*************************************************************************\r
- * Function: VAPI_set_comp_event_handler (kernel space only)\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA Handle \r
- * handler: Completion Event Handler function address.\r
- * private_data: Pointer to handler context (handler specific).\r
- * \r
- * \r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EPERM: not enough permissions.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * Registers a completion event handler. Only one CQ event handler can be registered per \r
- * HCA.\r
- * \r
- * Exposed only to kernel modules\r
- *\r
- * The CQ event handler function prototype is as follows:\r
- * \r
- * void\r
- * VAPI_completion_event_handler\r
- * (\r
- * IN VAPI_hca_hndl_t hca_hndl,\r
- * IN VAPI_cq_hndl_t cq_hndl,\r
- * IN void *private_data\r
- * )\r
- * \r
- * \r
- * \r
- * \r
- *\r
- *************************************************************************/ \r
-#ifdef __KERNEL__\r
-VAPI_ret_t MT_API VAPI_set_comp_event_handler(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_completion_event_handler_t handler,\r
- IN void* private_data\r
- );\r
-#endif\r
-\r
-/*************************************************************************\r
- * Function: VAPI_set_async_event_handler (kernel space only)\r
- *\r
- * Arguments:\r
- * hca_hndl: HCA Handle \r
- * handler: Async Event Handler function address.\r
- * private_data: Pointer to handler context (handler specific).\r
- * \r
- * \r
- * \r
- *\r
- * Returns:\r
- * VAPI_OK\r
- * VAPI_EINVAL_HCA_HNDL: invalid HCA handle\r
- * VAPI_EPERM: not enough permissions.\r
- * \r
- * \r
- *\r
- * Description:\r
- * \r
- * Registers an async event handler. \r
- * Exposed only to kernel modules\r
- *\r
- * The event handler function prototype is as follows:\r
- * \r
- * void\r
- * VAPI_async_event_handler\r
- * (\r
- * IN VAPI_hca_hndl_t hca_hndl,\r
- * IN VAPI_event_record_t *event_record_p,\r
- * IN void *private_data\r
- * )\r
- * \r
- *\r
- *************************************************************************/ \r
-#ifdef __KERNEL__\r
-VAPI_ret_t MT_API VAPI_set_async_event_handler(\r
- IN VAPI_hca_hndl_t hca_hndl,\r
- IN VAPI_async_event_handler_t handler,\r
- IN void* private_data\r
- );\r
-#endif /* KERNEL */\r
-\r
-#endif /*H_VAPI_H*/\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_VAPI_FEATURES_H\r
-#define H_VAPI_FEATURES_H\r
-\r
-/* VAPI_ features macros */\r
-#define VAPI_FEATURE_APM /* Automatic Path migration support */\r
-#define VAPI_FEATURE_ETIMEOUT /* defined new return code VAPI_ETIMEOUT */\r
-#define VAPI_FEATURE_RESIZE_CQ\r
-#define VAPI_FEATURE_RESOURCE_TRACKING /* User level resource tracking supported */\r
-#define VAPI_FEATURE_SMR_VALIDATION\r
-#define VAPI_FEATURE_ALT_RETRY_OBSOLETE /* retry count and rnr_retry are per QP, not per path */\r
-#define VAPI_FEATURE_DESTR_QP_FAIL_IF_MCG /* destroy QP fails if QP is attached to a mcg */\r
-#define VAPI_FEATURE_SRQ /* SRQ (Shared Receive Queue) support */\r
-#define VAPI_FEATURE_MODIFY_SRQ /* VAPI_modify_srq supported */\r
-#define VAPI_FEATURE_CQE_WITH_QP /* QP number included in VAPI_wc_desc_t */\r
-/* to be enabled when SQ Draining is entirely fixed*/\r
-/* #define VAPI_FEATURE_SQD */\r
-\r
-/* EVAPI features macros */\r
-#define EVAPI_FEATURE_DP_HNDL_CHK /* Data path handles validation */\r
-#define EVAPI_FEATURE_FMR /* Fast Memory Regions support */\r
-#define EVAPI_FEATURE_INLINE_SR /* Inline send */\r
-#define EVAPI_FEATURE_CQBLK /* EVAPI_poll_cq_block() */\r
-#define EVAPI_FEATURE_PEEK_CQ /* EVAPI_peek_cq() */\r
-#define EVAPI_FEATURE_REQ_NCOMP_NOTIF /* EVAPI_req_ncomp_notif() */\r
-#define EVAPI_FEATURE_ALLOC_PD_AV /* EVAPI_alloc_pd() */\r
-#define EVAPI_FEATURE_PROC_MAD_OPTS /*change in EVAPI_process_local_mad() arglist */\r
-#define EVAPI_FEATURE_APM\r
-#define EVAPI_FEATURE_DEVMEM\r
-#define EVAPI_FEATURE_DEVMEM2\r
-#define EVAPI_FEATURE_LOCAL_MAD_BAD_PARAM\r
-#define EVAPI_FEATURE_OPEN_CLOSE_HCA\r
-#define EVAPI_FEATURE_ASYNC_EVENTH\r
-#define EVAPI_FEATURE_LOCAL_MAD_SLID\r
-#define EVAPI_FEATURE_USER_PROFILE /* user profile. Affects EVAPI_open_hca() arlist*/\r
-#define EVAPI_FEATURE_VENDOR_ERR_SYNDROME /* EVAPI_vendor_err_syndrome_t in VAPI_wc_desc_t */\r
-#define EVAPI_FEATURE_GSI_SEND_PKEY /* EVAPI_post_gsi_sr with Pkey parameter */\r
-#define EVAPI_FEATURE_ALLOC_PD_AV_SQP /* EVAPI_alloc_pd_sqp() */\r
-#define EVAPI_FEATURE_FORK_SUPPORT /* support fork in multithreaded apps */\r
-#define EVAPI_FEATURE_POLL_AND_REARM_CQ /* VAPI_poll_and_rearm_cq */\r
-#define EVAPI_FEATURE_POST_RR2\r
-#define EVAPI_FEATURE_POST_SR2 \r
-\r
-/* Fixed bugs (FlowManager issue numbers) */\r
-#define BUG_FIX_FM12831\r
-#define BUG_FIX_FM12549\r
-#define BUG_FIX_FM16939\r
-\r
-#endif \r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_VAPI_TYPES_H\r
-#define H_VAPI_TYPES_H\r
-\r
-#include <mtl_common.h>\r
-#include <ib_defs.h>\r
-\r
-\r
-/* This is same as constant in MDOAL and MDHAL */\r
-#define HCA_MAXNAME 32\r
-\r
-\r
-/*\r
- * HCA Types\r
- *\r
- *\r
- */\r
-typedef char VAPI_hca_id_t[HCA_MAXNAME]; /* NULL terminated string of up to HCA_MAXNAME-1 chars */\r
-typedef u_int32_t VAPI_hca_hndl_t; /* HCA handle */\r
-typedef MT_ulong_ptr_t VAPI_pd_hndl_t; /* Protection Domain handle */\r
-typedef MT_ulong_ptr_t VAPI_ud_av_hndl_t; /* UD Address Vector Handle */\r
-typedef MT_ulong_ptr_t VAPI_cq_hndl_t; /* Completion Queue handle */\r
-typedef MT_ulong_ptr_t VAPI_qp_hndl_t; /* Queue Pair handle */\r
-typedef MT_ulong_ptr_t VAPI_srq_hndl_t; /* Shared Receive Queue handle */\r
-typedef u_int32_t VAPI_devmem_hndl_t;\r
-typedef u_int32_t VAPI_mr_hndl_t; /* Memory Region Handle */\r
-typedef MT_ulong_ptr_t VAPI_mw_hndl_t; /* Memory Window Handle */\r
-typedef u_int32_t VAPI_eec_hndl_t; /* E2E Context Handle */\r
-typedef u_int32_t VAPI_pkey_ix_t; /* Pkey index */\r
-typedef u_int32_t VAPI_rdd_hndl_t; /* RD domain handle */\r
-typedef u_int32_t VAPI_key_counter_t; /* QKEY/PKEY violation counter type */\r
-typedef IB_wqpn_t VAPI_qp_num_t; /* QP number (24 bits) */\r
-typedef IB_eecn_t VAPI_eec_num_t; /* EEC number (24 bits) */\r
-typedef u_int8_t VAPI_sched_queue_t; /* Schedule queue index */\r
-typedef IB_psn_t VAPI_psn_t; /* PSN number (24 bits) */\r
-typedef IB_qkey_t VAPI_qkey_t; /* QKey (32 bits) */\r
-typedef u_int8_t VAPI_retry_count_t; /* Number of retries */\r
-typedef u_int8_t VAPI_timeout_t; /* Timeout= 4.096usec * 2^<this_type> */\r
-typedef u_int32_t VAPI_cqe_num_t; /* number of entries in CQ*/\r
-typedef u_int32_t VAPI_lkey_t; /* L Key */\r
-typedef IB_rkey_t VAPI_rkey_t; /* R Key */ \r
-typedef IB_virt_addr_t VAPI_virt_addr_t; /* Virtual Address (/Length) */\r
-typedef u_int64_t VAPI_phy_addr_t; /* Physical address (/length)*/\r
-typedef u_int64_t VAPI_size_t;\r
-typedef u_int64_t VAPI_wr_id_t; /* Work request id */\r
-typedef u_int32_t VAPI_imm_data_t; /* Immediate data */\r
-typedef u_int16_t VAPI_ethertype_t; /* Ethertype */\r
-/* TBD: Those two types below may be removed... (check references) */\r
-typedef IB_gid_t VAPI_gid_t; /* GID */\r
-typedef IB_pkey_t VAPI_pkey_t; /* PKey (16 bits) */\r
-\r
-/* Use the following macro to init handles and denote uninitialized handles */\r
-#define VAPI_INVAL_HNDL ((MT_long_ptr_t)-1)\r
-#define VAPI_INVAL_SRQ_HNDL VAPI_INVAL_HNDL\r
-#define VAPI_INVAL_PD_HNDL VAPI_INVAL_HNDL\r
-\r
-#define EVAPI_DEFAULT_AVS_PER_PD 0xFFFFFFFF\r
-\r
-/* HCA Cap Flags */\r
-typedef enum {\r
- VAPI_RESIZE_OUS_WQE_CAP = 1, \r
- VAPI_BAD_PKEY_COUNT_CAP = (1<<1), \r
- VAPI_BAD_QKEY_COUNT_CAP = (1<<2),\r
- VAPI_RAW_MULTI_CAP = (1<<3), \r
- VAPI_AUTO_PATH_MIG_CAP = (1<<4),\r
- VAPI_CHANGE_PHY_PORT_CAP = (1<<5), \r
- VAPI_UD_AV_PORT_ENFORCE_CAP = (1<<6), /* IBTA comment #1821 */\r
- VAPI_CURR_QP_STATE_MOD_CAP = (1<<7), /*IB Spec 1.09 sec 11.2.1.2 */\r
- VAPI_SHUTDOWN_PORT_CAP = (1<<8), /*IB Spec 1.09 sec 11.2.1.2 */\r
- VAPI_INIT_TYPE_CAP = (1<<9), /*IB Spec 1.09 sec 11.2.1.2 */\r
- VAPI_PORT_ACTIVE_EV_CAP = (1<<10), /*IB Spec 1.09 sec 11.2.1.2 */\r
- VAPI_SYS_IMG_GUID_CAP = (1<<11), /*IB Spec 1.09 sec 11.2.1.2 */\r
- VAPI_RC_RNR_NAK_GEN_CAP = (1<<12) /*IB Spec 1.09 sec 11.2.1.2 */\r
-} VAPI_hca_cap_flags_t;\r
-\r
-\r
-/* HCA attributes mask enumeration */\r
-typedef enum {\r
- HCA_ATTR_IS_SM = 1,\r
- HCA_ATTR_IS_SNMP_TUN_SUP = 2,\r
- HCA_ATTR_IS_DEV_MGT_SUP = 4,\r
- HCA_ATTR_IS_VENDOR_CLS_SUP = 8,\r
- HCA_ATTR_IS_CLIENT_REREGISTRATION_SUP = 16,\r
- HCA_ATTR_MAX = 32 /*Dummy enum entry: always keep it the last one */\r
-} VAPI_hca_attr_mask_enum_t;\r
-\r
-\r
-/* HCA attributes mask */\r
-typedef u_int32_t VAPI_hca_attr_mask_t;\r
-\r
-#define HCA_ATTR_MASK_CLR_ALL(mask) ((mask)=0)\r
-#define HCA_ATTR_MASK_SET_ALL(mask) ((mask)=(HCA_ATTR_MAX-1))\r
-#define HCA_ATTR_MASK_SET(mask,attr) ((mask)|=(attr))\r
-#define HCA_ATTR_MASK_CLR(mask,attr) ((mask)&=(~(attr)))\r
-#define HCA_ATTR_IS_FLAGS_SET(mask) (((mask)&(\\r
- HCA_ATTR_IS_SM|\\r
- HCA_ATTR_IS_SNMP_TUN_SUP|\\r
- HCA_ATTR_IS_DEV_MGT_SUP|\\r
- HCA_ATTR_IS_VENDOR_CLS_SUP|\\r
- HCA_ATTR_IS_CLIENT_REREGISTRATION_SUP))!=0)\r
-#define HCA_ATTR_IS_SET(mask,attr) (((mask)&(attr))!=0)\r
-\r
-/* QP attributes mask enumeration */\r
-typedef enum {\r
- QP_ATTR_QP_STATE = 0x1, /* QP next state */\r
- QP_ATTR_EN_SQD_ASYN_NOTIF = 0x2, /* Enable SQD affiliated asynchronous event notification */\r
- QP_ATTR_QP_NUM = 0x4, /* Queue Pair Number. [Mellanox specific] */\r
- QP_ATTR_REMOTE_ATOMIC_FLAGS = 0x8, /* Enable/Disable RDMA and atomic */\r
- QP_ATTR_PKEY_IX = 0x10, /* Primary PKey index */\r
- QP_ATTR_PORT = 0x20, /* Primary port */\r
- QP_ATTR_QKEY = 0x40, /* QKey (UD/RD only) */\r
- QP_ATTR_AV = 0x80, /* Primary remote node address vector (RC/UC QP only) */\r
- QP_ATTR_PATH_MTU = 0x100, /* Path MTU : 6 bits (connected services only) */\r
- QP_ATTR_TIMEOUT = 0x200, /* Local Ack Timeout (RC only) */\r
- QP_ATTR_RETRY_COUNT = 0x400, /* retry count (RC only) */\r
- QP_ATTR_RNR_RETRY = 0x800, /* RNR retry count (RC only) */\r
- QP_ATTR_RQ_PSN = 0x1000, /* Packet Sequence Number for RQ */\r
- QP_ATTR_QP_OUS_RD_ATOM = 0x2000, /* Maximum number of oust. RDMA read/atomic as target */\r
- QP_ATTR_ALT_PATH = 0x4000, /* Alternate remote node address vector */\r
- QP_ATTR_RSRV_1 = 0x8000, /* reserved */\r
- QP_ATTR_RSRV_2 = 0x10000, /* reserved */\r
- QP_ATTR_RSRV_3 = 0x20000, /* reserved */\r
- QP_ATTR_RSRV_4 = 0x40000, /* reserved */\r
- QP_ATTR_RSRV_5 = 0x80000, /* reserved */\r
- QP_ATTR_RSRV_6 = 0x100000, /* reserved */\r
- QP_ATTR_MIN_RNR_TIMER = 0x200000, /* Minimum RNR NAK timer */\r
- QP_ATTR_SQ_PSN = 0x400000, /* Packet sequence number for SQ */\r
- QP_ATTR_OUS_DST_RD_ATOM = 0x800000, /* Number of outstanding RDMA rd/atomic ops at destination */\r
- QP_ATTR_PATH_MIG_STATE = 0x1000000, /* Migration state */\r
- QP_ATTR_CAP = 0x2000000, /* QP capabilities max_sq/rq_ous_wr only valid */\r
- QP_ATTR_DEST_QP_NUM = 0x4000000, /* Destination QP number (RC/UC) */\r
- QP_ATTR_SCHED_QUEUE = 0x8000000 /* Schedule queue for QoS association */\r
-} VAPI_qp_attr_mask_enum_t; \r
-\r
-/* QP attributes mask */\r
-typedef u_int32_t VAPI_qp_attr_mask_t;\r
-\r
-#define QP_ATTR_MASK_CLR_ALL(mask) ((mask)=0)\r
-#define QP_ATTR_MASK_SET_ALL(mask) ((mask)=(0x07FFFFFF))\r
-#define QP_ATTR_MASK_SET(mask,attr) ((mask)=((mask)|(attr)))\r
-#define QP_ATTR_MASK_CLR(mask,attr) ((mask)=((mask)&(~(attr))))\r
-#define QP_ATTR_IS_SET(mask,attr) (((mask)&(attr))!=0)\r
-\r
-\r
-/* HCA Atomic Operation Capabilities */\r
-typedef enum {\r
- VAPI_ATOMIC_CAP_NONE, /* No Atomic ops supported */\r
- VAPI_ATOMIC_CAP_HCA, /* Atomic cap supported within this HCA QPs */\r
- VAPI_ATOMIC_CAP_GLOB /* Atomicity supported among all entities in this sytem */\r
-} VAPI_atomic_cap_t;\r
-\r
-/* Signalling type */\r
-typedef enum {\r
- VAPI_SIGNAL_ALL_WR, \r
- VAPI_SIGNAL_REQ_WR\r
-} VAPI_sig_type_t;\r
-\r
-/* Transport Service Type */\r
-enum {\r
- VAPI_TS_RC=IB_TS_RC,\r
- VAPI_TS_RD=IB_TS_RD,\r
- VAPI_TS_UC=IB_TS_UC,\r
- VAPI_TS_UD=IB_TS_UD,\r
- VAPI_TS_RAW=IB_TS_RAW,\r
- VAPI_NUM_TS_TYPES\r
-}; \r
-typedef IB_ts_t VAPI_ts_type_t;\r
-\r
-/* The following value to be used for reserved GRH buffer space in UD RQ */\r
-/* (The offset of the payload in buffers posted to the UD RQ) */\r
-#define VAPI_GRH_LEN 40\r
-\r
-/* QP state */\r
-enum {\r
- VAPI_RESET,VAPI_INIT,VAPI_RTR,VAPI_RTS,VAPI_SQD,VAPI_SQE,VAPI_ERR\r
-};\r
-typedef u_int32_t VAPI_qp_state_t;\r
-\r
-/* Migration state */\r
-typedef enum {\r
- VAPI_MIGRATED, VAPI_REARM, VAPI_ARMED\r
-} VAPI_mig_state_t;\r
-\r
-/* Special QP Types */\r
-enum { \r
- VAPI_REGULAR_QP= 0, /* Encoding for non-special QP */\r
- VAPI_SMI_QP, VAPI_GSI_QP, VAPI_RAW_IPV6_QP, VAPI_RAW_ETY_QP \r
-};\r
-typedef u_int32_t VAPI_special_qp_t;\r
-\r
-/* Just a generic name for a type used to identify QP type */\r
-typedef VAPI_special_qp_t VAPI_qp_type_t; \r
-\r
-/* RDMA/Atomic Access Control */\r
-typedef enum {\r
- VAPI_EN_REM_WRITE=1, VAPI_EN_REM_READ=2, VAPI_EN_REM_ATOMIC_OP=4\r
-} \r
-VAPI_rdma_atom_acl_enum_t;\r
-typedef u_int32_t VAPI_rdma_atom_acl_t;\r
-\r
-/* Memory region/window types */\r
-typedef enum {\r
- VAPI_MR, /* Memory region */\r
- VAPI_MW, /* Memory Window */\r
- VAPI_MPR, /* Physical memory region */\r
- VAPI_MSHAR /* Shared memory region */\r
-} VAPI_mrw_type_t;\r
-\r
-/* Remote node address type */\r
-typedef enum {\r
- VAPI_RNA_RD, \r
- VAPI_RNA_UD, \r
- VAPI_RNA_RAW_ETY, \r
- VAPI_RNA_RAW_IPV6 \r
-} VAPI_remote_node_addr_type_t;\r
-\r
-/* Memory region/window ACLs */\r
-enum {\r
- VAPI_EN_LOCAL_WRITE= 1, \r
- VAPI_EN_REMOTE_WRITE= 1<<1, \r
- VAPI_EN_REMOTE_READ= 1<<2, \r
- VAPI_EN_REMOTE_ATOM= 1<<3, \r
- VAPI_EN_MEMREG_BIND= 1<<4\r
-};\r
-typedef u_int32_t VAPI_mrw_acl_t;\r
-\r
-/* Memory region change type */\r
-typedef enum {\r
- VAPI_MR_CHANGE_TRANS= 1,\r
- VAPI_MR_CHANGE_PD= 1<<1,\r
- VAPI_MR_CHANGE_ACL= 1<<2\r
-} VAPI_mr_change_flags_t; \r
-\r
-typedef u_int32_t VAPI_mr_change_t; /* VAPI_mr_change_flags_t combination */\r
-\r
-typedef enum {\r
- EVAPI_DEVMEM_EXT_DRAM /* External attached SDRAM */\r
-}EVAPI_devmem_type_t;\r
-\r
-\r
-/* Work requests opcodes */\r
-/* Note. The following enum must be maintained zero based without holes */\r
-typedef enum {\r
- VAPI_RDMA_WRITE,\r
- VAPI_RDMA_WRITE_WITH_IMM,\r
- VAPI_SEND,\r
- VAPI_SEND_WITH_IMM,\r
- VAPI_RDMA_READ,\r
- VAPI_ATOMIC_CMP_AND_SWP,\r
- VAPI_ATOMIC_FETCH_AND_ADD,\r
- VAPI_RECEIVE,\r
- VAPI_NUM_OPCODES\r
-} VAPI_wr_opcode_t;\r
-\r
-/* Completion Opcodes */\r
-typedef enum {\r
- VAPI_CQE_SQ_SEND_DATA, \r
- VAPI_CQE_SQ_RDMA_WRITE,\r
- VAPI_CQE_SQ_RDMA_READ,\r
- VAPI_CQE_SQ_COMP_SWAP,\r
- VAPI_CQE_SQ_FETCH_ADD,\r
- VAPI_CQE_SQ_BIND_MRW,\r
- VAPI_CQE_RQ_SEND_DATA,\r
- VAPI_CQE_RQ_RDMA_WITH_IMM, /* For RDMA Write Only */\r
- VAPI_CQE_INVAL_OPCODE = 0xFFFFFFFF /* special value to return on CQE with error */\r
-} VAPI_cqe_opcode_t;\r
-\r
-\r
-/* Work completion status */\r
-enum {\r
- VAPI_SUCCESS = IB_COMP_SUCCESS,\r
- VAPI_LOC_LEN_ERR = IB_COMP_LOC_LEN_ERR,\r
- VAPI_LOC_QP_OP_ERR = IB_COMP_LOC_QP_OP_ERR,\r
- VAPI_LOC_EE_OP_ERR = IB_COMP_LOC_EE_OP_ERR,\r
- VAPI_LOC_PROT_ERR = IB_COMP_LOC_PROT_ERR,\r
- VAPI_WR_FLUSH_ERR = IB_COMP_WR_FLUSH_ERR,\r
- VAPI_MW_BIND_ERR = IB_COMP_MW_BIND_ERR,\r
- VAPI_BAD_RESP_ERR = IB_COMP_BAD_RESP_ERR,\r
- VAPI_LOC_ACCS_ERR = IB_COMP_LOC_ACCS_ERR,\r
- VAPI_REM_INV_REQ_ERR = IB_COMP_REM_INV_REQ_ERR,\r
- VAPI_REM_ACCESS_ERR = IB_COMP_REM_ACCESS_ERR,\r
- VAPI_REM_OP_ERR = IB_COMP_REM_OP_ERR,\r
- VAPI_RETRY_EXC_ERR = IB_COMP_RETRY_EXC_ERR,\r
- VAPI_RNR_RETRY_EXC_ERR = IB_COMP_RNR_RETRY_EXC_ERR,\r
- VAPI_LOC_RDD_VIOL_ERR = IB_COMP_LOC_RDD_VIOL_ERR,\r
- VAPI_REM_INV_RD_REQ_ERR = IB_COMP_REM_INV_RD_REQ_ERR,\r
- VAPI_REM_ABORT_ERR= IB_COMP_REM_ABORT_ERR,\r
- VAPI_INV_EECN_ERR = IB_COMP_INV_EECN_ERR,\r
- VAPI_INV_EEC_STATE_ERR = IB_COMP_INV_EEC_STATE_ERR,\r
-/* VAPI_COMP_LOC_TOUT = IB_COMP_LOC_TOUT,*/ /* Use VAPI_RETRY_EXC_ERR instead */\r
-/* VAPI_COMP_RNR_TOUT = IB_COMP_RNR_TOUT,*/ /* Use VAPI_RNR_RETRY_EXC_ERR instead */\r
-\r
- VAPI_COMP_FATAL_ERR = IB_COMP_FATAL_ERR,\r
- VAPI_COMP_GENERAL_ERR = IB_COMP_GENERAL_ERR\r
-};\r
-typedef u_int32_t VAPI_wc_status_t;\r
-\r
-/* Vendor specific error syndrome */\r
-typedef u_int32_t EVAPI_vendor_err_syndrome_t;\r
-\r
-/* work request completion type */\r
-typedef enum {\r
- VAPI_SIGNALED, VAPI_UNSIGNALED\r
-} VAPI_comp_type_t;\r
-\r
-/* Completion Notification Type */\r
-typedef enum {\r
- VAPI_NOTIF_NONE, /* No completion notification requested */\r
- VAPI_SOLIC_COMP, /* Notify on solicited completion event only */\r
- VAPI_NEXT_COMP /* Notify on next completion */\r
-} VAPI_cq_notif_type_t;\r
-\r
-typedef VAPI_cq_hndl_t EVAPI_compl_handler_hndl_t; /* EVAPI completion handler handle */\r
-\r
-typedef u_int32_t VAPI_k_cq_hndl_t; /* Kernel level CQ access */\r
-\r
-/* Completion Event Handler Pointer */\r
-typedef void (MT_API *VAPI_completion_event_handler_t)(\r
- /*IN*/ VAPI_hca_hndl_t hca_hndl,\r
- /*IN*/ VAPI_cq_hndl_t cq_hndl,\r
- /*IN*/ void* private_data\r
- );\r
-\r
-/* CQ destruction callback */\r
-typedef void (MT_API *EVAPI_destroy_cq_cbk_t)(\r
- IN VAPI_hca_hndl_t k_hca_hndl,\r
- IN VAPI_k_cq_hndl_t k_cq_hndl,\r
- IN void* private_data\r
- );\r
-\r
-\r
-typedef u_int32_t VAPI_k_qp_hndl_t; /* Kernel level QP access */\r
-\r
-typedef void (MT_API *EVAPI_destroy_qp_cbk_t)(\r
- IN VAPI_hca_hndl_t k_hca_hndl,\r
- IN VAPI_k_qp_hndl_t k_qp_hndl,\r
- IN void* private_data\r
- );\r
- \r
-\r
-/* Event Record Event Types, valid modifier mentionned where unclear */\r
-typedef enum {\r
- VAPI_QP_PATH_MIGRATED, /*QP*/\r
- VAPI_EEC_PATH_MIGRATED, /*EEC*/\r
- VAPI_QP_COMM_ESTABLISHED, /*QP*/\r
- VAPI_EEC_COMM_ESTABLISHED, /*EEC*/ \r
- VAPI_SEND_QUEUE_DRAINED, /*QP*/\r
- VAPI_RECEIVE_QUEUE_DRAINED, /*QP (Last WQE Reached) */\r
- VAPI_SRQ_LIMIT_REACHED, /*SRQ*/\r
- VAPI_SRQ_CATASTROPHIC_ERROR, /*SRQ*/\r
- VAPI_CQ_ERROR, /*CQ*/\r
- VAPI_LOCAL_WQ_INV_REQUEST_ERROR, /*QP*/\r
- VAPI_LOCAL_WQ_ACCESS_VIOL_ERROR, /*QP*/\r
- VAPI_LOCAL_WQ_CATASTROPHIC_ERROR, /*QP*/\r
- VAPI_PATH_MIG_REQ_ERROR, /*QP*/\r
- VAPI_LOCAL_EEC_CATASTROPHIC_ERROR, /*EEC*/\r
- VAPI_LOCAL_CATASTROPHIC_ERROR, /*none*/\r
- VAPI_PORT_ERROR, /*PORT*/\r
- VAPI_PORT_ACTIVE, /*PORT*/\r
- VAPI_CLIENT_REREGISTER\r
-} VAPI_event_record_type_t;\r
-\r
-\r
-typedef enum {\r
- VAPI_EV_SYNDROME_NONE, /* no special syndrom for this event */\r
- VAPI_CATAS_ERR_FW_INTERNAL,\r
- VAPI_CATAS_ERR_EQ_OVERFLOW,\r
- VAPI_CATAS_ERR_MISBEHAVED_UAR_PAGE,\r
- VAPI_CATAS_ERR_UPLINK_BUS_ERR, \r
- VAPI_CATAS_ERR_HCA_DDR_DATA_ERR,\r
- VAPI_CATAS_ERR_INTERNAL_PARITY_ERR,\r
- VAPI_CATAS_ERR_MASTER_ABORT,\r
- VAPI_CATAS_ERR_GO_BIT,\r
- VAPI_CATAS_ERR_CMD_TIMEOUT,\r
- VAPI_CATAS_ERR_FATAL_CR, /* unexpected read from CR space */\r
- VAPI_CATAS_ERR_FATAL_TOKEN, /* invalid token on command completion */\r
- VAPI_CATAS_ERR_GENERAL, /* reason is not known */\r
- VAPI_CQ_ERR_OVERRUN,\r
- VAPI_CQ_ERR_ACCESS_VIOL,\r
- VAPI_CATAS_ERR_FATAL_EXTERNAL /* externally generated artificial fatal error */\r
-} VAPI_event_syndrome_t;\r
-\r
- /* Event Record */\r
-typedef struct {\r
- VAPI_event_record_type_t type; /* event record type */\r
- VAPI_event_syndrome_t syndrome;\r
- union {\r
- VAPI_qp_hndl_t qp_hndl; /* Affiliated QP handle */\r
- VAPI_srq_hndl_t srq_hndl; /* Affiliated SRQ handle */\r
- VAPI_eec_hndl_t eec_hndl; /* Affiliated EEC handle */\r
- VAPI_cq_hndl_t cq_hndl; /* Affiliated CQ handle */\r
- IB_port_t port_num; /* Affiliated Port number */\r
- } modifier;\r
-} VAPI_event_record_t;\r
-\r
-/* Async Event Handler */\r
-typedef void (MT_API *VAPI_async_event_handler_t)(\r
- /*IN*/ VAPI_hca_hndl_t hca_hndl,\r
- /*IN*/ VAPI_event_record_t *event_record_p, \r
- /*IN*/ void* private_data\r
- );\r
-\r
-typedef u_int32_t EVAPI_async_handler_hndl_t; /* EVAPI async event handler handle */\r
-\r
-\r
-/* HCA Verbs returns values */\r
-#define VAPI_ERROR_LIST \\r
-VAPI_ERROR_INFO( VAPI_OK, = 0 ,"Operation Completed Successfully") \\r
-VAPI_ERROR_INFO( VAPI_EGEN, =-255,"Generic error") \\r
-VAPI_ERROR_INFO( VAPI_EFATAL, EMPTY,"Fatal error (Local Catastrophic Error)") \\r
-VAPI_ERROR_INFO( VAPI_EAGAIN, EMPTY,"Resources temporary unavailable") \\r
-VAPI_ERROR_INFO( VAPI_ENOMEM, EMPTY,"Not enough memory") \\r
-VAPI_ERROR_INFO( VAPI_EBUSY, EMPTY,"Resource is busy") \\r
-VAPI_ERROR_INFO( VAPI_ETIMEOUT, EMPTY,"Operation timedout") \\r
-VAPI_ERROR_INFO( VAPI_EINTR, EMPTY,"Operation interrupted") \\r
-VAPI_ERROR_INFO( VAPI_EPERM, EMPTY,"Not enough permissions to perform operation")\\r
-VAPI_ERROR_INFO( VAPI_ENOSYS, EMPTY,"Not implemented") \\r
-VAPI_ERROR_INFO( VAPI_ESYSCALL, EMPTY,"Error in an underlying O/S call") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_PARAM, EMPTY,"Invalid Parameter") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_HCA_HNDL, EMPTY,"Invalid HCA Handle.") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_HCA_ID, EMPTY,"Invalid HCA identifier") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_COUNTER, EMPTY,"Invalid key counter index") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_COUNT_VAL, EMPTY,"Invalid counter value") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_PD_HNDL, EMPTY,"Invalid Protection Domain") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_RD_UNSUPPORTED, EMPTY,"RD is not supported") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_RDD_HNDL, EMPTY,"Invalid Reliable Datagram Domain") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_AV_HNDL, EMPTY,"Invalid Address Vector Handle") \\r
-VAPI_ERROR_INFO( VAPI_E2BIG_WR_NUM, EMPTY,"Max. WR number exceeds capabilities") \\r
-VAPI_ERROR_INFO( VAPI_E2BIG_SG_NUM, EMPTY,"Max. SG size exceeds capabilities") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_SERVICE_TYPE, EMPTY,"Invalid Service Type") \\r
-VAPI_ERROR_INFO( VAPI_ENOSYS_ATTR, EMPTY,"Unsupported attribute") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_ATTR, EMPTY,"Can not change attribute") \\r
-VAPI_ERROR_INFO( VAPI_ENOSYS_ATOMIC, EMPTY,"Atomic operations not supported") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_PKEY_IX, EMPTY,"Pkey index out of range") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_PKEY_TBL_ENTRY, EMPTY,"Pkey index point to invalid Pkey") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_QP_HNDL, EMPTY,"Invalid QP Handle") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_QP_STATE, EMPTY,"Invalid QP State") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_SRQ_HNDL, EMPTY,"Invalid SRQ Handle") \\r
-VAPI_ERROR_INFO( VAPI_ESRQ, EMPTY,"SRQ is in error state") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_EEC_HNDL, EMPTY,"Invalid EE-Context Handle") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_MIG_STATE, EMPTY,"Invalid Path Migration State") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_MTU, EMPTY,"MTU violation") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_PORT, EMPTY,"Invalid Port Number") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_RNR_NAK_TIMER, EMPTY,"Invalid RNR NAK timer field") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_LOCAL_ACK_TIMEOUT, EMPTY,"Invalid Local ACK timeout field") \\r
-VAPI_ERROR_INFO( VAPI_E2BIG_RAW_DGRAM_NUM, EMPTY,"Number of raw datagrams QP exeeded") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_QP_TYPE, EMPTY,"Invalid special QP type") \\r
-VAPI_ERROR_INFO( VAPI_ENOSYS_RAW, EMPTY,"Raw datagram QP not supported") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_CQ_HNDL, EMPTY,"Invalid Completion Queue Handle") \\r
-VAPI_ERROR_INFO( VAPI_E2BIG_CQ_NUM, EMPTY,"Number of entries in CQ exceeds Cap.") \\r
-VAPI_ERROR_INFO( VAPI_CQ_EMPTY, EMPTY,"CQ is empty") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_VA, EMPTY,"Invalid Virtual Address") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_LEN, EMPTY,"Invalid length") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_ACL, EMPTY,"Invalid ACL") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_PADDR, EMPTY,"Invalid physical address") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_OFST, EMPTY,"Invalid offset") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_MR_HNDL, EMPTY,"Invalid Memory Region Handle") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_MW_HNDL, EMPTY,"Invalid Memory Window Handle") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_OP, EMPTY,"Invalid operation") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_NOTIF_TYPE, EMPTY,"Invalid completion notification type") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_SG_FMT, EMPTY,"Invalid scatter/gather list format") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_SG_NUM, EMPTY,"Invalid scatter/gather list length") \\r
-VAPI_ERROR_INFO( VAPI_E2BIG_MCG_SIZE, EMPTY,"Number of QPs attached to multicast groups exceeded") \\r
-VAPI_ERROR_INFO( VAPI_EINVAL_MCG_GID, EMPTY,"Invalid Multicast group GID") \\r
-VAPI_ERROR_INFO( VAPI_COMPLETED, EMPTY,"Poll Loop Completed") \\r
-VAPI_ERROR_INFO( VAPI_POLL_NEEDED, EMPTY,"Drain CQ with poll_cq") \\r
-VAPI_ERROR_INFO( VAPI_EOL, EMPTY,"End Of List") \\r
-VAPI_ERROR_INFO( VAPI_ERROR_MAX, EMPTY,"Dummy max error code : put all error codes before it") \\r
- \r
-enum {\r
-#define VAPI_ERROR_INFO(A, B, C) A B,\r
- VAPI_ERROR_LIST\r
-#undef VAPI_ERROR_INFO\r
- VAPI_ERROR_DUMMY_CODE\r
-};\r
-\r
-typedef int32_t VAPI_ret_t;\r
-\r
-typedef struct {\r
- u_int32_t vendor_id; /* Vendor ID */\r
- u_int32_t vendor_part_id; /* Vendor Part ID */\r
- u_int32_t hw_ver; /* Hardware Version */\r
- u_int64_t fw_ver; /* Device's firmware version (device specific) */\r
-} VAPI_hca_vendor_t; \r
-\r
-/* HCA Port properties (port db) */\r
-typedef struct {\r
- IB_mtu_t max_mtu; /* Max MTU */\r
- u_int32_t max_msg_sz; /* Max message size */\r
- IB_lid_t lid; /* Base IB_LID. */\r
- u_int8_t lmc; /* IB_LMC for port. */ \r
- IB_port_state_t state; /* Port state */\r
- IB_port_cap_mask_t capability_mask; \r
- u_int8_t max_vl_num; /* Maximum number of VL supported by this port. */ \r
- VAPI_key_counter_t bad_pkey_counter; /* Bad PKey counter (if supported) */\r
- VAPI_key_counter_t qkey_viol_counter; /* QKey violation counter */\r
- IB_lid_t sm_lid; /* IB_LID of subnet manager to be used for this prot. */\r
- IB_sl_t sm_sl; /* IB_SL to be used in communication with subnet manager. */\r
- u_int16_t pkey_tbl_len; /* Current size of pkey table */\r
- u_int16_t gid_tbl_len; /* Current size of GID table */\r
- VAPI_timeout_t subnet_timeout; /* Subnet Timeout for this port (see PortInfo) */\r
- u_int8_t initTypeReply; /* optional InitTypeReply value. 0 if not supported */\r
-} VAPI_hca_port_t; \r
-\r
-/* HCA Capabilities Structure */\r
-typedef struct {\r
- u_int32_t max_num_qp; /* Maximum Number of QPs supported. */ \r
- u_int32_t max_qp_ous_wr; /* Maximum Number of oustanding WR on any WQ. */ \r
- u_int32_t flags; /* Various flags (VAPI_hca_cap_flags_t) */\r
- u_int32_t max_num_sg_ent; /* Max num of scatter/gather entries for desc other than RD */\r
- u_int32_t max_num_sg_ent_rd; /* Max num of scatter/gather entries for RD desc */\r
- u_int32_t max_num_cq; /* Max num of supported CQs */\r
- u_int32_t max_num_ent_cq; /* Max num of supported entries per CQ */\r
- u_int32_t max_num_mr; /* Maximum number of memory region supported. */ \r
- u_int64_t max_mr_size; /* Largest contigous block of memory region in bytes. */ \r
- u_int32_t max_pd_num; /* Maximum number of protection domains supported. */ \r
- u_int32_t page_size_cap; /* Largest page size supported by this HCA */ \r
- IB_port_t phys_port_num; /* Number of physical port of the HCA. */ \r
- u_int16_t max_pkeys; /* Maximum number of partitions supported . */\r
- IB_guid_t node_guid; /* Node GUID for this hca */\r
- VAPI_timeout_t local_ca_ack_delay; /* Log2 4.096usec Max. RX to ACK or NAK delay */\r
- u_int8_t max_qp_ous_rd_atom; /* Maximum number of oust. RDMA read/atomic as target */ \r
- u_int8_t max_ee_ous_rd_atom; /* EE Maximum number of outs. RDMA read/atomic as target */ \r
- u_int8_t max_res_rd_atom; /* Max. Num. of resources used for RDMA read/atomic as target */\r
- u_int8_t max_qp_init_rd_atom; /* Max. Num. of outs. RDMA read/atomic as initiator */\r
- u_int8_t max_ee_init_rd_atom; /* EE Max. Num. of outs. RDMA read/atomic as initiator */\r
- VAPI_atomic_cap_t atomic_cap; /* Level of Atomicity supported */\r
- u_int32_t max_ee_num; /* Maximum number of EEC supported. */\r
- u_int32_t max_rdd_num; /* Maximum number of IB_RDD supported */\r
- u_int32_t max_mw_num; /* Maximum Number of memory windows supported */\r
- u_int32_t max_raw_ipv6_qp; /* Maximum number of Raw IPV6 QPs supported */ \r
- u_int32_t max_raw_ethy_qp; /* Maximum number of Raw Ethertypes QPs supported */ \r
- u_int32_t max_mcast_grp_num; /* Maximum Number of multicast groups */ \r
- u_int32_t max_mcast_qp_attach_num; /* Maximum number of QP per multicast group */ \r
- u_int32_t max_total_mcast_qp_attach_num;/* Maximum number of QPs which can be attached to a mcast grp */\r
- u_int32_t max_ah_num; /* Maximum number of address vector handles */\r
-\r
- /* Extended HCA capabilities */\r
-\r
- /* FMRs (Fast Memory Regions) */\r
- u_int32_t max_num_fmr; /* maximum number FMRs */\r
- u_int32_t max_num_map_per_fmr; /* Maximum number of (re)maps per FMR before \r
- an unmap operation in required */\r
- /* SRQs (Shared Receive Queues) */\r
- u_int32_t max_num_srq; /* Maximum number of SRQs. Zero if SRQs are not supported. */\r
- u_int32_t max_wqe_per_srq; /* Maximum number of WRs per SRQ.*/\r
- u_int32_t max_srq_sentries; /* Maximum scatter entries per SRQ WQE */\r
- MT_bool srq_resize_supported;/* Ability to modify the maximum number of WRs per SRQ.*/\r
-\r
-} VAPI_hca_cap_t;\r
-\r
-\r
-/* HCA Properties for Modify HCA verb */\r
-typedef struct {\r
- MT_bool reset_qkey_counter; /* TRUE=> reset counter. FALSE=> do nothing */\r
- /* attributes in Capability Mask of port info that can be modified */\r
- MT_bool is_sm; \r
- MT_bool is_snmp_tun_sup;\r
- MT_bool is_dev_mgt_sup;\r
- MT_bool is_vendor_cls_sup;\r
- MT_bool is_client_reregister_sup;\r
-} VAPI_hca_attr_t; \r
-\r
-\r
-/* Address Vector (For UD AV as well as address-path in connected QPs */\r
-typedef struct { \r
- IB_gid_t dgid MT_BYTE_ALIGN(4); /* Destination GID (alignment for IA64) */\r
- IB_sl_t sl; /* Service Level 4 bits */\r
- IB_lid_t dlid; /* Destination LID */\r
- u_int8_t src_path_bits; /* Source path bits 7 bits */\r
- IB_static_rate_t static_rate; /* Maximum static rate : 6 bits */\r
-\r
- MT_bool grh_flag; /* Send GRH flag */\r
- /* For global destination or Multicast address:*/ \r
- u_int8_t traffic_class; /* TClass 8 bits */\r
- u_int8_t hop_limit; /* Hop Limit 8 bits */\r
- u_int32_t flow_label; /* Flow Label 20 bits */\r
- u_int8_t sgid_index; /* SGID index in SGID table */\r
-\r
- IB_port_t port; /* egress port (valid for UD AV only) */\r
- /* Following IBTA comment 1567 - should match QP's when UD AV port is enforced */\r
-\r
-} VAPI_ud_av_t; \r
-\r
-\r
-/* QP Capabilities */\r
-typedef struct {\r
- u_int32_t max_oust_wr_sq; /* Max outstanding WR on the SQ */\r
- u_int32_t max_oust_wr_rq; /* Max outstanding WR on the RQ */\r
- u_int32_t max_sg_size_sq; /* Max scatter/gather descriptor entries on the SQ */\r
- u_int32_t max_sg_size_rq; /* Max scatter/gather descriptor entries on the RQ */\r
- u_int32_t max_inline_data_sq; /* Max bytes in inline data on the SQ */\r
- /* max_inline_data_sq is currently valid only for VAPI_query_qp (ignored for VAPI_create_qp) */\r
- /* In order to enlarge the max_inline_data_sq capability, enlarge the max_sg_size_sq parameter */\r
-} VAPI_qp_cap_t; \r
-\r
-/* Queue Pair Creation Attributes */\r
-typedef struct {\r
- VAPI_cq_hndl_t sq_cq_hndl; /* CQ handle for the SQ */\r
- VAPI_cq_hndl_t rq_cq_hndl; /* CQ handle for the RQ */\r
- VAPI_qp_cap_t cap; /* Requested QP capabilities */\r
- VAPI_rdd_hndl_t rdd_hndl; /* Reliable Datagram Domain handle */\r
- VAPI_sig_type_t sq_sig_type; /* SQ Signalling type (SIGNAL_ALL_WR, SIGNAL_REQ_WR) */\r
- VAPI_sig_type_t rq_sig_type; /* RQ Signalling type (SIGNAL_ALL_WR, SIGNAL_REQ_WR) [Mellanox Specific]*/\r
- VAPI_pd_hndl_t pd_hndl; /* Protection domain handle */\r
- VAPI_ts_type_t ts_type; /* Transport Services Type */\r
-} VAPI_qp_init_attr_t;\r
-\r
-typedef struct {\r
- VAPI_srq_hndl_t srq_hndl; /* Set to VAPI_INVAL_SRQ_HNDL when QP is not associated with a SRQ */\r
-} VAPI_qp_init_attr_ext_t;\r
-\r
-/* Init. the extended attributes structure with the macro below to assure forward compatibility */\r
-#define VAPI_QP_INIT_ATTR_EXT_T_INIT(qp_ext_attr_p) (qp_ext_attr_p)->srq_hndl= VAPI_INVAL_SRQ_HNDL\r
-\r
-/* Queue Pair Creation Returned actual Attributes */\r
-typedef struct {\r
- VAPI_qp_num_t qp_num; /* QP number */\r
- VAPI_qp_cap_t cap; /* Actual QP capabilities */\r
-} VAPI_qp_prop_t;\r
-\r
-\r
-/* Queue Pair Full Attributes (for modify QP) */\r
-typedef struct {\r
- VAPI_qp_state_t qp_state; /* QP next state */\r
- MT_bool en_sqd_asyn_notif; /* Enable SQD affiliated asynchronous event notification */\r
- MT_bool sq_draining; /* query only - when (qp_state == VAPI_SQD) indicates whether sq is in drain process (TRUE), or drained.*/\r
- VAPI_qp_num_t qp_num; /* Queue Pair Number. [Mellanox specific] */\r
- VAPI_rdma_atom_acl_t remote_atomic_flags;/* Enable/Disable RDMA and atomic */\r
- VAPI_qkey_t qkey; /* QKey (UD/RD only) */\r
- IB_mtu_t path_mtu; /* Path MTU : 6 bits (connected services only) */\r
- VAPI_mig_state_t path_mig_state; /* Migration state */\r
- VAPI_psn_t rq_psn; /* Packet Sequence Number for RQ */\r
- VAPI_psn_t sq_psn; /* Packet sequence number for SQ */\r
- u_int8_t qp_ous_rd_atom; /* Maximum number of oust. RDMA read/atomic as target */\r
- u_int8_t ous_dst_rd_atom; /* Number of outstanding RDMA rd/atomic ops at destination */\r
- IB_rnr_nak_timer_code_t min_rnr_timer; /* Minimum RNR NAK timer */\r
- VAPI_qp_cap_t cap; /* QP capabilities max_sq/rq_ous_wr only valid */\r
- VAPI_qp_num_t dest_qp_num; /* Destination QP number (RC/UC) */\r
- VAPI_sched_queue_t sched_queue; /* Schedule queue (optional) */\r
-\r
- /* Primary path (RC/UC only) */\r
- VAPI_pkey_ix_t pkey_ix; /* Primary PKey index */\r
- IB_port_t port; /* Primary port */\r
- VAPI_ud_av_t av; /* Primary remote node address vector (RC/UC QP only)*/\r
- VAPI_timeout_t timeout; /* Local Ack Timeout (RC only) */\r
- VAPI_retry_count_t retry_count; /* retry count (RC only) */\r
- VAPI_retry_count_t rnr_retry; /* RNR retry count (RC only) */\r
- \r
- /* Alternate path (RC/UC only) */\r
- VAPI_pkey_ix_t alt_pkey_ix; /* Alternative PKey index */\r
- IB_port_t alt_port; /* Alternative port */\r
- VAPI_ud_av_t alt_av; /* Alternate remote node address vector */ \r
- VAPI_timeout_t alt_timeout; /* Local Ack Timeout (RC only) */\r
-} VAPI_qp_attr_t;\r
-\r
-/* SRQ's attributes */\r
-typedef struct {\r
- VAPI_pd_hndl_t pd_hndl; /* SRQ's PD. (Ignored on VAPI_modify_srq). */\r
- u_int32_t max_outs_wr; /* Max. outstanding WQEs */\r
- u_int32_t max_sentries;/* Max. scatter entries (Ignored on VAPI_modify_srq) */\r
- u_int32_t srq_limit; /* SRQ's limit (Ignored on VAPI_create_srq) */\r
-} VAPI_srq_attr_t;\r
-\r
-#define VAPI_SRQ_ATTR_T_INIT(srq_attr_p) { \\r
- (srq_attr_p)->pd_hndl= VAPI_INVAL_PD_HNDL; \\r
- (srq_attr_p)->max_outs_wr= 0; \\r
- (srq_attr_p)->max_sentries= 0; \\r
- (srq_attr_p)->srq_limit= 0; \\r
-}\r
-\r
-/* VAPI_modify_srq attributes mask */\r
-#define VAPI_SRQ_ATTR_LIMIT (1)\r
-#define VAPI_SRQ_ATTR_MAX_OUTS_WR (1<<1)\r
-typedef u_int8_t VAPI_srq_attr_mask_t;\r
-\r
-\r
-/* Physical memory buffer */\r
-typedef struct {\r
- VAPI_phy_addr_t start;\r
- VAPI_phy_addr_t size;\r
-} VAPI_phy_buf_t;\r
-\r
-\r
-/* Memory Region/Window */\r
-typedef struct {\r
- VAPI_mrw_type_t type; /* But not VAPI_MW */\r
- VAPI_lkey_t l_key; \r
- VAPI_rkey_t r_key;\r
- VAPI_virt_addr_t start;\r
- VAPI_size_t size;\r
- VAPI_pd_hndl_t pd_hndl;\r
- VAPI_mrw_acl_t acl; \r
- /* Physical buffers list : for physical memory region only (type==VAPI_MPR) */\r
- MT_size_t pbuf_list_len;\r
- VAPI_phy_buf_t *pbuf_list_p;\r
- VAPI_phy_addr_t iova_offset; /* Offset of "start" in first buffer */\r
-} VAPI_mr_t;\r
-\r
-typedef VAPI_mr_t VAPI_mrw_t; /* for backward compatibility */\r
-\r
-typedef struct\r
-{\r
- VAPI_lkey_t mr_lkey; /* L-Key of memory region to bind to */\r
- IB_virt_addr_t start; /* Memory window's virtual byte address */\r
- VAPI_size_t size; /* Size of memory window in bytes */\r
- VAPI_mrw_acl_t acl; /* Access Control (R/W permission - local/remote) */\r
-} VAPI_mw_bind_t;\r
-\r
-\r
-/* Scatter/ Gather Entry */\r
-typedef struct {\r
- VAPI_virt_addr_t addr;\r
- u_int32_t len;\r
- VAPI_lkey_t lkey;\r
-} VAPI_sg_lst_entry_t;\r
-\r
-/* Send Request Descriptor */\r
-typedef struct {\r
- VAPI_wr_id_t id;\r
- VAPI_wr_opcode_t opcode;\r
- VAPI_comp_type_t comp_type;\r
- VAPI_sg_lst_entry_t *sg_lst_p;\r
- u_int32_t sg_lst_len;\r
- VAPI_imm_data_t imm_data;\r
- MT_bool fence;\r
- VAPI_ud_av_hndl_t remote_ah;\r
- VAPI_qp_num_t remote_qp;\r
- VAPI_qkey_t remote_qkey;\r
- VAPI_ethertype_t ethertype;\r
- IB_eecn_t eecn;\r
- MT_bool set_se;\r
- VAPI_virt_addr_t remote_addr;\r
- VAPI_rkey_t r_key;\r
- /* atomic_operands */\r
- u_int64_t compare_add; /* First operand: Used for both "Compare & Swap" and "Fetch & Add" */\r
- u_int64_t swap; /* Second operand: Used for "Compare & Swap" */\r
- /* Atomic's "data segment" is the scather list defined in sg_lst_p+sg_lst_len (like RDMA-Read) */\r
-} VAPI_sr_desc_t;\r
-\r
-/* Receive Request Descriptor */\r
-typedef struct {\r
- VAPI_wr_id_t id;\r
- VAPI_wr_opcode_t opcode; /* RECEIVE */\r
- VAPI_comp_type_t comp_type; /* Mellanox Specific */\r
- VAPI_sg_lst_entry_t *sg_lst_p;\r
- u_int32_t sg_lst_len;\r
-} VAPI_rr_desc_t;\r
-\r
-/* Remote node address for completion entry */\r
-typedef struct {\r
- VAPI_remote_node_addr_type_t type;\r
- IB_lid_t slid;\r
- IB_sl_t sl;\r
-\r
- union {\r
- VAPI_qp_num_t qp; /* source QP (valid on type==RD,UD) */\r
- VAPI_ethertype_t ety; /* ethertype (valid on type==RAW_ETY) */\r
- } qp_ety;\r
-\r
- union {\r
- VAPI_eec_num_t loc_eecn; /* local EEC number (valid on type==RD) */\r
- u_int8_t dst_path_bits; /* dest path bits (valid on type==UD and RAW* ) */\r
- } ee_dlid;\r
-} VAPI_remote_node_addr_t;\r
-\r
-\r
-/* Work Completion Descriptor */\r
-typedef struct {\r
- VAPI_wc_status_t status;\r
- VAPI_wr_id_t id;\r
- IB_wqpn_t local_qp_num; /* QP number this completion was generated for */\r
- VAPI_cqe_opcode_t opcode; \r
- u_int32_t byte_len; /* Num. of bytes transferred */\r
- MT_bool imm_data_valid; /* Imm. data indicator */\r
- VAPI_imm_data_t imm_data;\r
- VAPI_remote_node_addr_t remote_node_addr;\r
- MT_bool grh_flag; \r
- VAPI_pkey_ix_t pkey_ix; /* for GSI */\r
- /* Vendor specific error syndrome (valid when status != VAPI_SUCCESS) */\r
- EVAPI_vendor_err_syndrome_t vendor_err_syndrome; \r
- u_int32_t free_res_count;\r
-} VAPI_wc_desc_t;\r
-\r
-\r
-\r
-/**********************************/\r
-/* Fast memory regions data types */\r
-/**********************************/\r
-\r
-typedef struct {\r
- VAPI_pd_hndl_t pd_hndl;\r
- VAPI_mrw_acl_t acl; \r
- u_int32_t max_pages; /* Maximum number of pages that can be mapped using this region *\r
- *(virtual mapping only) */\r
- u_int8_t log2_page_sz; /* Fixed page size for all maps on a given FMR */\r
- u_int32_t max_outstanding_maps; /* Maximum maps before invoking unmap for this region */\r
-} EVAPI_fmr_t;\r
-\r
-typedef struct {\r
- VAPI_virt_addr_t start; /* Mapped memory virtual address */\r
- VAPI_size_t size; /* Size of memory mapped to this region */\r
- MT_size_t page_array_len; /* If >0 then no memory locking is done and page table is taken from array below */\r
- VAPI_phy_addr_t *page_array; /* Page size is set in EVAPI_alloc_fmr by log2_page_sz field */ \r
-} EVAPI_fmr_map_t;\r
-\r
-typedef VAPI_mr_hndl_t EVAPI_fmr_hndl_t;\r
-\r
-\r
-typedef struct {\r
- VAPI_size_t total_mem;\r
- VAPI_size_t free_mem;\r
- VAPI_size_t largest_chunk;\r
-} EVAPI_devmem_info_t;\r
-\r
-\r
-\r
-/*EVAPI_process_local_mad options*/\r
-\r
-/* enumeration of options (effectively, bits in a bitmask) */\r
-typedef enum {\r
- EVAPI_MAD_IGNORE_MKEY = 1 /* process_local_mad will not validate the MKEY */\r
-} EVAPI_proc_mad_opt_enum_t;\r
-\r
-/* Associated "bitmask" type for use in structs and argument lists */\r
-typedef u_int32_t EVAPI_proc_mad_opt_t;\r
-\r
-\r
-/* profile typedef */\r
-\r
-typedef struct EVAPI_hca_profile_t {\r
- u_int32_t num_qp; /* min number of QPs to configure */\r
- u_int32_t num_cq; /* min number of CQs to configure */\r
- u_int32_t num_pd; /* min number of PDs to configure */\r
- u_int32_t num_mr; /* min number of mem regions to configure */\r
- u_int32_t num_mw; /* min number of mem windows to configure */\r
- u_int32_t max_qp_ous_rd_atom; /* max outstanding read/atomic operations as target PER QP */\r
- u_int32_t max_mcg; /* max number of multicast groups for this HCA */\r
- u_int32_t qp_per_mcg; /* max number of QPs per mcg */\r
- MT_bool require; /* if TRUE, EVAPI_open_hca will fail if cannot use exact profile values\r
- to open the HCA */\r
-} EVAPI_hca_profile_t;\r
-\r
-\r
-#endif /*H_VAPI_TYPES_H*/\r
\r
-DIRS=\\r
- user \\r
- kernel\r
-#\r
-# DO NOT EDIT THIS FILE!!! Edit .\sources. if you want to add a new source\r
-# file to this component. This file merely indirects to the real make file\r
-# that is shared by all the driver components of the OpenIB Windows project.\r
-#\r
-\r
-!INCLUDE ..\..\..\..\inc\openib.def\r
-TARGETNAME=mt23108\r
-TARGETPATH=..\..\..\..\bin\kernel\obj$(BUILD_ALT_DIR)\r
-TARGETTYPE=EXPORT_DRIVER\r
-\r
-DLLDEF=mt23108.def\r
-\r
-SOURCES= \\r
- mtl_common_kl_sources.c \\r
- mosal_kl_sources.c \\r
- mpga_kl_sources.c \\r
- hh_kl_sources.c \\r
- thh_kl_sources.c \\r
- thhul_kl_sources.c \\r
- vapi_common_kl_sources.c \\r
- tdriver_sources.c \\r
- mt23108.rc\r
-\r
-MT_HOME=..\r
-MDT_HOME=$(MT_HOME)\mlxsys\os_dep\win\tdriver\r
-MOSAL_HOME=$(MT_HOME)\mlxsys\mosal\os_dep\win\r
-THH_HOME=$(MT_HOME)\hca\hcahal\tavor\r
-\r
-INCLUDES=.;..\..\kernel; \\r
- ..\..\..\..\inc;..\..\..\..\inc\kernel; \\r
- $(MT_HOME)\mlxsys\tools; \\r
- $(MT_HOME)\tavor_arch_db; \\r
- $(MT_HOME)\Hca\verbs; \\r
- $(MT_HOME)\Hca\verbs\common; \\r
- $(MT_HOME)\mlxsys\mpga\os_dep\win; \\r
- $(MT_HOME)\mlxsys\mpga; \\r
- $(MT_HOME)\mlxsys\mtl_types; \\r
- $(MT_HOME)\mlxsys\mtl_types\win; \\r
- $(MT_HOME)\mlxsys\mtl_types\win\win; \\r
- $(MT_HOME)\mlxsys\mtl_common; \\r
- $(MT_HOME)\mlxsys\mtl_common\os_dep\win; \\r
- $(MT_HOME)\mlxsys\mosal; \\r
- $(MT_HOME)\mlxsys\mosal\os_dep\win; \\r
- $(MT_HOME)\Hca\hcahal; \\r
- $(THH_HOME); \\r
- $(THH_HOME)\util; \\r
- $(THH_HOME)\thh_hob; \\r
- $(THH_HOME)\cmdif; \\r
- $(THH_HOME)\eventp; \\r
- $(THH_HOME)\uar; \\r
- $(THH_HOME)\mrwm; \\r
- $(THH_HOME)\thh_cqm; \\r
- $(THH_HOME)\udavm; \\r
- $(THH_HOME)\mcgm; \\r
- $(THH_HOME)\ddrmm; \\r
- $(THH_HOME)\thh_qpm; \\r
- $(THH_HOME)\thh_srqm; \\r
- $(THH_HOME)\uldm; \\r
- $(THH_HOME)\thhul_hob; \\r
- $(THH_HOME)\thhul_pdm; \\r
- $(THH_HOME)\thhul_cqm; \\r
- $(THH_HOME)\thhul_qpm; \\r
- $(THH_HOME)\thhul_mwm; \\r
- $(THH_HOME)\thhul_srqm; \\r
- $(THH_HOME)\os_dep\win; \\r
- $(MDT_HOME);\r
- \r
-C_DEFINES=$(C_DEFINES) -DDRIVER -D__MSC__ \\r
- -D__KERNEL__ -DMT_KERNEL -D__WIN__ -D__LITTLE_ENDIAN -DMT_LITTLE_ENDIAN \\r
- -DMAX_ERROR=4 -DIVAPI_THH \\r
- -DMTL_MODULE=MDT -DUSE_MOSAL -DMT_BUILD_LIB -D__DLL_EXPORTS__ \\r
- -DUSE_KMUTEX -DSIMULTANUOUS_DPC -DMAP_PHYS_ADDR_VIA_KERNEL\r
-\r
-TARGETLIBS=$(TARGETPATH)\*\complib.lib\r
-\r
-MSC_WARNING_LEVEL= /W3\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-/* \r
- * Include all files that are not in the current directory.\r
- */\r
-\r
-#include "../hca/hcahal/hh.c"\r
-#include "../hca/hcahal/hh_common.c"\r
-/*++\r
-====================================================================================\r
-Copyright (c) 2001 Mellanox Technologies\r
-\r
-Module Name:\r
-\r
- MdMsg.mc\r
-\r
-Abstract:\r
-\r
- MDDL Driver event log messages\r
-\r
-Authors:\r
-\r
- Leonid Keller\r
-\r
-Environment:\r
-\r
- User Mode .\r
-\r
-=====================================================================================\r
---*/\r
-\r
-//\r
-// Values are 32 bit values layed out as follows:\r
-//\r
-// 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1\r
-// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0\r
-// +---+-+-+-----------------------+-------------------------------+\r
-// |Sev|C|R| Facility | Code |\r
-// +---+-+-+-----------------------+-------------------------------+\r
-//\r
-// where\r
-//\r
-// Sev - is the severity code\r
-//\r
-// 00 - Success\r
-// 01 - Informational\r
-// 10 - Warning\r
-// 11 - Error\r
-//\r
-// C - is the Customer code flag\r
-//\r
-// R - is a reserved bit\r
-//\r
-// Facility - is the facility code\r
-//\r
-// Code - is the facility's status code\r
-//\r
-//\r
-// Define the facility codes\r
-//\r
-#define FACILITY_RPC_STUBS 0x3\r
-#define FACILITY_RPC_RUNTIME 0x2\r
-#define FACILITY_MD_ERROR_CODE 0x7\r
-#define FACILITY_IO_ERROR_CODE 0x4\r
-\r
-\r
-//\r
-// Define the severity codes\r
-//\r
-#define STATUS_SEVERITY_WARNING 0x2\r
-#define STATUS_SEVERITY_SUCCESS 0x0\r
-#define STATUS_SEVERITY_INFORMATIONAL 0x1\r
-#define STATUS_SEVERITY_ERROR 0x3\r
-\r
-\r
-//\r
-// MessageId: MD_EVENT_LOG_LOAD_OK\r
-//\r
-// MessageText:\r
-//\r
-// The Mellanox InfiniHost Driver has loaded Successfully.\r
-//\r
-#define MD_EVENT_LOG_LOAD_OK ((NTSTATUS)0x40070001L)\r
-\r
-//\r
-// MessageId: MD_EVENT_LOG_LOAD_ERROR\r
-//\r
-// MessageText:\r
-//\r
-// The Mellanox InfiniHost Driver has failed to load\r
-//\r
-#define MD_EVENT_LOG_LOAD_ERROR ((NTSTATUS)0xC0070002L)\r
-\r
-//\r
-// MessageId: MD_EVENT_LOG_LOAD_ERROR_FW\r
-//\r
-// MessageText:\r
-//\r
-// The Mellanox InfiniHost Driver has failed to load: THH_add_hca failed. Check FW.\r
-//\r
-#define MD_EVENT_LOG_LOAD_ERROR_FW ((NTSTATUS)0xC0070003L)\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-/* \r
- * Include all files that are not in the current directory.\r
- */\r
-\r
-#include "../mlxsys/mosal/mosal_gen_nos.c"\r
-#include "../mlxsys/mosal/os_dep/win/mosal_bus.c"\r
-#include "../mlxsys/mosal/os_dep/win/mosal_timer.c"\r
-#include "../mlxsys/mosal/os_dep/win/mosal_mem.c"\r
-#include "../mlxsys/mosal/os_dep/win/mosal_que.c"\r
-#include "../mlxsys/mosal/os_dep/win/mosal_sync.c"\r
-#include "../mlxsys/mosal/os_dep/win/mosal_gen.c"\r
-#include "../mlxsys/mosal/os_dep/win/mosal_k2u_cbk.c"\r
-#include "../mlxsys/mosal/os_dep/win/mosal_mlock.c"\r
-#include "../mlxsys/mosal/os_dep/win/mosal_util.c"\r
-#include "../mlxsys/mosal/os_dep/win/mosal_thread.c"\r
-#include "../mlxsys/mosal/os_dep/win/mosal_iobuf.c"\r
-#include "../mlxsys/mosal/os_dep/win/mosal_ntddk.c"\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-/* \r
- * Include all files that are not in the current directory.\r
- */\r
-\r
-#include "../mlxsys/mpga/mpga.c"\r
-#include "../mlxsys/mpga/packet_append.c"\r
-#include "../mlxsys/mpga/internal_functions.c"\r
-#include "../mlxsys/mpga/packet_utilities.c"\r
-#include "../mlxsys/mpga/nMPGA_packet_append.c"\r
-#include "../mlxsys/mpga/nMPGA.c"\r
-LIBRARY mt23108.sys\r
-\r
-EXPORTS\r
-; DllInitialize and DllUnload must be exported for the OS reference counting to\r
-; work, and must be private for the compiler to accept them.\r
-DllInitialize private\r
-DllUnload private\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#include <oib_ver.h>\r
-\r
-#define VER_FILETYPE VFT_DRV\r
-#define VER_FILESUBTYPE VFT2_UNKNOWN\r
-\r
-#ifdef _DEBUG_\r
-#define VER_FILEDESCRIPTION_STR "Tavor HCA Function Driver (Debug)"\r
-#else\r
-#define VER_FILEDESCRIPTION_STR "Tavor HCA Function Driver"\r
-#endif\r
-\r
-#define VER_INTERNALNAME_STR "mt23108.sys"\r
-#define VER_ORIGINALFILENAME_STR "mt23108.sys"\r
-\r
-#include <common.ver>\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-/* \r
- * Include all files that are not in the current directory.\r
- */\r
-\r
-#include "../mlxsys/mtl_common/mtl_common.c"\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-/* \r
- * Include all files that are not in the current directory.\r
- */\r
-\r
-#include "../mlxsys/os_dep/win/tdriver/Md.c"\r
-#include "../mlxsys/os_dep/win/tdriver/MdDbg.c"\r
-#include "../mlxsys/os_dep/win/tdriver/MdIoctl.c"\r
-#include "../mlxsys/os_dep/win/tdriver/MdPnp.c"\r
-#include "../mlxsys/os_dep/win/tdriver/MdPwr.c"\r
-#include "../mlxsys/os_dep/win/tdriver/MdRdWr.c"\r
-#include "../mlxsys/os_dep/win/tdriver/MdUtil.c"\r
-#include "../mlxsys/os_dep/win/tdriver/MdConf.c"\r
-#include "../mlxsys/os_dep/win/tdriver/MdPci.c"\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-/* \r
- * Include all files that are not in the current directory.\r
- */\r
-#include "../hca/hcahal/tavor/thh_init.c"\r
-#include "../hca/hcahal/tavor/thh_hob/thh_hob.c"\r
-#include "../hca/hcahal/tavor/cmdif/cmdif.c"\r
-#include "../hca/hcahal/tavor/cmdif/cmds_wrap.c"\r
-#include "../hca/hcahal/tavor/eventp/eventp.c"\r
-#include "../hca/hcahal/tavor/eventp/event_irqh.c"\r
-#include "../hca/hcahal/tavor/uar/uar.c"\r
-#include "../hca/hcahal/tavor/ddrmm/tddrmm.c"\r
-#include "../hca/hcahal/tavor/uldm/thh_uldm.c"\r
-#include "../hca/hcahal/tavor/mrwm/tmrwm.c"\r
-#include "../hca/hcahal/tavor/thh_cqm/tcqm.c"\r
-#include "../hca/hcahal/tavor/thh_qpm/tqpm.c"\r
-#include "../hca/hcahal/tavor/thh_srqm/thh_srqm.c"\r
-#include "../hca/hcahal/tavor/udavm/udavm.c"\r
-#include "../hca/hcahal/tavor/mcgm/mcgm.c"\r
-#include "../hca/hcahal/tavor/os_dep/win/thh_mod_obj.c"\r
-#include "../hca/hcahal/tavor/util/tlog2.c"\r
-#include "../hca/hcahal/tavor/util/epool.c"\r
-#include "../hca/hcahal/tavor/util/sm_mad.c"\r
-#include "../hca/hcahal/tavor/util/extbuddy.c"\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-/* \r
- * Include all files that are not in the current directory.\r
- */\r
-#include "../hca/hcahal/tavor/thhul_hob/thhul_hob.c"\r
-#include "../hca/hcahal/tavor/thhul_pdm/thhul_pdm.c"\r
-#include "../hca/hcahal/tavor/thhul_cqm/thhul_cqm.c"\r
-#include "../hca/hcahal/tavor/thhul_srqm/thhul_srqm.c"\r
-#include "../hca/hcahal/tavor/thhul_qpm/thhul_qpm.c"\r
-#include "../hca/hcahal/tavor/thhul_mwm/thhul_mwm.c"\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-/* \r
- * Include all files that are not in the current directory.\r
- */\r
-\r
-#include "../hca/verbs/common/vip_array.c"\r
-#include "../hca/verbs/common/vip_hash.c"\r
-#include "../hca/verbs/common/vip_cirq.c"\r
-#include "../hca/verbs/common/vip_delay_unlock.c"\r
-#include "../hca/verbs/common/vapi_common.c"\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_H\r
-#define H_MOSAL_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/* ----- common stuff ----- */\r
-#include <mtl_common.h>\r
-\r
-/* ----- OS-dependent implementation ----- */\r
-#ifndef MT_KERNEL\r
-#include <complib/cl_spinlock.h>\r
-/* Initialization of user level library. \r
- * For dynamic linking, invoked via _init/DllMain. \r
- * For static linking, user/application (or another init point) must invoke this \r
- * function before any invocation of of MOSAL functions.\r
- */\r
-extern void MOSAL_user_lib_init(void); \r
-#endif\r
-\r
-#include <mosal_prot_ctx_imp.h>\r
-#include <mosal_prot_ctx.h>\r
-\r
-#include <mosal_sync_imp.h>\r
-#include <mosal_mem_imp.h>\r
-#include <mosal_iobuf_imp.h>\r
-\r
-\r
-#include <mosal_timer_imp.h>\r
-\r
-\r
-#include <mosal_thread_imp.h>\r
-//#include <mosalu_socket_imp.h>\r
-\r
-\r
-/* ----- mosal OS-specific types ----- */\r
-#include <mosal_types.h>\r
-\r
-/* ----- bus access ----- */\r
-#include <mosal_bus.h>\r
-\r
-/* ----- interrupts, DPC and timers ----- */\r
-#include <mosal_timer.h>\r
-\r
-/* ----- memory services ----- */\r
-#include <mosal_arch.h>\r
-#include <mosal_mem.h>\r
-#include <mosal_iobuf.h>\r
-#include <mosal_mlock.h>\r
-\r
-/* ----- queue management ----- */\r
-#include <mosal_que.h>\r
-\r
-/* ----- synchronization routines ----- */\r
-#include <mosal_sync.h>\r
-\r
-\r
-/* ----- thread routines ----- */\r
-#include <mosal_thread.h>\r
-\r
-/* ----- socket routines ----- */\r
-//#include <mosalu_socket.h>\r
-\r
-\r
-#if !defined(VXWORKS_OS)\r
-#include <mosal_i2c.h>\r
-#endif\r
-\r
-\r
-#ifndef MT_KERNEL_ONLY\r
-\r
-/* callback management */\r
-#include <mosal_k2u_cbk.h>\r
-\r
-#endif\r
-\r
-/* ----- driver services ----- */\r
-#ifdef __LINUX__\r
-#include <mosal_driver.h>\r
-#endif\r
-\r
-/* ----- general services ----- */\r
-#include <mosal_gen.h>\r
-#ifdef __WIN__\r
-#include <mosal_ntddk.h>\r
-#endif\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* H_MOSAL_H */\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_GEN_H\r
-#define H_MOSAL_GEN_H\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only): MOSAL_init\r
- *\r
- * Description:\r
- * Init of mosal\r
- *\r
- * Parameters: \r
- * major(IN) unsigned int\r
- * device major number \r
- * khz(IN) cpu frequency in khz\r
- *\r
- * Returns:\r
- * call_result_t\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_init(unsigned int major);\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only): MOSAL_cleanup\r
- *\r
- * Description:\r
- * Cleanup of mosal niternal struct\r
- *\r
- * Parameters: \r
- *\r
- * Returns:\r
- * call_result_t\r
- *\r
- ******************************************************************************/\r
-void MOSAL_cleanup(void);\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_is_privileged\r
- *\r
- * Description: Check if current processing context is privileged.\r
- * Use this function whenever operation should be limited to privileged\r
- * users, e.g., root/administrator etc. The function gets no parameters\r
- * as it relies on context of current process/thread. On systems with no\r
- * levels of flat hierarchy, this should always return TRUE.\r
- *\r
- * Parameters: (none).\r
- *\r
- * Returns:\r
- * MT_bool\r
- * TRUE if privileged user/context, FALSE if not.\r
- *\r
- ******************************************************************************/\r
-MT_bool MOSAL_is_privileged(void);\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only): MOSAL_getpid\r
- *\r
- * Description:\r
- * Wrapper to getpid\r
- *\r
- * Parameters: (none)\r
- *\r
- * Returns:\r
- * MOSAL_pid_t\r
- *\r
- ******************************************************************************/\r
-MOSAL_pid_t MOSAL_getpid(void);\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_setpid\r
- *\r
- * Description:\r
- * set current pid\r
- *\r
- * Parameters: \r
- * pid(IN) MOSAL_pid_t\r
- * points to the list head\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-void MOSAL_setpid(MOSAL_pid_t pid);\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_letobe64 \r
- *\r
- * Description:\r
- * ULONG conversion from little endian to big endian \r
- *\r
- * Parameters: \r
- * value(IN) u_int64_t\r
- *\r
- * Returns:\r
- * u_int64_t\r
- *\r
- ******************************************************************************/\r
-u_int64_t MOSAL_letobe64( u_int64_t value );\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_letobe32 \r
- *\r
- * Description:\r
- * ULONG conversion from little endian to big endian \r
- *\r
- * Parameters: \r
- * value(IN) u_int32_t\r
- *\r
- * Returns:\r
- * u_int32_t\r
- *\r
- ******************************************************************************/\r
-u_int32_t MOSAL_letobe32( u_int32_t value );\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_letobe16 \r
- *\r
- * Description:\r
- * USHORT conversion from little endian to big endian \r
- *\r
- * Parameters: \r
- * value(IN) u_int16_t\r
- *\r
- * Returns:\r
- * u_int16_t\r
- *\r
- ******************************************************************************/\r
-u_int16_t MOSAL_letobe16( u_int16_t value );\r
-\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only): MOSAL_betole32\r
- *\r
- * Description:\r
- * convert from big endian representation to little endian representation\r
- *\r
- * Parameters:\r
- * be(IN) number to be transformed\r
- *\r
- * Returns:\r
- * u_int32_t\r
- *\r
- ******************************************************************************/\r
-u_int32_t MOSAL_betole32(u_int32_t be);\r
-\r
-/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\r
- * \r
- * Un-protected double-linked list management\r
- *\r
- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */\r
-\r
-\r
-/* Doubly linked list structure. Can be used as either a list head, or as link words. */\r
-\r
-\r
-\r
-\r
-/* Doubly-linked list manipulation routines. Implemented as macros */\r
-/* but logically these are procedures. */\r
-\r
-\r
-\r
-/* VOID MOSAL_dlist_init_head( PLIST_ENTRY ListHead ); */\r
-\r
-#define MOSAL_dlist_init_head(ListHead) ((ListHead)->Flink = (ListHead)->Blink = (ListHead))\r
-\r
-\r
-/* BOOLEAN MOSAL_dlist_is_empty( PLIST_ENTRY ListHead ); */\r
-\r
-#define MOSAL_dlist_is_empty(ListHead) ((ListHead)->Flink == (ListHead))\r
-\r
-\r
-/* PLIST_ENTRY MOSAL_dlist_remove_head(PLIST_ENTRY ListHead); */\r
-\r
-/* !!! Usage: only 'el = MOSAL_dlist_remove_head(...)' */\r
-/* and NOT return MOSAL_dlist_remove_head(...) or if (MOSAL_dlist_remove_head(...) == ...) !!! */\r
-\r
-#define MOSAL_dlist_remove_head(ListHead) (ListHead)->Flink; {MOSAL_dlist_remove_entry((ListHead)->Flink)}\r
-\r
-\r
-/* PLIST_ENTRY MOSAL_dlist_remove_tail(PLIST_ENTRY ListHead); */\r
-\r
-/* !!! Usage: only 'el = MOSAL_dlist_remove_tail(...)' */\r
-/* and NOT return MOSAL_dlist_remove_tail(...) or if (MOSAL_dlist_remove_tail(...) == ...) !!! */\r
-\r
-#define MOSAL_dlist_remove_tail(ListHead) (ListHead)->Blink; {MOSAL_dlist_remove_entry((ListHead)->Blink)}\r
-\r
-\r
-/* VOID MOSAL_dlist_remove_entry( PLIST_ENTRY Entry ); */\r
-\r
-\r
-#define MOSAL_dlist_remove_entry(Entry) {\\r
- PLIST_ENTRY _EX_Blink;\\r
- PLIST_ENTRY _EX_Flink;\\r
- _EX_Flink = (Entry)->Flink;\\r
- _EX_Blink = (Entry)->Blink;\\r
- _EX_Blink->Flink = _EX_Flink;\\r
- _EX_Flink->Blink = _EX_Blink;\\r
- }\r
-\r
-\r
-/* VOID MOSAL_dlist_insert_tail( PLIST_ENTRY ListHead, PLIST_ENTRY Entry ); */\r
-\r
-\r
-#define MOSAL_dlist_insert_tail(ListHead,Entry) {\\r
- PLIST_ENTRY _EX_Blink;\\r
- PLIST_ENTRY _EX_ListHead;\\r
- _EX_ListHead = (ListHead);\\r
- _EX_Blink = _EX_ListHead->Blink;\\r
- (Entry)->Flink = _EX_ListHead;\\r
- (Entry)->Blink = _EX_Blink;\\r
- _EX_Blink->Flink = (Entry);\\r
- _EX_ListHead->Blink = (Entry);\\r
- }\r
-\r
-\r
-/* VOID MOSAL_dlist_insert_head( PLIST_ENTRY ListHead, PLIST_ENTRY Entry ); */\r
-\r
-\r
-#define MOSAL_dlist_insert_head(ListHead,Entry) {\\r
- PLIST_ENTRY _EX_Flink;\\r
- PLIST_ENTRY _EX_ListHead;\\r
- _EX_ListHead = (ListHead);\\r
- _EX_Flink = _EX_ListHead->Flink;\\r
- (Entry)->Flink = _EX_Flink;\\r
- (Entry)->Blink = _EX_ListHead;\\r
- _EX_Flink->Blink = (Entry);\\r
- _EX_ListHead->Flink = (Entry);\\r
- }\r
-\r
-\r
-#ifdef MT_KERNEL\r
-typedef enum {MOSAL_IN_ISR=1, MOSAL_IN_DPC, MOSAL_IN_TASK} MOSAL_exec_ctx_t;\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_get_exec_ctx\r
- *\r
- * Description:\r
- * get execution context of the current function (e.g. proccess or interrupt)\r
- *\r
- * Parameters: \r
- *\r
- * Returns:\r
- * MT_context_t\r
- *\r
- ******************************************************************************/\r
-MOSAL_exec_ctx_t MOSAL_get_exec_ctx(void);\r
-\r
-\r
-#endif /* MT_KERNEL */\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#include <mtl_common.h>\r
-#include <mosal.h>\r
-\r
-#ifdef __DARWIN__\r
-#error This function is unsupported in Darwin\r
-#endif\r
-\r
-call_result_t MOSAL_PCI_get_cfg_hdr(u_int8_t bus, u_int8_t dev_func, MOSAL_PCI_cfg_hdr_t * cfg_hdr)\r
-{\r
- call_result_t ret;\r
-\r
- u_int8_t offset;\r
- u_int32_t dword;\r
-\r
- MOSAL_PCI_hdr_type0_t * t0 = 0;\r
- MOSAL_PCI_hdr_type1_t * t1 = 0;\r
-\r
- for (offset = 0; offset < sizeof(MOSAL_PCI_cfg_hdr_t); offset += sizeof(u_int32_t))\r
- {\r
- ret = MOSAL_PCI_read_config_dword(bus,dev_func, offset, &dword);\r
- if (ret != MT_OK)\r
- {\r
- MTL_ERROR2("Failed to read from bus=%d devfun=%d\n", bus, dev_func);\r
- return(ret);\r
- }\r
-\r
- *((u_int32_t*)cfg_hdr + offset/sizeof(u_int32_t)) = dword;\r
- }\r
-\r
- if (cfg_hdr->type0.header_type == MOSAL_PCI_HEADER_TYPE0)\r
- {\r
- t0 = &cfg_hdr->type0;\r
-\r
- MTL_DEBUG4 ("vendor ID = 0x%.4x\n", t0->vid);\r
- MTL_DEBUG4 ("device ID = 0x%.4x\n", t0->devid);\r
- MTL_DEBUG4 ("command register = 0x%.4x\n", t0->cmd);\r
- MTL_DEBUG4 ("status register = 0x%.4x\n", t0->status); \r
- MTL_DEBUG4 ("revision ID = 0x%.2x\n", t0->revid);\r
- MTL_DEBUG4 ("class code = 0x%.2x\n", t0->class_code); \r
- MTL_DEBUG4 ("sub class code = 0x%.2x\n", t0->subclass);\r
- MTL_DEBUG4 ("programming interface = 0x%.2x\n", t0->progif);\r
- MTL_DEBUG4 ("cache line = 0x%.2x\n", t0->cache_line);\r
- MTL_DEBUG4 ("latency time = 0x%.2x\n", t0->latency);\r
- MTL_DEBUG4 ("header type = 0x%.2x\n", t0->header_type);\r
- MTL_DEBUG4 ("BIST = 0x%.2x\n", t0->bist);\r
- MTL_DEBUG4 ("base address 0 = 0x%.8x\n", t0->base0);\r
- MTL_DEBUG4 ("base address 1 = 0x%.8x\n", t0->base1); \r
- MTL_DEBUG4 ("base address 2 = 0x%.8x\n", t0->base2); \r
- MTL_DEBUG4 ("base address 3 = 0x%.8x\n", t0->base3); \r
- MTL_DEBUG4 ("base address 4 = 0x%.8x\n", t0->base4); \r
- MTL_DEBUG4 ("base address 5 = 0x%.8x\n", t0->base5); \r
- MTL_DEBUG4 ("cardBus CIS pointer = 0x%.8x\n", t0->cis); \r
- MTL_DEBUG4 ("sub system vendor ID = 0x%.4x\n", t0->sub_vid);\r
- MTL_DEBUG4 ("sub system ID = 0x%.4x\n", t0->sub_sysid);\r
- MTL_DEBUG4 ("expansion ROM base address = 0x%.8x\n", t0->rom_base);\r
- MTL_DEBUG4 ("interrupt line = 0x%.2x\n", t0->int_line);\r
- MTL_DEBUG4 ("interrupt pin = 0x%.2x\n", t0->int_pin);\r
- MTL_DEBUG4 ("min Grant = 0x%.2x\n", t0->min_grant);\r
- MTL_DEBUG4 ("max Latency = 0x%.2x\n", t0->max_latency);\r
-\r
- } else {\r
-\r
- t1 = &cfg_hdr->type1;\r
-\r
- MTL_DEBUG4 ("vendor ID = 0x%.4x\n", t1->vid);\r
- MTL_DEBUG4 ("device ID = 0x%.4x\n", t1->devid);\r
- MTL_DEBUG4 ("command register = 0x%.4x\n", t1->cmd);\r
- MTL_DEBUG4 ("status register = 0x%.4x\n", t1->status);\r
- MTL_DEBUG4 ("revision ID = 0x%.2x\n", t1->revid);\r
- MTL_DEBUG4 ("class code = 0x%.2x\n", t1->class_code);\r
- MTL_DEBUG4 ("sub class code = 0x%.2x\n", t1->sub_class);\r
- MTL_DEBUG4 ("programming interface = 0x%.2x\n", t1->progif);\r
- MTL_DEBUG4 ("cache line = 0x%.2x\n", t1->cache_line);\r
- MTL_DEBUG4 ("latency time = 0x%.2x\n", t1->latency);\r
- MTL_DEBUG4 ("header type = 0x%.2x\n", t1->header_type);\r
- MTL_DEBUG4 ("BIST = 0x%.2x\n", t1->bist);\r
- MTL_DEBUG4 ("base address 0 = 0x%.8x\n", t1->base0);\r
- MTL_DEBUG4 ("base address 1 = 0x%.8x\n", t1->base1);\r
- MTL_DEBUG4 ("primary bus number = 0x%.2x\n", t1->pri_bus);\r
- MTL_DEBUG4 ("secondary bus number = 0x%.2x\n", t1->sec_bus);\r
- MTL_DEBUG4 ("subordinate bus number = 0x%.2x\n", t1->sub_bus);\r
- MTL_DEBUG4 ("secondary latency timer = 0x%.2x\n", t1->sec_latency);\r
- MTL_DEBUG4 ("IO base = 0x%.2x\n", t1->iobase);\r
- MTL_DEBUG4 ("IO limit = 0x%.2x\n", t1->iolimit);\r
- MTL_DEBUG4 ("secondary status = 0x%.4x\n", t1->sec_status);\r
- MTL_DEBUG4 ("memory base = 0x%.4x\n", t1->mem_base);\r
- MTL_DEBUG4 ("memory limit = 0x%.4x\n", t1->mem_limit);\r
- MTL_DEBUG4 ("prefetch memory base = 0x%.4x\n", t1->pre_base);\r
- MTL_DEBUG4 ("prefetch memory limit = 0x%.4x\n", t1->pre_limit);\r
- MTL_DEBUG4 ("prefetch memory base upper = 0x%.8x\n", t1->pre_base_upper);\r
- MTL_DEBUG4 ("prefetch memory limit upper = 0x%.8x\n", t1->pre_limit_upper);\r
- MTL_DEBUG4 ("IO base upper 16 bits = 0x%.4x\n", t1->io_base_upper);\r
- MTL_DEBUG4 ("IO limit upper 16 bits = 0x%.4x\n", t1->io_limit_upper);\r
- MTL_DEBUG4 ("expansion ROM base address = 0x%.8x\n", t1->rom_base);\r
- MTL_DEBUG4 ("interrupt line = 0x%.2x\n", t1->int_line);\r
- MTL_DEBUG4 ("interrupt pin = 0x%.2x\n", t1->int_pin);\r
- MTL_DEBUG4 ("bridge control = 0x%.4x\n", t1->control);\r
-\r
- }\r
-\r
- return(MT_OK);\r
-\r
-}\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_I2C_H\r
-#define H_MOSAL_I2C_H\r
-\r
-#include <mtl_common.h>\r
-\r
-\r
-#define I2C_MAX_DEV_NAME 17 /* TBD: MOSAL name? */\r
-\r
-\r
-/* Forward declaration of device handle */\r
-typedef struct MOSAL_i2c_dev_st * MOSAL_i2c_devh_t;\r
-\r
-\r
-/* Forwad declaration of device */\r
-typedef struct MOSAL_i2c_dev_st MOSAL_i2c_dev_t;\r
-\r
-\r
-\r
-/***************************************************************************************************\r
- * Function: MOSAL_I2C_master_receive\r
- *\r
- * Description: master receive data\r
- *\r
- * Parameters:\r
- * dev_h (IN) Device handle.\r
- * slv_addr (IN) The address of the receipent\r
- * buffer (OUT) (LEN @count) Pointer where to put data received\r
- * count (IN) Number of bytes to be receive\r
- * bytes_received_p (OUT) Pointer to var to receive number of bytes received\r
- * sendSTOP (IN) Send stop after transaction\r
- * key (IN) Key to autenticate the caller.\r
- * \r
- * Returns: MT_OK success\r
- * MT_ERROR failure to initialize\r
- * \r
- * Notes:\r
- *\r
- **************************************************************************************************/\r
-call_result_t MOSAL_I2C_master_receive(MOSAL_i2c_devh_t dev_h, u_int8_t slv_addr,\r
- void *buffer, u_int16_t count, u_int32_t *bytes_received_p, MT_bool sendSTOP, u_int32_t key);\r
-\r
-/***************************************************************************************************\r
- * \r
- * Function(MOSAL): MOSAL_I2C_master_transmit\r
- *\r
- * Description: master transmit data\r
- *\r
- *\r
- * Parameters: \r
- * dev_h (IN) I2C device handle.\r
- * slv_addr (IN) The address of the receipent.\r
- * buffer (IN) (LEN @count) Pointer to data to be transmitted.\r
- * count (IN) Number of bytes to be sent.\r
- * bytes_sent_p (OUT) Pointer to var to receive number of bytes sent\r
- * sendSTOP (IN) Flag when 1 send STOP - otherwise don't send STOP\r
- * key_p (IN/OUT) Pointer to key. \r
- * \r
- * Returns: MT_OK success\r
- * MT_ERROR failure to initialize\r
- * \r
- *****************************************************************************************/\r
-call_result_t MOSAL_I2C_master_transmit(MOSAL_i2c_devh_t dev_h, unsigned char slv_addr, void *buffer,\r
- int count, int *bytes_sent_p, MT_bool sendSTOP, u_int32_t * const key_p);\r
-\r
-/***************************************************************************************************\r
- * Function: MOSAL_I2C_send_stop\r
- *\r
- * Description: send STOP to the i2c bus\r
- *\r
- * Parameters: \r
- * dev_h (IN) device handle\r
- * key (IN) pointer to a key previously received from master transmit\r
- * \r
- * Returns: MT_OK success\r
- * MT_ERROR failure to initialize\r
- * \r
- * Notes:\r
- *\r
- **************************************************************************************************/\r
-call_result_t MOSAL_I2C_send_stop(MOSAL_i2c_devh_t dev_h, const u_int32_t key);\r
-\r
-\r
-\r
-/*****************************************************************************************\r
- * Function: MOSAL_I2C_read\r
- *\r
- * \r
- * Description: Read from i2c device.\r
- *\r
- * \r
- * Parameters:\r
- * dev_h (IN) Handle of device to use.\r
- * i2c_addr (IN) I2C bus address of target device.\r
- * addr (IN) Offset in target device for read start.\r
- * data (OUT) (LEN @length) Buffer in local memory where data read will be written.\r
- * length (IN) Number of bytes to read.\r
- * \r
- *\r
- * Returns: MT_OK success\r
- * MT_ERROR failed to read\r
- *\r
- *****************************************************************************************/\r
-call_result_t MOSAL_I2C_read(MOSAL_i2c_devh_t dev_h, u_int16_t i2c_addr, u_int32_t addr,\r
- u_int8_t* data, u_int32_t length);\r
-\r
-\r
-/*****************************************************************************************\r
- * Function: MOSAL_I2C_write\r
- * \r
- * Description: write to i2c device.\r
- *\r
- * \r
- * Parameters:\r
- * dev_h (IN) Handle of device to use.\r
- * i2c_addr (IN) I2C bus address of target device.\r
- * addr (IN) Offset in target device for write start.\r
- * data (IN) (LEN @length) Buffer in local memory where data to be written is found\r
- * length (IN) Number of bytes to read.\r
- * \r
- *\r
- * Returns: MT_OK success\r
- * MT_ERROR failed to write\r
- *\r
- *****************************************************************************************/\r
-call_result_t MOSAL_I2C_write(MOSAL_i2c_devh_t dev_h, u_int16_t i2c_addr,\r
- u_int32_t addr, u_int8_t *data, u_int32_t length);\r
-\r
-\r
-/*****************************************************************************************\r
- * Function: MOSAL_I2C_open\r
- * \r
- * Description: Open I2C device returning handle to it. \r
- *\r
- * \r
- * Parameters:\r
- * name (IN) (LEN s) Device name.\r
- * dev_h (OUT) Handle of device to use.\r
- * \r
- *\r
- * Returns: MT_OK success\r
- * MT_ENODEV not device register for this name \r
- * MT_ERROR generic error\r
- *\r
- *****************************************************************************************/\r
-call_result_t MOSAL_I2C_open(char * name, MOSAL_i2c_devh_t * dev_h);\r
-\r
-\r
-/*****************************************************************************************\r
- * Function: MOSAL_I2C_close\r
- * \r
- * Description: close a previously opened device.\r
- *\r
- * \r
- * Parameters:\r
- * dev_h (IN) Handle of device to use.\r
- * \r
- *\r
- * Returns: MT_OK success\r
- * MT_ENODEV Inavlid handle\r
- * MT_ERROR generic error\r
- *\r
- *****************************************************************************************/\r
-call_result_t MOSAL_I2C_close(MOSAL_i2c_devh_t dev_h);\r
-\r
-\r
-\r
-\r
-\r
-/*****************************************************************************************\r
- *\r
- * Function (Kernel only): MOSAL_I2C_add_dev\r
- *\r
- * Description: Register an i2c device.\r
- * \r
- * Parameters: \r
- * devst (IN) Device struture.\r
- * devh (OUT) Return device handle.\r
- *\r
- * Returns: MT_OK\r
- * MT_ENOMEM\r
- *\r
- *\r
- * Notes: this function should be called only from the modules registering the device\r
- * inside the kernel.\r
- *****************************************************************************************/\r
-call_result_t MOSAL_I2C_add_dev(MOSAL_i2c_dev_t * devst, MOSAL_i2c_devh_t *devh);\r
-\r
-/*****************************************************************************************\r
- *\r
- * Function (Kernel only): MOSAL_I2C_del_dev\r
- *\r
- * Description: Deregister I2C device.\r
- * \r
- * Parameters: \r
- * devh (IN) Device struture.\r
- *\r
- * Returns: MT_OK\r
- * MT_EINVAL - invalid device.\r
- *\r
- * Notes: this function should be called only from the modules registering the device\r
- * inside the kernel.\r
- *****************************************************************************************/\r
-call_result_t MOSAL_I2C_del_dev(MOSAL_i2c_devh_t devh);\r
-\r
- \r
-#endif /* H_MOSAL_I2C_H */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef __MOSAL_IOBUF_H_\r
-#define __MOSAL_IOBUF_H_\r
-\r
-typedef enum {\r
- MOSAL_PERM_READ = 1,\r
- MOSAL_PERM_WRITE = 1<<1\r
-}\r
-MOSAL_mem_perm_enum_t;\r
-\r
-typedef u_int32_t MOSAL_mem_perm_t;\r
-\r
-typedef struct {\r
- MT_virt_addr_t va; /* virtual address of the buffer */\r
- MT_size_t size; /* size in bytes of the buffer */\r
- MOSAL_prot_ctx_t prot_ctx;\r
- u_int32_t nr_pages;\r
- MT_u_int_t page_shift;\r
- u_int32_t os_dep_flags;\r
-}\r
-MOSAL_iobuf_props_t;\r
-\r
-\r
-typedef struct mosal_iobuf_iter_st MOSAL_iobuf_iter_t;\r
-typedef struct mosal_iobuf_st *MOSAL_iobuf_t;\r
-\r
-/**** Note ****\r
- Other platform must define specific flags in the same manner as bellow\r
- and consume free numbers. Wheather flags may or may not be or'ed must \r
- be specified specifically */\r
-/*=== Linux specific flags ===*/\r
-/* The following flags MAY NOT be or'ed */\r
-#define MOSAL_IOBUF_LNX_FLG_MARK_ALL_DONTCOPY ((u_int32_t)1<<0)\r
-#define MOSAL_IOBUF_LNX_FLG_MARK_FULL_PAGES_DONTCOPY ((u_int32_t)1<<1) /* mark only regions that occupy integral number of pages */\r
-\r
-\r
-/* The following are os specific flags contained in MOSAL_iobuf_props_t\r
- * The same rules for allocating numbers are as above */\r
-#define MOSAL_IOBUF_LNX_FLG_PROP_MARKED_DONT_COPY ((u_int32_t)1<<0)\r
-\r
-/******************************************************************************\r
- * Function (Kernel space only): MOSAL_iobuf_register\r
- *\r
- * Description: register a virtual buf and assure it is locked\r
- *\r
- * Parameters:\r
- * va(in) virtual address to register\r
- * size(in) size in bytes of area to be registered\r
- * prot_ctx(in) context of the calling thread\r
- * iobuf_p(out) pointer to return iobuf object\r
- * flags(in) flags affecting function's behavior. Flags may have meaning\r
- * in a subset of OS specific implementations of this function.\r
- * Others can ignore them. Document all flags bellow.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK success\r
- * MT_EINVAL invalid argument\r
- * MT_EAGAIN not enough resources\r
- *\r
- * Notes: upon successful return the buffer pointed by va is guaranteed to be\r
- * locked\r
- * Flags: MOSAL_IOBUF_LNX_FLG_MARK_ALL_DONTCOPY\r
- * MOSAL_IOBUF_LNX_FLG_MARK_FULL_PAGES_DONTCOPY\r
- * \r
- ******************************************************************************/\r
-DLL_API call_result_t \r
-#ifndef MTL_TRACK_ALLOC\r
-MOSAL_iobuf_register\r
-#else\r
-MOSAL_iobuf_register_memtrack \r
-#endif\r
- (MT_virt_addr_t va,\r
- MT_size_t size,\r
- MOSAL_prot_ctx_t prot_ctx,\r
- MOSAL_mem_perm_t req_perm,\r
- MOSAL_iobuf_t *iobuf_p,\r
- u_int32_t flags);\r
-\r
-#ifdef MTL_TRACK_ALLOC\r
-#define MOSAL_iobuf_register(va, size, prot_ctx, req_perm, iobuf_p, flags) \\r
- ({ \\r
- call_result_t rc; \\r
- rc = MOSAL_iobuf_register_memtrack(va, size, prot_ctx, req_perm, iobuf_p, flags); \\r
- if ( rc == MT_OK ) { \\r
- memtrack_alloc(MEMTRACK_IOBUF, (unsigned long)(*iobuf_p), size, __FILE__, __LINE__); \\r
- } \\r
- rc; \\r
- })\r
-#endif\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function (Kernel space only): MOSAL_iobuf_deregister\r
- *\r
- * Description: deregister the memory context and free resources\r
- *\r
- * Parameters:\r
- * iobuf(in) iobuf object to be released\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK success\r
- * Notes: when the function returns the the memory area is no longer guaranteed\r
- * to be locked and iobuf is no longer valid\r
- ******************************************************************************/\r
-DLL_API call_result_t \r
-#ifndef MTL_TRACK_ALLOC\r
-MOSAL_iobuf_deregister\r
-#else\r
-MOSAL_iobuf_deregister_memtrack \r
-#endif\r
- (MOSAL_iobuf_t iobuf);\r
-\r
-#ifdef MTL_TRACK_ALLOC\r
-#define MOSAL_iobuf_deregister(iobuf) \\r
- ({ \\r
- call_result_t rc; \\r
- memtrack_free(MEMTRACK_IOBUF, (unsigned long)(iobuf), __FILE__, __LINE__); \\r
- rc = MOSAL_iobuf_deregister_memtrack(iobuf); \\r
- rc; \\r
- })\r
-#endif\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function (Kernel space only): MOSAL_iobuf_get_props\r
- *\r
- * Description: get the properties of the iobuf\r
- *\r
- * Parameters:\r
- * iobuf(in) iobuf object\r
- * props_p(out) pointer by which to return props\r
- * \r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK success\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_iobuf_get_props(MOSAL_iobuf_t iobuf,\r
- MOSAL_iobuf_props_t *props_p);\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function (Kernel space only): MOSAL_iobuf_get_tpt\r
- *\r
- * Description: get the tpt of the iobuf\r
- *\r
- * Parameters:\r
- * iobuf(in) iobuf object\r
- * npages(in) number of entries in pa_arr\r
- * pa_arr(out) pointer to hold physical addresses\r
- * page_size_p(out) where to copy the page size\r
- * (may be null if output is not desired)\r
- * act_table_sz_p(out) where to copy actual number of entries in the table\r
- * (may be null if output is not desired)\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK success\r
- * Notes: the physical addresses of the pages are returned as from the start of the buffer\r
- * to up to npages translation or the max translations on the buffer - the minimum\r
- * between the two\r
- ******************************************************************************/\r
-call_result_t MOSAL_iobuf_get_tpt(MOSAL_iobuf_t iobuf,\r
- u_int32_t npages,\r
- MT_phys_addr_t *pa_arr,\r
- u_int32_t *page_size_p,\r
- u_int32_t *act_table_sz_p);\r
-\r
-\r
-/******************************************************************************\r
- * Function (Kernel space only): MOSAL_iobuf_cmp_tpt\r
- *\r
- * Description: compare the tpt of two iobufs\r
- *\r
- * Parameters:\r
- * iobuf_1(in) first iobuf object\r
- * iobuf_2(in) second iobuf object\r
- *\r
- * Returns:\r
- * 0 tpt's are equal\r
- * != 0 tpt's differ\r
- * Notes: The function compares iobufs belonging to the same protection context.\r
- * If the protection context differs it returns -1; If the protection context\r
- * is kernel than only the va and size of both iobus are compared. It is assumed\r
- * that there can be no two vitual addresses that map to the same physical address.\r
- * In user space it could be that the sizes of the buffers are not equal bu the\r
- * number of pages is equal. In that case if the physical addresses of the two\r
- * buffers are equal then the iobufs are considered equal\r
- * \r
- ******************************************************************************/\r
-int MOSAL_iobuf_cmp_tpt(MOSAL_iobuf_t iobuf_1, MOSAL_iobuf_t iobuf_2);\r
-\r
-\r
-/******************************************************************************\r
- * Function (Kernel space only): MOSAL_iobuf_get_tpt_seg\r
- *\r
- * Description: get a number of entries from the tpt as specified by the iterator\r
- * and the n_pages_in param\r
- *\r
- * Parameters:\r
- * iobuf(in) iobuf object\r
- * iterator_p(in/out) iterator for accessing translation tables\r
- * n_pages_in(in) number of translations required\r
- * n_pages_out_p(out) number of translations provided\r
- * page_tbl_p(out) pointer to array where to return translations\r
- *\r
- * Returns:\r
- * MT_OK\r
- ******************************************************************************/\r
-call_result_t MOSAL_iobuf_get_tpt_seg(MOSAL_iobuf_t iobuf, MOSAL_iobuf_iter_t *iterator_p,\r
- MT_size_t n_pages_in, MT_size_t *n_pages_out_p,\r
- MT_phys_addr_t *page_tbl_p);\r
-\r
-\r
-/******************************************************************************\r
- * Function (Kernel space only): MOSAL_iobuf_iter_init\r
- *\r
- * Description: initialize the iterator to the begginig of the translation\r
- * table\r
- *\r
- * Parameters:\r
- * iobuf(in) iobuf object\r
- * iterator_p(out) iterator to initialize\r
- *\r
- * Returns:\r
- * MT_OK\r
- ******************************************************************************/\r
-call_result_t MOSAL_iobuf_iter_init(MOSAL_iobuf_t iobuf, MOSAL_iobuf_iter_t *iterator_p);\r
-\r
-\r
-/******************************************************************************\r
- * Function (Kernel space only): MOSAL_iobuf_restore_perm\r
- *\r
- * Description: Restore the permissions on the page tables to the value as\r
- * when the object was created \r
- *\r
- * Parameters:\r
- * iobuf(in) iobuf object\r
- *\r
- * Returns:\r
- * MT_OK\r
- ******************************************************************************/\r
-call_result_t MOSAL_iobuf_restore_perm(MOSAL_iobuf_t iobuf);\r
-\r
-#endif /* __MOSAL_IOBUF_H_ */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_K2U_CBK_H\r
-#define H_MOSAL_K2U_CBK_H\r
-\r
-#include <mtl_common.h>\r
-\r
-/* Max. num. of bytes for callback data */\r
-#define MAX_CBK_DATA_SZ 512\r
-\r
-/* Per process resources handle */\r
-typedef int k2u_cbk_hndl_t;\r
-\r
-#define INVALID_K2U_CBK_HNDL ((k2u_cbk_hndl_t)(-1))\r
-\r
-/* Callback ID for demultiplexing of different callbacks in the same process */\r
-typedef unsigned int k2u_cbk_id_t;\r
-\r
-/* Generic callback */\r
-typedef void (*k2u_cbk_t)(k2u_cbk_id_t cbk_id, void* data_p, MT_size_t size);\r
-\r
-\r
-/******************************************************************************\r
- * Function (user-space only): k2u_cbk_register\r
- *\r
- * Description: Register a handler in the user-level generic callback agent.\r
- *\r
- * Parameters:\r
- * cbk (IN) - Function pointer of the generic callback.\r
- * cbk_hndl_p(OUT)- Callback handle for this process (per process, to be used by kernel caller)\r
- * cbk_id_p (OUT)- ID to be used when calling this callback from kernel (per this process).\r
- *\r
- * Returns: MT_OK,\r
- * MT_EAGAIN on problems with resources allocation. \r
- *\r
- *****************************************************************************/\r
-call_result_t k2u_cbk_register(k2u_cbk_t cbk, k2u_cbk_hndl_t *cbk_hndl_p, k2u_cbk_id_t *cbk_id_p);\r
-\r
-\r
-/******************************************************************************\r
- * Function (user-space only): k2u_cbk_deregister\r
- *\r
- * Description: Deregister a handler in the user-level generic callback agent.\r
- *\r
- * Parameters:\r
- * cbk_id (IN)- ID of callback to deregister.\r
- *\r
- * Returns: MT_OK,\r
- * MT_EAGAIN on problems with resources allocation. \r
- *\r
- *****************************************************************************/\r
-call_result_t k2u_cbk_deregister(k2u_cbk_id_t cbk_id);\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-space only): k2u_cbk_invoke\r
- *\r
- * Description: Invoke from kernel a registered handler in user-level.\r
- *\r
- * Parameters:\r
- * k2u_cbk_h(IN) - handle of cbk resources for process of callback to invoke.\r
- * cbk_id(IN) - ID to be used when calling this callback from kernel (per this process).\r
- * data_p(IN) (LEN MAX_CBK_DATA_SZ) - Pointer in kernel-space for data buffer (of up to MAX_CBK_DATA_SZ bytes).\r
- * This data must be "vmalloc"ed.\r
- * size(IN) - Number of valid bytes copies to data buffer.\r
- *\r
- * Returns: MT_OK,\r
- * MT_EINVAL on invalid handle or size of data more than MAX_CBK_DATA_SZ,\r
- * MT_EAGAIN on problems with resources allocation. \r
- *\r
- * Note: The data is not copied but given data_p is saved in the queue and vfreed \r
- * when delivered (copied) to the user-level process.\r
- *\r
- *****************************************************************************/\r
-call_result_t k2u_cbk_invoke(k2u_cbk_hndl_t k2u_cbk_h, k2u_cbk_id_t cbk_id,\r
- void *data_p, MT_size_t size);\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_K2U_CBK_PRIV_H\r
-#define H_MOSAL_K2U_CBK_PRIV_H\r
-\r
-/* This "callback ID" should be used to notify polling thread of cleanup request */\r
-#define K2U_CBK_CLEANUP_CBK_ID ((k2u_cbk_id_t)(-1))\r
-\r
-/******************************************************************************\r
- * Function(No automatic wrapper): k2u_cbk_init \r
- *\r
- * Description: Init private resources for k2u callback for calling process (e.g. message q).\r
- *\r
- * Parameters:\r
- * k2u_cbk_h_p (OUT) - returned handle (pointer in user-space)\r
- *\r
- * Returns: MT_OK,\r
- * MT_EAGAIN on problems with resources allocation,\r
- * MT_EBUSY if a handle is already allocated for this process (returned in k2u_cbk_h_p). \r
- *\r
- *****************************************************************************/\r
-call_result_t k2u_cbk_init(k2u_cbk_hndl_t *k2u_cbk_h_p);\r
-\r
-\r
-/******************************************************************************\r
- * Function(No automatic wrapper): k2u_cbk_cleanup\r
- *\r
- * Description: Clean private resources for k2u callback for calling process.\r
- *\r
- * Parameters:\r
- * k2u_cbk_h (IN) - handle of cbk resources for this process\r
- *\r
- *\r
- * Returns: MT_OK,\r
- * MT_EINVAL for invalid handle (e.g. this handle is not of this process). \r
- *\r
- *****************************************************************************/\r
-call_result_t k2u_cbk_cleanup(k2u_cbk_hndl_t k2u_cbk_h);\r
-\r
-\r
-/******************************************************************************\r
- * Function: k2u_cbk_pollq\r
- *\r
- * Description: Poll the message queue (will block if no message in the queue).\r
- *\r
- * Parameters:\r
- * k2u_cbk_h (IN) - handle of cbk resources for this process\r
- * cbk_id_p (OUT) - Id for given callback data.\r
- * data_p (OUT) (LEN MAX_CBK_DATA_SZ) - Pointer in user-space for data buffer (of MAX_CBK_DATA_SZ bytes).\r
- * size_p (OUT) - Number of valid bytes copies to data buffer.\r
- *\r
- * Returns: MT_OK,\r
- * MT_EINVAL for invalid handle (e.g. this handle is not of this process) or NULL ptrs,\r
- * MT_EAGAIN if q is empty\r
- *\r
- *****************************************************************************/\r
-call_result_t k2u_cbk_pollq(k2u_cbk_hndl_t k2u_cbk_h,\r
- k2u_cbk_id_t *cbk_id_p,void *data_p, MT_size_t *size_p);\r
-\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_MEM_H\r
-#define H_MOSAL_MEM_H\r
- \r
-#include <mtl_types.h>\r
-#include <mtl_errno.h>\r
-#include <mtl_common.h>\r
-#include <mosal_arch.h>\r
-#include "mosal_mlock.h"\r
-\r
-\r
-/*============ macro definitions =============================================*/\r
-#define VA_NULL ((MT_virt_addr_t)0)\r
-#define PA_NULL ((MT_phys_addr_t)0)\r
-#define INVAL_PHYS_ADDR ((MT_phys_addr_t)_UI64_MAX)\r
-\r
-typedef u_int32_t mem_attr_t;\r
-\r
-#if !defined(__DARWIN__) || !defined(MT_KERNEL)\r
-typedef char * MOSAL_shmem_key_t;\r
-\r
-/*MOSAL shared memory flags */\r
-#define MOSAL_SHM_CREATE 0x1 /*Create a new shared memory region */\r
-#define MOSAL_SHM_EXCL 0x2 /*Ensure that the new region has been created*/\r
-#define MOSAL_SHM_READONLY 0x4 /*Create read-only region*/\r
-#define MOSAL_SHM_HUGEPAGE 0x8 /*Create huge page */\r
-/************************************/\r
-#endif /* !defined(__DARWIN__) || !defined(MT_KERNEL) */\r
-\r
-\r
-#define MIN_PAGE_SZ MOSAL_SYS_PAGE_SIZE\r
-#define MIN_PAGE_SZ_MASK (~((MT_virt_addr_t)MIN_PAGE_SZ - 1)) \r
-#define MIN_PAGE_SZ_ALIGN(x) (((x) + ~MIN_PAGE_SZ_MASK) & MIN_PAGE_SZ_MASK) \r
-\r
-#define MOSAL_PAGE_ALIGN(va, size) (((va) + ~MOSAL_PAGE_MASK((va)+(size))) \\r
- & MOSAL_PAGE_MASK(va + size))\r
- \r
-typedef enum {\r
- MOSAL_MEM_FLAGS_NO_CACHE =1,/* non-chached mapping (to be used for address not in main memory) */ \r
- MOSAL_MEM_FLAGS_PERM_READ = (1<<1), /* Read permission */\r
- MOSAL_MEM_FLAGS_PERM_WRITE= (1<<2) /* Write permission */\r
- /* Note: currently write permission implies read permissions too */ \r
-} MOSAL_mem_flags_enum_t;\r
-\r
-typedef u_int32_t MOSAL_mem_flags_t; /* To be used with flags from MOSAL_mem_flags_enum_t */\r
-\r
-\r
-static __INLINE__ const char *MOSAL_prot_ctx_str(const MOSAL_prot_ctx_t prot_ctx)\r
-{\r
- if ( prot_ctx == MOSAL_get_kernel_prot_ctx() ) {\r
- return "KERNEL";\r
- }\r
- else if ( prot_ctx == MOSAL_get_current_prot_ctx() ) {\r
- return "USER";\r
- }\r
- else {\r
- return "INVALID";\r
- }\r
-}\r
-\r
-\r
-\r
-/******************************************************************************\r
- *\r
- * Function(User Space only): MOSAL_io_remap\r
- *\r
- * Description: Map a physical contigous buffer to virtual address.\r
- *\r
- * Parameters: \r
- * pa (IN) MT_phys_addr_t\r
- * Physical address.\r
- * size (IN) u_int32_t\r
- * Size of memory buffer in bytes\r
- * \r
- *\r
- * Returns: On success returns pointer to new virtual memory buffer else\r
- * returns zero.\r
- *\r
- * Notes: The returned address will be page alligned. In case 'size' is not \r
- * page alligned the amount of allocated memory can be bigger than the \r
- * requested.\r
- *\r
- ******************************************************************************/\r
-MT_virt_addr_t \r
-#ifndef MTL_TRACK_ALLOC\r
-MOSAL_io_remap\r
-#else\r
-MOSAL_io_remap_memtrack\r
-#endif\r
- (MT_phys_addr_t pa, MT_size_t size); \r
-\r
-#ifdef MTL_TRACK_ALLOC\r
-#define MOSAL_io_remap(pa, size) \\r
- ({ \\r
- MT_virt_addr_t rc; \\r
- rc = MOSAL_io_remap_memtrack((pa), (size)); \\r
- if ( rc != VA_NULL ) { \\r
- memtrack_alloc(MEMTRACK_IOREMAP, (unsigned long)(rc), (size), __FILE__, __LINE__);\\r
- } \\r
- rc; \\r
- })\r
- \r
-#endif\r
-\r
-void\r
-#ifndef MTL_TRACK_ALLOC\r
-MOSAL_io_unmap\r
-#else\r
-MOSAL_io_unmap_memtrack\r
-#endif\r
- (MT_virt_addr_t va);\r
-\r
-\r
-#ifdef MTL_TRACK_ALLOC\r
-#define MOSAL_io_unmap(va) do { \\r
- memtrack_free(MEMTRACK_IOREMAP, (unsigned long)(va), __FILE__, __LINE__); \\r
- MOSAL_io_unmap_memtrack(va); \\r
- } \\r
- while (0)\r
-#endif\r
-\r
-\r
-/******************************************************************************\r
- *\r
- * Function: MOSAL_map_phys_addr\r
- *\r
- * Description: \r
- * Map physical address range to given process/memory context \r
- * MOSAL_io_remap is mapped to this with \r
- * prot_ctx==MOSAL_PROT_CTX_KERNEL and flags=MOSAL_MEM_FLAGS_NO_CACHE\r
- *\r
- * Parameters: \r
- * pa (IN) MT_phys_addr_t\r
- * Physical address.\r
- * bsize (IN) u_int32_t\r
- * Size of memory buffer in bytes\r
- * flags (IN) MOSAL_mem_flags_t\r
- * Mapping attributes \r
- * prot_ctx (IN) MOSAL_prot_ctx_t\r
- * Protection/memory context to map to (kernel or current user level)\r
- *\r
- * Returns:\r
- * On success returns pointer to new virtual address to which this \r
- * physical memory is mapped (in given prot_ctx).\r
- * NULL if failed.\r
- * Note: Mapping must be made for IO memory only and not for RAM.\r
- *\r
- ******************************************************************************/\r
-MT_virt_addr_t MOSAL_map_phys_addr(MT_phys_addr_t pa, MT_size_t bsize,\r
- MOSAL_mem_flags_t flags, MOSAL_prot_ctx_t prot_ctx);\r
-\r
-/******************************************************************************\r
- *\r
- * Function: MOSAL_unmap_phys_addr\r
- *\r
- * Description: \r
- * Unmap physical address range previously mapped using MOSAL_map_phys_addr\r
- *\r
- * Parameters: \r
- * prot_ctx (IN) MOSAL_prot_ctx_t\r
- * Protection context of memory space of given virtual address.\r
- * virt (IN) MT_virt_addr_t\r
- * Mapping address as returned by MOSAL_map_phys_addr (page aligned).\r
- * bsize (IN) u_int32_t\r
- * Size of memory buffer in bytes\r
- *\r
- * Returns: HH_OK, HH_EINVAL - invalid address\r
- *\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_unmap_phys_addr(MOSAL_prot_ctx_t prot_ctx, MT_virt_addr_t virt, \r
- MT_size_t bsize);\r
-\r
-\r
-/******************************************************************************\r
- *\r
- * Function: MOSAL_virt_to_phys\r
- *\r
- * Description: Translate virtual address to physical.\r
- *\r
- * Parameters: \r
- * prot_ctx(IN) source of the address (kernel or user)\r
- * va (IN) const MT_virt_addr_t \r
- * Virtual address.\r
- * pa_p(OUT) returned physical address\r
- * \r
- * Returns: MT_OK On success\r
- * MT_ENOMEM when not in address space\r
- * MT_ENORSC when physical page is not available\r
- * MT_EINVAL invalid value of prot_ctx\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_virt_to_phys(MOSAL_prot_ctx_t prot_ctx,\r
- const MT_virt_addr_t va, MT_phys_addr_t *pa_p);\r
-\r
-/******************************************************************************\r
- *\r
- * Function (Kernel space only): MOSAL_virt_to_phys_ex\r
- *\r
- * Description: Translate virtual address to physical.\r
- *\r
- * Parameters: \r
- * prot_ctx(IN) source of the address (kernel or user)\r
- * va (IN) Virtual address\r
- * page_pp(OUT) pointer to return struct page * mapped to va\r
- * pa_p(OUT) returned physical address\r
- * wr_enable(IN) if set pte is made write enabled\r
- * \r
- * Returns: MT_OK On success\r
- * MT_ENOMEM when not in address space\r
- * MT_ENORSC when physical page is not available\r
- * MT_EINVAL invalid value of prot_ctx\r
- *\r
- ******************************************************************************/\r
-#if defined(__KERNEL__) && !defined(VXWORKS_OS) && !defined(__WIN__)\r
-call_result_t MOSAL_virt_to_phys_ex(MOSAL_prot_ctx_t prot_ctx, const MT_virt_addr_t va,\r
- struct page **page_pp, MT_phys_addr_t *pa_p, MT_u_int_t wr_enable);\r
-#endif\r
-\r
-#if !defined(__DARWIN__)\r
-/******************************************************************************\r
- *\r
- * Function (Kernel space only): MOSAL_phys_to_virt\r
- *\r
- * Description: Translate physical address to virtual.\r
- *\r
- * Parameters: \r
- * pa (IN) const MT_phys_addr_t \r
- * Physical address.\r
- * \r
- * Returns: On success returns a virtual address in current address space, corresponding to pa. \r
- * Else returns zero.\r
- *\r
- ******************************************************************************/\r
-MT_virt_addr_t MOSAL_phys_to_virt(const MT_phys_addr_t pa);\r
-\r
-\r
-/******************************************************************************\r
- *\r
- * Function (user_only): MOSAL_virt_to_bus\r
- *\r
- * Description: Translate a virtual address to a bus address.\r
- *\r
- * Parameters: \r
- * va (IN) MT_virt_addr_t\r
- * Virtual address.\r
- * \r
- * Returns: On success returns bus address pointed by va. Else returns zero.\r
- *\r
- ******************************************************************************/\r
-MT_phys_addr_t MOSAL_virt_to_bus(MT_virt_addr_t va);\r
-\r
-\r
-/******************************************************************************\r
- *\r
- * Function (differ when kernel or user): MOSAL_phys_ctg_get\r
- *\r
- * Description: allocate a physically contiguous pinned memory region. \r
- *\r
- * Parameters: \r
- * size (IN) \r
- * size of physically contiguous memory to be allocate.\r
- * \r
- * Returns: virtual address of memory or NULL if failed. \r
- *\r
- ******************************************************************************/\r
-MT_virt_addr_t MOSAL_phys_ctg_get(MT_size_t size);\r
-\r
-/******************************************************************************\r
- *\r
- * Function (differ when kernel or user): MOSAL_phys_ctg_free\r
- *\r
- * Description: free an allocate physically contiguous pinned memory region.\r
- *\r
- * Parameters: \r
- * va (IN) \r
- * address of region to be freed.\r
- * \r
- * Returns: void\r
- *******************************************************************************/\r
-call_result_t MOSAL_phys_ctg_free(MT_virt_addr_t addr, MT_size_t size);\r
-\r
-#endif /* __DARWIN__) */\r
-\r
-#define MOSAL_atomic_cmp_xchg(va, new_val, cmp_val) MOSAL_arch_atomic_cmp_xchg((va), (new_val), (cmp_val))\r
-#define MOSAL_atomic_xchg( va, new_val ) MOSAL_arch_atomic_xchg((va), (new_val))\r
-\r
-#define PAGE_SIZE_4M 0x400000\r
-#define PAGE_SIZE_2M 0x200000\r
-#define PAGE_SIZE_4K 0x1000\r
-#define PAGE_SIZE_8K 0x2000\r
-#define PAGE_SIZE_16K 0x4000\r
-#define PAGE_SIZE_64K 0x10000\r
-#define PAGE_SHIFT_4M 22\r
-#define PAGE_SHIFT_2M 21\r
-#define PAGE_SHIFT_4K 12\r
-#define PAGE_SHIFT_8K 13\r
-#define PAGE_SHIFT_16K 14\r
-#define PAGE_SHIFT_64K 16\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_get_page_shift\r
- *\r
- * Description: \r
- * get page shift for the va in the protection context specified by prot_ctx.\r
- *\r
- * Parameters: \r
- * prot_ctx (IN) protection context\r
- * va (IN) virtual address \r
- * page_shift_p (OUT) returned page shift\r
- *\r
- * Returns: MT_OK\r
- * MT_ENOMEM when address not valid\r
- *\r
- * Note: If the address va does not belong to address space in the specified\r
- * context the function fails.\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_get_page_shift( MOSAL_prot_ctx_t prot_ctx, MT_virt_addr_t va,\r
- unsigned *page_shift_p);\r
-\r
-/******************************************************************************\r
- * Function: (inline function) MOSAL_get_page_size\r
- *\r
- * Description:\r
- * get page size for the va in the protection context specified by prot_ctx.\r
- *\r
- * Parameters: \r
- * prot_ctx(IN) protection context\r
- * va(IN) virtual address \r
- * page_size_p(OUT) returned page size\r
- *\r
- * Returns: MT_OK\r
- * MT_ENOMEM when address not valid\r
- *\r
- * Note: If the address va does not belong to address space in the specified\r
- * context the function fails.\r
- *\r
- ******************************************************************************/\r
-static __INLINE__ call_result_t MOSAL_get_page_size(MOSAL_prot_ctx_t prot_ctx,\r
- MT_virt_addr_t va, \r
- unsigned *page_size_p)\r
-{\r
- unsigned int page_shift;\r
- call_result_t rc;\r
-\r
- rc = MOSAL_get_page_shift(prot_ctx, va, &page_shift);\r
- if ( rc != MT_OK ) {\r
- return rc;\r
- }\r
- *page_size_p = 1<<page_shift;\r
- MTL_TRACE1(MT_FLFMT("%s: va="VIRT_ADDR_FMT", prot=%s, page_size=%d"), __func__, va, MOSAL_prot_ctx_str(prot_ctx), *page_size_p);\r
- return rc;\r
-}\r
-\r
-#if !defined(__DARWIN__) || !defined(MT_KERNEL)\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_shmget:\r
- *\r
- * Description:\r
- * Retrieve a shared memory region for the given key\r
- * Parameters: \r
- * key(IN) MOSAL_shmem_key_t - A unique key for the memory region \r
- * size(IN) MT_size_t - size of needed memory region\r
- * flags(IN) - permitions flags that may be:\r
- * MOSAL_SHM_CREATE - create \r
- * MOSAL_SHM_EXCL - fall if the memory region with the given key \r
- * MOSAL_SHM_READONLY - readonly region (by default region will be created \r
- * with read-write permitions\r
- * already exists\r
- * \r
- * id_p(OUT) MOSAL_shmid_t - id of created region (in case of success)\r
- *\r
- * Returns:\r
- * MT_OK - in case of success\r
- * MT_EACCES - if user has no permitions to access this memory region\r
- * MT_EAGAIN - no resources\r
- * MT_EBUSY - if MOSAL_SHM_CREATE | MOSAL_SHM_EXCL was set in flags and the region with \r
- * such a key already exists\r
- * MT_EINVAL - otherwise\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_shmget(MOSAL_shmem_key_t key, \r
- MT_size_t size, \r
- u_int32_t flags, \r
- MOSAL_shmid_t * id_p);\r
-\r
- \r
-/******************************************************************************\r
- * Function \r
- * MOSAL_shmat:\r
- *\r
- * Description:\r
- * Attaches previously allocated shared memory region to virtual address \r
- * space of the calling process.\r
- * Parameters: \r
- * id(IN) MOSAL_shmem_key_t - ID of shared memory region \r
- * flags(IN) - permitions flags that may be:\r
- * MOSAL_SHM_READONLY - create read-only memory region\r
- * otherwise the region will be mapped with read-write permitions\r
- * addr_p(OUT) - Start virtual address of the mapped shared region in case of success\r
- *\r
- * Returns:\r
- * MT_OK - incase of seccess\r
- * MT_EACCES - If calling process has no permissions to access the region with\r
- * the given ID\r
- * MT_EINVAL - Bad id\r
- * MT_EAGAIN - Couldn't allocate page tables for a new address range or for a descriptor\r
- * MT_ERROR - otherwise\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_shmat(MOSAL_shmid_t id, int flags, void ** addr_p);\r
-\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_shmdt:\r
- *\r
- * Description:\r
- * Detaches virtual address mapping of previously attached shared memory region .\r
- * Parameters: \r
- * addr(IN) void * - Virtual address do detach\r
- * Returns:\r
- * MT_OK - success\r
- * MT_EINVAL - Bad address\r
- ******************************************************************************/\r
-call_result_t MOSAL_shmdt(void * addr);\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_shmrm:\r
- *\r
- * Description:\r
- * Schadules for removing the shared memory region with the given ID\r
- * Parameters: \r
- * id(IN) MOSAL_shmid_t - ID of the memory region\r
- * Returns:\r
- * MT_OK in case of success\r
- * MT_EACCES if called by the user which is not a creator of the region\r
- * MT_EINVAL -otherwise\r
- ******************************************************************************/\r
-call_result_t MOSAL_shmrm(MOSAL_shmid_t id);\r
-\r
-#endif /* !defined(__DARWIN__) || !defined(MT_KERNEL) */\r
-\r
-#endif /* H_MOSAL_MEM_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_MLOCK_H\r
-#define H_MOSAL_MLOCK_H\r
-\r
-#include <mosal_iobuf.h>\r
-\r
-typedef struct MOSAL_mlock_ctx_st *MOSAL_mlock_ctx_t;\r
-\r
-#if !defined(__DARWIN__)\r
-/******************************************************************************\r
- *\r
- * Function: MOSAL_mlock\r
- *\r
- * Arguments:\r
- * addr (IN) - Base of the region\r
- * size (IN) - Size of the region\r
- *\r
- * Returns:\r
- * MT_OK, \r
- * appropriate error code otherwise\r
- *\r
- * Description:\r
- * Locks memory region.\r
- *\r
- ********************************************************************************/\r
-call_result_t MOSAL_mlock(MT_virt_addr_t addr, MT_size_t size);\r
-\r
-/********************************************************************************\r
- * Function: MOSAL_munlock\r
- *\r
- * Arguments:\r
- * addr (IN) - Base of the region\r
- * size (IN) - Size of the region\r
- *\r
- * Returns:\r
- * MT_OK, \r
- * appropriate error code otherwise\r
- *\r
- * Description:\r
- * Unlocks memory region.\r
- *\r
- ********************************************************************************/\r
-call_result_t MOSAL_munlock(MT_virt_addr_t addr, MT_size_t size);\r
-\r
-\r
-/********************************************************************************\r
- * Function: (kernel-mode only): MOSAL_mlock_ctx_init\r
- *\r
- * Arguments:\r
- * mlock_ctx_p (OUT): pointer to return mlock context in.\r
- *\r
- * Returns:\r
- * MT_OK, \r
- * appropriate error code otherwise\r
- *\r
- * Description:\r
- * Initiailize MOSAL_mlock context for this process\r
- * This function should only be called by MOSAL wrapper "open" entry point.\r
- * Returned context should be saved in file descriptor (private)\r
- ********************************************************************************/\r
-call_result_t MOSAL_mlock_ctx_init(MOSAL_mlock_ctx_t *mlock_ctx_p);\r
-\r
-/********************************************************************************\r
- * Function: (kernel-mode only): MOSAL_mlock_ctx_cleanup\r
- *\r
- * Arguments:\r
- * mlock_ctx (IN): mlock context allocated with MOSAL_init_mlock_ctx\r
- * Returns:\r
- *\r
- * Description:\r
- * Free MOSAL_mlock context for this process\r
- * This function should be invoked by the "close" entry point of MOSAL wrapper \r
- ********************************************************************************/\r
-call_result_t MOSAL_mlock_ctx_cleanup(MOSAL_mlock_ctx_t mlock_ctx);\r
-\r
-/********************************************************************************\r
- * Function: (kernel-mode only): MOSAL_mlock_iobuf\r
- *\r
- * Arguments:\r
- * va(IN): start address of the region to be locked\r
- * size(IN): size of the area to be locked\r
- * iobuf(IN/OUT): iobuf associated with this area\r
- * page_shift(IN): page shift of the va\r
- * Returns:\r
- *\r
- ********************************************************************************/\r
-call_result_t MOSAL_mlock_iobuf(MT_virt_addr_t addr, MT_size_t size, MOSAL_iobuf_t mosal_iobuf,\r
- unsigned int page_shift);\r
-\r
-/********************************************************************************\r
- * Function: (kernel-mode only): MOSAL_munlock_iobuf\r
- *\r
- * Arguments:\r
- * va(IN): start address of the region to be unlocked\r
- * size(IN): size of the area to be unlocked\r
- * iobuf(IN/OUT): iobuf associated with this area\r
- * page_shift(IN): page shift of the va\r
- * Returns:\r
- *\r
- ********************************************************************************/\r
-call_result_t MOSAL_munlock_iobuf(MT_virt_addr_t addr, MT_size_t size, MOSAL_iobuf_t mosal_iobuf,\r
- unsigned int page_shift);\r
-\r
-#endif /* !defined(__DARWIN__) */\r
-\r
-#endif /*__MOSAL_MLOCK_H__*/\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef __MOSAL_PROT_CTX_H\r
-#define __MOSAL_PROT_CTX_H\r
-\r
-typedef mosal_prot_ctx_t MOSAL_prot_ctx_t;\r
-typedef mosal_pid_t MOSAL_pid_t;\r
-\r
-typedef MOSAL_prot_ctx_t MOSAL_protection_ctx_t; /* keep for backward compatibility */\r
-\r
-#define MOSAL_get_current_prot_ctx() mosal_get_current_prot_ctx() \r
-#define MOSAL_get_kernel_prot_ctx() mosal_get_kernel_prot_ctx() \r
-\r
-#ifdef __KERNEL__\r
-#define MY_PROT_CTX MOSAL_get_kernel_prot_ctx()\r
-#else\r
-#define MY_PROT_CTX MOSAL_get_current_prot_ctx()\r
-#endif\r
-\r
-#endif /* __MOSAL_PROT_CTX_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_QUE_H\r
-#define H_MOSAL_QUE_H\r
-\r
-\r
-/* Message queue defs. */\r
-typedef u_int32_t MOSAL_qhandle_t;\r
-typedef void (*MOSAL_data_free_t)(void*); /* prototype for queue data freeing */\r
-#define MOSAL_MAX_QHANDLES 1024\r
-#define NULL_MOSAL_QHANDLE 0xFFFFFFFF\r
-\r
-\r
-/*********************************** Event queues ****************************/\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only): MOSAL_qcreate\r
- *\r
- * Description: Create Event Queue\r
- * This function creates new queue\r
- *\r
- * Parameters:\r
- * qh(OUT) MOSAL_qhandle_t *\r
- * The handle to be used in MOSAL_qget() and MOSAL_qput() and \r
- * MOSAL_qdelete\r
- * qdestroy_free(IN) MOSAL_data_free_t\r
- * This function is called to free all message queue left-overs\r
- * when qdestroy is called while queue is not empty.\r
- * Set to NULL if no free is needed (there is another mechanism for \r
-this data freeing)\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK or MT_ERROR.\r
- *\r
- *****************************************************************************/\r
-call_result_t MOSAL_qcreate(MOSAL_qhandle_t *qh,MOSAL_data_free_t qdestroy_free);\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only): MOSAL_isqempty\r
- *\r
- * Description:\r
- * Check is it comething in queue\r
- * Parameters:\r
- * qh(IN) MOSAL_qhandle_t\r
- * The event queue handle.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * TRUE - the queue is empty\r
- * FALSE - the queue isn't empty\r
- *\r
- *****************************************************************************/\r
-MT_bool MOSAL_isqempty(MOSAL_qhandle_t qh);\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only): MOSAL_qget\r
- *\r
- * Description:\r
- * reads the next data portion from event_queue\r
- * Parameters:\r
- * qh(IN) MOSAL_qhandle_t\r
- * The event queue handle.\r
- * size(OUT) int *\r
- * Actual data size\r
- * maxsize(IN) int\r
- * Length of the data buffer\r
- * data(OUT) (LEN @maxsize) void *\r
- * Data buffer to fill\r
- * block(IN) MT_bool\r
- * If true and queue empty, the call is blocked.\r
- * \r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK\r
- * MT_EINTR\r
- * MT_EAGAIN on non-blocking access if the queue is empty\r
- * MT_ERROR.\r
- *\r
- *****************************************************************************/\r
-call_result_t MOSAL_qget(MOSAL_qhandle_t qh, int *size, void **data, MT_bool block);\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only): MOSAL_qput\r
- *\r
- * Description:\r
- * puts the next data portion from event_queue\r
- * Parameters:\r
- * qh(IN) MOSAL_qhandle_t\r
- * The event queue handle.\r
- * size(IN) int\r
- * Actual data size\r
- * data(IN) (LEN @size) void *\r
- * Data buffer\r
- * \r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK\r
- * MT_ERROR.\r
- *\r
- *****************************************************************************/\r
-call_result_t MOSAL_qput(MOSAL_qhandle_t qh, int size, void *data);\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only): MOSAL_qdestroy\r
- *\r
- * Description:\r
- * destroy the queue\r
- *\r
- * Parameters:\r
- * qh(IN) MOSAL_qhandle_t\r
- * The event queue handle.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK\r
- * MT_ERROR.\r
- *\r
- *****************************************************************************/\r
-call_result_t MOSAL_qdestroy(MOSAL_qhandle_t qh);\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only): MOSAL_qprint\r
- *\r
- * Description:\r
- * print the queue (data assumed to be a strings)\r
- *\r
- * Parameters:\r
- * qh(IN) MOSAL_qhandle_t\r
- * The event queue handle.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK\r
- *\r
- *****************************************************************************/\r
-call_result_t MOSAL_qprint(MOSAL_qhandle_t qh);\r
-\r
-\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_SYNC_H\r
-#define H_MOSAL_SYNC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-\r
-typedef struct {\r
- u_int32_t sec; /* Seconds */\r
- u_int32_t msec; /* Milliseconds */\r
-} MOSAL_time_t;\r
-\r
-\r
-\r
-/* //////////////////////////////////// */\r
-\r
-/* ////////////////////////////////////////////////////////////////////////////// */\r
-/* Synchronization object */\r
-/* ////////////////////////////////////////////////////////////////////////////// */\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_syncobj_init\r
- *\r
- * Description:\r
- * Init sync object\r
- *\r
- * Parameters: \r
- * obj_p(IN) pointer to synch object\r
- *\r
- * Returns:\r
- * in kernel always returns MT_OK\r
- * in user mode may return MT_ERROR\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_syncobj_init(MOSAL_syncobj_t *obj_p);\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_syncobj_free\r
- *\r
- * Description:\r
- * Destroy sync object\r
- *\r
- * Parameters:\r
- * obj_p(IN) pointer to synch object\r
- *\r
- * Returns:\r
- * MT_OK\r
- * MT_ERR\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_syncobj_free(MOSAL_syncobj_t *obj_p);\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_syncobj_waiton\r
- *\r
- * Description:\r
- * cause process to sleep until synchonization object is signalled or time\r
- * expires\r
- *\r
- * Parameters: \r
- * obj_p(IN) pointer to synch object\r
- * micro_sec(IN) max time to wait in microseconds.\r
- * MOSAL_SYNC_TIMEOUT_INFINITE = inifinite timeout\r
- *\r
- * Returns:\r
- * MT_OK - woke up by event\r
- * MT_ETIMEDOUT - wokeup because of timeout\r
- * MT_EINTR - waiting for event interrupted due to a (SYSV) signal\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_syncobj_waiton(MOSAL_syncobj_t *obj_p, MT_size_t micro_sec);\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_syncobj_signal\r
- *\r
- * Description:\r
- * signal the synchronization object\r
- *\r
- * Parameters: \r
- * obj_p(IN) pointer to synch object\r
- *\r
- * Returns:\r
- * N/A\r
- *\r
- ******************************************************************************/\r
-void MOSAL_syncobj_signal(MOSAL_syncobj_t *obj_p);\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_syncobj_clear\r
- *\r
- * Description:\r
- * reset sync object (i.e. bring it to init - not-signalled -state)\r
- *\r
- * Parameters: \r
- * obj_p(IN) pointer to synch object\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-void MOSAL_syncobj_clear(MOSAL_syncobj_t *obj_p);\r
-\r
-\r
-/* ////////////////////////////////////////////////////////////////////////////// */\r
-/* Semaphores */\r
-/* ////////////////////////////////////////////////////////////////////////////// */\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_sem_init\r
- *\r
- * Description:\r
- * init semaphore\r
- *\r
- * Parameters: \r
- * sem_p(OUT) pointer to semaphore to be initialized\r
- * count(IN) max number of processes that can hold the semaphore at the same time\r
- *\r
- * Returns:\r
- * OK\r
- * MT_EAGAIN\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_sem_init(MOSAL_semaphore_t *sem_p, MT_size_t count);\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_sem_free\r
- *\r
- * Description:\r
- * free semaphore\r
- *\r
- * Parameters:\r
- * sem_p(OUT) pointer to semaphore to be freed\r
- *\r
- * Returns:\r
- * OK\r
- * MT_ERROR - internal error (double free)\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_sem_free(MOSAL_semaphore_t *sem_p);\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_sem_acq\r
- *\r
- * Description:\r
- * acquire the semaphore\r
- *\r
- * Parameters: \r
- * sem_p(IN) pointer to semaphore\r
- * block(IN) if - FALSE, return immediately if could not acquire, otherwise block if necessary\r
- *\r
- * Returns:\r
- * MT_OK - semaphore acquired\r
- * MT_EINTR - interrupted (in blocking mode)\r
- * MT_EAGAIN - semaphore not acquired (only - in non-blocking mode)\r
- *\r
- *******************************************************************************/\r
-call_result_t MOSAL_sem_acq(MOSAL_semaphore_t *sem_p, MT_bool block);\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_sem_rel\r
- *\r
- * Description:\r
- * release the semaphore\r
- *\r
- * Parameters: \r
- * sem_p(IN) pointer to semaphore\r
- *\r
- * Returns:\r
- * N/A\r
- *\r
- ******************************************************************************/\r
-void MOSAL_sem_rel(MOSAL_semaphore_t *sem_p);\r
-\r
-\r
-/* ////////////////////////////////////////////////////////////////////////////// */\r
-/* Mutexes */\r
-/* ////////////////////////////////////////////////////////////////////////////// */\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_mutex_init\r
- *\r
- * Description:\r
- * init mutex\r
- *\r
- * Parameters: \r
- * mtx_p(OUT) pointer to mutex to be initialized\r
- *\r
- * Returns:\r
- * OK\r
- * MT_EAGAIN\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_mutex_init(MOSAL_mutex_t *mtx_p);\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_mutex_free\r
- *\r
- * Description:\r
- * init mutex\r
- *\r
- * Parameters: \r
- * mtx_p(OUT) pointer to mutex to be destroyed\r
- *\r
- * Returns:\r
- * OK\r
- * MT_ERROR\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_mutex_free(MOSAL_mutex_t *mtx_p);\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_mutex_acq\r
- *\r
- * Description:\r
- * acquire the mutex\r
- *\r
- * Parameters: \r
- * mtx_p(IN) pointer to mutex\r
- * block(IN) if - FALSE, return immediately if could not acquire, otherwise block if necessary\r
- *\r
- * Returns:\r
- * MT_OK - mutex acquired\r
- * MT_EINTR - mutex not acquired (only - in non-blocking mode)\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_mutex_acq(MOSAL_mutex_t *mtx_p, MT_bool block);\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_mutex_rel\r
- *\r
- * Description:\r
- * release the mutex\r
- *\r
- * Parameters: \r
- * mtx_p(IN) pointer to mutex\r
- *\r
- * Returns:\r
- * N/A\r
- *\r
- ******************************************************************************/\r
-void MOSAL_mutex_rel(MOSAL_mutex_t *mtx_p);\r
-\r
-\r
-/* ////////////////////////////////////////////////////////////////////////////// */\r
-/* Delay of execution */\r
-/* ////////////////////////////////////////////////////////////////////////////// */\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_delay_execution\r
- *\r
- * Description:\r
- * delay execution of this control path for a the specified time period. Note\r
- * that in some implementaions it performs busy wait.\r
- *\r
- * Parameters: \r
- * time_micro(IN) required delay time in microseconds\r
- *\r
- * Returns:\r
- * N/A\r
- *\r
- ******************************************************************************/\r
-void MOSAL_delay_execution(u_int32_t time_micro);\r
-\r
-/* ////////////////////////////////////////////////////////////////////////////// */\r
-/* Spinlocks */\r
-/* ////////////////////////////////////////////////////////////////////////////// */\r
-\r
-\r
-/**************************************************************************************************\r
- * Function (different for kernel and user space): MOSAL_spinlock_init\r
- *\r
- * Description: Creates a locking mechanism to allow synchronization between different processors.\r
- * It is initialized to an unlocked state\r
- *\r
- * Parameters: spinlock: pointer to spinlock element.\r
- *\r
- * \r
- * Returns: MT_OK\r
- * MT_AGAIN: not enough resources.\r
- * \r
- *************************************************************************************************/\r
-call_result_t MOSAL_spinlock_init(MOSAL_spinlock_t *sp);\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_mutex_acq_ui\r
- *\r
- * Description:\r
- * acquire the mutex - uninterruptable\r
- *\r
- * Parameters: \r
- * mtx_p(IN) pointer to mutex\r
- *\r
- *\r
- ******************************************************************************/\r
-void MOSAL_mutex_acq_ui(MOSAL_mutex_t *mtx_p);\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_sem_acq_ui\r
- *\r
- * Description:\r
- * acquire the semaphore - uninterruptable\r
- *\r
- * Parameters: \r
- * sem_p(IN) pointer to semaphore\r
- *\r
- *******************************************************************************/\r
-void MOSAL_sem_acq_ui(MOSAL_semaphore_t *sem_p);\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_syncobj_waiton_ui\r
- *\r
- * Description:\r
- * cause process to sleep until synchonization object is signalled or time\r
- * expires - uninterruptable\r
- *\r
- * Parameters: \r
- * obj_p(IN) pointer to synch object\r
- * micro_sec(IN) max time to wait in microseconds.\r
- * MOSAL_SYNC_TIMEOUT_INFINITE = inifinite timeout\r
- *\r
- * Returns:\r
- * MT_OK - woke up by event\r
- * MT_ETIMEDOUT - wokeup because of timeout\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_syncobj_waiton_ui(MOSAL_syncobj_t *obj_p, MT_size_t micro_sec);\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_sleep:\r
- *\r
- * Description:\r
- * Suspends the execution of the current process (in Linux)/thread (in Wondows) \r
- * for the given number of seconds\r
- *\r
- * Parameters: \r
- * sec(IN) u_int32_t - number of seconds to sleep\r
- *\r
- * Returns:\r
- * 0 - if sleep and parans were okay\r
- * otherwise - if it wasn't\r
- * Remarks:\r
- * sec must be less that MAX_DWORD/1000\r
- *\r
- ******************************************************************************/\r
-int MOSAL_sleep( u_int32_t sec );\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_usleep:\r
- *\r
- * Description:\r
- * Suspends the execution of the current process for the given number of\r
- * microseconds. The function guarantees to go to sleep for at least usec\r
- * microseconds\r
- * Parameters: \r
- * usec(IN) number of micro seconds to sleep\r
- *\r
- * Returns:\r
- * MT_OK\r
- * MT_EINTR signal received\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_usleep(u_int32_t usec);\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_usleep_ui:\r
- *\r
- * Description:\r
- * Suspends the execution of the current process for the given number of\r
- * microseconds. The function guarantees to go to sleep for at least usec\r
- * microseconds. The function is non interruptile\r
- * Parameters: \r
- * usec(IN) number of micro seconds to sleep\r
- *\r
- * Returns: void\r
- *\r
- ******************************************************************************/\r
-void MOSAL_usleep_ui(u_int32_t usec);\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_gettimeofday:\r
- *\r
- * Description:\r
- * retrns MOSAL_time_t struct defining the current time\r
- * Parameters: \r
- * time_p(OUT) MOSAL_time_t * - current time\r
- *\r
- *\r
- ******************************************************************************/\r
-void MOSAL_gettimeofday(MOSAL_time_t * time_p);\r
-\r
-\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
- }\r
-#endif\r
-\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_THREAD_H\r
-#define H_MOSAL_THREAD_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-#define MOSAL_THREAD_FLAGS_DETACHED 1 /* Create thread as detached - valid for user-space only */\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_thread_start \r
- *\r
- * Description:\r
- * create a thread and run a t-function in its context\r
- * The thread is created as JOINABLE unless the flag MOSAL_THREAD_FLAGS_DETACHED is used.\r
- *\r
- * Parameters: \r
- * mto_p(IN) pointer to MOSAL thread object\r
- * flags(IN) flags for thread creation (MOSAL_THREAD_FLAGS_DETACHED)\r
- * mtf(IN) t-function \r
- * mtf_ctx(IN) t-function context\r
- *\r
- * Returns:\r
- * MT_OK - thread started; for blocking mode - t-function is running;\r
- * MT_EAGAIN - for blocking mode - timeout; thread hasn't started yet; \r
- * other - error;\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_thread_start( \r
- MOSAL_thread_t *mto_p, /* pointer to MOSAL thread object */\r
- u_int32_t flags, /* flags for thread creation */\r
- MOSAL_thread_func_t mtf, /* t-function name */\r
- void *mtf_ctx /* t-function context (optionally) */\r
- );\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_thread_kill \r
- *\r
- * Description:\r
- * terminate the tread brutally\r
- *\r
- * Parameters: \r
- * mto_p(IN) pointer to MOSAL thread object\r
- *\r
- * Returns:\r
- * MT_OK - thread terminated\r
- * MT_ERROR - a failure on thread termination\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_thread_kill( \r
- MOSAL_thread_t *mto_p /* pointer to MOSAL thread object */\r
- );\r
-\r
-\r
-#ifdef __cplusplus\r
- }\r
-#endif\r
-\r
-\r
-#endif\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_TIMER_H\r
-#define H_MOSAL_TIMER_H\r
-\r
-#if defined(__LINUX__) && defined(__x86_64__)\r
-#include <asm/msr.h>\r
-#endif\r
-\r
-#ifdef MT_KERNEL\r
-\r
-/* typedef for MOSAL INTERRUPT object */\r
-struct MOSAL_ISR;\r
-typedef struct MOSAL_ISR MOSAL_ISR_t;\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_ISR_set\r
- *\r
- * Description:\r
- * connect interrupt handler\r
- *\r
- * Parameters:\r
- * isr_p(IN) MOSAL_ISR_t *\r
- * interrupt object\r
- * handler(IN) intr_handler_t\r
- * Pointer to the intr. handler.\r
- * irq(IN) MOSAL_IRQ_ID_t\r
- * The IRQ number of the intr which invokes this handler.\r
- * name(IN) char *\r
- * Just informationa name. In Linux environment\r
- * that name will be presented in /proc/interrupts\r
- * dev_id(IN) MT_ulong_ptr_t\r
- * Unique device ID. Use on intr sharing.\r
- * If NULL, the device may NOT share the IRQ\r
- * with other devices (handlers).\r
- * Otherwise, this pointer may be used as the "This"\r
- * pointer of device data object when calling handler.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * 0-OK -1-Error\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_ISR_set(\r
- MOSAL_ISR_t * isr_p,\r
- MOSAL_ISR_func_t handler,\r
- MOSAL_IRQ_ID_t irq,\r
- char * name,\r
- MT_ulong_ptr_t dev_id\r
- );\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_ISR_unset\r
- *\r
- * Description:\r
- * disconnect interrupt handler\r
- *\r
- * Parameters:\r
- * isr_p(IN) MOSAL_ISR_t *\r
- * interrupt object\r
- *\r
- * Returns:\r
- * call_result_t\r
- * 0-OK -1-Error\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_ISR_unset( MOSAL_ISR_t * isr_p );\r
-\r
-#if !defined(__DARWIN__)\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_set_intr_handler\r
- *\r
- * Description:\r
- * Sets the given interrupt handler to be called back on the given IRQ.\r
- * If dev_id!=NULL, the handler would be linked to IRQ only if previously\r
- * set handler were sharing handlers (had dev_id!=NULL), too.\r
- * This means that a non-sharing handler may be the only handler which\r
- * is called back on a given IRQ.\r
- *\r
- * Parameters:\r
- * handler(IN) intr_handler_t\r
- * Pointer to the intr. handler.\r
- * irq(IN) MOSAL_IRQ_ID_t\r
- * The IRQ number of the intr which invokes this handler.\r
- * name(IN) char *\r
- * Just informationa name. In Linux environment\r
- * that name will be presented in /proc/interrupts\r
- * dev_id(IN) void*\r
- * Unique device ID. Use on intr sharing.\r
- * If NULL, the device may NOT share the IRQ\r
- * with other devices (handlers).\r
- * Otherwise, this pointer may be used as the "This"\r
- * pointer of device data object when calling handler.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * 0-OK -1-Error\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_set_intr_handler(intr_handler_t handler,\r
- MOSAL_IRQ_ID_t irq,\r
- char *name,\r
- void* dev_id);\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_unset_intr_handler\r
- *\r
- * Description:\r
- * Removes the given interrupt handler of the callback chain on the given IRQ.\r
- *\r
- * Parameters:\r
- * handler(IN) intr_handler_t\r
- * Pointer to the intr. handler.\r
- * irq(IN) MOSAL_IRQ_ID_t\r
- * The IRQ number of the intr which invokes this handler.\r
- * dev_id(IN) void*\r
- * Unique device ID. Use on intr sharing.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK if success, MT_ERROR if failed.\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_unset_intr_handler(intr_handler_t handler,\r
- MOSAL_IRQ_ID_t irq,\r
- void* dev_id);\r
-\r
-#endif /* ! defined__DARWIN__ */\r
-\r
-#if ((defined(__LINUX__) && (LINUX_KERNEL_2_4 || LINUX_KERNEL_2_6))) || defined(__WIN__) || defined(VXWORKS_OS) || defined(__DARWIN__)\r
-/* This code is only for kernel 2.4 or kernel 2.6 */\r
-\r
-\r
-\r
-/* ////////////////////////////////////////////////////////////////////////////// */\r
-\r
-/* DPC (=tasklet) functions */\r
-\r
-/* ////////////////////////////////////////////////////////////////////////////// */\r
-\r
-/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\r
- * Component: \r
- * MOSAL tasklet/DPC implementation [tasklets and DPC are synonyms]\r
- *\r
- * Data object: \r
- * MOSAL DPC object - struct MOSAL_DPC, wrapping tasklet in Linux and DPC in Windows\r
- *\r
- * Functions:\r
- * void MOSAL_DPC_init(MOSAL_DPC_t *d ...) - initialize a MOSAL DPC object;\r
- * void MOSAL_DPC_schedule(MOSAL_DPC_t *d) - schedule a MOSAL DPC object;\r
- * void MOSAL_DPC_schedule_ctx(MOSAL_DPC_t *d) - schedule a MOSAL DPC object with parameters;\r
- * call_result_t MOSAL_DPC_add_ctx(MOSAL_DPC_t *d,...) - add DPC request context to a MOSAL DPC object;\r
- * \r
- *\r
- * Macros:\r
- * MOSAL_DPC_enable(MOSAL_DPC_t *d) - enable DPC (only Linux)\r
- * MOSAL_DPC_disable(MOSAL_DPC_t *d) - disable DPC (only Linux)\r
- *\r
- * Example of usage (taken from CM\msgdspch.c and ported to MOSAL API):\r
- *\r
- * ** declare a MOSAL DPC object 'cm_machine_tasklet', calling function 'cm_machine' \r
- * MOSAL_DPC_t cm_machine_tasklet;\r
- * MOSAL_DPC_init (&cm_machine_tasklet, cm_machine, 0, 0);\r
- *\r
- * ** schedule it **\r
- * MOSAL_DPC_schedule( &cm_machine_tasklet );\r
- * \r
- * Notes:\r
- * 1. There are no static initialization like Linux's DECLARE_TASKLET() !\r
- * 2. DPC function has Linux's prototype: void a_DPC_function(unsigned long ), \r
- * but the meaning of the parameters depends on the type of DPC.\r
- * 3. There are 2 types of DPC: MOSAL_SINGLE_CTX and MOSAL_MULTIPLE_CTX.\r
- * 4. DPC of MOSAL_SINGLE_CTX type:\r
- * - allows only one interrupt per one DPC invocation;\r
- * - doesn't relay dynamic parameters from ISR to DPC;\r
- * - The parameter of a_DPC_function() is in fact a user callback context;\r
- * 5. DPC of MULITPLE_CTX type:\r
- * - allows several interrupts before and during a DPC invocation;\r
- * - on every interrupt ISR fills a DPC context with static and dynamic parameters and\r
- * enqueues it to the DPC context chain. The DPC handles all the chain while it works.\r
- * - The parameter of a_DPC_function() is in fact a pointer to DPC_CONTEXT_t (see below);\r
- * \r
- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */\r
- \r
-\r
-struct DPC_CONTEXT;\r
-typedef struct DPC_CONTEXT DPC_CONTEXT_t;\r
-\r
-/* typedef for MOSAL DPC object */\r
-struct MOSAL_DPC;\r
-typedef struct MOSAL_DPC MOSAL_DPC_t;\r
-\r
-\r
-/* Functions */\r
-\r
-\r
- /******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_DPC_init\r
- *\r
- * Description:\r
- * init a MOSAL DPC object\r
- *\r
- * Parameters:\r
- * d - MOSAL DPC object\r
- * func - user DPC;\r
- * data - its data;\r
- * type - type of DPC\r
- *\r
- * Returns:\r
- *\r
- * Notes:\r
- * (Windows) Callers of this routine must be running at IRQL PASSIVE_LEVEL\r
- *\r
- ******************************************************************************/\r
-void MOSAL_DPC_init(MOSAL_DPC_t *d, MOSAL_DPC_func_t func, MT_ulong_ptr_t func_ctx, MOSAL_DPC_type_t type );\r
-\r
- /******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_DPC_schedule\r
- *\r
- * Description:\r
- * schedule user DPC \r
- *\r
- * Parameters:\r
- * d - MOSAL DPC object\r
- *\r
- * Returns:\r
- *\r
- * Notes:\r
- * (Windows) Callers of this routine must be running at IRQL PASSIVE_LEVEL\r
- *\r
- ******************************************************************************/\r
-MT_bool MOSAL_DPC_schedule(MOSAL_DPC_t *d);\r
-\r
-\r
-#if !defined(__DARWIN__)\r
- /******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_DPC_schedule_ctx\r
- *\r
- * Description:\r
- * schedule user DPC with relaying a context\r
- *\r
- * Parameters:\r
- * d - MOSAL DPC object\r
- * isr_ctx1 - context, relayed by ISR, inserting DPC;\r
- * isr_ctx2 - context, relayed by ISR, inserting DPC; \r
- *\r
- * Returns:\r
- *\r
- * Notes:\r
- * (Windows) Callers of this routine must be running at IRQL PASSIVE_LEVEL\r
- *\r
- ******************************************************************************/\r
-MT_bool MOSAL_DPC_schedule_ctx(MOSAL_DPC_t *d, void * isr_ctx1, void * isr_ctx2);\r
-\r
-#ifdef SUPPORT_MULTIPLE_CTX \r
- /******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_DPC_add_ctx\r
- *\r
- * Description:\r
- * add DPC request context to a MOSAL DPC object\r
- *\r
- * Parameters:\r
- * d - MOSAL DPC object\r
- * ctx1 - context, relayed by ISR, inserting DPC;\r
- * ctx2 - context, relayed by ISR, inserting DPC; \r
- *\r
- * Returns:\r
- * MT_ENORSC - if no ctx structures\r
- * MT_OK - otherwise\r
- *\r
- * Notes:\r
- * A helper routine for ISR, inserting DPC \r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_DPC_add_ctx(MOSAL_DPC_t *d, PVOID ctx1, PVOID ctx2);\r
-# endif /* SUPPORT_MULTIPLE_CTX */\r
-#endif /* ! defined __DARWIN__ */\r
-\r
-/* ////////////////////////////////////////////////////////////////////////////// */\r
-\r
-/* Timer functions */\r
-\r
-/* ////////////////////////////////////////////////////////////////////////////// */\r
-\r
-/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\r
- * Component: \r
- * MOSAL timer functions implementation \r
- *\r
- * Data object: \r
- * MOSAL timer object - struct MOSAL_timer, wrapping OS-dependent structures\r
- *\r
- * Functions:\r
- * void MOSAL_timer_init(MOSAL_timer_t *t) - initialize a MOSAL timer object;\r
- * void MOSAL_timer_add(MOSAL_timer_t *t ...) - start timer;\r
- * void MOSAL_timer_del(MOSAL_timer_t *t ...) - cancel timer;\r
- * void MOSAL_timer_mod(MOSAL_timer_t *t ...) - restart timer;\r
- *\r
- * Example of usage (taken from CMkernel\cm_sm.c and ported to MOSAL API):\r
- *\r
- * ** declare a MOSAL timer object 'cm_machine_tasklet', calling function 'cm_machine' **\r
- * MOSAL_timer_t try_timer;\r
- * MOSAL_timer_init (&try_timer);\r
- *\r
- * ** start timer **\r
- * MOSAL_timer_add( &try_timer, cmk_try_timeout, connection->local_com_id, usec );\r
- * \r
- * Portability notes:\r
- * 1. Functions MOSAL_timer_del() and MOSAL_timer_mod() return 'void' (and not 'int' as in Linux);\r
- *\r
- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */\r
-\r
-/* timer object */\r
-struct MOSAL_timer;\r
-typedef struct MOSAL_timer MOSAL_timer_t;\r
-\r
-#if !defined(__DARWIN__)\r
- /******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_timer_init\r
- *\r
- * Description:\r
- * init a MOSAL DPC object\r
- *\r
- * Parameters:\r
- * d - MOSAL timer object\r
- * func - user DPC;\r
- * data - its data;\r
- *\r
- * Returns:\r
- *\r
- * Notes:\r
- * 1. Callers of this routine must be running at IRQL PASSIVE_LEVEL;\r
- * 2. Every timer must use its own MOSAL timer object ! \r
- * 3. Different MOSAL timer objects may use the same DPC function;\r
- *\r
- ******************************************************************************/\r
-__INLINE__ void MOSAL_timer_init(MOSAL_timer_t *t);\r
-\r
- /******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_timer_add\r
- *\r
- * Description:\r
- * start timer\r
- *\r
- * Parameters:\r
- * d - MOSAL timer object\r
- * func - user DPC;\r
- * data - its data;\r
- * usecs - interval; 'func' will be called in 'usecs' microseconds\r
- *\r
- * Returns:\r
- *\r
- * Notes:\r
- * Callers of this routine must be running at IRQL <= DISPATCH_LEVEL\r
- *\r
- ******************************************************************************/\r
-__INLINE__ void MOSAL_timer_add(MOSAL_timer_t *t, MOSAL_DPC_func_t func, MT_ulong_ptr_t data, long usecs);\r
-\r
- /******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_timer_del\r
- *\r
- * Description:\r
- * delete timer\r
- *\r
- * Parameters:\r
- * d - MOSAL timer object\r
- *\r
- * Returns:\r
- *\r
- * Notes:\r
- * Callers of this routine must be running at IRQL <= DISPATCH_LEVEL \r
- * NOTE for Linux - *** do not use the callback function to call add_timer to\r
- * add this timer to the list as it may cause a race condition ***\r
- *\r
- ******************************************************************************/\r
-__INLINE__ void MOSAL_timer_del(MOSAL_timer_t *t);\r
-\r
- /******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_timer_mod\r
- *\r
- * Description:\r
- * stop the running timer and restart it in 'usecs' microseconds\r
- *\r
- * Parameters:\r
- * d - MOSAL timer object\r
- * usecs - interval; 'func' will be called in 'usecs' microseconds\r
- *\r
- * Returns:\r
- *\r
- * Notes:\r
- * Callers of this routine must be running at IRQL <= DISPATCH_LEVEL\r
- *\r
- ******************************************************************************/\r
-__INLINE__ void MOSAL_timer_mod(MOSAL_timer_t *t, long usecs);\r
-\r
-#endif /* ! defined __DARWIN__ */\r
-\r
-\r
-#endif /* ((defined(__LINUX__) && LINUX_KERNEL_2_4)) || defined(__WIN__) */\r
-#endif /* MT_KERNEL */\r
-\r
-/* ////////////////////////////////////////////////////////////////////////////// */\r
-\r
-/* Time functions */\r
-\r
-/* ////////////////////////////////////////////////////////////////////////////// */\r
-\r
-#if defined(__WIN__) || defined(VXWORKS_OS)\r
-\r
-/* Time */\r
-\r
-\r
-/* taken from Linux/time.h */\r
-struct MOSAL_timespec {\r
- long tv_sec; /* seconds */\r
- long tv_nsec; /* nanoseconds */\r
-};\r
-\r
-\r
-typedef struct MOSAL_timespec MOSAL_timespec_t;\r
-\r
-#endif /* __WIN__ || VXWORKS_OS */\r
-\r
-#ifdef __DARWIN__\r
-typedef struct mach_timespec MOSAL_timespec_t;\r
-#endif\r
-\r
-#if defined(__LINUX__)\r
-typedef struct timespec MOSAL_timespec_t;\r
-#endif\r
-\r
-\r
-#ifdef MT_KERNEL\r
- /******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_time_get_clock\r
- *\r
- * Description:\r
- * get current system clock (in microseconds)\r
- *\r
- * Parameters:\r
- * ts(OUT) - pointer to a structure, describing the time\r
- *\r
- * Returns:\r
- *\r
- * Notes:\r
- * Callers of this routine must be running at IRQL <= DISPATCH_LEVEL\r
- *\r
- ******************************************************************************/\r
- void MOSAL_time_get_clock(MOSAL_timespec_t *ts);\r
-\r
- /******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_time_compare\r
- *\r
- * Description:\r
- * compare 2 absolute times\r
- *\r
- * Parameters:\r
- * ts1(IN) - pointer to a structure, describing the time\r
- * ts2(IN) - pointer to a structure, describing the time\r
- *\r
- * Returns:\r
- * positive - when ts1 > ts2\r
- * negative - when ts1 < ts2\r
- * zero - when ts1 = ts2\r
- *\r
- *\r
- ******************************************************************************/\r
-static __INLINE__ int MOSAL_time_compare(MOSAL_timespec_t *ts1, MOSAL_timespec_t *ts2 )\r
-{\r
- if (ts1->tv_sec > ts2->tv_sec)\r
- return 1;\r
- if (ts1->tv_sec < ts2->tv_sec)\r
- return -1;\r
- if (ts1->tv_nsec < ts2->tv_nsec)\r
- return -1;\r
- return ts1->tv_nsec > ts2->tv_nsec;\r
-}\r
-\r
- /******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_time_add_usec\r
- *\r
- * Description:\r
- * enlarge an absolute time 'ts' by 'usec' of microseconds\r
- *\r
- * Parameters:\r
- * ts(IN) - pointer to a structure, describing the time\r
- * usecs(IN) - a POSITIVE number of microseconds to add\r
- *\r
- * Returns:\r
- * updated 'ts'\r
- *\r
- ******************************************************************************/\r
-static __INLINE__ MOSAL_timespec_t * MOSAL_time_add_usec(MOSAL_timespec_t *ts, long usecs )\r
-{\r
- ts->tv_sec += usecs / 1000000L;\r
- ts->tv_nsec += (usecs % 1000000L) * 1000;\r
- if (ts->tv_nsec > 1000000000L) {\r
- ts->tv_sec++;\r
- ts->tv_nsec -= 1000000000L;\r
- }\r
- return ts;\r
-}\r
-\r
- /******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_time_init\r
- *\r
- * Description:\r
- * Zero 'ts' structure\r
- *\r
- * Parameters:\r
- * ts(IN) - pointer to a structure, describing the time\r
- * usecs(IN) - a POSITIVE number of microseconds to add\r
- *\r
- * Returns:\r
- * updated 'ts'\r
- *\r
- ******************************************************************************/\r
-static __INLINE__ void MOSAL_time_init(MOSAL_timespec_t *ts)\r
-{\r
- ts->tv_sec = ts->tv_nsec = 0;\r
-}\r
-#endif /* MT_KERNEL */\r
-\r
- /******************************************************************************\r
- * Function (inline): \r
- * MOSAL_get_time_counter\r
- *\r
- * Description:\r
- * get te current value of a counter that progresses monotonically with time\r
- *\r
- * Parameters:\r
- *\r
- * Returns:\r
- * value of the counter or 0 if not supported by the architecture\r
- *\r
- ******************************************************************************/\r
-static __INLINE__ u_int64_t MOSAL_get_time_counter(void)\r
-{\r
-#if (defined(__i386__) || defined(i386)) && (defined(__LINUX__) || defined(VXWORKS_OS))\r
- unsigned long long int x;\r
- __asm__ volatile (".byte 0x0f, 0x31" : "=A" (x));\r
- return x;\r
- \r
-#elif defined(__WIN__)\r
- return win_get_time_counter(); /* defined in mtl_sys_defs.h */\r
- \r
-#elif defined(__x86_64__) && defined(__LINUX__)\r
- u_int32_t low, high;\r
- rdtsc(low, high);\r
- return (((u_int64_t)high)<<32) | (u_int64_t)low;\r
-#else\r
- return 0;\r
-#endif\r
-}\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_get_counts_per_sec\r
- *\r
- * Description: get number of counts in 1 sec (refer to MOSAL_get_time_counter)\r
- *\r
- * Parameters:\r
- *\r
- * Returns:\r
- * Number of counts in 1 sec or 0 if not supported\r
- *\r
- ******************************************************************************/\r
-u_int64_t MOSAL_get_counts_per_sec(void);\r
-\r
-#endif /* H_MOSAL_TIMER_H */\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef _MOSALU_SOCKET_H\r
-#define _MOSALU_SOCKET_H\r
-\r
-#ifndef MT_KERNEL\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_socket\r
- *\r
- * Description:\r
- * create a socket \r
- *\r
- * Parameters: \r
- * domain (IN)\r
- * type (IN)\r
- * protocol(IN)\r
- * Returns:\r
- * the socket on success, otherwise -1\r
- ******************************************************************************/\r
-int MOSAL_socket_socket(MOSAL_socket_domain_t domain,MOSAL_socket_type_t type,MOSAL_socket_protocol_t protocol);\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_close \r
- *\r
- * Description:\r
- * closes the socket\r
- *\r
- * Parameters: \r
- * sock\r
- * Returns:\r
- * 0 on success, -1 otherwise\r
- ******************************************************************************/\r
-int MOSAL_socket_close(int sock);\r
-\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_connect \r
- *\r
- * Description: client\r
- * connect to server \r
- *\r
- * Parameters: \r
- * sock\r
- * adrs(IN) server's adrs details \r
- * len(IN) sizeof struct adrs\r
- * Returns:\r
- * 0 on success, -1 otherwise\r
- ******************************************************************************/\r
-int MOSAL_socket_connect(int sock ,const MOSAL_sockaddr_t* adrs,\r
- MOSAL_socklen_t len);\r
-\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_bind \r
- *\r
- * Description: server\r
- * bind the socket to adrs \r
- *\r
- * Parameters: \r
- * sock (IN) \r
- * adrs (IN) server's adrs details \r
- * len (IN) size of struct adrs \r
- * Returns:\r
- * 0 on success, -1 otherwise\r
- *\r
- ******************************************************************************/\r
-int MOSAL_socket_bind(int sock,const MOSAL_sockaddr_t* adrs,\r
- MOSAL_socklen_t len); \r
-\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_listen \r
- *\r
- * Description: server\r
- * start listening on this socket \r
- *\r
- * Parameters: \r
- * sock(IN) \r
- * n (IN) length of queue of requests\r
- *\r
- * Returns:\r
- * 0 on success, -1 otherwise\r
- ******************************************************************************/\r
-int MOSAL_socket_listen(int sock ,int n); \r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_accept \r
- *\r
- * Description: server\r
- * extracts the first connection on the queue of pending connections, creates a new socket with\r
- * the properties of sock, and allocates a new file descriptor.\r
- * the socket \r
- *\r
- * Parameters: \r
- * sock\r
- * client_adrs_p(OUT) adrs of the first connection accepted\r
- * len_p(OUT) sizeof adrs\r
- * \r
- * Returns:\r
- * the new socket on success, -1 otherwise\r
- ******************************************************************************/\r
-int MOSAL_socket_accept(int sock,MOSAL_sockaddr_t* client_adrs,MOSAL_socklen_t* len_p); \r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_send \r
- *\r
- * Description: \r
- * send len bytes from buffer through socket \r
- * Parameters: \r
- * sock(IN) \r
- * buf\r
- * len - num of bytes to send\r
- * flags\r
- * Returns: returns the number sent or -1\r
- * \r
- ******************************************************************************/\r
-int MOSAL_socket_send(int sock,const void* buf,int len,int flags);\r
-\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_recv \r
- *\r
- * Description: \r
- * recv len bytes from buffer through socket \r
- * Parameters: \r
- * sock(IN) pointer to MOSAL socket object\r
- * buf\r
- * len - num of bytes to read\r
- * flags\r
- * Returns: returns the number read or -1\r
- ******************************************************************************/\r
-int MOSAL_socket_recv(int sock,void* buf,int len,int flags);\r
-\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_sendto \r
- *\r
- * Description: \r
- * send N bytes from buf on socket to peer at adrs adrs.\r
- * Parameters: \r
- * sock_p(IN) pointer to MOSAL socket object\r
- * buf\r
- * n - num of bytes to send\r
- * flags\r
- * adrs\r
- * adrs_len\r
- * \r
- * Returns: returns the number sent or -1\r
- ******************************************************************************/\r
-int MOSAL_socket_sendto (int sock,void *buf, int n,int flags, MOSAL_sockaddr_t* adrs,\r
- MOSAL_socklen_t adrs_len);\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_recvfrom \r
- *\r
- * Description: \r
- * read N bytes into buf on socket to peer at adrs adrs.\r
- * If ADDR is not NULL, fill in *ADDR_LEN bytes of it with tha address of\r
- * the sender, and store the actual size of the address in *ADDR_LEN.\r
- *\r
- * Parameters: \r
- * sock(IN) pointer to MOSAL socket object\r
- * buf\r
- * n - num of bytes to read\r
- * flags\r
- * adrs\r
- * adrs_len\r
- * \r
- * Returns: returns the number read or -1\r
- ******************************************************************************/\r
-\r
-int MOSAL_socket_recvfrom (int sock, void *buf, int n, int flags,\r
- MOSAL_sockaddr_t* adrs,MOSAL_socklen_t* adrs_len_p);\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_setsockopt \r
- *\r
- * Description: \r
- * set an option on socket or protocol level\r
- *\r
- * Parameters: \r
- * sock(IN) pointer to MOSAL socket object\r
- * level(IN) option level\r
- * optname(IN) option name\r
- * optval(IN) pointer to buffer, containing the option value\r
- * optlen(IN) buffer size\r
- * \r
- * Returns: 0 on success, -1 otherwise\r
- ******************************************************************************/\r
-int MOSAL_socket_setsockopt(int sock, MOSAL_socket_optlevel_t level, \r
- MOSAL_socket_optname_t optname, const void *optval, int optlen );\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_get_last_error \r
- *\r
- * Description: \r
- * get last error on the socket\r
- *\r
- * Parameters: \r
- * \r
- * Returns: the error number\r
- ******************************************************************************/\r
-int MOSAL_socket_get_last_error(void);\r
-\r
-#endif\r
-\r
-#endif\r
\r
-EXPORTS\r
-;\r
-; mtl_common\r
-;\r
- mtl_log_set\r
- mtl_log\r
- mtl_strerror\r
- mtl_strerror_sym\r
-;\r
-; MOSAL\r
-;\r
- ; ----- mosal_wrap_clt.c -----\r
- MOSAL_PCI_present\r
- MOSAL_PCI_find_device\r
- MOSAL_PCI_find_class\r
- MOSAL_PCI_read_config_byte\r
- MOSAL_PCI_read_config_word\r
- MOSAL_PCI_write_config_byte\r
- MOSAL_PCI_write_config_word\r
- MOSAL_PCI_read_config_dword\r
- MOSAL_PCI_write_config_dword\r
- MOSAL_PCI_read_config_data\r
- MOSAL_PCI_write_config_data\r
- MOSAL_PCI_read_io_byte\r
- MOSAL_PCI_read_io_word\r
- MOSAL_PCI_read_io_dword\r
- MOSAL_PCI_write_io_byte\r
- MOSAL_PCI_write_io_word\r
- MOSAL_PCI_write_io_dword\r
- MOSAL_PCI_read_mem\r
- MOSAL_PCI_write_mem\r
- MOSAL_PCI_get_cfg_hdr\r
- MOSAL_MPC860_present\r
- MOSAL_MPC860_write\r
- MOSAL_MPC860_read\r
- MOSAL_is_privileged\r
- k2u_cbk_init\r
- k2u_cbk_cleanup\r
- MOSAL_map_phys_addr\r
- MOSAL_unmap_phys_addr\r
- MOSAL_virt_to_phys\r
- MOSAL_virt_to_phys\r
- MOSAL_mlock\r
- MOSAL_munlock\r
- MOSAL_get_counts_per_sec\r
- MOSAL_nsecs\r
-; MOSAL_get_page_size\r
- MOSAL_get_page_shift\r
- ; ----- Mosalu_mem.c -----\r
- MOSAL_user_lib_init\r
- MOSAL_io_remap\r
- MOSAL_io_unmap\r
- MOSAL_io_release\r
- MOSAL_phys_ctg_get\r
- MOSAL_phys_ctg_free\r
- MOSAL_shmrm\r
- MOSAL_shmdt\r
- MOSAL_shmat\r
- MOSAL_shmget\r
- MOSAL_get_sys_page_size\r
- MOSAL_get_sys_page_shift\r
- ; ----- Mosalu_sync.c -----\r
- MOSAL_syncobj_init\r
- MOSAL_syncobj_waiton\r
- MOSAL_syncobj_waiton_ui\r
- MOSAL_syncobj_signal\r
- MOSAL_syncobj_clear\r
- MOSAL_sem_init\r
- MOSAL_sem_acq\r
- MOSAL_sem_acq_ui\r
- MOSAL_sem_acq_to\r
- MOSAL_sem_rel\r
- MOSAL_mutex_init\r
- MOSAL_mutex_acq\r
- MOSAL_mutex_acq_ui\r
- MOSAL_mutex_acq_to\r
- MOSAL_mutex_rel\r
- MOSAL_delay_execution\r
- MOSAL_spinlock_init\r
- MOSAL_sleep\r
- MOSAL_usleep\r
- MOSAL_gettimeofday\r
-; MOSAL_spinlock_lock\r
-; MOSAL_spinlock_irq_lock\r
-; MOSAL_spinlock_unlock\r
- MOSAL_gettimeofday\r
- ; ----- mosalu_k2u_cbk.c -----\r
- k2u_cbk_register\r
- k2u_cbk_deregister\r
- ; ----- Mosalu_thread.c -----\r
- MOSAL_thread_start\r
- MOSAL_thread_kill\r
- MOSAL_thread_wait_for_exit\r
- ; ----- Mosalu_socket.c -----\r
- MOSAL_socket_socket\r
- MOSAL_socket_close\r
- MOSAL_socket_connect\r
- MOSAL_socket_bind\r
- MOSAL_socket_listen\r
- MOSAL_socket_accept\r
- MOSAL_socket_send\r
- MOSAL_socket_recv\r
- MOSAL_socket_sendto\r
- MOSAL_socket_recvfrom\r
- MOSAL_socket_setsockopt\r
- MOSAL_socket_get_last_error\r
- ; ----- Mosalu_dirver.c -----\r
- MOSAL_getpid\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_ARCH_H\r
-#define H_MOSAL_ARCH_H\r
- \r
-#include <mtl_types.h>\r
-#include <mtl_errno.h>\r
-#include <mtl_common.h>\r
-\r
-\r
-static __inline u_int32_t MOSAL_arch_atomic_cmp_xchg(volatile u_int32_t * addr, u_int32_t new_val, u_int32_t cmp_val )\r
-{\r
- return InterlockedCompareExchange( (PLONG)addr, new_val, cmp_val );\r
-}\r
-\r
-static __inline u_int32_t MOSAL_arch_atomic_xchg(volatile u_int32_t * addr, u_int32_t new_val)\r
-{\r
- return InterlockedExchange( (PLONG)addr, new_val );\r
-}\r
-\r
-static __inline u_int32_t MOSAL_arch_atomic_inc32(volatile u_int32_t * addr)\r
-{\r
- return InterlockedIncrement((PLONG)addr);\r
-}\r
-\r
-static __inline u_int32_t MOSAL_arch_atomic_dec32(volatile u_int32_t * addr)\r
-{\r
- return InterlockedDecrement((PLONG)addr);\r
-}\r
-\r
-\r
-/******************************************************************************\r
- *\r
- * Function (only include): MOSAL_atomic_inc32\r
- *\r
- * Description: atomically increment a dword (u_int32_t).\r
- *\r
- * Parameters: \r
- * va (IN) void pointer to dword containing bit.\r
- * \r
- * Returns: incremented value.\r
- *\r
- ******************************************************************************/\r
-#define MOSAL_atomic_inc32(va) MOSAL_arch_atomic_inc32((va))\r
-\r
-/******************************************************************************\r
- *\r
- * Function (only include): MOSAL_atomic_dec32\r
- *\r
- * Description: atomically decrement a dword (u_int32_t).\r
- *\r
- * Parameters: \r
- * va (IN) void pointer to dword containing bit.\r
- * \r
- * Returns: decremented value.\r
- *\r
- ******************************************************************************/\r
-#define MOSAL_atomic_dec32(va) MOSAL_arch_atomic_dec32((va))\r
-\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "mosal_priv.h"\r
-\r
-#if 0\r
-// Without use of NTDDK\r
-\r
-call_result_t MOSAL_PCI_read_config_dword(u_int8_t bus,\r
- u_int8_t dev_func,\r
- u_int8_t offset,\r
- u_int32_t* data_p)\r
-{\r
- /* find dev_p */\r
- MOSAL_dev_t * dev_p = find_device_by_location( bus, dev_func );\r
- if (dev_p == NULL)\r
- return MT_ERROR;\r
-\r
- return ReadWritePciConfig( dev_p, data_p, offset, sizeof(long), TRUE );\r
-}\r
-\r
-\r
-call_result_t MOSAL_PCI_write_config_dword(u_int8_t bus,\r
- u_int8_t dev_func,\r
- u_int8_t offset,\r
- u_int32_t data)\r
-{\r
- /* find dev_p */\r
- MOSAL_dev_t * dev_p = find_device_by_location( bus, dev_func );\r
- return ReadWritePciConfig( dev_p, &data, offset, sizeof(long), FALSE );\r
-}\r
-\r
-\r
-#endif\r
-\r
-bool MOSAL_PCI_present(void)\r
-{\r
- return TRUE;\r
-}\r
-\r
-\r
-call_result_t MOSAL_PCI_find_class(u_int32_t class_code,\r
- u_int16_t index,\r
- u_int8_t * bus_p,\r
- u_int8_t * dev_func_p)\r
-{\r
- return MT_ENOSYS;\r
-}\r
-\r
-call_result_t MOSAL_PCI_read_io_byte(u_int32_t addr, u_int8_t *data_p)\r
-{\r
- return MT_ENOSYS;\r
-}\r
-\r
-call_result_t MOSAL_PCI_read_io_word(u_int32_t addr, u_int16_t *data_p)\r
-{\r
- return MT_ENOSYS;\r
-}\r
-\r
-call_result_t MOSAL_PCI_read_io_dword(u_int32_t addr, u_int32_t *data_p)\r
-{\r
- return MT_ENOSYS;\r
-}\r
-\r
-call_result_t MOSAL_PCI_write_io_byte(u_int32_t addr, u_int8_t data)\r
-{\r
- return MT_ENOSYS;\r
-}\r
-\r
-call_result_t MOSAL_PCI_write_io_word(u_int32_t addr, u_int16_t data)\r
-{\r
- return MT_ENOSYS;\r
-}\r
-\r
-call_result_t MOSAL_PCI_write_io_dword(u_int32_t addr, u_int32_t data)\r
-{\r
- return MT_ENOSYS;\r
-}\r
-\r
-\r
-call_result_t MOSAL_PCI_read_mem(u_int64_t addr, u_int64_t size, void *data_p)\r
-{\r
- PULONG from = (PULONG)addr;\r
- PULONG to = (PULONG)data_p; \r
- ULONG count = (ULONG)size >> 2;\r
- ULONG rest = (ULONG)size - (count<<2);\r
-\r
- if (count > 0)\r
- READ_REGISTER_BUFFER_ULONG( from, to, count);\r
- if (rest > 0)\r
- {\r
- from += count;\r
- to += count;\r
- READ_REGISTER_BUFFER_UCHAR( (PUCHAR)from, (PUCHAR)to, rest);\r
- }\r
-\r
- return MT_OK;\r
-}\r
-\r
-call_result_t MOSAL_PCI_write_mem(u_int64_t addr, u_int64_t size, void *data_p)\r
-{\r
- PULONG to = (PULONG)addr;\r
- PULONG from = (PULONG)data_p; \r
- ULONG count = (ULONG)size >> 2;\r
- ULONG rest = (ULONG)size - (count<<2);\r
-\r
- if (count > 0)\r
- WRITE_REGISTER_BUFFER_ULONG( to, from, count);\r
- if (rest > 0)\r
- {\r
- from += count;\r
- to += count;\r
- WRITE_REGISTER_BUFFER_UCHAR( (PUCHAR)to, (PUCHAR)from, rest);\r
- }\r
-\r
- return MT_OK;\r
-}\r
-\r
-/*\r
- * MPC860\r
- * ------\r
- */\r
-bool MOSAL_MPC860_present()\r
-{\r
- bool rc;\r
-\r
- MTL_TRACE1("\n-> MOSAL_MPC860_present \n");\r
-\r
-#ifdef PPC_PRESENT\r
- rc = TRUE;\r
-#else\r
- rc = FALSE;\r
-#endif\r
-\r
- MTL_TRACE1("<- MOSAL_MPC860_present rc=%s, \n", rc ? "TRUE":"FALSE");\r
- return rc;\r
-}\r
-\r
-call_result_t MOSAL_MPC860_write(u_int32_t addr,\r
- u_int32_t size,\r
- void * data_p)\r
-{\r
- call_result_t rc;\r
-\r
- MTL_TRACE1("\n-> MOSAL_MPC860_write addr=%08x, size=%d, data_p=%p\n",\r
- addr, size, data_p);\r
-\r
-#ifdef PPC_PRESENT\r
- rc = MOSAL_MAPP_mem_write(addr, size, data_p);\r
-#else\r
- rc = MT_ENOSYS;\r
-#endif\r
-\r
- MTL_TRACE1("<- MOSAL_MPC860_write rc=%d (%s)\n",\r
- rc, mtl_strerror_sym(rc));\r
- return rc;\r
-}\r
-\r
-\r
-call_result_t MOSAL_MPC860_read(u_int32_t addr,\r
- u_int32_t size,\r
- void * data_p)\r
-{\r
- call_result_t rc;\r
-\r
- MTL_TRACE1("\n-> MOSAL_MPC860_read addr=%08x, size=%d, data_p=%p\n",\r
- addr, size, data_p);\r
-\r
-#ifdef PPC_PRESENT\r
- rc = MOSAL_MAPP_mem_read(addr, size, data_p);\r
-#else\r
- rc = MT_ENOSYS;\r
-#endif\r
-\r
- MTL_TRACE1("<- MOSAL_MPC860_read rc=%d (%s)\n",\r
- rc, mtl_strerror_sym(rc));\r
- return rc;\r
-}\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_BUS_H\r
-#define H_MOSAL_BUS_H\r
-\r
-#include <mtl_types.h>\r
-#include <mtl_pci_types.h>\r
-\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_PCI_present\r
- *\r
- * Description: Check on existance of PCI in system.\r
- * This function should be called before using any of the following.\r
- *\r
- * Parameters: (none)\r
- *\r
- * Returns:\r
- * bool\r
- * TRUE if PCI exist.\r
- *\r
- ******************************************************************************/\r
-bool MOSAL_PCI_present(void);\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_PCI_find_class\r
- *\r
- * Description: Find a PCI device based on class code.\r
- *\r
- * Parameters:\r
- * class_code(IN) u_int32_t\r
- * 24 Class code bits.\r
- * index(IN) u_int16_t\r
- * Occurance of device of given Vendor/Device IDs.\r
- * bus_p(OUT) u_int8_t *\r
- * Bus num of matching device.\r
- * dev_func_p(OUT) u_int8_t *\r
- * Device/Function ([7:3]/[2:0]) of matching device.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK if found, MT_ENODEV if such device not found.\r
- *\r
- * Note:\r
- * For hot-swap support, the PCI bus should be really probed on device\r
- * search, and not a preset DB (which was usually created during boot).\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_PCI_find_class(u_int32_t class_code, u_int16_t index,\r
- u_int8_t *bus_p, u_int8_t *dev_func_p);\r
-\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_PCI_get_cfg_hdr\r
- *\r
- * Description: Get header type0 or type1\r
- *\r
- * Parameters:\r
- * bus(IN) u_int8_t\r
- * Bus num of device.\r
- * dev_func(IN) u_int8_t\r
- * Device/Function ([7:3]/[2:0]) of device.\r
- * \r
- * cfg_hdr(OUT) MOSAL_PCI_cfg_hdr_t\r
- * Union of type0 and type1 header.\r
- * \r
- * Returns:\r
- * call_result_t\r
- * MT_OK if success, MT_ERROR\r
- *\r
- * Notes:\r
- * If header type is unknown it can be extracted from header_type field of \r
- * type0 member offset or type1. \r
- * \r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_PCI_get_cfg_hdr(u_int8_t bus, u_int8_t dev_func, MOSAL_PCI_cfg_hdr_t * cfg_hdr);\r
-\r
-\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_PCI_read_io_byte\r
- *\r
- * Description: Read byte of PCI I/O space.\r
- *\r
- * Parameters:\r
- * addr(IN) u_int32_t\r
- * I/O address to read.\r
- * data_p(OUT) u_int8_t *\r
- * Ptr to a byte data buffer.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK if success, MT_ERROR if failed.\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_PCI_read_io_byte(u_int32_t addr, u_int8_t *data_p);\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_PCI_read_io_word\r
- *\r
- * Description: Read word of PCI I/O space.\r
- *\r
- * Parameters:\r
- * addr(IN) u_int32_t\r
- * I/O address to read.\r
- * data_p(OUT) u_int16_t *\r
- * Ptr to a word data buffer.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK if success, MT_ERROR if failed.\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_PCI_read_io_word(u_int32_t addr, u_int16_t *data_p);\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_PCI_read_io_dword\r
- *\r
- * Description: Read dword of PCI I/O space.\r
- *\r
- * Parameters:\r
- * addr(IN) u_int32_t\r
- * I/O address to read.\r
- * data_p(OUT) u_int32_t *\r
- * Ptr to a dword data buffer.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK if success, MT_ERROR if failed.\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_PCI_read_io_dword(u_int32_t addr, u_int32_t *data_p);\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_PCI_write_io_byte\r
- *\r
- * Description: Write byte of PCI I/O space.\r
- *\r
- * Parameters:\r
- * addr(IN) u_int32_t\r
- * I/O address to write.\r
- * data(IN) u_int8_t\r
- * Byte data to write.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK if success, MT_ERROR if failed.\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_PCI_write_io_byte(u_int32_t addr, u_int8_t data);\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_PCI_write_io_word\r
- *\r
- * Description: Write word of PCI I/O space.\r
- *\r
- * Parameters:\r
- * addr(IN) u_int32_t\r
- * I/O address to write.\r
- * data(IN) u_int16_t\r
- * Word data to write.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK if success, MT_ERROR if failed.\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_PCI_write_io_word(u_int32_t addr, u_int16_t data);\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_PCI_write_io_dword\r
- *\r
- * Description: Write dword of PCI I/O space.\r
- *\r
- * Parameters:\r
- * addr(IN) u_int32_t\r
- * I/O address to write.\r
- * data(IN) u_int32_t\r
- * Dword data to write.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK if success, MT_ERROR if failed.\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_PCI_write_io_dword(u_int32_t addr, u_int32_t data);\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_PCI_read_mem\r
- *\r
- * Description: Read PCI I/O space.\r
- *\r
- * Parameters:\r
- * addr(IN) u_int64_t\r
- * I/O address to read.\r
- * size(IN) u_int64_t\r
- * Num. of bytes to read.\r
- * data_p(OUT) (LEN @size) void *\r
- * Ptr to data buffer of 'size' bytes at least.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK if success, MT_ERROR if failed.\r
- *\r
- * Note:\r
- * PCI access is optimized for maximum possible throughput/burst size.\r
- * 64 bit transactions are issued if possible.\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_PCI_read_mem(u_int64_t addr, u_int64_t size, void *data_p);\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_PCI_write_mem\r
- *\r
- * Description: Write PCI I/O space.\r
- *\r
- * Parameters:\r
- * addr(IN) u_int64_t\r
- * I/O address to write.\r
- * size(IN) u_int64_t\r
- * Num. of bytes to write.\r
- * data_p(IN) (LEN @size) void *\r
- * Ptr to data buffer of 'size' bytes at least.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK if success, MT_ERROR if failed.\r
- *\r
- * Note:\r
- * PCI access is optimized for maximum possible throughput/burst size.\r
- * 64 bit transactions are issued if possible.\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_PCI_write_mem(u_int64_t addr, u_int64_t size, void *data_p);\r
-\r
-\r
-\r
-\r
-/**************************************************************************************************\r
- * MPC860 bus\r
- **************************************************************************************************/\r
-\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_MPC860_present\r
- *\r
- * Description: Check on existance of MPC860 bus in system.\r
- * This function should be called before using any of the following.\r
- *\r
- * Parameters: (none)\r
- *\r
- * Returns:\r
- * bool\r
- * TRUE if MPC860 bus exist.\r
- *\r
- ******************************************************************************/\r
-bool MOSAL_MPC860_present(void);\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_MPC860_read\r
- *\r
- * Description: Read MPC860 External Bus mem. space.\r
- *\r
- * Parameters:\r
- * addr(IN) u_int32_t\r
- * Address to read.\r
- * size(IN) u_int32_t\r
- * Num. of bytes to read.\r
- * data_p(OUT) (LEN @size) void *\r
- * Ptr to data buffer of 'size' bytes at least.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK if success, MT_ERROR if failed.\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_MPC860_read(u_int32_t addr, u_int32_t size, void *data_p);\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_MPC860_write\r
- *\r
- * Description: Write MPC860 External Bus mem. space.\r
- *\r
- * Parameters:\r
- * addr(IN) u_int32_t\r
- * Address to write.\r
- * size(IN) u_int32_t\r
- * Num. of bytes to write.\r
- * data_p(IN) (LEN @size) void *\r
- * Ptr to data buffer of 'size' bytes at least.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK if success, MT_ERROR if failed.\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_MPC860_write(u_int32_t addr, u_int32_t size, void *data_p);\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_reset_card\r
- *\r
- * Description:\r
- * reset the card by its bus and dev_func \r
- *\r
- * Parameters: \r
- *\r
- * Returns:\r
- * MT_OK or MT_ERROR\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_reset_card(u_int8_t bus, u_int8_t dev_func);\r
-\r
-\r
-\r
-#endif /* H_MOSAL_BUS_H */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifdef __KERNEL__\r
-\r
-#include "mosal_priv.h"\r
-#include "MdIoctl.h"\r
-\r
-/* ----- Kernel Space ----- */\r
-\r
-call_result_t MOSAL_manual_wrapper( MOSAL_rsct_t *res_p, int cmd, void *pi, void * po)\r
-{\r
- call_result_t rc;\r
- switch ( cmd ) {\r
- case K2U_CBK_CBK_INIT:\r
- {\r
- k2u_cbk_hndl_t k2u_cbk_h;\r
-\r
- if ( res_p->k2u_cbk_h != INVALID_K2U_CBK_HNDL ) {\r
- MTL_ERROR1(MT_FLFMT("%s: called k2u_cbk_init() more than once for the same process - pid=%d"), __func__, MOSAL_getpid());\r
- return MT_ERROR;\r
- }\r
- rc = k2u_cbk_init(&k2u_cbk_h);\r
- if ( rc != MT_OK ) {\r
- return rc;\r
- }\r
- res_p->k2u_cbk_h = k2u_cbk_h;\r
- MTL_TRACE3(MT_FLFMT("%s: k2u_cbk_init() returned handle=%d"), __func__, k2u_cbk_h);\r
- /* return the result */\r
- memcpy(po, &k2u_cbk_h, sizeof(k2u_cbk_h));\r
- return rc;\r
- }\r
- break;\r
-\r
- case K2U_CBK_CBK_CLEANUP:\r
- {\r
- k2u_cbk_hndl_t k2u_cbk_h = *(k2u_cbk_hndl_t*)pi;\r
- rc = k2u_cbk_cleanup(k2u_cbk_h);\r
- if ( rc == MT_OK ) {\r
- if ( res_p->k2u_cbk_h != INVALID_K2U_CBK_HNDL ) {\r
- res_p->k2u_cbk_h = INVALID_K2U_CBK_HNDL;\r
- MTL_TRACE3(MT_FLFMT("%s: k2u_cbk_cleanup() freed handle %ld"), __func__, k2u_cbk_h);\r
- }\r
- else {\r
- MTL_ERROR1(MT_FLFMT("%s: called k2u_cbk_cleanup() while there was an invalid handle in mosal resource tracking"), __func__);\r
- }\r
- }\r
- return rc;\r
- }\r
- break;\r
-\r
- default:\r
- return -ENOTTY;\r
-\r
- }\r
-}\r
-\r
-#ifndef MT_BUILD_LIB\r
-NTSTATUS \r
-DriverEntry(\r
- IN PDRIVER_OBJECT pi_pDriverObject,\r
- IN PUNICODE_STRING pi_pRegistryPath\r
- )\r
-{ /* DriverEntry */\r
-\r
- DbgPrint("\n***** MOSAL_KL: DriverEntry()");\r
- return STATUS_SUCCESS;\r
-\r
-} /* DriverEntry */\r
-\r
-NTSTATUS DllInitialize(PUNICODE_STRING RegistryPath)\r
-{\r
- DbgPrint("\n***** MOSAL_KL: DllInitialize()");\r
- return STATUS_SUCCESS;\r
-}\r
-\r
-NTSTATUS DllUnload()\r
-{\r
- DbgPrint("\n***** MOSAL_KL: DllUnload()");\r
- return STATUS_SUCCESS;\r
-}\r
-#endif\r
-#endif\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "mosal_priv.h"\r
-#include <MdIoctl.h>\r
-\r
-#ifdef USE_TRACE\r
-void MOSAL_trace_init();\r
-#endif\r
-call_result_t MOSAL_mem_init();\r
-void MOSAL_mem_cleanup();\r
-static void calib_counts_per_sec(void);\r
-\r
-/* k2u_cbk prototype. Implemented in mosal_k2u_cbk.c */\r
-call_result_t MOSAL_k2u_cbk_mod_init(void);\r
-\r
-/* external variables */\r
-MOSAL_pid_t MOSAL_pid = 0;\r
-\r
-/* global variables */\r
-\r
-/* device DB */\r
-MOSAL_dev_t MOSAL_dev_db[MOSAL_MAXDEV]; \r
-\r
-/* current max irql */\r
-KIRQL cur_max_irql = DISPATCH_LEVEL;\r
-\r
-MOSAL_rsct_t * MOSAL_rsct_open(MOSAL_pid_t pid)\r
-{\r
- /* allocate resource element */\r
- MOSAL_rsct_t *res_p = (MOSAL_rsct_t*)TMALLOC(MOSAL_rsct_t);\r
- if (res_p == NULL) {\r
- MTL_ERROR4("MOSAL_rsct_open: allocation failed \n");\r
- }\r
- else {\r
- /* store mosal_mem resources */\r
- res_p->mosal_mem = MOSAL_mem_rsct_open(pid);\r
- /* store mosal_k2u_cbk resources */\r
- res_p->k2u_cbk_h = INVALID_K2U_CBK_HNDL;\r
- }\r
- return res_p;\r
-}\r
-\r
-void MOSAL_rsct_close(MOSAL_rsct_t * res_p, MOSAL_pid_t pid)\r
-{\r
- call_result_t rc;\r
- /* clean mosal_mlock resources */\r
- MOSAL_mlock_cleanup_pcs(pid);\r
- /* clean mosal_mem resources */\r
- MOSAL_mem_rsct_close(res_p->mosal_mem);\r
- /* clean mosal_k2u_cbk resources */\r
- if ( res_p->k2u_cbk_h != INVALID_K2U_CBK_HNDL ) {\r
- rc = k2u_cbk_cleanup(res_p->k2u_cbk_h);\r
- if ( rc != MT_OK ) {\r
- MTL_ERROR1(MT_FLFMT("k2u_cbk_cleanup failed, pid=%d (%s)"),\r
- pid,mtl_strerror_sym(rc));\r
- return;\r
- }\r
- }\r
- FREE(res_p);\r
-}\r
- \r
-/* exported functions */\r
-call_result_t MOSAL_init(unsigned int major)\r
-{\r
- call_result_t rc = init_dpc();\r
- if (rc)\r
- return rc;\r
- \r
- /*Initialize memory locking mechanizm*/\r
- rc = MOSAL_mlock_init();\r
- if (rc != MT_OK) {\r
- return(rc);\r
- }\r
-\r
- /*Initialize memory API*/\r
- rc = MOSAL_mem_init();\r
- if (rc != MT_OK) {\r
- return(rc);\r
- }\r
-\r
- /* Initialize k2u_cbk mechanism */\r
- rc = MOSAL_k2u_cbk_mod_init();\r
- if (rc != MT_OK) \r
- return(rc);\r
- /* not in use for now\r
- init_queues();\r
- */\r
- RtlZeroMemory(MOSAL_dev_db, sizeof(MOSAL_dev_db)); \r
- //calib_counts_per_sec();\r
-\r
- /* trace */\r
- #ifdef USE_TRACE\r
- MOSAL_trace_init();\r
- #endif\r
- \r
- return MT_OK;\r
-}\r
-\r
-void MOSAL_cleanup() \r
-{ \r
- RtlZeroMemory(MOSAL_dev_db, sizeof(MOSAL_dev_db)); \r
- deinit_dpc();\r
- MOSAL_mem_cleanup();\r
- MOSAL_mlock_cleanup();\r
-}\r
-\r
-MOSAL_pid_t MOSAL_getpid(void) \r
-{ \r
- return (MOSAL_pid_t)IoGetCurrentProcess();\r
-}\r
-\r
-void MOSAL_setpid(MOSAL_pid_t pid) \r
-{ \r
- MOSAL_pid = (MOSAL_pid_t)IoGetCurrentProcess();\r
-}\r
-\r
-bool MOSAL_is_privileged() { return TRUE; }\r
-\r
-/*\r
- * MOSAL_get_exec_ctx - get execution context\r
- */\r
-MOSAL_exec_ctx_t MOSAL_get_exec_ctx()\r
-{\r
- KIRQL irql = KeGetCurrentIrql();\r
- if (irql < DISPATCH_LEVEL)\r
- return MOSAL_IN_TASK;\r
- if (irql == DISPATCH_LEVEL)\r
- return MOSAL_IN_DPC;\r
- return MOSAL_IN_ISR;\r
-}\r
-\r
-/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\r
- * \r
- * Endian conversions\r
- *\r
- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_letobe64 \r
- *\r
- * Description:\r
- * ULONG conversion from little endian to big endian \r
- *\r
- * Parameters: \r
- * value(IN) u_int64_t\r
- *\r
- * Returns:\r
- * u_int64_t\r
- *\r
- \r
-******************************************************************************/\r
-u_int64_t MOSAL_letobe64( u_int64_t value )\r
-{\r
-#if 1\r
- /* it isn't supported really */\r
- return RtlUlonglongByteSwap(value);\r
-#else\r
- volatile u_int64_t res;\r
- *((volatile int * const)&res + 1) = RtlUlongByteSwap(*(volatile int * const)&value);\r
- *(volatile int * const)&res = RtlUlongByteSwap(*((volatile int * const)&value + 1));\r
- return res;\r
-#endif\r
-}\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_letobe32 \r
- *\r
- * Description:\r
- * ULONG conversion from little endian to big endian \r
- *\r
- * Parameters: \r
- * value(IN) u_int32_t\r
- *\r
- * Returns:\r
- * u_int32_t\r
- *\r
- \r
-******************************************************************************/\r
-u_int32_t MOSAL_letobe32( u_int32_t value )\r
-{\r
- return RtlUlongByteSwap(value);\r
-}\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_letobe16 \r
- *\r
- * Description:\r
- * USHORT conversion from little endian to big endian \r
- *\r
- * Parameters: \r
- * value(IN) u_int16_t\r
- *\r
- * Returns:\r
- * u_int16_t\r
- *\r
- \r
-******************************************************************************/\r
-u_int16_t MOSAL_letobe16( u_int16_t value )\r
-{\r
- return RtlUshortByteSwap(value);\r
-}\r
-\r
-u_int64_t MOSAL_get_counts_per_sec(void)\r
-{\r
- /* Number of 100ns increments in a second. */\r
- return 10000000;\r
-}\r
-\r
-u_int64_t MOSAL_nsecs(void) \r
-{ \r
- return KeQueryInterruptTime() * 100;\r
-}\r
-\r
-\r
-call_result_t MOSAL_reset_card(u_int8_t bus, u_int8_t dev_func)\r
-{\r
- call_result_t rc;\r
- MOSAL_dev_t *dev_p = find_device_by_location( bus, dev_func );\r
- if (dev_p == NULL) {\r
- MTL_ERROR1("MOSAL_reset_card: failed to find appropriate device (bus %d, dev_func 0x%02x)\n", (int)bus, dev_func);\r
- return MT_ERROR;\r
- }\r
- MTL_ERROR1("MOSAL_reset_card: calling driver to reset the card (bus %d, dev_func 0x%02x)\n", (int)bus, dev_func);\r
- rc = (call_result_t)((Md_Mosal_Helper_t)dev_p->drv_helper)( dev_p->drv_helper_ctx, MD_HELPER_CARD_RESET );\r
- if (rc != MT_OK)\r
- MTL_ERROR1("MOSAL_reset_card: failed to reset the card (rc 0x%x, bus %d, dev_func 0x%02x)\n", \r
- (u_int32_t)rc, (int)bus, dev_func);\r
- return rc;\r
-}\r
-\r
-\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_GEN_PRIV_H\r
-#define H_MOSAL_GEN_PRIV_H\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_nsecs\r
- *\r
- * Description: read the counter of S_TICKs (S_TICK is usually of 100 nsec duration)\r
- *\r
- * Parameters:\r
- *\r
- * Returns:\r
- * the value of counter of S_TICKs (n.b. S stands for "some" or "strange" )\r
- *\r
- ******************************************************************************/\r
-u_int64_t MOSAL_nsecs(void);\r
-\r
-#define MOSAL_TAKE64_LOW_ADDR(arg) ((long*)&(arg))\r
-#define MOSAL_TAKE64_HIGH_ADDR(arg) ((long*)&(arg)+1)\r
-#define MOSAL_TAKE64_LOW_VAL(arg) (*(MOSAL_TAKE64_LOW_ADDR(arg)))\r
-#define MOSAL_TAKE64_HIGH_VAL(arg) (*(MOSAL_TAKE64_HIGH_ADDR(arg)))\r
-\r
-#include "mosal_k2u_cbk.h"\r
-/* per process MOSAL resource tracking info */\r
-typedef struct {\r
- void * mosal_mem;\r
- k2u_cbk_hndl_t k2u_cbk_h; /* handle to callback db */\r
-} MOSAL_rsct_t;\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_rsct_open\r
- *\r
- ******************************************************************************/\r
-MOSAL_rsct_t *MOSAL_rsct_open(MOSAL_pid_t pid);\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_rsct_close\r
- *\r
- ******************************************************************************/\r
-void MOSAL_rsct_close(MOSAL_rsct_t *p_rsct, MOSAL_pid_t pid);\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_manual_wrapper\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_manual_wrapper( MOSAL_rsct_t *res_p, int cmd, void *pi, void * po);\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include <mtl_common.h>\r
-#include "mosal_iobuf_imp.h"\r
-#include "mosal_priv.h"\r
-\r
-\r
-// non-WDM implementation \r
-\r
-NTKERNELAPI\r
-PHYSICAL_ADDRESS\r
-MmGetPhysicalAddress (\r
- IN PVOID BaseAddress\r
- );\r
-\r
-/*\r
- * MOSAL_iobuf_get_props\r
- */\r
-call_result_t MOSAL_iobuf_get_props(MOSAL_iobuf_t iobuf,\r
- MOSAL_iobuf_props_t *props_p)\r
-{\r
- call_result_t rc;\r
-\r
- // sanity check\r
- if (!iobuf) return MT_EINVAL;\r
- \r
- props_p->size = iobuf->size;\r
- props_p->va = iobuf->va;\r
- props_p->nr_pages = iobuf->nr_pages;\r
- props_p->prot_ctx = iobuf->prot_ctx;\r
- rc = MOSAL_get_page_shift(MOSAL_get_current_prot_ctx(), iobuf->va, &props_p->page_shift);\r
- if ( rc != MT_OK ) {\r
- return rc;\r
- }\r
-\r
- return MT_OK;\r
-}\r
-\r
-\r
-\r
-/*\r
- * MOSAL_iobuf_register\r
- */\r
-static call_result_t register_segment(MT_virt_addr_t va,\r
- MT_size_t size,\r
- MOSAL_prot_ctx_t prot_ctx,\r
- MOSAL_mem_perm_t req_perm,\r
- MOSAL_iobuf_t iobuf_p)\r
-{\r
- PMDL mdl_p;\r
- call_result_t rc;\r
- KPROCESSOR_MODE mode; \r
- MOSAL_iobuf_seg_t new_iobuf;\r
- static ULONG cnt=0;\r
- LOCK_OPERATION Operation;\r
- int n_tries=1, retry = 0, try_num=1;\r
- int fake_ro =0;\r
- \r
- // set Operation\r
- if ((req_perm & MOSAL_PERM_READ) && (req_perm & MOSAL_PERM_WRITE))\r
- Operation = IoModifyAccess;\r
- else\r
- if (req_perm & MOSAL_PERM_WRITE)\r
- Operation = IoWriteAccess;\r
- else\r
- if (req_perm & MOSAL_PERM_READ)\r
- Operation = IoReadAccess;\r
- else {\r
- MTL_ERROR4("MOSAL_iobuf_register: Illegal permission parameter (%d)\n", req_perm);\r
- rc = MT_EINVAL;\r
- goto err0;\r
- }\r
- \r
- // allocate IOBUF segment object\r
- new_iobuf = (MOSAL_iobuf_seg_t)TMALLOC(struct mosal_iobuf_seg_st);\r
- if (new_iobuf == NULL) {\r
- MTL_ERROR4("MOSAL_iobuf_register: TMALLOC failed\n");\r
- rc = MT_EKMALLOC;\r
- goto err0;\r
- }\r
- \r
- // allocate MDL \r
- mdl_p = IoAllocateMdl( (PVOID)va, (ULONG)size, FALSE,FALSE,NULL);\r
- if (mdl_p == NULL) {\r
- MTL_ERROR4("MOSAL_iobuf_register: IoAllocateMdl failed, va %p, sz %d\n", va, size);\r
- rc = MT_EKMALLOC;\r
- goto err1;\r
- }\r
-\r
- // make context-dependent things\r
- if (prot_ctx == MOSAL_PROT_CTX_KERNEL) { /* Mapping to kernel virtual address */\r
-// MmBuildMdlForNonPagedPool(mdl_p); // fill MDL ??? - should we do that really ?\r
- mode = KernelMode;\r
- }\r
- else {\r
- ASSERT(KeGetCurrentIrql() < DISPATCH_LEVEL);\r
- mode = UserMode;\r
- }\r
-\r
- // fake RO access: in case of MOSAL_PERM_READ access we replace by MOSAL_PERM_WRITE to enforce rw pa list\r
- if (Operation == IoReadAccess) {\r
- fake_ro = 1;\r
- Operation = IoWriteAccess;\r
- }\r
-\r
-check_va_validity:\r
- __try\r
- { /* try */\r
- MmProbeAndLockPages( mdl_p, mode, Operation ); /* lock memory */\r
- } /* try */\r
- \r
- __except (EXCEPTION_EXECUTE_HANDLER)\r
- {\r
- NTSTATUS Status = GetExceptionCode();\r
- MTL_ERROR4("MOSAL_iobuf_register: Exception 0x%x on MmProbeAndLockPages(), va %p, sz %d, try_num %d\n", \r
- Status, va, size, try_num);\r
- if (Status != STATUS_ACCESS_VIOLATION) {\r
- /* usually, c00000a1 - process memory quote is exceeded */\r
- rc = MT_EAGAIN;\r
- goto err2;\r
- }\r
- // fake RO access\r
- if (fake_ro) {\r
- fake_ro = 0;\r
- Operation = IoReadAccess;\r
- goto check_va_validity;\r
- }\r
- \r
- //\r
- // case STATUS_ACCESS_VIOLATION: try to understand whether va is valid\r
- //\r
-\r
- // mark, that we are in retry mode\r
- retry = 1;\r
-\r
- // failure on IoModifyAccess mode is unclear case - we'll read and write in this case\r
- if (Operation == IoModifyAccess) {\r
- Operation = IoReadAccess;\r
- n_tries = 2;\r
- }\r
-\r
- // we perform all the tries with the same STATUS_ACCESS_VIOLATION result\r
- if (n_tries <= 0) {\r
- /* adress is not valid */\r
- rc = MT_ENOMEM;\r
- goto err2;\r
- }\r
-\r
- // switch the mode\r
- if (Operation == IoReadAccess) \r
- Operation = IoWriteAccess;\r
- else\r
- Operation = IoReadAccess;\r
-\r
- // try once more\r
- n_tries--; try_num++;\r
- goto check_va_validity;\r
- \r
- }\r
-\r
- // fake RO access\r
- if (fake_ro) {\r
- fake_ro = 0;\r
- MmUnlockPages( mdl_p ); // unlock the buffer \r
- Operation = IoReadAccess;\r
- goto check_va_validity;\r
- }\r
-\r
- // check, whether we failed the first time\r
- if (retry) {\r
- MmUnlockPages( mdl_p ); // unlock the buffer \r
- rc = MT_EPERM;\r
- goto err2;\r
- }\r
-\r
- if( mode == UserMode )\r
- {\r
- if (req_perm & MOSAL_PERM_WRITE)\r
- {\r
- new_iobuf->h_secure = MmSecureVirtualMemory(\r
- (PVOID)va, (SIZE_T)size, PAGE_READWRITE );\r
- }\r
- else\r
- {\r
- new_iobuf->h_secure = MmSecureVirtualMemory(\r
- (PVOID)va, (SIZE_T)size, PAGE_READONLY );\r
- }\r
-\r
- if( !new_iobuf->h_secure )\r
- {\r
- rc = MT_EPERM;\r
- goto err3;\r
- }\r
- }\r
- else\r
- {\r
- new_iobuf->h_secure = NULL;\r
- }\r
-\r
- // fill IOBUF object\r
- new_iobuf->va = va;\r
- new_iobuf->size= size;\r
- new_iobuf->nr_pages = ADDRESS_AND_SIZE_TO_SPAN_PAGES( va, size );\r
- new_iobuf->mdl_p = mdl_p;\r
- new_iobuf->prot_ctx = prot_ctx;\r
- MOSAL_dlist_insert_tail( &iobuf_p->seg_que, &new_iobuf->link );\r
- return MT_OK;\r
-\r
-err3:\r
- MmUnlockPages( mdl_p );\r
-err2:\r
- IoFreeMdl(mdl_p);\r
-err1: \r
- FREE((PVOID)new_iobuf);\r
-err0: \r
- return rc;\r
-}\r
-\r
-static void deregister_segment(MOSAL_iobuf_seg_t iobuf_seg_p)\r
-{\r
- if( iobuf_seg_p->h_secure )\r
- MmUnsecureVirtualMemory( iobuf_seg_p->h_secure);\r
- MmUnlockPages( iobuf_seg_p->mdl_p ); // unlock the buffer \r
- IoFreeMdl( iobuf_seg_p->mdl_p ); // free MDL\r
- FREE(iobuf_seg_p);\r
-}\r
-\r
-/*\r
- * MOSAL_iobuf_register\r
- */\r
-call_result_t MOSAL_iobuf_register(MT_virt_addr_t va,\r
- MT_size_t size,\r
- MOSAL_prot_ctx_t prot_ctx,\r
- MOSAL_mem_perm_t req_perm,\r
- MOSAL_iobuf_t *iobuf_p,\r
- u_int32_t flags)\r
-{\r
- call_result_t rc;\r
- MOSAL_iobuf_t new_iobuf; // new allocated IOBUF object\r
- MT_virt_addr_t seg_va; // current segment start\r
- MT_size_t seg_size; // current segment size\r
- MT_size_t rdc; // remain data counter - what is rest to lock\r
- MT_size_t delta; // he size of the last not full page of the first segment\r
- MOSAL_iobuf_seg_t iobuf_seg_p; // pointer to current segment object\r
- unsigned page_size;\r
- \r
-// 32 - for any case \r
-#define PFNS_IN_PAGE_SIZE_MDL ((PAGE_SIZE - sizeof(struct _MDL) - 32) / sizeof(long))\r
-#define MIN_IOBUF_SEGMENT_SIZE (PAGE_SIZE * PFNS_IN_PAGE_SIZE_MDL) // 4MB \r
-\r
- ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL);\r
-\r
- // sanity checks\r
- if ( !iobuf_p ) return MT_EINVAL;\r
- if ( size == 0 ) return MT_EINVAL;\r
- if ( va == VA_NULL ) return MT_EINVAL;\r
-\r
- // allocate IOBUF object\r
- new_iobuf = (MOSAL_iobuf_t)TMALLOC(struct mosal_iobuf_st);\r
- if (new_iobuf == NULL) {\r
- MTL_ERROR4("MOSAL_iobuf_register: TMALLOC failed, va %p, sz %d\n", va, size);\r
- rc = MT_EAGAIN;\r
- goto err0;\r
- }\r
- \r
- // init IOBUF object\r
- MOSAL_dlist_init_head( &new_iobuf->seg_que );\r
- new_iobuf->seg_num = 0;\r
-\r
- // Round the seg_va down to a page boundary so that we always get a seg_size\r
- // that is an integral number of pages.\r
- delta = va & (PAGE_SIZE - 1);\r
- seg_va = va - delta;\r
- // Since we rounded down the seg_va, we need to round up the rdc and size.\r
- seg_size = rdc = size + delta;\r
-\r
- // allocate segments\r
- while (rdc > 0) {\r
- // map a segment\r
- rc = register_segment(seg_va, seg_size, prot_ctx, req_perm, new_iobuf );\r
-\r
- // success - move to another segment\r
- if (rc == MT_OK) {\r
- rdc -= seg_size;\r
- seg_va += seg_size;\r
- new_iobuf->seg_num++;\r
- if (seg_size > rdc)\r
- seg_size = rdc;\r
- continue;\r
- }\r
-\r
- // failure - too large a buffer: lessen it and try once more\r
- if (rc == MT_EKMALLOC) {\r
- // no where to lessen - too low memory\r
- if (seg_size <= MIN_IOBUF_SEGMENT_SIZE)\r
- break;\r
- // lessen the size\r
- seg_size >>= 1;\r
- // round the segment size to the page boundary (only for the first segment)\r
- if (new_iobuf->seg_num == 0) {\r
- rc = MOSAL_get_page_size( prot_ctx, seg_va, &page_size );\r
- if (rc != MT_OK) \r
- break;\r
- delta = ((ULONG_PTR)seg_va + seg_size) & (page_size - 1);\r
- seg_size -= delta;\r
- seg_size += page_size;\r
- if (seg_size > rdc)\r
- seg_size = rdc;\r
- }\r
- continue;\r
- }\r
-\r
- // got unrecoverable error\r
- break;\r
- }\r
-\r
- // SUCCESS\r
- if ( rc == MT_OK) {\r
- // fill IOBUF object\r
- new_iobuf->va = va;\r
- new_iobuf->size= size;\r
- new_iobuf->nr_pages = ADDRESS_AND_SIZE_TO_SPAN_PAGES( va, size );\r
- new_iobuf->prot_ctx = prot_ctx;\r
- *iobuf_p = new_iobuf;\r
- MTL_DEBUG4("MOSAL_iobuf_register: registered buffer va %p, sz %d, seg_num %d\n", va, size, new_iobuf->seg_num);\r
- return MT_OK;\r
- }\r
- \r
- // FAILURE - release segments\r
- while (!MOSAL_dlist_is_empty( &new_iobuf->seg_que )) {\r
- iobuf_seg_p = (MOSAL_iobuf_seg_t)(PVOID)MOSAL_dlist_remove_tail( &new_iobuf->seg_que );\r
- deregister_segment(iobuf_seg_p);\r
- new_iobuf->seg_num--;\r
- }\r
- ASSERT(new_iobuf->seg_num == 0);\r
-\r
- FREE((PVOID)new_iobuf);\r
-err0: \r
- return rc;\r
-}\r
-\r
-\r
-\r
-/*\r
- * MOSAL_iobuf_deregister\r
- */\r
-call_result_t MOSAL_iobuf_deregister(MOSAL_iobuf_t iobuf_p)\r
-{\r
- MOSAL_iobuf_seg_t iobuf_seg_p; // pointer to current segment object\r
- \r
- ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL);\r
-\r
- // sanity check\r
- if (!iobuf_p) return MT_EINVAL;\r
-\r
- // release segments\r
- while (!MOSAL_dlist_is_empty( &iobuf_p->seg_que )) {\r
- iobuf_seg_p = (MOSAL_iobuf_seg_t)(PVOID)MOSAL_dlist_remove_tail( &iobuf_p->seg_que );\r
- deregister_segment(iobuf_seg_p);\r
- iobuf_p->seg_num--;\r
- }\r
- ASSERT(iobuf_p->seg_num == 0);\r
- \r
- // release the rest\r
- FREE(iobuf_p);\r
- \r
- return MT_OK;\r
-}\r
-\r
-\r
-\r
-/*\r
- * MOSAL_iobuf_get_tpt\r
- */\r
-call_result_t MOSAL_iobuf_get_tpt(MOSAL_iobuf_t iobuf,\r
- u_int32_t npages,\r
- MT_phys_addr_t *pa_arr,\r
- u_int32_t *page_size_p,\r
- u_int32_t *act_table_sz_p)\r
-{\r
- u_int32_t i, cnt = MT_MIN(npages,iobuf->nr_pages);\r
- MOSAL_iobuf_seg_t iobuf_seg_p = (MOSAL_iobuf_seg_t)iobuf->seg_que.Flink; // pointer to current segment object\r
- PPFN_NUMBER pfn_p;\r
- MT_phys_addr_t *pa_buf_p = pa_arr;\r
- call_result_t rc;\r
- u_int32_t pg_sz;\r
- u_int32_t pg_shift;\r
-\r
- // get page shift\r
- rc = MOSAL_get_page_shift(MOSAL_get_current_prot_ctx(), iobuf->va, &pg_shift);\r
- if ( rc != MT_OK ) {\r
- return rc;\r
- }\r
- \r
- // get page size\r
- rc = MOSAL_get_page_size(MOSAL_get_current_prot_ctx(), iobuf->va, &pg_sz);\r
- if ( rc != MT_OK ) {\r
- return rc;\r
- }\r
- \r
- ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL);\r
-\r
- // sanity check\r
- if (!iobuf) return MT_EINVAL;\r
-\r
- //\r
- // copy phys addresses\r
- //\r
-\r
- // pass along the chain of segments\r
- for (; (PVOID)iobuf_seg_p != (PVOID)&iobuf->seg_que; iobuf_seg_p = (MOSAL_iobuf_seg_t)iobuf_seg_p->link.Flink ) {\r
- // get the start of PFN array\r
- pfn_p = MmGetMdlPfnArray( iobuf_seg_p->mdl_p );\r
- // for all the pages in this array\r
- for (i = 0; i < iobuf_seg_p->nr_pages; i++, pa_buf_p++, pfn_p++) {\r
- // convert PFN to the physical address\r
- *pa_buf_p = (MT_phys_addr_t)*pfn_p << pg_shift;\r
- // for the very first page - add the offset from the start of the page\r
- if (pa_buf_p == pa_arr)\r
- *pa_buf_p |= iobuf->va & (pg_sz - 1);\r
- // if the user's buffer is full - exit\r
- if (--cnt == 0)\r
- goto exit;\r
- }\r
- }\r
- \r
-exit: \r
- if (page_size_p) *page_size_p = pg_sz;\r
- if (act_table_sz_p) *act_table_sz_p = iobuf->nr_pages;\r
- return MT_OK;\r
-}\r
-\r
-\r
-/*\r
- * MOSAL_iobuf_iter_init\r
- */\r
-call_result_t MOSAL_iobuf_iter_init(MOSAL_iobuf_t iobuf, MOSAL_iobuf_iter_t *iterator_p)\r
-{\r
- iterator_p->seg_p = (MOSAL_iobuf_seg_t)iobuf->seg_que.Flink;\r
- iterator_p->pfn_ix = 0;\r
- return MT_OK;\r
-}\r
-\r
-/*\r
- * MOSAL_iobuf_cmp_tpt\r
- */\r
-int MOSAL_iobuf_cmp_tpt( MOSAL_iobuf_t iobuf1_p, MOSAL_iobuf_t iobuf2_p )\r
-{\r
- u_int32_t i;\r
- MOSAL_iobuf_seg_t seg1_p; // pointer to current segment object in 1st iobuf\r
- MOSAL_iobuf_seg_t seg2_p; // pointer to current segment object in 2nd iobuf\r
- PPFN_NUMBER pfn1_p, pfn2_p; \r
- u_int32_t pfn_ix1, pfn_ix2; // inde of PFN in PFN array of the current segment\r
-\r
- //\r
- // the case of different protection contexts -count that as an error\r
- //\r
- if ( iobuf1_p->prot_ctx != iobuf2_p->prot_ctx ) \r
- return -1;\r
-\r
- //\r
- // a case where both iobufs are in kernel space\r
- //\r
- if ( iobuf1_p->prot_ctx == MOSAL_get_kernel_prot_ctx() ) {\r
- if ( (iobuf1_p->va!=iobuf2_p->va) || (iobuf1_p->size!=iobuf2_p->size) ) \r
- return -1;\r
- return 0;\r
- }\r
-\r
- // \r
- // a case where both iobufs are in user space(s)\r
- //\r
-\r
- // quick checks\r
- /* differrent sizes */\r
- if ( iobuf1_p->nr_pages !=iobuf2_p->nr_pages ) \r
- return -1;\r
-\r
- // prepare to the loop\r
- seg1_p = (MOSAL_iobuf_seg_t)iobuf1_p->seg_que.Flink; // first segment of the first iobuf\r
- seg2_p = (MOSAL_iobuf_seg_t)iobuf2_p->seg_que.Flink; // first segment of the second iobuf\r
- pfn1_p = MmGetMdlPfnArray( seg1_p->mdl_p );\r
- pfn2_p = MmGetMdlPfnArray( seg2_p->mdl_p );\r
- pfn_ix1= pfn_ix2=0;\r
- \r
- // pass along all the PFN arrays\r
- for (i = 0; i < iobuf1_p->nr_pages; i++) {\r
- // compare page numbers\r
- if (*pfn1_p++ != *pfn2_p++) \r
- return -1;\r
- \r
- // get to the next PFN of the 1st iobuf\r
- if (++pfn_ix1 >= seg1_p->nr_pages) {\r
- seg1_p = (MOSAL_iobuf_seg_t)seg1_p->link.Flink;\r
- if ((PVOID)seg1_p == (PVOID)&iobuf1_p->seg_que) {\r
- i++;\r
- break;\r
- }\r
- pfn1_p = MmGetMdlPfnArray( seg1_p->mdl_p );\r
- pfn_ix1 = 0;\r
- }\r
- \r
- // get to the next PFN of the 2nd iobuf\r
- if (++pfn_ix2 >= seg2_p->nr_pages) {\r
- seg2_p = (MOSAL_iobuf_seg_t)seg2_p->link.Flink;\r
- if ((PVOID)seg2_p == (PVOID)&iobuf2_p->seg_que) {\r
- i++;\r
- break;\r
- }\r
- pfn2_p = MmGetMdlPfnArray( seg2_p->mdl_p );\r
- pfn_ix2 = 0;\r
- }\r
- }\r
-\r
- ASSERT( i == iobuf1_p->nr_pages);\r
- return 0;\r
-}\r
-\r
-\r
-\r
-/*\r
- * MOSAL_iobuf_get_tpt_seg\r
- */\r
-call_result_t MOSAL_iobuf_get_tpt_seg(MOSAL_iobuf_t iobuf, MOSAL_iobuf_iter_t *iterator_p,\r
- MT_size_t n_pages_in, MT_size_t *n_pages_out_p,\r
- MT_phys_addr_t *page_tbl_p)\r
-{\r
- u_int32_t i=0;\r
- MOSAL_iobuf_seg_t seg_p; // pointer to current segment object \r
- PPFN_NUMBER pfn_p; \r
- u_int32_t pfn_ix; // index of PFN in PFN array of the current segment\r
- MT_phys_addr_t *pa_buf_p = page_tbl_p;\r
- call_result_t rc;\r
- u_int32_t pg_sz;\r
- u_int32_t pg_shift;\r
-\r
- // get page shift\r
- rc = MOSAL_get_page_shift(MOSAL_get_current_prot_ctx(), iobuf->va, &pg_shift);\r
- if ( rc != MT_OK ) {\r
- return rc;\r
- }\r
- \r
- // get page size\r
- rc = MOSAL_get_page_size(MOSAL_get_current_prot_ctx(), iobuf->va, &pg_sz);\r
- if ( rc != MT_OK ) {\r
- return rc;\r
- }\r
- \r
-\r
- // prepare to the loop\r
- seg_p = iterator_p->seg_p; // first segment of the first iobuf\r
- pfn_ix= iterator_p->pfn_ix;\r
- if ((PVOID)seg_p == (PVOID)&iobuf->seg_que)\r
- goto exit;\r
- pfn_p = MmGetMdlPfnArray( seg_p->mdl_p ) + pfn_ix;\r
- \r
- // pass along all the PFN arrays\r
- for (; i < n_pages_in; i++, pa_buf_p++) {\r
- // convert PFN to the physical address\r
- *pa_buf_p = (MT_phys_addr_t)*pfn_p++ << pg_shift;\r
- \r
- // for the very first page - add the offset from the start of the page\r
- if (pa_buf_p == page_tbl_p)\r
- *pa_buf_p |= iobuf->va & (pg_sz - 1);\r
- \r
- // get to the next PFN \r
- if (++pfn_ix >= seg_p->nr_pages) {\r
- seg_p = (MOSAL_iobuf_seg_t)seg_p->link.Flink;\r
- pfn_ix = 0;\r
- if ((PVOID)seg_p == (PVOID)&iobuf->seg_que) {\r
- i++;\r
- break;\r
- }\r
- pfn_p = MmGetMdlPfnArray( seg_p->mdl_p );\r
- }\r
- }\r
-\r
-exit:\r
- iterator_p->seg_p = seg_p;\r
- iterator_p->pfn_ix = pfn_ix;\r
- *n_pages_out_p = i;\r
- return MT_OK;\r
-}\r
-\r
-/*\r
- * MOSAL_iobuf_ctx_init\r
- */\r
-call_result_t MOSAL_iobuf_ctx_init(MOSAL_mlock_ctx_t *mlock_ctx_p)\r
-{\r
- return MT_OK; // ??\r
-}\r
-\r
-/*\r
- * MOSAL_iobuf_ctx_cleanup\r
- */\r
-call_result_t MOSAL_iobuf_ctx_cleanup(MOSAL_mlock_ctx_t mlock_ctx)\r
-{\r
- return MT_OK; // ??\r
-}\r
-\r
-/*\r
- * MOSAL_iobuf_restore_perm\r
- */\r
-call_result_t MOSAL_iobuf_restore_perm(MOSAL_iobuf_t iobuf)\r
-{\r
- return MT_ENOSYS;\r
-}\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef __MOSAL_IOBUF_IMP__H\r
-#define __MOSAL_IOBUF_IMP__H\r
- \r
- \r
-#ifdef __KERNEL__\r
-#include <mosal.h>\r
-\r
-/* segment */\r
-struct mosal_iobuf_seg_st {\r
- LIST_ENTRY link;\r
- PMDL mdl_p;\r
- MT_virt_addr_t va; /* virtual address of the buffer */\r
- MT_size_t size; /* size in bytes of the buffer */\r
- u_int32_t nr_pages;\r
- MOSAL_prot_ctx_t prot_ctx;\r
- void *h_secure;\r
-};\r
-\r
-typedef struct mosal_iobuf_seg_st * MOSAL_iobuf_seg_t;\r
-\r
-/* iterator for getting segments of tpt */\r
-struct mosal_iobuf_iter_st {\r
- MOSAL_iobuf_seg_t seg_p; /* the item from where to take the next translations */\r
- unsigned int pfn_ix; /* index from where to take the next translation */\r
-};\r
-\r
- \r
-\r
-struct mosal_iobuf_st {\r
- MT_virt_addr_t va; /* virtual address of the buffer */\r
- MT_size_t size; /* size in bytes of the buffer */\r
- u_int32_t nr_pages;\r
- MOSAL_prot_ctx_t prot_ctx;\r
- LIST_ENTRY seg_que;\r
- int seg_num;\r
-};\r
-#endif\r
-\r
-call_result_t MOSAL_iobuf_init(void);\r
-void MOSAL_iobuf_cleanup(void);\r
- \r
-#endif /* __MOSAL_IOBUF_IMP__H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#define C_K2U_CBK_K_C\r
-\r
-#include <limits.h>\r
-\r
-#include "mosal_priv.h"\r
-/* Maximum processes supported */\r
-#define MAX_PROCS 256\r
-/* Max outstanding calls per process - additional calls will be lost */\r
-#define LOG2_MAX_OUTS_CALLS_PER_PROC 7\r
-#define MAX_OUTS_CALLS_PER_PROC (1<<LOG2_MAX_OUTS_CALLS_PER_PROC)\r
-#define MAX_OUTS_CALLS_MASK (MAX_OUTS_CALLS_PER_PROC-1)\r
-\r
-/* message queue format */\r
-typedef struct {\r
- k2u_cbk_id_t id;\r
- u_int8_t *data_p;\r
- MT_size_t size;\r
-} cbk_msg_t;\r
-\r
-/* Process callback data */\r
-typedef struct {\r
- MOSAL_semaphore_t qsem; /* semaphore to count outstanding messages in queue */\r
- cbk_msg_t msg_q[MAX_OUTS_CALLS_PER_PROC]; /* message queue cyclic buffer */\r
- volatile u_int32_t prod; /* producer index for msg_q buffer */\r
- volatile u_int32_t cons; /* consumer index for msg_q buffer */\r
- MT_ulong_ptr_t tid; /* Thread id - to identify polling thread */\r
- MT_ulong_ptr_t pid; /* Process id (to identify "cleanup" invoker) */\r
- u_int32_t ref_cnt; /* reference count of consumers of this module */\r
-} proc_cbk_dat_t;\r
-\r
-\r
-static MOSAL_spinlock_t cbk_dat_lock; /* Protect structured below */\r
-/* Callback data per process (handles) */\r
-static proc_cbk_dat_t* cbk_db[MAX_PROCS]={NULL};\r
-\r
-static call_result_t k2u_cbk_rsrc_cleanup(k2u_cbk_hndl_t k2u_cbk_h);\r
-\r
-/* Initialization for this module */\r
-call_result_t MOSAL_k2u_cbk_mod_init(void)\r
-{\r
- MOSAL_spinlock_init(&cbk_dat_lock);\r
- return MT_OK;\r
-}\r
-\r
-\r
-call_result_t k2u_cbk_init(k2u_cbk_hndl_t *k2u_cbk_h_p)\r
-{\r
- k2u_cbk_hndl_t free_hndl;\r
- proc_cbk_dat_t *new_proc;\r
-\r
- if ( !k2u_cbk_h_p ) return MT_EINVAL;\r
-/* Allocate and initialize new callback context entrry */\r
- new_proc= (proc_cbk_dat_t*)MALLOC(sizeof(proc_cbk_dat_t));\r
- if (new_proc == NULL) {\r
- MTL_ERROR1("%s: Cannot allocate vmem for proc_cbk_dat_t\n", __func__);\r
- return MT_EAGAIN;\r
- }\r
- new_proc->cons= new_proc->prod= 0; /* init consumer-producer buffer */\r
- new_proc->tid= (MT_ulong_ptr_t)KeGetCurrentThread();\r
- new_proc->pid= MOSAL_getpid();\r
- new_proc->ref_cnt = 1;\r
- MOSAL_sem_init(&(new_proc->qsem),0);\r
-\r
- /* Insert context to handles array */\r
-\r
- MOSAL_spinlock_dpc_lock(&cbk_dat_lock);\r
-\r
- /* Find free handle */\r
- for (free_hndl= 0; free_hndl < MAX_PROCS; free_hndl++) {\r
- if (cbk_db[free_hndl] == NULL) break;\r
- }\r
- if (free_hndl == MAX_PROCS) { /* no free entry */\r
- MOSAL_spinlock_unlock(&cbk_dat_lock);\r
- FREE(new_proc);\r
- MTL_ERROR4(MT_FLFMT("No resources for registering additional processes (max.=%d)"),\r
- MAX_PROCS);\r
- return MT_EAGAIN;\r
- }\r
- \r
- cbk_db[free_hndl]= new_proc;\r
- \r
- MOSAL_spinlock_unlock(&cbk_dat_lock);\r
-\r
- MTL_DEBUG4("%s: allocated cbk handle %d for tid=" MT_ULONG_PTR_FMT ".\n", __func__,\r
- free_hndl,KeGetCurrentThread());\r
- \r
- *k2u_cbk_h_p = free_hndl;\r
- return MT_OK;\r
-}\r
-\r
-\r
-call_result_t k2u_cbk_cleanup(k2u_cbk_hndl_t k2u_cbk_h)\r
-{\r
- MOSAL_spinlock_dpc_lock(&cbk_dat_lock);\r
- if ( (k2u_cbk_h>=MAX_PROCS) ||\r
- (k2u_cbk_h==INVALID_K2U_CBK_HNDL) ||\r
- (cbk_db[k2u_cbk_h]==NULL) ) {\r
- MOSAL_spinlock_unlock(&cbk_dat_lock);\r
- MTL_ERROR1(MT_FLFMT("%s: called with invalid handle"), __func__);\r
- return MT_EINVAL;\r
- }\r
- MOSAL_spinlock_unlock(&cbk_dat_lock);\r
-\r
- k2u_cbk_invoke(k2u_cbk_h,K2U_CBK_CLEANUP_CBK_ID,NULL,0);\r
-\r
- return k2u_cbk_rsrc_cleanup(k2u_cbk_h);\r
-}\r
-\r
-static inline call_result_t rm_db_entry(k2u_cbk_hndl_t k2u_cbk_h)\r
-{\r
- proc_cbk_dat_t *rm_proc;\r
-\r
- rm_proc= cbk_db[k2u_cbk_h];\r
- MOSAL_spinlock_dpc_lock(&cbk_dat_lock);\r
- cbk_db[k2u_cbk_h]= NULL; /* remove from db and only after free resources */\r
- MOSAL_spinlock_unlock(&cbk_dat_lock);\r
- /* Free resources allocated in queue */\r
- FREE(rm_proc);\r
- return MT_OK;\r
-}\r
-\r
-static call_result_t k2u_cbk_rsrc_cleanup(k2u_cbk_hndl_t k2u_cbk_h)\r
-{\r
- proc_cbk_dat_t *cbk_p = NULL;\r
-\r
- MOSAL_spinlock_dpc_lock(&cbk_dat_lock);\r
- MTL_TRACE3(MT_FLFMT("%s called with handle=%d"), __func__, k2u_cbk_h);\r
- if ( (k2u_cbk_h>=MAX_PROCS) ||\r
- (k2u_cbk_h==INVALID_K2U_CBK_HNDL) ||\r
- (cbk_db[k2u_cbk_h]==NULL) ) {\r
- MOSAL_spinlock_unlock(&cbk_dat_lock);\r
- MTL_ERROR1(MT_FLFMT("%s: invalid handle=%d"), __func__, k2u_cbk_h);\r
- return MT_EINVAL;\r
- }\r
- if ( cbk_db[k2u_cbk_h]->pid != MOSAL_getpid() ) {\r
- MOSAL_spinlock_unlock(&cbk_dat_lock);\r
- MTL_ERROR1(MT_FLFMT("%s: tried to cleanup but belongs to a different pgrp"), __func__);\r
- return MT_EPERM;\r
- }\r
- cbk_db[k2u_cbk_h]->ref_cnt--;\r
- MTL_TRACE3(MT_FLFMT("%s: ref_cnt=%d"), __func__, cbk_db[k2u_cbk_h]->ref_cnt);\r
- if ( cbk_db[k2u_cbk_h]->ref_cnt == 0 ) {\r
- cbk_p = cbk_db[k2u_cbk_h];\r
- cbk_db[k2u_cbk_h] = NULL;\r
- }\r
- MOSAL_spinlock_unlock(&cbk_dat_lock);\r
- if ( cbk_p ) {\r
- FREE(cbk_p);\r
- }\r
- return MT_OK;\r
-}\r
-\r
-\r
-/* This function is assumed to be invoked by a single (cbk_polling) thread, per k2u_cbk handle */\r
-/* Since this is the only context that the callback entry may be removed\r
- * we do not bother to hold the mutex.\r
- * Only on entry removedl (rm_db_entry) the mutex is held to sync. with k2u_cbk_invoke()\r
- */\r
-call_result_t k2u_cbk_pollq(k2u_cbk_hndl_t k2u_cbk_h,\r
- k2u_cbk_id_t *cbk_id_p,void *data_p, MT_size_t *size_p)\r
-{\r
- volatile cbk_msg_t *msg_p;\r
- MT_ulong_ptr_t cur_tid = (MT_ulong_ptr_t)KeGetCurrentThread();\r
- \r
- MOSAL_spinlock_dpc_lock(&cbk_dat_lock);\r
- \r
- if ( (k2u_cbk_h>MAX_PROCS) ||\r
- (k2u_cbk_h==INVALID_K2U_CBK_HNDL) ||\r
- (cbk_db[k2u_cbk_h] == NULL) ) {\r
- MOSAL_spinlock_unlock(&cbk_dat_lock);\r
- MTL_ERROR4(MT_FLFMT("%s: Invalid handle (%d)"), __func__, k2u_cbk_h);\r
- return MT_EINVAL;\r
- }\r
-\r
- if (cbk_db[k2u_cbk_h]->tid != cur_tid) {\r
- MTL_ERROR1(MT_FLFMT(\r
- "Polling request was tried by thread with tid " MT_ULONG_PTR_FMT " != polling thread tid (" MT_ULONG_PTR_FMT ")"),\r
- cur_tid,cbk_db[k2u_cbk_h]->tid);\r
- MOSAL_spinlock_unlock(&cbk_dat_lock);\r
- return MT_EPERM;\r
- }\r
-\r
- cbk_db[k2u_cbk_h]->ref_cnt++;\r
- MTL_TRACE3(MT_FLFMT("%s: ref_cnt=%d"), __func__, cbk_db[k2u_cbk_h]->ref_cnt);\r
- /* Now that we are sure that the real (only) queue owner is invoking this function\r
- * we can relase the mutex since the handle entry cannot be removed by another \r
- * thread (this function is the only access to rm_db_entry() ).\r
- * No synchronization is required in regard to consumer index (update by this thread only)\r
- */\r
- MOSAL_spinlock_unlock(&cbk_dat_lock);\r
-\r
- if (MOSAL_sem_acq(&(cbk_db[k2u_cbk_h]->qsem),TRUE) != MT_OK) {\r
- MTL_DEBUG4(MT_FLFMT("MOSAL_sem_acq for qsem was interrupted."));\r
- k2u_cbk_rsrc_cleanup(k2u_cbk_h);\r
- return MT_EINTR;\r
- }\r
- \r
- MTL_TRACE3(MT_FLFMT("%s: woke up with a new id=%d"), __func__, *cbk_id_p);\r
-\r
- if (cbk_db[k2u_cbk_h]->cons == cbk_db[k2u_cbk_h]->prod) {\r
- MTL_ERROR2(MT_FLFMT("Passed queue semaphore but found no message (hndl=%d, tid=" MT_ULONG_PTR_FMT ")"),\r
- k2u_cbk_h,KeGetCurrentThread());\r
- k2u_cbk_rsrc_cleanup(k2u_cbk_h);\r
- return MT_EAGAIN;\r
- }\r
-\r
- msg_p= cbk_db[k2u_cbk_h]->msg_q+cbk_db[k2u_cbk_h]->cons;\r
- *cbk_id_p = msg_p->id;\r
- *size_p = msg_p->size;\r
- if (msg_p->size > 0) {\r
- memcpy( data_p,msg_p->data_p,msg_p->size);\r
- FREE(msg_p->data_p);\r
- }\r
- cbk_db[k2u_cbk_h]->cons= (cbk_db[k2u_cbk_h]->cons+1) & MAX_OUTS_CALLS_MASK;\r
- \r
- k2u_cbk_rsrc_cleanup(k2u_cbk_h);\r
- return MT_OK; \r
-}\r
-\r
-\r
-call_result_t k2u_cbk_invoke(k2u_cbk_hndl_t k2u_cbk_h, k2u_cbk_id_t cbk_id,\r
- void *data_p, MT_size_t size)\r
-{\r
- cbk_msg_t *msg_p;\r
- u_int32_t next_prod; /* next producer index */\r
- MT_ulong_ptr_t cur_pid = MOSAL_getpid();\r
- MT_ulong_ptr_t cur_tid = (MT_ulong_ptr_t)KeGetCurrentThread();\r
-\r
- if ((size > 0) && (data_p == NULL)) return MT_EINVAL;\r
-\r
- MOSAL_spinlock_dpc_lock(&cbk_dat_lock);\r
- \r
- if ( (k2u_cbk_h>=MAX_PROCS) ||\r
- (k2u_cbk_h==INVALID_K2U_CBK_HNDL) ||\r
- (cbk_db[k2u_cbk_h]==NULL) ) {\r
- MOSAL_spinlock_unlock(&cbk_dat_lock);\r
- MTL_ERROR4(MT_FLFMT("%s: Invalid handle (%d)"), __func__,\r
- k2u_cbk_h);\r
- return MT_EINVAL;\r
- }\r
-\r
- MTL_TRACE4(__FUNCTION__ ": called for cbk_hndl=%d cbk_id=%d data size=0x"SIZE_T_FMT".\n",\r
- k2u_cbk_h,cbk_id,size);\r
-\r
- /* for cleanup, check that current thread is in the same process group of the polling thread */\r
- if ((cbk_id == K2U_CBK_CLEANUP_CBK_ID) && (cbk_db[k2u_cbk_h]->pid != cur_pid)) {\r
- MTL_ERROR1(MT_FLFMT(\r
- "K2U_CBK_CLEANUP_CBK_ID is used by a thread (tid=" MT_ULONG_PTR_FMT ") which is in pid=" MT_ULONG_PTR_FMT " != " MT_ULONG_PTR_FMT " "\r
- " of the polling thread (tid=" MT_ULONG_PTR_FMT ")"),\r
- cur_tid,cur_pid,cbk_db[k2u_cbk_h]->pid,cbk_db[k2u_cbk_h]->tid);\r
- MOSAL_spinlock_unlock(&cbk_dat_lock);\r
- return MT_EPERM;\r
- } \r
-\r
- if (size > MAX_CBK_DATA_SZ) {\r
- MOSAL_spinlock_unlock(&cbk_dat_lock);\r
- MTL_ERROR4(__FUNCTION__ ": given data size ("SIZE_T_FMT") is more than allowed (%d).\n",\r
- size,MAX_CBK_DATA_SZ);\r
- return MT_EINVAL;\r
- }\r
- \r
- next_prod= (cbk_db[k2u_cbk_h]->prod+1) & MAX_OUTS_CALLS_MASK;\r
- if (next_prod == cbk_db[k2u_cbk_h]->cons) {\r
- MOSAL_spinlock_unlock(&cbk_dat_lock);\r
- MTL_ERROR4("%s: Call queue is full - invocation is dropped.\n", __func__);\r
- return MT_EAGAIN;\r
- }\r
- msg_p= cbk_db[k2u_cbk_h]->msg_q+cbk_db[k2u_cbk_h]->prod;\r
- msg_p->id= cbk_id;\r
- msg_p->data_p= data_p;\r
- msg_p->size= size;\r
- cbk_db[k2u_cbk_h]->prod= next_prod;\r
- MOSAL_sem_rel(&(cbk_db[k2u_cbk_h]->qsem)); /* signal for new message in queue */\r
- MTL_TRACE1(MT_FLFMT("%s: signaled process for a new event: event id=%d"), __func__, cbk_id);\r
- \r
- MOSAL_spinlock_unlock(&cbk_dat_lock);\r
- \r
- return MT_OK;\r
-}\r
\r
-EXPORTS\r
- ; for OS only\r
- DllInitialize private\r
- DllUnload private\r
- MOSAL_manual_wrapper\r
- ;\r
- ; mtl_common\r
- ;\r
- mtl_log_set\r
- mtl_log\r
- mtl_strerror\r
- mtl_strerror_sym\r
- ; windows implementation of tracing\r
- NT_trace\r
- NT_trace1\r
- NT_trace2\r
- NT_trace3\r
- NT_trace4\r
- NT_trace5\r
- NT_trace6\r
- NT_trace7\r
- NT_trace8\r
- NT_trace9\r
- NT_error\r
- NT_error1\r
- NT_error2\r
- NT_error3\r
- NT_error4\r
- NT_error5\r
- NT_error6\r
- NT_error7\r
- NT_error8\r
- NT_error9\r
- NT_debug\r
- NT_debug1\r
- NT_debug2\r
- NT_debug3\r
- NT_debug4\r
- NT_debug5\r
- NT_debug6\r
- NT_debug7\r
- NT_debug8\r
- NT_debug9\r
-\r
- ;\r
- ; MOSAL\r
- ;\r
-\r
- ; ----- Mosal_ntddk.c -----\r
- MOSAL_PCI_find_device\r
- MOSAL_PCI_read_config_byte\r
- MOSAL_PCI_read_config_word\r
- MOSAL_PCI_read_config_dword\r
- MOSAL_PCI_read_config_data\r
- MOSAL_PCI_write_config_byte\r
- MOSAL_PCI_write_config_word\r
- MOSAL_PCI_write_config_dword\r
- MOSAL_PCI_write_config_data\r
- ; ----- Mosal_bus.c -----\r
- MOSAL_PCI_find_class\r
- MOSAL_PCI_read_io_byte\r
- MOSAL_PCI_read_io_word\r
- MOSAL_PCI_read_io_dword\r
- MOSAL_PCI_write_io_byte\r
- MOSAL_PCI_write_io_word\r
- MOSAL_PCI_write_io_dword\r
- MOSAL_PCI_read_mem\r
- MOSAL_PCI_write_mem\r
- MOSAL_MPC860_write\r
- MOSAL_MPC860_read\r
- ; ----- Mosal_gen.c -----\r
- MOSAL_init\r
- MOSAL_cleanup\r
- MOSAL_is_privileged\r
- MOSAL_getpid\r
- MOSAL_setpid\r
- MOSAL_letobe64\r
- MOSAL_letobe32\r
- MOSAL_letobe16\r
- MOSAL_get_exec_ctx\r
- MOSAL_mark_time\r
- MOSAL_calc_diff\r
- MOSAL_set_counts_per_sec\r
- MOSAL_rsct_open\r
- MOSAL_rsct_close\r
- MOSAL_nsecs\r
- MOSAL_reset_card\r
- ; ----- Mosal_k2u_cbk.c -----\r
- k2u_cbk_init\r
- k2u_cbk_cleanup\r
- k2u_cbk_invoke\r
- k2u_cbk_pollq\r
- ; ----- Mosal_mem.c -----\r
- MOSAL_get_va_attr\r
- MOSAL_set_vmbuff_attr\r
- MOSAL_io_remap\r
- MOSAL_io_unmap\r
- MOSAL_map_phys_addr\r
- MOSAL_unmap_phys_addr\r
- MOSAL_virt_to_phys\r
- MOSAL_virt_to_phys\r
- MOSAL_write_phys_mem\r
- MOSAL_read_phys_mem\r
- MOSAL_vfree\r
- MOSAL_phys_ctg_get\r
- MOSAL_phys_ctg_free\r
- MOSAL_mem_alloc\r
- MOSAL_mem_free\r
- MOSAL_la_list_init\r
- MOSAL_la_list_alloc\r
- MOSAL_la_list_free\r
- MOSAL_la_list_delete\r
- MOSAL_get_page_shift\r
- ; ----- Mosal_mlock.c -----\r
- MOSAL_mlock\r
- MOSAL_munlock\r
- MOSAL_mlock_init\r
- ; ----- Mosal_que.c -----\r
- MOSAL_qcreate\r
- MOSAL_isqempty\r
- MOSAL_qget\r
- MOSAL_qput\r
- MOSAL_qdestroy\r
- ; ----- Mosal_sync.c -----\r
- MOSAL_syncobj_init\r
- MOSAL_syncobj_waiton\r
- MOSAL_syncobj_waiton_ui\r
- MOSAL_syncobj_signal\r
- MOSAL_syncobj_clear\r
- MOSAL_sem_init\r
- MOSAL_sem_acq\r
- MOSAL_sem_acq_ui\r
- MOSAL_sem_rel\r
- MOSAL_mutex_init\r
- MOSAL_mutex_acq\r
- MOSAL_mutex_acq_ui\r
- MOSAL_mutex_acq_to\r
- MOSAL_mutex_rel\r
- MOSAL_delay_execution\r
- MOSAL_spinlock_init\r
-; MOSAL_spinlock_lock\r
-; MOSAL_spinlock_irq_lock\r
-; MOSAL_spinlock_unlock\r
- MOSAL_usleep\r
- MOSAL_usleep_ui\r
- ; ----- Mosal_timer.c -----\r
- MOSAL_ISR_set\r
- MOSAL_ISR_unset\r
- MOSAL_set_intr_handler\r
- MOSAL_unset_intr_handler\r
- MOSAL_DPC_init\r
- MOSAL_DPC_schedule\r
- MOSAL_DPC_add_ctx\r
- MOSAL_DPC_schedule_ctx\r
- MOSAL_get_counts_per_sec\r
- MOSAL_time_get_clock\r
- MOSAL_get_cnt\r
- ; ----- Mosal_util.c -----\r
- MOSAL_add_device\r
- MOSAL_remove_device\r
- ; ----- Mosal_thread.c -----\r
- MOSAL_thread_start\r
- MOSAL_thread_kill\r
- MOSAL_thread_wait_for_exit\r
- MOSAL_thread_set_name\r
- ; ----- Mosal_wrap_kernel.c -----\r
- MOSAL_ioctl\r
- ; ----- mosal_iobuf.c -----\r
- MOSAL_iobuf_get_props\r
- MOSAL_iobuf_register\r
- MOSAL_iobuf_deregister\r
- MOSAL_iobuf_get_tpt\r
- MOSAL_iobuf_get_tpt_seg\r
- MOSAL_iobuf_cmp_tpt\r
- MOSAL_iobuf_iter_init\r
- MOSAL_iobuf_restore_perm\r
- ; ----- mosal_gen_nos.c -----\r
- MOSAL_PCI_get_cfg_hdr\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include <limits.h>\r
-#include "mosal_priv.h"\r
-\r
-/* hash using */\r
-#ifdef MT_64BIT\r
-\r
-/* 64-bit platform */\r
-#include <vip_hashv4p.h>\r
-#define hash_insert VIP_hashv4p_insert\r
-#define hash_erase VIP_hashv4p_erase\r
-#define hash_traverse VIP_hashv4p_traverse\r
-#define hash_create VIP_hashv4p_create\r
-#define hash_destroy VIP_hashv4p_destroy\r
-#define hash_p_t VIP_hashv4p_p_t\r
-#define hash_key_t VIP_hashv4p_key_t\r
-#define hash_value_t VIP_hashv4p_value_t\r
-\r
-#define HASH_INSERT(hash,sp,val,label) \\r
- { \\r
- u_int64_t key[2]; \\r
- key[0] = (u_int64_t)MOSAL_getpid(); \\r
- key[1] = *(u_int64_t*)(sp); \\r
- if (hash_insert( hash, (u_int32_t*)&key[0], val) != 0) \\r
- goto label; \\r
- }\r
-\r
-#define HASH_ERASE(hash,sp,val,label) \\r
- { \\r
- u_int64_t key[2]; \\r
- key[0] = (u_int64_t)MOSAL_getpid(); \\r
- key[1] = *(u_int64_t*)(sp); \\r
- if (hash_erase( hash, (u_int32_t*)&key[0], (void*)&(val)) != 0) \\r
- goto label; \\r
- }\r
-\r
-#else\r
-\r
-/* 32-bit platform */\r
-#include <vip_hash64p.h>\r
-#define hash_insert VIP_hash64p_insert\r
-#define hash_erase VIP_hash64p_erase\r
-#define hash_traverse VIP_hash64p_traverse\r
-#define hash_create VIP_hash64p_create\r
-#define hash_destroy VIP_hash64p_destroy\r
-#define hash_p_t VIP_hash64p_p_t\r
-#define hash_key_t VIP_hash64p_key_t\r
-#define hash_value_t VIP_hash64p_value_t\r
-\r
-#define HASH_INSERT(hash,sp,val,label) \\r
- { \\r
- ULARGE_INTEGER key; \\r
- key.HighPart = (LONG)MOSAL_getpid(); \\r
- key.LowPart = *(PULONG)(sp); \\r
- if (hash_insert( hash, *(u_int64_t*)&key, val) != 0) \\r
- goto label; \\r
- }\r
-\r
-#define HASH_ERASE(hash,sp,val,label) \\r
- { \\r
- ULARGE_INTEGER key; \\r
- key.HighPart = (LONG)MOSAL_getpid(); \\r
- key.LowPart = *(PULONG)(sp); \\r
- if (hash_erase( hash, *(u_int64_t*)&key, (void*)&(val)) != 0) \\r
- goto label; \\r
- }\r
-\r
-#endif\r
-\r
-#include "mosal_ntddk.h"\r
-\r
-\r
-/* prototypes from <ntddk.h> */\r
-NTKERNELAPI\r
-PVOID\r
-MmAllocateContiguousMemory (\r
- IN SIZE_T NumberOfBytes,\r
- IN PHYSICAL_ADDRESS HighestAcceptableAddress\r
- );\r
-\r
-NTKERNELAPI\r
-VOID\r
-MmFreeContiguousMemory (\r
- IN PVOID BaseAddress\r
- );\r
-\r
-static hash_p_t hash_tbl_mdl = NULL;\r
-static MOSAL_semaphore_t sem;\r
-\r
-\r
-/* \r
- *\r
- * resource tracking\r
- *\r
- */\r
-\r
-typedef enum { TYPE_IO_REMAP, TYPE_PHYS_CTG, TYPE_PHYS_ADDR , TYPE_PHYS_ADDR_DIR } mem_rmv_type_t;\r
-\r
-typedef struct {\r
- LIST_ENTRY link;\r
- mem_rmv_type_t type;\r
- MOSAL_pid_t pid;\r
- PMDL mdl_p;\r
- MT_phys_addr_t pa;\r
- MT_virt_addr_t va;\r
- } io_remap_el_t;\r
-\r
-typedef struct {\r
- LIST_ENTRY link;\r
- mem_rmv_type_t type;\r
- MOSAL_pid_t pid;\r
- PMDL mdl_p;\r
- MT_virt_addr_t va;\r
- } phys_ctg_el_t;\r
-\r
-typedef struct {\r
- LIST_ENTRY link;\r
- mem_rmv_type_t type;\r
- MOSAL_pid_t pid;\r
- PMDL mdl_p;\r
- MT_virt_addr_t va;\r
- MT_size_t bsize;\r
- } phys_addr_el_t;\r
-\r
-\r
-PVOID MOSAL_mem_rsct_open(MOSAL_pid_t pid)\r
-{\r
- /* allocate resource list */\r
- mem_rmv_t *rmv_p = (mem_rmv_t*)TMALLOC(mem_rmv_t);\r
- if (rmv_p == NULL) {\r
- MTL_ERROR4("MOSAL_mem_rsct_open: allocation failed \n");\r
- }\r
- else {\r
- /* fill resource list */\r
- rmv_p->pid = pid;\r
- InitializeListHead( &rmv_p->io_remap_que );\r
- InitializeListHead( &rmv_p->phys_ctg_que );\r
- InitializeListHead( &rmv_p->phys_addr_que );\r
- }\r
-\r
- return (PVOID)rmv_p;\r
-}\r
-\r
-static void remove_hash_els(\r
- mem_rmv_t *rmv_p\r
- )\r
-{\r
- MOSAL_pid_t pid = rmv_p->pid;\r
-\r
- /* remove io_remap requests */\r
- while (!IsListEmpty( &rmv_p->io_remap_que )) {\r
- io_remap_el_t *rmv_el_p = (io_remap_el_t*)RemoveHeadList( &rmv_p->io_remap_que );\r
- MOSAL_io_release_for_user(rmv_el_p->pa);\r
- }\r
- \r
- /* remove phys_ctg requests */\r
- while (!IsListEmpty( &rmv_p->phys_ctg_que )) {\r
- phys_ctg_el_t *rmv_el_p = (phys_ctg_el_t*)RemoveHeadList( &rmv_p->phys_ctg_que );\r
- MOSAL_phys_ctg_free_for_user(rmv_el_p->va);\r
- }\r
- \r
- /* remove phys_addr requests */\r
- while (!IsListEmpty( &rmv_p->phys_addr_que )) {\r
- phys_addr_el_t *rmv_el_p = (phys_addr_el_t*)RemoveHeadList( &rmv_p->phys_addr_que );\r
- MOSAL_unmap_phys_addr(MOSAL_PROT_CTX_CURRENT_USER, rmv_el_p->va, rmv_el_p->bsize);\r
- }\r
- \r
-}\r
-\r
-static int clean_hash_pcs(hash_key_t key, hash_value_t val, void* vp)\r
-{\r
- mem_rmv_t *rmv_p = (mem_rmv_t*)vp;\r
- io_remap_el_t * el_p_tmp = (io_remap_el_t *)val;\r
- MT_virt_addr_t system_range_start = (MT_virt_addr_t)(MT_WIN_SYSTEM_SPACE_START); /* MmSystemRangeStart */\r
- \r
- /* check for val to be a pointer in kernel space */\r
- if ( (MT_virt_addr_t)val < system_range_start)\r
- return MT_EAGAIN;\r
- \r
- if (el_p_tmp->pid == rmv_p->pid) {\r
- /* it's our process- let's build remove element */\r
- switch (el_p_tmp->type) {\r
- case TYPE_IO_REMAP:\r
- { \r
- io_remap_el_t * el_p = (io_remap_el_t *)val;\r
- InsertTailList( &rmv_p->io_remap_que, &el_p->link );\r
- }\r
- break;\r
- \r
- case TYPE_PHYS_CTG:\r
- { \r
- phys_ctg_el_t * el_p = (phys_ctg_el_t *)val;\r
- InsertTailList( &rmv_p->phys_ctg_que, &el_p->link );\r
- }\r
- break;\r
- \r
- case TYPE_PHYS_ADDR:\r
- case TYPE_PHYS_ADDR_DIR:\r
- { \r
- phys_addr_el_t * el_p = (phys_addr_el_t *)val;\r
- InsertTailList( &rmv_p->phys_addr_que, &el_p->link );\r
- }\r
- break;\r
- }\r
- }\r
- return MT_EAGAIN;\r
-}\r
-\r
-void MOSAL_mem_rsct_close(mem_rmv_t *rmv_p)\r
-{\r
- MOSAL_sem_acq( &sem, TRUE );\r
- hash_traverse( hash_tbl_mdl, clean_hash_pcs, (void*)rmv_p ); \r
- remove_hash_els( rmv_p );\r
- MOSAL_sem_rel( &sem );\r
- FREE(rmv_p);\r
-}\r
-\r
-\r
-\r
-/* \r
- *\r
- * init/cleanup\r
- *\r
- */\r
-\r
-call_result_t MOSAL_mem_init()\r
-{\r
- /* init MDL hash */\r
- if (hash_tbl_mdl == NULL) {\r
- if (hash_create( 0, &hash_tbl_mdl ) != 0) {\r
- MTL_ERROR2("MOSAL_mem_init: hash_create failed\n");\r
- return MT_ERROR;\r
- }\r
- }\r
- MOSAL_sem_init( &sem, 1 );\r
- return MT_OK;\r
-}\r
-\r
-void MOSAL_mem_cleanup()\r
-{\r
- if (hash_tbl_mdl != NULL) \r
- hash_destroy( hash_tbl_mdl, NULL, NULL );\r
- hash_tbl_mdl = NULL;\r
-}\r
-\r
-\r
-/* \r
- *\r
- * Functions for user space\r
- *\r
- */\r
-\r
-/*\r
- * MOSAL_io_remap_for_user\r
- */\r
-MT_virt_addr_t MOSAL_io_remap_for_user(MT_phys_addr_t pa, MT_size_t size)\r
-{\r
- PVOID kernel_p;\r
- PMDL mdl_p;\r
- PVOID user_p;\r
- PHYSICAL_ADDRESS wpa;\r
- io_remap_el_t *remap_el_p;\r
- MOSAL_pid_t pid = MOSAL_getpid();\r
-\r
- /* map physical address to a kernel virtual one */\r
- wpa.QuadPart = pa;\r
- kernel_p = MmMapIoSpace( wpa, size, MmNonCached ); \r
- if (kernel_p == NULL) goto err0;\r
- \r
- /* allocate MDL */\r
- mdl_p = IoAllocateMdl( kernel_p, (ULONG)size, FALSE,FALSE,NULL);\r
- if (mdl_p == NULL) goto err1;\r
- \r
- /* fill MDL */\r
- MmBuildMdlForNonPagedPool(mdl_p);\r
- \r
- /* map the buffer into user space */\r
- /* use NTDDK function */\r
- user_p = MmMapLockedPagesSpecifyCache( mdl_p, UserMode, \r
- MmNonCached, NULL, FALSE, NormalPagePriority );\r
- if (user_p == NULL) goto err2;\r
-\r
- /* allocate hash element */\r
- remap_el_p = (io_remap_el_t*)TMALLOC(io_remap_el_t);\r
- if (remap_el_p == NULL) {\r
- MTL_ERROR4("MOSAL_io_remap_for_user: allocation failed \n");\r
- goto err3;\r
- }\r
- \r
- /* fill hash element */\r
- remap_el_p->type = TYPE_IO_REMAP;\r
- remap_el_p->pid = pid;\r
- remap_el_p->mdl_p = mdl_p;\r
- remap_el_p->pa = pa;\r
- remap_el_p->va = (MT_virt_addr_t)user_p;\r
-\r
- /* store mdl for future release */\r
- HASH_INSERT(hash_tbl_mdl,&wpa,remap_el_p,err4);\r
- \r
- return (MT_virt_addr_t)user_p;\r
-\r
-err4:\r
- FREE(remap_el_p);\r
-err3:\r
- MmUnmapLockedPages((PVOID)user_p, mdl_p );\r
-err2:\r
- IoFreeMdl( mdl_p );\r
-err1:\r
- MmUnmapIoSpace( kernel_p, size ); \r
-err0: \r
- return (MT_virt_addr_t)0;\r
-}\r
-\r
-/*\r
- * MOSAL_io_release_for_user\r
- */\r
-void MOSAL_io_release_for_user(MT_phys_addr_t pa)\r
-{\r
- PMDL mdl_p;\r
- io_remap_el_t *remap_el_p = NULL;\r
- \r
- /* get saved mdl */\r
- HASH_ERASE(hash_tbl_mdl,&pa,remap_el_p,err1);\r
- if (remap_el_p == NULL) {\r
- MTL_ERROR4("MOSAL_io_release_for_user: internal error \n");\r
- goto err0;\r
- }\r
-\r
- /* release resources */\r
- mdl_p = remap_el_p->mdl_p;\r
- if (mdl_p != NULL) {\r
- PVOID kernel_p;\r
- ULONG size;\r
- \r
- /* unmap buffer from user space */\r
- MmUnmapLockedPages((PVOID)remap_el_p->va, mdl_p );\r
- \r
- /* unmap kernel memory */\r
- kernel_p = MmGetSystemAddressForMdlSafe( mdl_p, HighPagePriority );\r
- size = MmGetMdlByteCount( mdl_p);\r
- if (kernel_p != NULL)\r
- MmUnmapIoSpace( kernel_p, size ); \r
-\r
- /* free MDL */\r
- IoFreeMdl( mdl_p );\r
- }\r
- FREE(remap_el_p);\r
- return;\r
-err1: \r
- MTL_ERROR4("MOSAL_io_release_for_user: hash_erase failed \n");\r
-err0: \r
- return;\r
-}\r
-\r
-\r
-/*\r
- * Allocate physically contiguous memory\r
- * \r
- *\r
- */\r
-MT_virt_addr_t MOSAL_phys_ctg_get_for_user(MT_size_t size)\r
-{\r
- char * kernel_p;\r
- PMDL mdl_p;\r
- MT_virt_addr_t user_p;\r
- PHYSICAL_ADDRESS wpa;\r
- phys_ctg_el_t *phys_ctg_el_p;\r
- MOSAL_pid_t pid = MOSAL_getpid();\r
-\r
- /* map physical address to a kernel virtual one */\r
- wpa.QuadPart = _UI64_MAX;\r
- \r
- /* map physical address to a kernel virtual one */\r
- kernel_p = MmAllocateContiguousMemory( size, wpa );\r
- if (kernel_p == NULL) goto err0;\r
- \r
- /* allocate MDL */\r
- mdl_p = IoAllocateMdl( kernel_p, (ULONG)size, FALSE,FALSE,NULL);\r
- if (mdl_p == NULL) goto err1;\r
- \r
- /* fill MDL */\r
- MmBuildMdlForNonPagedPool(mdl_p);\r
- \r
- /* map the buffer into user space */\r
- /* use NTDDK function */\r
- user_p = (MT_virt_addr_t)MmMapLockedPagesSpecifyCache( mdl_p, \r
- UserMode, MmNonCached, NULL, FALSE, NormalPagePriority );\r
- if (user_p == (MT_virt_addr_t)0) goto err2;\r
-\r
- /* allocate hash element */\r
- phys_ctg_el_p = (phys_ctg_el_t*)TMALLOC(phys_ctg_el_t);\r
- if (phys_ctg_el_p == NULL) {\r
- MTL_ERROR4("MOSAL_phys_ctg_get_for_user: allocation failed \n");\r
- goto err3;\r
- }\r
- \r
- /* fill hash element */\r
- phys_ctg_el_p->type = TYPE_PHYS_CTG;\r
- phys_ctg_el_p->pid = pid;\r
- phys_ctg_el_p->mdl_p = mdl_p;\r
- phys_ctg_el_p->va = user_p;\r
-\r
-\r
- /* store mdl for future release */\r
- HASH_INSERT(hash_tbl_mdl,&user_p,phys_ctg_el_p,err4);\r
- \r
- return user_p;\r
-\r
-err4:\r
- FREE(phys_ctg_el_p);\r
-err3:\r
- MmUnmapLockedPages((PVOID)user_p, mdl_p );\r
-err2:\r
- IoFreeMdl( mdl_p );\r
-err1:\r
- MmFreeContiguousMemory( kernel_p ); \r
-err0: \r
- return (MT_virt_addr_t)0;\r
-}\r
-\r
-void MOSAL_phys_ctg_free_for_user(MT_virt_addr_t va)\r
-{\r
- phys_ctg_el_t *phys_ctg_el_p = NULL;\r
- PMDL mdl_p;\r
- \r
- /* find mdl */\r
- HASH_ERASE(hash_tbl_mdl,&va,phys_ctg_el_p,err0);\r
- if (phys_ctg_el_p == NULL) {\r
- MTL_ERROR4("MOSAL_phys_ctg_free_for_user: internal error \n");\r
- return;\r
- }\r
- \r
- /* release resources */\r
- mdl_p = phys_ctg_el_p->mdl_p;\r
- if (mdl_p != NULL) {\r
- PVOID kernel_p;\r
- \r
- /* unmap buffer from user space */\r
- MmUnmapLockedPages((PVOID)va, mdl_p );\r
- \r
- /* free contiguous memory */\r
- kernel_p = MmGetSystemAddressForMdlSafe( mdl_p, HighPagePriority );\r
- if (kernel_p != NULL)\r
- MmFreeContiguousMemory( kernel_p ); \r
-\r
- /* free MDL */\r
- IoFreeMdl( mdl_p );\r
- }\r
- FREE(phys_ctg_el_p);\r
-err0: \r
- return;\r
-}\r
-\r
-/* \r
- *\r
- * Functions for kernel space\r
- *\r
- */\r
- \r
-\r
-MT_virt_addr_t MOSAL_io_remap(MT_phys_addr_t pa, MT_size_t size)\r
-{\r
- char * buffer_p;\r
- PHYSICAL_ADDRESS wpa;\r
-\r
- /* map physical address to a kernel virtual one */\r
- wpa.QuadPart = pa;\r
- buffer_p = MmMapIoSpace( wpa, size, MmNonCached ); \r
-\r
- /* store size for future release */\r
- if (buffer_p == NULL)\r
- goto err0;\r
- \r
- HASH_INSERT(hash_tbl_mdl,&buffer_p,(void*)size,err1);\r
- \r
- return (MT_virt_addr_t)buffer_p;\r
- \r
-err1:\r
- MmUnmapIoSpace( buffer_p, size ); \r
-err0:\r
- return (MT_virt_addr_t)NULL;\r
-}\r
-\r
-void MOSAL_io_unmap(MT_virt_addr_t va)\r
-{\r
- MT_size_t size;\r
- HASH_ERASE(hash_tbl_mdl,&va,size,err);\r
- MmUnmapIoSpace( (void *)va, size ); \r
-err:\r
- return;\r
-}\r
-\r
-/*\r
- * MOSAL_vfree\r
- */\r
-void MOSAL_vfree(MT_virt_addr_t va)\r
-{\r
-#ifdef __KERNEL__\r
- VFREE((void *)va);\r
-#endif\r
-}\r
-\r
-MT_virt_addr_t MOSAL_map_phys_addr_via_kernel(MT_phys_addr_t pa, MT_size_t bsize,\r
- MOSAL_mem_flags_t flags, MOSAL_prot_ctx_t prot_ctx)\r
-{\r
- char * buffer_p;\r
- PHYSICAL_ADDRESS wpa;\r
- MEMORY_CACHING_TYPE mtype = (flags & MOSAL_MEM_FLAGS_NO_CACHE) ? MmNonCached : MmCached;\r
- PMDL mdl_p;\r
- PVOID user_p;\r
- LOCK_OPERATION Operation = IoReadAccess;\r
- phys_addr_el_t *phys_addr_el_p;\r
- MOSAL_pid_t pid = MOSAL_getpid();\r
-\r
- /* map physical address to a kernel virtual one */\r
- wpa.QuadPart = pa;\r
- buffer_p = MmMapIoSpace( wpa, bsize, mtype ); \r
- if (buffer_p == NULL)\r
- goto err0;\r
- \r
- if (prot_ctx == MOSAL_PROT_CTX_KERNEL) { /* Mapping to kernel virtual address */\r
- MTL_DEBUG2("MOSAL_map_phys_addr: Mapped phys.="PHYS_ADDR_FMT" to virt.=" VIRT_ADDR_FMT"\n",pa,buffer_p);\r
- return (MT_virt_addr_t)buffer_p; \r
- }\r
-\r
- /* else: MOSAL_PROT_CTX_CURRENT_USER */\r
-\r
- /* allocate MDL */\r
- mdl_p = IoAllocateMdl( buffer_p, (ULONG)bsize, FALSE,TRUE,NULL);\r
- if (mdl_p == NULL) goto err1;\r
- \r
- /* fill MDL */\r
- MmBuildMdlForNonPagedPool(mdl_p);\r
-\r
- /* lock pages and set acess flags */\r
-#ifdef LOCK_PHYS_PAGES \r
- if ((flags & MOSAL_MEM_FLAGS_PERM_READ)) \r
- Operation = IoReadAccess;\r
- if ((flags & MOSAL_MEM_FLAGS_PERM_WRITE)) \r
- Operation = IoWriteAccess; \r
- /* The probing fails, seems to be, because it probes physical memory */\r
- MmProbeAndLockPages( mdl_p, UserMode, Operation ); \r
-#endif \r
- \r
- /* map the buffer into user space */\r
- /* use NTDDK function */\r
- user_p = MmMapLockedPagesSpecifyCache( mdl_p, UserMode, mtype, NULL, FALSE, NormalPagePriority );\r
- if (user_p == NULL) goto err2;\r
-\r
- /* allocate hash element */\r
- phys_addr_el_p = (phys_addr_el_t*)TMALLOC(phys_addr_el_t);\r
- if (phys_addr_el_p == NULL) {\r
- MTL_ERROR4("MOSAL_map_phys_addr: allocation failed \n");\r
- goto err3;\r
- }\r
- \r
- /* fill hash element */\r
- phys_addr_el_p->type = TYPE_PHYS_ADDR;\r
- phys_addr_el_p->pid = pid;\r
- phys_addr_el_p->mdl_p = mdl_p;\r
- phys_addr_el_p->va = (MT_virt_addr_t)user_p;\r
- phys_addr_el_p->bsize = bsize;\r
-\r
- /* store mdl for future release */\r
- HASH_INSERT(hash_tbl_mdl,&user_p,phys_addr_el_p,err4);\r
- \r
- MTL_DEBUG2("MOSAL_map_phys_addr: Mapped phys.="PHYS_ADDR_FMT" to virt.=" VIRT_ADDR_FMT"\n",pa,user_p);\r
- \r
- return (MT_virt_addr_t)user_p;\r
-\r
-err4:\r
- FREE(phys_addr_el_p);\r
-err3:\r
- MmUnmapLockedPages((PVOID)user_p, mdl_p );\r
-err2:\r
- IoFreeMdl( mdl_p );\r
-err1:\r
- MmUnmapIoSpace( buffer_p, bsize ); \r
-err0: \r
- return (MT_virt_addr_t)0;\r
-\r
-}\r
-\r
-MT_virt_addr_t MOSAL_map_phys_addr_directly(MT_phys_addr_t pa, MT_size_t bsize,\r
- MOSAL_mem_flags_t flags, MOSAL_prot_ctx_t prot_ctx)\r
-{\r
- PHYSICAL_MEMORY_INFO info;\r
- NTSTATUS ntStatus;\r
- MOSAL_dev_t *dev_p;\r
- MT_virt_addr_t user_p;\r
- phys_addr_el_t *phys_addr_el_p;\r
- MOSAL_pid_t pid = MOSAL_getpid();\r
-\r
- /* for KERNEL - do it in the previous style */\r
- if (prot_ctx == MOSAL_PROT_CTX_KERNEL) { /* Mapping to kernel virtual address */\r
- return MOSAL_map_phys_addr_via_kernel(pa, bsize, flags, prot_ctx);\r
- }\r
- \r
- /* if can't find the device - do it in the previous style */\r
- dev_p = find_device_by_phys_addr( pa, bsize );\r
- if (dev_p == NULL)\r
- return MOSAL_map_phys_addr_via_kernel(pa, bsize, flags, prot_ctx);\r
-\r
- /* fill the parameters */\r
- info.InterfaceType = PCIBus;\r
- info.BusNumber = (ULONG)dev_p->bus;\r
- info.BusAddress.QuadPart = pa;\r
- info.AddressSpace = 0;\r
- info.Length = (ULONG)bsize;\r
-\r
- /* map it now: if failed - do it in the previous style */\r
- ntStatus = MapMemMapTheMemory( NULL, &info, sizeof(info), sizeof(PVOID) );\r
- if (!NT_SUCCESS(ntStatus))\r
- return MOSAL_map_phys_addr_via_kernel(pa, bsize, flags, prot_ctx);\r
- else\r
- user_p = *(MT_virt_addr_t *)&info;\r
-\r
- /* allocate hash element */\r
- phys_addr_el_p = (phys_addr_el_t*)TMALLOC(phys_addr_el_t);\r
- if (phys_addr_el_p == NULL) {\r
- MTL_ERROR4("MOSAL_map_phys_addr: allocation failed \n");\r
- goto err0;\r
- }\r
- \r
- /* fill hash element */\r
- phys_addr_el_p->type = TYPE_PHYS_ADDR_DIR;\r
- phys_addr_el_p->pid = pid;\r
- phys_addr_el_p->mdl_p = NULL;\r
- phys_addr_el_p->va = user_p;\r
- phys_addr_el_p->bsize = bsize;\r
-\r
- /* store mdl for future release */\r
- HASH_INSERT(hash_tbl_mdl,&user_p,phys_addr_el_p,err1);\r
- MTL_DEBUG4("MOSAL_map_phys_addr_directly: Mapped phys.="PHYS_ADDR_FMT" for task 0x%x to virt.=" VIRT_ADDR_FMT"\n",\r
- pa,(LONG)MOSAL_getpid(), user_p);\r
-\r
- return user_p;\r
- \r
-err1:\r
- MTL_ERROR2("MOSAL_map_phys_addr: HASH_INSERT failed for task 0x%x, va 0x%x\n", \r
- (LONG)MOSAL_getpid(), (ULONG)user_p);\r
- FREE(phys_addr_el_p);\r
-err0:\r
- ntStatus = MapMemUnmapTheMemory( NULL, (PVOID)&user_p, sizeof(MT_virt_addr_t), 0);\r
- if (ntStatus) {\r
- MTL_ERROR2("MOSAL_map_phys_addr_directly: unwinding after error: MapMemUnmapTheMemory failed (0x%x)\n",ntStatus);\r
- }\r
- return (MT_virt_addr_t)0;\r
-}\r
-\r
-MT_virt_addr_t MOSAL_map_phys_addr(MT_phys_addr_t pa, MT_size_t bsize,\r
- MOSAL_mem_flags_t flags, MOSAL_prot_ctx_t prot_ctx)\r
-{\r
- #ifdef MAP_PHYS_ADDR_VIA_KERNEL\r
- return MOSAL_map_phys_addr_via_kernel(pa, bsize, flags, prot_ctx);\r
- #else\r
- return MOSAL_map_phys_addr_directly(pa, bsize, flags, prot_ctx);\r
- #endif\r
-}\r
-\r
-call_result_t MOSAL_unmap_phys_addr(MOSAL_prot_ctx_t prot_ctx, MT_virt_addr_t virt, \r
- MT_size_t bsize)\r
-{\r
- NTSTATUS ntStatus;\r
- if (prot_ctx == MOSAL_PROT_CTX_KERNEL) { /* Mapping to kernel virtual address */\r
- MmUnmapIoSpace( (PVOID)virt, bsize ); \r
- } \r
- else {\r
- PMDL mdl_p;\r
- phys_addr_el_t *phys_addr_el_p = NULL;\r
- void * kvirt;\r
- \r
- /* find MDL */\r
- HASH_ERASE(hash_tbl_mdl,&virt,phys_addr_el_p,err0);\r
- if (phys_addr_el_p == NULL) {\r
- MTL_ERROR4("MOSAL_unmap_phys_addr: internal error \n");\r
- goto err0;\r
- }\r
-\r
- #ifndef MAP_PHYS_ADDR_VIA_KERNEL\r
- if (phys_addr_el_p->type == TYPE_PHYS_ADDR_DIR) {\r
- FREE(phys_addr_el_p); /* free book keeping info */\r
- ntStatus = MapMemUnmapTheMemory( NULL, (PVOID)&virt, sizeof(MT_virt_addr_t), 0);\r
- if (ntStatus) {\r
- MTL_ERROR2("MOSAL_unmap_phys_addr_directly: MapMemUnmapTheMemory failed for task 0x%x, virt 0x%x (0x%x)\n",\r
- (LONG)MOSAL_getpid(), (ULONG)virt, ntStatus);\r
- }\r
- #if 0\r
- else {\r
- MTL_DEBUG4("MOSAL_unmap_phys_addr: unmapping done for task 0x%x, va 0x%x\n", \r
- (LONG)MOSAL_getpid(), (ULONG)virt);\r
- }\r
- #endif\r
- return ntStatus;\r
- }\r
- #endif \r
- \r
- mdl_p = phys_addr_el_p->mdl_p;\r
- \r
- /* release resources */\r
-\r
- /* unmap buffer from user space */\r
- MmUnmapLockedPages((PVOID)virt, mdl_p );\r
- \r
- /* unlock pages */\r
-#ifdef LOCK_PHYS_PAGES \r
- MmUnlockPages(mdl_p);\r
-#endif \r
-\r
- /* unmap kernel memory */\r
- kvirt = MmGetMdlVirtualAddress(mdl_p);\r
- MmUnmapIoSpace( kvirt, bsize ); \r
-\r
- /* free MDL */\r
- IoFreeMdl( mdl_p );\r
-\r
- /* free book keeping info */\r
- FREE(phys_addr_el_p);\r
- }\r
- \r
- return MT_OK;\r
-err0:\r
- MTL_ERROR2("MOSAL_unmap_phys_addr: HASH_ERASE failed for task 0x%x, va 0x%x\n", \r
- (LONG)MOSAL_getpid(), (ULONG)virt);\r
- return MT_ERROR;\r
- \r
-}\r
-\r
-/*\r
- * Allocate physically contiguous memory\r
- * \r
- *\r
- */\r
-MT_virt_addr_t MOSAL_phys_ctg_get(MT_size_t size)\r
-{\r
- MT_virt_addr_t buffer_p;\r
- PHYSICAL_ADDRESS wpa;\r
- \r
- /* map physical address to a kernel virtual one */\r
- wpa.QuadPart = _UI64_MAX;\r
-\r
- /* map physical address to a kernel virtual one */\r
- buffer_p = (MT_virt_addr_t)MmAllocateContiguousMemory( size, wpa );\r
- \r
- /* reset memory */\r
- memset((void *)buffer_p, 0xda, size);\r
-\r
- return buffer_p; \r
-}\r
-\r
-call_result_t MOSAL_phys_ctg_free(MT_virt_addr_t va, MT_size_t size)\r
-{\r
- MmFreeContiguousMemory((void*)va);\r
- return MT_OK;\r
-}\r
-\r
-\r
-call_result_t MOSAL_get_va_attr(MT_virt_addr_t va, mem_attr_t *attr)\r
-{\r
- return(MT_ENOSYS);\r
-}\r
-\r
-call_result_t MOSAL_set_vmbuff_attr(MT_virt_addr_t va, u_int32_t size, \r
-mem_attr_t attr)\r
-{\r
- return(MT_ENOSYS);\r
-}\r
-\r
-#if 1\r
-\r
-// non-WDM implementation \r
-\r
-NTKERNELAPI\r
-PHYSICAL_ADDRESS\r
-MmGetPhysicalAddress (\r
- IN PVOID BaseAddress\r
- );\r
-\r
-NTKERNELAPI\r
-PVOID\r
-MmGetVirtualForPhysical (\r
- IN PHYSICAL_ADDRESS PhysicalAddress\r
- );\r
-\r
-\r
-MT_virt_addr_t MOSAL_phys_to_virt(const MT_phys_addr_t pa)\r
-{\r
- PHYSICAL_ADDRESS wpa;\r
-\r
- wpa.QuadPart = pa;\r
- return (MT_virt_addr_t)MmGetVirtualForPhysical(wpa);\r
-}\r
-\r
-call_result_t MOSAL_virt_to_phys(MOSAL_prot_ctx_t prot_ctx,\r
- const MT_virt_addr_t va, MT_phys_addr_t *pa_p)\r
-{\r
- PHYSICAL_ADDRESS wpa = MmGetPhysicalAddress((void*)(MT_ulong_ptr_t)va);\r
- *pa_p = (MT_phys_addr_t)wpa.QuadPart;\r
- if (!*pa_p)\r
- return MT_ENORSC;\r
- return MT_OK;\r
-}\r
-\r
-/*\r
- * write by physical address\r
- *\r
- * TBD: Add check for top of physical memory\r
- */\r
-u_int32_t MOSAL_write_phys_mem(MT_phys_addr_t pa, u_int32_t val)\r
-{\r
- MT_virt_addr_t va = (MT_virt_addr_t)(MOSAL_phys_to_virt(pa));\r
- MOSAL_MMAP_IO_WRITE_DWORD( (PULONG)va, val );\r
- return val; \r
-}\r
-\r
-/*\r
- * read by physical address\r
- *\r
- * TBD: Add check for top of physical memory\r
- */\r
-u_int32_t MOSAL_read_phys_mem(MT_phys_addr_t pa)\r
-{\r
- return MOSAL_MMAP_IO_READ_DWORD((PULONG)MOSAL_phys_to_virt(pa));\r
-}\r
-\r
-\r
-#else\r
-\r
-// WDM implementation: \r
-// 1) works only on PASSIVE LEVEL\r
-// 2) very inefficient: performs map/unmap on every read/write\r
-\r
-u_int32_t MOSAL_write_phys_mem(MT_phys_addr_t pa, u_int32_t val)\r
-{\r
- if(KeGetCurrentIrql() == PASSIVE_LEVEL)\r
- {\r
- MT_virt_addr_t va = MOSAL_io_remap(pa, sizeof(u_int32_t));\r
- *(u_int32_t*)va = val;\r
- MmUnmapIoSpace((void*)va, sizeof(u_int32_t));\r
- return val; \r
- }\r
- else \r
- return(0);\r
-}\r
-\r
-u_int32_t MOSAL_read_phys_mem(MT_phys_addr_t pa)\r
-{\r
- if(KeGetCurrentIrql() == PASSIVE_LEVEL)\r
- {\r
- MT_virt_addr_t va = MOSAL_io_remap(pa, sizeof(u_int32_t));\r
- u_int32_t val = *(u_int32_t*)va;\r
- MmUnmapIoSpace((void*)va, sizeof(u_int32_t));\r
- return val; \r
- }\r
- else \r
- return(0);\r
-}\r
-#endif\r
- \r
-/******************************************************************************\r
- * Function:\r
- * MOSAL_mem_alloc\r
- *\r
- * Description:\r
- * allocate kernel memory\r
- *\r
- * Parameters: \r
- * size(IN) MT_size_t\r
- * Size of memory to allocate\r
- * flags(IN) u_int32_t\r
- * Flags\r
- * in LINUX - flags like GFP_KERNEL, GFP_ATOMIC; in NT - Pool Tag or 0 (\r
-without tag)\r
- *\r
- * Returns:\r
- * MT_virt_addr_t\r
- *\r
- \r
-******************************************************************************/\r
-MT_virt_addr_t MOSAL_mem_alloc( MT_size_t size, u_int32_t flags )\r
-{ \r
- if (flags)\r
- return (MT_virt_addr_t)ExAllocatePoolWithTag(NonPagedPool,size,flags);\r
- else\r
- return (MT_virt_addr_t)ExAllocatePoolWithTag(NonPagedPool,size,'amOM');\r
-}\r
-\r
-/******************************************************************************\r
- * Function:\r
- * MOSAL_mem_free\r
- *\r
- * Description:\r
- * release kernel memory\r
- *\r
- * Parameters: \r
- * addr(IN) MT_virt_addr_t\r
- *\r
- * Returns:\r
- *\r
- \r
-******************************************************************************/\r
-void MOSAL_mem_free( MT_virt_addr_t addr )\r
-{\r
- ExFreePool((void *)addr);\r
-}\r
-\r
-/* PAGE_SIZE API */\r
-call_result_t MOSAL_get_page_shift( \r
- MOSAL_prot_ctx_t prot_ctx, \r
- MT_virt_addr_t va, \r
- unsigned int *page_shift_p\r
-)\r
-{\r
- *page_shift_p = MOSAL_SYS_PAGE_SHIFT;\r
- return MT_OK;\r
-}\r
-\r
-\r
-/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * \r
- * \r
- * Look-aside List Management for non-paged memory\r
- *\r
- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */\r
-\r
-/******************************************************************************\r
- * Function:\r
- * MOSAL_la_list_init\r
- *\r
- * Description:\r
- * initializes a lookaside list for nonpaged entries of the specified size\r
- *\r
- * Parameters: \r
- * Lookaside(IN) PNPAGED_LOOKASIDE_LIST\r
- * Pointer to the caller-supplied memory for the lookaside list head to be \r
-initialized\r
- * Allocate(IN) PALLOCATE_FUNCTION\r
- * Either points to a caller-supplied routine for allocating an entry when \r
-the lookaside list is empty, or this parameter can be NULL\r
- * Free(IN) PFREE_FUNCTION\r
- * Either points to a caller-supplied routine for freeing an entry whenever \r
-the lookaside list is full, or this parameter can be NULL\r
- * Flags(IN) ULONG\r
- * Reserved. Must be zero\r
- * Size(IN) SIZE_T\r
- * Specifies the size in bytes for each nonpaged entry to be allocated \r
-subsequently \r
- * Tag(IN) ULONG\r
- * Specifies the pool tag for lookaside list entries\r
- * Depth(IN) USHORT \r
- * Reserved. Must be zero\r
- *\r
- * Returns:\r
- *\r
- \r
-******************************************************************************/\r
-void MOSAL_la_list_init(\r
- PNPAGED_LOOKASIDE_LIST Lookaside,\r
- PALLOCATE_FUNCTION Allocate OPTIONAL,\r
- PFREE_FUNCTION Free OPTIONAL,\r
- ULONG Flags,\r
- SIZE_T Size,\r
- ULONG Tag,\r
- USHORT Depth\r
- )\r
-{\r
- ExInitializeNPagedLookasideList( Lookaside, Allocate, Free, Flags, Size, Tag\r
-, Depth );\r
-}\r
-\r
-/******************************************************************************\r
- * Function:\r
- * MOSAL_la_list_alloc\r
- *\r
- * Description:\r
- * returns a pointer to a nonpaged entry from the given lookaside list, \r
- * or it returns a pointer to a newly allocated nonpaged entry\r
- *\r
- * Parameters: \r
- * Lookaside(IN) PNPAGED_LOOKASIDE_LIST\r
- * pointer to the list head\r
- *\r
- * Returns:\r
- * void*\r
- * a pointer to an entry if one can be allocated. Otherwise, it returns NULL.\r
- *\r
- \r
-******************************************************************************/\r
-void *MOSAL_la_list_alloc( PNPAGED_LOOKASIDE_LIST Lookaside )\r
-{\r
- return ExAllocateFromNPagedLookasideList(Lookaside);\r
-}\r
-\r
-/******************************************************************************\r
- * Function:\r
- * MOSAL_la_list_free\r
- *\r
- * Description:\r
- * returns an entry to the pool\r
- *\r
- * Parameters: \r
- * Lookaside(IN) PNPAGED_LOOKASIDE_LIST\r
- * pointer to the list head\r
- * Entry(IN) PVOID\r
- * Entry to be returned\r
- *\r
- * Returns:\r
- *\r
- \r
-******************************************************************************/\r
-void MOSAL_la_list_free( PNPAGED_LOOKASIDE_LIST Lookaside, PVOID Entry )\r
-{\r
- ExFreeToNPagedLookasideList(Lookaside, Entry);\r
-}\r
-\r
-/******************************************************************************\r
- * Function:\r
- * MOSAL_la_list_delete\r
- *\r
- * Description:\r
- * deletes the list\r
- *\r
- * Parameters: \r
- * Lookaside(IN) PNPAGED_LOOKASIDE_LIST\r
- * pointer to the list head\r
- *\r
- * Returns:\r
- *\r
- \r
-******************************************************************************/\r
-void MOSAL_la_list_delete( PNPAGED_LOOKASIDE_LIST Lookaside )\r
-{ \r
- ExDeleteNPagedLookasideList(Lookaside);\r
-}\r
-\r
-\r
-\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#ifndef H_MOSAL_MEM_IMP_H\r
-#define H_MOSAL_MEM_IMP_H\r
-\r
-/* PAGE_SIZE API */\r
-#ifdef MT_KERNEL\r
-#define MOSAL_SYS_PAGE_SHIFT PAGE_SHIFT\r
-#define MOSAL_SYS_PAGE_SIZE (1 << MOSAL_SYS_PAGE_SHIFT)\r
-\r
-#else\r
-u_int32_t MOSAL_get_sys_page_size(MT_virt_addr_t va); \r
-u_int32_t MOSAL_get_sys_page_shift(MT_virt_addr_t va); \r
-\r
-#define MOSAL_SYS_PAGE_SIZE MOSAL_get_sys_page_size(0)\r
-#define MOSAL_SYS_PAGE_SHIFT MOSAL_get_sys_page_shift(0)\r
-#endif\r
-\r
-/* #define __MOSAL_MMAP_IO_WRITE_QWORD_ATOMIC__ */\r
-//static __inline void MOSAL_io_write_qword(u_int64_t data, volatile u_int64_t *target_p)\r
-//{\r
-// #ifdef MT_KERNEL\r
-// WRITE_REGISTER_BUFFER_ULONG((PULONG)target_p,(PULONG)&data,2); \r
-// #else\r
-// *target_p = data;\r
-// #endif\r
-//}\r
-\r
-static __inline u_int64_t MOSAL_io_read_qword(volatile u_int64_t *source_p)\r
-{\r
- #ifdef MT_KERNEL\r
- u_int64_t x;\r
- READ_REGISTER_BUFFER_ULONG((PULONG)&x,(PULONG)source_p,2);\r
- return x;\r
- #else\r
- return *source_p;\r
- #endif\r
-}\r
-\r
-static __inline void MOSAL_io_write_dword(volatile u_int32_t *target_p, u_int32_t data)\r
-{\r
- #ifdef MT_KERNEL\r
- WRITE_REGISTER_ULONG((PULONG)(target_p),(ULONG)(data));\r
- #else\r
- *target_p = data;\r
- #endif\r
-}\r
-\r
-static __inline u_int32_t MOSAL_io_read_dword(volatile u_int32_t *target_p)\r
-{\r
- #ifdef MT_KERNEL\r
- return READ_REGISTER_ULONG((PULONG)(target_p));\r
- #else\r
- return *target_p;\r
- #endif\r
-}\r
-\r
-/* access to memory-mapped physical memory */ \r
-#ifdef MT_KERNEL\r
-#define MOSAL_MMAP_IO_READ_BYTE(reg) READ_REGISTER_UCHAR((PUCHAR)(reg))\r
-#define MOSAL_MMAP_IO_READ_WORD(reg) READ_REGISTER_USHORT((PUSHORT)(reg))\r
-#define MOSAL_MMAP_IO_READ_DWORD(reg) READ_REGISTER_ULONG((PULONG)(reg)) /* MOSAL_io_read_dword(reg) // */\r
-#define MOSAL_MMAP_IO_READ_QWORD(reg,buf) READ_REGISTER_BUFFER_ULONG((PULONG)(reg),(PULONG)(buf),2)\r
-#define MOSAL_MMAP_IO_READ_BUF_BYTE(reg,buf,size) READ_REGISTER_BUFFER_UCHAR((PUCHAR)(reg),(PUCHAR)(buf),size) \r
-#define MOSAL_MMAP_IO_READ_BUF_WORD(reg,buf,size) READ_REGISTER_BUFFER_USHORT((PUSHORT)(reg),(PUSHORT)(buf),size) \r
-#define MOSAL_MMAP_IO_READ_BUF_DWORD(reg,buf,size) READ_REGISTER_BUFFER_ULONG((PULONG)(reg),(PULONG)(buf),size) \r
-#define MOSAL_MMAP_IO_WRITE_BYTE(reg,data) WRITE_REGISTER_UCHAR((PUCHAR)(reg),(UCHAR)(data))\r
-#define MOSAL_MMAP_IO_WRITE_WORD(reg,data) WRITE_REGISTER_USHORT((PUSHORT)(reg),(USHORT)(data))\r
-//#define MOSAL_MMAP_IO_WRITE_DWORD(reg,data) MOSAL_io_write_dword((volatile u_int32_t *)(reg),(u_int32_t)(data)) //WRITE_REGISTER_ULONG((PULONG)(reg),(ULONG)(data))\r
-#define MOSAL_MMAP_IO_WRITE_DWORD(reg,data) WRITE_REGISTER_ULONG((PULONG)(reg),(ULONG)(data))\r
-#define MOSAL_MMAP_IO_WRITE_QWORD(reg,data) WRITE_REGISTER_BUFFER_ULONG((PULONG)(reg),(PULONG)&(data),2);\r
- //{ \\r
- // volatile u_int64_t l_int64 = data; \\r
- // WRITE_REGISTER_BUFFER_ULONG((PULONG)(reg),(PULONG)&l_int64,2); \\r
- //}\r
-#define MOSAL_MMAP_IO_WRITE_BUF_BYTE(reg,buf,size) WRITE_REGISTER_BUFFER_UCHAR((PUCHAR)(reg),(PUCHAR)(buf),size)\r
-#define MOSAL_MMAP_IO_WRITE_BUF_WORD(reg,buf,size) WRITE_REGISTER_BUFFER_USHORT((PUSHORT)(reg),(PUSHORT)(buf),size)\r
-#define MOSAL_MMAP_IO_WRITE_BUF_DWORD(reg,buf,size) WRITE_REGISTER_BUFFER_ULONG((PULONG)(reg),(PULONG)(buf),size)\r
-#else\r
-#define MOSAL_MMAP_IO_READ_BYTE(reg) (*(volatile u_int8_t * const)(reg))\r
-#define MOSAL_MMAP_IO_READ_WORD(reg) (*(volatile u_int16_t * const)(reg))\r
-#define MOSAL_MMAP_IO_READ_DWORD(reg) (*(volatile u_int32_t * const)(reg))\r
-#define MOSAL_MMAP_IO_READ_QWORD(reg) MOSAL_io_read_qword((volatile u_int64_t*)(reg))\r
-/*\r
-#define MOSAL_MMAP_IO_READ_QWORD(reg,buf) \\r
- *(u_int32_t*)(buf) = *(u_int32_t *)(reg); *((u_int32_t*)(buf)+1) = *((u_int32_t *)(reg)+1)\r
-*/\r
-#define MOSAL_MMAP_IO_READ_BUF_BYTE(reg,buf,size) memcpy((volatile void*)(buf),(volatile void*)(reg),size)\r
-#define MOSAL_MMAP_IO_READ_BUF_WORD(reg,buf,size) memcpy((volatile void*)(buf),(volatile void*)(reg),(size)<<1)\r
-#define MOSAL_MMAP_IO_READ_BUF_DWORD(reg,buf,size) memcpy((volatile void*)(buf),(volatile void*)(reg),(size)<<2)\r
-#define MOSAL_MMAP_IO_WRITE_BYTE(reg,data) *(volatile u_int8_t* const)(reg) = data\r
-#define MOSAL_MMAP_IO_WRITE_WORD(reg,data) *(volatile u_int16_t* const)(reg) = data\r
-#define MOSAL_MMAP_IO_WRITE_DWORD(reg,data) *(volatile u_int32_t* const)(reg) = data\r
-#define MOSAL_MMAP_IO_WRITE_QWORD(reg,data) *(volatile u_int64_t* const)(reg) = data\r
-/*\r
-#define MOSAL_MMAP_IO_WRITE_QWORD(reg,buf) \\r
- *(u_int32_t*)(reg) = *(u_int32_t *)(buf); *((u_int32_t*)(reg)+1) = *((u_int32_t *)(buf)+1)\r
-*/ \r
-#define MOSAL_MMAP_IO_WRITE_BUF_BYTE(reg,buf,size) memcpy((volatile void*)(reg),(volatile void*)(buf),size)\r
-#define MOSAL_MMAP_IO_WRITE_BUF_WORD(reg,buf,size) memcpy((volatile void*)(reg),(volatile void*)(buf),(size)<<1)\r
-#define MOSAL_MMAP_IO_WRITE_BUF_DWORD(reg,buf,size) memcpy((volatile void*)(reg),(volatile void*)(buf),(size)<<2)\r
-\r
-\r
-#ifndef PAGE_SIZE\r
-#define PAGE_SIZE MOSAL_get_sys_page_size( 0 )\r
-#endif\r
-\r
-\r
-#endif\r
-\r
-\r
-/******************************************************************************\r
- * MOSAL_pci_virt_alloc_consistent\r
- *\r
- * Description:\r
- * allocate virtually contigous consistent memory (coherent)\r
- *\r
- * Parameters: \r
- * size(IN) the required allocation size in bytes\r
- * alignment (IN) the required alignment in bytes\r
- *\r
- * Returns: virtual address of allocated area\r
- * 0 if failed\r
- *\r
- ******************************************************************************/\r
-/* void *MOSAL_pci_virt_alloc_consistent(MT_size_t size, u_int8_t alignment); */\r
-#ifdef CONFIG_NOT_COHERENT_CACHE\r
- /* none coherent cache */\r
- #ifdef MT_KERNEL\r
- #define MOSAL_pci_virt_alloc_consistent(size, alignment) VMALLOC((size))\r
- #else\r
- /* no support in user level */\r
- #endif\r
-#else \r
- #define MOSAL_pci_virt_alloc_consistent(size, alignment) VMALLOC((size))\r
-#endif \r
-\r
-\r
-/******************************************************************************\r
- * MOSAL_pci_virt_free_consistent\r
- *\r
- * Description:\r
- * de-allocate virtually contigous consistent memory (coherent)\r
- *\r
- * Parameters: \r
- * vaddr(IN) address of freed allocation\r
- * size(IN) size of area to be freed in bytes\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-/*void MOSAL_pci_virt_free_consistent(void *vaddr, MT_size_t size);*/\r
-#ifdef CONFIG_NOT_COHERENT_CACHE\r
- /* none coherent cache */\r
- #ifdef MT_KERNEL\r
- #define MOSAL_pci_virt_free_consistent(vaddr, size) VFREE((vaddr))\r
- #else\r
- /* no support in user level */\r
- #endif\r
-#else \r
- #define MOSAL_pci_virt_free_consistent(vaddr, size) VFREE((vaddr))\r
-#endif \r
-\r
-\r
-/******************************************************************************\r
- * MOSAL_pci_phys_alloc_consistent\r
- *\r
- * Description:\r
- * allocate physically contigous consistent memory (coherent)\r
- *\r
- * Parameters: \r
- * size(IN) the required allocation size in bytes\r
- * alignment(IN) the required alignment in bytes\r
- *\r
- * Returns: virtual address of allocated area\r
- * 0 if failed\r
- *\r
- ******************************************************************************/\r
-/* void *MOSAL_pci_phys_alloc_consistent(MT_size_t size, u_int8_t alignment); */\r
-#ifdef MT_KERNEL\r
- #define MOSAL_pci_phys_alloc_consistent(size,alignment) ((void*)(MT_ulong_ptr_t)MOSAL_phys_ctg_get(size))\r
-\r
-#else\r
- /* no support in user level */\r
-#endif\r
-\r
-\r
-/******************************************************************************\r
- * MOSAL_pci_phys_free_consistent\r
- *\r
- * Description:\r
- * de-allocate physically contigous consistent memory (coherent)\r
- *\r
- * Parameters: \r
- * vaddr(IN) address of freed allocation\r
- * size(IN) size of area to be freed in bytes\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-/*void MOSAL_pci_phys_free_consistent(void *vaddr, MT_size_t size);*/\r
-#ifdef MT_KERNEL\r
- #define MOSAL_pci_phys_free_consistent(vaddr, size) \\r
- MOSAL_phys_ctg_free((MT_virt_addr_t)(MT_ulong_ptr_t)(vaddr), size)\r
-#else\r
- /* no support in user level */\r
-#endif\r
-\r
-\r
-#endif /* H_MOSAL_MEM_IMP_H */\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_MEM_PRIV_H\r
-#define H_MOSAL_MEM_PRIV_H\r
-\r
-\r
-/******************************************************************************\r
- *\r
- * Function: MOSAL_io_remap_for_user\r
- *\r
- * Description: Map a physical contiguous buffer to virtual address.\r
- *\r
- * Parameters: \r
- * pa (IN) MT_phys_addr_t\r
- * Physical address.\r
- * size (IN) MT_size_t\r
- * Size of memory buffer in bytes\r
- * \r
- *\r
- * Returns: On success returns pointer to new virtual memory buffer else\r
- * returns zero.\r
- *\r
- * Notes: The returned address will be page alligned. In case 'size' is not \r
- * page alligned the amount of allocated memory can be bigger than the \r
- * requested.\r
- *\r
- ******************************************************************************/\r
-MT_virt_addr_t MOSAL_io_remap_for_user(MT_phys_addr_t pa, MT_size_t size); \r
-\r
-/******************************************************************************\r
- *\r
- * Function: MOSAL_io_release_for_user\r
- *\r
- * Description: Unmap a physical contiguous buffer to virtual address.\r
- *\r
- * Parameters: \r
- * pa (IN) MT_phys_addr_t\r
- * Physical address.\r
- *\r
- * Returns: \r
- *\r
- ******************************************************************************/\r
-void MOSAL_io_release_for_user(MT_phys_addr_t pa); \r
-\r
-/******************************************************************************\r
- *\r
- * Function: MOSAL_phys_ctg_get_for_user\r
- *\r
- * Description: allocate a physically contiguous pinned memory region. \r
- *\r
- * Parameters: \r
- * size (IN) \r
- * size of physically contiguous memory to be allocate.\r
- * \r
- * Returns: virtual address of memory or NULL if failed. \r
- *\r
- ******************************************************************************/\r
-MT_virt_addr_t MOSAL_phys_ctg_get_for_user(MT_size_t size);\r
-\r
-\r
-/******************************************************************************\r
- *\r
- * Function: MOSAL_phys_ctg_free_for_user\r
- *\r
- * Description: release a physically contiguous pinned memory region. \r
- *\r
- * Parameters: \r
- * addr (IN) \r
- * address of physically contiguous memory to be released.\r
- * \r
- * Returns: virtual address of memory or NULL if failed. \r
- *\r
- ******************************************************************************/\r
-void MOSAL_phys_ctg_free_for_user(MT_virt_addr_t addr);\r
-\r
-#ifdef __KERNEL__\r
-\r
-/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\r
- * \r
- * Look-aside List Management for non-paged memory\r
- *\r
- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_la_list_init\r
- *\r
- * Description:\r
- * initializes a lookaside list for nonpaged entries of the specified size\r
- *\r
- * Parameters: \r
- * Lookaside(IN) PNPAGED_LOOKASIDE_LIST\r
- * Pointer to the caller-supplied memory for the lookaside list head to be initialized\r
- * Allocate(IN) PALLOCATE_FUNCTION\r
- * Either points to a caller-supplied routine for allocating an entry when the lookaside list is empty, or this parameter can be NULL\r
- * Free(IN) PFREE_FUNCTION\r
- * Either points to a caller-supplied routine for freeing an entry whenever the lookaside list is full, or this parameter can be NULL\r
- * Flags(IN) ULONG\r
- * Reserved. Must be zero\r
- * Size(IN) SIZE_T\r
- * Specifies the size in bytes for each nonpaged entry to be allocated subsequently \r
- * Tag(IN) ULONG\r
- * Specifies the pool tag for lookaside list entries\r
- * Depth(IN) USHORT \r
- * Reserved. Must be zero\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-void MOSAL_la_list_init(\r
- PNPAGED_LOOKASIDE_LIST Lookaside,\r
- PALLOCATE_FUNCTION Allocate, \r
- PFREE_FUNCTION Free,\r
- ULONG Flags,\r
- SIZE_T Size,\r
- ULONG Tag,\r
- USHORT Depth\r
- );\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_la_list_alloc\r
- *\r
- * Description:\r
- * returns a pointer to a nonpaged entry from the given lookaside list, \r
- * or it returns a pointer to a newly allocated nonpaged entry\r
- *\r
- * Parameters: \r
- * Lookaside(IN) PNPAGED_LOOKASIDE_LIST\r
- * pointer to the list head\r
- *\r
- * Returns:\r
- * void*\r
- * a pointer to an entry if one can be allocated. Otherwise, it returns NULL.\r
- *\r
- ******************************************************************************/\r
-void *MOSAL_la_list_alloc( PNPAGED_LOOKASIDE_LIST Lookaside );\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_la_list_free\r
- *\r
- * Description:\r
- * returns an entry to the pool\r
- *\r
- * Parameters: \r
- * Lookaside(IN) PNPAGED_LOOKASIDE_LIST\r
- * pointer to the list head\r
- * Entry(IN) PVOID\r
- * Entry to be returned\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-void MOSAL_la_list_free( PNPAGED_LOOKASIDE_LIST Lookaside, PVOID Entry );\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_la_list_delete\r
- *\r
- * Description:\r
- * deletes the list\r
- *\r
- * Parameters: \r
- * Lookaside(IN) PNPAGED_LOOKASIDE_LIST\r
- * pointer to the list head\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-void MOSAL_la_list_delete( PNPAGED_LOOKASIDE_LIST Lookaside );\r
-\r
-typedef struct {\r
- MOSAL_pid_t pid;\r
- LIST_ENTRY io_remap_que;\r
- LIST_ENTRY phys_ctg_que;\r
- LIST_ENTRY phys_addr_que;\r
-} mem_rmv_t;\r
-\r
-\r
-PVOID MOSAL_mem_rsct_open(MOSAL_pid_t pid);\r
-void MOSAL_mem_rsct_close(mem_rmv_t *rmv_p);\r
-\r
-\r
-#endif /* __KERNEL__ */\r
-\r
-#endif /* H_MOSAL_MEM_PRIV_H */\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "mosal_priv.h"\r
-\r
-/* hash using */\r
-#include <vip_hash64p.h>\r
-#ifdef MT_64BIT\r
-\r
-/* 64-bit platform */\r
-#include <vip_hashv4p.h>\r
-#define hash_insert VIP_hashv4p_insert\r
-#define hash_erase VIP_hashv4p_erase\r
-#define hash_create VIP_hashv4p_create\r
-#define hash_destroy VIP_hashv4p_destroy\r
-#define hash_find VIP_hashv4p_find\r
-#define hash_p_t VIP_hashv4p_p_t\r
-#define HASH_KEY_DEFINE(key) u_int64_t key[2]\r
-#define HASH_KEY_BUILD(key,a,s) key[0] = (u_int64_t)(a); key[1] = (u_int64_t)(s)\r
-#define HASH_KEY_VALUE(key) (u_int32_t*)(key)\r
-#define HASH_KEY_ASSIGN(dest, src) memcpy( dest, src, sizeof(VIP_hashv4p_key_t) )\r
-#else\r
-\r
-/* 32-bit platform */\r
-#define hash_insert VIP_hash64p_insert\r
-#define hash_erase VIP_hash64p_erase\r
-#define hash_create VIP_hash64p_create\r
-#define hash_destroy VIP_hash64p_destroy\r
-#define hash_find VIP_hash64p_find\r
-#define hash_p_t VIP_hash64p_p_t\r
-#define HASH_KEY_DEFINE(key) ULARGE_INTEGER key\r
-#define HASH_KEY_BUILD(key,a,s) key.HighPart = (LONG)(a); key.LowPart = (ULONG)(s)\r
-#define HASH_KEY_VALUE(key) *(u_int64_t*)&(key)\r
-#define HASH_KEY_ASSIGN(dest, src) dest = src\r
-#endif\r
-\r
-\r
-static VIP_hash64p_p_t hash_pcs = NULL;\r
-static MOSAL_semaphore_t sem;\r
-static LIST_ENTRY pcs_que;\r
-\r
-/* process element in the hash_pcs */\r
-typedef struct {\r
- LIST_ENTRY link; /* link for pcs_que */\r
- LIST_ENTRY que; /* que for the same addr/size request elements */\r
- hash_p_t hash_req_p;\r
- ULONG cnt;\r
- MOSAL_pid_t pid;\r
-} mlock_hash_t;\r
-\r
-/* element, containing list mlock requests with the same addr/size (sits in the process' hash) */\r
-typedef struct {\r
- LIST_ENTRY link; /* link for mlock_hash_t.que */\r
- LIST_ENTRY que; /* que for mlock requests */\r
- ULONG cnt;\r
- HASH_KEY_DEFINE(key);\r
-} mlock_req_que_t;\r
-\r
-/* element for an mlock requst */\r
-typedef struct {\r
- LIST_ENTRY link; /* link for mlock_req_que_t.que */\r
- PMDL mdl_p;\r
- void *h_secure; /* handle returned by MmSecureVirtualMemory */\r
-\r
-} mlock_req_t;\r
-\r
-/* The problem of the MOSAL_mlock() function is that it can be called \r
-SEVERAL times with the SAME parameters from the SAME or \r
-DIFFERENT processes.\r
-The implementation is as follows:\r
- 1. On mlock_init() a HASH for processes - hash_pcs - is created.\r
- 2. For every process its own HASH64 - hash_req - is created and \r
- the pointer to it is put into hash_pcs;\r
- 3. On every mlock request we do the following:\r
- - find process descriptor in hash_pcs; if not found - create;\r
- - find mlock request queue structure - req_que - in hash_req; \r
- if not found - allocate and put it into hash_req. This \r
- structure is inserted by addr-size key;\r
- - allocate mlock request structure - req - and chain it to req_que;\r
- - increment que depth counter;\r
- 4. On every munlock request:\r
- - find process hash;\r
- - find req_que element by addr-size key;\r
- - erase the last element in the queue;\r
- - decrement the que depth counter;\r
-*/\r
-call_result_t MOSAL_mlock(MT_virt_addr_t addr, MT_size_t size)\r
-{\r
- PMDL mdl_p;\r
- HASH_KEY_DEFINE(key);\r
- MT_virt_addr_t system_range_start = (MT_virt_addr_t)(MT_WIN_SYSTEM_SPACE_START); /* MmSystemRangeStart */\r
- MOSAL_pid_t pid = MOSAL_getpid();\r
- hash_p_t hash_req_p = NULL;\r
- mlock_req_que_t * req_que_p = NULL;\r
- mlock_req_t * req_p = NULL;\r
- BOOLEAN hash_created = FALSE;\r
- BOOLEAN hash_inserted = FALSE;\r
- BOOLEAN req_inserted = FALSE;\r
- mlock_hash_t * hash_p = NULL; \r
- int is_kernel_memory = (addr >= system_range_start);\r
-\r
- MOSAL_sem_acq( &sem, TRUE );\r
- \r
- /* on first request from process - create its hash_pcs */\r
- if (VIP_hash64p_find( hash_pcs, (u_int64_t)pid, &hash_p) != 0) \r
- { /* hash not found - create new */\r
- \r
- /* create hash */\r
- if (hash_create( 0, &hash_req_p ) != 0) {\r
- MTL_ERROR4("MOSAL_mlock: hash_create failed\n");\r
- goto err_exit;\r
- }\r
- hash_created = TRUE;\r
-\r
- /* allocate hash element */\r
- hash_p = (mlock_hash_t*)MALLOC(sizeof(mlock_hash_t));\r
- if (hash_p == NULL) {\r
- MTL_ERROR4("MOSAL_mlock: MALLOC0 failed\n");\r
- goto err0;\r
- }\r
-\r
- /* fill hash element */\r
- hash_p->pid = pid;\r
- hash_p->cnt = 0;\r
- hash_p->hash_req_p = hash_req_p;\r
- InitializeListHead( &hash_p->que );\r
- \r
- /* insert hash */\r
- if (VIP_hash64p_insert( hash_pcs, (u_int64_t)pid, hash_p) != 0) {\r
- MTL_ERROR4("MOSAL_mlock: VIP_hashp_insert failed\n");\r
- goto err1;\r
- }\r
- hash_inserted = TRUE;\r
- \r
- } /* hash not found - create new */\r
- else\r
- hash_req_p = hash_p->hash_req_p;\r
-\r
- /* allocate request element */\r
- req_p = (mlock_req_t*)MALLOC(sizeof(mlock_req_t));\r
- if (req_p == NULL) {\r
- MTL_ERROR4("MOSAL_mlock: MALLOC1 failed\n");\r
- goto err2;\r
- }\r
- \r
- /* make key */\r
- HASH_KEY_BUILD(key,addr,size);\r
-\r
- /* on first request with this key create request element */\r
- if (hash_find( hash_req_p, HASH_KEY_VALUE(key), &req_que_p) != 0) \r
- { /* mlock element not found - let's create it */\r
-\r
- /* allocate request element */\r
- req_que_p = (mlock_req_que_t*)MALLOC(sizeof(mlock_req_que_t));\r
- if (req_que_p == NULL) { \r
- MTL_ERROR4("MOSAL_mlock: MALLOC2 failed\n");\r
- goto err3;\r
- }\r
-\r
- /* init it */\r
- req_que_p->cnt = 0;\r
- InitializeListHead( &req_que_p->que );\r
-\r
- /* insert in hash */\r
- if (hash_insert( hash_req_p, HASH_KEY_VALUE(key), req_que_p) != 0) {\r
- MTL_ERROR4("MOSAL_mlock: hash_insert failed\n");\r
- goto err4;\r
- }\r
- req_inserted = TRUE;\r
- \r
- } /* mlock element not found - let's create it */\r
- \r
- /* allocate MDL */\r
- mdl_p = IoAllocateMdl( (PVOID)addr, (ULONG)size, FALSE,TRUE,NULL);\r
- if (mdl_p == NULL) {\r
- MTL_ERROR4("MOSAL_mlock: IoAllocateMdl failed\n");\r
- goto err5;\r
- }\r
-\r
- /* Now we have all stuff to do the task:\r
- mdl_p - pointer to MDL, locking the memory;\r
- req_p - pointer to mlock request element, keeping 'mdl_p';\r
- req_que_p - pointer to queue header, containing all mlock requests \r
- with the same addr/size pair;\r
- hash_p - pointer to hash_pcs element, owning all queue headers;\r
- */\r
- \r
- /* fill MDL */\r
- if (is_kernel_memory)\r
- MmBuildMdlForNonPagedPool(mdl_p);\r
-\r
- __try\r
- { /* try */\r
- \r
- /* lock memory */\r
- MmProbeAndLockPages( mdl_p, \r
- (is_kernel_memory) ? KernelMode : UserMode, \r
- IoWriteAccess ); \r
- \r
- } /* try */\r
- \r
- __except (EXCEPTION_EXECUTE_HANDLER)\r
- {\r
- NTSTATUS Status = GetExceptionCode();\r
- MTL_ERROR4("MOSAL_mlock: Exception 0x%x on MmProbeAndLockPages(), addr 0x%p, size %d\n", Status, addr, size);\r
- goto err6;\r
- }\r
-\r
- __try\r
- {\r
- req_p->h_secure =\r
- MmSecureVirtualMemory( (PVOID)addr, (SIZE_T)size, PAGE_READWRITE );\r
- }\r
- __except( EXCEPTION_EXECUTE_HANDLER )\r
- {\r
- goto err7;\r
- }\r
- \r
- /* store MDL */\r
- req_p->mdl_p = mdl_p;\r
- InsertTailList( &req_que_p->que, &req_p->link );\r
- req_que_p->cnt++;\r
- HASH_KEY_ASSIGN(req_que_p->key, key);\r
- hash_p->cnt++;\r
-\r
- /* link new elements */\r
- if (hash_inserted)\r
- InsertTailList( &pcs_que, &hash_p->link );\r
- if (req_inserted)\r
- InsertTailList( &hash_p->que, &req_que_p->link );\r
- \r
- MOSAL_sem_rel( &sem );\r
- return MT_OK;\r
-\r
-err7:\r
- MmUnlockPages(mdl_p);\r
-err6:\r
- IoFreeMdl(mdl_p);\r
-err5:\r
- if (req_inserted && hash_req_p != NULL) \r
- hash_erase( hash_req_p, HASH_KEY_VALUE(key), &req_que_p);\r
-err4:\r
- if (req_que_p != NULL)\r
- FREE(req_que_p);\r
-err3:\r
- if (req_p != NULL)\r
- FREE(req_p);\r
-err2:\r
- if (hash_inserted && hash_pcs != NULL) \r
- VIP_hash64p_erase( hash_pcs, (u_int64_t)pid, &hash_p);\r
-err1:\r
- if (hash_p != NULL)\r
- FREE(hash_p);\r
-err0:\r
- if (hash_created && hash_req_p != NULL) \r
- hash_destroy( hash_req_p, NULL, NULL);\r
-err_exit:\r
- MOSAL_sem_rel( &sem );\r
- return MT_ERROR;\r
-}\r
-\r
-call_result_t MOSAL_munlock(MT_virt_addr_t addr, MT_size_t size)\r
-{\r
- MOSAL_pid_t pid = MOSAL_getpid();\r
- mlock_hash_t * hash_p = NULL; \r
- mlock_hash_t * hash_tst_p = NULL; \r
- hash_p_t hash_req_p;\r
- mlock_req_que_t * req_que_p = NULL;\r
- mlock_req_que_t * req_que_tst_p = NULL;\r
- HASH_KEY_DEFINE(key);\r
- mlock_req_t* req_p;\r
- PMDL mdl_p;\r
-\r
- /* protect from mlock */\r
- MOSAL_sem_acq( &sem, TRUE );\r
- \r
- if (VIP_hash64p_find( hash_pcs, (u_int64_t)pid, &hash_p) != 0) {\r
- MOSAL_sem_rel( &sem );\r
- MTL_ERROR4("MOSAL_munlock: Not found info for that pid (0x%x) \n", pid);\r
- return MT_ERROR;\r
- }\r
-\r
- /* make key */ \r
- HASH_KEY_BUILD(key,addr,size);\r
-\r
- /* get que element */\r
- hash_req_p = hash_p->hash_req_p;\r
- if (hash_find( hash_req_p, HASH_KEY_VALUE(key), &req_que_p) != 0) {\r
- MTL_ERROR4("MOSAL_munlock: no que element for that pid (0x%x) \n", hash_p->pid);\r
- return MT_ERROR;\r
- }\r
-\r
- /* get mlock request element and MDL */\r
- if (IsListEmpty( &req_que_p->que )) {\r
- MTL_ERROR4("MOSAL_munlock: no req elements for that pid (0x%x) \n", hash_p->pid);\r
- return MT_ERROR;\r
- }\r
- req_p = (mlock_req_t*)RemoveTailList( &req_que_p->que );\r
- mdl_p = req_p->mdl_p;\r
-\r
- /* Now we have all the stuff to do the task:\r
- mdl_p - pointer to MDL, locking the memory;\r
- req_p - pointer to mlock request element, keeping 'mdl_p';\r
- req_que_p - pointer to queue header, containing all mlock requests \r
- with the same addr/size pair;\r
- hash_p - pointer to hash_pcs element, owning all queue headers;\r
- */\r
-\r
- /* unlock pages */ \r
- if (mdl_p) {\r
- MmUnlockPages(mdl_p);\r
- IoFreeMdl(mdl_p);\r
- }\r
-\r
- MmUnsecureVirtualMemory( req_p->h_secure );\r
- \r
- /* \r
- * remove bookkeeping info \r
- */\r
-\r
- /* (1) remove mlock request element */\r
- FREE(req_p);\r
-\r
- /* (2) when no pending requests, release queue element */\r
- if (--req_que_p->cnt == 0) {\r
- if (hash_erase( hash_req_p, HASH_KEY_VALUE(key), &req_que_tst_p) != 0) {\r
- MTL_ERROR4("MOSAL_munlock_pid: hash_erase failed \n");\r
- }\r
- else \r
- ASSERT(req_que_tst_p == req_que_p);\r
- RemoveEntryList(&req_que_p->link);\r
- FREE(req_que_p);\r
- }\r
-\r
- /* (3) when no pending queues, release hash element */\r
- if (--hash_p->cnt == 0) {\r
- if (VIP_hash64p_erase( hash_pcs, (u_int64_t)hash_p->pid, &hash_tst_p) != 0) {\r
- MTL_ERROR4("MOSAL_munlock_pid: hash_erase failed \n");\r
- }\r
- else\r
- ASSERT(hash_tst_p == hash_p);\r
- hash_destroy( hash_req_p, NULL, NULL);\r
- RemoveEntryList(&hash_p->link);\r
- FREE(hash_p);\r
- }\r
-\r
- MOSAL_sem_rel( &sem );\r
- return MT_OK;\r
-}\r
-\r
-static void cleanup_req(mlock_hash_t * hash_p, mlock_req_que_t * req_que_p)\r
-{\r
- mlock_req_t * req_p = NULL;\r
- mlock_req_que_t * req_que_tst_p = NULL;\r
- hash_p_t hash_req_p = hash_p->hash_req_p;\r
- \r
- /* remove all requests of this request queue */ \r
- while (!IsListEmpty( &req_que_p->que )) {\r
- req_p = (mlock_req_t*)RemoveTailList( &req_que_p->que );\r
- if (req_p->mdl_p) { /* unlock pages */\r
- MmUnsecureVirtualMemory( req_p->h_secure );\r
- MmUnlockPages(req_p->mdl_p);\r
- IoFreeMdl(req_p->mdl_p);\r
- }\r
- FREE(req_p);\r
- }\r
- \r
- /* remove request que element */ \r
- if (hash_erase( hash_req_p, HASH_KEY_VALUE(req_que_p->key), &req_que_tst_p) != 0) {\r
- MTL_ERROR4("cleanup_req: hash_erase failed \n");\r
- }\r
- else \r
- ASSERT(req_que_tst_p == req_que_p);\r
- RemoveEntryList(&req_que_p->link);\r
- FREE(req_que_p);\r
-}\r
-\r
-static void cleanup_pcs_stuff(mlock_hash_t * hash_p)\r
-{\r
- mlock_req_que_t * req_que_p = NULL;\r
- mlock_hash_t * hash_tst_p;\r
- /* remove all requests queues of this process */ \r
- while (!IsListEmpty( &hash_p->que )) {\r
- req_que_p = (mlock_req_que_t*)RemoveTailList( &hash_p->que );\r
- cleanup_req(hash_p, req_que_p);\r
- }\r
- \r
- /* remove process element */ \r
- if (VIP_hash64p_erase( hash_pcs, (u_int64_t)hash_p->pid, &hash_tst_p) != 0) {\r
- MTL_ERROR4("cleanup_pcs_stuff: hash_erase failed \n");\r
- }\r
- else\r
- ASSERT(hash_tst_p == hash_p);\r
- hash_destroy( hash_p->hash_req_p, NULL, NULL);\r
- RemoveEntryList(&hash_p->link);\r
- FREE(hash_p);\r
-}\r
-\r
-void MOSAL_mlock_cleanup_pcs(MOSAL_pid_t pid)\r
-{\r
- mlock_hash_t * hash_p; \r
- PLIST_ENTRY link_p;\r
- MT_bool found = FALSE;\r
- \r
- MOSAL_sem_acq( &sem, TRUE );\r
- if (hash_pcs != NULL) {\r
- for ( link_p = pcs_que.Flink; link_p != &pcs_que; link_p = link_p->Flink ) {\r
- hash_p = (mlock_hash_t*)CONTAINING_RECORD(link_p, mlock_hash_t, link);\r
- if (hash_p->pid == pid) {\r
- found = TRUE;\r
- break;\r
- }\r
- }\r
- if (found == TRUE)\r
- cleanup_pcs_stuff(hash_p);\r
- }\r
- MOSAL_sem_rel( &sem );\r
-}\r
-\r
-void MOSAL_mlock_cleanup(void)\r
-{\r
- mlock_hash_t * hash_p; \r
- \r
- MOSAL_sem_acq( &sem, TRUE );\r
- if (hash_pcs != NULL) {\r
- while (!IsListEmpty( &pcs_que )) {\r
- hash_p = (mlock_hash_t*)RemoveTailList( &pcs_que );\r
- cleanup_pcs_stuff(hash_p);\r
- }\r
- VIP_hash64p_destroy( hash_pcs, NULL, NULL );\r
- hash_pcs = NULL;\r
- }\r
- MOSAL_sem_rel( &sem );\r
-}\r
-\r
-call_result_t MOSAL_mlock_init(void)\r
-{\r
- hash_pcs = NULL;\r
- if (VIP_hash64p_create( 0, &hash_pcs ) != 0) {\r
- MTL_ERROR4("MOSAL_mlock_init: hash_create failed\n");\r
- return MT_ERROR;\r
- }\r
- MOSAL_sem_init( &sem, 1 );\r
- InitializeListHead( &pcs_que );\r
- return(MT_OK);\r
-}\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_MLOCK_PRIV_H\r
-#define H_MOSAL_MLOCK_PRIV_H\r
-\r
-/********************************************************************************\r
- * Function: \r
- * MOSAL_mlock_init\r
- *\r
- * Arguments:\r
- * void\r
- * Returns:\r
- * MT_OK, \r
- * appropriate error code otherwise\r
- *\r
- * Description:\r
- * Initializes data structures needed for MOSAL_mlock/MOSAL_munlock functions\r
- *\r
- ********************************************************************************/\r
-call_result_t MOSAL_mlock_init(void);\r
-\r
-\r
-/********************************************************************************\r
- * Function: \r
- * MOSAL_mlock_cleanup\r
- *\r
- * Arguments:\r
- * void\r
- * Returns:\r
- * void\r
- * Description:\r
- * Cleans data structures needed for MOSAL_mlock/MOSAL_munlock functions\r
- *\r
- ********************************************************************************/\r
-void MOSAL_mlock_cleanup(void);\r
-\r
-void MOSAL_mlock_cleanup_pcs(MOSAL_pid_t pid);\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "mtl_types.h"\r
-#include "mosal_ntddk.h"\r
-#include <stdarg.h>\r
-\r
-// leo\r
-#define DONT_TRANSLATE_BUS_ADDRESS 1\r
-\r
-/*\r
- * PCI\r
- * ---\r
- */\r
-call_result_t MOSAL_PCI_find_device(u_int16_t vendor_id,\r
- u_int16_t dev_id,\r
- u_int16_t index,\r
- u_int8_t * bus_p,\r
- u_int8_t * dev_func_p)\r
-{\r
-#define N_BUSES 8\r
-#define N_SLOTS 32\r
- ULONG l_Bus;\r
- ULONG l_Slot;\r
- ULONG l_DevId;\r
- ULONG l_Bytes;\r
- ULONG OurDevId = ((ULONG)dev_id << 16) | (ULONG)vendor_id;\r
- ULONG l_Function = 0; /* don't know how to find it */\r
- int cnt = 0;\r
-\r
- for (l_Bus = 0; l_Bus < N_BUSES; l_Bus++ ) {\r
- for (l_Slot = 0; l_Slot < N_SLOTS; l_Slot++ ) {\r
- l_Bytes = HalGetBusDataByOffset(\r
- PCIConfiguration,\r
- l_Bus,\r
- l_Slot,\r
- (PVOID)&l_DevId,\r
- 0,\r
- sizeof(ULONG)\r
- );\r
- if (l_Bytes != sizeof(ULONG)) \r
- continue; /* as if - "not found" */\r
- if (l_DevId == OurDevId) {\r
- if (index == cnt)\r
- goto found;\r
- else\r
- cnt++;\r
- }\r
- }\r
- }\r
-\r
-found: \r
- if (l_DevId == OurDevId && (index == cnt)) {\r
- *bus_p = (u_int8_t)l_Bus;\r
- *dev_func_p = (u_int8_t)((l_Slot<<3) | l_Function);\r
- return MT_OK;\r
- }\r
- else\r
- return MT_ENORSC;\r
-}\r
-\r
-call_result_t MOSAL_PCI_read_config_byte(u_int8_t bus, u_int8_t dev_func,\r
- u_int8_t offset, u_int8_t* data_p)\r
-{\r
- ULONG l_Bytes;\r
- l_Bytes = HalGetBusDataByOffset(\r
- PCIConfiguration,\r
- bus,\r
- dev_func>>3,\r
- (PVOID)data_p,\r
- offset,\r
- sizeof(u_int8_t)\r
- );\r
- if (l_Bytes != sizeof(u_int8_t)) \r
- return MT_ENORSC;\r
- return MT_OK;\r
-}\r
-\r
-call_result_t MOSAL_PCI_read_config_word(u_int8_t bus, u_int8_t dev_func,\r
- u_int8_t offset, u_int16_t* data_p)\r
-{\r
- ULONG l_Bytes;\r
- l_Bytes = HalGetBusDataByOffset(\r
- PCIConfiguration,\r
- bus,\r
- dev_func>>3,\r
- (PVOID)data_p,\r
- offset,\r
- sizeof(u_int16_t)\r
- );\r
- if (l_Bytes != sizeof(u_int16_t)) \r
- return MT_ENORSC;\r
- return MT_OK;\r
-}\r
-\r
-\r
-call_result_t MOSAL_PCI_read_config_dword(u_int8_t bus,\r
- u_int8_t dev_func,\r
- u_int8_t offset,\r
- u_int32_t* data_p)\r
-{\r
- ULONG l_Bytes;\r
- l_Bytes = HalGetBusDataByOffset(\r
- PCIConfiguration,\r
- bus,\r
- dev_func>>3,\r
- (PVOID)data_p,\r
- offset,\r
- sizeof(ULONG)\r
- );\r
- if (l_Bytes != sizeof(ULONG)) \r
- return MT_ENORSC;\r
- return MT_OK;\r
-}\r
-\r
-call_result_t MOSAL_PCI_read_config_data(u_int8_t bus,\r
- u_int8_t dev_func,\r
- u_int8_t offset,\r
- u_int32_t length,\r
- u_int8_t* data_p\r
- )\r
-{\r
- ULONG l_Bytes;\r
- l_Bytes = HalGetBusDataByOffset(\r
- PCIConfiguration,\r
- bus,\r
- dev_func>>3,\r
- (PVOID)data_p,\r
- offset,\r
- length\r
- );\r
- if (l_Bytes != length) \r
- return MT_ENORSC;\r
- return MT_OK;\r
- }\r
-\r
-\r
-call_result_t MOSAL_PCI_write_config_byte(u_int8_t bus, u_int8_t dev_func,\r
- u_int8_t offset, u_int8_t data)\r
-{\r
- ULONG l_Bytes;\r
- l_Bytes = HalSetBusDataByOffset(\r
- PCIConfiguration,\r
- bus,\r
- dev_func>>3,\r
- (PVOID)&data,\r
- offset,\r
- sizeof(u_int8_t)\r
- );\r
- if (l_Bytes != sizeof(u_int8_t)) \r
- return MT_ENORSC;\r
- return MT_OK;\r
-}\r
-\r
-call_result_t MOSAL_PCI_write_config_word(u_int8_t bus, u_int8_t dev_func,\r
- u_int8_t offset, u_int16_t data)\r
-{\r
- ULONG l_Bytes;\r
- l_Bytes = HalSetBusDataByOffset(\r
- PCIConfiguration,\r
- bus,\r
- dev_func>>3,\r
- (PVOID)&data,\r
- offset,\r
- sizeof(u_int16_t)\r
- );\r
- if (l_Bytes != sizeof(u_int16_t)) \r
- return MT_ENORSC;\r
- return MT_OK;\r
-}\r
-\r
-\r
-\r
-call_result_t MOSAL_PCI_write_config_dword(u_int8_t bus,\r
- u_int8_t dev_func,\r
- u_int8_t offset,\r
- u_int32_t data)\r
-{\r
- ULONG l_Bytes;\r
- l_Bytes = HalSetBusDataByOffset(\r
- PCIConfiguration,\r
- bus,\r
- dev_func>>3,\r
- (PVOID)&data,\r
- offset,\r
- sizeof(ULONG)\r
- );\r
- if (l_Bytes != sizeof(ULONG)) \r
- return MT_ENORSC;\r
- return MT_OK;\r
-}\r
-\r
-call_result_t MOSAL_PCI_write_config_data(u_int8_t bus,\r
- u_int8_t dev_func,\r
- u_int8_t offset,\r
- u_int32_t length,\r
- u_int8_t* data_p\r
- )\r
-{\r
- ULONG l_Bytes;\r
- l_Bytes = HalSetBusDataByOffset(\r
- PCIConfiguration,\r
- bus,\r
- dev_func>>3,\r
- (PVOID)data_p,\r
- offset,\r
- length\r
- );\r
- if (l_Bytes != length) \r
- return MT_ENORSC;\r
- return MT_OK;\r
- }\r
-\r
-\r
-NTSTATUS\r
-MapMemMapTheMemory(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN OUT PVOID IoBuffer,\r
- IN ULONG InputBufferLength,\r
- IN ULONG OutputBufferLength\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Given a physical address, maps this address into a user mode process's\r
- address space\r
-\r
-Arguments:\r
-\r
- DeviceObject - pointer to a device object\r
-\r
- IoBuffer - pointer to the I/O buffer\r
-\r
- InputBufferLength - input buffer length\r
-\r
- OutputBufferLength - output buffer length\r
-\r
-Return Value:\r
-\r
- STATUS_SUCCESS if sucessful, otherwise\r
- STATUS_UNSUCCESSFUL,\r
- STATUS_INSUFFICIENT_RESOURCES,\r
- (other STATUS_* as returned by kernel APIs)\r
-\r
---*/\r
-{\r
-\r
- PPHYSICAL_MEMORY_INFO ppmi = (PPHYSICAL_MEMORY_INFO) IoBuffer;\r
-\r
- INTERFACE_TYPE interfaceType;\r
- ULONG busNumber;\r
- PHYSICAL_ADDRESS physicalAddress;\r
- ULONG length;\r
- UNICODE_STRING physicalMemoryUnicodeString;\r
- OBJECT_ATTRIBUTES objectAttributes;\r
- HANDLE physicalMemoryHandle = NULL;\r
- PVOID PhysicalMemorySection = NULL;\r
- ULONG inIoSpace, inIoSpace2;\r
- NTSTATUS ntStatus;\r
- PHYSICAL_ADDRESS physicalAddressBase;\r
- PHYSICAL_ADDRESS physicalAddressEnd;\r
- PHYSICAL_ADDRESS viewBase;\r
- PHYSICAL_ADDRESS mappedLength;\r
-#ifndef DONT_TRANSLATE_BUS_ADDRESS\r
- BOOLEAN translateBaseAddress;\r
- BOOLEAN translateEndAddress;\r
-#endif \r
- PVOID virtualAddress;\r
- SIZE_T viewSize;\r
-\r
- if ( ( InputBufferLength < sizeof (PHYSICAL_MEMORY_INFO) ) ||\r
- ( OutputBufferLength < sizeof (PVOID) ) )\r
- {\r
- DbgPrint("(MapMemMapTheMemory) Insufficient input or output buffer\n");\r
-\r
- ntStatus = STATUS_INSUFFICIENT_RESOURCES;\r
-\r
- goto done;\r
- }\r
-\r
- interfaceType = ppmi->InterfaceType;\r
- busNumber = ppmi->BusNumber;\r
- physicalAddress = ppmi->BusAddress;\r
- inIoSpace = inIoSpace2 = ppmi->AddressSpace;\r
- length = ppmi->Length;\r
-\r
-\r
- //\r
- // Get a pointer to physical memory...\r
- //\r
- // - Create the name\r
- // - Initialize the data to find the object\r
- // - Open a handle to the oject and check the status\r
- // - Get a pointer to the object\r
- // - Free the handle\r
- //\r
-\r
- RtlInitUnicodeString (&physicalMemoryUnicodeString,\r
- L"\\Device\\PhysicalMemory");\r
-\r
- InitializeObjectAttributes (&objectAttributes,\r
- &physicalMemoryUnicodeString,\r
- OBJ_CASE_INSENSITIVE,\r
- (HANDLE) NULL,\r
- (PSECURITY_DESCRIPTOR) NULL);\r
-\r
- ntStatus = ZwOpenSection (&physicalMemoryHandle,\r
- SECTION_ALL_ACCESS,\r
- &objectAttributes);\r
-\r
- if (!NT_SUCCESS(ntStatus))\r
- {\r
- DbgPrint("(MapMemMapTheMemory) ZwOpenSection failed (0x%x)\n", ntStatus);\r
-\r
- goto done;\r
- }\r
-\r
- ntStatus = ObReferenceObjectByHandle (physicalMemoryHandle,\r
- SECTION_ALL_ACCESS,\r
- (POBJECT_TYPE) NULL,\r
- KernelMode,\r
- &PhysicalMemorySection,\r
- (POBJECT_HANDLE_INFORMATION) NULL);\r
-\r
- if (!NT_SUCCESS(ntStatus))\r
- {\r
- DbgPrint("(MapMemMapTheMemory) ObReferenceObjectByHandle failed (0x%x)\n", ntStatus);\r
-\r
- goto close_handle;\r
- }\r
-\r
- //\r
- // Initialize the physical addresses that will be translated\r
- //\r
-\r
- physicalAddressEnd.QuadPart = physicalAddress.QuadPart + length;\r
-\r
- //\r
- // Translate the physical addresses.\r
- //\r
-\r
-#ifdef DONT_TRANSLATE_BUS_ADDRESS\r
- physicalAddressBase = physicalAddress;\r
-#else\r
- translateBaseAddress =\r
- HalTranslateBusAddress (interfaceType,\r
- busNumber,\r
- physicalAddress,\r
- &inIoSpace,\r
- &physicalAddressBase);\r
-\r
- translateEndAddress =\r
- HalTranslateBusAddress (interfaceType,\r
- busNumber,\r
- physicalAddressEnd,\r
- &inIoSpace2,\r
- &physicalAddressEnd);\r
-\r
- if ( !(translateBaseAddress && translateEndAddress) ) {\r
- DbgPrint("(MapMemMapTheMemory) HalTranslatephysicalAddress failed\n");\r
-\r
- ntStatus = STATUS_UNSUCCESSFUL;\r
-\r
- goto close_handle;\r
- }\r
-#endif\r
-\r
- //\r
- // Calculate the length of the memory to be mapped\r
- //\r
-\r
- mappedLength.QuadPart =\r
- physicalAddressEnd.QuadPart - physicalAddressBase.QuadPart;\r
- //\r
- // If the mappedlength is zero, somthing very weird happened in the HAL\r
- // since the Length was checked against zero.\r
- //\r
-\r
- if (mappedLength.LowPart == 0) {\r
- DbgPrint("(MapMemMapTheMemory) mappedLength.LowPart == 0\n");\r
-\r
- ntStatus = STATUS_UNSUCCESSFUL;\r
-\r
- goto close_handle;\r
- }\r
-\r
- length = mappedLength.LowPart;\r
-\r
- //\r
- // If the address is in io space, just return the address, otherwise\r
- // go through the mapping mechanism\r
- //\r
-\r
- if (inIoSpace) {\r
- *((PVOID *) IoBuffer) = (PVOID) physicalAddressBase.QuadPart;\r
- } else {\r
- //\r
- // initialize view base that will receive the physical mapped\r
- // address after the MapViewOfSection call.\r
- //\r
-\r
- viewBase = physicalAddressBase;\r
-\r
- //\r
- // Let ZwMapViewOfSection pick an address\r
- //\r
-\r
- virtualAddress = NULL;\r
-\r
- //\r
- // Map the section\r
- //\r
- viewSize = length;\r
- ntStatus = ZwMapViewOfSection (physicalMemoryHandle,\r
- (HANDLE) -1,\r
- &virtualAddress,\r
- 0L,\r
- length,\r
- &viewBase,\r
- &viewSize,\r
- ViewShare,\r
- 0,\r
- PAGE_READWRITE | PAGE_NOCACHE);\r
-\r
- if (!NT_SUCCESS(ntStatus))\r
- {\r
- DbgPrint("(MapMemMapTheMemory) ZwMapViewOfSection failed (0x%x)\n", ntStatus);\r
-\r
- goto close_handle;\r
- }\r
-\r
- //\r
- // Mapping the section above rounded the physical address down to the\r
- // nearest 64 K boundary. Now return a virtual address that sits where\r
- // we want by adding in the offset from the beginning of the section.\r
- //\r
-\r
- (char*) virtualAddress += (ULONG)physicalAddressBase.LowPart -\r
- (ULONG)viewBase.LowPart;\r
-\r
- *((PVOID *) IoBuffer) = virtualAddress;\r
-\r
- }\r
-\r
- ntStatus = STATUS_SUCCESS;\r
-\r
-close_handle:\r
- ZwClose (physicalMemoryHandle);\r
-\r
-done:\r
- return ntStatus;\r
-}\r
-\r
-// leo\r
-// for some reason Compaq driver doesn't make ObDereference \r
-// i fixed it it here\r
-NTSTATUS\r
-MapMemUnmapTheMemory(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN PVOID IoBuffer,\r
- IN ULONG InputBufferLength,\r
- IN ULONG OutputBufferLength\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Given a physical address, maps this address into a user mode process's\r
- address space\r
-\r
-Arguments:\r
-\r
- DeviceObject - pointer to a device object\r
-\r
- IoBuffer - pointer to the I/O buffer\r
-\r
- InputBufferLength - input buffer length\r
-\r
- OutputBufferLength - output buffer length\r
-\r
-Return Value:\r
-\r
- STATUS_SUCCESS if sucessful, otherwise\r
- STATUS_UNSUCCESSFUL,\r
- STATUS_INSUFFICIENT_RESOURCES,\r
- (other STATUS_* as returned by kernel APIs)\r
-\r
---*/\r
-{\r
- UNICODE_STRING physicalMemoryUnicodeString;\r
- OBJECT_ATTRIBUTES objectAttributes;\r
- HANDLE physicalMemoryHandle = NULL;\r
- PVOID PhysicalMemorySection = NULL;\r
- NTSTATUS ntStatus, ntStatusUnmap;\r
- PVOID virtualAddress = *(PVOID*)IoBuffer;\r
-\r
- // unmap \r
- ntStatusUnmap = ZwUnmapViewOfSection ((HANDLE) -1, virtualAddress );\r
- if (!NT_SUCCESS(ntStatusUnmap)) {\r
- DbgPrint("(MapMemUnmapTheMemory) ZwUnmapViewOfSection failed (0x%x)\n", ntStatusUnmap);\r
- // no goto error - we'll try to dereference the object any way\r
- }\r
- \r
- //\r
- // dereference the section object\r
- //\r
-\r
- // open the section object\r
- RtlInitUnicodeString (&physicalMemoryUnicodeString, L"\\Device\\PhysicalMemory");\r
- InitializeObjectAttributes (&objectAttributes, &physicalMemoryUnicodeString,\r
- OBJ_CASE_INSENSITIVE, (HANDLE) NULL, (PSECURITY_DESCRIPTOR) NULL);\r
- ntStatus = ZwOpenSection (&physicalMemoryHandle, SECTION_ALL_ACCESS, &objectAttributes);\r
- if (!NT_SUCCESS(ntStatus)) {\r
- DbgPrint("(MapMemUnmapTheMemory) ZwOpenSection failed. Can't dereference the section object (0x%x)\n", ntStatus);\r
- goto done;\r
- }\r
-\r
- // get pointer to the object\r
- ntStatus = ObReferenceObjectByHandle (physicalMemoryHandle, SECTION_ALL_ACCESS,\r
- (POBJECT_TYPE) NULL, KernelMode, &PhysicalMemorySection, (POBJECT_HANDLE_INFORMATION) NULL);\r
- if (!NT_SUCCESS(ntStatus)) {\r
- DbgPrint("(MapMemUnmapTheMemory) ObReferenceObjectByHandle failed. Can't dereference the section object (0x%x)\n", ntStatus);\r
- goto close_handle;\r
- }\r
-\r
- // dereference the object (twice - because we made the second reference in order to get a pointer to the object)\r
- ObDereferenceObject( PhysicalMemorySection );\r
- ObDereferenceObject( PhysicalMemorySection );\r
-\r
- // close the object\r
-close_handle:\r
- ZwClose (physicalMemoryHandle);\r
-\r
-done: \r
- if (!NT_SUCCESS(ntStatusUnmap)) \r
- ntStatus = ntStatusUnmap;\r
- \r
- return ntStatus;\r
-}\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_NTDDK_H\r
-#define H_MOSAL_NTDDK_H\r
-\r
-#include <mtl_errno.h>\r
-#if 0\r
-#include <mtl_types.h>\r
-#else\r
-typedef char int8_t;\r
-typedef unsigned char u_int8_t;\r
-typedef short int int16_t;\r
-typedef unsigned short int u_int16_t;\r
-typedef INT32 int32_t;\r
-typedef UINT32 u_int32_t;\r
-typedef INT64 int64_t;\r
-typedef UINT64 u_int64_t;\r
-#endif\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_PCI_find_device\r
- *\r
- * Description: Find a PCI device based on Vendor and deviceID.\r
- *\r
- * Parameters:\r
- * vendor_id(IN) u_int16_t\r
- * Vendor ID.\r
- * dev_id(IN) u_int16_t\r
- * Device ID.\r
- * index(IN) u_int16_t\r
- * Occurance of device of given Vendor/Device IDs.\r
- * bus_p(OUT) u_int8_t *\r
- * Bus num of matching device.\r
- * dev_func_p(OUT) u_int8_t *\r
- * Device/Function ([7:3]/[2:0]) of matching device.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK if found, MT_ENODEV if such device not found.\r
- *\r
- * Note:\r
- * For hot-swap support, the PCI bus should be really probed on device\r
- * search, and not a preset DB (which was usually created during boot).\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_PCI_find_device(u_int16_t vendor_id, u_int16_t dev_id,\r
- u_int16_t index,\r
- u_int8_t *bus_p, u_int8_t *dev_func_p);\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_PCI_read_config_byte\r
- *\r
- * Description: Read byte of PCI config space.\r
- *\r
- * Parameters:\r
- * bus(IN) u_int8_t\r
- * Bus num of device.\r
- * dev_func(IN) u_int8_t\r
- * Device/Function ([7:3]/[2:0]) of device.\r
- * offset(IN) u_int8_t\r
- * Offset in device's config header.\r
- * data_p(OUT) u_int8_t*\r
- * Ptr to a byte data buffer which holds read val.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK if success, MT_ERROR if failed.\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_PCI_read_config_byte(u_int8_t bus, u_int8_t dev_func,\r
- u_int8_t offset, u_int8_t* data_p);\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_PCI_read_config_word\r
- *\r
- * Description: Read byte of PCI config space.\r
- *\r
- * Parameters:\r
- * bus(IN) u_int8_t\r
- * Bus num of device.\r
- * dev_func(IN) u_int8_t\r
- * Device/Function ([7:3]/[2:0]) of device.\r
- * offset(IN) u_int8_t\r
- * Offset in device's config header.\r
- * data_p(OUT) u_int16_t*\r
- * Ptr to a word data buffer which holds read val.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK if success, MT_ERROR if failed.\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_PCI_read_config_word(u_int8_t bus, u_int8_t dev_func,\r
- u_int8_t offset, u_int16_t* data_p);\r
-\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_PCI_read_config_dword\r
- *\r
- * Description: Read byte of PCI config space.\r
- *\r
- * Parameters:\r
- * bus(IN) u_int8_t\r
- * Bus num of device.\r
- * dev_func(IN) u_int8_t\r
- * Device/Function ([7:3]/[2:0]) of device.\r
- * offset(IN) u_int8_t\r
- * Offset in device's config header.\r
- * data_p(OUT) u_int32_t*\r
- * Ptr to a dword data buffer which holds read val.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK if success, MT_ERROR if failed.\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_PCI_read_config_dword(u_int8_t bus, u_int8_t dev_func,\r
- u_int8_t offset, u_int32_t* data_p);\r
-\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_PCI_read_config_data\r
- *\r
- * Description: Read byte of PCI config space.\r
- *\r
- * Parameters:\r
- * bus(IN) u_int8_t\r
- * Bus num of device.\r
- * dev_func(IN) u_int8_t\r
- * Device/Function ([7:3]/[2:0]) of device.\r
- * offset(IN) u_int8_t\r
- * Offset in device's config header.\r
- * length(IN) u_int32_t\r
- * Length of data.\r
- * data_p(OUT) u_int8_t*\r
- * Ptr to a dword data buffer which holds read val.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK if success, MT_ERROR if failed.\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_PCI_read_config_data(u_int8_t bus, u_int8_t dev_func,\r
- u_int8_t offset, u_int32_t length, u_int8_t* data_p);\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_PCI_write_config_byte\r
- *\r
- * Description: Write byte to PCI config space.\r
- *\r
- * Parameters:\r
- * bus(IN) u_int8_t\r
- * Bus num of device.\r
- * dev_func(IN) u_int8_t\r
- * Device/Function ([7:3]/[2:0]) of device.\r
- * offset(IN) u_int8_t\r
- * Offset in device's config header.\r
- * data(IN) u_int8_t\r
- * Val to write.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK if success, MT_ERROR if failed.\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_PCI_write_config_byte(u_int8_t bus, u_int8_t dev_func,\r
- u_int8_t offset, u_int8_t data);\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_PCI_write_config_word\r
- *\r
- * Description: Write word of PCI config space.\r
- *\r
- * Parameters:\r
- * bus(IN) u_int8_t\r
- * Bus num of device.\r
- * dev_func(IN) u_int8_t\r
- * Device/Function ([7:3]/[2:0]) of device.\r
- * offset(IN) u_int8_t\r
- * Offset in device's config header.\r
- * data(IN) u_int16_t\r
- * Val to write.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK if success, MT_ERROR if failed.\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_PCI_write_config_word(u_int8_t bus, u_int8_t dev_func,\r
- u_int8_t offset, u_int16_t data);\r
-\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_PCI_write_config_dword\r
- *\r
- * Description: Write dword of PCI config space.\r
- *\r
- * Parameters:\r
- * bus(IN) u_int8_t\r
- * Bus num of device.\r
- * dev_func(IN) u_int8_t\r
- * Device/Function ([7:3]/[2:0]) of device.\r
- * offset(IN) u_int8_t\r
- * Offset in device's config header.\r
- * data(IN) u_int32_t\r
- * Val to write.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK if success, MT_ERROR if failed.\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_PCI_write_config_dword(u_int8_t bus,\r
- u_int8_t dev_func,\r
- u_int8_t offset,\r
- u_int32_t data);\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_PCI_write_config_data\r
- *\r
- * Description: Write dword of PCI config space.\r
- *\r
- * Parameters:\r
- * bus(IN) u_int8_t\r
- * Bus num of device.\r
- * dev_func(IN) u_int8_t\r
- * Device/Function ([7:3]/[2:0]) of device.\r
- * offset(IN) u_int8_t\r
- * Offset in device's config header.\r
- * length(IN) u_int32_t\r
- * Length of data.\r
- * data_p(IN) u_int8_t*\r
- * Val to write.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK if success, MT_ERROR if failed.\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_PCI_write_config_data(u_int8_t bus,\r
- u_int8_t dev_func,\r
- u_int8_t offset,\r
- u_int32_t length,\r
- u_int8_t* data_p);\r
-\r
-\r
-#ifdef __KERNEL__\r
-/* \r
- * Our user mode app will pass an initialized structure like this\r
- * down to the kernel mode driver\r
- */\r
-\r
-typedef struct\r
-{\r
- INTERFACE_TYPE InterfaceType; /* Isa, Eisa, etc.... */\r
- ULONG BusNumber; /* Bus number */\r
- PHYSICAL_ADDRESS BusAddress; /* Bus-relative address */\r
- ULONG AddressSpace; /* 0 is memory, 1 is I/O */\r
- ULONG Length; /* Length of section to map */\r
-\r
-} PHYSICAL_MEMORY_INFO, *PPHYSICAL_MEMORY_INFO;\r
-\r
-NTSTATUS\r
-MapMemMapTheMemory(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN OUT PVOID IoBuffer,\r
- IN ULONG InputBufferLength,\r
- IN ULONG OutputBufferLength\r
- );\r
-\r
-NTSTATUS\r
-MapMemUnmapTheMemory(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN PVOID IoBuffer,\r
- IN ULONG InputBufferLength,\r
- IN ULONG OutputBufferLength\r
- );\r
-#endif\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_PRIV_H\r
-#define H_MOSAL_PRIV_H\r
-\r
-/* ----- common stuff ----- */\r
-#include <mtl_common.h>\r
-#include <mosal_prot_ctx_imp.h>\r
-#include <mosal_prot_ctx.h>\r
-\r
-\r
-/* ----- mosal OS-independent types ----- */\r
-\r
-/* exported services */\r
-#include "mosal_timer_priv.h"\r
-#include "mosal_que_priv.h"\r
-#include "mosal_mem_priv.h"\r
-#include "mosal_mlock_priv.h"\r
-#include "mosal_que_priv.h"\r
-#include "mosal_gen_priv.h"\r
-#include "mosal.h"\r
-#include "mosal_sync_priv.h"\r
-#include "mosal_k2u_cbk_priv.h"\r
-\r
-/* ----- helpers ----- */\r
-#include "mosal_util.h"\r
-\r
-#endif\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_PROT_CTX_IMP_H\r
-#define H_MOSAL_PROT_CTX_IMP_H\r
-\r
-typedef MT_ulong_ptr_t mosal_pid_t;\r
-\r
-/* Protection and virtual-memory context */\r
-typedef enum {\r
- MOSAL_PROT_CTX_KERNEL, /* Kernel protection/memory context */ \r
- MOSAL_PROT_CTX_CURRENT_USER /* Current user level protection/memory context */\r
-} mosal_prot_ctx_t;\r
-\r
-/* "functions" for backward compatibility */\r
-#define mosal_get_current_prot_ctx() MOSAL_PROT_CTX_CURRENT_USER\r
-#define mosal_get_kernel_prot_ctx() MOSAL_PROT_CTX_KERNEL\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "mosal_priv.h"\r
-\r
-extern KIRQL cur_max_irql;\r
-\r
-\r
-/* structures */\r
-/* Mosal queue defs. */\r
-struct mosalq_el\r
-{\r
- // must be the first\r
- LIST_ENTRY link;\r
- union {\r
- struct { /* data element */\r
- int size;\r
- void * data;\r
- };\r
- struct { /* process element */\r
- KEVENT h_event; \r
- };\r
- };\r
-};\r
-\r
-struct mosalq_st\r
-{\r
- LIST_ENTRY link;\r
- LIST_ENTRY proc_que;\r
- LIST_ENTRY data_que;\r
- MOSAL_data_free_t qdestroy_free; /* Use to free of data on qdestroy */\r
- BOOLEAN remove;\r
- int proc_num;\r
-};\r
-\r
-/* queue support */\r
-static struct mosalq_st q_hdr[MOSAL_MAX_QHANDLES]; /* q db */\r
-static struct mosalq_el q_el[MOSAL_MAX_QELEMENTS];\r
-static LIST_ENTRY q_free_el;\r
-static LIST_ENTRY q_free_hdr;\r
-\r
-#define QPTR_2_HANDLE(ptr) (((char*)ptr - (char*)&q_hdr[0]) / sizeof(struct mosalq_st))\r
-#define QHANDLE_2_PTR(ix) (&q_hdr[ix])\r
-\r
-/* Helpers */\r
-void init_queues()\r
-{\r
- int i; \r
- struct mosalq_el * q_el_p = &q_el[0];\r
- struct mosalq_st * q_hdr_p = &q_hdr[0];\r
-\r
- /* zero DBs */\r
- memset(q_hdr, 0, sizeof(q_hdr));\r
- memset(q_el, 0, sizeof(q_el));\r
-\r
- /* init free chain headers */\r
- InitializeListHead( &q_free_el );\r
- InitializeListHead( &q_free_hdr );\r
-\r
- /* init q_el and link them into LIFO chain */\r
- for (i=0; i<MOSAL_MAX_QELEMENTS; i++, q_el_p++) {\r
- InsertTailList( &q_free_el, &q_el_p->link );\r
- }\r
-\r
- /* init q_hdr and link them into LIFO chain */\r
- for (i=0; i<MOSAL_MAX_QHANDLES; i++, q_hdr_p++) {\r
- InitializeListHead( &q_hdr_p->proc_que );\r
- InitializeListHead( &q_hdr_p->data_que );\r
- InsertTailList( &q_free_hdr, &q_hdr_p->link );\r
- }\r
-\r
-}\r
-\r
-struct mosalq_st *alloc_qhdr()\r
-{\r
- struct mosalq_st * hdr;\r
- \r
- if ( IsListEmpty( &q_free_hdr ) )\r
- return NULL;\r
- hdr = (struct mosalq_st *)RemoveHeadList( &q_free_hdr );\r
- return hdr;\r
-}\r
-\r
-struct mosalq_el *alloc_qel()\r
-{\r
- struct mosalq_el * el;\r
- \r
- if ( IsListEmpty( &q_free_el ) )\r
- return NULL;\r
- el = (struct mosalq_el *)RemoveHeadList( &q_free_el );\r
- return el;\r
-}\r
-\r
-void free_qhdr(struct mosalq_st *q_hdr_p)\r
-{\r
- InsertHeadList( &q_free_hdr, &q_hdr_p->link );\r
-}\r
-\r
-void free_qel(struct mosalq_el *q_el_p)\r
-{\r
- InsertHeadList( &q_free_el, &q_el_p->link );\r
-}\r
-\r
-\r
-call_result_t MOSAL_qcreate(MOSAL_qhandle_t *qh, MOSAL_data_free_t qdestroy_free)\r
-{\r
- call_result_t rc = MT_OK;\r
- struct mosalq_st * q_hdr_p = alloc_qhdr();\r
-\r
- MTL_TRACE1("-> MOSAL_qcreate(...)\n");\r
-\r
- if (q_hdr_p == NULL)\r
- return MT_EAGAIN; /* no free q handle */\r
- memset( q_hdr_p, 0, sizeof(struct mosalq_st) );\r
- InitializeListHead( &q_hdr_p->proc_que );\r
- InitializeListHead( &q_hdr_p->data_que );\r
- q_hdr_p->qdestroy_free = qdestroy_free;\r
- q_hdr_p->proc_num = 0;\r
- q_hdr_p->remove = FALSE;\r
- *qh = (MOSAL_qhandle_t)QPTR_2_HANDLE(q_hdr_p);\r
-\r
- MTL_TRACE1("<- MOSAL_qcreate qh=%d rc=%d (%s)\n\n",\r
- *qh, rc, mtl_strerror_sym(rc));\r
- return rc;\r
-}\r
-\r
-bool MOSAL_isqempty(MOSAL_qhandle_t qh)\r
-{\r
- /* check parameters */\r
- if (qh >= MOSAL_MAX_QHANDLES) \r
- return MT_ENORSC; /* no such queue */\r
- return IsListEmpty(&(QHANDLE_2_PTR(qh))->data_que);\r
-}\r
-\r
-#ifdef SUSPEND_IRP\r
-call_result_t complete_MOSAL_qget(call_result_t rc, int *size, void **data, struct mosalq_st * q_hdr_p )\r
-{\r
- struct mosalq_el *q_data_p;\r
- \r
- if (rc == MT_OK)\r
- { /* get data */\r
- if (!IsListEmpty(&q_hdr_p->data_que))\r
- { \r
- q_data_p = (struct mosalq_el*)RemoveHeadList( &q_hdr_p->data_que);\r
- *size = q_data_p->size;\r
- *data = q_data_p->data;\r
- free_qel(q_data_p);\r
- }\r
- else\r
- { /* it can only be on qdestroy with pending processes */\r
- *size = 0;\r
- *data = NULL;\r
- rc = MT_ERROR;\r
- // free the queue header\r
- q_hdr_p->proc_num--;\r
- if (q_hdr_p->remove && !q_hdr_p->proc_num)\r
- free_qhdr( q_hdr_p );\r
- } /* it can only be on qdestroy with pending processes */\r
- } /* get data */\r
-\r
- MTL_TRACE1("<- MOSAL_qget, size=%d rc=%d (%s)\n\n",\r
- *size, rc, mtl_strerror_sym(rc));\r
- return rc;\r
-}\r
-#endif\r
-\r
-call_result_t MOSAL_qget(MOSAL_qhandle_t qh, int *size, void **data, bool block)\r
-{\r
- call_result_t rc = MT_OK;\r
- struct mosalq_st * q_hdr_p;\r
- struct mosalq_el *q_data_p, *q_proc_p;\r
- bool was_empty = FALSE;\r
- KIRQL irql;\r
-\r
- MTL_TRACE1("-> MOSAL_qget(0x%x, ..., %d)\n", (u_int32_t)qh, block);\r
- /* check parameters */\r
- if (qh >= MOSAL_MAX_QHANDLES) \r
- {\r
- rc = MT_ENORSC; /* no such queue */\r
- goto exit;\r
- }\r
- q_hdr_p = QHANDLE_2_PTR(qh);\r
-\r
- // ??? Race with ISR: Here must be SpinLockAcquire()\r
- KeRaiseIrql( (KIRQL)cur_max_irql, &irql);\r
- if ( IsListEmpty( &q_hdr_p->data_que ))\r
- { /* no data pending */\r
- if (block)\r
- { /* blocking mode */\r
-\r
- /* get proc element */\r
- q_proc_p = alloc_qel();\r
- if (q_proc_p == NULL)\r
- {\r
- rc = MT_ENORSC;\r
- goto fix_irql;\r
- }\r
- else\r
- { /* put the process on wait */\r
- MTL_TRACE4(" MOSAL_qget(0x%x, ...) - go sleep\n", (u_int32_t)qh);\r
- // init the proc element\r
- KeInitializeEvent( &q_proc_p->h_event, NotificationEvent, FALSE);\r
- // queue it\r
- InsertTailList( &q_hdr_p->proc_que, &q_proc_p->link );\r
- q_hdr_p->proc_num++;\r
- // ??? Race with ISR: Here must be SpinLockRelease()\r
- KeLowerIrql(irql);\r
- // Wait until the IRP will be complete\r
- KeWaitForSingleObject(\r
- &q_proc_p->h_event, // event to wait for\r
- Executive, // thread type (to wait into its context)\r
- KernelMode, // mode of work\r
- FALSE, // alertable\r
- NULL // timeout\r
- );\r
- goto exit;\r
-\r
- } /* put the process on wait */\r
-\r
- } /* blocking mode */\r
- else\r
- {\r
- // ??? Race with ISR: Here must be SpinLockRelease()\r
- rc = MT_EAGAIN;\r
- goto fix_irql;\r
- }\r
-\r
- } /* no data pending */\r
-fix_irql:\r
- KeLowerIrql(irql);\r
-\r
-exit:\r
-#ifdef SUSPEND_IRP\r
- return complete_MOSAL_qget(rc, size, data, q_hdr_p );\r
-#else\r
-\r
- if (rc == MT_OK)\r
- { /* get data */\r
- if (!IsListEmpty(&q_hdr_p->data_que))\r
- { \r
- q_data_p = (struct mosalq_el*)RemoveHeadList( &q_hdr_p->data_que);\r
- *size = q_data_p->size;\r
- *data = q_data_p->data;\r
- free_qel(q_data_p);\r
- }\r
- else\r
- { /* it can only be on qdestroy with pending processes */\r
- *size = 0;\r
- *data = NULL;\r
- rc = MT_ERROR;\r
- // free the queue header\r
- q_hdr_p->proc_num--;\r
- if (q_hdr_p->remove && !q_hdr_p->proc_num)\r
- free_qhdr( q_hdr_p );\r
- } /* it can only be on qdestroy with pending processes */\r
- } /* get data */\r
-\r
- MTL_TRACE1("<- MOSAL_qget, size=%d rc=%d (%s)\n\n",\r
- *size, rc, mtl_strerror_sym(rc));\r
- return rc;\r
-#endif\r
-}\r
-\r
-call_result_t MOSAL_qput(MOSAL_qhandle_t qh, int size, void *data)\r
-{\r
- call_result_t rc = MT_OK;\r
- struct mosalq_st * q_hdr_p;\r
- struct mosalq_el *q_data_p, *q_proc_p;\r
- bool was_empty = FALSE;\r
-\r
- MTL_TRACE1("-> MOSAL_qput(%d,%d,<data>)\n", (u_int32_t)qh, size);\r
- /* check parameters */\r
- if (qh >= MOSAL_MAX_QHANDLES) \r
- return MT_ENORSC; /* no such queue */\r
- q_hdr_p = QHANDLE_2_PTR(qh);\r
-\r
- /* get data element */\r
- q_data_p = alloc_qel();\r
- if (q_data_p == NULL)\r
- return MT_ENORSC;\r
-\r
- /* fill data element */\r
- q_data_p->size = size;\r
- q_data_p->data = data;\r
-\r
- /* put element into the queue */\r
- if ( IsListEmpty( &q_hdr_p->data_que ))\r
- was_empty = TRUE;\r
- InsertTailList( &q_hdr_p->data_que, &q_data_p->link );\r
- if (was_empty && !IsListEmpty( &q_hdr_p->proc_que ))\r
- { /* awake waiting process */ \r
- MTL_TRACE4(" MOSAL_qput(0x%x) - try to wake up\n", (u_int32_t)qh);\r
- q_proc_p = (struct mosalq_el*)RemoveHeadList( &q_hdr_p->proc_que );\r
- q_hdr_p->proc_num--;\r
- KeSetEvent (&q_proc_p->h_event, IO_NO_INCREMENT, FALSE);\r
- free_qel( q_proc_p );\r
- }\r
-\r
- MTL_TRACE1("<- MOSAL_qput rc=%d (%s)\n\n", rc, mtl_strerror_sym(rc));\r
- return rc;\r
-}\r
-\r
-call_result_t MOSAL_qdestroy(MOSAL_qhandle_t qh)\r
-{\r
- call_result_t rc = MT_OK;\r
- struct mosalq_st * q_hdr_p;\r
- struct mosalq_el *q_data_p, *q_proc_p;\r
-\r
- MTL_TRACE1("-> MOSAL_qdestroy(0x%x)\n", (u_int32_t)qh);\r
- /* check parameters */\r
- if (qh >= MOSAL_MAX_QHANDLES) \r
- return MT_ENORSC; /* no such queue */\r
- q_hdr_p = QHANDLE_2_PTR(qh);\r
-\r
- // free data, if any\r
- while ( !IsListEmpty( &q_hdr_p->data_que ) )\r
- { /* free data elements */\r
- // get first data elemenet\r
- q_data_p = (struct mosalq_el*)RemoveHeadList( &q_hdr_p->data_que);\r
- // release its data\r
- if (q_hdr_p->qdestroy_free && q_data_p->data)\r
- q_hdr_p->qdestroy_free(q_data_p->data);\r
- // release the element itself\r
- free_qel( q_data_p );\r
- }\r
-\r
- // post waiting processes, if any\r
- while ( !IsListEmpty( &q_hdr_p->proc_que ) )\r
- { \r
- q_proc_p = (struct mosalq_el*)RemoveHeadList( &q_hdr_p->proc_que );\r
- KeSetEvent (&q_proc_p->h_event, IO_NO_INCREMENT, FALSE);\r
- free_qel( q_proc_p );\r
- q_hdr_p->remove = TRUE;\r
- }\r
-\r
- // free the queue header\r
- if (!q_hdr_p->remove)\r
- free_qhdr( q_hdr_p );\r
-\r
- MTL_TRACE1("<- MOSAL_qdestroy rc=%d (%s)\n\n", rc, mtl_strerror_sym(rc));\r
- return rc;\r
-}\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_QUE_PRIV_H\r
-#define H_MOSAL_QUE_PRIV_H\r
-\r
-#define MOSAL_MAX_QELEMENTS 1024\r
-void init_queues();\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-\r
-/* !!! function ExTryToAcquireFastMutex() is not defined for WDM drivers, so we'll use KMUTEX :( */\r
-/* Defined in the SOURCES file as build flags */\r
-//#define USE_KMUTEX 0\r
-\r
-#include "mosal_priv.h"\r
-\r
-////////////////////////////////////////////////////////////////////////////////\r
-// Debug Tools\r
-////////////////////////////////////////////////////////////////////////////////\r
-#ifdef USE_TRACE\r
-#define TRACE_ARRAY_SIZE 1024\r
-#define TRACE_CNT_NUM 8\r
-int g_trace_ix = 0;\r
-char g_trace_buf[TRACE_ARRAY_SIZE];\r
-KSPIN_LOCK g_trace_sp;\r
-long g_trace_cnt[TRACE_CNT_NUM];\r
-void MOSAL_trace_init()\r
-{\r
- KeInitializeSpinLock(&g_trace_sp);\r
- g_trace_ix = 0;\r
- RtlZeroMemory( g_trace_cnt, sizeof(g_trace_cnt) );\r
-}\r
-#endif\r
-\r
-void MOSAL_trace_log(char who, char value1, char value2, char value3)\r
-{\r
-#ifdef USE_TRACE\r
- KIRQL irql;\r
- \r
- irql = KeAcquireSpinLockRaiseToSynch(&g_trace_sp);\r
- if (who < TRACE_CNT_NUM)\r
- g_trace_cnt[who]++;\r
- g_trace_buf[g_trace_ix++] = who;\r
- g_trace_buf[g_trace_ix++] = value1;\r
- g_trace_buf[g_trace_ix++] = value2;\r
- g_trace_buf[g_trace_ix++] = value3;\r
- if (g_trace_ix >= TRACE_ARRAY_SIZE)\r
- g_trace_ix = 0;\r
- KeReleaseSpinLock(&g_trace_sp, irql );\r
-#endif\r
-}\r
-\r
-\r
-////////////////////////////////////////////////////////////////////////////////\r
-// Synchronization object\r
-////////////////////////////////////////////////////////////////////////////////\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_syncobj_init\r
- *\r
- * Description:\r
- * Init sync object\r
- *\r
- * Parameters: \r
- * obj_p(IN) pointer to synch object\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_syncobj_init(MOSAL_syncobj_t *obj_p)\r
-{\r
- KeInitializeEvent( &obj_p->event, NotificationEvent , FALSE );\r
- return MT_OK;\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_syncobj_waiton\r
- *\r
- * Description:\r
- * cause process to sleep until synchonization object is signalled or time\r
- * expires\r
- *\r
- * Parameters: \r
- * obj_p(IN) pointer to synch object\r
- * micro_sec(IN) max time to wait in microseconds\r
- *\r
- * Returns:\r
- * MT_OK - woke up by event\r
- * MT_EINTR - woke up by signal\r
- * MT_ETIMEDOUT - wokeup because of timeout\r
- * MT_ERROR - some other error\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_syncobj_waiton(MOSAL_syncobj_t *obj_p, MT_size_t micro_sec)\r
-{\r
- NTSTATUS status;\r
- LARGE_INTEGER timeout;\r
- KPROCESSOR_MODE pcs_mode = ExGetPreviousMode();\r
- \r
- timeout.QuadPart = ((int64_t)(u_int64_t)micro_sec) * (-10);\r
-\r
- if ( micro_sec == MOSAL_SYNC_TIMEOUT_INFINITE ) \r
- status = KeWaitForSingleObject( &obj_p->event, Executive, pcs_mode, TRUE, NULL );\r
- else\r
- status = KeWaitForSingleObject( &obj_p->event, Executive, pcs_mode, TRUE, &timeout );\r
- if (status == STATUS_SUCCESS)\r
- return MT_OK;\r
- if (status == STATUS_TIMEOUT)\r
- return MT_ETIMEDOUT;\r
- return MT_EINTR;\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_syncobj_waiton\r
- *\r
- * Description:\r
- * cause process to sleep until synchonization object is signalled or time\r
- * expires\r
- *\r
- * Parameters: \r
- * obj_p(IN) pointer to synch object\r
- * micro_sec(IN) max time to wait in microseconds\r
- *\r
- * Returns:\r
- * MT_OK - woke up by event\r
- * MT_ETIMEDOUT - wokeup because of timeout\r
- * MT_ERROR - some other error\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_syncobj_waiton_ui(MOSAL_syncobj_t *obj_p, MT_size_t micro_sec)\r
-{\r
- NTSTATUS status;\r
- LARGE_INTEGER timeout;\r
- KPROCESSOR_MODE pcs_mode = ExGetPreviousMode();\r
-\r
- timeout.QuadPart = ((int64_t)(u_int64_t)micro_sec) * (-10);\r
-\r
-try_once_more: \r
- if ( micro_sec == MOSAL_SYNC_TIMEOUT_INFINITE ) \r
- status = KeWaitForSingleObject( &obj_p->event, Executive, pcs_mode, FALSE, NULL );\r
- else\r
- status = KeWaitForSingleObject( &obj_p->event, Executive, pcs_mode, FALSE, &timeout );\r
- if (status == STATUS_SUCCESS)\r
- return MT_OK;\r
- if (status == STATUS_TIMEOUT)\r
- return MT_ETIMEDOUT;\r
- goto try_once_more;\r
-}\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_syncobj_signal\r
- *\r
- * Description:\r
- * signal the synchronization object\r
- *\r
- * Parameters: \r
- * obj_p(IN) pointer to synch object\r
- *\r
- * Returns:\r
- * N/A\r
- *\r
- ******************************************************************************/\r
-void MOSAL_syncobj_signal(MOSAL_syncobj_t *obj_p)\r
-{\r
- ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL);\r
- KeSetEvent( &obj_p->event, 0, FALSE );\r
-}\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_syncobj_clear\r
- *\r
- * Description:\r
- * reset sync object (i.e. bring it to init - not-signalled -state)\r
- *\r
- * Parameters: \r
- * obj_p(IN) pointer to synch object\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-void MOSAL_syncobj_clear(MOSAL_syncobj_t *obj_p)\r
-{\r
- ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL);\r
- KeClearEvent( &obj_p->event );\r
-}\r
-\r
-\r
-\r
-////////////////////////////////////////////////////////////////////////////////\r
-// Semaphores\r
-////////////////////////////////////////////////////////////////////////////////\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_sem_init\r
- *\r
- * Description:\r
- * init semaphore\r
- *\r
- * Parameters: \r
- * sem_p(OUT) pointer to semaphore to be initialized\r
- * count(IN) max number of processes that can hold the semaphore at the same time\r
- *\r
- * Returns:\r
- *\r
- \r
-******************************************************************************/\r
-call_result_t MOSAL_sem_init(MOSAL_semaphore_t *sem_p, MT_size_t count)\r
-{\r
- ASSERT(KeGetCurrentIrql() == PASSIVE_LEVEL);\r
- KeInitializeSemaphore( &sem_p->sem, (LONG)count, LONG_MAX );\r
- return MT_OK;\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_sem_acq\r
- *\r
- * Description:\r
- * acquire the semaphore\r
- *\r
- * Parameters: \r
- * sem_p(IN) pointer to semaphore\r
- * block(IN) if - FALSE, return immediately if could not acquire, otherwise block if necessary\r
- *\r
- * Returns:\r
- * MT_OK - semaphore acquired\r
- * MT_EAGAIN - semaphore not acquired (only - in non-blocking mode)\r
- *\r
- *******************************************************************************/\r
-call_result_t MOSAL_sem_acq(MOSAL_semaphore_t *sem_p, MT_bool block)\r
-{\r
- NTSTATUS status;\r
- LARGE_INTEGER timeout = { 0, 0 };\r
- KPROCESSOR_MODE pcs_mode = ExGetPreviousMode();\r
- \r
- if (block) {\r
- ASSERT(KeGetCurrentIrql() < DISPATCH_LEVEL);\r
- status = KeWaitForSingleObject( &sem_p->sem, Executive, pcs_mode, TRUE, NULL );\r
- }\r
- else {\r
- ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL);\r
- status = KeWaitForSingleObject( &sem_p->sem, Executive, pcs_mode, TRUE, &timeout );\r
- }\r
- if (status == STATUS_SUCCESS)\r
- return MT_OK;\r
- if (status == STATUS_TIMEOUT)\r
- return MT_ETIMEDOUT;\r
- return MT_EINTR;\r
-}\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_sem_acq_ui\r
- *\r
- * Description:\r
- * acquire the semaphore\r
- *\r
- * Parameters: \r
- * sem_p(IN) pointer to semaphore\r
- *\r
- * Returns:\r
- *\r
- *******************************************************************************/\r
-void MOSAL_sem_acq_ui(MOSAL_semaphore_t *sem_p)\r
-{\r
- NTSTATUS status;\r
- LARGE_INTEGER timeout = { 0, 0 };\r
- KPROCESSOR_MODE pcs_mode = ExGetPreviousMode();\r
- \r
- ASSERT(KeGetCurrentIrql() < DISPATCH_LEVEL);\r
- while (1) {\r
- status = KeWaitForSingleObject( &sem_p->sem, Executive, pcs_mode, FALSE, NULL );\r
- if (status == STATUS_SUCCESS)\r
- break;\r
- }\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_sem_rel\r
- *\r
- * Description:\r
- * release the semaphore\r
- *\r
- * Parameters: \r
- * sem_p(IN) pointer to semaphore\r
- *\r
- * Returns:\r
- * N/A\r
- *\r
- ******************************************************************************/\r
-void MOSAL_sem_rel(MOSAL_semaphore_t *sem_p)\r
-{\r
- ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL);\r
- KeReleaseSemaphore( &sem_p->sem, 0, 1, FALSE );\r
-}\r
-\r
-////////////////////////////////////////////////////////////////////////////////\r
-// Mutexes\r
-////////////////////////////////////////////////////////////////////////////////\r
-\r
-typedef struct MOSAL_mutex MOSAL_mutex_t;\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_mutex_init\r
- *\r
- * Description:\r
- * init mutex\r
- *\r
- * Parameters: \r
- * mtx_p(OUT) pointer to mutex to be initialized\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_mutex_init(MOSAL_mutex_t *mtx_p)\r
-{\r
- ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL);\r
- #ifdef USE_KMUTEX\r
- KeInitializeMutex( &mtx_p->mutex, 0 );\r
- #else\r
- ExInitializeFastMutex( &mtx_p->mutex );\r
- #endif\r
- return MT_OK;\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_mutex_acq\r
- *\r
- * Description:\r
- * acquire the mutex\r
- *\r
- * Parameters: \r
- * mtx_p(IN) pointer to mutex\r
- * block(IN) if - FALSE, return immediately if could not acquire, otherwise block if necessary\r
- *\r
- * Returns:\r
- * MT_OK - mutex acquired\r
- * MT_ETIMEDOUT - mutex not acquired (only - in non-blocking mode)\r
- * MT_EINTR - mutex not acquired out of some other error\r
- *\r
-******************************************************************************/\r
-call_result_t MOSAL_mutex_acq(MOSAL_mutex_t *mtx_p, MT_bool block)\r
-{\r
- NTSTATUS status = STATUS_SUCCESS;\r
- LARGE_INTEGER timeout = { 0, 0 };\r
- KPROCESSOR_MODE pcs_mode = ExGetPreviousMode();\r
- \r
- if (block) {\r
- ASSERT(KeGetCurrentIrql() < DISPATCH_LEVEL);\r
- #ifdef USE_KMUTEX\r
- status = KeWaitForSingleObject( &mtx_p->mutex, Executive, pcs_mode, TRUE, NULL );\r
- #else \r
- ExAcquireFastMutex( &mtx_p->mutex );\r
- #endif \r
- }\r
- else {\r
- #ifdef USE_KMUTEX\r
- ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL);\r
- status = KeWaitForSingleObject( &mtx_p->mutex, Executive, pcs_mode, TRUE, &timeout );\r
- #else \r
- ASSERT(KeGetCurrentIrql() < DISPATCH_LEVEL);\r
- /* !!! this function is not defined for WDM drivers, so we'll use KMUTEX :( */\r
- if (!ExTryToAcquireFastMutex( &mtx_p->mutex ))\r
- status = STATUS_TIMEOUT;\r
- #endif \r
- } \r
- if (status == STATUS_SUCCESS)\r
- return MT_OK;\r
- if (status == STATUS_TIMEOUT)\r
- return MT_ETIMEDOUT;\r
- return MT_EINTR;\r
-}\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_mutex_acq_ui\r
- *\r
- * Description:\r
- * acquire the mutex\r
- *\r
- * Parameters: \r
- * mtx_p(IN) pointer to mutex\r
- *\r
- * Returns:\r
- * MT_OK - mutex acquired\r
- *\r
-******************************************************************************/\r
-void MOSAL_mutex_acq_ui(MOSAL_mutex_t *mtx_p)\r
-{\r
- NTSTATUS status = STATUS_SUCCESS;\r
- LARGE_INTEGER timeout = { 0, 0 };\r
- KPROCESSOR_MODE pcs_mode = ExGetPreviousMode();\r
-\r
- ASSERT(KeGetCurrentIrql() < DISPATCH_LEVEL);\r
- while (1) {\r
- #ifdef USE_KMUTEX\r
- status = KeWaitForSingleObject( &mtx_p->mutex, Executive, pcs_mode, FALSE, NULL );\r
- #else \r
- ExAcquireFastMutex( &mtx_p->mutex );\r
- #endif \r
- if (status == STATUS_SUCCESS)\r
- break;\r
- }\r
-}\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_mutex_acq_to\r
- *\r
- * Description:\r
- * acquire the mutex\r
- *\r
- * Parameters: \r
- * mtx_p(IN) pointer to mutex\r
- * micro_sec(IN) wait period \r
- *\r
- * Returns:\r
- * MT_OK - mutex acquired\r
- * MT_ETIMEDOUT - mutex not acquired out of timeout\r
- * MT_EINTR - mutex not acquired out of some other error\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_mutex_acq_to(MOSAL_mutex_t *mtx_p, MT_size_t micro_sec)\r
-{\r
- NTSTATUS status;\r
- LARGE_INTEGER timeout;\r
- KPROCESSOR_MODE pcs_mode = ExGetPreviousMode();\r
-\r
- timeout.QuadPart = ((int64_t)(u_int64_t)micro_sec) * (-10);\r
-\r
- ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL);\r
- if ( micro_sec == MOSAL_SYNC_TIMEOUT_INFINITE ) \r
- status = KeWaitForSingleObject( &mtx_p->mutex, Executive, pcs_mode, TRUE, NULL );\r
- else\r
- status = KeWaitForSingleObject( &mtx_p->mutex, Executive, pcs_mode, TRUE, &timeout );\r
- if (status == STATUS_SUCCESS)\r
- return MT_OK;\r
- if (status == STATUS_TIMEOUT)\r
- return MT_ETIMEDOUT;\r
- return MT_EINTR;\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_mutex_rel\r
- *\r
- * Description:\r
- * release the mutex\r
- *\r
- * Parameters: \r
- * mtx_p(IN) pointer to mutex\r
- *\r
- * Returns:\r
- * N/A\r
- *\r
- ******************************************************************************/\r
-void MOSAL_mutex_rel(MOSAL_mutex_t *mtx_p)\r
-{\r
- #ifdef USE_KMUTEX\r
- ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL);\r
- KeReleaseMutex( &mtx_p->mutex, FALSE );\r
- #else\r
- ASSERT(KeGetCurrentIrql() == APC_LEVEL);\r
- ExReleaseFastMutex( &mtx_p->mutex );\r
- #endif\r
-} \r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_mutex_get_stat\r
- *\r
- * Description:\r
- * get mutex status\r
- *\r
- * Parameters: \r
- * mtx_p(IN) pointer to mutex\r
- *\r
- * Returns:\r
- * If the return value is one, the state of the mutex object is signaled\r
- *\r
- ******************************************************************************/\r
-#if WINVER == 0x500\r
-/*\r
- * The ntddk.h header file in the 3790 DDK for Win2k references but doesn't\r
- * define this function.\r
- */\r
-NTKERNELAPI\r
-LONG\r
-KeReadStateMutant(\r
- IN PRKMUTEX Mutex\r
- );\r
-#endif\r
-\r
-LONG MOSAL_mutex_get_stat(MOSAL_mutex_t *mtx_p)\r
-{\r
- #ifdef USE_KMUTEX\r
- ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL);\r
- return KeReadStateMutex( &mtx_p->mutex );\r
- #else\r
- ASSERT(FALSE);\r
- return 0;\r
- #endif\r
-} \r
-\r
-\r
-////////////////////////////////////////////////////////////////////////////////\r
-// Delay of execution\r
-////////////////////////////////////////////////////////////////////////////////\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_delay_execution\r
- *\r
- * Description:\r
- * delay execution of this control path for a the specified time period. Note\r
- * that in some implementaions it performs busy wait.\r
- *\r
- * Parameters: \r
- * time_micro(IN) required delay time in microseconds\r
- *\r
- * Returns:\r
- * N/A\r
- *\r
- ******************************************************************************/\r
-void MOSAL_delay_execution(u_int32_t time_micro)\r
-{\r
- LARGE_INTEGER timeout;\r
- timeout.QuadPart = ((int64_t)(u_int64_t)time_micro) * (-10);\r
- KeDelayExecutionThread( KernelMode, FALSE, &timeout );\r
-}\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_usleep:\r
- *\r
- * Description:\r
- * Suspends the execution of the current process for the given number of\r
- * microseconds. The function guarantees to go to sleep for at least usec\r
- * microseconds\r
- * Parameters: \r
- * usec(IN) number of micro seconds to sleep\r
- *\r
- * Returns:\r
- * MT_OK\r
- * MT_EINTR signal received\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_usleep(u_int32_t usec)\r
-{\r
- LARGE_INTEGER timeout = RtlEnlargedIntegerMultiply( - 10, usec );\r
- NTSTATUS status = KeDelayExecutionThread( KernelMode, TRUE, &timeout );\r
- if (status == STATUS_SUCCESS)\r
- return MT_OK;\r
- return MT_EINTR;\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_usleep_ui:\r
- *\r
- * Description:\r
- * Suspends the execution of the current process for the given number of\r
- * microseconds. The function guarantees to go to sleep for at least usec\r
- * microseconds. The function is non interruptile\r
- * Parameters: \r
- * usec(IN) number of micro seconds to sleep\r
- *\r
- * Returns: void\r
- *\r
- ******************************************************************************/\r
-void MOSAL_usleep_ui(u_int32_t usec)\r
-{\r
- LARGE_INTEGER timeout = RtlEnlargedIntegerMultiply( - 10, usec );\r
- KeDelayExecutionThread( KernelMode, FALSE, &timeout );\r
-}\r
-\r
-\r
-/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\r
- * \r
- * SpinLocks\r
- *\r
- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_spinlock_init\r
- *\r
- * Description:\r
- * initialize spinlock\r
- *\r
- * Parameters: \r
- * sp(IN) MOSAL_spinlock_t*\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_spinlock_init(MOSAL_spinlock_t *sp)\r
-{\r
- KeInitializeSpinLock(&sp->lock);\r
- return MT_OK;\r
-}\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_SYNC_IMP_H\r
-#define H_MOSAL_SYNC_IMP_H\r
-\r
-/* spinlock */\r
-#ifdef __KERNEL__\r
-\r
-#ifdef USE_TRACE\r
-/* function names */\r
-#define FUNC_MOSAL_spinlock_lock 1\r
-#define FUNC_MOSAL_spinlock_unlock 2\r
-#define FUNC_MOSAL_spinlock_irq_lock 3\r
-\r
-void MOSAL_trace_log(char who, char value1, char value2, char value3);\r
-\r
-#define TRACE_LOG(who,val1,val2,val3) MOSAL_trace_log(who,val1,val2,val3)\r
-#else\r
-#define TRACE_LOG(who,val1,val2,val3) \r
-#endif\r
-\r
-\r
-/* sync object */\r
-struct MOSAL_syncobj {\r
- KEVENT event; \r
-};\r
-\r
-/* semaphore */\r
-struct MOSAL_semaphore {\r
- KSEMAPHORE sem;\r
-};\r
-\r
-/* mutex */\r
-struct MOSAL_mutex {\r
-#ifdef USE_KMUTEX\r
- KMUTEX mutex;\r
-#else\r
- FAST_MUTEX mutex;\r
-#endif\r
-};\r
-\r
-\r
-struct MOSAL_spinlock\r
-{\r
- KSPIN_LOCK lock;\r
- u_int32_t flags;\r
- KIRQL irql;\r
-};\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_spinlock_lock\r
- *\r
- * Description:\r
- * acquire spinlock (after elevating IRQL)\r
- *\r
- * Parameters: \r
- * sp(IN) MOSAL_spinlock_t*\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-static _inline call_result_t MOSAL_spinlock_lock(struct MOSAL_spinlock *sp)\r
-{ \r
-#ifdef USE_TRACE\r
- KIRQL irql = KeGetCurrentIrql();\r
-#endif\r
- ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL);\r
- KeAcquireSpinLock(&sp->lock, &sp->irql);\r
- TRACE_LOG(FUNC_MOSAL_spinlock_lock, irql,KeGetCurrentIrql(),0);\r
- return(MT_OK);\r
-}\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_spinlock_unlock\r
- *\r
- * Description:\r
- * release spinlock (and decrease IRQL)\r
- *\r
- * Parameters: \r
- * sp(IN) MOSAL_spinlock_t*\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-static _inline void MOSAL_spinlock_unlock(struct MOSAL_spinlock *sp)\r
-{\r
-#ifdef USE_TRACE\r
- KIRQL irql = KeGetCurrentIrql();\r
-#endif\r
-#ifdef USE_SPINLOCK_SANITY_CHECKS\r
-#ifdef SYNCH_LEVEL\r
- /* sanity check */\r
- if (sp->irql == SYNCH_LEVEL) {\r
- DbgPrint( "MOSAL_spinlock_unlock: IRQLs: current %d, new %d \n", KeGetCurrentIrql(), sp->irql);\r
- }\r
-#endif \r
-#endif \r
- \r
- TRACE_LOG(FUNC_MOSAL_spinlock_unlock, irql, sp->irql,0);\r
- KeReleaseSpinLock(&sp->lock, sp->irql );\r
-}\r
-\r
-NTKERNELAPI\r
-KIRQL\r
-FASTCALL\r
-KeAcquireSpinLockRaiseToSynch (\r
- PKSPIN_LOCK SpinLock\r
- );\r
-\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_spinlock_irq_lock\r
- *\r
- * Description:\r
- * acquire spinlock in ISR \r
- *\r
- * Parameters: \r
- * sp(IN) MOSAL_spinlock_t*\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-static _inline call_result_t MOSAL_spinlock_irq_lock( struct MOSAL_spinlock *sp )\r
-{\r
-#ifdef USE_TRACE\r
- KIRQL irql = KeGetCurrentIrql();\r
-#endif\r
- sp->irql = KeAcquireSpinLockRaiseToSynch(&sp->lock);\r
-#ifdef USE_SPINLOCK_SANITY_CHECKS\r
-#ifdef SYNCH_LEVEL\r
- /* sanity */\r
- if (sp->irql == SYNCH_LEVEL) {\r
- DbgPrint( "MOSAL_spinlock_irq_lock: prev IRQL %d\n", sp->irql);\r
- }\r
-#endif \r
-#endif \r
- TRACE_LOG(FUNC_MOSAL_spinlock_irq_lock, irql, KeGetCurrentIrql(), 0);\r
- return(MT_OK);\r
-}\r
-\r
-#define MOSAL_spinlock_dpc_lock MOSAL_spinlock_lock\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_mutex_get_stat\r
- *\r
- * Description:\r
- * get mutex status\r
- *\r
- * Parameters: \r
- * mtx_p(IN) pointer to mutex\r
- *\r
- * Returns:\r
- * If the return value is one, the state of the mutex object is signaled\r
- *\r
- ******************************************************************************/\r
-LONG MOSAL_mutex_get_stat(struct MOSAL_mutex *mtx_p);\r
-\r
-#else\r
-/* user mode */\r
-\r
-\r
-/* sync object - TBD */\r
-struct MOSAL_syncobj {\r
- HANDLE event;\r
-};\r
-\r
-/* semaphore - TBD */\r
-struct MOSAL_semaphore {\r
- HANDLE sem;\r
-};\r
-\r
-/* mutex object - TBD */\r
-struct MOSAL_mutex {\r
- HANDLE mutex;\r
-};\r
-\r
-/* spinlock */\r
-typedef cl_spinlock_t MOSAL_spinlock_t;\r
-#define UL_SPIN_LOCK_UNLOCKED 1\r
-\r
-/******************************************************************************\r
- * Function (user-mode only):\r
- * MOSAL_spinlock_lock\r
- *\r
- * Description:\r
- * acquire spinlock (after elevating IRQL)\r
- *\r
- * Parameters: \r
- * sp(IN) MOSAL_spinlock_t*\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-static _inline call_result_t priv_spinlock_lock(MOSAL_spinlock_t *sp)\r
-{\r
- cl_spinlock_acquire (sp );\r
- return MT_OK;\r
-}\r
-\r
-static _inline call_result_t MOSAL_spinlock_lock(MOSAL_spinlock_t *sp)\r
-{\r
- return priv_spinlock_lock(sp);\r
-}\r
-\r
-/******************************************************************************\r
- * Function (user-mode only):\r
- * MOSAL_spinlock_unlock\r
- *\r
- * Description:\r
- * release spinlock (and decrease IRQL)\r
- *\r
- * Parameters: \r
- * sp(IN) MOSAL_spinlock_t*\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-static _inline void MOSAL_spinlock_unlock(MOSAL_spinlock_t *sp)\r
-{\r
- cl_spinlock_release( sp);\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function (user-mode only):\r
- * MOSAL_spinlock_irq_lock\r
- *\r
- * Description:\r
- * acquire spinlock in ISR (no change of IRQL)\r
- *\r
- * Parameters: \r
- * sp(IN) MOSAL_spinlock_t*\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-static _inline call_result_t MOSAL_spinlock_irq_lock( MOSAL_spinlock_t *sp )\r
-{\r
- return priv_spinlock_lock(sp);\r
-}\r
-\r
-#define MOSAL_spinlock_dpc_lock MOSAL_spinlock_lock\r
-\r
-#endif\r
-\r
-typedef struct MOSAL_mutex MOSAL_mutex_t;\r
-typedef struct MOSAL_syncobj MOSAL_syncobj_t;\r
-typedef struct MOSAL_semaphore MOSAL_semaphore_t;\r
-\r
-#if defined(__KERNEL__)\r
-typedef struct MOSAL_spinlock MOSAL_spinlock_t;\r
-#endif\r
-\r
-#define MOSAL_UL_SPINLOCK_STATIC_INIT {UL_SPIN_LOCK_UNLOCKED}\r
-\r
-call_result_t MOSAL_mutex_acq_to(MOSAL_mutex_t *mtx_p, MT_size_t micro_sec);\r
-\r
-/* "free" functions are dummy for both kernel and user space under linux*/\r
-static inline call_result_t MOSAL_syncobj_free(MOSAL_syncobj_t *obj_p)\r
-{\r
- UNREFERENCED_PARAMETER( obj_p );\r
- return MT_OK;\r
-}\r
-\r
-static inline call_result_t MOSAL_sem_free(MOSAL_semaphore_t *sem_p)\r
-{\r
- UNREFERENCED_PARAMETER( sem_p );\r
- return MT_OK;\r
-}\r
-\r
-static inline call_result_t MOSAL_mutex_free(MOSAL_mutex_t *mtx_p)\r
-{\r
- UNREFERENCED_PARAMETER( mtx_p );\r
- return MT_OK;\r
-}\r
-\r
-#define MOSAL_SYNC_TIMEOUT_INFINITE 0\r
-\r
-#endif /* H_MOSAL_SYNC_IMP_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_SYNC_PRIV_H\r
-#define H_MOSAL_SYNC_PRIV_H\r
-\r
-#include "mosal_sync_imp.h"\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "mosal_priv.h"\r
-\r
-#define THREAD_WAIT_FOR_EXIT 0x80000000\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_thread_start \r
- *\r
- * Description:\r
- * create a tread and run a t-function in its context\r
- *\r
- * Parameters: \r
- * mto_p(IN) pointer to MOSAL thread object\r
- * flags(IN) // flags for thread creation \r
- * mtf(IN) t-function \r
- * mtf_ctx(IN) t-function context\r
- *\r
- * Returns:\r
- * MT_OK - thread started; for blocking mode - t-function is running;\r
- * MT_EAGAIN - for blocking mode - timeout; thread hasn't started yet; \r
- * other - error;\r
- *\r
- ******************************************************************************/\r
-static void ThreadProc(void * lpParameter )\r
-{\r
- MOSAL_thread_t *mto_p = (MOSAL_thread_t *)lpParameter; \r
- mto_p->res = (u_int32_t)mto_p->func(mto_p->func_ctx);\r
- MOSAL_syncobj_signal( &mto_p->sync );\r
- mto_p->th = 0;\r
- PsTerminateSystemThread(mto_p->res);\r
-}\r
-\r
-call_result_t MOSAL_thread_start( \r
- MOSAL_thread_t *mto_p, // pointer to MOSAL thread object\r
- u_int32_t flags, // flags for thread creation \r
- MOSAL_thread_func_t mtf, // t-function name \r
- void *mtf_ctx // t-function context (optionally) \r
- )\r
-{\r
- NTSTATUS status;\r
- \r
- // sanity checks\r
- if (mtf == NULL)\r
- return MT_EINVAL;\r
-\r
- // init thread object\r
- mto_p->func = mtf;\r
- mto_p->func_ctx = mtf_ctx;\r
- mto_p->flags = flags;\r
- MOSAL_syncobj_init( &mto_p->sync );\r
-\r
- // create and run the thread\r
- ASSERT(KeGetCurrentIrql() == PASSIVE_LEVEL);\r
- status = PsCreateSystemThread( &mto_p->th, (ACCESS_MASK)0L , NULL, NULL, NULL, ThreadProc, mto_p );\r
- if (status != STATUS_SUCCESS)\r
- return MT_ERROR;\r
- \r
- return status;\r
-} \r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_thread_kill \r
- *\r
- * Description:\r
- * terminate the tread brutally\r
- *\r
- * Parameters: \r
- * mto_p(IN) pointer to MOSAL thread object\r
- *\r
- * Returns:\r
- * MT_OK - thread terminated\r
- * MT_ERROR - a failure on thread termination\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_thread_kill( \r
- MOSAL_thread_t *mto_p // pointer to MOSAL thread object\r
- )\r
- {\r
- /* didn't find a way to perform that */\r
- return MT_ERROR;\r
- }\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_thread_wait_for_exit \r
- *\r
- * Description:\r
- * create a tread and run a t-function in its context\r
- *\r
- * Parameters: \r
- * mto_p(IN) pointer to MOSAL thread object\r
- * micro_sec(IN) timeout in mcs; MOSAL_THREAD_WAIT_FOREVER means ENDLESS\r
- * exit_code(OUT) return code of the thread\r
- *\r
- * Returns:\r
- * MT_OK - thread started; for blocking mode - t-function is running;\r
- * MT_EAGAIN - for blocking mode - timeout; thread hasn't started yet; \r
- * other - error;\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_thread_wait_for_exit( \r
- MOSAL_thread_t *mto_p, // pointer to MOSAL thread object\r
- MT_size_t micro_sec, // timeout in mcs; MOSAL_THREAD_WAIT_FOREVER means ENDLESS \r
- u_int32_t *exit_code // return code of the thread\r
- )\r
-{\r
- call_result_t status;\r
- mto_p->flags |= THREAD_WAIT_FOR_EXIT;\r
- status = MOSAL_syncobj_waiton(&mto_p->sync, micro_sec);\r
- if (exit_code != NULL) {\r
- if (status == MT_OK )\r
- *exit_code = mto_p->res;\r
- else\r
- *exit_code = status;\r
- }\r
- return status;\r
-}\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_thread_set_name \r
- *\r
- * Description:\r
- * set thread name\r
- *\r
- * Parameters: \r
- * mto_p(IN) pointer to MOSAL thread object\r
- * name(IN) thread name\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
- void MOSAL_thread_set_name(\r
- MOSAL_thread_t *mto_p, // pointer to MOSAL thread object\r
- char *name // thread name\r
- )\r
-{\r
-}\r
-\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_THREAD_IMP_H\r
-#define H_MOSAL_THREAD_IMP_H\r
-\r
-#define MOSAL_KTHREAD_CLONE_FLAGS 0\r
-\r
-/* MOSAL thread object */\r
-struct MOSAL_thread;\r
-typedef struct MOSAL_thread MOSAL_thread_t;\r
-\r
-#ifndef __KERNEL__\r
-typedef void* (*MOSAL_thread_func_t)( void * );\r
-#else\r
-typedef int (*MOSAL_thread_func_t)( void * );\r
-#endif\r
-\r
-/* MOSAL thread object implementation */\r
-struct MOSAL_thread {\r
- HANDLE th; /* thread handle */\r
- MOSAL_thread_func_t func; /* t-function */\r
- void * func_ctx; /* t-function context */\r
- u_int32_t flags; /* flags for thread creation */\r
- u_int32_t res; /* return code */\r
- MOSAL_syncobj_t sync; /* sync object */\r
-};\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_thread_is_in_work \r
- *\r
- * Description:\r
- * check, whether thread is working (i.e hasn't exited yet)\r
- *\r
- * Parameters: \r
- * mto_p(IN) pointer to MOSAL thread object\r
- *\r
- * Returns:\r
- * TRUE - in work\r
- * FALSE - exited \r
- *\r
- ******************************************************************************/\r
-static _inline MT_bool MOSAL_thread_is_in_work( \r
- MOSAL_thread_t *mto_p /* pointer to MOSAL thread object */\r
- )\r
-{\r
- return (MT_bool)(mto_p->th != 0);\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function:\r
- * MOSAL_thread_wait_for_exit \r
- *\r
- * Description:\r
- * wait for a target thread to exit\r
- *\r
- * Parameters: \r
- * mto_p(IN) pointer to MOSAL thread object\r
- * micro_sec(IN) timeout in mcs; MOSAL_THREAD_WAIT_FOREVER means ENDLESS\r
- * exit_code(OUT) return code of the thread\r
- *\r
- * Returns:\r
- * MT_OK - thread started; for blocking mode - t-function is running;\r
- * MT_EAGAIN - for blocking mode - timeout; thread hasn't started yet; \r
- * other - error;\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_thread_wait_for_exit( \r
- MOSAL_thread_t *mto_p, /* pointer to MOSAL thread object */\r
- MT_size_t micro_sec, /* timeout in mcs; MOSAL_THREAD_WAIT_FOREVER means ENDLESS */\r
- u_int32_t *exit_code /* return code of the thread */\r
- );\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_thread_wait_for_term \r
- *\r
- * Description:\r
- * wait till the target thread exits\r
- *\r
- * Parameters: \r
- * mto_p(IN) pointer to MOSAL thread object\r
- * exit_code(OUT) return code of the thread\r
- *\r
- * Returns:\r
- * MT_OK - thread started; for blocking mode - t-function is running;\r
- * MT_EAGAIN - thread hasn't started yet; \r
- * other - error;\r
- *\r
- ******************************************************************************/\r
-#define MOSAL_thread_wait_for_term(mto_p,exit_code) MOSAL_thread_wait_for_exit(mto_p,MOSAL_SYNC_TIMEOUT_INFINITE,exit_code)\r
-\r
-#ifdef __KERNEL__\r
-\r
-\r
-/*\r
- * cloning flags (taken from sched.h)\r
- */\r
-#define MOSAL_KTHREAD_CSIGNAL 0 /* signal mask to be sent at exit */\r
-#define MOSAL_KTHREAD_CLONE_VM 0 /* set if VM shared between processes */\r
-#define MOSAL_KTHREAD_CLONE_FS 0 /* set if fs info shared between processes */\r
-#define MOSAL_KTHREAD_CLONE_FILES 0 /* set if open files shared between processes */\r
-#define MOSAL_KTHREAD_CLONE_SIGHAND 0 /* set if signal handlers and blocked signals shared */\r
-#define MOSAL_KTHREAD_CLONE_PID 0 /* set if pid shared */\r
-#define MOSAL_KTHREAD_CLONE_PTRACE 0 /* set if we want to let tracing continue on the child too */\r
-#define MOSAL_KTHREAD_CLONE_VFORK 0 /* set if the parent wants the child to wake it up on mm_release */\r
-#define MOSAL_KTHREAD_CLONE_PARENT 0 /* set if we want to have the same parent as the cloner */\r
-#define MOSAL_KTHREAD_CLONE_THREAD 0 /* Same thread group? */\r
-#define MOSAL_KTHREAD_CLONE_NEWNS 0 /* New namespace group? */\r
-\r
-#define MOSAL_KTHREAD_CLONE_SIGNAL 0\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_thread_set_name \r
- *\r
- * Description:\r
- * set thread name\r
- *\r
- * Parameters: \r
- * mto_p(IN) pointer to MOSAL thread object\r
- * name(IN) thread name\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
- void MOSAL_thread_set_name(\r
- MOSAL_thread_t *mto_p, /* pointer to MOSAL thread object */\r
- char *name /* thread name */\r
- );\r
-\r
-\r
-#endif\r
-\r
-#endif /* H_MOSAL_SYNC_IMP_H */\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "mosal_priv.h"\r
-\r
-\r
-\r
-//\r
-// externals\r
-//\r
-// TAVOR\r
-extern MOSAL_dev_t MOSAL_dev_db[MOSAL_MAXDEV]; \r
-\r
-//\r
-// Restrictrions\r
-//\r
-#define MAX_SIMULT_ISRS 100 // number of pending ISRs in DPC context queues\r
-\r
-//\r
-// Static data\r
-//\r
-LIST_ENTRY ctx_lifo;\r
-void * ctx_array = NULL;\r
-\r
-////////////////////////////////////////////////////////////////////////////////\r
-// ISR functions\r
-////////////////////////////////////////////////////////////////////////////////\r
-\r
-/******************************************************************************\r
- * Function: general_isr\r
- *\r
- * Description: device ISR handler\r
- *\r
- * Parameters:\r
- * pi_pIntObject........... Interrupt Object\r
- * pi_pContext............. My device context\r
- *\r
- * Returns:\r
- *\r
- *****************************************************************************/\r
-static BOOLEAN \r
-generic_isr(\r
- PKINTERRUPT pi_pIntObject, \r
- PVOID pi_pContext\r
- )\r
-{ /* general_isr */\r
- MOSAL_ISR_t * isr_p = (MOSAL_ISR_t *)pi_pContext;\r
-\r
- return( isr_p->func(isr_p->ctx, NULL, pi_pIntObject ) );\r
-\r
-} /* general_isr */\r
-\r
-\r
-/*\r
- * Interrupt handler registration\r
- */\r
-call_result_t MOSAL_ISR_set(\r
- MOSAL_ISR_t * isr_p,\r
- MOSAL_ISR_func_t handler,\r
- MOSAL_IRQ_ID_t irq,\r
- char * name,\r
- MT_ulong_ptr_t ctx\r
- )\r
-{\r
- int name_sz = (int)strlen(name) + 1;\r
- MOSAL_dev_t * dev_p = find_device_by_name(name);\r
- NTSTATUS status;\r
- \r
- // allocate memory\r
- isr_p->name = TNVMALLOC( char, name_sz );\r
- if (!isr_p->name)\r
- return MT_EMALLOC;\r
- \r
- // store parameters in the object\r
- isr_p->func = handler;\r
- isr_p->irq = irq;\r
- isr_p->ctx = ctx;\r
- RtlCopyMemory(isr_p->name, name, name_sz);\r
-\r
- /* connect interrupt */\r
- dev_p->int_object_p = NULL;\r
- status = IoConnectInterrupt(\r
- &isr_p->int_object_p, /* InterruptObject */\r
- (PKSERVICE_ROUTINE) generic_isr, /* ISR */ \r
- (PVOID)isr_p, /* ISR context */\r
- &dev_p->isr_lock, /* spinlock */\r
- irq, /* interrupt vector */\r
- dev_p->irql, /* IRQL */\r
- dev_p->irql, /* Synchronize IRQL */\r
- dev_p->int_mode, /* interrupt type: LATCHED or LEVEL */\r
- dev_p->int_shared, /* vector shared or not */\r
- dev_p->affinity, /* interrupt affinity */ \r
- FALSE /* whether to save Float registers */\r
- );\r
-\r
- if (!NT_SUCCESS(status))\r
- return MT_ERROR; /* failed to connect interrupt */\r
- else\r
- return MT_OK;\r
-}\r
-\r
-/*\r
- * Interrupt handler registration\r
- */\r
-call_result_t MOSAL_ISR_unset(\r
- MOSAL_ISR_t * isr_p\r
- )\r
-{\r
- // free memory\r
- if ( isr_p->name ) \r
- VFREE( isr_p->name );\r
- \r
- /* disconnect interrupt */\r
- if (isr_p->int_object_p != NULL)\r
- {\r
- IoDisconnectInterrupt( isr_p->int_object_p );\r
- memset( isr_p, 0, sizeof(MOSAL_ISR_t) ); \r
- }\r
-\r
- return MT_OK;\r
-}\r
-\r
-static BOOLEAN \r
-general_isr(\r
- PKINTERRUPT pi_pIntObject, \r
- PVOID pi_pContext\r
- )\r
-{ /* general_isr */\r
- MOSAL_dev_t *dev_p = (MOSAL_dev_t *)pi_pContext;\r
-\r
- /* call device handler (in fact, it's general MDHAL handler */ \r
-#ifdef HANDLE_INTERRUTS_AT_DPC\r
- dev_p->thandler((MT_ulong_ptr_t)dev_p->dev_id, (void*)dev_p, NULL );\r
-#else\r
- dev_p->ghandler(dev_p->irq_num, dev_p->dev_id, NULL );\r
-#endif \r
-\r
- return TRUE;\r
-\r
-} /* general_isr */\r
-\r
-\r
-call_result_t MOSAL_set_intr_handler(intr_handler_t handler, MOSAL_IRQ_ID_t irq, \r
-char *name, void* dev_id)\r
-{\r
- MOSAL_dev_t * dev_p = find_device_by_name(name);\r
- NTSTATUS status;\r
-\r
- /* get pointer to device object */\r
- if (dev_p == NULL)\r
- return MT_ENODEV;\r
-\r
- /* store MDHAL interrupt context */\r
- dev_p->ghandler = handler;\r
- dev_p->irq_num = irq;\r
- dev_p->dev_id = dev_id;\r
-\r
- /* connect interrupt */\r
- dev_p->int_object_p = NULL;\r
- status = IoConnectInterrupt(\r
- &dev_p->int_object_p, /* InterruptObject */\r
- (PKSERVICE_ROUTINE) general_isr, /* ISR */ \r
- (PVOID)dev_p, /* ISR context */\r
- &dev_p->isr_lock, /* spinlock */\r
- irq, /* interrupt vector */\r
- dev_p->irql, /* IRQL */\r
- dev_p->irql, /* Synchronize IRQL */\r
- dev_p->int_mode, /* interrupt type: LATCHED or LEVEL */\r
- dev_p->int_shared, /* vector shared or not */\r
- dev_p->affinity, /* interrupt affinity */ \r
- FALSE /* whether to save Float registers */\r
- );\r
-\r
- if (!NT_SUCCESS(status))\r
- return MT_ERROR; /* failed to connect interrupt */\r
- else\r
- return MT_OK;\r
-}\r
-\r
-call_result_t MOSAL_unset_intr_handler(intr_handler_t handler,\r
- MOSAL_IRQ_ID_t irq,\r
- void* dev_id)\r
-{\r
- MOSAL_dev_t * dev_p = &MOSAL_dev_db[0];\r
- int i;\r
-\r
- /* get pointer to device object */\r
- for (i=0; i<MOSAL_MAXDEV; i++, dev_p++)\r
- {\r
- if (dev_p->ghandler == handler && dev_p->irq_num == irq && dev_p->dev_id == dev_id)\r
- break;\r
- }\r
- if (i >= MOSAL_MAXDEV)\r
- return MT_ENODEV;\r
-\r
- /* disconnect interrupt */\r
- if (dev_p->int_object_p != NULL)\r
- {\r
- IoDisconnectInterrupt( dev_p->int_object_p );\r
- dev_p->int_object_p = NULL;\r
- dev_p->thandler = NULL;\r
- dev_p->ghandler = NULL;\r
- dev_p->irq_num = 0;\r
- dev_p->dev_id = 0;\r
- }\r
-\r
- return MT_OK;\r
-}\r
-\r
-\r
-////////////////////////////////////////////////////////////////////////////////\r
-// DPC functions\r
-////////////////////////////////////////////////////////////////////////////////\r
-\r
-/******************************************************************************\r
- * Function:\r
- * deinit_dpc\r
- *\r
- * Description:\r
- * deinit all stuff, related to DPC handling\r
- *\r
- * Parameters:\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-\r
-void deinit_dpc()\r
-{\r
-#ifdef SUPPORT_MULTIPLE_CTX \r
- // release DPC contexts\r
- if (ctx_array != NULL)\r
- ExFreePool( ctx_array );\r
-#endif \r
-}\r
-\r
-/******************************************************************************\r
- * Function:\r
- * init_dpc\r
- *\r
- * Description:\r
- * init all stuff, related to DPC handling\r
- *\r
- * Parameters:\r
- *\r
- * Returns:\r
- * MT_OK - OK, error - otherwise\r
- *\r
- ******************************************************************************/\r
-\r
-call_result_t init_dpc()\r
-{\r
-#ifdef SUPPORT_MULTIPLE_CTX \r
- int i;\r
- LDPC_CONTEXT_t * p; \r
-\r
- // init static data\r
- InitializeListHead( &ctx_lifo );\r
- ctx_array = NULL;\r
- \r
- // allocate array of DPC contexts\r
- p = (LDPC_CONTEXT_t *)ExAllocatePoolWithTag( NonPagedPool, \r
- sizeof(LDPC_CONTEXT_t) * MAX_SIMULT_ISRS, ' cpd' );\r
- if (p == NULL)\r
- return MT_ENORSC;\r
- ctx_array = (PVOID)p;\r
- \r
- // create LIFO list of DPC contexts\r
- for (i=0; i < MAX_SIMULT_ISRS; i++, p++)\r
- {\r
- InsertTailList( &ctx_lifo, &p->link );\r
- }\r
-#endif\r
- return MT_OK;\r
-}\r
-\r
-/******************************************************************************\r
- * Function:\r
- * generic_dpc\r
- *\r
- * Description:\r
- * calls user platform-independent DPC for all requests, pending the same MOSAL DPC object\r
- *\r
- * Parameters:\r
- * Dpc - Win2K DPC object\r
- * DeferredContext - it's context\r
- * SystemArgument1 - context, relayed by ISR, inserting DPC; not in use\r
- * SystemArgument2 - context, relayed by ISR, inserting DPC; not in use\r
- *\r
- * Returns:\r
- *\r
- * Notes:\r
- * Before inserting DPC ISR must add its context parameters to the MOSAL DPC\r
- * object's context chain \r
- *\r
- ******************************************************************************/\r
-BOOLEAN get_dpc_ctx( PVOID SynchronizeContext )\r
-{\r
-#ifdef SUPPORT_MULTIPLE_CTX \r
- MOSAL_DPC_t *d = (MOSAL_DPC_t *)SynchronizeContext;\r
- d->dpc_ctx_p = (LDPC_CONTEXT_t *)RemoveHeadList( &d->ctx_head );\r
-#endif \r
- return TRUE;\r
-}\r
-\r
-BOOLEAN free_dpc_ctx( PVOID SynchronizeContext )\r
-{\r
-#ifdef SUPPORT_MULTIPLE_CTX \r
- LDPC_CONTEXT_t *p = (LDPC_CONTEXT_t *)SynchronizeContext;\r
- InsertTailList( &ctx_lifo, &p->link );\r
-#endif \r
- return TRUE;\r
-}\r
-\r
-static VOID generic_dpc(\r
- IN PKDPC Dpc,\r
- IN PVOID DeferredContext,\r
- IN PVOID SystemArgument1,\r
- IN PVOID SystemArgument2\r
- )\r
-{\r
- MOSAL_DPC_t *d = (MOSAL_DPC_t *)DeferredContext;\r
-\r
- if ( d->type == MOSAL_SINGLE_CTX)\r
- { /* the DPC has no race conditions */\r
-\r
- // fill DPC context\r
- d->dpc_ctx.isr_ctx1 = SystemArgument1;\r
- d->dpc_ctx.isr_ctx2 = SystemArgument2;\r
- \r
- // call user's DPC\r
- if (d->func)\r
- (d->func)(&d->dpc_ctx);\r
-\r
- } /* the DPC has no race conditions */\r
-\r
-\r
- else\r
-\r
- // if it is MOSAL_NO_CTX DPC - all is simple\r
- if ( d->type == MOSAL_NO_CTX)\r
- { /* the DPC has no race conditions */\r
-\r
- // call user's DPC\r
- if (d->func)\r
- (d->func)(&d->dpc_ctx);\r
-\r
- } /* the DPC has no race conditions */\r
- \r
- // if it is MOSAL_NO_CTX DPC - all is simple\r
- \r
-#ifdef SUPPORT_MULTIPLE_CTX \r
-\r
- else\r
- /* !!! Pay attention:\r
- In order to use this part, one has to use\r
- MOSAL_DPC_schedule_ctx( user_dpc_ctx, whatever, int_object_p );\r
- */\r
-\r
- { /* the DPC can have race conditions with ISRs and itself */\r
- PKINTERRUPT int_object_p = (PKINTERRUPT)SystemArgument2; \r
- \r
- //\r
- // One DPC can be inserted several times by the same or different ISR\r
- // Because only one DPC can stay in queue, the ISR would first link the relayed to context\r
- // to the DPC context queue and then would try to enqueue the DPC\r
- //\r
- while (1)\r
- { /* handle all the requests to this DPC */\r
- \r
- // the requests are added by ISRs with guarded routines\r
- // so the below removing is to be guarded against DPC-ISR race\r
- // Note that the queue can be empty in case when the same DPC was scheduled on 2\r
- // processors and the first one has already emptied the queue !\r
- // Note also that 2 DPCs can run simultaneously on 2 processors \r
- // over the same MOSAL_DPC object ! In this case the same user DPC can be simultaneously\r
- // called with 2 different contexts\r
-\r
- // get first DPC context\r
- KeSynchronizeExecution( int_object_p, get_dpc_ctx, (PVOID)d ); \r
- if (d->ldpc_ctx_p == NULL)\r
- break;\r
- \r
- // call user's DPC\r
- if (d->func)\r
- (d->func)(&d->ldpc_ctx_p->dpc_ctx);\r
- \r
- // release the request element\r
- KeSynchronizeExecution( int_object_p, free_dpc_ctx, (PVOID)d->ldpc_ctx_p ); \r
- \r
- } /* handle all the requests to this DPC */\r
- \r
- } /* the DPC can have race conditions with ISRs and itself */ \r
- \r
-#endif \r
-}\r
-\r
-\r
- /******************************************************************************\r
- * Function:\r
- * MOSAL_DPC_add_ctx\r
- *\r
- * Description:\r
- * add DPC request context to a MOSAL DPC object\r
- *\r
- * Parameters:\r
- * d - MOSAL DPC object\r
- * ctx1 - context, relayed by ISR, inserting DPC;\r
- * ctx2 - context, relayed by ISR, inserting DPC; \r
- *\r
- * Returns:\r
- * MT_ENORSC - if no ctx structures\r
- * MT_OK - otherwise\r
- *\r
- * Notes:\r
- * A helper routine for ISR, inserting DPC \r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_DPC_add_ctx(MOSAL_DPC_t *d, PVOID ctx1, PVOID ctx2)\r
-{\r
-#ifdef SUPPORT_MULTIPLE_CTX \r
- // allocate a context structure\r
- LDPC_CONTEXT_t *p;\r
- MOSAL_spinlock_irq_lock( &d->lock );\r
- p = (LDPC_CONTEXT_t *)RemoveHeadList( &ctx_lifo);\r
- if (p == NULL) {\r
- MOSAL_spinlock_unlock( &d->lock );\r
- return MT_ENORSC;\r
- }\r
-\r
- // fill the context \r
- p->dpc_ctx.func_ctx = d->dpc_ctx.func_ctx;\r
- p->dpc_ctx.isr_ctx1 = ctx1;\r
- p->dpc_ctx.isr_ctx2 = ctx2;\r
-\r
- // add it to the MOSAL DPC object\r
- InsertTailList( &d->ctx_head, &p->link );\r
- MOSAL_spinlock_unlock( &d->lock );\r
-#endif\r
-\r
- return MT_OK;\r
-}\r
-\r
-\r
- /******************************************************************************\r
- * Function:\r
- * MOSAL_DPC_init\r
- *\r
- * Description:\r
- * init a MOSAL DPC object\r
- *\r
- * Parameters:\r
- * d - MOSAL DPC object\r
- * func - user DPC;\r
- * data - its data;\r
- * type - type of DPC\r
- *\r
- * Returns:\r
- *\r
- * Notes:\r
- * Callers of this routine must be running at IRQL PASSIVE_LEVEL\r
- *\r
- ******************************************************************************/\r
-\r
-void MOSAL_DPC_init(MOSAL_DPC_t *d, MOSAL_DPC_func_t func, MT_ulong_ptr_t func_ctx, MOSAL_DPC_type_t type )\r
-{\r
- // init MOSAL DPC object\r
- d->func = (void *)func;\r
- d->dpc_ctx.func_ctx = func_ctx;\r
- d->type = type;\r
- MOSAL_spinlock_init( &d->lock );\r
- \r
-#ifdef SUPPORT_MULTIPLE_CTX \r
- InitializeListHead( &d->ctx_head );\r
-#endif \r
-\r
- // init OS DPC object with generic DPC instead of user one\r
- KeInitializeDpc( &d->dpc, generic_dpc, (PVOID)d );\r
-}\r
-\r
- /******************************************************************************\r
- * Function:\r
- * MOSAL_DPC_schedule\r
- *\r
- * Description:\r
- * schedule user DPC \r
- *\r
- * Parameters:\r
- * d - MOSAL DPC object\r
- *\r
- * Returns:\r
- *\r
- * Notes:\r
- * Callers of this routine must be running at IRQL PASSIVE_LEVEL\r
- *\r
- ******************************************************************************/\r
-\r
-MT_bool MOSAL_DPC_schedule(MOSAL_DPC_t *d)\r
-{\r
-#if defined( DPC_IS_DIRECT_CALL )\r
- /* call user's DPC directly */\r
- if (d->func)\r
- {\r
- (d->func)(&d->dpc_ctx);\r
- return TRUE;\r
- }\r
- else\r
- {\r
- return FALSE;\r
- }\r
-#else\r
- return KeInsertQueueDpc( &d->dpc, NULL, NULL );\r
-#endif\r
-}\r
-\r
- /******************************************************************************\r
- * Function:\r
- * MOSAL_DPC_schedule_ctx\r
- *\r
- * Description:\r
- * schedule user DPC with relaying a context\r
- *\r
- * Parameters:\r
- * d - MOSAL DPC object\r
- * isr_ctx1 - context, relayed by ISR, inserting DPC;\r
- * isr_ctx2 - context, relayed by ISR, inserting DPC; \r
- *\r
- * Returns:\r
- *\r
- * Notes:\r
- * (Windows) Callers of this routine must be running at IRQL PASSIVE_LEVEL\r
- *\r
- ******************************************************************************/\r
-MT_bool MOSAL_DPC_schedule_ctx(MOSAL_DPC_t *d, void * isr_ctx1, void * isr_ctx2)\r
-{\r
- return KeInsertQueueDpc( &d->dpc, isr_ctx1, isr_ctx2 );\r
-}\r
-\r
-////////////////////////////////////////////////////////////////////////////////\r
-// Timer functions\r
-////////////////////////////////////////////////////////////////////////////////\r
-\r
- /******************************************************************************\r
- * Function:\r
- * MOSAL_timer_init\r
- *\r
- * Description:\r
- * init a MOSAL DPC object\r
- *\r
- * Parameters:\r
- * d - MOSAL timer object\r
- * func - user DPC;\r
- * data - its data;\r
- *\r
- * Returns:\r
- *\r
- * Notes:\r
- * 1. Callers of this routine must be running at IRQL PASSIVE_LEVEL;\r
- * 2. Every timer must use its own MOSAL timer object ! \r
- * 3. Different MOSAL timer objects may use the same DPC function;\r
- *\r
- ******************************************************************************/\r
-\r
-__INLINE__ void MOSAL_timer_init(MOSAL_timer_t *t)\r
-{\r
- // init MOSAL DPC object\r
- MOSAL_DPC_init( &t->mdpc, NULL, (MT_ulong_ptr_t)NULL, MOSAL_NO_CTX);\r
- KeInitializeTimer( &t->timer );\r
-}\r
-\r
- /******************************************************************************\r
- * Function:\r
- * MOSAL_timer_add\r
- *\r
- * Description:\r
- * start timer\r
- *\r
- * Parameters:\r
- * d - MOSAL timer object\r
- * func - user DPC;\r
- * data - its data;\r
- * usecs - interval; 'func' will be called in 'usecs' microseconds\r
- *\r
- * Returns:\r
- *\r
- * Notes:\r
- * Callers of this routine must be running at IRQL <= DISPATCH_LEVEL\r
- *\r
- ******************************************************************************/\r
-\r
-__INLINE__ void MOSAL_timer_add(MOSAL_timer_t *t, MOSAL_DPC_func_t func, MT_ulong_ptr_t data, long usecs)\r
-{\r
- // recalculate timeout value (it is in usecs)\r
- // our tick is a 100 nanosec. Negative value means time, relative to the current\r
- LARGE_INTEGER DueTime;\r
- DueTime.QuadPart = ((int64_t)usecs * (-10));\r
- \r
- // update the DPC object \r
- MOSAL_spinlock_irq_lock( &t->mdpc.lock );\r
- t->mdpc.func = func;\r
- t->mdpc.dpc_ctx.func_ctx = data;\r
- MOSAL_spinlock_unlock( &t->mdpc.lock );\r
-\r
- // start timer\r
- KeSetTimer( &t->timer, DueTime, &t->mdpc.dpc );\r
-}\r
-\r
- /******************************************************************************\r
- * Function:\r
- * MOSAL_timer_del\r
- *\r
- * Description:\r
- * delete timer\r
- *\r
- * Parameters:\r
- * d - MOSAL timer object\r
- *\r
- * Returns:\r
- *\r
- * Notes:\r
- * Callers of this routine must be running at IRQL <= DISPATCH_LEVEL\r
- *\r
- ******************************************************************************/\r
-\r
-__INLINE__ void MOSAL_timer_del(MOSAL_timer_t *t)\r
-{\r
- KeCancelTimer( &t->timer );\r
-}\r
-\r
- /******************************************************************************\r
- * Function:\r
- * MOSAL_timer_mod\r
- *\r
- * Description:\r
- * stop the running timer and restart it in 'usecs' microseconds\r
- *\r
- * Parameters:\r
- * d - MOSAL timer object\r
- * usecs - interval; 'func' will be called in 'usecs' microseconds\r
- *\r
- * Returns:\r
- *\r
- * Notes:\r
- * Callers of this routine must be running at IRQL <= DISPATCH_LEVEL\r
- *\r
- ******************************************************************************/\r
-\r
-__INLINE__ void MOSAL_timer_mod(MOSAL_timer_t *t, long usecs)\r
-{\r
- // recalculate timeout value (it is in usecs)\r
- // our tick is a 100 nanosec. Negative value means time, relative to the current\r
- LARGE_INTEGER DueTime;\r
- DueTime.QuadPart = ((int64_t)usecs * (-10));\r
- \r
- // start timer\r
- KeSetTimer( &t->timer, DueTime, &t->mdpc.dpc );\r
-}\r
-\r
-////////////////////////////////////////////////////////////////////////////////\r
-// Time functions \r
-////////////////////////////////////////////////////////////////////////////////\r
-\r
-\r
- /******************************************************************************\r
- * Function:\r
- * MOSAL_time_get_clock\r
- *\r
- * Description:\r
- * get current system clock (in microseconds)\r
- *\r
- * Parameters:\r
- * ts(OUT) - pointer to a structure, describing the time\r
- *\r
- * Returns:\r
- *\r
- * Notes:\r
- * Callers of this routine must be running at IRQL <= DISPATCH_LEVEL\r
- *\r
- ******************************************************************************/\r
-void MOSAL_time_get_clock(MOSAL_timespec_t *ts)\r
-{\r
- // get abs time in ticks (100 nanosec units)\r
- LARGE_INTEGER AbsTime;\r
- KeQuerySystemTime( &AbsTime );\r
- \r
- // convert to MOSAL_timespec_t\r
- ts->tv_sec = (ULONG)(AbsTime.QuadPart / 10000000);\r
- ts->tv_nsec = (ULONG)(AbsTime.QuadPart % 10000000);\r
-}\r
-\r
-u_int32_t MOSAL_get_cnt()\r
-{\r
- static LONG cnt = 0;\r
- return (u_int32_t)InterlockedIncrement(&cnt);\r
-}\r
-\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_TIMER_IMP_H\r
-#define H_MOSAL_TIMER_IMP_H\r
-\r
-/* IRQ back compatibility */\r
-#ifndef IRQ_HANDLED\r
- typedef void irqreturn_t;\r
- #define IRQ_HANDLED\r
-#endif\r
-\r
-typedef u_int32_t MOSAL_IRQ_ID_t;\r
-typedef void MOSAL_intr_regs_t;\r
-typedef BOOLEAN (*intr_handler_t)(int irq, void *dev_id, MOSAL_intr_regs_t* regs_p);\r
-/* user ISR function prototype */\r
-typedef BOOLEAN (*MOSAL_ISR_func_t)(MT_ulong_ptr_t func_ctx, void * isr_ctx1, void * isr_ctx2 );\r
-\r
-#ifdef MT_KERNEL\r
-\r
-#include "mosal_sync_imp.h"\r
-\r
-/* ISRs */\r
-\r
-\r
-struct MOSAL_ISR {\r
- MOSAL_ISR_func_t func;\r
- MOSAL_IRQ_ID_t irq;\r
- char * name;\r
- MT_ulong_ptr_t ctx;\r
- void * isr_ctx1;\r
- void * isr_ctx2;\r
- PKINTERRUPT int_object_p; \r
-};\r
-\r
-\r
-/* DPCs */\r
-\r
-/* the structure contains the context, relayed to user DPC */\r
-\r
-struct DPC_CONTEXT {\r
- MT_ulong_ptr_t func_ctx; /* DPC ("static") context */\r
- void * isr_ctx1; /* "dynamic" context, relayed by ISR */\r
- void * isr_ctx2; /* "dynamic" context, relayed by ISR */\r
-}; \r
-\r
-\r
-// user DPC function prototype\r
-typedef void (*MOSAL_DPC_func_t)(struct DPC_CONTEXT * func_ctx);\r
-\r
-\r
-/* linked DPC context */\r
-struct LDPC_CONTEXT {\r
- LIST_ENTRY link; /* must be the first ! */\r
- struct DPC_CONTEXT dpc_ctx; /* user DPC context */\r
-}; \r
-\r
-typedef struct LDPC_CONTEXT LDPC_CONTEXT_t;\r
-\r
-/* MOSAL DPC object */\r
-struct MOSAL_dev;\r
-\r
-/* types of DPC (if doesn't need to relay info from ISR to DPC - use MOSAL_NO_CTX value) */\r
-typedef enum { MOSAL_NO_CTX, MOSAL_SINGLE_CTX, MOSAL_MULTIPLE_CTX } MOSAL_DPC_type_t;\r
-\r
-struct MOSAL_DPC {\r
- KDPC dpc; /* OS DPC object */\r
- MOSAL_DPC_func_t func; /* user DPC to be called */\r
- struct DPC_CONTEXT dpc_ctx; /* user DPC context */\r
- MOSAL_DPC_type_t type; /* type of DPC */\r
- MOSAL_spinlock_t lock; /* spinlock */\r
- \r
-#ifdef SUPPORT_MULTIPLE_CTX \r
- LIST_ENTRY ctx_head; /* queue of requests */\r
- LDPC_CONTEXT_t * ldpc_ctx_p; /* returned value from a synchronized routine */\r
- struct MOSAL_dev * isr_ctx; /* pointer to MOSAL device */\r
-#endif \r
-};\r
-\r
-/* Macros */\r
-#define MOSAL_DPC_enable(MOSAL_DPC_p) \r
-#define MOSAL_DPC_disable(MOSAL_DPC_p)\r
-\r
-\r
-/* TIMERs */\r
-\r
-\r
-/* MOSAL timer object */\r
-struct MOSAL_timer {\r
- KTIMER timer; /* OS DPC object */\r
- struct MOSAL_DPC mdpc; /* MOSAL DPC object */\r
-};\r
-\r
-u_int32_t MOSAL_get_cnt();\r
-\r
-#endif /* __KERNEL__ */\r
-\r
-#endif /* H_MOSAL_TIMER_IMP_H */\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_TIMER_PRIV_H\r
-#define H_MOSAL_TIMER_PRIV_H\r
-\r
-#include "mosal_timer_imp.h"\r
-\r
-#ifdef __KERNEL__\r
-\r
-\r
-/* INTERRUPTS */\r
-\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function: general_isr\r
- *\r
- * Description: device ISR handler\r
- *\r
- * Parameters:\r
- * pi_pIntObject........... Interrupt Object\r
- * pi_pContext............. My device context\r
- *\r
- * Returns:\r
- *\r
- *****************************************************************************/\r
-BOOLEAN \r
-general_isr(\r
- PKINTERRUPT pi_pIntObject, \r
- PVOID pi_pContext\r
- );\r
-\r
-\r
-void deinit_dpc();\r
-call_result_t init_dpc();\r
-\r
-#endif /* __KERNEL__ */\r
-\r
-#endif /* H_MOSAL_TIMER_PRIV_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_TYPES_H\r
-#define H_MOSAL_TYPES_H\r
-\r
-/* TAVOR */\r
-#define MOSAL_MAXDEV 32\r
-#define MOSAL_MAXNAME 32\r
-\r
-#define MOSAL_EXPECT_TRUE(cond) (cond)\r
-#define MOSAL_EXPECT_FALSE(cond) (cond)\r
-\r
-\r
-typedef HANDLE MOSAL_shmid_t;\r
-\r
-#endif\r
-\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "mosal_priv.h"\r
-\r
-\r
-\r
-/* device DB */\r
-extern MOSAL_dev_t MOSAL_dev_db[MOSAL_MAXDEV]; \r
-\r
-extern KIRQL cur_max_irql;\r
-\r
-/******************************************************************************\r
- * Function:\r
- * find_device_by_name\r
- *\r
- * Description:\r
- * find device entry in MOSAL device DB by device name \r
- *\r
- * Parameters:\r
- * name - device name\r
- *\r
- * Returns:\r
- * pointer to the entry on SUCCESS\r
- * NULL - otherwise\r
- *\r
- \r
-******************************************************************************/\r
-MOSAL_dev_t *find_device_by_name( char *name)\r
-{\r
- int i;\r
-\r
- /* find place for new device */\r
- for (i=0; i<MOSAL_MAXDEV; i++)\r
- {\r
- if (strstr(MOSAL_dev_db[i].name, name) != NULL)\r
- return &MOSAL_dev_db[i];\r
- }\r
- return NULL;\r
-}\r
-\r
-/******************************************************************************\r
- * Function:\r
- * find_device_by_location\r
- *\r
- * Description:\r
- * find device entry in MOSAL device DB by device location \r
- *\r
- * Parameters:\r
- * name - device name\r
- *\r
- * Returns:\r
- * pointer to the entry on SUCCESS\r
- * NULL - otherwise\r
- *\r
- \r
-******************************************************************************/\r
-MOSAL_dev_t *find_device_by_location( u_int8_t bus, u_int8_t dev_func )\r
-{\r
- int i;\r
-\r
- /* find place for new device */\r
- for (i=0; i<MOSAL_MAXDEV; i++)\r
- {\r
- if ((MOSAL_dev_db[i].bus == bus) && (MOSAL_dev_db[i].dev_func == \r
-dev_func))\r
- return &MOSAL_dev_db[i];\r
- }\r
- return NULL;\r
-}\r
-\r
-/******************************************************************************\r
- * Function:\r
- * find_device_by_phys_addr\r
- *\r
- * Description:\r
- * find device entry in MOSAL device DB by physical address\r
- *\r
- * Parameters:\r
- * pa - phys address\r
- * bsize - region size\r
- *\r
- * Returns:\r
- * pointer to the entry on SUCCESS\r
- * NULL - otherwise\r
- *\r
- \r
-******************************************************************************/\r
-MOSAL_dev_t *find_device_by_phys_addr( MT_phys_addr_t pa, MT_size_t bsize )\r
-{\r
- int i; MT_phys_addr_t dpa;MT_size_t dbsize;\r
-\r
- /* find place for new device */\r
- for (i=0; i<MOSAL_MAXDEV; i++)\r
- {\r
- // check DDR\r
- dpa = (MT_phys_addr_t)MOSAL_dev_db[i].m_Ddr.m_MemPhysAddr.QuadPart; \r
- dbsize = (MT_size_t)MOSAL_dev_db[i].m_Ddr.m_ulMemSize;\r
- if ((dpa <= pa) && ((dpa + dbsize) >= (pa + bsize)))\r
- return &MOSAL_dev_db[i];\r
- // check UAR\r
- dpa = (MT_phys_addr_t)MOSAL_dev_db[i].m_Uar.m_MemPhysAddr.QuadPart; \r
- dbsize = (MT_size_t)MOSAL_dev_db[i].m_Uar.m_ulMemSize;\r
- if ((dpa <= pa) && ((dpa + dbsize) >= (pa + bsize)))\r
- return &MOSAL_dev_db[i];\r
- // check CR\r
- dpa = (MT_phys_addr_t)MOSAL_dev_db[i].m_Cr.m_MemPhysAddr.QuadPart; \r
- dbsize = (MT_size_t)MOSAL_dev_db[i].m_Cr.m_ulMemSize;\r
- if ((dpa <= pa) && ((dpa + dbsize) >= (pa + bsize)))\r
- return &MOSAL_dev_db[i];\r
- }\r
- return NULL;\r
-}\r
-\r
-/******************************************************************************\r
- * Function:\r
- * SendAwaitIrpCompletion\r
- *\r
- * Description:\r
- * IRP completion routine \r
- *\r
- * Parameters:\r
- *\r
- * Returns:\r
- * pointer to the entry on SUCCESS\r
- * NULL - otherwise\r
- *\r
- \r
-******************************************************************************/\r
-NTSTATUS\r
-SendAwaitIrpCompletion (\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN PIRP Irp,\r
- IN PVOID Context\r
- )\r
-{\r
- UNREFERENCED_PARAMETER (DeviceObject); \r
- KeSetEvent ((PKEVENT) Context, IO_NO_INCREMENT, FALSE);\r
- return STATUS_MORE_PROCESSING_REQUIRED; // Keep this IRP\r
-}\r
-\r
-/******************************************************************************\r
- * Function:\r
- * SendAwaitIrp\r
- *\r
- * Description:\r
- * Create and send IRP stack down the stack and wait for the response (\r
-Blocking Mode)\r
- *\r
- * Parameters:\r
- * pi_pDeviceExt.......... ointer to USB device extension\r
- * pi_MajorCode........... IRP major code\r
- * pi_MinorCode........... IRP minor code\r
- * pi_pBuffer............. parameter buffer\r
- * pi_nSize............... size of the buffer\r
- *\r
- * Returns:\r
- * pointer to the entry on SUCCESS\r
- * NULL - otherwise\r
- *\r
- \r
-******************************************************************************/\r
-NTSTATUS \r
-SendAwaitIrp(\r
- IN PDEVICE_OBJECT pi_pFdo,\r
- IN PDEVICE_OBJECT pi_pLdo,\r
- IN ULONG pi_MajorCode,\r
- IN ULONG pi_MinorCode,\r
- IN PVOID pi_pBuffer,\r
- IN int pi_nSize\r
- )\r
-/*++\r
-\r
- Routine Description: \r
-\r
- Create and send IRP stack down the stack and wait for the response (\r
-Blocking Mode)\r
-\r
- Arguments: \r
- \r
- pi_pFdo................ our device\r
- pi_pLdo................ lower device\r
- pi_MajorCode........... IRP major code\r
- pi_MinorCode........... IRP minor code\r
- pi_pBuffer............. parameter buffer\r
- pi_nSize............... size of the buffer\r
-\r
- Returns: \r
- \r
- standard NTSTATUS return codes.\r
-\r
- Notes:\r
-\r
---*/\r
-{ /* SendAwaitIrp */\r
- // Event\r
- KEVENT l_hEvent;\r
- // Pointer to IRP\r
- PIRP l_pIrp;\r
- // Stack location\r
- PIO_STACK_LOCATION l_pStackLocation;\r
- // Returned status\r
- NTSTATUS l_Status;\r
-\r
- // call validation\r
- if(KeGetCurrentIrql() != PASSIVE_LEVEL)\r
- return STATUS_SUCCESS;\r
-\r
- // create event\r
- KeInitializeEvent(&l_hEvent, NotificationEvent, FALSE);\r
-\r
- // build IRP request to USBD driver\r
- l_pIrp = IoAllocateIrp( pi_pFdo->StackSize, FALSE );\r
-\r
- // validate request\r
- if (!l_pIrp)\r
- {\r
- //MdKdPrint( DBGLVL_MAXIMUM, ("(SendAwaitIrp) Unable to allocate IRP !\n"));\r
- return STATUS_INSUFFICIENT_RESOURCES;\r
- }\r
-\r
- // fill IRP\r
- l_pIrp->IoStatus.Status = STATUS_NOT_SUPPORTED;\r
-\r
- // set completion routine\r
- IoSetCompletionRoutine(l_pIrp,SendAwaitIrpCompletion, &l_hEvent, TRUE, \r
-TRUE, TRUE);\r
-\r
- // fill stack location\r
- l_pStackLocation = IoGetNextIrpStackLocation(l_pIrp);\r
- l_pStackLocation->MajorFunction= (UCHAR)pi_MajorCode;\r
- l_pStackLocation->MinorFunction= (UCHAR)pi_MinorCode;\r
- RtlCopyMemory( &l_pStackLocation->Parameters, pi_pBuffer, pi_nSize );\r
-\r
- // Call lower driver perform request\r
- l_Status = IoCallDriver( pi_pLdo, l_pIrp ); \r
-\r
- // if the request not performed --> wait\r
- if (l_Status == STATUS_PENDING)\r
- {\r
- // Wait until the IRP will be complete\r
- KeWaitForSingleObject(\r
- &l_hEvent, // event to wait for\r
- Executive, // thread type (to wait into its context)\r
- KernelMode, // mode of work\r
- FALSE, // alertable\r
- NULL // timeout\r
- );\r
- l_Status = l_pIrp->IoStatus.Status;\r
- }\r
-\r
- IoFreeIrp(l_pIrp);\r
-\r
- return l_Status;\r
-\r
-} /* SendAwaitIrp */\r
-\r
-/******************************************************************************\r
- * Function:\r
- * ReadWritePciConfig\r
- *\r
- * Description:\r
- * Create and send IRP stack down the stack and wait for the response (\r
-Blocking Mode)\r
- *\r
- * Parameters:\r
- * pi_pDeviceExt.......... ointer to USB device extension\r
- * pi_MajorCode........... IRP major code\r
- * pi_MinorCode........... IRP minor code\r
- * pi_pBuffer............. parameter buffer\r
- * pi_nSize............... size of the buffer\r
- *\r
- * Returns:\r
- * pointer to the entry on SUCCESS\r
- * NULL - otherwise\r
- *\r
- \r
-******************************************************************************/\r
-NTSTATUS\r
-ReadWritePciConfig(\r
- IN MOSAL_dev_handle_t pi_pDev,\r
- IN PVOID pi_pDataBuffer,\r
- IN ULONG pi_nPciSpaceOffset,\r
- IN ULONG pi_nDataLength,\r
- IN BOOLEAN pi_fReadConfig\r
- )\r
-\r
-{ /* ReadWritePciConfig */ \r
-\r
- // parameter buffer for the request\r
- ReadWriteConfig_t l_RwParams;\r
-\r
- // parameter validation\r
- //MDASSERT(pi_pDataBuffer);\r
- //MDASSERT(pi_nDataLength);\r
- \r
- // fill request parameters\r
- l_RwParams.Buffer = pi_pDataBuffer;\r
- l_RwParams.Length = pi_nDataLength;\r
- l_RwParams.Offset = pi_nPciSpaceOffset;\r
- l_RwParams.WhichSpace = PCI_WHICHSPACE_CONFIG;\r
- \r
- return SendAwaitIrp( pi_pDev->fdo_p, pi_pDev->ldo_p, IRP_MJ_PNP, \r
- pi_fReadConfig ? IRP_MN_READ_CONFIG : IRP_MN_WRITE_CONFIG, &l_RwParams, \r
-sizeof(ReadWriteConfig_t));\r
-\r
-} /* ReadWritePciConfig */ \r
-\r
-/******************************************************************************\r
- * Function: MOSAL_add_device\r
- *\r
- * Description: add OS- and Driver-specific parameters of the device\r
- *\r
- * Parameters:\r
- *\r
- * Returns:\r
- * MT_OK - success\r
- * MT_EBUSY - Device already exists\r
- *\r
- *****************************************************************************/\r
-call_result_t MOSAL_add_device(\r
- MOSAL_dev_handle_t * dev_pp, /* returned handle */ \r
- MOSAL_dev_t * parm_p /* entry, filled */\r
- ) \r
-{\r
- MOSAL_dev_t * dev_p;\r
- int i;\r
-\r
- *dev_pp = NULL;\r
- for (i=0; i<MOSAL_MAXDEV; i++)\r
- {\r
- if (MOSAL_dev_db[i].state == MW_BUSY && !strcmp(MOSAL_dev_db[i].name\r
-, parm_p->name))\r
- {\r
- /* Device already exists !!! */\r
- return MT_EBUSY;\r
- }\r
- }\r
-\r
- for (i=0; i<MOSAL_MAXDEV; i++)\r
- {\r
- if (MOSAL_dev_db[i].state == MW_FREE)\r
- {\r
- dev_p = &MOSAL_dev_db[i];\r
- memcpy( dev_p, parm_p, sizeof(MOSAL_dev_t) );\r
- dev_p->state = MW_BUSY;\r
- KeInitializeSpinLock( &dev_p->isr_lock );\r
- *dev_pp = dev_p;\r
- /* calculate current max irql */\r
- if (cur_max_irql < dev_p->irql)\r
- cur_max_irql = dev_p->irql;\r
- return MT_OK;\r
- }\r
- }\r
- return MT_ENORSC;\r
-}\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_remove_device\r
- *\r
- * Description: add OS- and Driver-specific parameters of the device\r
- *\r
- * Parameters:\r
- *\r
- * Returns:\r
- * MT_OK - success\r
- * MT_EBUSY - Device already exists\r
- *\r
- *****************************************************************************/\r
-call_result_t MOSAL_remove_device(MOSAL_dev_handle_t dev_p) \r
-{\r
- int i;\r
- \r
- if (dev_p == NULL)\r
- return MT_ERROR;\r
-\r
- /* recalculate current max irql */\r
- cur_max_irql = DISPATCH_LEVEL;\r
- dev_p->irq_num = 0;\r
- for (i=0; i<MOSAL_MAXDEV; i++)\r
- {\r
- if (MOSAL_dev_db[i].state == MW_BUSY)\r
- {\r
- dev_p = &MOSAL_dev_db[i];\r
- if (cur_max_irql < dev_p->irql)\r
- cur_max_irql = dev_p->irql;\r
- }\r
- }\r
- /* disconnect interrupt */\r
- if (dev_p->int_object_p != NULL)\r
- IoDisconnectInterrupt( dev_p->int_object_p );\r
- memset( dev_p, 0, sizeof(MOSAL_dev_t) ); \r
- dev_p->state = MW_FREE;\r
- return MT_OK;\r
-}\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSAL_UTIL_H\r
-#define H_MOSAL_UTIL_H\r
-\r
-/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\r
- * \r
- * Structures\r
- *\r
- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */\r
-\r
-typedef enum {MW_FREE, MW_BUSY} mw_dev_state_t;\r
-\r
-#ifdef __KERNEL__\r
-/* taken from wdm.h */\r
-typedef struct {\r
- ULONG WhichSpace;\r
- PVOID Buffer;\r
- ULONG Offset;\r
- ULONG POINTER_ALIGNMENT Length;\r
-} ReadWriteConfig_t, *PReadWriteConfig_t;\r
-\r
-\r
-/* device configuration and other specific information */\r
-\r
-typedef struct MD_BAR_S {\r
- PHYSICAL_ADDRESS m_MemPhysAddr;\r
- ULONG m_ulMemSize;\r
- USHORT m_usMemFlags;\r
- PUCHAR m_pKernelAddr;\r
- ULONG m_ulKernelSize;\r
- ULONG m_ulKernelOffset;\r
-} MD_BAR_T, *PMD_BAR_T;\r
-\r
-\r
-\r
-/* OS- and Driver-specific device parameters */\r
-typedef struct MOSAL_dev {\r
- mw_dev_state_t state; /* Device status flag */\r
- char name[MOSAL_MAXNAME]; /* Device name */\r
- PKINTERRUPT int_object_p; /* NT interrupt object */\r
- MOSAL_ISR_func_t thandler; /* device interrupt handler */\r
- intr_handler_t ghandler; /* device interrupt handler */\r
- void * dev_id; /* interrupt handler context */\r
- MOSAL_IRQ_ID_t irq_num; /* IRQ vector number */\r
- KIRQL irql; /* interrupt level */\r
- KAFFINITY affinity; /* processor affinity */\r
- BOOLEAN int_shared; /* whether interrupt is shared */\r
- KINTERRUPT_MODE int_mode; /* interrupt mode */\r
- PDEVICE_OBJECT fdo_p; /* functional device object */\r
- PDEVICE_OBJECT ldo_p; /* lower device object */\r
- u_int8_t bus; /* PCI bus number of the IB card */\r
- u_int8_t dev_func; /* device/function of the IB card */\r
- KSPIN_LOCK isr_lock; /* lock for the ISR */\r
- MD_BAR_T m_Cr; /* CR space */\r
- MD_BAR_T m_Uar; /* UAR-space region */\r
- MD_BAR_T m_Ddr; /* DDR-space region */\r
- void * drv_helper; /* driver function for perfrming tings, that MOSAL can't do */\r
- void * drv_helper_ctx; /* it's context */\r
-} MOSAL_dev_t; \r
-\r
-typedef MOSAL_dev_t * MOSAL_dev_handle_t;\r
-\r
-\r
-/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * \r
-* * * * * * * * *\r
- * \r
- * Helpers\r
- *\r
- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * \r
-* * * * * * * * */\r
-\r
-/******************************************************************************\r
- * Function:\r
- * find_device_by_name\r
- *\r
- * Description:\r
- * find device entry in MOSAL device DB by device name \r
- *\r
- * Parameters:\r
- * name - device name\r
- *\r
- * Returns:\r
- * pointer to the entry on SUCCESS\r
- * NULL - otherwise\r
- *\r
- \r
-******************************************************************************/\r
-MOSAL_dev_t *find_device_by_name( char *name);\r
-\r
-/******************************************************************************\r
- * Function:\r
- * find_device_by_location\r
- *\r
- * Description:\r
- * find device entry in MOSAL device DB by device location \r
- *\r
- * Parameters:\r
- * name - device name\r
- *\r
- * Returns:\r
- * pointer to the entry on SUCCESS\r
- * NULL - otherwise\r
- *\r
- \r
-******************************************************************************/\r
-MOSAL_dev_t *find_device_by_location( u_int8_t bus, u_int8_t dev_func );\r
-\r
-/******************************************************************************\r
- * Function:\r
- * find_device_by_phys_addr\r
- *\r
- * Description:\r
- * find device entry in MOSAL device DB by physical address\r
- *\r
- * Parameters:\r
- * pa - phys address\r
- * bsize - region size\r
- *\r
- * Returns:\r
- * pointer to the entry on SUCCESS\r
- * NULL - otherwise\r
- *\r
- \r
-******************************************************************************/\r
-MOSAL_dev_t *find_device_by_phys_addr( MT_phys_addr_t pa, MT_size_t bsize );\r
-\r
-/******************************************************************************\r
- * Function:\r
- * SendAwaitIrpCompletion\r
- *\r
- * Description:\r
- * IRP completion routine \r
- *\r
- * Parameters:\r
- *\r
- * Returns:\r
- * pointer to the entry on SUCCESS\r
- * NULL - otherwise\r
- *\r
- \r
-******************************************************************************/\r
-NTSTATUS\r
-SendAwaitIrpCompletion (\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN PIRP Irp,\r
- IN PVOID Context\r
- );\r
-\r
-/******************************************************************************\r
- * Function:\r
- * SendAwaitIrp\r
- *\r
- * Description:\r
- * Create and send IRP stack down the stack and wait for the response (\r
-Blocking Mode)\r
- *\r
- * Parameters:\r
- * pi_pDeviceExt.......... ointer to USB device extension\r
- * pi_MajorCode........... IRP major code\r
- * pi_MinorCode........... IRP minor code\r
- * pi_pBuffer............. parameter buffer\r
- * pi_nSize............... size of the buffer\r
- *\r
- * Returns:\r
- * pointer to the entry on SUCCESS\r
- * NULL - otherwise\r
- *\r
- \r
-******************************************************************************/\r
-NTSTATUS \r
-SendAwaitIrp(\r
- IN PDEVICE_OBJECT pi_pFdo,\r
- IN PDEVICE_OBJECT pi_pLdo,\r
- IN ULONG pi_MajorCode,\r
- IN ULONG pi_MinorCode,\r
- IN PVOID pi_pBuffer,\r
- IN int pi_nSize\r
- );\r
-\r
-/******************************************************************************\r
- * Function:\r
- * ReadWritePciConfig\r
- *\r
- * Description:\r
- * Create and send IRP stack down the stack and wait for the response (\r
-Blocking Mode)\r
- *\r
- * Parameters:\r
- * pi_pDeviceExt.......... ointer to USB device extension\r
- * pi_MajorCode........... IRP major code\r
- * pi_MinorCode........... IRP minor code\r
- * pi_pBuffer............. parameter buffer\r
- * pi_nSize............... size of the buffer\r
- *\r
- * Returns:\r
- * pointer to the entry on SUCCESS\r
- * NULL - otherwise\r
- *\r
- \r
-******************************************************************************/\r
-NTSTATUS\r
-ReadWritePciConfig(\r
- IN MOSAL_dev_handle_t pi_pDev,\r
- IN PVOID pi_pDataBuffer,\r
- IN ULONG pi_nPciSpaceOffset,\r
- IN ULONG pi_nDataLength,\r
- IN BOOLEAN pi_fReadConfig\r
- );\r
-\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_add_device\r
- *\r
- * Description: add OS- and Driver-specific parameters of the device\r
- *\r
- * Parameters:\r
- *\r
- * Returns:\r
- * MT_OK - success\r
- * MT_EBUSY - Device already exists\r
- *\r
- *****************************************************************************/\r
-call_result_t MOSAL_add_device(\r
- MOSAL_dev_handle_t * dev_pp, /* returned handle */ \r
- MOSAL_dev_t * parm_p /* entry, filled */\r
- );\r
-\r
-/******************************************************************************\r
- * Function: MOSAL_remove_device\r
- *\r
- * Description: add OS- and Driver-specific parameters of the device\r
- *\r
- * Parameters:\r
- *\r
- * Returns:\r
- * MT_OK - success\r
- * MT_EBUSY - Device already exists\r
- *\r
- *****************************************************************************/\r
-call_result_t MOSAL_remove_device(MOSAL_dev_t* dev_p); \r
-#endif\r
-#endif\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#if WINVER >= 0x0502\r
-#include <winsock2.h>\r
-#endif\r
-#include <windows.h>\r
-#include <stdio.h>\r
-\r
-#ifdef MT_KERNEL\r
-#if 0\r
-BOOL mosal_main( HANDLE hModule, \r
- DWORD ul_reason_for_call, \r
- LPVOID lpReserved\r
- )\r
-{\r
- /* The status to return */\r
- BOOL l_fRetCode = TRUE;\r
- /* socket dll version */\r
- WORD wVersionRequested;\r
- /* socket dll information */\r
- WSADATA WsaData;\r
- /* return code */\r
- int rc;\r
- /* print buffer */\r
- char buf[360];\r
-\r
- switch (ul_reason_for_call)\r
- {\r
- case DLL_PROCESS_ATTACH:\r
- { /* DLL_PROCESS_ATTACH */\r
-\r
- sprintf( buf, "MOSAL:DllMain: >> DLL_PROCESS_ATTACH: Pid 0x%x\n",\r
- GetCurrentProcessId() );\r
- //OutputDebugString(buf); \r
- \r
- /* start sockets */\r
- wVersionRequested = MAKEWORD( 2, 0 );\r
- rc = WSAStartup( wVersionRequested, &WsaData );\r
- if (rc != 0) {\r
- sprintf( buf, "Error 0x%x in call to WSAStartup()\r\n", rc );\r
- OutputDebugString(buf);\r
- l_fRetCode = FALSE; \r
- break;\r
- }\r
- else { \r
- sprintf( buf, "MOSAL:DllMain: Ver 0x%x, MaxSock %d, Descr '%s'\n",\r
- WsaData.wHighVersion,\r
- WsaData.iMaxSockets,\r
- WsaData.szDescription\r
- );\r
- //OutputDebugString(buf); \r
- }\r
- \r
- }/* DLL_PROCESS_ATTACH */\r
- break;\r
-\r
- case DLL_PROCESS_DETACH:\r
- { /* DLL_PROCESS_DETACH */\r
- \r
- /* end up with sockets */\r
- WSACleanup();\r
- \r
- } /* DLL_PROCESS_DETACH */\r
- break;\r
- \r
- case DLL_THREAD_ATTACH:\r
- break;\r
-\r
-\r
- case DLL_THREAD_DETACH:\r
- break;\r
- }\r
- return l_fRetCode;\r
-}\r
-#endif\r
-\r
-unsigned long MOSAL_getpid()\r
-{\r
- return (unsigned long)GetCurrentProcessId();\r
-}\r
-#endif // MT_KERNEL\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#define C_K2U_CBK_U_C\r
-\r
-#include <string.h>\r
-#include "mosal_priv.h"\r
-#include "mosalu_k2u_cbk.h"\r
-#include <mtib.h>\r
-\r
-static pcs_cbk_t s_pcs_cbk = { 0, 0, 0, 0, 0, 0, NULL };\r
-static void k2u_cbk_thread_cleanup(void);\r
-\r
-\r
-/* THREAD ENTRY POINT */\r
-DWORD WINAPI start_thread(\r
- pcs_cbk_p_t pi_pCbk // pointer to callback info\r
-)\r
-{ \r
- k2u_cbk_id_t id;\r
- u_int8_t data[MAX_CBK_DATA_SZ];\r
- MT_size_t size;\r
- call_result_t rc;\r
-\r
- /* Make initialization of kernel resources from this thread to allow owner validation in kernel */\r
- if ((rc= k2u_cbk_init(&pi_pCbk->this_proc_cbk_hndl)) != MT_OK) {\r
- MTL_ERROR1("%s: failed initializing kernel stub (%s).\n", __func__,mtl_strerror(rc));\r
- return 0;\r
- }\r
-\r
- /* release main thread */\r
- SetEvent( pi_pCbk->event );\r
- \r
- /* poll private message queue until MT_EAGAIN (empty) */\r
- while (1) {\r
- rc= k2u_cbk_pollq(pi_pCbk->this_proc_cbk_hndl,&id,data,&size);\r
- if (rc == MT_EINTR) {\r
- MTL_DEBUG2(MT_FLFMT("k2u_cbk_pollq returned with MT_EINTR"));\r
- continue; /* poll interrupted (signal pending...) */\r
- }\r
- if (rc != MT_OK) break;\r
- if (id == K2U_CBK_CLEANUP_CBK_ID) break;\r
- if (MOSAL_mutex_acq(&pi_pCbk->mutex, TRUE) != MT_OK) break;\r
- if ((id < MAX_CBK) && (pi_pCbk->cbks[id] != NULL)) { /* found matching callback */\r
- pi_pCbk->cbks[id](id,data,size); /* invoke callback */\r
- }\r
- MOSAL_mutex_rel(&pi_pCbk->mutex);\r
- }\r
- if (id != K2U_CBK_CLEANUP_CBK_ID) {\r
- MTL_ERROR1(MT_FLFMT("k2u_cbk_pollq returned error (%s). k2u_cbk will be disabled."),\r
- mtl_strerror_sym(rc)); \r
- }\r
- return 0;\r
-}\r
-\r
-call_result_t k2u_cbk_register(k2u_cbk_t cbk, k2u_cbk_hndl_t *cbk_hndl_p, k2u_cbk_id_t *cbk_id_p)\r
-{\r
- k2u_cbk_id_t id;\r
- pcs_cbk_p_t l_pCbk = &s_pcs_cbk;\r
- DWORD status;\r
- HANDLE wait_list[3];\r
- MT_bool first_cbk;\r
- \r
- if (cbk == NULL) {\r
- MTL_ERROR2("%s: NULL callback.\n", __func__);\r
- return MT_EINVAL;\r
- }\r
- \r
- if (l_pCbk->num_o_cbks == 0) { /* first callback */\r
- MOSAL_mutex_init(&l_pCbk->mutex);\r
- }\r
- \r
- if (MOSAL_mutex_acq(&l_pCbk->mutex, TRUE) != MT_OK) { \r
- return MT_EAGAIN;\r
- }\r
-\r
- /* Find free cbk id */\r
- if (l_pCbk->num_o_cbks == MAX_CBK) {\r
- MTL_ERROR2("%s: All callback resources are used (%d).\n", __func__,MAX_CBK);\r
- MOSAL_mutex_rel(&l_pCbk->mutex);\r
- return MT_OK;\r
- }\r
- \r
- /* From this point we are sure that we will find at least one free id */\r
- for (id= 0; id < MAX_CBK; id++) {\r
- if (l_pCbk->cbks[id] == NULL) break;\r
- } /* for */\r
- \r
- #ifdef MAX_DEBUG\r
- if (id == MAX_CBK) {\r
- MTL_ERROR1("%s: No free callback entry was found !\n", __func__);\r
- MOSAL_mutex_rel(&l_pCbk->mutex);\r
- return MT_OK;\r
- }\r
- #endif \r
-\r
- l_pCbk->num_o_cbks++;\r
-\r
- l_pCbk->cbks[id]= cbk; /* Assure assignment is done only when data is valid*/\r
- first_cbk= (l_pCbk->num_o_cbks == 1);\r
- /* block additional allocations while setting up polling thread (with mutex unlocked) */ \r
- if (first_cbk) l_pCbk->num_o_cbks= MAX_CBK; \r
- MOSAL_mutex_rel(&l_pCbk->mutex);\r
-\r
- if (first_cbk) { /* first callback */\r
-\r
- /* init data */\r
- l_pCbk->event = CreateEvent( NULL, FALSE, FALSE, NULL );\r
- if ( l_pCbk->event == NULL ) {\r
- MTL_ERROR1( "k2u_cbk_register: Cannot create event (0x%x)\n", GetLastError());\r
- goto event_fail; \r
- }\r
- \r
- /* Wait for old thread to complete cleanup */\r
- WaitForSingleObject( l_pCbk->threadHandle, INFINITE );\r
- CloseHandle( l_pCbk->threadHandle );\r
- l_pCbk->threadHandle = NULL;\r
-\r
- /* run helper thread to poll the callbacks */\r
- l_pCbk->threadHandle = CreateThread(\r
- NULL, // pointer to security attributes\r
- 0, // initial thread stack size\r
- start_thread, // pointer to thread function\r
- l_pCbk, // argument for new thread\r
- 0, // creation flags: run immediately\r
- &l_pCbk->threadId // pointer to receive thread ID\r
- ); \r
-\r
- if (l_pCbk->threadHandle == NULL) {\r
- MTL_ERROR1( "k2u_cbk_register: Cannot create thread for k2u_cbk_t\n");\r
- goto thread_fail;\r
- } \r
-\r
- /* wait thread to start or exit */\r
- wait_list[0] = l_pCbk->threadHandle; \r
- wait_list[1] = l_pCbk->event; \r
- status = WaitForMultipleObjects( 2, wait_list, FALSE, INFINITE );\r
- if (status == WAIT_OBJECT_0) { /* thread exited */\r
- MTL_ERROR1( "k2u_cbk_register: Polling thread failed to start\n");\r
- goto thread_exit;\r
- }\r
- l_pCbk->num_o_cbks = 1;\r
- \r
- /* register cleanup function */\r
- mtib_RegisterCF( k2u_cbk_thread_cleanup );\r
- }\r
-\r
- *cbk_id_p= id;\r
- *cbk_hndl_p= l_pCbk->this_proc_cbk_hndl;\r
- return MT_OK;\r
- \r
-thread_exit:\r
- CloseHandle( l_pCbk->threadHandle );\r
- l_pCbk->threadHandle = NULL;\r
-thread_fail:\r
- l_pCbk->cbks[id]= NULL;\r
- l_pCbk->num_o_cbks= 0;\r
-event_fail:\r
- return MT_EAGAIN;\r
-}\r
-\r
-call_result_t k2u_cbk_deregister(k2u_cbk_id_t cbk_id)\r
-{\r
- pcs_cbk_p_t l_pCbk = &s_pcs_cbk;\r
- \r
- if (MOSAL_mutex_acq(&l_pCbk->mutex, TRUE) != MT_OK) { \r
- return MT_EAGAIN;\r
- }\r
- \r
- if ((cbk_id > MAX_CBK) || (l_pCbk->cbks[cbk_id] == NULL)) {\r
- MOSAL_mutex_rel(&l_pCbk->mutex);\r
- MTL_ERROR2( "k2u_cbk_deregister: Invalid callback ID (%d).\n",cbk_id);\r
- return MT_EINVAL;\r
- }\r
-\r
- /* Remove from table before freeing (avoid inconsistant data while getting signal) */\r
- l_pCbk->cbks[cbk_id] = NULL; \r
- l_pCbk->num_o_cbks--;\r
- if (l_pCbk->num_o_cbks == 0) { /* no more callbacks - restore old handler */\r
- k2u_cbk_cleanup(l_pCbk->this_proc_cbk_hndl); /* free kernel resources */\r
- MTL_DEBUG4( "k2u_cbk_deregister: cleaned up this process cbk resources.\n");\r
- }\r
- \r
- MOSAL_mutex_rel(&l_pCbk->mutex);\r
- return MT_OK;\r
-}\r
-\r
-static void k2u_cbk_thread_cleanup(void)\r
-{\r
- unsigned int i;\r
- pcs_cbk_p_t l_pCbk = &s_pcs_cbk;\r
- MTL_DEBUG1( "k2u_cbk_thread_cleanup: \n");\r
- \r
- if (l_pCbk->num_o_cbks != 0) {\r
- for (i=0; i<l_pCbk->num_o_cbks; i++)\r
- k2u_cbk_deregister(i);\r
- }\r
-}\r
-\r
-/*\r
- * MANUAL WRAPPER\r
- */\r
-\r
-#include <MdIoctl.h>\r
-\r
-static UDLL_THREAD_EXEC_FUNC_T perform_ioctl;\r
-static first_time = 0;\r
-\r
-int k2u_ioctl_wrapper(int ops, void *pi, u_int32_t pi_sz, void *po, u_int32_t po_sz)\r
-{ \r
- if (!first_time)\r
- { /* the tx library is not open yet */\r
-\r
- // register DLL\r
- if( mtib_RegisterWL(&perform_ioctl) )\r
- return MT_ENOMOD;\r
- \r
- // mark successful open\r
- first_time = 1;\r
- \r
- } /* the tx library is not open yet */\r
-\r
- return perform_ioctl( (int)ops, pi, pi_sz, po, po_sz);\r
-}\r
-\r
-call_result_t k2u_cbk_init(k2u_cbk_hndl_t *k2u_cbk_h_p)\r
-{\r
- int ioctl_rc;\r
-\r
- ioctl_rc = k2u_ioctl_wrapper(K2U_CBK_CBK_INIT, NULL, 0, k2u_cbk_h_p, sizeof(k2u_cbk_hndl_t));\r
-\r
- return ioctl_rc ? MT_ERROR : MT_OK;\r
-}\r
-\r
-\r
-call_result_t k2u_cbk_cleanup(k2u_cbk_hndl_t k2u_cbk_h)\r
-{\r
- int ioctl_rc;\r
- \r
- ioctl_rc = k2u_ioctl_wrapper(K2U_CBK_CBK_CLEANUP, (void*)&k2u_cbk_h, sizeof(k2u_cbk_hndl_t), NULL, 0);\r
- return ioctl_rc ? MT_ERROR : MT_OK;\r
-}\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MOSALU_K2U_CBK_H\r
-#define H_MOSALU_K2U_CBK_H\r
-\r
-#include "mosal_priv.h"\r
-\r
-/* Maximum callbacks per process */\r
-#define MAX_CBK 32\r
-\r
-typedef struct {\r
- k2u_cbk_hndl_t this_proc_cbk_hndl; /* Init when registering first callback */\r
- u_int32_t num_o_cbks; /* current number of callbacks */\r
- DWORD threadId; /* thread ID: for any case */\r
- HANDLE threadHandle; /* thread handle */\r
- HANDLE event; /* "thread started" event */\r
- MOSAL_mutex_t mutex; /* mutex, protecting the structure */\r
- k2u_cbk_t cbks[MAX_CBK]; /* callbacks (index=id) */\r
-} pcs_cbk_t, *pcs_cbk_p_t;\r
-\r
-\r
-#endif\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "mosal_priv.h"\r
-\r
-#if 0\r
-\r
-void MOSAL_user_lib_init(void) { }\r
-\r
-/*\r
- * Map io memory to user address space\r
- *\r
- */\r
-MT_virt_addr_t MOSAL_io_remap(MT_phys_addr_t pa, MT_size_t size)\r
-{\r
- MT_virt_addr_t bp;\r
-\r
- /* ??? How we do it in Windows */\r
- #if 0\r
- if(getuid() != 0){\r
- MTL_ERROR1("MOSAL_io_remap: Only root can do that\n");\r
- return(0);\r
- }\r
- #endif\r
- \r
- /* Check for alignments */\r
- if(size < MIN_PAGE_SZ_ALIGN(size) || pa < MIN_PAGE_SZ_ALIGN(pa)){\r
- MTL_ERROR1("MOSAL_io_remap: Physical address or size not aligned to min. page size\n");\r
- return(0);\r
- }\r
-\r
-#ifdef STRICT_ALIGNEMENT\r
-\r
- if(pa < ((pa + (size - 1)) & (~((~0UL + size))))) {\r
- MTL_ERROR1("MOSAL_io_remap: Physical address must be sized aligned\n");\r
- return(0);\r
- }\r
-\r
-#endif /* STRICT ALIGNEMENT */\r
- \r
- bp = MOSAL_io_remap_for_user(pa, size);\r
- \r
- if(bp == (MT_virt_addr_t)0) {\r
- MTL_ERROR('1', "MOSAL_io_remap: Failed to mmap file\n");\r
- return(0);\r
- } \r
- \r
- return (bp);\r
-}\r
-\r
-void MOSAL_io_unmap(MT_virt_addr_t va)\r
-{\r
- MTL_ERROR1("MOSAL_io_unmap: Not supported yet !!! \n");\r
-}\r
-\r
-void MOSAL_io_release(MT_phys_addr_t pa)\r
-{\r
- MOSAL_io_release_for_user(pa); \r
-}\r
-\r
-MT_virt_addr_t MOSAL_phys_ctg_get(MT_size_t size)\r
-{\r
- return MOSAL_phys_ctg_get_for_user(size);\r
-}\r
-\r
-call_result_t MOSAL_phys_ctg_free(MT_virt_addr_t addr, MT_size_t size)\r
-{\r
- MOSAL_phys_ctg_free_for_user(addr);\r
- return 0;\r
-}\r
-\r
-call_result_t MOSAL_shmget(MOSAL_shmem_key_t key, \r
- MT_size_t size, \r
- u_int32_t flags, \r
- MOSAL_shmid_t * id_p)\r
-{\r
- DWORD ret;\r
- DWORD win_flags=0;\r
- u_int64_t size64 = size;\r
- DWORD dwMaximumSizeHigh = (DWORD)(size64 >> 32);\r
- DWORD dwMaximumSizeLow = (DWORD)(size64 & 0xffffffff);\r
-\r
- if (flags & MOSAL_SHM_READONLY) {\r
- win_flags = PAGE_READONLY; //ReadOnly for everybody\r
- } else {\r
- win_flags = PAGE_READWRITE; //ReadWrite for everybody\r
- }\r
-\r
- //If it should be created\r
- if (flags & MOSAL_SHM_CREATE) {\r
- *id_p = CreateFileMapping(INVALID_HANDLE_VALUE, NULL, win_flags, dwMaximumSizeHigh, dwMaximumSizeLow, key);\r
- } else {\r
- //If it should be opened\r
- if (flags & MOSAL_SHM_READONLY) {\r
- win_flags = FILE_MAP_READ;\r
- } else {\r
- win_flags = FILE_MAP_ALL_ACCESS;\r
- }\r
-\r
- *id_p = OpenFileMapping(win_flags, FALSE , key);\r
- }\r
-\r
- ret = GetLastError();\r
- \r
- if ( (flags & MOSAL_SHM_EXCL ) && (flags & MOSAL_SHM_CREATE) ) {\r
- if (ret == ERROR_ALREADY_EXISTS) {\r
- CloseHandle(*id_p);\r
- return MT_EBUSY;\r
- }\r
- }\r
-\r
-\r
- if (*id_p == NULL) {\r
- \r
- switch (ret) {\r
- case ERROR_ACCESS_DENIED : return MT_EACCES;\r
- case ERROR_TOO_MANY_OPEN_FILES : \r
- case ERROR_NOT_ENOUGH_MEMORY: return MT_EAGAIN;\r
- default: return MT_EINVAL;\r
- }\r
- } else {\r
- return MT_OK;\r
- }\r
-}\r
-\r
-call_result_t MOSAL_shmat(MOSAL_shmid_t id, int flags, void ** addr_p)\r
-{\r
- DWORD win_flags=0;\r
- DWORD ret;\r
-\r
-\r
- if (flags & MOSAL_SHM_READONLY) {\r
- win_flags |= FILE_MAP_READ;\r
- } else {\r
- win_flags |= FILE_MAP_ALL_ACCESS;\r
- }\r
-\r
- *addr_p = MapViewOfFile(id, win_flags, 0, 0, 0);\r
- ret = GetLastError();\r
-\r
- if (*addr_p == NULL) {\r
- switch (ret) {\r
- case ERROR_ACCESS_DENIED : return MT_EACCES;\r
- case ERROR_TOO_MANY_OPEN_FILES : \r
- case ERROR_NOT_ENOUGH_MEMORY: return MT_EAGAIN;\r
- case ERROR_INVALID_ACCESS: return MT_EINVAL;\r
- default: return MT_ERROR;\r
- }\r
- } else {\r
- return MT_OK;\r
- }\r
-}\r
-\r
-call_result_t MOSAL_shmdt(void * addr)\r
-{\r
- if (!UnmapViewOfFile(addr)) {\r
- return MT_EINVAL;\r
- } else {\r
- return MT_OK;\r
- }\r
-}\r
-\r
-call_result_t MOSAL_shmrm(MOSAL_shmid_t id)\r
-{\r
- if (!CloseHandle(id)) {\r
- switch (GetLastError()) {\r
- case ERROR_ACCESS_DENIED : return MT_EACCES;\r
- default: return MT_EINVAL;\r
- }\r
- } else {\r
- return MT_OK;\r
- }\r
-}\r
-\r
-#endif\r
-\r
-/* PAGE_SIZE API */\r
-\r
-u_int32_t MOSAL_get_sys_page_size(MT_virt_addr_t va) \r
-{ \r
- static page_size = 0;\r
- SYSTEM_INFO lpSystemInfo;\r
- if (!page_size) {\r
- GetSystemInfo( &lpSystemInfo );\r
- page_size = (u_int32_t)lpSystemInfo.dwPageSize;\r
- }\r
- return page_size;\r
-}\r
-\r
-u_int32_t MOSAL_get_sys_page_shift(MT_virt_addr_t va) \r
-{\r
- static page_shift = 0;\r
- u_int32_t i, page_size = MOSAL_get_sys_page_size( va ); \r
- if (!page_shift) {\r
- for (i=0; page_size; page_size >>= 1, i++);\r
- page_shift = i - 1;\r
- }\r
- return page_shift;\r
-}\r
-\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "mosal_priv.h"\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_socket\r
- *\r
- * Description:\r
- * create a socket \r
- *\r
- * Parameters: \r
- * domain (IN)\r
- * type (IN)\r
- * protocol(IN)\r
- * Returns:\r
- * the socket on success, otherwise -1\r
- ******************************************************************************/\r
-int MOSAL_socket_socket(MOSAL_socket_domain_t domain,MOSAL_socket_type_t type,MOSAL_socket_protocol_t protocol)\r
-{\r
- SOCKET sd = socket( domain, type, protocol );\r
- if (sd == INVALID_SOCKET)\r
- return -1;\r
- else\r
- return (int)sd;\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_close \r
- *\r
- * Description:\r
- * closes the socket\r
- *\r
- * Parameters: \r
- * sock\r
- * Returns:\r
- * 0 on success, -1 otherwise\r
- ******************************************************************************/\r
-int MOSAL_socket_close(int sock)\r
-{\r
- int rc = closesocket( (SOCKET)sock );\r
- if (rc == SOCKET_ERROR)\r
- return -1;\r
- else\r
- return 0;\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_connect \r
- *\r
- * Description: client\r
- * connect to server \r
- *\r
- * Parameters: \r
- * sock\r
- * adrs(IN) server's adrs details \r
- * len(IN) sizeof struct adrs\r
- * Returns:\r
- * 0 on success, -1 otherwise\r
- ******************************************************************************/\r
-int MOSAL_socket_connect(int sock ,const MOSAL_sockaddr_t* adrs,\r
- MOSAL_socklen_t len)\r
-{\r
- int rc = connect( (SOCKET)sock, (const struct sockaddr FAR *)adrs, len );\r
- if (rc == SOCKET_ERROR)\r
- return -1;\r
- else\r
- return 0;\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_bind \r
- *\r
- * Description: server\r
- * bind the socket to adrs \r
- *\r
- * Parameters: \r
- * sock (IN) \r
- * adrs (IN) server's adrs details \r
- * len (IN) size of struct adrs \r
- * Returns:\r
- * 0 on success, -1 otherwise\r
- *\r
- ******************************************************************************/\r
-int MOSAL_socket_bind(int sock,const MOSAL_sockaddr_t* adrs,\r
- MOSAL_socklen_t len)\r
-{\r
- int rc = bind( (SOCKET)sock, (const struct sockaddr FAR *)adrs, len );\r
- if (rc == SOCKET_ERROR)\r
- return -1;\r
- else\r
- return 0;\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_listen \r
- *\r
- * Description: server\r
- * start listening on this socket \r
- *\r
- * Parameters: \r
- * sock(IN) \r
- * n (IN) length of queue of requests\r
- *\r
- * Returns:\r
- * 0 on success, -1 otherwise\r
- ******************************************************************************/\r
-int MOSAL_socket_listen(int sock ,int n) \r
-{\r
- int rc = listen( (SOCKET)sock, n );\r
- if (rc == SOCKET_ERROR)\r
- return -1;\r
- else\r
- return 0;\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_accept \r
- *\r
- * Description: server\r
- * extracts the first connection on the queue of pending connections, creates a new socket with\r
- * the properties of sock, and allocates a new file descriptor.\r
- * the socket \r
- *\r
- * Parameters: \r
- * sock\r
- * client_adrs_p(OUT) adrs of the first connection accepted\r
- * len_p(OUT) sizeof adrs\r
- * \r
- * Returns:\r
- * the new socket on success, -1 otherwise\r
- ******************************************************************************/\r
-int MOSAL_socket_accept(int sock,MOSAL_sockaddr_t* client_adrs,MOSAL_socklen_t* len_p)\r
-{\r
- SOCKET sd = accept( (SOCKET)sock, (struct sockaddr FAR *)client_adrs, (int FAR *)len_p );\r
- if (sd == INVALID_SOCKET)\r
- return -1;\r
- else\r
- return (int)sd;\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_send \r
- *\r
- * Description: \r
- * send len bytes from buffer through socket \r
- * Parameters: \r
- * sock(IN) \r
- * buf\r
- * len - num of bytes to send\r
- * flags\r
- * Returns: returns the number sent or -1\r
- * \r
- ******************************************************************************/\r
-int MOSAL_socket_send(int sock,const void* buf,int len,int flags)\r
-{\r
- int byte_cnt = send( (SOCKET)sock, (const char FAR *)buf, len, 0 );\r
- if (byte_cnt == SOCKET_ERROR)\r
- return -1;\r
- else\r
- return byte_cnt;\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_recv \r
- *\r
- * Description: \r
- * recv len bytes from buffer through socket \r
- * Parameters: \r
- * sock(IN) pointer to MOSAL socket object\r
- * buf\r
- * len - num of bytes to read\r
- * flags\r
- * Returns: returns the number read or -1\r
- ******************************************************************************/\r
-int MOSAL_socket_recv(int sock,void* buf,int len,int flags)\r
-{\r
- int byte_cnt = recv( (SOCKET)sock, (char FAR *)buf, len, 0 );\r
- if (byte_cnt == SOCKET_ERROR)\r
- return -1;\r
- \r
- if (byte_cnt == 0)\r
- return -1; /* socket closed */\r
- else\r
- return byte_cnt;\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_sendto \r
- *\r
- * Description: \r
- * send N bytes from buf on socket to peer at adrs adrs.\r
- * Parameters: \r
- * sock(IN) - pointer to MOSAL socket object\r
- * buf(IN)\r
- * n(IN) - num of bytes to send\r
- * flags\r
- * adrs\r
- * adrs_len\r
- * \r
- * Returns: returns the number sent or -1\r
- ******************************************************************************/\r
-int MOSAL_socket_sendto (int sock,void *buf, int n,int flags, MOSAL_sockaddr_t* adrs,\r
- MOSAL_socklen_t adrs_len)\r
-{\r
- int byte_cnt = sendto( (SOCKET)sock, (const char FAR *)buf, n, 0, \r
- (const struct sockaddr FAR *)adrs, (int)adrs_len );\r
- if (byte_cnt == SOCKET_ERROR)\r
- return -1;\r
-\r
- if (byte_cnt == 0)\r
- return -1; /* socket closed */\r
- else\r
- return byte_cnt;\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_recvfrom \r
- *\r
- * Description: \r
- * read N bytes into buf on socket to peer at adrs adrs.\r
- * If ADDR is not NULL, fill in *ADDR_LEN bytes of it with tha address of\r
- * the sender, and store the actual size of the address in *ADDR_LEN.\r
- *\r
- * Parameters: \r
- * sock(IN) pointer to MOSAL socket object\r
- * buf\r
- * n - num of bytes to read\r
- * flags\r
- * adrs\r
- * adrs_len\r
- * \r
- * Returns: returns the number read or -1\r
- ******************************************************************************/\r
-int MOSAL_socket_recvfrom (int sock, void *buf, int n, int flags,\r
- MOSAL_sockaddr_t* adrs,MOSAL_socklen_t* adrs_len_p)\r
-{\r
- int byte_cnt = recvfrom( (SOCKET)sock, (char FAR*)buf, n, 0, \r
- (struct sockaddr FAR *)adrs, (int FAR *)adrs_len_p);\r
- if (byte_cnt == SOCKET_ERROR)\r
- return -1;\r
- else\r
- return byte_cnt;\r
-}\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_setsockopt \r
- *\r
- * Description: \r
- * set an option on socket or protocol level\r
- *\r
- * Parameters: \r
- * sock(IN) pointer to MOSAL socket object\r
- * level(IN) option level\r
- * optname(IN) option name\r
- * optval(IN) pointer to buffer, containing the option value\r
- * optlen(IN) buffer size\r
- * \r
- * Returns: 0 on success, -1 otherwise\r
- ******************************************************************************/\r
-int MOSAL_socket_setsockopt(int sock, MOSAL_socket_optlevel_t level, \r
- MOSAL_socket_optname_t optname, const void *optval, int optlen )\r
-{\r
- int rc = setsockopt( (SOCKET)sock, (int)level, (int)optname, \r
- (const char FAR *)optval, optlen );\r
- if (rc == SOCKET_ERROR)\r
- return -1;\r
- else\r
- return 0;\r
-}\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_socket_get_last_error \r
- *\r
- * Description: \r
- * get last error on the socket\r
- *\r
- * Parameters: \r
- * \r
- * Returns: the error number\r
- ******************************************************************************/\r
-int MOSAL_socket_get_last_error(void)\r
-{\r
- int rc = WSAGetLastError();\r
- return rc;\r
-}\r
-\r
-#if 0\r
-\r
-/******************************************************************************\r
- * Function \r
- * MOSAL_inet_aton \r
- *\r
- * Description: \r
- * convert IP address in decimal notation to 'struct in_addr'\r
- *\r
- * Parameters: \r
- * \r
- * Returns: 0 on error, IP address - otherwise\r
- ******************************************************************************/\r
-int inet_aton( const char *ip, struct in_addr *adrs )\r
-{\r
- ULONG l_ulIpAddr;\r
- struct hostent * l_pHostEntry;\r
- SOCKET sid;\r
- int rc;\r
- struct sockaddr_in srv_sock;\r
- int addr_size = sizeof(struct sockaddr);\r
- ULONG l_ulIpAddr;\r
-\r
- /* suppose, it's a decimal IP address string. Convert into binary value */\r
- l_ulIpAddr = inet_addr(ip);\r
- \r
- if (l_ulIpAddr == INADDR_NONE)\r
- { /* incorrect IP address or a URL name */\r
-\r
- /* try to resolve the name */\r
- l_pHostEntry = gethostbyname( ip_addr );\r
- if (l_pHostEntry == NULL) {\r
- DebugPrint("\nError 0x%x in call to gethostbyname()", WSAGetLastError());\r
- return 0;\r
- } \r
- /* copy the first IP address to the SOCKET structure */\r
- l_ulIpAddr = *(ULONG*)l_pHostEntry->h_addr_list[0];\r
- }\r
- \r
- *adrs->S_addr = l_ulIpAddr;\r
-\r
- return (int)l_ulIpAddr;\r
-}\r
-\r
-#endif\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef _MOSALU_SOCKET_IMP_H\r
-#define _MOSALU_SOCKET_IMP_H\r
-\r
-#ifndef __KERNEL__\r
-\r
-//#include <winsock2.h>\r
-\r
-\r
-typedef enum {MOSAL_PF_INET=PF_INET, MOSAL_PF_LOCAL=PF_UNIX } MOSAL_socket_domain_t;\r
-typedef enum {MOSAL_SOCK_STREAM=SOCK_STREAM, MOSAL_SOCK_DGRAM= SOCK_DGRAM } MOSAL_socket_type_t;\r
-typedef enum {MOSAL_IPPROTO_TCP=IPPROTO_TCP, MOSAL_IPPROTO_IP=IPPROTO_IP } MOSAL_socket_protocol_t;\r
-typedef enum {MOSAL_SOL_SOCKET=SOL_SOCKET, MOSAL_SOL_IPPROTO_TCP=IPPROTO_TCP } MOSAL_socket_optlevel_t;\r
-typedef enum {MOSAL_SO_REUSEADDR=SO_REUSEADDR } MOSAL_socket_optname_t;\r
-\r
-/* , MOSAL_SO_EXCLUSIVEADDRUSE=SO_EXCLUSIVEADDRUSE */\r
-\r
-typedef int MOSAL_socklen_t;\r
-typedef struct sockaddr_in MOSAL_sockaddr_t;\r
-\r
-#define inet_aton(ip,in_addr_p) ((in_addr_p)->s_addr=inet_addr(ip))\r
-\r
-#endif\r
-#endif\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#undef MTL_MODULE \r
-#define MTL_MODULE MOSAL\r
-\r
-#include "mosal_priv.h"\r
-#if !defined(__KERNEL__)\r
-/* user mode */\r
-#include <complib/cl_spinlock.h>\r
-#endif\r
-\r
-////////////////////////////////////////////////////////////////////////////////\r
-// Synchronization object\r
-////////////////////////////////////////////////////////////////////////////////\r
-\r
-/******************************************************************************\r
- * Function (user-mode only):\r
- * MOSAL_syncobj_init\r
- *\r
- * Description:\r
- * Init sync object\r
- *\r
- * Parameters: \r
- * obj_p(IN) pointer to synch object\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_syncobj_init(MOSAL_syncobj_t *obj_p)\r
-{\r
- obj_p->event = CreateEvent( \r
- NULL, // default security descriptor\r
- TRUE, // reset type: manual (by MOSAL_syncobj_clear)\r
- FALSE, // initial state: non-signalled\r
- NULL // object name: unnamed\r
- );\r
- if (obj_p->event == NULL)\r
- return MT_ERROR;\r
- return MT_OK;\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function (user-mode only):\r
- * MOSAL_syncobj_waiton\r
- *\r
- * Description:\r
- * cause process to sleep until synchonization object is signalled or time\r
- * expires\r
- *\r
- * Parameters: \r
- * obj_p(IN) pointer to synch object\r
- * micro_sec(IN) max time to wait in microseconds\r
- *\r
- * Returns:\r
- * MT_OK - woke up by event\r
- * MT_EAGAIN - wokeup because of timeout\r
- * \r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_syncobj_waiton(MOSAL_syncobj_t *obj_p, MT_size_t micro_sec)\r
-{\r
- DWORD status;\r
- DWORD msecs = (DWORD)(micro_sec / 1000);\r
-\r
- if (!msecs) msecs = 1;\r
- if ( micro_sec == MOSAL_SYNC_TIMEOUT_INFINITE ) \r
- status = WaitForSingleObject(\r
- obj_p->event, // handle to object\r
- INFINITE // time-out interval\r
- );\r
- else\r
- status = WaitForSingleObject(\r
- obj_p->event, // handle to object\r
- msecs // time-out interval\r
- );\r
- if (status == WAIT_OBJECT_0)\r
- return MT_OK;\r
- if (status == WAIT_TIMEOUT)\r
- return MT_ETIMEDOUT;\r
- return MT_ERROR;\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function (userl-mode only):\r
- * MOSAL_syncobj_waiton\r
- *\r
- * Description:\r
- * cause process to sleep until synchonization object is signalled or time\r
- * expires\r
- *\r
- * Parameters: \r
- * obj_p(IN) pointer to synch object\r
- * micro_sec(IN) max time to wait in microseconds\r
- *\r
- * Returns:\r
- * MT_OK - woke up by event\r
- * MT_EAGAIN - wokeup because of timeout\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_syncobj_waiton_ui(MOSAL_syncobj_t *obj_p, MT_size_t micro_sec)\r
-{\r
- return MOSAL_syncobj_waiton(obj_p, micro_sec);\r
-}\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function (user-mode only):\r
- * MOSAL_syncobj_signal\r
- *\r
- * Description:\r
- * signal the synchronization object\r
- *\r
- * Parameters: \r
- * obj_p(IN) pointer to synch object\r
- *\r
- * Returns:\r
- * N/A\r
- *\r
- ******************************************************************************/\r
-void MOSAL_syncobj_signal(MOSAL_syncobj_t *obj_p)\r
-{\r
- SetEvent( obj_p->event );\r
-}\r
-\r
-/******************************************************************************\r
- * Function (user-mode only):\r
- * MOSAL_syncobj_clear\r
- *\r
- * Description:\r
- * reset sync object (i.e. bring it to init - not-signalled -state)\r
- *\r
- * Parameters: \r
- * obj_p(IN) pointer to synch object\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-void MOSAL_syncobj_clear(MOSAL_syncobj_t *obj_p)\r
-{\r
- ResetEvent( obj_p->event );\r
-}\r
-\r
-\r
-////////////////////////////////////////////////////////////////////////////////\r
-// Semaphores\r
-////////////////////////////////////////////////////////////////////////////////\r
-\r
-\r
-/******************************************************************************\r
- * Function (user-mode only):\r
- * MOSAL_sem_init\r
- *\r
- * Description:\r
- * init semaphore\r
- *\r
- * Parameters: \r
- * sem_p(OUT) pointer to semaphore to be initialized\r
- * count(IN) max number of processes that can hold the semaphore at the same time\r
- *\r
- * Returns:\r
- *\r
- \r
-******************************************************************************/\r
-call_result_t MOSAL_sem_init(MOSAL_semaphore_t *sem_p, MT_size_t count)\r
-{\r
- sem_p->sem = CreateSemaphore(\r
- NULL, // default security descriptor\r
- (LONG)count, // initial count\r
- LONG_MAX, // maximum count\r
- NULL // object name: unnamed\r
- );\r
- if (sem_p->sem != NULL)\r
- return MT_OK;\r
- return MT_ERROR;\r
-}\r
-\r
-/******************************************************************************\r
- * Function (user-mode only):\r
- * MOSAL_sem_acq\r
- *\r
- * Description:\r
- * acquire the semaphore\r
- *\r
- * Parameters: \r
- * sem_p(IN) pointer to semaphore\r
- * block(IN) true if return immediatly if could not acquire, otherwise block if necessary\r
- *\r
- * Returns:\r
- * MT_OK - semaphore acquired\r
- * MT_EAGAIN - semaphore not acquired (only - in non-blocking mode)\r
- *\r
- *******************************************************************************/\r
-call_result_t MOSAL_sem_acq(MOSAL_semaphore_t *sem_p, MT_bool block)\r
-{\r
- DWORD status;\r
- \r
- if (block) {\r
- status = WaitForSingleObject(\r
- sem_p->sem, // handle to object\r
- INFINITE // time-out interval\r
- );\r
- }\r
- else {\r
- status = WaitForSingleObject(\r
- sem_p->sem, // handle to object\r
- 0 // time-out interval\r
- );\r
- }\r
-\r
- if (status == WAIT_OBJECT_0)\r
- return MT_OK;\r
- return MT_EAGAIN;\r
-}\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function (user-mode only):\r
- * MOSAL_sem_acq_ui\r
- *\r
- * Description:\r
- * acquire the semaphore\r
- *\r
- * Parameters: \r
- * sem_p(IN) pointer to semaphore\r
- *\r
- * Returns:\r
- *\r
- *******************************************************************************/\r
-void MOSAL_sem_acq_ui(MOSAL_semaphore_t *sem_p)\r
-{\r
- WaitForSingleObject( sem_p->sem, INFINITE );\r
-}\r
-\r
-/******************************************************************************\r
- * Function (user-mode only):\r
- * MOSAL_sem_acq_to\r
- *\r
- * Description:\r
- * acquire the semaphore with timeout\r
- *\r
- * Parameters: \r
- * sem_p(IN) pointer to semaphore\r
- * micro_sec(IN) timeout\r
- *\r
- * Returns:\r
- * MT_OK - semaphore acquired\r
- * MT_EAGAIN - semaphore not acquired because of timeout\r
- * MT_ERROR - semaphore not acquired by other reason\r
- *\r
- *******************************************************************************/\r
-call_result_t MOSAL_sem_acq_to(MOSAL_semaphore_t *sem_p, MT_size_t micro_sec)\r
-{\r
- DWORD status;\r
- DWORD msecs = (DWORD)(micro_sec / 1000);\r
-\r
- if (!msecs) msecs = 1;\r
- if ( micro_sec == MOSAL_SYNC_TIMEOUT_INFINITE ) \r
- status = WaitForSingleObject(\r
- sem_p->sem, // handle to object\r
- INFINITE // time-out interval\r
- );\r
- else\r
- status = WaitForSingleObject(\r
- sem_p->sem, // handle to object\r
- msecs // time-out interval\r
- );\r
- if (status == WAIT_OBJECT_0)\r
- return MT_OK;\r
- if (status == WAIT_TIMEOUT)\r
- return MT_EAGAIN;\r
- return MT_ERROR;\r
-}\r
-\r
-/******************************************************************************\r
- * Function (user-mode only):\r
- * MOSAL_sem_rel\r
- *\r
- * Description:\r
- * release the semaphore\r
- *\r
- * Parameters: \r
- * sem_p(IN) pointer to semaphore\r
- *\r
- * Returns:\r
- * N/A\r
- *\r
- ******************************************************************************/\r
-void MOSAL_sem_rel(MOSAL_semaphore_t *sem_p)\r
-{\r
- LONG prev;\r
- \r
- ReleaseSemaphore(\r
- sem_p->sem, // handle to semaphore\r
- 1, // count increment amount\r
- &prev // previous count\r
- );\r
-}\r
-\r
-////////////////////////////////////////////////////////////////////////////////\r
-// Mutexes\r
-////////////////////////////////////////////////////////////////////////////////\r
-\r
-typedef struct MOSAL_mutex MOSAL_mutex_t;\r
-\r
-/******************************************************************************\r
- * Function (user-mode only):\r
- * MOSAL_mutex_init\r
- *\r
- * Description:\r
- * init mutex\r
- *\r
- * Parameters: \r
- * mtx_p(OUT) pointer to mutex to be initialized\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_mutex_init(MOSAL_mutex_t *mtx_p)\r
-{\r
- mtx_p->mutex = CreateMutex(\r
- NULL, // default security descriptor\r
- FALSE, // not to acquire on creation\r
- NULL // object name: unnamed\r
- );\r
- return MT_OK;\r
-}\r
-\r
-/******************************************************************************\r
- * Function (user-mode only):\r
- * MOSAL_mutex_acq\r
- *\r
- * Description:\r
- * acquire the mutex\r
- *\r
- * Parameters: \r
- * mtx_p(IN) pointer to mutex\r
- * block(IN) true if return immediatly if could not acquire, otherwise block if necessary\r
- *\r
- * Returns:\r
- * MT_OK - mutex acquired\r
- * MT_EAGAIN - mutex not acquired (only - in non-blocking mode)\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_mutex_acq(MOSAL_mutex_t *mtx_p, MT_bool block)\r
-{\r
- DWORD status;\r
- \r
- if (block) {\r
- status = WaitForSingleObject(\r
- mtx_p->mutex, // handle to object\r
- INFINITE // time-out interval\r
- );\r
- }\r
- else {\r
- status = WaitForSingleObject(\r
- mtx_p->mutex, // handle to object\r
- 0 // time-out interval\r
- );\r
- }\r
-\r
- if (status == WAIT_OBJECT_0)\r
- return MT_OK;\r
- return MT_EAGAIN;\r
-}\r
-\r
-\r
-/******************************************************************************\r
- * Function (user-mode only):\r
- * MOSAL_mutex_acq_ui\r
- *\r
- * Description:\r
- * acquire the mutex\r
- *\r
- * Parameters: \r
- * mtx_p(IN) pointer to mutex\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-void MOSAL_mutex_acq_ui(MOSAL_mutex_t *mtx_p)\r
-{\r
- WaitForSingleObject( mtx_p->mutex, INFINITE );\r
-}\r
-\r
-/******************************************************************************\r
- * Function (kernel-mode only):\r
- * MOSAL_mutex_acq_to\r
- *\r
- * Description:\r
- * acquire the mutex\r
- *\r
- * Parameters: \r
- * mtx_p(IN) pointer to mutex\r
- * micro_sec(IN) wait interval\r
- *\r
- * Returns:\r
- * MT_OK - mutex acquired\r
- * MT_EAGAIN - mutex not acquired out of timeout\r
- * MT_ERROR - mutex not acquired out of some other error\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_mutex_acq_to(MOSAL_mutex_t *mtx_p, MT_size_t micro_sec)\r
-{\r
- DWORD status;\r
- DWORD timeout = (DWORD)((micro_sec + 999) / 1000);\r
-\r
- if ( micro_sec == MOSAL_SYNC_TIMEOUT_INFINITE ) \r
- status = WaitForSingleObject(\r
- mtx_p->mutex, // handle to object\r
- INFINITE // time-out interval\r
- );\r
- else\r
- status = WaitForSingleObject(\r
- mtx_p->mutex, // handle to object\r
- timeout // time-out interval\r
- );\r
-\r
- if (status == WAIT_OBJECT_0)\r
- return MT_OK;\r
- if (status == WAIT_TIMEOUT)\r
- return MT_ETIMEDOUT;\r
- return MT_EINTR;\r
-}\r
-\r
-\r
-\r
-/******************************************************************************\r
- * Function (user-mode only):\r
- * MOSAL_mutex_rel\r
- *\r
- * Description:\r
- * release the mutex\r
- *\r
- * Parameters: \r
- * mtx_p(IN) pointer to mutex\r
- *\r
- * Returns:\r
- * N/A\r
- *\r
- ******************************************************************************/\r
-void MOSAL_mutex_rel(MOSAL_mutex_t *mtx_p)\r
-{\r
- ReleaseMutex( mtx_p->mutex );\r
-} \r
-\r
-\r
-////////////////////////////////////////////////////////////////////////////////\r
-// Delay of execution\r
-////////////////////////////////////////////////////////////////////////////////\r
-\r
-/******************************************************************************\r
- * Function (user-mode only):\r
- * MOSAL_delay_execution\r
- *\r
- * Description:\r
- * delay execution of this control path for a the specified time period. Note\r
- * that in some implementaions it performs busy wait.\r
- *\r
- * Parameters: \r
- * time_micro(IN) required delay time in microseconds\r
- *\r
- * Returns:\r
- * N/A\r
- * \r
- ******************************************************************************/\r
-void MOSAL_delay_execution(u_int32_t time_micro)\r
-{\r
- Sleep( time_micro/1000 );\r
-}\r
-\r
-/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\r
- * \r
- * SpinLocks\r
- *\r
- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */\r
-\r
-\r
-/******************************************************************************\r
- * Function (user-mode only):\r
- * MOSAL_spinlock_init\r
- *\r
- * Description:\r
- * initialize spinlock\r
- *\r
- * Parameters: \r
- * sp(IN) MOSAL_spinlock_t*\r
- *\r
- * Returns:\r
- *\r
- ******************************************************************************/\r
-\r
-call_result_t MOSAL_spinlock_init(MOSAL_spinlock_t *sp)\r
-{\r
- cl_spinlock_init( sp );\r
- return MT_OK;\r
-}\r
-\r
-\r
-int MOSAL_sleep( u_int32_t sec )\r
-{\r
- if (sec >= MAXDWORD/1000) {\r
- MTL_ERROR1("The tout is too big\n");\r
- return 1;\r
- }\r
-\r
- Sleep(sec*1000);\r
- \r
- return 0;\r
-}\r
-\r
-//int MOSAL_usleep( u_int32_t usec )\r
-//{\r
-// usleep(usec);\r
-// return 0;\r
-//}\r
-\r
-void MOSAL_gettimeofday(MOSAL_time_t * time_p)\r
-{\r
- SYSTEMTIME tv;\r
- GetSystemTime(&tv);\r
-\r
- time_p->sec = tv.wSecond;\r
- time_p->msec = tv.wMilliseconds;\r
-}\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "mosal_priv.h"\r
-\r
-/******************************************************************************\r
- * Function:\r
- * MOSAL_thread_start \r
- *\r
- * Description:\r
- * create a tread and run a t-function in its context\r
- *\r
- * Parameters: \r
- * mto_p(IN) pointer to MOSAL thread object\r
- * flags(IN) flags for thread creation \r
- * mtf(IN) t-function \r
- * mtf_ctx(IN) t-function context\r
- *\r
- * Returns:\r
- * MT_OK - thread created\r
- * other - error on creating a thread;\r
- *\r
- ******************************************************************************/\r
-static u_int32_t WINAPI ThreadProc(\r
- LPVOID lpParameter // thread data\r
-)\r
-{\r
- MOSAL_thread_t *mto_p = (MOSAL_thread_t *)lpParameter; \r
- mto_p->res = (u_int32_t)(u_int64_t)mto_p->func(mto_p->func_ctx);\r
- MOSAL_syncobj_signal( &mto_p->sync );\r
- mto_p->th = 0;\r
- ExitThread(mto_p->res);\r
- return mto_p->res;\r
-}\r
-\r
-call_result_t MOSAL_thread_start( \r
- MOSAL_thread_t *mto_p, // pointer to MOSAL thread object\r
- u_int32_t flags, // flags for thread creation \r
- MOSAL_thread_func_t mtf, // t-function name \r
- void *mtf_ctx // t-function context (optionally) \r
- )\r
-{\r
- // sanity checks\r
- if (mtf == NULL)\r
- return MT_EINVAL;\r
-\r
- // init thread object\r
- mto_p->func = mtf;\r
- mto_p->func_ctx = mtf_ctx;\r
- MOSAL_syncobj_init( &mto_p->sync );\r
-\r
- // create and run the thread\r
- mto_p->th = CreateThread( NULL, 0, ThreadProc, mto_p, 0, NULL );\r
- if (mto_p->th == NULL)\r
- return MT_ERROR;\r
- \r
- return MT_OK;\r
-} \r
-\r
-/******************************************************************************\r
- * Function:\r
- * MOSAL_thread_kill \r
- *\r
- * Description:\r
- * terminate the tread brutally\r
- *\r
- * Parameters: \r
- * mto_p(IN) pointer to MOSAL thread object\r
- *\r
- * Returns:\r
- * MT_OK - thread terminated\r
- * MT_ERROR - a failure on thread termination\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_thread_kill( \r
- MOSAL_thread_t *mto_p // pointer to MOSAL thread object\r
- )\r
- {\r
- if (TerminateThread( mto_p->th, 0 ))\r
- return MT_OK;\r
- return MT_ERROR;\r
- }\r
-\r
-/******************************************************************************\r
- * Function:\r
- * MOSAL_thread_wait_for_exit \r
- *\r
- * Description:\r
- * create a tread and run a t-function in its context\r
- *\r
- * Parameters: \r
- * mto_p(IN) pointer to MOSAL thread object\r
- * micro_sec(IN) timeout in mcs; MOSAL_THREAD_WAIT_FOREVER means ENDLESS\r
- * exit_code(OUT) return code of the thread\r
- *\r
- * Returns:\r
- * MT_OK - thread started; for blocking mode - t-function is running;\r
- * MT_EAGAIN - for blocking mode - timeout; thread hasn't started yet; \r
- * other - error;\r
- *\r
- ******************************************************************************/\r
-call_result_t MOSAL_thread_wait_for_exit( \r
- MOSAL_thread_t *mto_p, // pointer to MOSAL thread object\r
- MT_size_t micro_sec, // timeout in mcs; MOSAL_THREAD_WAIT_FOREVER means ENDLESS \r
- u_int32_t *exit_code // return code of the thread\r
- )\r
-{\r
- call_result_t status;\r
- status = MOSAL_syncobj_waiton( &mto_p->sync, micro_sec );\r
- if (exit_code != NULL) {\r
- if (status == MT_OK )\r
- *exit_code = mto_p->res;\r
- else\r
- *exit_code = status;\r
- }\r
- return status;\r
-}\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef MPGA_headers_H\r
-#define MPGA_headers_H\r
-\r
-\r
- \r
-typedef u_int8_t nMPGA_bit_t; \r
-\r
-\r
- \r
-struct IB_LRH_p_t{ /* ***** LRH ***** Local Route Header(8 bytes)*/\r
- nMPGA_bit_t VL[0x04]; /*"Only 4 LS-bits"The virtual lane that the packet is using */\r
- nMPGA_bit_t LVer[0x04]; /*"Only 4 LS-bits"Link level protocol of the packet*/\r
- nMPGA_bit_t SL[0x04]; /*"Only 4 LS-bits"Service level requested within the subnet*/\r
- nMPGA_bit_t reserved1[0x02]; /*"Only 2 LS-bits"Transmitted as 0,ignored on receive. **internally modified** */\r
- nMPGA_bit_t LNH[0x02]; /*"Only 2 LS-bits"Identifies the headers that follow the LRH. **internally modified** */\r
- nMPGA_bit_t DLID[0x10]; /*The destination port and path on the local subnet*/\r
- nMPGA_bit_t reserved2[0x05]; /*"Only 5 LS-bits"Transmitted as 0,ignored on receive.**internally modified** */\r
- nMPGA_bit_t PktLen[0x0b]; /*"Only 11 LS-bits"The size of tha packet in four-byte words. **internally modified** */\r
- nMPGA_bit_t SLID[0x10]; /*The source port (injection point) on the local subnet*/\r
-};\r
-\r
-struct IB_GRH_p_t{ /* **** GRH **** Global Route Header(40 bytes)*/\r
- nMPGA_bit_t IPVer[0x04]; /*"Only 4 LS-bits"The version og the GRH*/\r
- nMPGA_bit_t TClass[0x08]; /*Used by IBA to communicate global service level*/\r
- nMPGA_bit_t FlowLabel[0x14]; /*"Only 20 LS-bits"Sequences of packets requiring special handl*/\r
- nMPGA_bit_t PayLen[0x10]; /*The length of the packet in bytes **internally modified** */\r
- nMPGA_bit_t NxtHdr[0x08]; /*Identifies the headers that follow the GRH*/\r
- nMPGA_bit_t HopLmt[0x08]; /*Bound on the number of hops between subnets*/\r
- nMPGA_bit_t SGID[0x80]; /*Global indentifier for the source port*/\r
- nMPGA_bit_t DGID[0x80]; /*Global indentifier for the detination port*/\r
-};\r
-\r
-struct IB_BTH_p_t{ /* **** BTH **** Base Transport Header (12 bytes)*/\r
- nMPGA_bit_t OpCode[0x08]; /*IBA packet type and which extentions follows **internally modified** */\r
- nMPGA_bit_t SE; /*"Only 1 LS-bit"If an event sould be gen by responder or not*/\r
- nMPGA_bit_t M; /*"Only 1 LS-bit"Communication migration state*/\r
- nMPGA_bit_t PadCnt[0x02]; /*"Only 2 LS-bits"Number of bytes that align to 4 byte boundary **internally modified** */\r
- nMPGA_bit_t TVer[0x04]; /*"Only 4 LS-bits"IBA transport headers version. **internally modified** */\r
- nMPGA_bit_t P_KEY[0x10]; /*Logical partition associated with this packet*/\r
- nMPGA_bit_t reserved1[0x08]; /*Transmitted as 0,ignored on receive. Not included in the icrc. **internally modified** */\r
- nMPGA_bit_t DestQP[0x18]; /*"Only 24 LS-bits"Destination work queu pair number*/\r
- nMPGA_bit_t A; /*"Only 1 LS-bit"If an ack should be returnd by the responder*/\r
- nMPGA_bit_t reserved2[0x07]; /*"only 7 LS-bits"Transmitted as 0,ignored .included in icrc. **internally modified** */\r
- nMPGA_bit_t PSN[0x18]; /*"Only 24 LS-bits"detect a missing or duplicate packet*/\r
-};\r
-\r
-struct IB_RDETH_p_t{ /* **** RDETH **** (4 bytes)*/\r
- /*Reliable Datagram Extended Transport Header*/\r
- nMPGA_bit_t reserved1[0x08]; /*Transmitted as 0,ignored on receive.*/\r
- nMPGA_bit_t EECnxt[0x18]; /*"Only 24 LS-bits"Which end to end context for this packet*/\r
-};\r
-\r
-struct IB_DETH_p_t{ /* **** DETH ****(8 bytes)*/\r
- /*Datagram Extended Transport Header */\r
- nMPGA_bit_t Q_Key[0x20]; /*For an authorize access to destination queue*/\r
- nMPGA_bit_t reserved1[0x08]; /*ransmitted as 0,ignored on receive.*/\r
- nMPGA_bit_t SrcQP[0x18]; /*"Only 24 LS-bits"Work queu nuber at the source*/\r
-};\r
-\r
-struct IB_RETH_p_t{ /* **** RETH ****(16 bytes)*/\r
- /*RDMA Extended Transport Header */\r
- nMPGA_bit_t VA[0x40]; /*Virtual address of the RDMA operation*/\r
- nMPGA_bit_t R_Key[0x20]; /*Remote key that authorize access for the RDMA operation*/\r
- nMPGA_bit_t DMALen[0x20]; /*The length of the DMA operation*/\r
-};\r
-\r
-struct IB_AtomicETH_p_t{ /* **** AtomicETH ****(28 bytes)*/\r
- /*Atomic Extended Transport Header */\r
- nMPGA_bit_t VA[0x40]; /*Remote virtual address */\r
- nMPGA_bit_t R_Key[0x20]; /*Remote key that authorize access to the remote virtual address*/\r
- nMPGA_bit_t SwapDt[0x40]; /*An operand in atomic operations*/\r
- nMPGA_bit_t CmpDt[0x40]; /*An operand in cmpswap atomic operation*/\r
-};\r
-\r
-struct IB_AETH_p_t{ /* *** ACK ****(4 bytes)*/\r
- /*ACK Extended Transport Header */\r
- nMPGA_bit_t Syndrome[0x08]; /*Indicates ACK or NAK plus additional info*/\r
- nMPGA_bit_t MSN[0x18]; /*Sequence number of the last message completed*/\r
-};\r
-\r
-struct IB_AtomicAckETH_p_t{ /* **** AtomicAckETH ****(8 bytes)*/\r
- /* Atomic ACK Extended Transport Header */\r
- nMPGA_bit_t OrigRemDt[0x40]; /*Return oprand in atomic operation and contains the data*/\r
- /*in the remote memory location before the atomic operation*/\r
-};\r
-\r
-struct IB_ImmDt_p_t{ /* **** Immediate Data **** (4 bytes)*/\r
- /* Contains the additional data that is placed in the */\r
- nMPGA_bit_t ImmDt[0x20]; /* received Completion Queue Element (CQE). */\r
- /* The ImmDt is Only in Send or RDMA-Write packets. */\r
-};\r
-\r
-\r
-\r
-/*IBA LOCAL*/\r
-struct MPGA_rc_send_first_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_rc_send_middle_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_rc_send_last_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_rc_send_last_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-struct MPGA_rc_send_only_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_rc_send_only_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-\r
-/*RDMA Write types*/\r
-struct MPGA_rc_write_first_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
-};\r
-\r
-struct MPGA_rc_write_middle_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_rc_write_last_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_rc_write_last_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-struct MPGA_rc_write_only_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
-};\r
-\r
-struct MPGA_rc_write_only_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-/*RDMA read types*/\r
-struct MPGA_rc_read_req_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
-};\r
-\r
-struct MPGA_rc_read_res_first_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_AETH_p_t IB_AETH_P;\r
-};\r
-\r
-struct MPGA_rc_read_res_middle_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_rc_read_res_last_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_AETH_p_t IB_AETH_P;\r
-};\r
-\r
-struct MPGA_rc_read_res_only_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_AETH_p_t IB_AETH_P;\r
-};\r
-\r
-/* Other Types*/\r
-struct MPGA_rc_ack_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_AETH_p_t IB_AETH_P;\r
-};\r
-\r
-struct MPGA_rc_atomic_ack_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_AETH_p_t IB_AETH_P;\r
- struct IB_AtomicAckETH_p_t IB_AtomicAckETH;\r
-};\r
-\r
-struct MPGA_rc_CmpSwap_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_AtomicETH_p_t IB_AtomicETH;\r
-};\r
-\r
-struct MPGA_rc_FetchAdd_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_AtomicETH_p_t IB_AtomicETH;\r
-};\r
-\r
-/* Unreliable Connection */\r
-/*Send Types*/\r
-struct MPGA_uc_send_first_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_uc_send_middle_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_uc_send_last_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_uc_send_last_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-struct MPGA_uc_send_only_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_uc_send_only_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-/*RDMA Write types*/\r
-struct MPGA_uc_write_first_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
-};\r
-\r
-struct MPGA_uc_write_middle_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_uc_write_last_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_uc_write_last_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-struct MPGA_uc_write_only_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
-};\r
-\r
-struct MPGA_uc_write_only_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-/* Reliable Datagram */\r
-\r
-/*Send Types*/\r
-struct MPGA_rd_send_first_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
-};\r
-\r
-struct MPGA_rd_send_middle_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
-};\r
-\r
-struct MPGA_rd_send_last_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
-};\r
-\r
-struct MPGA_rd_send_last_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-struct MPGA_rd_send_only_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
-};\r
-\r
-struct MPGA_rd_send_only_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-\r
-/*RDMA Write types*/\r
-struct MPGA_rd_write_first_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
-};\r
-\r
-struct MPGA_rd_write_middle_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
-};\r
-\r
-struct MPGA_rd_write_last_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
-};\r
-\r
-struct MPGA_rd_write_last_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-struct MPGA_rd_write_only_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
-};\r
-\r
-struct MPGA_rd_write_only_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-struct MPGA_rd_read_req_p_t{ \r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
-};\r
-\r
-struct MPGA_rd_read_res_first_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_AETH_p_t IB_AETH_P;\r
-};\r
-\r
-struct MPGA_rd_read_res_middle_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
-};\r
-\r
-struct MPGA_rd_read_res_last_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_AETH_p_t IB_AETH_P;\r
-};\r
-\r
-struct MPGA_rd_read_res_only_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_AETH_p_t IB_AETH_P;\r
-};\r
-\r
-\r
-struct MPGA_rd_ack_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_AETH_p_t IB_AETH_P;\r
-};\r
-\r
-struct MPGA_rd_atomic_ack_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_AETH_p_t IB_AETH_P;\r
- struct IB_AtomicAckETH_p_t IB_AtomicAckETH_P;\r
-};\r
-\r
-struct MPGA_rd_CmpSwap_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
- struct IB_AtomicETH_p_t IB_AtomicETH_P;\r
-};\r
-\r
-struct MPGA_rd_FetchAdd_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
- struct IB_AtomicETH_p_t IB_AtomicETH_P;\r
-};\r
-\r
-struct MPGA_rd_resync_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
-};\r
-\r
-/* Unreliable Datagram */\r
-\r
-struct MPGA_ud_send_only_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
-};\r
-\r
-struct MPGA_ud_send_only_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-\r
-\r
-\r
-/*IBA GLOBAL*/\r
-struct MPGA_G_rc_send_first_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_G_rc_send_middle_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_G_rc_send_last_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_G_rc_send_last_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-struct MPGA_G_rc_send_only_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_G_rc_send_only_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-\r
-/*RDMA Write types*/\r
-struct MPGA_G_rc_write_first_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
-};\r
-\r
-struct MPGA_G_rc_write_middle_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_G_rc_write_last_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_G_rc_write_last_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-struct MPGA_G_rc_write_only_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
-};\r
-\r
-struct MPGA_G_rc_write_only_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-/*RDMA read types*/\r
-struct MPGA_G_rc_read_req_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
-};\r
-\r
-struct MPGA_G_rc_read_res_first_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_AETH_p_t IB_AETH_P;\r
-};\r
-\r
-struct MPGA_G_rc_read_res_middle_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_G_rc_read_res_last_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_AETH_p_t IB_AETH_P;\r
-};\r
-\r
-struct MPGA_G_rc_read_res_only_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_AETH_p_t IB_AETH_P;\r
-};\r
-\r
-/* Other Types*/\r
-struct MPGA_G_rc_ack_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_AETH_p_t IB_AETH_P;\r
-};\r
-\r
-struct MPGA_G_rc_atomic_ack_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_AETH_p_t IB_AETH_P;\r
- struct IB_AtomicAckETH_p_t IB_AtomicAckETH;\r
-};\r
-\r
-struct MPGA_G_rc_CmpSwap_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_AtomicETH_p_t IB_AtomicETH;\r
-};\r
-\r
-struct MPGA_G_rc_FetchAdd_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_AtomicETH_p_t IB_AtomicETH;\r
-};\r
-\r
-/* Unreliable Connection */\r
-/*Send Types*/\r
-struct MPGA_G_uc_send_first_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_G_uc_send_middle_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_G_uc_send_last_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_G_uc_send_last_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-struct MPGA_G_uc_send_only_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_G_uc_send_only_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-/*RDMA Write types*/\r
-struct MPGA_G_uc_write_first_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
-};\r
-\r
-struct MPGA_G_uc_write_middle_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_G_uc_write_last_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
-};\r
-\r
-struct MPGA_G_uc_write_last_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-struct MPGA_G_uc_write_only_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
-};\r
-\r
-struct MPGA_G_uc_write_only_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-/* Reliable Datagram */\r
-\r
-/*Send Types*/\r
-struct MPGA_G_rd_send_first_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
-};\r
-\r
-struct MPGA_G_rd_send_middle_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
-};\r
-\r
-struct MPGA_G_rd_send_last_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
-};\r
-\r
-struct MPGA_G_rd_send_last_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-struct MPGA_G_rd_send_only_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
-};\r
-\r
-struct MPGA_G_rd_send_only_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-\r
-/*RDMA Write types*/\r
-struct MPGA_G_rd_write_first_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
-};\r
-\r
-struct MPGA_G_rd_write_middle_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
-};\r
-\r
-struct MPGA_G_rd_write_last_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
-};\r
-\r
-struct MPGA_G_rd_write_last_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-struct MPGA_G_rd_write_only_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
-};\r
-\r
-struct MPGA_G_rd_write_only_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-struct MPGA_G_rd_read_req_p_t{ \r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
- struct IB_RETH_p_t IB_RETH_P;\r
-};\r
-\r
-struct MPGA_G_rd_read_res_first_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_AETH_p_t IB_AETH_P;\r
-};\r
-\r
-struct MPGA_G_rd_read_res_middle_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
-};\r
-\r
-struct MPGA_G_rd_read_res_last_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_AETH_p_t IB_AETH_P;\r
-};\r
-\r
-struct MPGA_G_rd_read_res_only_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_AETH_p_t IB_AETH_P;\r
-};\r
-\r
-\r
-struct MPGA_G_rd_ack_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_AETH_p_t IB_AETH_P;\r
-};\r
-\r
-struct MPGA_G_rd_atomic_ack_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_AETH_p_t IB_AETH_P;\r
- struct IB_AtomicAckETH_p_t IB_AtomicAckETH_P;\r
-};\r
-\r
-struct MPGA_G_rd_CmpSwap_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
- struct IB_AtomicETH_p_t IB_AtomicETH_P;\r
-};\r
-\r
-struct MPGA_G_rd_FetchAdd_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
- struct IB_AtomicETH_p_t IB_AtomicETH_P;\r
-};\r
-\r
-struct MPGA_G_rd_resync_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_RDETH_p_t IB_RDETH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
-};\r
-\r
-/* Unreliable Datagram */\r
-\r
-struct MPGA_G_ud_send_only_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
-};\r
-\r
-struct MPGA_G_ud_send_only_ImmDt_p_t{\r
- struct IB_LRH_p_t IB_LRH_P;\r
- struct IB_GRH_p_t IB_GRH_P;\r
- struct IB_BTH_p_t IB_BTH_P;\r
- struct IB_DETH_p_t IB_DETH_P;\r
- struct IB_ImmDt_p_t IB_ImmDt_P;\r
-};\r
-\r
-\r
-union MPGA_headers_p_t{\r
- /* IBA LOCAL*/\r
- /* RC - Reliable Connection - opcode prefix 000*/ /* OpCode */ \r
- struct MPGA_rc_send_first_p_t MPGA_rc_send_first_p; /* 00000 */\r
- struct MPGA_rc_send_middle_p_t MPGA_rc_send_middle_p; /* 00001 */\r
- struct MPGA_rc_send_last_p_t MPGA_rc_send_last_p; /* 00010 */\r
- struct MPGA_rc_send_last_ImmDt_p_t MPGA_rc_send_last_ImmDt_p; /* 00011 */\r
- struct MPGA_rc_send_only_p_t MPGA_rc_send_only_p; /* 00100 */\r
- struct MPGA_rc_send_only_ImmDt_p_t MPGA_rc_send_only_ImmDt_p; /* 00101 */\r
-\r
- struct MPGA_rc_write_first_p_t MPGA_rc_write_first_p; /* 00110 */\r
- struct MPGA_rc_write_middle_p_t MPGA_rc_write_middle_p; /* 00111 */\r
- struct MPGA_rc_write_last_p_t MPGA_rc_write_last_p; /* 01000 */\r
- struct MPGA_rc_write_last_ImmDt_p_t MPGA_rc_write_last_ImmDt_p;/* 01001 */\r
- struct MPGA_rc_write_only_p_t MPGA_rc_write_only_p; /* 01010 */\r
- struct MPGA_rc_write_only_ImmDt_p_t MPGA_rc_write_only_ImmDt_p;/* 01011 */\r
-\r
- struct MPGA_rc_read_req_p_t MPGA_rc_read_req_p; /* 01100 */\r
- struct MPGA_rc_read_res_first_p_t MPGA_rc_read_res_first_p; /* 01101 */\r
- struct MPGA_rc_read_res_middle_p_t MPGA_rc_read_res_middle_p; /* 01110 */\r
- struct MPGA_rc_read_res_last_p_t MPGA_rc_read_res_last_p; /* 01111 */\r
- struct MPGA_rc_read_res_only_p_t MPGA_rc_read_res_only_p; /* 10000 */\r
- \r
- struct MPGA_rc_ack_p_t MPGA_rc_ack_p; /* 10001 */\r
- struct MPGA_rc_atomic_ack_p_t MPGA_rc_atomic_ack_p; /* 10010 */\r
- struct MPGA_rc_CmpSwap_p_t MPGA_rc_CmpSwap_p; /* 10011 */\r
- struct MPGA_rc_FetchAdd_p_t MPGA_rc_FetchAdd_p; /* 10100 */\r
- \r
- /* UC - Unreliable Connection - opcode prefix 001*/ \r
- struct MPGA_uc_send_first_p_t MPGA_uc_send_first_p; /* 00000 */\r
- struct MPGA_uc_send_middle_p_t MPGA_uc_send_middle_p; /* 00001 */\r
- struct MPGA_uc_send_last_p_t MPGA_uc_send_last_p; /* 00010 */\r
- struct MPGA_uc_send_last_ImmDt_p_t MPGA_uc_send_last_ImmDt_p; /* 00011 */\r
- struct MPGA_uc_send_only_p_t MPGA_uc_send_only_p; /* 00100 */\r
- struct MPGA_uc_send_only_ImmDt_p_t MPGA_uc_send_only_ImmDt_p; /* 00101 */\r
- \r
- struct MPGA_uc_write_first_p_t MPGA_uc_write_first_p; /* 00110 */\r
- struct MPGA_uc_write_middle_p_t MPGA_uc_write_middle_p; /* 00111 */\r
- struct MPGA_uc_write_last_p_t MPGA_uc_write_last_p; /* 01000 */\r
- struct MPGA_uc_write_last_ImmDt_p_t MPGA_uc_write_last_ImmDt_p;/* 01001 */\r
- struct MPGA_uc_write_only_p_t MPGA_uc_write_only_p; /* 01010 */\r
- struct MPGA_uc_write_only_ImmDt_p_t MPGA_uc_write_only_ImmDt_p;/* 01011 */\r
- \r
- /* RD - Reliable Datagram - opcode prefix 010*/ \r
- struct MPGA_rd_send_first_p_t MPGA_rd_send_first_p; /* 00000 */\r
- struct MPGA_rd_send_middle_p_t MPGA_rd_send_middle_p; /* 00001 */\r
- struct MPGA_rd_send_last_p_t MPGA_rd_send_last_p; /* 00010 */\r
- struct MPGA_rd_send_last_ImmDt_p_t MPGA_rd_send_last_ImmDt_p; /* 00011 */\r
- struct MPGA_rd_send_only_p_t MPGA_rd_send_only_p; /* 00100 */\r
- struct MPGA_rd_send_only_ImmDt_p_t MPGA_rd_send_only_ImmDt_p; /* 00101 */\r
- \r
- struct MPGA_rd_write_first_p_t MPGA_rd_write_first_p; /* 00110 */\r
- struct MPGA_rd_write_middle_p_t MPGA_rd_write_middle_p; /* 00111 */\r
- struct MPGA_rd_write_last_p_t MPGA_rd_write_last_p; /* 01000 */\r
- struct MPGA_rd_write_last_ImmDt_p_t MPGA_rd_write_last_ImmDt_p;/* 01001 */\r
- struct MPGA_rd_write_only_p_t MPGA_rd_write_only_p; /* 01010 */\r
- struct MPGA_rd_write_only_ImmDt_p_t MPGA_rd_write_only_ImmDt_p;/* 01011 */\r
- \r
- struct MPGA_rd_read_req_p_t MPGA_rd_read_req_p; /* 01100 */\r
- struct MPGA_rd_read_res_first_p_t MPGA_rd_read_res_first_p; /* 01101 */\r
- struct MPGA_rd_read_res_middle_p_t MPGA_rd_read_res_middle_p; /* 01110 */\r
- struct MPGA_rd_read_res_last_p_t MPGA_rd_read_res_last_p; /* 01111 */\r
- struct MPGA_rd_read_res_only_p_t MPGA_rd_read_res_only_p; /* 10000 */\r
- \r
- struct MPGA_rd_ack_p_t MPGA_rd_ack_p; /* 10001 */\r
- struct MPGA_rd_atomic_ack_p_t MPGA_rd_atomic_ack_p; /* 10010 */\r
- struct MPGA_rd_CmpSwap_p_t MPGA_rd_CmpSwap_p; /* 10011 */\r
- struct MPGA_rd_FetchAdd_p_t MPGA_rd_FetchAdd_p; /* 10100 */\r
- struct MPGA_rd_resync_p_t MPGA_rd_resync_p; /* 10101 */\r
- \r
- /* UD - UnReliable Datagram - opcode prefix 011*/ \r
- struct MPGA_ud_send_only_p_t MPGA_ud_send_only_p; /* 00100 */\r
- struct MPGA_ud_send_only_ImmDt_p_t MPGA_ud_send_only_ImmDt_p; /* 00101 */\r
-\r
-\r
- /*IBA GLOBAL*/\r
- /* RC - Reliable Connection - opcode prefix 000*/ /* OpCode */ \r
- struct MPGA_G_rc_send_first_p_t MPGA_G_rc_send_first_p; /* 00000 */\r
- struct MPGA_G_rc_send_middle_p_t MPGA_G_rc_send_middle_p; /* 00001 */\r
- struct MPGA_G_rc_send_last_p_t MPGA_G_rc_send_last_p; /* 00010 */\r
- struct MPGA_G_rc_send_last_ImmDt_p_t MPGA_G_rc_send_last_ImmDt_p; /* 00011 */\r
- struct MPGA_G_rc_send_only_p_t MPGA_G_rc_send_only_p; /* 00100 */\r
- struct MPGA_G_rc_send_only_ImmDt_p_t MPGA_G_rc_send_only_ImmDt_p; /* 00101 */\r
-\r
- struct MPGA_G_rc_write_first_p_t MPGA_G_rc_write_first_p; /* 00110 */\r
- struct MPGA_G_rc_write_middle_p_t MPGA_G_rc_write_middle_p; /* 00111 */\r
- struct MPGA_G_rc_write_last_p_t MPGA_G_rc_write_last_p; /* 01000 */\r
- struct MPGA_G_rc_write_last_ImmDt_p_t MPGA_G_rc_write_last_ImmDt_p;/* 01001 */\r
- struct MPGA_G_rc_write_only_p_t MPGA_G_rc_write_only_p; /* 01010 */\r
- struct MPGA_G_rc_write_only_ImmDt_p_t MPGA_G_rc_write_only_ImmDt_p;/* 01011 */\r
-\r
- struct MPGA_G_rc_read_req_p_t MPGA_G_rc_read_req_p; /* 01100 */\r
- struct MPGA_G_rc_read_res_first_p_t MPGA_G_rc_read_res_first_p; /* 01101 */\r
- struct MPGA_G_rc_read_res_middle_p_t MPGA_G_rc_read_res_middle_p; /* 01110 */\r
- struct MPGA_G_rc_read_res_last_p_t MPGA_G_rc_read_res_last_p; /* 01111 */\r
- struct MPGA_G_rc_read_res_only_p_t MPGA_G_rc_read_res_only_p; /* 10000 */\r
- \r
- struct MPGA_G_rc_ack_p_t MPGA_G_rc_ack_p; /* 10001 */\r
- struct MPGA_G_rc_atomic_ack_p_t MPGA_G_rc_atomic_ack_p; /* 10010 */\r
- struct MPGA_G_rc_CmpSwap_p_t MPGA_G_rc_CmpSwap_p; /* 10011 */\r
- struct MPGA_G_rc_FetchAdd_p_t MPGA_G_rc_FetchAdd_p; /* 10100 */\r
- \r
- /* UC - Unreliable Connection - opcode prefix 001*/ \r
- struct MPGA_G_uc_send_first_p_t MPGA_G_uc_send_first_p; /* 00000 */\r
- struct MPGA_G_uc_send_middle_p_t MPGA_G_uc_send_middle_p; /* 00001 */\r
- struct MPGA_G_uc_send_last_p_t MPGA_G_uc_send_last_p; /* 00010 */\r
- struct MPGA_G_uc_send_last_ImmDt_p_t MPGA_G_uc_send_last_ImmDt_p; /* 00011 */\r
- struct MPGA_G_uc_send_only_p_t MPGA_G_uc_send_only_p; /* 00100 */\r
- struct MPGA_G_uc_send_only_ImmDt_p_t MPGA_G_uc_send_only_ImmDt_p; /* 00101 */\r
- \r
- struct MPGA_G_uc_write_first_p_t MPGA_G_uc_write_first_p; /* 00110 */\r
- struct MPGA_G_uc_write_middle_p_t MPGA_G_uc_write_middle_p; /* 00111 */\r
- struct MPGA_G_uc_write_last_p_t MPGA_G_uc_write_last_p; /* 01000 */\r
- struct MPGA_G_uc_write_last_ImmDt_p_t MPGA_G_uc_write_last_ImmDt_p;/* 01001 */\r
- struct MPGA_G_uc_write_only_p_t MPGA_G_uc_write_only_p; /* 01010 */\r
- struct MPGA_G_uc_write_only_ImmDt_p_t MPGA_G_uc_write_only_ImmDt_p;/* 01011 */\r
- \r
- /* RD - Reliable Datagram - opcode prefix 010*/ \r
- struct MPGA_G_rd_send_first_p_t MPGA_G_rd_send_first_p; /* 00000 */\r
- struct MPGA_G_rd_send_middle_p_t MPGA_G_rd_send_middle_p; /* 00001 */\r
- struct MPGA_G_rd_send_last_p_t MPGA_G_rd_send_last_p; /* 00010 */\r
- struct MPGA_G_rd_send_last_ImmDt_p_t MPGA_G_rd_send_last_ImmDt_p; /* 00011 */\r
- struct MPGA_G_rd_send_only_p_t MPGA_G_rd_send_only_p; /* 00100 */\r
- struct MPGA_G_rd_send_only_ImmDt_p_t MPGA_G_rd_send_only_ImmDt_p; /* 00101 */\r
- \r
- struct MPGA_G_rd_write_first_p_t MPGA_G_rd_write_first_p; /* 00110 */\r
- struct MPGA_G_rd_write_middle_p_t MPGA_G_rd_write_middle_p; /* 00111 */\r
- struct MPGA_G_rd_write_last_p_t MPGA_G_rd_write_last_p; /* 01000 */\r
- struct MPGA_G_rd_write_last_ImmDt_p_t MPGA_G_rd_write_last_ImmDt_p;/* 01001 */\r
- struct MPGA_G_rd_write_only_p_t MPGA_G_rd_write_only_p; /* 01010 */\r
- struct MPGA_G_rd_write_only_ImmDt_p_t MPGA_G_rd_write_only_ImmDt_p;/* 01011 */\r
- \r
- struct MPGA_G_rd_read_req_p_t MPGA_G_rd_read_req_p; /* 01100 */\r
- struct MPGA_G_rd_read_res_first_p_t MPGA_G_rd_read_res_first_p; /* 01101 */\r
- struct MPGA_G_rd_read_res_middle_p_t MPGA_G_rd_read_res_middle_p; /* 01110 */\r
- struct MPGA_G_rd_read_res_last_p_t MPGA_G_rd_read_res_last_p; /* 01111 */\r
- struct MPGA_G_rd_read_res_only_p_t MPGA_G_rd_read_res_only_p; /* 10000 */\r
- \r
- struct MPGA_G_rd_ack_p_t MPGA_G_rd_ack_p; /* 10001 */\r
- struct MPGA_G_rd_atomic_ack_p_t MPGA_G_rd_atomic_ack_p; /* 10010 */\r
- struct MPGA_G_rd_CmpSwap_p_t MPGA_G_rd_CmpSwap_p; /* 10011 */\r
- struct MPGA_G_rd_FetchAdd_p_t MPGA_G_rd_FetchAdd_p; /* 10100 */\r
- struct MPGA_G_rd_resync_p_t MPGA_G_rd_resync_p; /* 10101 */\r
- \r
- /* UD - UnReliable Datagram - opcode prefix 011*/ \r
- struct MPGA_G_ud_send_only_p_t MPGA_G_ud_send_only_p; /* 00100 */\r
- struct MPGA_G_ud_send_only_ImmDt_p_t MPGA_G_ud_send_only_ImmDt_p; /* 00101 */\r
-\r
-\r
-};\r
-\r
-\r
-\r
-/* IBA LOCAL */\r
-/* RC - Reliable Connected types */\r
-/*-------------------------------*/\r
-/*Send Types*/\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_rc_send_first_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_rc_send_middle_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_rc_send_last_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_rc_send_last_ImmDt_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_rc_send_only_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_rc_send_only_ImmDt_t;\r
-\r
-\r
-/*RDMA Write types*/\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RETH_st IB_RETH;\r
-} MPGA_rc_write_first_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_rc_write_middle_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_rc_write_last_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_rc_write_last_ImmDt_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RETH_st IB_RETH;\r
-} MPGA_rc_write_only_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RETH_st IB_RETH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_rc_write_only_ImmDt_t;\r
-/*RDMA read types*/\r
-typedef struct { \r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RETH_st IB_RETH;\r
-} MPGA_rc_read_req_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_AETH_st IB_AETH;\r
-} MPGA_rc_read_res_first_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_rc_read_res_middle_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_AETH_st IB_AETH;\r
-} MPGA_rc_read_res_last_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_AETH_st IB_AETH;\r
-} MPGA_rc_read_res_only_t;\r
-/* Other Types*/\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_AETH_st IB_AETH;\r
-} MPGA_rc_ack_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_AETH_st IB_AETH;\r
- IB_AtomicAckETH_st IB_AtomicAckETH;\r
-} MPGA_rc_atomic_ack_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_AtomicETH_st IB_AtomicETH;\r
-} MPGA_rc_CmpSwap_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_AtomicETH_st IB_AtomicETH;\r
-} MPGA_rc_FetchAdd_t;\r
-\r
-/* Unreliable Connection */\r
-/*Send Types*/\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_uc_send_first_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_uc_send_middle_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_uc_send_last_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_uc_send_last_ImmDt_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_uc_send_only_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_uc_send_only_ImmDt_t;\r
-\r
-/*RDMA Write types*/\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RETH_st IB_RETH;\r
-} MPGA_uc_write_first_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_uc_write_middle_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_uc_write_last_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_uc_write_last_ImmDt_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RETH_st IB_RETH;\r
-} MPGA_uc_write_only_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RETH_st IB_RETH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_uc_write_only_ImmDt_t;\r
-\r
-/* Reliable Datagram */\r
-\r
-/*Send Types*/\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
-} MPGA_rd_send_first_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
-} MPGA_rd_send_middle_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
-} MPGA_rd_send_last_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_rd_send_last_ImmDt_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
-} MPGA_rd_send_only_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_rd_send_only_ImmDt_t;\r
-\r
-\r
-/*RDMA Write types*/\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
- IB_RETH_st IB_RETH;\r
-} MPGA_rd_write_first_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
-} MPGA_rd_write_middle_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
-} MPGA_rd_write_last_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_rd_write_last_ImmDt_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
- IB_RETH_st IB_RETH;\r
-} MPGA_rd_write_only_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
- IB_RETH_st IB_RETH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_rd_write_only_ImmDt_t;\r
-\r
-typedef struct { \r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
- IB_RETH_st IB_RETH;\r
-} MPGA_rd_read_req_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_AETH_st IB_AETH;\r
-} MPGA_rd_read_res_first_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
-} MPGA_rd_read_res_middle_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_AETH_st IB_AETH;\r
-} MPGA_rd_read_res_last_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_AETH_st IB_AETH;\r
-} MPGA_rd_read_res_only_t;\r
-\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_AETH_st IB_AETH;\r
-} MPGA_rd_ack_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_AETH_st IB_AETH;\r
- IB_AtomicAckETH_st IB_AtomicAckETH;\r
-} MPGA_rd_atomic_ack_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
- IB_AtomicETH_st IB_AtomicETH;\r
-} MPGA_rd_CmpSwap_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
- IB_AtomicETH_st IB_AtomicETH;\r
-} MPGA_rd_FetchAdd_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
-} MPGA_rd_resync_t;\r
-\r
-/* Unreliable Datagram */\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_DETH_st IB_DETH;\r
-} MPGA_ud_send_only_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_BTH_st IB_BTH;\r
- IB_DETH_st IB_DETH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_ud_send_only_ImmDt_t;\r
-\r
-\r
-/* IBA GLOBAL */\r
-/* RC - Reliable Connected types */\r
-/*-------------------------------*/\r
-/*Send Types*/\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_G_rc_send_first_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_G_rc_send_middle_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_G_rc_send_last_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_G_rc_send_last_ImmDt_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_G_rc_send_only_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_G_rc_send_only_ImmDt_t;\r
-\r
-\r
-/*RDMA Write types*/\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RETH_st IB_RETH;\r
-} MPGA_G_rc_write_first_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_G_rc_write_middle_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_G_rc_write_last_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_G_rc_write_last_ImmDt_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RETH_st IB_RETH;\r
-} MPGA_G_rc_write_only_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RETH_st IB_RETH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_G_rc_write_only_ImmDt_t;\r
-/*RDMA read types*/\r
-typedef struct { \r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RETH_st IB_RETH;\r
-} MPGA_G_rc_read_req_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_AETH_st IB_AETH;\r
-} MPGA_G_rc_read_res_first_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_G_rc_read_res_middle_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_AETH_st IB_AETH;\r
-} MPGA_G_rc_read_res_last_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_AETH_st IB_AETH;\r
-} MPGA_G_rc_read_res_only_t;\r
-/* Other Types*/\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_AETH_st IB_AETH;\r
-} MPGA_G_rc_ack_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_AETH_st IB_AETH;\r
- IB_AtomicAckETH_st IB_AtomicAckETH;\r
-} MPGA_G_rc_atomic_ack_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_AtomicETH_st IB_AtomicETH;\r
-} MPGA_G_rc_CmpSwap_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_AtomicETH_st IB_AtomicETH;\r
-} MPGA_G_rc_FetchAdd_t;\r
-\r
-/* Unreliable Connection */\r
-/*Send Types*/\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_G_uc_send_first_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_G_uc_send_middle_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_G_uc_send_last_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_G_uc_send_last_ImmDt_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_G_uc_send_only_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_G_uc_send_only_ImmDt_t;\r
-\r
-/*RDMA Write types*/\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RETH_st IB_RETH;\r
-} MPGA_G_uc_write_first_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_G_uc_write_middle_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
-} MPGA_G_uc_write_last_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_G_uc_write_last_ImmDt_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RETH_st IB_RETH;\r
-} MPGA_G_uc_write_only_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RETH_st IB_RETH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_G_uc_write_only_ImmDt_t;\r
-\r
-/* Reliable Datagram */\r
-\r
-/*Send Types*/\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
-} MPGA_G_rd_send_first_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
-} MPGA_G_rd_send_middle_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
-} MPGA_G_rd_send_last_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_G_rd_send_last_ImmDt_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
-} MPGA_G_rd_send_only_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_G_rd_send_only_ImmDt_t;\r
-\r
-\r
-/*RDMA Write types*/\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
- IB_RETH_st IB_RETH;\r
-} MPGA_G_rd_write_first_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
-} MPGA_G_rd_write_middle_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
-} MPGA_G_rd_write_last_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_G_rd_write_last_ImmDt_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
- IB_RETH_st IB_RETH;\r
-} MPGA_G_rd_write_only_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
- IB_RETH_st IB_RETH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_G_rd_write_only_ImmDt_t;\r
-\r
-typedef struct { \r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
- IB_RETH_st IB_RETH;\r
-} MPGA_G_rd_read_req_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_AETH_st IB_AETH;\r
-} MPGA_G_rd_read_res_first_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
-} MPGA_G_rd_read_res_middle_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_AETH_st IB_AETH;\r
-} MPGA_G_rd_read_res_last_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_AETH_st IB_AETH;\r
-} MPGA_G_rd_read_res_only_t;\r
-\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_AETH_st IB_AETH;\r
-} MPGA_G_rd_ack_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_AETH_st IB_AETH;\r
- IB_AtomicAckETH_st IB_AtomicAckETH;\r
-} MPGA_G_rd_atomic_ack_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
- IB_AtomicETH_st IB_AtomicETH;\r
-} MPGA_G_rd_CmpSwap_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
- IB_AtomicETH_st IB_AtomicETH;\r
-} MPGA_G_rd_FetchAdd_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_RDETH_st IB_RDETH;\r
- IB_DETH_st IB_DETH;\r
-} MPGA_G_rd_resync_t;\r
-\r
-/* Unreliable Datagram */\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_DETH_st IB_DETH;\r
-} MPGA_G_ud_send_only_t;\r
-\r
-typedef struct {\r
- IB_LRH_st IB_LRH;\r
- IB_GRH_st IB_GRH;\r
- IB_BTH_st IB_BTH;\r
- IB_DETH_st IB_DETH;\r
- IB_ImmDt_st IB_ImmDt;\r
-} MPGA_G_ud_send_only_ImmDt_t;\r
-\r
-\r
-typedef union {\r
-\r
- /*IBA LOCAL*/\r
- /* RC - Reliable Connection - opcode prefix 000*/ /* OpCode */ \r
- MPGA_rc_send_first_t MPGA_rc_send_first; /* 00000 */ \r
- MPGA_rc_send_middle_t MPGA_rc_send_middle; /* 00001 */ \r
- MPGA_rc_send_last_t MPGA_rc_send_last; /* 00010 */ \r
- MPGA_rc_send_last_ImmDt_t MPGA_rc_send_last_ImmDt; /* 00011 */ \r
- MPGA_rc_send_only_t MPGA_rc_send_only; /* 00100 */ \r
- MPGA_rc_send_only_ImmDt_t MPGA_rc_send_only_ImmDt; /* 00101 */ \r
- \r
- MPGA_rc_write_first_t MPGA_rc_write_first; /* 00110 */ \r
- MPGA_rc_write_middle_t MPGA_rc_write_middle; /* 00111 */ \r
- MPGA_rc_write_last_t MPGA_rc_write_last; /* 01000 */ \r
- MPGA_rc_write_last_ImmDt_t MPGA_rc_write_last_ImmDt;/* 01001 */ \r
- MPGA_rc_write_only_t MPGA_rc_write_only; /* 01010 */ \r
- MPGA_rc_write_only_ImmDt_t MPGA_rc_write_only_ImmDt;/* 01011 */ \r
-\r
- MPGA_rc_read_req_t MPGA_rc_read_req; /* 01100 */\r
- MPGA_rc_read_res_first_t MPGA_rc_read_res_first; /* 01101 */\r
- MPGA_rc_read_res_middle_t MPGA_rc_read_res_middle; /* 01110 */\r
- MPGA_rc_read_res_last_t MPGA_rc_read_res_last; /* 01111 */\r
- MPGA_rc_read_res_only_t MPGA_rc_read_res_only; /* 10000 */\r
- \r
- MPGA_rc_ack_t MPGA_rc_ack; /* 10001 */ \r
- MPGA_rc_atomic_ack_t MPGA_rc_atomic_ack; /* 10010 */ \r
- MPGA_rc_CmpSwap_t MPGA_rc_CmpSwap; /* 10011 */ \r
- MPGA_rc_FetchAdd_t MPGA_rc_FetchAdd; /* 10100 */ \r
-\r
- /* UC - Unreliable Connection - opcode prefix 001*/\r
- MPGA_uc_send_first_t MPGA_uc_send_first; /* 00000 */ \r
- MPGA_uc_send_middle_t MPGA_uc_send_middle; /* 00001 */ \r
- MPGA_uc_send_last_t MPGA_uc_send_last; /* 00010 */ \r
- MPGA_uc_send_last_ImmDt_t MPGA_uc_send_last_ImmDt; /* 00011 */ \r
- MPGA_uc_send_only_t MPGA_uc_send_only; /* 00100 */ \r
- MPGA_uc_send_only_ImmDt_t MPGA_uc_send_only_ImmDt; /* 00101 */ \r
- \r
- MPGA_uc_write_first_t MPGA_uc_write_first; /* 00110 */ \r
- MPGA_uc_write_middle_t MPGA_uc_write_middle; /* 00111 */ \r
- MPGA_uc_write_last_t MPGA_uc_write_last; /* 01000 */ \r
- MPGA_uc_write_last_ImmDt_t MPGA_uc_write_last_ImmDt;/* 01001 */ \r
- MPGA_uc_write_only_t MPGA_uc_write_only; /* 01010 */ \r
- MPGA_uc_write_only_ImmDt_t MPGA_uc_write_only_ImmDt;/* 01011 */\r
-\r
- /* RD - Reliable Datagram - opcode prefix 010*/ \r
- MPGA_rd_send_first_t MPGA_rd_send_first; /* 00000 */ \r
- MPGA_rd_send_middle_t MPGA_rd_send_middle; /* 00001 */ \r
- MPGA_rd_send_last_t MPGA_rd_send_last; /* 00010 */ \r
- MPGA_rd_send_last_ImmDt_t MPGA_rd_send_last_ImmDt; /* 00011 */ \r
- MPGA_rd_send_only_t MPGA_rd_send_only; /* 00100 */ \r
- MPGA_rd_send_only_ImmDt_t MPGA_rd_send_only_ImmDt; /* 00101 */ \r
- \r
- MPGA_rd_write_first_t MPGA_rd_write_first; /* 00110 */ \r
- MPGA_rd_write_middle_t MPGA_rd_write_middle; /* 00111 */ \r
- MPGA_rd_write_last_t MPGA_rd_write_last; /* 01000 */ \r
- MPGA_rd_write_last_ImmDt_t MPGA_rd_write_last_ImmDt;/* 01001 */ \r
- MPGA_rd_write_only_t MPGA_rd_write_only; /* 01010 */ \r
- MPGA_rd_write_only_ImmDt_t MPGA_rd_write_only_ImmDt;/* 01011 */ \r
-\r
- MPGA_rd_read_req_t MPGA_rd_read_req; /* 01100 */\r
- MPGA_rd_read_res_first_t MPGA_rd_read_res_first; /* 01101 */\r
- MPGA_rd_read_res_middle_t MPGA_rd_read_res_middle; /* 01110 */\r
- MPGA_rd_read_res_last_t MPGA_rd_read_res_last; /* 01111 */\r
- MPGA_rd_read_res_only_t MPGA_rd_read_res_only; /* 10000 */\r
- \r
- MPGA_rd_ack_t MPGA_rd_ack; /* 10001 */ \r
- MPGA_rd_atomic_ack_t MPGA_rd_atomic_ack; /* 10010 */ \r
- MPGA_rd_CmpSwap_t MPGA_rd_CmpSwap; /* 10011 */ \r
- MPGA_rd_FetchAdd_t MPGA_rd_FetchAdd; /* 10100 */ \r
- MPGA_rd_resync_t MPGA_rd_resync; /* 10101 */\r
-\r
- /* UD - UnReliable Datagram - opcode prefix 011*/ \r
- MPGA_ud_send_only_t MPGA_ud_send_only; /* 01010 */ \r
- MPGA_ud_send_only_ImmDt_t MPGA_ud_send_only_ImmDt; /* 01011 */\r
-\r
-\r
-\r
- /* IBA GLOBAL */\r
- /* RC - Reliable Connection - opcode prefix 000*/ /* OpCode */ \r
- MPGA_G_rc_send_first_t MPGA_G_rc_send_first; /* 00000 */ \r
- MPGA_G_rc_send_middle_t MPGA_G_rc_send_middle; /* 00001 */ \r
- MPGA_G_rc_send_last_t MPGA_G_rc_send_last; /* 00010 */ \r
- MPGA_G_rc_send_last_ImmDt_t MPGA_G_rc_send_last_ImmDt; /* 00011 */ \r
- MPGA_G_rc_send_only_t MPGA_G_rc_send_only; /* 00100 */ \r
- MPGA_G_rc_send_only_ImmDt_t MPGA_G_rc_send_only_ImmDt; /* 00101 */ \r
- \r
- MPGA_G_rc_write_first_t MPGA_G_rc_write_first; /* 00110 */ \r
- MPGA_G_rc_write_middle_t MPGA_G_rc_write_middle; /* 00111 */ \r
- MPGA_G_rc_write_last_t MPGA_G_rc_write_last; /* 01000 */ \r
- MPGA_G_rc_write_last_ImmDt_t MPGA_G_rc_write_last_ImmDt;/* 01001 */ \r
- MPGA_G_rc_write_only_t MPGA_G_rc_write_only; /* 01010 */ \r
- MPGA_G_rc_write_only_ImmDt_t MPGA_G_rc_write_only_ImmDt;/* 01011 */ \r
-\r
- MPGA_G_rc_read_req_t MPGA_G_rc_read_req; /* 01100 */\r
- MPGA_G_rc_read_res_first_t MPGA_G_rc_read_res_first; /* 01101 */\r
- MPGA_G_rc_read_res_middle_t MPGA_G_rc_read_res_middle; /* 01110 */\r
- MPGA_G_rc_read_res_last_t MPGA_G_rc_read_res_last; /* 01111 */\r
- MPGA_G_rc_read_res_only_t MPGA_G_rc_read_res_only; /* 10000 */\r
- \r
- MPGA_G_rc_ack_t MPGA_G_rc_ack; /* 10001 */ \r
- MPGA_G_rc_atomic_ack_t MPGA_G_rc_atomic_ack; /* 10010 */ \r
- MPGA_G_rc_CmpSwap_t MPGA_G_rc_CmpSwap; /* 10011 */ \r
- MPGA_G_rc_FetchAdd_t MPGA_G_rc_FetchAdd; /* 10100 */ \r
-\r
- /* UC - Unreliable Connection - opcode prefix 001*/\r
- MPGA_G_uc_send_first_t MPGA_G_uc_send_first; /* 00000 */ \r
- MPGA_G_uc_send_middle_t MPGA_G_uc_send_middle; /* 00001 */ \r
- MPGA_G_uc_send_last_t MPGA_G_uc_send_last; /* 00010 */ \r
- MPGA_G_uc_send_last_ImmDt_t MPGA_G_uc_send_last_ImmDt; /* 00011 */ \r
- MPGA_G_uc_send_only_t MPGA_G_uc_send_only; /* 00100 */ \r
- MPGA_G_uc_send_only_ImmDt_t MPGA_G_uc_send_only_ImmDt; /* 00101 */ \r
- \r
- MPGA_G_uc_write_first_t MPGA_G_uc_write_first; /* 00110 */ \r
- MPGA_G_uc_write_middle_t MPGA_G_uc_write_middle; /* 00111 */ \r
- MPGA_G_uc_write_last_t MPGA_G_uc_write_last; /* 01000 */ \r
- MPGA_G_uc_write_last_ImmDt_t MPGA_G_uc_write_last_ImmDt;/* 01001 */ \r
- MPGA_G_uc_write_only_t MPGA_G_uc_write_only; /* 01010 */ \r
- MPGA_G_uc_write_only_ImmDt_t MPGA_G_uc_write_only_ImmDt;/* 01011 */\r
-\r
- /* RD - Reliable Datagram - opcode prefix 010*/ \r
- MPGA_G_rd_send_first_t MPGA_G_rd_send_first; /* 00000 */ \r
- MPGA_G_rd_send_middle_t MPGA_G_rd_send_middle; /* 00001 */ \r
- MPGA_G_rd_send_last_t MPGA_G_rd_send_last; /* 00010 */ \r
- MPGA_G_rd_send_last_ImmDt_t MPGA_G_rd_send_last_ImmDt; /* 00011 */ \r
- MPGA_G_rd_send_only_t MPGA_G_rd_send_only; /* 00100 */ \r
- MPGA_G_rd_send_only_ImmDt_t MPGA_G_rd_send_only_ImmDt; /* 00101 */ \r
- \r
- MPGA_G_rd_write_first_t MPGA_G_rd_write_first; /* 00110 */ \r
- MPGA_G_rd_write_middle_t MPGA_G_rd_write_middle; /* 00111 */ \r
- MPGA_G_rd_write_last_t MPGA_G_rd_write_last; /* 01000 */ \r
- MPGA_G_rd_write_last_ImmDt_t MPGA_G_rd_write_last_ImmDt;/* 01001 */ \r
- MPGA_G_rd_write_only_t MPGA_G_rd_write_only; /* 01010 */ \r
- MPGA_G_rd_write_only_ImmDt_t MPGA_G_rd_write_only_ImmDt;/* 01011 */ \r
-\r
- MPGA_G_rd_read_req_t MPGA_G_rd_read_req; /* 01100 */\r
- MPGA_G_rd_read_res_first_t MPGA_G_rd_read_res_first; /* 01101 */\r
- MPGA_G_rd_read_res_middle_t MPGA_G_rd_read_res_middle; /* 01110 */\r
- MPGA_G_rd_read_res_last_t MPGA_G_rd_read_res_last; /* 01111 */\r
- MPGA_G_rd_read_res_only_t MPGA_G_rd_read_res_only; /* 10000 */\r
- \r
- MPGA_G_rd_ack_t MPGA_G_rd_ack; /* 10001 */ \r
- MPGA_G_rd_atomic_ack_t MPGA_G_rd_atomic_ack; /* 10010 */ \r
- MPGA_G_rd_CmpSwap_t MPGA_G_rd_CmpSwap; /* 10011 */ \r
- MPGA_G_rd_FetchAdd_t MPGA_G_rd_FetchAdd; /* 10100 */ \r
- MPGA_G_rd_resync_t MPGA_G_rd_resync; /* 10101 */\r
-\r
- /* UD - UnReliable Datagram - opcode prefix 011*/ \r
- MPGA_G_ud_send_only_t MPGA_G_ud_send_only; /* 01010 */ \r
- MPGA_G_ud_send_only_ImmDt_t MPGA_G_ud_send_only_ImmDt; /* 01011 */\r
-\r
-}MPGA_headers_t;\r
-\r
-#endif /* MPGA_headers_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-\r
-#ifndef __IB_OPCODES_H\r
-#define __IB_OPCODES_H\r
-\r
-/***********************************************/\r
-/* Define all base transport OpCode fields */\r
-/***********************************************/\r
-\r
-typedef u_int8_t IB_opcode_t;\r
-\r
-typedef enum{\r
- \r
- IB_ST_RC = 0, /* Reliable Connection (RC). */\r
- \r
- IB_ST_UC = 1, /* Unreliable Connection (UC). */\r
- \r
- IB_ST_RD = 2, /* Reliable Datagram (RD). */\r
- \r
- IB_ST_UD = 3 /* Unreliable Datagram (UD). */\r
- \r
-} IB_service_type_t; \r
-/***********************************************/\r
-/* reliable Connection (RC) */\r
-/***********************************************/\r
-#define RC_SEND_FIRST_OP 0x00\r
-#define RC_SEND_MIDDLE_OP 0x01\r
-#define RC_SEND_LAST_OP 0x02\r
-#define RC_SEND_LAST_W_IM_OP 0x03\r
-#define RC_SEND_ONLY_OP 0x04\r
-#define RC_SEND_ONLY_W_IM_OP 0x05\r
-\r
-#define RC_WRITE_FIRST_OP 0x06\r
-#define RC_WRITE_MIDDLE_OP 0x07\r
-#define RC_WRITE_LAST_OP 0x08\r
-#define RC_WRITE_LAST_W_IM_OP 0x09\r
-#define RC_WRITE_ONLY_OP 0x0A\r
-#define RC_WRITE_ONLY_W_IM_OP 0x0B\r
-\r
-#define RC_READ_REQ_OP 0x0C\r
-#define RC_READ_RESP_FIRST_OP 0x0D\r
-#define RC_READ_RESP_MIDDLE_OP 0x0E\r
-#define RC_READ_RESP_LAST_OP 0x0F\r
-#define RC_READ_RESP_ONLY_OP 0x10\r
-\r
-#define RC_ACKNOWLEDGE_OP 0x11\r
-#define RC_ATOMIC_ACKNOWLEDGE_OP 0x12\r
-\r
-#define RC_CMP_SWAP_OP 0x13\r
-#define RC_FETCH_ADD_OP 0x14\r
-\r
-/***********************************************/\r
-/* Unreliable Connection (UC) */\r
-/***********************************************/\r
-\r
-#define UC_SEND_FIRST_OP 0x20\r
-#define UC_SEND_MIDDLE_OP 0x21\r
-#define UC_SEND_LAST_OP 0x22\r
-#define UC_SEND_LAST_W_IM_OP 0x23\r
-#define UC_SEND_ONLY_OP 0x24\r
-#define UC_SEND_ONLY_W_IM_OP 0x25\r
-\r
-#define UC_WRITE_FIRST_OP 0x26\r
-#define UC_WRITE_MIDDLE_OP 0x27\r
-#define UC_WRITE_LAST_OP 0x28\r
-#define UC_WRITE_LAST_W_IM_OP 0x29\r
-#define UC_WRITE_ONLY_OP 0x2A\r
-#define UC_WRITE_ONLY_W_IM_OP 0x2B\r
-\r
-/***********************************************/\r
-/* Reliable Datagram (RD) */\r
-/***********************************************/\r
-\r
-#define RD_SEND_FIRST_OP 0x40\r
-#define RD_SEND_MIDDLE_OP 0x41\r
-#define RD_SEND_LAST_OP 0x42\r
-#define RD_SEND_LAST_W_IM_OP 0x43\r
-#define RD_SEND_ONLY_OP 0x44\r
-#define RD_SEND_ONLY_W_IM_OP 0x45\r
-\r
-#define RD_WRITE_FIRST_OP 0x46\r
-#define RD_WRITE_MIDDLE_OP 0x47\r
-#define RD_WRITE_LAST_OP 0x48\r
-#define RD_WRITE_LAST_W_IM_OP 0x49\r
-#define RD_WRITE_ONLY_OP 0x4A\r
-#define RD_WRITE_ONLY_W_IM_OP 0x4B\r
-\r
-#define RD_READ_REQ_OP 0x4C\r
-#define RD_READ_RESP_FIRST_OP 0x4D\r
-#define RD_READ_RESP_MIDDLE_OP 0x4E\r
-#define RD_READ_RESP_LAST_OP 0x4F\r
-#define RD_READ_RESP_ONLY_OP 0x50\r
-\r
-#define RD_ACKNOWLEDGE_OP 0x51\r
-#define RD_ATOMIC_ACKNOWLEDGE_OP 0x52\r
-\r
-#define RD_CMP_SWAP_OP 0x53\r
-#define RD_FETCH_ADD_OP 0x54\r
-\r
-/***********************************************/\r
-/* Unreliable Datagram (UD) */\r
-/***********************************************/\r
-\r
-#define UD_SEND_ONLY_OP 0x64\r
-#define UD_SEND_ONLY_W_IM_OP 0x65\r
-\r
-\r
-\r
-#endif /* __IB_OPCODES_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#ifndef MT_KERNEL\r
-\r
- #include <stdio.h>\r
- #include <stdlib.h>\r
-\r
-#endif /* MT_KERNEL */ \r
-\r
-/* MPGA Includes */ \r
-#include <internal_functions.h>\r
-\r
-/* Layers Includes */\r
-#include <mtl_common.h>\r
-#ifdef __WIN__\r
-#include <mosal.h>\r
-#endif\r
-\r
-\r
-\r
-/*For the calc of the ICRC */\r
-static u_int32_t crc32_table[256] = { /* The Polynomial used is 0x04C11DB7 seed 0xFFFFFFFF */\r
-0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,\r
-0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,\r
-0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE, 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,\r
-0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,\r
-0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172, 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,\r
-0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940, 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,\r
-0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,\r
-0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924, 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,\r
-0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A, 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,\r
-0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,\r
-0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E, 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,\r
-0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C, 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,\r
-0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,\r
-0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0, 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,\r
-0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086, 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,\r
-0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,\r
-0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A, 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,\r
-0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8, 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,\r
-0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,\r
-0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC, 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,\r
-0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252, 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,\r
-0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,\r
-0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236, 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,\r
-0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04, 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,\r
-0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,\r
-0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38, 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,\r
-0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E, 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,\r
-0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,\r
-0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2, 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,\r
-0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0, 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,\r
-0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6, 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,\r
-0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94, 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D\r
-};\r
-\r
-static u_int16_t crc16_table[256] = { /* The Polynomial used is 0x100B seed 0xFFFF */\r
- 0x0000, 0x1BA1, 0x3742, 0x2CE3, 0x6E84, 0x7525, 0x59C6, 0x4267,\r
- 0xDD08, 0xC6A9, 0xEA4A, 0xF1EB, 0xB38C, 0xA82D, 0x84CE, 0x9F6F,\r
- 0x1A01, 0x01A0, 0x2D43, 0x36E2, 0x7485, 0x6F24, 0x43C7, 0x5866,\r
- 0xC709, 0xDCA8, 0xF04B, 0xEBEA, 0xA98D, 0xB22C, 0x9ECF, 0x856E,\r
- 0x3402, 0x2FA3, 0x0340, 0x18E1, 0x5A86, 0x4127, 0x6DC4, 0x7665,\r
- 0xE90A, 0xF2AB, 0xDE48, 0xC5E9, 0x878E, 0x9C2F, 0xB0CC, 0xAB6D,\r
- 0x2E03, 0x35A2, 0x1941, 0x02E0, 0x4087, 0x5B26, 0x77C5, 0x6C64,\r
- 0xF30B, 0xE8AA, 0xC449, 0xDFE8, 0x9D8F, 0x862E, 0xAACD, 0xB16C,\r
- 0x6804, 0x73A5, 0x5F46, 0x44E7, 0x0680, 0x1D21, 0x31C2, 0x2A63,\r
- 0xB50C, 0xAEAD, 0x824E, 0x99EF, 0xDB88, 0xC029, 0xECCA, 0xF76B,\r
- 0x7205, 0x69A4, 0x4547, 0x5EE6, 0x1C81, 0x0720, 0x2BC3, 0x3062,\r
- 0xAF0D, 0xB4AC, 0x984F, 0x83EE, 0xC189, 0xDA28, 0xF6CB, 0xED6A,\r
- 0x5C06, 0x47A7, 0x6B44, 0x70E5, 0x3282, 0x2923, 0x05C0, 0x1E61,\r
- 0x810E, 0x9AAF, 0xB64C, 0xADED, 0xEF8A, 0xF42B, 0xD8C8, 0xC369,\r
- 0x4607, 0x5DA6, 0x7145, 0x6AE4, 0x2883, 0x3322, 0x1FC1, 0x0460,\r
- 0x9B0F, 0x80AE, 0xAC4D, 0xB7EC, 0xF58B, 0xEE2A, 0xC2C9, 0xD968,\r
- 0xD008, 0xCBA9, 0xE74A, 0xFCEB, 0xBE8C, 0xA52D, 0x89CE, 0x926F,\r
- 0x0D00, 0x16A1, 0x3A42, 0x21E3, 0x6384, 0x7825, 0x54C6, 0x4F67,\r
- 0xCA09, 0xD1A8, 0xFD4B, 0xE6EA, 0xA48D, 0xBF2C, 0x93CF, 0x886E,\r
- 0x1701, 0x0CA0, 0x2043, 0x3BE2, 0x7985, 0x6224, 0x4EC7, 0x5566,\r
- 0xE40A, 0xFFAB, 0xD348, 0xC8E9, 0x8A8E, 0x912F, 0xBDCC, 0xA66D,\r
- 0x3902, 0x22A3, 0x0E40, 0x15E1, 0x5786, 0x4C27, 0x60C4, 0x7B65,\r
- 0xFE0B, 0xE5AA, 0xC949, 0xD2E8, 0x908F, 0x8B2E, 0xA7CD, 0xBC6C,\r
- 0x2303, 0x38A2, 0x1441, 0x0FE0, 0x4D87, 0x5626, 0x7AC5, 0x6164,\r
- 0xB80C, 0xA3AD, 0x8F4E, 0x94EF, 0xD688, 0xCD29, 0xE1CA, 0xFA6B,\r
- 0x6504, 0x7EA5, 0x5246, 0x49E7, 0x0B80, 0x1021, 0x3CC2, 0x2763,\r
- 0xA20D, 0xB9AC, 0x954F, 0x8EEE, 0xCC89, 0xD728, 0xFBCB, 0xE06A,\r
- 0x7F05, 0x64A4, 0x4847, 0x53E6, 0x1181, 0x0A20, 0x26C3, 0x3D62,\r
- 0x8C0E, 0x97AF, 0xBB4C, 0xA0ED, 0xE28A, 0xF92B, 0xD5C8, 0xCE69,\r
- 0x5106, 0x4AA7, 0x6644, 0x7DE5, 0x3F82, 0x2423, 0x08C0, 0x1361,\r
- 0x960F, 0x8DAE, 0xA14D, 0xBAEC, 0xF88B, 0xE32A, 0xCFC9, 0xD468,\r
- 0x4B07, 0x50A6, 0x7C45, 0x67E4, 0x2583, 0x3E22, 0x12C1, 0x0960\r
-};\r
-\r
-/*static u_int8_t test_array[] = {\r
-0x70, 0x12, 0x37, 0x5C, 0x00, 0x0E, 0x17, 0xD2, 0x0A, 0x20, 0x24, 0x87,\r
-0x00, 0x87, 0xB1, 0xB3, 0x00, 0x0D, 0xEC, 0x2A, 0x01, 0x71, 0x0A, 0x1C,\r
-0x01, 0x5D, 0x40, 0x02, 0x38, 0xF2, 0x7A, 0x05, 0x00, 0x00, 0x00, 0x0E,\r
-0xBB, 0x88, 0x4D, 0x85, 0xFD, 0x5C, 0xFB, 0xA4, 0x72, 0x8B, 0xC0, 0x69,\r
-0x0E, 0xD4, 0x00, 0x00\r
-};*/\r
-\r
-/*static u_int8_t test_array2[] = {\r
-0x70, 0x13, 0x37, 0x5C, 0x00, 0x18, 0x17, 0xD2, 0x60, 0x00, 0x00, 0x00, 0x00, 0x32,\r
-0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x25, 0x00, 0x00, 0x00, 0x00,\r
-0x00, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x17, 0x00, 0x00,\r
-0x00, 0x00, 0x00, 0x00, 0x00, 0x96, 0x0A, 0x20, 0x24, 0x87, 0x00, 0x87, 0xB1, 0xB3,\r
-0x00, 0x0D, 0xEC, 0x2A, 0x01, 0x71, 0x0A, 0x1C, 0x01, 0x5D, 0x40, 0x02, 0x38, 0xF2,\r
-0x7A, 0x05, 0x00, 0x00, 0x00, 0x0E, 0xBB, 0x88, 0x4D, 0x85, 0xFD, 0x5C, 0xFB, 0xA4,\r
-0x72, 0x8B, 0xC0, 0x69, 0x0E, 0xD4, 0x00, 0x00\r
-};*/\r
-\r
-/*static u_int8_t test_array_vcrc[] = {\r
-0x70, 0x12, 0x37, 0x5C, 0x00, 0x0E, 0x17, 0xD2, 0x0A, 0x20, 0x24, 0x87,\r
-0x00, 0x87, 0xB1, 0xB3, 0x00, 0x0D, 0xEC, 0x2A, 0x01, 0x71, 0x0A, 0x1C,\r
-0x01, 0x5D, 0x40, 0x02, 0x38, 0xF2, 0x7A, 0x05, 0x00, 0x00, 0x00, 0x0E,\r
-0xBB, 0x88, 0x4D, 0x85, 0xFD, 0x5C, 0xFB, 0xA4, 0x72, 0x8B, 0xC0, 0x69,\r
-0x0E, 0xD4, 0x00, 0x00, 0x96, 0x25, 0xB7, 0x5A\r
-};*/\r
-/***********************************************************************************/\r
-/* Allocate Packet */\r
-/***********************************************************************************/\r
-call_result_t\r
-allocate_packet(u_int16_t payload_size, u_int16_t *payload_buf_p,\r
- u_int16_t packet_size, u_int16_t **packet_buf_p)\r
-{\r
- u_int8_t* temp_buffer_p,i;\r
- u_int8_t* start_of_payload_p;\r
- u_int8_t align;\r
-\r
- align = ((IBWORD - (payload_size % IBWORD)) % IBWORD);\r
- if(packet_size < payload_size) return MT_EINVAL;\r
- /*preventing the memcpy from writing on non alocated mem */\r
-\r
- if((temp_buffer_p = ALLOCATE(u_int8_t,packet_size))== NULL){ /* Allocting size in bytes*/\r
- MTL_ERROR('1', "\nfailed to allocate temp_buffer_p");\r
- return(MT_EKMALLOC);\r
- };\r
-\r
- for(i=0;i < align ;i++)\r
- {\r
- *(temp_buffer_p + (packet_size) - (i + 1)) = 0x00;\r
- /*Appending Zeros at the end of the packet to align to 4 byte long*/\r
- }\r
-\r
- start_of_payload_p = temp_buffer_p + (packet_size - payload_size - align );\r
- /*The address of the first byte in the packet payload*/\r
- MTL_TRACE('5', "\n the allocated mem is %p start payload is %p",temp_buffer_p,start_of_payload_p);\r
- if(payload_buf_p != NULL){\r
- memcpy(start_of_payload_p,payload_buf_p, payload_size);\r
- /*Coping the given buffer (payload) to the end of th buffer living place for the header*/\r
- }\r
-\r
- MTL_TRACE('5', "\n start of payload[0] inside = %d",start_of_payload_p[0]);\r
-\r
- (*packet_buf_p) = (u_int16_t *)start_of_payload_p;/*init the given pointer*/\r
-\r
- MTL_TRACE('5', "\n *packet_buf[0] = %d",(*packet_buf_p)[0]);\r
- MTL_TRACE('5', "\n packet_buf_p is %p\n",(*packet_buf_p)); \r
- \r
- return(MT_OK);\r
-}\r
-\r
-/***********************************************************************************/\r
-/* Allocate Packet_LRH */\r
-/***********************************************************************************/\r
-call_result_t\r
-allocate_packet_LRH(u_int16_t TCRC_packet_size, u_int16_t t_packet_size,\r
- u_int16_t *t_packet_buf_p, u_int16_t packet_size, u_int16_t **packet_buf_p)\r
-{\r
- u_int8_t* temp_buffer_p;\r
- u_int8_t* end_of_LRH_p;\r
- if(packet_size < TCRC_packet_size) return MT_EINVAL;\r
- /*preventing the memcpy from writing on non alocated mem */\r
-\r
- if((temp_buffer_p = ALLOCATE(u_int8_t,(packet_size)))== NULL){ /* Allocting size in bytes*/\r
- MTL_ERROR('1', "\nfailed to allocate temp_buffer_p");\r
- return(MT_EKMALLOC);\r
- };\r
-\r
- end_of_LRH_p = temp_buffer_p + (packet_size - TCRC_packet_size);\r
- /*The address of the first byte in the packet payload*/\r
-\r
- if(t_packet_buf_p != NULL){\r
- memcpy(end_of_LRH_p, t_packet_buf_p, t_packet_size);\r
- /*Coping the given buffer (payload) to the end of th buffer living place for the header*/\r
- }\r
-\r
- (*packet_buf_p) = (u_int16_t *)end_of_LRH_p;/*init the given pointer*/\r
-\r
- return(MT_OK);\r
-}\r
-\r
-/***********************************************************************************/\r
-/* init packet struct */\r
-/***********************************************************************************/\r
-call_result_t\r
-init_pkt_st(IB_PKT_st *pkt_st_p)\r
-{\r
- pkt_st_p->lrh_st_p = NULL;\r
- pkt_st_p->grh_st_p = NULL;\r
- pkt_st_p->bth_st_p = NULL;\r
- pkt_st_p->rdeth_st_p = NULL;\r
- pkt_st_p->deth_st_p = NULL;\r
- pkt_st_p->reth_st_p = NULL;\r
- pkt_st_p->atomic_eth_st_p = NULL;\r
- pkt_st_p->aeth_st_p = NULL;\r
- pkt_st_p->atomic_acketh_st_p = NULL;\r
- pkt_st_p->payload_buf = NULL;\r
- pkt_st_p->payload_size = 0;/*Not a pointer like every one Not every one is perfect*/\r
- pkt_st_p->packet_size = 0;\r
- return(MT_OK);\r
-}\r
-\r
-/***********************************************************************************/\r
-/* is little endian */\r
-/***********************************************************************************/\r
-u_int8_t\r
-is_little_endian()\r
-{\r
- int* p_2_int;\r
- u_int8_t* p_2_8_bit;\r
- \r
- p_2_int = ALLOCATE(int,1);\r
- *p_2_int = 1;\r
- p_2_8_bit =(u_int8_t *)p_2_int + (sizeof(int) - 1); /*higer byte*/\r
- \r
- if(*p_2_8_bit == 1){\r
- MTL_TRACE('3', "\n\n\n\n ********** This is a big endian machine **********\n\n\n\n");\r
- FREE(p_2_int);\r
- return(BIG_ENDIAN_TYPE);\r
- }else{\r
- MTL_TRACE('3', "\n\n\n\n ********** This is a little endian machine **********\n\n\n\n");\r
- FREE(p_2_int);\r
- return(LITTLE_ENDIAN_TYPE);\r
- }\r
-} \r
-\r
-/***********************************************************************************/\r
-/* little endain 16 */\r
-/***********************************************************************************/\r
-u_int16_t\r
-little_endian_16(u_int8_t byte_0, u_int8_t byte_1)\r
-{\r
- u_int8_t convert_arry[2];\r
- u_int16_t *p_2_16bit;\r
-\r
- convert_arry[0] = byte_0;\r
- convert_arry[1] = byte_1;\r
-\r
- p_2_16bit = (u_int16_t*)convert_arry;\r
-\r
- return(*(p_2_16bit));\r
-}\r
-\r
-/***********************************************************************************/\r
-/* little endain 32 */\r
-/***********************************************************************************/\r
-u_int32_t\r
-little_endian_32(u_int8_t byte_0, u_int8_t byte_1, u_int8_t byte_2, u_int8_t byte_3)\r
-{\r
- u_int8_t convert_arry[4];\r
- u_int32_t *p_2_32bit;\r
-\r
- convert_arry[0] = byte_0;\r
- convert_arry[1] = byte_1;\r
- convert_arry[2] = byte_2;\r
- convert_arry[3] = byte_3;\r
-\r
- p_2_32bit = (u_int32_t*)convert_arry;\r
-\r
- return(*(p_2_32bit));\r
-}\r
-\r
-/***********************************************************************************/\r
-/* little endain 64 */\r
-/***********************************************************************************/\r
-u_int64_t\r
-little_endian_64(u_int8_t byte_0, u_int8_t byte_1, u_int8_t byte_2, u_int8_t byte_3,\r
- u_int8_t byte_4, u_int8_t byte_5, u_int8_t byte_6, u_int8_t byte_7)\r
-{\r
- u_int8_t convert_arry[8];\r
- u_int64_t *p_2_64bit;\r
-\r
- convert_arry[0] = byte_0;\r
- convert_arry[1] = byte_1;\r
- convert_arry[2] = byte_2;\r
- convert_arry[3] = byte_3;\r
- convert_arry[4] = byte_4;\r
- convert_arry[5] = byte_5;\r
- convert_arry[6] = byte_6;\r
- convert_arry[7] = byte_7;\r
-\r
- p_2_64bit = (u_int64_t*)convert_arry;\r
-\r
- return(*(p_2_64bit));\r
-}\r
-\r
-/***********************************************************************************/\r
-/* fast calc ICRC */\r
-/***********************************************************************************/\r
-u_int32_t\r
-fast_calc_ICRC(u_int16_t packet_size, u_int16_t *packet_buf_p,LNH_t LNH)\r
-{\r
- u_int8_t *start_ICRC;\r
- u_int8_t *packet_start;\r
- u_int32_t ICRC;\r
-\r
-if((LNH != IBA_LOCAL) && (LNH != IBA_GLOBAL)) return (MT_OK);\r
- /* This is not a IBA trans port (No need for ICRC*/\r
-\r
- start_ICRC = (u_int8_t*)packet_buf_p +packet_size -VCRC_LEN -ICRC_LEN;\r
- packet_start =(u_int8_t*) packet_buf_p;\r
-\r
- ICRC = update_ICRC((u_int8_t *)packet_start, (u_int16_t)(packet_size -VCRC_LEN -ICRC_LEN), LNH);\r
- /*ICRC = update_ICRC(test_array1, 52);*/\r
- return(ICRC);\r
-}\r
-\r
-/***********************************************************************************/\r
-/* Update ICRC */\r
-/***********************************************************************************/\r
-u_int32_t\r
-update_ICRC(u_int8_t *byte, u_int16_t size,LNH_t LNH) /* size of the buffer in bytes*/\r
-{\r
- u_int8_t VL_mask = 0xF0;\r
- u_int8_t TClass_mask = 0x0F;\r
- u_int8_t reserved_mask = 0xFF;\r
- u_int16_t index = 0;\r
- u_int32_t ICRC = 0xFFFFFFFF;\r
-\r
-\r
- \r
- if(LNH == IBA_LOCAL){\r
- VL_mask = VL_mask | byte[0]; /*LRH field*/\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (VL_mask)]; /*masked 1111____*/\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[1]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[2]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[3]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[4]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[5]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[6]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[7]) ];\r
- /*BTH field*/\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[8]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[9]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[10]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[11]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ reserved_mask ]; /*masked 11111111*/\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[13]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[14]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[15]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[16]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[17]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[18]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[19]) ];\r
-\r
- size = size - BTH_LEN - LRH_LEN;\r
- index = BTH_LEN + LRH_LEN;\r
-\r
- while(size--)\r
- {\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[index]) ];\r
- index ++;\r
- }\r
- }else{/*It is IBA Global*/\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (0xFF) ]; /*masking all the LRH field*/\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (0xFF) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (0xFF) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (0xFF) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (0xFF) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (0xFF) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (0xFF) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (0xFF) ]; /* 0 - 7 bytes*/\r
-\r
- TClass_mask = TClass_mask | byte[8]; /*GRH field 40 byte*/\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (TClass_mask)]; /*masked _ _ _ _ 1111*/\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (0xFF) ]; /*byte 9 masking the FLow Lable*/\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (0xFF) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (0xFF) ]; /*end of masking FLow Lable*/\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[12]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[13]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[14]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (0xFF) ]; /*Masking the HopLmt 1111111*/\r
-\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[16]) ]; /*SGID DGID*/\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[17]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[18]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[19]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[20]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[21]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[22]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[23]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[24]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[25]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[26]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[27]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[28]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[29]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[30]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[31]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[32]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[33]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[34]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[35]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[36]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[37]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[38]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[39]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[40]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[41]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[42]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[43]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[44]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[45]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[46]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[47]) ];\r
- /*BTH field 12 bytes*/\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[48]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[49]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[50]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[51]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (reserved_mask)];/*masking reserved field*/\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[53]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[54]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[55]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[56]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[57]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[58]) ];\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[59]) ];\r
-\r
- size = size - LRH_LEN - GRH_LEN - BTH_LEN ;\r
- index = LRH_LEN + GRH_LEN + BTH_LEN;\r
-\r
- while(size--) /*The rest of The packet*/\r
- {\r
- ICRC = (ICRC >> 8) ^ crc32_table[(ICRC & 0xFF) ^ (byte[index]) ];\r
- index ++;\r
- }\r
- }\r
-\r
- return (ICRC ^ 0xFFFFFFFF);\r
-}\r
-\r
-\r
-/***********************************************************************************/\r
-/* fast calc VCRC */\r
-/***********************************************************************************/\r
-u_int16_t\r
-fast_calc_VCRC(u_int16_t packet_size, u_int16_t *packet_buf_p)\r
-{\r
- u_int8_t *start_VCRC;\r
- u_int8_t *packet_start;\r
- u_int16_t VCRC = 0 ;\r
-\r
- start_VCRC = (u_int8_t*)packet_buf_p +packet_size -VCRC_LEN ;\r
- packet_start =(u_int8_t*) packet_buf_p;\r
-\r
- VCRC = update_VCRC((u_int8_t *)packet_start, (u_int16_t)(packet_size -VCRC_LEN));\r
- /*VCRC = update_VCRC(test_array_vcrc, 56);*/\r
- return(VCRC);\r
-}\r
-/***********************************************************************************/\r
-/* update VCRC */\r
-/***********************************************************************************/\r
-u_int16_t\r
-update_VCRC(u_int8_t *byte, u_int16_t size)\r
-{\r
- u_int16_t VCRC = 0xFFFF; /*VCRC SEED */\r
-\r
- while( size-- ){\r
- VCRC = (VCRC >> 8) ^ crc16_table[(VCRC & 0xFF) ^ *byte++];\r
- }\r
-\r
- return(VCRC ^ 0xFFFF);\r
-}\r
-\r
-/***********************************************************************************/\r
-/* Check ICRC */\r
-/***********************************************************************************/\r
-call_result_t\r
-check_ICRC(IB_PKT_st *pkt_st_p, u_int16_t *packet_start_p)\r
-{\r
- u_int32_t extracted_ICRC;\r
- u_int32_t calc_ICRC;\r
- u_int8_t* start_ICRC_p;\r
- LNH_t LNH;\r
-\r
- LNH = (pkt_st_p->lrh_st_p)->LNH;/*For calc ICRC */\r
- start_ICRC_p =(u_int8_t*)(packet_start_p) + ((pkt_st_p->lrh_st_p)->PktLen) * IBWORD - ICRC_LEN;\r
-\r
- extract_ICRC((u_int16_t*)start_ICRC_p, &extracted_ICRC);\r
- calc_ICRC = fast_calc_ICRC(pkt_st_p->packet_size, packet_start_p, LNH);\r
-// calc_ICRC = __be32_to_cpu(calc_ICRC);\r
-\r
- if(calc_ICRC != extracted_ICRC){\r
- MTL_TRACE('1', "\n** ERROR extracted ICRC != calc ICRC **\n");\r
- return(MT_ERROR);\r
- }else return(MT_OK);\r
-}\r
-/***********************************************************************************/\r
-/* Check VCRC */\r
-/***********************************************************************************/\r
-call_result_t\r
-check_VCRC(IB_PKT_st *pkt_st_p, u_int16_t *packet_start_p)\r
-{\r
- u_int16_t extracted_VCRC;\r
- u_int16_t calc_VCRC;\r
- u_int8_t* start_VCRC_p;\r
-\r
- start_VCRC_p =(u_int8_t*)(packet_start_p) + ((pkt_st_p->lrh_st_p)->PktLen) * IBWORD ;\r
-\r
- extract_VCRC((u_int16_t*)start_VCRC_p, &extracted_VCRC);\r
- calc_VCRC = fast_calc_VCRC(pkt_st_p->packet_size, packet_start_p);\r
-// calc_VCRC = __be16_to_cpu(calc_VCRC);\r
-\r
- if(calc_VCRC != extracted_VCRC){\r
- MTL_TRACE('1', "\n** ERROR extracted VCRC != calc VCRC **\n");\r
- return(MT_ERROR);\r
- }else return(MT_OK);\r
-}\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#ifndef H_INTERNAL_FUNCTIONS_H\r
-#define H_INTERNAL_FUNCTIONS_H\r
-\r
-/* Layers Includes */ \r
-#ifdef VXWORKS_OS\r
-#include <bit_ops.h>\r
-#endif /* VXWORKS_OS */\r
-#include <mtl_types.h>\r
-#include <mtl_common.h>\r
-\r
-/* MPGA Includes */ \r
-#include <packet_append.h>\r
-\r
-\r
-#define LITTLE_ENDIAN_TYPE 0\r
-#define BIG_ENDIAN_TYPE 1\r
-\r
-#define ALLOCATE(__type,__num) (__type *)INTR_MALLOC((__num)*sizeof(__type))\r
-\r
-#define INSERTF(W,O1,F,O2,S) ( MT_INSERT32(W, MT_EXTRACT32(F, O2, S), O1, S) )\r
-#define IS_LITTLE_ENDIAN (is_little_endian())\r
-#define IS_BIG_ENDIAN (is_little_endian())\r
-\r
-\r
-/******************************************************************************\r
-* Function: allocate_packet\r
-*\r
-* Description: This function aloocate IB packets for the transport layer only.\r
-* it allocates the buf acording to the packet size given ,\r
-* The function will make the malloc for the packet buffer.\r
-* and will appdate the payload_buf_p.\r
-*\r
-*\r
-* Parameters:\r
-* payload_size(in) u_int16_t\r
-* The size of the packet payload.\r
-* payload_buf_p(in) u_int16_t *\r
-* A pointer to the payload buffer.\r
-* packet_size_p(out) u_int16_t *\r
-* The full size of the packet (for transport layer). will update if need.\r
-* packet_buf_p(out) u_int16_t **\r
-* A pointer to the packet pointer (will be allocated by the function.\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR .\r
-* MT_EKMALLOC. could not allocate mem .\r
-*\r
-*****************************************************************************/\r
-call_result_t\r
-allocate_packet(u_int16_t payload_size, u_int16_t *payload_buf_p,\r
- u_int16_t packet_size, u_int16_t **packet_buf_p);\r
-\r
-/******************************************************************************\r
-* Function: allocate_packet_LRH\r
-*\r
-* Description: This function aloocate IB packets for the transport layer only.\r
-* it allocates the buf acording to the packet size given ,\r
-* The function will make the malloc for the packet buffer.\r
-* and will appdate the payload_buf_p.\r
-*\r
-*\r
-* Parameters:\r
-* TCRC_packet_size(in) u_int16_t\r
-* The size of the Transport packet with the crc .\r
-* t_packet_size(in) u_int16_t\r
-* The size of the Transport packet with out the crc .\r
-* t_packet_buf_p(in) u_int16_t *\r
-* A pointer to the transport packet.\r
-* packet_size(in) u_int16_t\r
-* The full size of the packet with the LRH.\r
-* packet_buf_p(out) u_int16_t **\r
-* A pointer to the packet pointer (will be allocated by the function).\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR .\r
-* MT_EKMALLOC. could not allocate mem .\r
-*\r
-*****************************************************************************/\r
-call_result_t\r
-allocate_packet_LRH(u_int16_t TCRC_packet_size, u_int16_t t_packet_size,\r
- u_int16_t *t_packet_buf_p, u_int16_t packet_size, u_int16_t **packet_buf_p);\r
-\r
-/******************************************************************************\r
-* Function: analyze_trans_packet\r
-*\r
-* Description: This function Analyze transport layer packets .\r
-* and updates the needed structures acording to its content.\r
-*\r
-* Parameters:\r
-* pkt_st_p(out) IB_Pkt_st *\r
-* A pointer to a packet structure that will be update by the function.\r
-* packet_buf_p(in) u_int16_t **\r
-* A pointer to the start of the packet (Must have LRH field) .\r
-*\r
-* NOTE : the function will allocate mem for the inside buffers\r
-* and it is the user responsibility for free it.\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR\r
-*\r
-*****************************************************************************/\r
-call_result_t\r
-analyze_trans_packet(IB_PKT_st *pkt_st_p, u_int16_t **packet_buf_p);\r
-\r
-/******************************************************************************\r
-* Function: is_it_little_endian\r
-*\r
-* Description: This function checks if the machine is a big or little endian.\r
-* it will return IS_LITTLE_ENDAIN (0) if it is a little endain and\r
-* IS_BIG_ENDAIN (1) if it is a big_endian machine.\r
-*\r
-* Parameters:\r
-*\r
-* Returns:\r
-* u_int8_t:\r
-* LITTLE_ENDAIN_TYPE (0).\r
-* BIG_ENDAIN_TYPE (1).\r
-*\r
-*****************************************************************************/\r
-u_int8_t is_little_endian(void);\r
-\r
-/******************************************************************************\r
-* Function: little_endian_16\r
-*\r
-* Description: This function convert Big endain implimintation to little.\r
-*\r
-* all The parametrs are:\r
-* byte_x(in) u_int8_t\r
-* The first byte is the LSB and so on\r
-*\r
-* Returns:\r
-* u_int16_t:\r
-******************************************************************************/\r
-u_int16_t\r
-little_endian_16(u_int8_t byte_0, u_int8_t byte_1);\r
-\r
-/******************************************************************************\r
-* Function: little_endian_32\r
-*\r
-* Description: This function convert Big endain implimintation to little.\r
-*\r
-* all The parametrs are:\r
-* byte_x(in) u_int8_t\r
-* The first byte is the LSB and so on\r
-*\r
-* Returns:\r
-* u_int32_t:\r
-******************************************************************************/\r
-u_int32_t\r
-little_endian_32(u_int8_t byte_0, u_int8_t byte_1, u_int8_t byte_2, u_int8_t byte_3);\r
-\r
-/******************************************************************************\r
-* Function: little_endian_64\r
-*\r
-* Description: This function convert Big endain implimintation to little.\r
-*\r
-* all The parametrs are:\r
-* byte_x(in) u_int8_t\r
-* The first byte is the LSB and so on\r
-*\r
-* Returns:\r
-* u_int64_t:\r
-******************************************************************************/\r
-u_int64_t\r
-little_endian_64(u_int8_t byte_0, u_int8_t byte_1, u_int8_t byte_2, u_int8_t byte_3,\r
- u_int8_t byte_4, u_int8_t byte_5, u_int8_t byte_6, u_int8_t byte_7);\r
-\r
-/******************************************************************************\r
-* Function: init pkt st (init packet struct)\r
-*\r
-* Description: This function inisilize the pkt_st members with null pointer.\r
-* and zero for the packet size member.\r
-*\r
-* all The parametrs are:\r
-* pkt_st_p(out) IB_PKY_st\r
-* packet struct pointer .\r
-*\r
-* Returns:\r
-* MT_OK\r
-* MT_ERROR\r
-******************************************************************************/\r
-call_result_t\r
-init_pkt_st(IB_PKT_st *pkt_st_p);\r
-\r
-/******************************************************************************\r
-* Function: Fast calc ICRC\r
-*\r
-* Description: This function calculate the ICRC only if it is an IBA_GLOBAL\r
-* or IBA_LOCAL packet .\r
-*\r
-* all The parametrs are:\r
-* packet_size(in) u_int8_t\r
-* The packet size .\r
-* packet_buf_p(in) u_int16_t*\r
-* Pointer to the start of the packet befor the LRH field\r
-* LNH(in) LNH_t\r
-* Packet kind IBA_GLOBAL LOCAL (RAW GRH) (RAW RWH)\r
-*\r
-* Returns:\r
-* CALC ICRC (u_int32_t)\r
-******************************************************************************/\r
-u_int32_t\r
-fast_calc_ICRC(u_int16_t packet_size, u_int16_t *packet_buf_p,LNH_t LNH);\r
-\r
-/******************************************************************************\r
-* Function: Fast calc VCRC\r
-*\r
-* Description: This function calculate the VCRC of the IB Packet.\r
-*\r
-* all The parametrs are:\r
-* packet_size(in) u_int8_t\r
-* The packet size .\r
-* packet_buf_p(in) u_int16_t*\r
-* Pointer to the start of the packet befor the LRH field\r
-*\r
-* Returns:\r
-* CALC VCRC (u_int16_t)\r
-******************************************************************************/\r
-u_int16_t\r
-fast_calc_VCRC(u_int16_t packet_size, u_int16_t *packet_buf_p);\r
-\r
-/******************************************************************************\r
-* Function: Update ICRC\r
-*\r
-* Description: This function is updating The ICRC using the crc32 .\r
-* table for a fast calcculation.\r
-*\r
-* all The parametrs are:\r
-* packet_size(in) u_int8_t\r
-* The packet size .\r
-* packet_buf_p(in) u_int16_t*\r
-* Pointer to the start of the packet befor the LRH field\r
-* LNH(in) LNH_t\r
-* Packet kind IBA_GLOBAL LOCAL (RAW GRH) (RAW RWH)\r
-*\r
-* Returns:\r
-* CALC ICRC (u_int32_t)\r
-******************************************************************************/\r
-u_int32_t\r
-update_ICRC(u_int8_t *byte, u_int16_t size, LNH_t LNH);\r
-\r
-/******************************************************************************\r
-* Function: Update VCRC\r
-*\r
-* Description: This function is updating The VCRC using the crc16 .\r
-* table for a fast calcculation.\r
-*\r
-* all The parametrs are:\r
-* packet_size(in) u_int8_t\r
-* The packet size .\r
-* packet_buf_p(in) u_int16_t*\r
-* Pointer to the start of the packet befor the LRH field\r
-*\r
-* Returns:\r
-* CALC VCRC (u_int16_t)\r
-******************************************************************************/\r
-u_int16_t\r
-update_VCRC(u_int8_t *byte, u_int16_t size);\r
-\r
-/******************************************************************************\r
-* Function: Cheak VCRC\r
-*\r
-* Description: This function is cheaking The VCRC using the crc16 .\r
-* table for a fast calcculation and extract_VCRC function for compering.\r
-* the 2 results.\r
-*\r
-* all The parametrs are:\r
-* pkt_st_p(in) IB_PKT_ST *\r
-* General struct packet .\r
-* packet_start_p(in) u_int16_t*\r
-* Pointer to the start of the packet befor the LRH field\r
-*\r
-* Returns:\r
-* MT_OK results the same .\r
-* MT_ERROR .\r
-******************************************************************************/\r
-call_result_t\r
-check_VCRC(IB_PKT_st *pkt_st_p, u_int16_t *packet_start_p);\r
-\r
-/******************************************************************************\r
-* Function: Cheak ICRC\r
-*\r
-* Description: This function is cheaking The ICRC using the crc16 .\r
-* table for a fast calcculation and extract_ICRC function for compering.\r
-* the 2 results.\r
-*\r
-* all The parametrs are:\r
-* pkt_st_p(in) IB_PKT_ST *\r
-* General struct packet .\r
-* packet_start_p(in) u_int16_t*\r
-* Pointer to the start of the packet befor the LRH field\r
-*\r
-* Returns:\r
-* MT_OK\r
-* MT_ERROR.\r
-******************************************************************************/\r
-call_result_t\r
-check_ICRC(IB_PKT_st *pkt_st_p, u_int16_t *packet_start_p);\r
-\r
-#endif /* internal function */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-/************************************/\r
-\r
-\r
-#ifdef __LINUX__\r
-#ifdef MT_KERNEL\r
-#include <linux/module.h>\r
-//#include <linux/modversions.h>\r
-#endif\r
-#endif\r
-\r
-\r
-#include <mpga.h>\r
-#include <ib_opcodes.h>\r
-#include <packet_append.h>\r
-#include <internal_functions.h>\r
-#include <bit_ops.h>\r
-\r
-/************************************/\r
-\r
-#ifndef VXWORKS_OS\r
-#ifdef __WIN__\r
-#define MLOCK(__buff, __size) 0 \r
-#else\r
-\r
-#ifndef MT_KERNEL \r
-#include <sys/mman.h> /* for mlock function */\r
-#define MLOCK(__buff, __size) mlock(__buff, __size)\r
-#else\r
-#define MLOCK(__buff, __size) 0 \r
-#endif\r
-\r
-#endif\r
-\r
-#else /* VXWORKS_OS */\r
-#define MLOCK(__buff, __size) 0 \r
-#endif /* VXWORKS_OS */\r
-\r
-\r
-/*********************************************************************************/\r
-/* build packet with lrh */\r
-/*********************************************************************************/\r
-call_result_t\r
-MPGA_build_pkt_lrh (IB_LRH_st *lrh_st_p, u_int16_t t_packet_size, void *t_packet_buf_vp,\r
- u_int16_t *packet_size_p, void **packet_buf_vp,LNH_t LNH)\r
-{\r
- u_int8_t *start_LRH_p;\r
- u_int16_t TCRC_packet_size = 0;/*This arg will be send to the allocate function*/\r
- u_int32_t ICRC = 0; /*for making space for the crc fileds*/\r
- u_int16_t VCRC = 0;\r
- u_int8_t *start_ICRC_p;\r
- u_int8_t *start_VCRC_p;\r
- u_int16_t **packet_buf_p;\r
- u_int16_t *t_packet_buf_p;\r
- u_int8_t align = 0;\r
-\r
- packet_buf_p = (u_int16_t**)packet_buf_vp; /*casting to u_int16_t */\r
- t_packet_buf_p = (u_int16_t*)t_packet_buf_vp;\r
-\r
- if(LNH == IBA_LOCAL) TCRC_packet_size = t_packet_size + ICRC_LEN + VCRC_LEN;\r
- else{\r
- if(LNH == RAW) align = (4 - (t_packet_size % IBWORD)) % IBWORD; /*should be RAW packet at this stage*/\r
- TCRC_packet_size = t_packet_size + VCRC_LEN + align;/*for sending to the allocate functiom*/\r
- }\r
-\r
- (*packet_size_p) = TCRC_packet_size + LRH_LEN; /*CRC fields are included*/\r
-\r
-\r
- if((allocate_packet_LRH(TCRC_packet_size, t_packet_size, t_packet_buf_p,\r
- *packet_size_p, packet_buf_p)) != MT_OK) return(MT_EKMALLOC);\r
- /*packet_bup_p is a p2p*/\r
-\r
-/*Update the fields in the given lrh struct*/\r
- lrh_st_p->LNH = (u_int8_t)LNH;\r
- lrh_st_p->PktLen = (*packet_size_p - VCRC_LEN) / IBWORD;\r
- /*from the firest byte of the LRH till the VCRC in 4 byte word*/\r
- lrh_st_p->reserved1 = 0;\r
- lrh_st_p->reserved2 = 0;\r
-\r
-\r
- start_LRH_p = (u_int8_t*)(*packet_buf_p) - LRH_LEN;\r
-\r
- start_LRH_p[0] = INSERTF(start_LRH_p[0],4,lrh_st_p->VL,0,4);\r
- start_LRH_p[0] = INSERTF(start_LRH_p[0],0,lrh_st_p->LVer,0,4);\r
- start_LRH_p[1] = INSERTF(start_LRH_p[1],4,lrh_st_p->SL,0,4);\r
- start_LRH_p[1] = INSERTF(start_LRH_p[1],2,lrh_st_p->reserved1,0,2);\r
- start_LRH_p[1] = INSERTF(start_LRH_p[1],0,lrh_st_p->LNH,0,2);\r
- start_LRH_p[2] = INSERTF(start_LRH_p[2],0,lrh_st_p->DLID,8,8);\r
- start_LRH_p[3] = INSERTF(start_LRH_p[3],0,lrh_st_p->DLID,0,8);\r
- start_LRH_p[4] = INSERTF(start_LRH_p[4],3,lrh_st_p->reserved2,0,5);\r
- start_LRH_p[4] = INSERTF(start_LRH_p[4],0,lrh_st_p->PktLen,8,3);\r
- start_LRH_p[5] = INSERTF(start_LRH_p[5],0,lrh_st_p->PktLen,0,8);\r
- start_LRH_p[6] = INSERTF(start_LRH_p[6],0,lrh_st_p->SLID,8,8);\r
- start_LRH_p[7] = INSERTF(start_LRH_p[7],0,lrh_st_p->SLID,0,8);\r
-\r
- (*packet_buf_p) = (u_int16_t*)start_LRH_p;\r
-\r
- if(LNH == IBA_LOCAL){ /*appending the ICRC */\r
- start_ICRC_p = (u_int8_t*)start_LRH_p + LRH_LEN + t_packet_size;\r
- ICRC = fast_calc_ICRC(*packet_size_p, *packet_buf_p, LNH);\r
- append_ICRC((u_int16_t*)start_ICRC_p, ICRC);\r
- }\r
-\r
- start_VCRC_p = (u_int8_t*)start_LRH_p + LRH_LEN + TCRC_packet_size -VCRC_LEN;\r
- VCRC = fast_calc_VCRC(*packet_size_p, *packet_buf_p); /* appendinf the VCRC*/\r
- append_VCRC((u_int16_t*)start_VCRC_p, VCRC);\r
-\r
- return(MT_OK);\r
-}\r
-\r
-\r
-/*******************************************************************************/\r
-/* reliable send */\r
-/*******************************************************************************/\r
-call_result_t\r
-MPGA_reliable_send(IB_BTH_st *bth_st_p, u_int16_t payload_size, void *payload_buf_vp,\r
- u_int16_t *packet_size_p, void **packet_buf_vp, IB_pkt_place packet_place)\r
-{\r
- return(MT_ENOSYS);\r
-}\r
-\r
-/*******************************************************************************/\r
-/* reliable send only */\r
-/*******************************************************************************/\r
-call_result_t\r
-MPGA_rc_send_only(IB_BTH_st *bth_st_p, u_int16_t payload_size, void *payload_buf_vp,\r
- u_int16_t *packet_size_p, void **packet_buf_vp)\r
-{\r
- u_int16_t header_size;\r
- u_int16_t packet_size;\r
- u_int16_t *payload_buf_p;\r
- u_int16_t **packet_buf_p;\r
-\r
- packet_buf_p = (u_int16_t**)packet_buf_vp;\r
- payload_buf_p = (u_int16_t*)payload_buf_vp;/*casting the void to u_int16_t* ,data could be 4096B*/\r
-\r
- header_size = RC_SEND_ONLY_LEN; /*init parameters*/\r
- packet_size = header_size + payload_size + ((IBWORD - (payload_size % IBWORD)) % IBWORD);\r
-\r
- /*Updating fields and given arguments*/\r
-(*packet_size_p) = packet_size;\r
- bth_st_p->OpCode = RC_SEND_ONLY_OP; /*opcode is 00000100 */\r
-\r
- if((allocate_packet(payload_size, payload_buf_p, packet_size, packet_buf_p)) != MT_OK)\r
- return(MT_EKMALLOC);\r
-\r
- /*packet_bup_p is a p2p*/\r
- /*printf("\n in before append bth reliable packet_buf_p is %d",(*packet_buf_p));*/\r
-\r
- if((append_BTH (bth_st_p, packet_buf_p, payload_size)) != MT_OK) return(MT_ERROR);\r
- /*appending the bth field */\r
-\r
- return(MT_OK);\r
-}\r
-\r
-/***********************************************************************************/\r
-/* reliable rdma write only */\r
-/***********************************************************************************/\r
-call_result_t\r
-MPGA_rc_rdma_w_only(IB_BTH_st *bth_st_p, IB_RETH_st *reth_st_p,\r
- u_int16_t payload_size, void *payload_buf_vp,\r
- u_int16_t *packet_size_p, void **packet_buf_vp)\r
-{\r
- u_int16_t header_size;\r
- u_int16_t packet_size;\r
- u_int16_t *payload_buf_p;\r
- u_int16_t **packet_buf_p;\r
-\r
- packet_buf_p = (u_int16_t**)packet_buf_vp;\r
- payload_buf_p = (u_int16_t*)payload_buf_vp;/*casting the void to u_int16_t* ,data could be 4096B*/\r
- header_size = RC_WRITE_ONLY_LEN; /*init parametrs */\r
- packet_size = header_size + payload_size + ((IBWORD - (payload_size % IBWORD)) % IBWORD);\r
-\r
- (*packet_size_p) = packet_size;/*Update given arg to the packet size with out LRH or GRH */\r
- bth_st_p->OpCode = RC_WRITE_ONLY_OP; /*opcode is 00001001 */\r
-\r
- if((allocate_packet(payload_size, payload_buf_p, packet_size, packet_buf_p)) != MT_OK)\r
- return(MT_EKMALLOC);/*packet_bup_p is a p2p*/\r
-\r
- /*appending the wanted fields*/\r
- if((append_RETH (reth_st_p, packet_buf_p)) != MT_OK) return(MT_ERROR);\r
- /*appending the reth field*/\r
- if((append_BTH (bth_st_p, packet_buf_p, payload_size)) != MT_OK) return(MT_ERROR);\r
- /*appending the bth field */\r
-\r
- return(MT_OK);\r
-}\r
-\r
-\r
-\r
-/***********************************************************************************/\r
-/* reliable rdma write first */\r
-/***********************************************************************************/\r
-call_result_t\r
-MPGA_rc_rdma_w_first(IB_BTH_st *bth_st_p, IB_RETH_st *reth_st_p,\r
- u_int16_t payload_size, void *payload_buf_vp,\r
- u_int16_t *packet_size_p, void **packet_buf_vp)\r
-{\r
- u_int16_t header_size;\r
- u_int16_t packet_size;\r
- u_int16_t *payload_buf_p;\r
- u_int16_t **packet_buf_p;\r
-\r
- packet_buf_p = (u_int16_t**)packet_buf_vp;\r
- payload_buf_p = (u_int16_t*)payload_buf_vp;/*casting the void to u_int16_t* ,data could be 4096B*/\r
- header_size = RC_WRITE_FIRST_LEN; /*init parametrs */\r
- packet_size = header_size + payload_size + ((IBWORD - (payload_size % IBWORD)) % IBWORD);\r
-\r
- (*packet_size_p) = packet_size;/*Update given arg to the packet size with out LRH or GRH */\r
- bth_st_p->OpCode = RC_WRITE_FIRST_OP; /*opcode is 00001001 */\r
-\r
- if((allocate_packet(payload_size, payload_buf_p, packet_size, packet_buf_p)) != MT_OK)\r
- return(MT_EKMALLOC);/*packet_bup_p is a p2p*/\r
-\r
- /*appending the wanted fields*/\r
- if((append_RETH (reth_st_p, packet_buf_p)) != MT_OK) return(MT_ERROR);\r
- /*appending the reth field*/\r
- if((append_BTH (bth_st_p, packet_buf_p, payload_size)) != MT_OK) return(MT_ERROR);\r
- /*appending the bth field */\r
-\r
- return(MT_OK);\r
-}\r
-\r
-\r
-\r
-\r
-/***********************************************************************************/\r
-/* reliable rdma write middle */\r
-/***********************************************************************************/\r
-call_result_t\r
-MPGA_rc_rdma_w_middle(IB_BTH_st *bth_st_p, u_int16_t payload_size,\r
- void *payload_buf_vp, u_int16_t *packet_size_p,\r
- void **packet_buf_vp)\r
-{\r
- u_int16_t header_size;\r
- u_int16_t packet_size;\r
- u_int16_t *payload_buf_p;\r
- u_int16_t **packet_buf_p;\r
-\r
- packet_buf_p = (u_int16_t**)packet_buf_vp;\r
- payload_buf_p = (u_int16_t*)payload_buf_vp;/*casting the void to u_int16_t* ,data could be 4096B*/\r
- header_size = RC_WRITE_MIDDLE_LEN; /*init parametrs */\r
- packet_size = header_size + payload_size + ((IBWORD - (payload_size % IBWORD)) % IBWORD);\r
-\r
- (*packet_size_p) = packet_size;/*Update given arg to the packet size with out LRH or GRH */\r
- bth_st_p->OpCode = RC_WRITE_MIDDLE_OP; /*opcode is 00001001 */\r
-\r
- if((allocate_packet(payload_size, payload_buf_p, packet_size, packet_buf_p)) != MT_OK)\r
- return(MT_EKMALLOC);/*packet_bup_p is a p2p*/\r
-\r
- /*appending the bth field */\r
- if((append_BTH (bth_st_p, packet_buf_p, payload_size)) != MT_OK) return(MT_ERROR);\r
- \r
-\r
- return(MT_OK);\r
-}\r
-\r
-\r
-/***********************************************************************************/\r
-/* reliable rdma write last */\r
-/***********************************************************************************/\r
-call_result_t\r
-MPGA_rc_rdma_w_last(IB_BTH_st *bth_st_p, u_int16_t payload_size,\r
- void *payload_buf_vp, u_int16_t *packet_size_p,\r
- void **packet_buf_vp)\r
-{\r
- u_int16_t header_size;\r
- u_int16_t packet_size;\r
- u_int16_t *payload_buf_p;\r
- u_int16_t **packet_buf_p;\r
-\r
- packet_buf_p = (u_int16_t**)packet_buf_vp;\r
- payload_buf_p = (u_int16_t*)payload_buf_vp;/*casting the void to u_int16_t* ,data could be 4096B*/\r
- header_size = RC_WRITE_LAST_LEN; /*init parametrs */\r
- packet_size = header_size + payload_size + ((IBWORD - (payload_size % IBWORD)) % IBWORD);\r
-\r
- (*packet_size_p) = packet_size;/*Update given arg to the packet size with out LRH or GRH */\r
- bth_st_p->OpCode = RC_WRITE_LAST_OP; /*opcode is 00001001 */\r
-\r
- if((allocate_packet(payload_size, payload_buf_p, packet_size, packet_buf_p)) != MT_OK)\r
- return(MT_EKMALLOC);/*packet_bup_p is a p2p*/\r
-\r
- /*appending the bth field */\r
- if((append_BTH (bth_st_p, packet_buf_p, payload_size)) != MT_OK) return(MT_ERROR);\r
- \r
-\r
- return(MT_OK);\r
-}\r
-\r
-\r
-/***********************************************************************************/\r
-/* reliable rdma read request only */\r
-/***********************************************************************************/\r
-call_result_t\r
-MPGA_rc_rdma_r_req(IB_BTH_st *bth_st_p, IB_RETH_st *reth_st_p,\r
- u_int16_t *packet_size_p, void **packet_buf_vp)\r
-{\r
- u_int16_t header_size;\r
- u_int16_t packet_size;\r
- u_int16_t payload_size = 0;/*For passing on to the functions*/\r
- u_int16_t **packet_buf_p;\r
-\r
- packet_buf_p = (u_int16_t**)packet_buf_vp;\r
- header_size = RC_READ_REQ_LEN; /*init parametrs */\r
- packet_size = header_size; /*No payload in this packet*/\r
-\r
- (*packet_size_p) = packet_size;/*Update given arg to the packet size with out LRH or GRH */\r
- bth_st_p->OpCode = RC_READ_REQ_OP; /*opcode is 00001100 (overwrite)*/\r
-\r
- if((allocate_packet(payload_size, NULL, packet_size, packet_buf_p)) != MT_OK)\r
- return(MT_EKMALLOC); /*packet_bup_p is a p2p*/\r
-\r
- if((append_RETH (reth_st_p, packet_buf_p)) != MT_OK) return(MT_ERROR);\r
- /*appending the reth field*/\r
- if((append_BTH (bth_st_p, packet_buf_p, payload_size)) != MT_OK) return(MT_ERROR);\r
- /*appending the bth field */\r
- return(MT_OK);\r
-}\r
-\r
-/***********************************************************************************/\r
-/* reliable rdma read response (First Middle or Last) */\r
-/***********************************************************************************/\r
-call_result_t\r
-MPGA_rc_rdma_r_resp(IB_BTH_st *bth_st_p, IB_AETH_st *aeth_st_p,\r
- u_int16_t payload_size, void *payload_buf_vp, u_int16_t *packet_size_p, \r
- void **packet_buf_vp, IB_pkt_place packet_place) \r
-{\r
- u_int16_t header_size = 0;\r
- u_int16_t packet_size = 0;\r
- u_int16_t *payload_buf_p;\r
- u_int16_t **packet_buf_p;\r
- \r
- packet_buf_p = (u_int16_t**)packet_buf_vp;\r
- payload_buf_p = (u_int16_t*)payload_buf_vp;/*casting the void to u_int16_t* ,data could be 4096B*/\r
- \r
- switch(packet_place){\r
- case FIRST_PACKET: bth_st_p->OpCode = RC_READ_RESP_FIRST_OP;\r
- header_size = RC_READ_RESP_FIRST_LEN; /*init parametrs */ \r
- break;\r
- case MIDDLE_PACKET: bth_st_p->OpCode = RC_READ_RESP_MIDDLE_OP;\r
- header_size = RC_READ_RESP_MIDDLE_LEN; /*init parametrs */ \r
- break;\r
- case LAST_PACKET: bth_st_p->OpCode = RC_READ_RESP_LAST_OP;\r
- header_size = RC_READ_RESP_LAST_LEN; /*init parametrs */ \r
- break;\r
- default: MTL_ERROR('1', "\nERROR (PLACE) IN rdma r resp\n");\r
- };\r
- \r
- packet_size = header_size + payload_size + ((IBWORD - (payload_size % IBWORD)) % IBWORD); \r
- (*packet_size_p) = packet_size;/*Update given arg to the packet size with out LRH or GRH */ \r
- \r
- if((allocate_packet(payload_size, payload_buf_p, packet_size, packet_buf_p)) != MT_OK)\r
- return(MT_EKMALLOC);/*packet_bup_p is a p2p*/\r
- \r
- /*appending the wanted fields*/\r
- if(packet_place != MIDDLE_PACKET){\r
- if((append_AETH (aeth_st_p, packet_buf_p)) != MT_OK) return(MT_ERROR);\r
- } \r
- /*appending the reth field*/\r
- if((append_BTH (bth_st_p, packet_buf_p, payload_size)) != MT_OK) return(MT_ERROR);\r
- /*appending the bth field */\r
- return(MT_OK);\r
-}\r
- \r
-/***********************************************************************************/\r
-/* reliable rdma read response only */\r
-/***********************************************************************************/\r
-call_result_t\r
-MPGA_rc_rdma_r_resp_only(IB_BTH_st *bth_st_p, IB_AETH_st *aeth_st_p,\r
- u_int16_t payload_size, void *payload_buf_vp,\r
- u_int16_t *packet_size_p, void **packet_buf_vp)\r
-{\r
- u_int16_t header_size;\r
- u_int16_t packet_size;\r
- u_int16_t *payload_buf_p;\r
- u_int16_t **packet_buf_p;\r
-\r
- packet_buf_p = (u_int16_t**)packet_buf_vp;\r
- payload_buf_p = (u_int16_t*)payload_buf_vp;/*casting the void to u_int16_t* ,data could be 4096B*/\r
- header_size = RC_READ_RESP_ONLY_LEN; /*init parametrs */\r
- packet_size = header_size + payload_size + ((IBWORD - (payload_size % IBWORD)) % IBWORD);\r
-\r
- (*packet_size_p) = packet_size;/*Update given arg to the packet size with out LRH or GRH */\r
- bth_st_p->OpCode = RC_READ_RESP_ONLY_OP; /*opcode is 00001001 */\r
-\r
- if((allocate_packet(payload_size, payload_buf_p, packet_size, packet_buf_p)) != MT_OK)\r
- return(MT_EKMALLOC);/*packet_bup_p is a p2p*/\r
-\r
- /*appending the wanted fields*/\r
- if((append_AETH (aeth_st_p, packet_buf_p)) != MT_OK) return(MT_ERROR);\r
- /*appending the reth field*/\r
- if((append_BTH (bth_st_p, packet_buf_p, payload_size)) != MT_OK) return(MT_ERROR);\r
- /*appending the bth field */\r
- return(MT_OK);\r
-}\r
-\r
-/***********************************************************************************/\r
-/* unreliable Datagram send only */\r
-/***********************************************************************************/\r
-call_result_t\r
-MPGA_ud_send_only(IB_BTH_st *bth_st_p, IB_DETH_st *deth_st_p,\r
- u_int16_t payload_size, void *payload_buf_vp,\r
- u_int16_t *packet_size_p, void **packet_buf_vp) \r
-{\r
- u_int16_t header_size;\r
- u_int16_t packet_size;\r
- u_int16_t *payload_buf_p;\r
- u_int16_t **packet_buf_p;\r
-\r
- packet_buf_p = (u_int16_t**)packet_buf_vp;\r
- payload_buf_p = (u_int16_t*)payload_buf_vp;/*casting the void to u_int16_t* ,data could be 4096B*/\r
- header_size = UD_SEND_ONLY_LEN; /*init parametrs */\r
- packet_size = header_size + payload_size + ((IBWORD - (payload_size % IBWORD)) % IBWORD);\r
-\r
- (*packet_size_p) = packet_size;/*Update given arg to the packet size with out LRH or GRH */\r
- bth_st_p->OpCode = UD_SEND_ONLY_OP; /*opcode is 01100100 */\r
-\r
- if((allocate_packet(payload_size, payload_buf_p, packet_size, packet_buf_p)) != MT_OK)\r
- return(MT_EKMALLOC);/*packet_bup_p is a p2p*/\r
-\r
- /*appending the wanted fields*/\r
- if((append_DETH (deth_st_p, packet_buf_p)) != MT_OK) return(MT_ERROR);\r
- /*appending the reth field*/\r
- if((append_BTH (bth_st_p, packet_buf_p, payload_size)) != MT_OK) return(MT_ERROR);\r
- /*appending the bth field */\r
- return(MT_OK);\r
-}\r
-\r
-\r
-\r
-/************************************************************************/\r
-/* Bulding headers only */\r
-/************************************************************************/\r
-\r
-\r
-\r
-/*************************************************************************/\r
-/* fast RC send first */\r
-/*************************************************************************/\r
-call_result_t \r
-MPGA_fast_rc_send_first(IB_LRH_st *lrh_st_p, IB_GRH_st *grh_st_p,\r
- IB_BTH_st *bth_st_p, LNH_t LNH, u_int16_t payload_size, \r
- u_int16_t *header_size_p, void **header_buf_p)\r
-{\r
- u_int16_t header_size = 0, packet_size;\r
- u_int8_t* temp_header_buff;\r
-\r
- if (LNH != IBA_LOCAL) return(MT_ENOSYS);\r
-\r
- header_size = RC_SEND_FIRST_LEN + LRH_LEN; \r
- packet_size = header_size + payload_size + ((IBWORD - (payload_size % IBWORD)) % IBWORD) + ICRC_LEN + VCRC_LEN;\r
-\r
- (*header_size_p) = header_size;/*Update given arg to the packet size with out LRH or GRH */\r
- bth_st_p->OpCode = RC_SEND_FIRST_OP; /*opcode is 01100100 */\r
-\r
- if ((temp_header_buff = ALLOCATE(u_int8_t,(header_size)))== NULL)\r
- { /* Allocting size in bytes*/\r
- MTL_TRACE('5', "\nfailed to allocate temp_buffer_p");\r
- return(MT_ENOMEM);\r
- };\r
- \r
- if(MLOCK(temp_header_buff, header_size)){\r
- MTL_TRACE('5', "\nfailed to lock temp_head_buff");\r
- return(MT_ENOMEM);\r
- };\r
- \r
-\r
- temp_header_buff += header_size; /* Building the header from end to start */ \r
-\r
- /*************appending the wanted fields**********************/\r
- if ((append_BTH (bth_st_p, (u_int16_t**)&temp_header_buff, payload_size)) != MT_OK) return(MT_ERROR);\r
- /*appending the bth field */\r
-\r
- if ((append_LRH (lrh_st_p, packet_size, (u_int16_t**)&temp_header_buff, LNH)) != MT_OK) return(MT_ERROR);\r
- /*appending the lrh field */\r
-\r
- *header_buf_p = temp_header_buff;\r
-\r
- return(MT_OK);\r
-}\r
-/*************************************************************************/\r
-/* fast RC send middle */\r
-/*************************************************************************/\r
-call_result_t \r
-MPGA_fast_rc_send_middle(IB_LRH_st *lrh_st_p, IB_GRH_st *grh_st_p,\r
- IB_BTH_st *bth_st_p, LNH_t LNH, u_int16_t payload_size, \r
- u_int16_t *header_size_p, void **header_buf_p)\r
-{\r
- u_int16_t header_size = 0, packet_size;\r
- u_int8_t* temp_header_buff;\r
-\r
- if (LNH != IBA_LOCAL) return(MT_ENOSYS);\r
-\r
- header_size = RC_SEND_MIDDLE_LEN + LRH_LEN; \r
- packet_size = header_size + payload_size + ((IBWORD - (payload_size % IBWORD)) % IBWORD) + ICRC_LEN + VCRC_LEN;\r
-\r
- (*header_size_p) = header_size;/*Update given arg to the packet size with out LRH or GRH */\r
- bth_st_p->OpCode = RC_SEND_MIDDLE_OP; \r
-\r
- if ((temp_header_buff = ALLOCATE(u_int8_t,(header_size)))== NULL)\r
- { /* Allocting size in bytes*/\r
- MTL_TRACE('5', "\nfailed to allocate temp_buffer_p");\r
- return(MT_ENOSYS);\r
- };\r
-\r
- if(MLOCK(temp_header_buff, header_size)){\r
- MTL_TRACE('5', "\nfailed to lock temp_head_buff");\r
- return(MT_ENOMEM);\r
- };\r
-\r
- temp_header_buff += header_size; /* Building the header from end to start */ \r
-\r
- /*************appending the wanted fields**********************/\r
- if ((append_BTH (bth_st_p, (u_int16_t**)&temp_header_buff, payload_size)) != MT_OK) return(MT_ERROR);\r
- /*appending the bth field */\r
-\r
- if ((append_LRH (lrh_st_p, packet_size, (u_int16_t**)&temp_header_buff, LNH)) != MT_OK) return(MT_ERROR);\r
- /*appending the lrh field */\r
-\r
- *header_buf_p = temp_header_buff;\r
-\r
- return(MT_OK);\r
-}\r
-/*************************************************************************/\r
-/* fast RC send last */\r
-/*************************************************************************/\r
-call_result_t \r
-MPGA_fast_rc_send_last(IB_LRH_st *lrh_st_p, IB_GRH_st *grh_st_p,\r
- IB_BTH_st *bth_st_p, LNH_t LNH, u_int16_t payload_size, \r
- u_int16_t *header_size_p, void **header_buf_p)\r
-{\r
- u_int16_t header_size = 0, packet_size;\r
- u_int8_t* temp_header_buff;\r
-\r
- if (LNH != IBA_LOCAL) return(MT_ENOSYS);\r
-\r
- header_size = RC_SEND_LAST_LEN + LRH_LEN; \r
- packet_size = header_size + payload_size + ((IBWORD - (payload_size % IBWORD)) % IBWORD) + ICRC_LEN + VCRC_LEN;\r
-\r
- (*header_size_p) = header_size;/*Update given arg to the packet size with out LRH or GRH */\r
- bth_st_p->OpCode = RC_SEND_LAST_OP; \r
-\r
- if ((temp_header_buff = ALLOCATE(u_int8_t,(header_size)))== NULL)\r
- { /* Allocting size in bytes*/\r
- MTL_TRACE('5', "\nfailed to allocate temp_buffer_p");\r
- return(MT_EAGAIN);\r
- };\r
-\r
- if(MLOCK(temp_header_buff, header_size)){\r
- MTL_TRACE('5', "\nfailed to lock temp_head_buff");\r
- return(MT_ENOMEM);\r
- };\r
-\r
-\r
- temp_header_buff += header_size; /* Building the header from end to start */ \r
-\r
- /*************appending the wanted fields**********************/\r
- if ((append_BTH (bth_st_p, (u_int16_t**)&temp_header_buff, payload_size)) != MT_OK) return(MT_ERROR);\r
- /*appending the bth field */\r
-\r
- if ((append_LRH (lrh_st_p, packet_size, (u_int16_t**)&temp_header_buff, LNH)) != MT_OK) return(MT_ERROR);\r
- /*appending the lrh field */\r
-\r
- *header_buf_p = temp_header_buff;\r
-\r
- return(MT_OK);\r
-}\r
-/*************************************************************************/\r
-/* fast RC send only */\r
-/*************************************************************************/\r
-call_result_t \r
-MPGA_fast_rc_send_only(IB_LRH_st *lrh_st_p, IB_GRH_st *grh_st_p,\r
- IB_BTH_st *bth_st_p, LNH_t LNH, u_int16_t payload_size, \r
- u_int16_t *header_size_p, void **header_buf_p)\r
-{\r
- u_int16_t header_size = 0, packet_size;\r
- u_int8_t* temp_header_buff;\r
-\r
- if (LNH != IBA_LOCAL) return(MT_EAGAIN);\r
-\r
- header_size = RC_SEND_ONLY_LEN + LRH_LEN; \r
- packet_size = header_size + payload_size + ((IBWORD - (payload_size % IBWORD)) % IBWORD) + ICRC_LEN + VCRC_LEN;\r
-\r
- (*header_size_p) = header_size;/*Update given arg to the packet size with out LRH or GRH */\r
- bth_st_p->OpCode = RC_SEND_ONLY_OP; /*opcode is 01100100 */\r
-\r
- if ((temp_header_buff = ALLOCATE(u_int8_t,(header_size)))== NULL)\r
- { /* Allocting size in bytes*/\r
- MTL_TRACE('5', "\nfailed to allocate temp_buffer_p");\r
- return(MT_ENOMEM);\r
- };\r
-\r
- if(MLOCK(temp_header_buff, header_size)){\r
- MTL_TRACE('5', "\nfailed to lock temp_head_buff");\r
- return(MT_ENOMEM);\r
- };\r
-\r
- temp_header_buff += header_size; /* Building the header from end to start */ \r
-\r
- /*************appending the wanted fields**********************/\r
- if ((append_BTH (bth_st_p, (u_int16_t**)&temp_header_buff, payload_size)) != MT_OK) return(MT_ERROR);\r
- /*appending the bth field */\r
-\r
- if ((append_LRH (lrh_st_p, packet_size, (u_int16_t**)&temp_header_buff, LNH)) != MT_OK) return(MT_ERROR);\r
- /*appending the lrh field */\r
-\r
- *header_buf_p = temp_header_buff;\r
-\r
- return(MT_OK);\r
-}\r
-/*************************************************************************/\r
-/* fast RC RDMA read response first */\r
-/*************************************************************************/\r
-call_result_t \r
-MPGA_fast_rc_read_resp_first(IB_LRH_st *lrh_st_p, IB_GRH_st *grh_st_p,\r
- IB_BTH_st *bth_st_p, IB_AETH_st *aeth_st_p, LNH_t LNH, \r
- u_int16_t payload_size, u_int16_t *header_size_p, \r
- void **header_buf_p)\r
-{\r
- u_int16_t header_size = 0, packet_size;\r
- u_int8_t* temp_header_buff;\r
-\r
- if (LNH != IBA_LOCAL) return(MT_ENOSYS);\r
-\r
- header_size = RC_READ_RESP_FIRST_LEN + LRH_LEN; \r
- packet_size = header_size + payload_size + ((IBWORD - (payload_size % IBWORD)) % IBWORD) + ICRC_LEN + VCRC_LEN;\r
-\r
- (*header_size_p) = header_size;/*Update given arg to the packet size with out LRH or GRH */\r
- bth_st_p->OpCode = RC_READ_RESP_FIRST_OP; \r
-\r
- if ((temp_header_buff = ALLOCATE(u_int8_t,(header_size)))== NULL)\r
- { /* Allocting size in bytes*/\r
- MTL_TRACE('5', "\nfailed to allocate temp_buffer_p in rc read resp first");\r
- return(MT_ENOMEM);\r
- };\r
-\r
- if(MLOCK(temp_header_buff, header_size)){\r
- MTL_TRACE('5', "\nfailed to lock temp_head_buff");\r
- return(MT_ENOMEM);\r
- };\r
-\r
- temp_header_buff += header_size; /* Building the header from end to start */ \r
-\r
- /*************appending the wanted fields**********************/\r
- if ((append_AETH (aeth_st_p, (u_int16_t**)&temp_header_buff)) != MT_OK) return(MT_ERROR);\r
- /*appending the aeth field */\r
-\r
-\r
- if ((append_BTH (bth_st_p, (u_int16_t**)&temp_header_buff, payload_size)) != MT_OK) return(MT_ERROR);\r
- /*appending the bth field */\r
-\r
- if ((append_LRH (lrh_st_p, packet_size, (u_int16_t**)&temp_header_buff, LNH)) != MT_OK) return(MT_ERROR);\r
- /*appending the lrh field */\r
-\r
- *header_buf_p = temp_header_buff;\r
-\r
- return(MT_OK);\r
-}\r
-/*************************************************************************/\r
-/* fast RC RDMA read response middle */\r
-/*************************************************************************/\r
-call_result_t \r
-MPGA_fast_rc_read_resp_middle(IB_LRH_st *lrh_st_p, IB_GRH_st *grh_st_p,\r
- IB_BTH_st *bth_st_p, LNH_t LNH, u_int16_t payload_size, \r
- u_int16_t *header_size_p, void **header_buf_p)\r
-{\r
- u_int16_t header_size = 0, packet_size;\r
- u_int8_t* temp_header_buff;\r
-\r
- if (LNH != IBA_LOCAL) return(MT_ENOSYS);\r
-\r
- header_size = RC_READ_RESP_MIDDLE_LEN + LRH_LEN; \r
- packet_size = header_size + payload_size + ((IBWORD - (payload_size % IBWORD)) % IBWORD) + ICRC_LEN + VCRC_LEN;\r
-\r
- (*header_size_p) = header_size;/*Update given arg to the packet size with out LRH or GRH */\r
- bth_st_p->OpCode = RC_READ_RESP_MIDDLE_OP; \r
-\r
- if ((temp_header_buff = ALLOCATE(u_int8_t,(header_size)))== NULL)\r
- { /* Allocting size in bytes*/\r
- MTL_TRACE('5', "\nfailed to allocate temp_buffer_p in rc read resp middle");\r
- return(MT_ENOMEM);\r
- };\r
-\r
- if(MLOCK(temp_header_buff, header_size)){\r
- MTL_TRACE('5', "\nfailed to lock temp_head_buff");\r
- return(MT_ENOMEM);\r
- };\r
-\r
-\r
- temp_header_buff += header_size; /* Building the header from end to start */ \r
-\r
- /*************appending the wanted fields**********************/\r
- \r
- if ((append_BTH (bth_st_p, (u_int16_t**)&temp_header_buff, payload_size)) != MT_OK) return(MT_ERROR);\r
- /*appending the bth field */\r
-\r
- if ((append_LRH (lrh_st_p, packet_size, (u_int16_t**)&temp_header_buff, LNH)) != MT_OK) return(MT_ERROR);\r
- /*appending the lrh field */\r
-\r
- *header_buf_p = temp_header_buff;\r
-\r
- return(MT_OK);\r
-}\r
-/*************************************************************************/\r
-/* fast RC RDMA read response last */\r
-/*************************************************************************/\r
-call_result_t \r
-MPGA_fast_rc_read_resp_last(IB_LRH_st *lrh_st_p, IB_GRH_st *grh_st_p,\r
- IB_BTH_st *bth_st_p, IB_AETH_st *aeth_st_p, LNH_t LNH, \r
- u_int16_t payload_size, u_int16_t *header_size_p, \r
- void **header_buf_p)\r
-{\r
- u_int16_t header_size = 0, packet_size;\r
- u_int8_t* temp_header_buff;\r
-\r
- if (LNH != IBA_LOCAL) return(MT_ENOSYS);\r
-\r
- header_size = RC_READ_RESP_LAST_LEN + LRH_LEN; \r
- packet_size = header_size + payload_size + ((IBWORD - (payload_size % IBWORD)) % IBWORD) + ICRC_LEN + VCRC_LEN;\r
-\r
- (*header_size_p) = header_size;/*Update given arg to the packet size with out LRH or GRH */\r
- bth_st_p->OpCode = RC_READ_RESP_LAST_OP; \r
-\r
- if ((temp_header_buff = ALLOCATE(u_int8_t,(header_size)))== NULL)\r
- { /* Allocting size in bytes*/\r
- MTL_TRACE('5', "\nfailed to allocate temp_buffer_p in rc read resp last");\r
- return(MT_ENOMEM);\r
- };\r
-\r
- if(MLOCK(temp_header_buff, header_size)){\r
- MTL_TRACE('5', "\nfailed to lock temp_head_buff");\r
- return(MT_ENOMEM);\r
- };\r
-\r
- temp_header_buff += header_size; /* Building the header from end to start */ \r
-\r
- /*************appending the wanted fields**********************/\r
- if ((append_AETH (aeth_st_p, (u_int16_t**)&temp_header_buff)) != MT_OK) return(MT_ERROR);\r
- /*appending the aeth field */\r
-\r
-\r
- if ((append_BTH (bth_st_p, (u_int16_t**)&temp_header_buff, payload_size)) != MT_OK) return(MT_ERROR);\r
- /*appending the bth field */\r
-\r
- if ((append_LRH (lrh_st_p, packet_size, (u_int16_t**)&temp_header_buff, LNH)) != MT_OK) return(MT_ERROR);\r
- /*appending the lrh field */\r
-\r
- *header_buf_p = temp_header_buff;\r
-\r
- return(MT_OK);\r
-}\r
-/*************************************************************************/\r
-/* fast RC RDMA read response only */\r
-/*************************************************************************/\r
-call_result_t \r
-MPGA_fast_rc_read_resp_only(IB_LRH_st *lrh_st_p, IB_GRH_st *grh_st_p,\r
- IB_BTH_st *bth_st_p, IB_AETH_st *aeth_st_p, LNH_t LNH, \r
- u_int16_t payload_size, u_int16_t *header_size_p, \r
- void **header_buf_p)\r
-{\r
- u_int16_t header_size = 0, packet_size;\r
- u_int8_t* temp_header_buff;\r
-\r
- if (LNH != IBA_LOCAL) return(MT_ENOSYS);\r
-\r
- header_size = RC_READ_RESP_ONLY_LEN + LRH_LEN; \r
- packet_size = header_size + payload_size + ((IBWORD - (payload_size % IBWORD)) % IBWORD) + ICRC_LEN + VCRC_LEN;\r
-\r
- (*header_size_p) = header_size;/*Update given arg to the packet size with out LRH or GRH */\r
- bth_st_p->OpCode = RC_READ_RESP_ONLY_OP; \r
-\r
- if ((temp_header_buff = ALLOCATE(u_int8_t,(header_size)))== NULL)\r
- { /* Allocting size in bytes*/\r
- MTL_TRACE('5', "\nfailed to allocate temp_buffer_p in rc read resp only");\r
- return(MT_ENOMEM);\r
- };\r
-\r
- if(MLOCK(temp_header_buff, header_size)){\r
- MTL_TRACE('5', "\nfailed to lock temp_head_buff");\r
- return(MT_ENOMEM);\r
- };\r
-\r
-\r
- temp_header_buff += header_size; /* Building the header from end to start */ \r
-\r
- /*************appending the wanted fields**********************/\r
- if ((append_AETH (aeth_st_p, (u_int16_t**)&temp_header_buff)) != MT_OK) return(MT_ERROR);\r
- /*appending the aeth field */\r
-\r
-\r
- if ((append_BTH (bth_st_p, (u_int16_t**)&temp_header_buff, payload_size)) != MT_OK) return(MT_ERROR);\r
- /*appending the bth field */\r
-\r
- if ((append_LRH (lrh_st_p, packet_size, (u_int16_t**)&temp_header_buff, LNH)) != MT_OK) return(MT_ERROR);\r
- /*appending the lrh field */\r
-\r
- *header_buf_p = temp_header_buff;\r
-\r
- return(MT_OK);\r
-}\r
-\r
-/*************************************************************************/\r
-/* fast RC ACKNOW */\r
-/*************************************************************************/\r
-call_result_t \r
-MPGA_fast_rc_acknowledge(IB_LRH_st *lrh_st_p, IB_GRH_st *grh_st_p,\r
- IB_BTH_st *bth_st_p, IB_AETH_st *aeth_st_p, LNH_t LNH,\r
- u_int16_t *header_size_p, void **header_buf_p)\r
-{\r
- u_int16_t header_size = 0, packet_size;\r
- u_int8_t* temp_header_buff;\r
- u_int16_t payload_size = 0; /* NO payload in Acknowledge packet */ \r
-\r
- if (LNH != IBA_LOCAL) return(MT_ENOSYS);\r
-\r
- header_size = RC_ACKNOWLEDGE_LEN + LRH_LEN; /*UD is for transport only init parametrs */\r
- packet_size = header_size + ICRC_LEN + VCRC_LEN;\r
-\r
- (*header_size_p) = header_size;/*Update given arg to the packet size with out LRH or GRH */\r
- bth_st_p->OpCode = RC_ACKNOWLEDGE_OP; /*opcode is 01100100 */\r
-\r
- if ((temp_header_buff = ALLOCATE(u_int8_t,(header_size)))== NULL)\r
- { /* Allocting size in bytes*/\r
- MTL_TRACE('5', "\nfailed to allocate temp_buffer_p");\r
- return(MT_ENOMEM);\r
- };\r
-\r
- if(MLOCK(temp_header_buff, header_size)){\r
- MTL_TRACE('5', "\nfailed to lock temp_head_buff");\r
- return(MT_ENOMEM);\r
- };\r
-\r
- temp_header_buff += header_size; \r
-\r
- /*************appending the wanted fields**********************/\r
- if ((append_AETH (aeth_st_p, (u_int16_t**)&temp_header_buff)) != MT_OK) return(MT_ERROR);\r
- /*appending the aeth field*/\r
-\r
- if ((append_BTH (bth_st_p, (u_int16_t**)&temp_header_buff, payload_size)) != MT_OK) return(MT_ERROR);\r
- /*appending the bth field */\r
-\r
- if ((append_LRH (lrh_st_p, packet_size, (u_int16_t**)&temp_header_buff, LNH)) != MT_OK) return(MT_ERROR);\r
- /*appending the lrh field */\r
-\r
- *header_buf_p = temp_header_buff;\r
-\r
- return(MT_OK);\r
-}\r
-\r
-/*************************************************************************/\r
-/* fast UD packet send only */\r
-/*************************************************************************/\r
-call_result_t\r
-MPGA_fast_ud_send_only(IB_LRH_st *lrh_st_p, IB_BTH_st *bth_st_p,\r
- IB_DETH_st *deth_st_p, u_int16_t payload_size,\r
- u_int16_t *header_size_p, void **header_buf_p)\r
-{\r
- u_int16_t header_size, packet_size;\r
- u_int8_t* temp_header_buff;\r
- LNH_t LNH; \r
-\r
- header_size = UD_SEND_ONLY_LEN + LRH_LEN; /*UD is for transport only init parametrs */\r
- packet_size = header_size + payload_size + ((IBWORD - (payload_size % IBWORD)) % IBWORD) + ICRC_LEN + VCRC_LEN;\r
-\r
- (*header_size_p) = header_size;\r
- bth_st_p->OpCode = UD_SEND_ONLY_OP; \r
-\r
- if ((temp_header_buff = ALLOCATE(u_int8_t,(header_size)))== NULL)\r
- { /* Allocting size in bytes*/\r
- MTL_TRACE('5', "\nfailed to allocate temp_buffer_p");\r
- return(MT_ENOMEM);\r
- };\r
-\r
- if(MLOCK(temp_header_buff, header_size)){\r
- MTL_TRACE('5', "\nfailed to lock temp_head_buff");\r
- return(MT_ENOMEM);\r
- };\r
-\r
-\r
- temp_header_buff += header_size; \r
-\r
- /*************appending the wanted fields**********************/\r
- if ((append_DETH (deth_st_p, (u_int16_t**)&temp_header_buff)) != MT_OK) return(MT_ERROR);\r
- /*appending the deth field*/\r
-\r
- if ((append_BTH (bth_st_p, (u_int16_t**)&temp_header_buff, payload_size)) != MT_OK) return(MT_ERROR);\r
- /*appending the bth field */\r
- LNH = IBA_LOCAL;\r
- if ((append_LRH (lrh_st_p, packet_size, (u_int16_t**)&temp_header_buff, LNH)) != MT_OK) return(MT_ERROR);\r
- /*appending the lrh field */\r
-\r
- *header_buf_p = temp_header_buff;\r
-\r
- \r
- return(MT_OK);\r
-}\r
-\r
-/*************************************************************************/\r
-/* fast UD packet send only with grh */\r
-/*************************************************************************/\r
-call_result_t\r
-MPGA_fast_ud_send_grh(IB_LRH_st *lrh_st_p, IB_GRH_st *grh_st_p, \r
- IB_BTH_st *bth_st_p, IB_DETH_st *deth_st_p, \r
- u_int16_t payload_size, u_int16_t *header_size_p, \r
- void **header_buf_p)\r
-{\r
- u_int16_t header_size, packet_size;\r
- u_int8_t* temp_header_buff;\r
- LNH_t LNH;\r
- \r
- header_size = UD_SEND_ONLY_LEN + LRH_LEN + GRH_LEN; /*UD is for transport only init parametrs */\r
- packet_size = header_size + payload_size + ((IBWORD - (payload_size % IBWORD)) % IBWORD) + ICRC_LEN + VCRC_LEN;\r
-\r
- (*header_size_p) = header_size;\r
- bth_st_p->OpCode = UD_SEND_ONLY_OP; /*opcode is 01100100 */\r
-\r
- if ((temp_header_buff = ALLOCATE(u_int8_t,(header_size)))== NULL)\r
- { /* Allocting size in bytes*/\r
- MTL_TRACE('5', "\nfailed to allocate temp_buffer_p");\r
- return(MT_ENOMEM);\r
- };\r
-\r
- if(MLOCK(temp_header_buff, header_size)){\r
- MTL_TRACE('5', "\nfailed to lock temp_head_buff");\r
- return(MT_ENOMEM);\r
- };\r
-\r
-\r
- temp_header_buff += header_size; \r
-\r
- /*************appending the wanted fields**********************/\r
- if ((append_DETH (deth_st_p, (u_int16_t**)&temp_header_buff)) != MT_OK) return(MT_ERROR);\r
- /*appending the deth field*/\r
-\r
- if ((append_BTH (bth_st_p, (u_int16_t**)&temp_header_buff, payload_size)) != MT_OK) return(MT_ERROR);\r
- /*appending the bth field */\r
-\r
- if ((append_GRH (grh_st_p, packet_size, (u_int16_t**)&temp_header_buff )) != MT_OK) return(MT_ERROR);\r
- \r
- LNH = IBA_GLOBAL;\r
- if ((append_LRH (lrh_st_p, packet_size, (u_int16_t**)&temp_header_buff, LNH)) != MT_OK) return(MT_ERROR);\r
- /*appending the lrh field */\r
-\r
- *header_buf_p = temp_header_buff;\r
-\r
- return(MT_OK);\r
-}\r
-\r
-/***********************************************************************************/\r
-/* Analyze Packet */\r
-/***********************************************************************************/\r
-call_result_t\r
-MPGA_analyze_packet(IB_PKT_st *pkt_st_p, void *packet_buf_vp)\r
-{\r
- u_int16_t *packet_buf_p;\r
- call_result_t return_val = MT_OK;\r
-\r
- packet_buf_p = (u_int16_t*)packet_buf_vp;\r
- init_pkt_st(pkt_st_p);/*inisilize the given struct all the poiters to Null size 0*/\r
-\r
- if((pkt_st_p->lrh_st_p = ALLOCATE(IB_LRH_st,1)) == NULL){ /* Allocting size in bytes*/\r
- MTL_ERROR('1', "\n** ERROR failed to allocate pkt_st_p->lrh_st");\r
- return(MT_EKMALLOC);\r
- };\r
- \r
- MTL_TRACE('5', "\n Extracting lrh field");\r
- extract_LRH((pkt_st_p->lrh_st_p),&packet_buf_p);\r
-/*Sendind start_packet_p and not packet_buf_p */\r
-\r
- /*Init the pkt_st_p parameterers */\r
- pkt_st_p->packet_size = ((pkt_st_p->lrh_st_p)->PktLen * 4) + VCRC_LEN;\r
- pkt_st_p->payload_size = ((pkt_st_p->lrh_st_p)->PktLen * 4) - ICRC_LEN - LRH_LEN; \r
-\r
-switch((pkt_st_p->lrh_st_p)->LNH){\r
-\r
- case RAW: /* 0x0 |LRH|... (Etertype)*/\r
- MTL_TRACE('5', "\n Analayze RAW packet");\r
- (pkt_st_p->payload_buf) = packet_buf_p;/*Updating the pointer to the payload point NO GRH*/\r
- (pkt_st_p->payload_size) += ICRC_LEN; \r
- if(check_VCRC(pkt_st_p, (u_int16_t*)packet_buf_vp)== MT_ERROR){\r
- return_val = MT_ERROR;/*Checking the VCRC*/\r
- }\r
- break;\r
- case IP_NON_IBA_TRANS: /* 0x1 |LRH|GRH|... */\r
- MTL_TRACE('5', "\n Analayze NON IBA packet");\r
- break;\r
- case IBA_LOCAL: /* 0x2 |LRH|BTH|... */\r
- MTL_TRACE('5', "\n Analayze LOCAL packet");\r
- if(check_ICRC(pkt_st_p, (u_int16_t*)packet_buf_vp)== MT_ERROR){\r
- return_val = MT_ERROR;/*Checking the ICRC*/\r
- }\r
- if(check_VCRC(pkt_st_p, (u_int16_t*)packet_buf_vp)== MT_ERROR){\r
- return_val = MT_ERROR;/*Checking the VCRC*/\r
- }\r
- if((analyze_trans_packet(pkt_st_p, &packet_buf_p)) == MT_ERROR){\r
- return_val = MT_ERROR;\r
- }\r
- break;\r
- case IBA_GLOBAL: /* 0x3 |LRH|GRH|BTH|... */\r
- MTL_TRACE('5', "\n Analayze GLOBAL packet");\r
- return_val = MT_ERROR; \r
- break;\r
- default:\r
- MTL_ERROR('1', "\n ERROR case in analyze packet\n");\r
- return_val = MT_ERROR;\r
- break;\r
- }\r
-\r
- return(return_val);\r
-}\r
-\r
-/***********************************************************************************/\r
-/* Analyze Transport Packet */\r
-/***********************************************************************************/\r
-call_result_t\r
-analyze_trans_packet(IB_PKT_st *pkt_st_p, u_int16_t **packet_p)\r
-{\r
-\r
- if((pkt_st_p->bth_st_p = ALLOCATE(IB_BTH_st,1)) == NULL){ /* Allocting size in bytes*/\r
- MTL_ERROR('1', "\nfailed to allocate pkt_st_p->bth_st");\r
- return(MT_EKMALLOC);\r
- };\r
- MTL_TRACE('5', "\n Extracting the BTH field");\r
- extract_BTH((pkt_st_p->bth_st_p), packet_p);\r
- (pkt_st_p->payload_size) -= BTH_LEN;\r
-\r
- switch((pkt_st_p->bth_st_p)->OpCode){\r
-\r
- case RC_SEND_FIRST_OP:\r
- case RC_SEND_MIDDLE_OP:\r
- case RC_SEND_LAST_OP:\r
- case RC_SEND_ONLY_OP: /*0x4 /BTH/pyload/ */\r
- (pkt_st_p->payload_buf) = *packet_p;/*Updating the pointer to the packet buf*/\r
- break;\r
- case RC_WRITE_ONLY_OP: /*0xa /BTH/RETH/pyload/ */\r
- case RC_WRITE_FIRST_OP:\r
- if((pkt_st_p->reth_st_p = ALLOCATE(IB_RETH_st,1)) == NULL){ /* Allocting size in bytes*/\r
- MTL_ERROR('1', "\nfailed to allocate pkt_st_p->reth_st");\r
- return(MT_EKMALLOC);\r
- };\r
- extract_RETH((pkt_st_p->reth_st_p),packet_p);\r
- (pkt_st_p->payload_size) -= RETH_LEN;\r
- (pkt_st_p->payload_buf) = *packet_p;\r
- break;\r
-\r
- case RC_WRITE_LAST_W_IM_OP:\r
- case RC_WRITE_ONLY_W_IM_OP:\r
- if((pkt_st_p->reth_st_p = ALLOCATE(IB_RETH_st,1)) == NULL){ /* Allocting size in bytes*/\r
- MTL_ERROR('1', "\nfailed to allocate pkt_st_p->reth_st");\r
- return(MT_EKMALLOC);\r
- };\r
- extract_RETH((pkt_st_p->reth_st_p),packet_p);\r
- (pkt_st_p->payload_size) -= RETH_LEN;\r
- (pkt_st_p->payload_buf) = *packet_p;\r
- \r
- if((pkt_st_p->immdt_st_p = ALLOCATE(IB_ImmDt_st,1)) == NULL){ /* Allocting size in bytes*/\r
- MTL_ERROR('1', "\nfailed to allocate pkt_st_p->IB_ImmDt_st");\r
- return(MT_EKMALLOC);\r
- };\r
- extract_ImmDt((pkt_st_p->immdt_st_p),packet_p);\r
- (pkt_st_p->payload_size) -= ImmDt_LEN;\r
- (pkt_st_p->payload_buf) = *packet_p;\r
- break;\r
-\r
- case RC_WRITE_LAST_OP: /* BTH */\r
- case RC_WRITE_MIDDLE_OP:\r
- break;\r
- case RC_SEND_ONLY_W_IM_OP:\r
- case RC_SEND_LAST_W_IM_OP:\r
- if((pkt_st_p->immdt_st_p = ALLOCATE(IB_ImmDt_st,1)) == NULL){ /* Allocting size in bytes*/\r
- MTL_ERROR('1', "\nfailed to allocate pkt_st_p->IB_ImmDt_st");\r
- return(MT_EKMALLOC);\r
- };\r
- extract_ImmDt((pkt_st_p->immdt_st_p),packet_p);\r
- (pkt_st_p->payload_size) -= ImmDt_LEN;\r
- (pkt_st_p->payload_buf) = *packet_p;\r
- break;\r
-\r
- case RC_READ_REQ_OP: /*0xc /BTH/RETH/ */\r
- if((pkt_st_p->reth_st_p = ALLOCATE(IB_RETH_st,1)) == NULL){ /* Allocting size in bytes*/\r
- MTL_ERROR('1', "\nfailed to allocate pkt_st_p->reth_st");\r
- return(MT_EKMALLOC);\r
- };\r
- extract_RETH((pkt_st_p->reth_st_p),packet_p);\r
- (pkt_st_p->payload_size) -= RETH_LEN; /* should be zero */\r
- /*No payload to this packet*/\r
- break;\r
- \r
- case RC_READ_RESP_FIRST_OP:\r
- if((pkt_st_p->aeth_st_p = ALLOCATE(IB_AETH_st,1)) == NULL){ /* Allocting size in bytes*/\r
- MTL_ERROR('1', "\nfailed to allocate pkt_st_p->aeth_st");\r
- return(MT_EKMALLOC);\r
- };\r
- extract_AETH((pkt_st_p->aeth_st_p),packet_p); \r
- (pkt_st_p->payload_size) -= AETH_LEN;\r
- (pkt_st_p->payload_buf) = *packet_p; \r
- break;\r
- \r
- case RC_READ_RESP_MIDDLE_OP:\r
- (pkt_st_p->payload_buf) = *packet_p;\r
- break;\r
- \r
- case RC_READ_RESP_LAST_OP: /*BTH/AETH/pyload*/\r
- if((pkt_st_p->aeth_st_p = ALLOCATE(IB_AETH_st,1)) == NULL){ /* Allocting size in bytes*/\r
- MTL_ERROR('1', "\nfailed to allocate pkt_st_p->aeth_st");\r
- return(MT_EKMALLOC);\r
- };\r
- extract_AETH((pkt_st_p->aeth_st_p),packet_p);\r
- (pkt_st_p->payload_size) -= AETH_LEN;\r
- (pkt_st_p->payload_buf) = *packet_p;\r
- break; \r
- \r
- case RC_READ_RESP_ONLY_OP: /*0x10 /BTH/AETH/payload/ */\r
- if((pkt_st_p->aeth_st_p = ALLOCATE(IB_AETH_st,1)) == NULL){ /* Allocting size in bytes*/\r
- MTL_ERROR('1', "\nfailed to allocate pkt_st_p->aeth_st");\r
- return(MT_EKMALLOC);\r
- };\r
- extract_AETH((pkt_st_p->aeth_st_p),packet_p);\r
- (pkt_st_p->payload_size) -= AETH_LEN;\r
- (pkt_st_p->payload_buf) = *packet_p;\r
- break;\r
-\r
- case RC_ACKNOWLEDGE_OP:\r
- \r
- if ((pkt_st_p->aeth_st_p = ALLOCATE(IB_AETH_st,1)) == NULL)\r
- { /* Allocting size in bytes*/\r
- MTL_ERROR('1', "\nfailed to allocate pkt_st_p->aeth_st");\r
- return(MT_EKMALLOC);\r
- };\r
- extract_AETH((pkt_st_p->aeth_st_p),packet_p);\r
- pkt_st_p->payload_size -= AETH_LEN;\r
- (pkt_st_p->payload_buf) = *packet_p; \r
- MTL_TRACE('5', "\n this is a ack packet PSN is 0x%X MSN is 0x%X\n",pkt_st_p->bth_st_p->PSN,pkt_st_p->aeth_st_p->MSN);\r
- break;\r
-\r
- /****************************************************/\r
- /* unreliable data Gram UD */\r
- /****************************************************/\r
- case UD_SEND_ONLY_OP: /*0x64 /BTH/DETH/payload/ */\r
- if((pkt_st_p->deth_st_p = ALLOCATE(IB_DETH_st,1)) == NULL){ /* Allocting size in bytes*/\r
- MTL_ERROR('1', "\nfailed to allocate pkt_st_p->deth_st");\r
- return(MT_EKMALLOC);\r
- }\r
- extract_DETH((pkt_st_p->deth_st_p),packet_p);\r
- (pkt_st_p->payload_size) -= DETH_LEN;\r
- (pkt_st_p->payload_buf) = *packet_p;\r
- break;\r
-\r
- /****************************************************/\r
- /* unreliable connection UC */\r
- /*****************************************************/\r
-\r
-\r
- default:\r
- MTL_ERROR('1', "\n The Function does not support this kind of a packet\n");\r
- return(MT_ERROR);\r
- break;\r
- }\r
-\r
- return(MT_OK);\r
-}\r
-\r
-#ifdef MT_KERNEL\r
-#ifdef __WIN__\r
-int MPGA_init_module(void)\r
-#else\r
-int init_module(void)\r
-#endif\r
-{\r
- MTL_TRACE('1', "MPGA: loading module\n");\r
- return(0);\r
-}\r
-\r
-#ifdef __WIN__\r
-void MPGA_cleanup_module(void)\r
-#else\r
-void cleanup_module(void)\r
-#endif\r
-{\r
- MTL_TRACE('1', "MPGA: removing module\n");\r
- return;\r
-}\r
-\r
-#endif /* MT_KERNEL */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#ifndef H_PACKET_GEN_H\r
-#define H_PACKET_GEN_H\r
-\r
-/* Layers Includes */ \r
-#include <mtl_types.h>\r
-\r
-/* MPGA Includes */\r
-#include <ib_opcodes.h>\r
-#include <packet_append.h>\r
-#include <packet_utilities.h> \r
- \r
-/******************************************************************************\r
- * Function: MPGA_build_pkt_lrh (build pakcet with lrh field)\r
- *\r
- * Description: This function is appending LRH to IB packets .\r
- * To use this function you must have a LRH struct,\r
- * with all the detailes to create the wanted packet.\r
- * The function should generate an IB packet .\r
- *\r
- *\r
- * Parameters:\r
- * lrh_st_p(*in) IB_LRH_st *\r
- * Local route header of the generated packet.\r
- * t_packet_size(in) u_int16_t\r
- * The transport packet size in bytes.\r
- * t_packet_buf_p(in) u_int16_t *\r
- * A pointer to the transport packet buffer that the lrh will be appended on.\r
- * packet_size_p(out) u_int16_t *\r
- * A pointer to the size in bytes include the VCRC of the packet (will be calc by the func).\r
- * sould be allocted be the user .\r
- * packet_buf_p(out) void **\r
- * A pointer to the full packet .\r
- * The function will allocate this buf and apdate the pointer.\r
- * LNH(in) LNH_T\r
- * Link Next Header Definition.\r
- * * The LNH given will be placed on in the lrh_st_p->LNH field.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR if no packet was generated.\r
- *****************************************************************************/\r
-call_result_t\r
-MPGA_build_pkt_lrh(IB_LRH_st *lrh_st_p, u_int16_t t_packet_size, void *t_packet_buf_p,\r
- u_int16_t *packet_size_p, void **packet_buf_p, LNH_t LNH);\r
-\r
-/******************************************************************************\r
-* Function: reliable_send (First , Middle or Last)\r
-*\r
-* Description: This function generats IB packets for the transport layer only.\r
-* it appends the BTH field to the given payload ,\r
-* The function will make the malloc for the packet buffer.\r
-* and will update both packet_size_p and packet_buf_p\r
-*\r
-*\r
-* Parameters:\r
-* bth_st_p(in) IB_BTH_st *\r
-* Base transport header (no need for opcode field).\r
-* payload_size(in) u_int16_t\r
-* The size of the packet payload.\r
-* payload_buf_p(in) void *\r
-* A pointer to the payload buffer.\r
-* packet_size_p(out) u_int16_t *\r
-* A pointer to the size of the packet .\r
-* packet_buf_p(out) void **\r
-* A pointer to the packet pointer (will be allocated by the function).\r
-* packet_place(in) IB_packet_place\r
-* Indicate if it is a first middle or last packet send .\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR if no packet was generated.\r
-*\r
-*****************************************************************************/\r
-call_result_t\r
-MPGA_reliable_send(IB_BTH_st *bth_st_p, u_int16_t payload_size, void *payload_buf_p,\r
- u_int16_t *packet_size_p, void **packet_buf_p, IB_pkt_place packet_place);\r
-\r
-/******************************************************************************\r
-* Function: reliable_send_only (Send Only)\r
-*\r
-* Description: This function generats IB packets (reliable send only)\r
-* for the transport layer only.\r
-* it appends the BTH field to the given payload ,\r
-* The function will make the malloc for the packet buffer.\r
-* and will update both packet_size_p and packet_buf_p\r
-*\r
-*\r
-* Parameters:\r
-* bth_st_p(in) IB_BTH_st *\r
-* Base transport header (no need for opcode field).\r
-* payload_size(in) u_int16_t\r
-* The size of the packet payload.\r
-* payload_buf_p(in) void *\r
-* A pointer to the payload buffer.\r
-* packet_size_p(out) u_int16_t *\r
-* A pointer to the size of the packet .\r
-* packet_buf_p(out) void **\r
-* A pointer to the packet pointer(will be allocated by the function).\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR if no packet was generated.\r
-*\r
-*****************************************************************************/\r
-call_result_t\r
-MPGA_rc_send_only(IB_BTH_st *bth_st_p, u_int16_t payload_size,\r
- void *payload_buf_p, u_int16_t *packet_size_p, void **packet_buf_p);\r
-\r
-/******************************************************************************\r
-* Function: reliable_rdma_w_only\r
-*\r
-* Description: This function generats IB packets (reliable rdma write only)\r
-* for the transport layer only.\r
-* it appends the BTH and RETH field to the given payload ,\r
-* The function will make the malloc for the packet buffer.\r
-* and will update both packet_size_p and packet_buf_p\r
-*\r
-*\r
-* Parameters:\r
-* bth_st_p(in) IB_BTH_st *\r
-* Base transport header (no need for opcode field).\r
-* reth_st_p(in) IB_RETH_st *\r
-* RDMA Extended trasport header .\r
-* payload_size(in) u_int16_t\r
-* The size of the packet payload.\r
-* payload_buf_p(in) void *\r
-* A pointer to the payload buffer.\r
-* packet_size_p(out) u_int16_t *\r
-* A pointer to the size of the packet .\r
-* packet_buf_p(out) void **\r
-* A pointer to the packet pointer(will be allocated by the function).\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR if no packet was generated.\r
-*\r
-*****************************************************************************/\r
-call_result_t\r
-MPGA_rc_rdma_w_only(IB_BTH_st *bth_st_p, IB_RETH_st *reth_st_p,\r
- u_int16_t payload_size, void *payload_buf_p,\r
- u_int16_t *packet_size_p, void **packet_buf_p); \r
-\r
-/******************************************************************************\r
-* Function: reliable_rdma_w_first\r
-*\r
-* Description: This function generats IB packets (reliable rdma write first)\r
-* for the transport layer only.\r
-* it appends the BTH and RETH field to the given payload ,\r
-* The function will make the malloc for the packet buffer.\r
-* and will update both packet_size_p and packet_buf_p\r
-*\r
-*\r
-* Parameters:\r
-* bth_st_p(in) IB_BTH_st *\r
-* Base transport header (no need for opcode field).\r
-* reth_st_p(in) IB_RETH_st *\r
-* RDMA Extended trasport header .\r
-* payload_size(in) u_int16_t\r
-* The size of the packet payload.\r
-* payload_buf_p(in) void *\r
-* A pointer to the payload buffer.\r
-* packet_size_p(out) u_int16_t *\r
-* A pointer to the size of the packet .\r
-* packet_buf_p(out) void **\r
-* A pointer to the packet pointer(will be allocated by the function).\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR if no packet was generated.\r
-*\r
-*****************************************************************************/\r
-call_result_t\r
-MPGA_rc_rdma_w_first(IB_BTH_st *bth_st_p, IB_RETH_st *reth_st_p,\r
- u_int16_t payload_size, void *payload_buf_p,\r
- u_int16_t *packet_size_p, void **packet_buf_p); \r
-\r
-/******************************************************************************\r
-* Function: reliable_rdma_w_middle\r
-*\r
-* Description: This function generats IB packets (reliable rdma write middle)\r
-* for the transport layer only.\r
-* it appends the given payload to the BTH.\r
-* The function will make the malloc for the packet buffer.\r
-* and will update both packet_size_p and packet_buf_p\r
-*\r
-*\r
-* Parameters:\r
-* bth_st_p(in) IB_BTH_st *\r
-* Base transport header (no need for opcode field).\r
-* payload_size(in) u_int16_t\r
-* The size of the packet payload.\r
-* payload_buf_p(in) void *\r
-* A pointer to the payload buffer.\r
-* packet_size_p(out) u_int16_t *\r
-* A pointer to the size of the packet .\r
-* packet_buf_p(out) void **\r
-* A pointer to the packet pointer(will be allocated by the function).\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR if no packet was generated.\r
-*\r
-*****************************************************************************/\r
-call_result_t\r
-MPGA_rc_rdma_w_middle(IB_BTH_st *bth_st_p, u_int16_t payload_size, \r
- void *payload_buf_p, u_int16_t *packet_size_p,\r
- void **packet_buf_p); \r
-\r
-/******************************************************************************\r
-* Function: reliable_rdma_w_last\r
-*\r
-* Description: This function generats IB packets (reliable rdma write last)\r
-* for the transport layer only.\r
-* it appends the given payload to the BTH.\r
-* The function will make the malloc for the packet buffer.\r
-* and will update both packet_size_p and packet_buf_p\r
-*\r
-*\r
-* Parameters:\r
-* bth_st_p(in) IB_BTH_st *\r
-* Base transport header (no need for opcode field).\r
-* payload_size(in) u_int16_t\r
-* The size of the packet payload.\r
-* payload_buf_p(in) void *\r
-* A pointer to the payload buffer.\r
-* packet_size_p(out) u_int16_t *\r
-* A pointer to the size of the packet .\r
-* packet_buf_p(out) void **\r
-* A pointer to the packet pointer(will be allocated by the function).\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR if no packet was generated.\r
-*\r
-*****************************************************************************/\r
-call_result_t\r
-MPGA_rc_rdma_w_last(IB_BTH_st *bth_st_p, u_int16_t payload_size, \r
- void *payload_buf_p, u_int16_t *packet_size_p,\r
- void **packet_buf_p); \r
-\r
-/******************************************************************************\r
-* Function: reliable_rdma_read_request\r
-*\r
-* Description: This function generats IB packets (reliable rdma read request)\r
-* for the transport layer only.\r
-* it appends the BTH and RETH field to the given payload ,\r
-*\r
-*\r
-* Parameters:\r
-* bth_st_p(in) IB_BTH_st *\r
-* Base transport header (no need for opcode field).\r
-* reth_st_p(in) IB_RETH_st *\r
-* RDMA Extended trasport header .\r
-* packet_size_p(out) u_int16_t *\r
-* A pointer to the size of the packet .\r
-* packet_buf_p(out) void **\r
-* A pointer to the packet pointer(will be allocated by the function).\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR.\r
-*\r
-*****************************************************************************/\r
-call_result_t\r
-MPGA_rc_rdma_r_req(IB_BTH_st *bth_st_p, IB_RETH_st *reth_st_p,\r
- u_int16_t *packet_size_p, void **packet_buf_p);\r
-\r
-/******************************************************************************\r
- * Function: reliable_rdma_read_response (First Middle or Last)\r
- *\r
- * Description: This function generats IB packets (reliable rdma read response First Middle or Last)\r
- * for the transport layer only.\r
- * it appends the BTH and AETH (if needed) field to the given payload ,\r
- * The function will allocate the packet buffer.\r
- * and will update both packet_size_p and packet_buf_p\r
- *\r
- *\r
- * Parameters:\r
- * bth_st_p(in) IB_BTH_st *\r
- * Base transport header (no need for opcode field).\r
- * aeth_st_p(in) IB_AETH_st *\r
- * ACK Extended Transport Header\r
- * payload_size(in) u_int16_t\r
- * The size of the packet payload.\r
- * payload_buf_p(in) void *\r
- * A pointer to the payload buffer.\r
- * packet_size_p(out) u_int16_t *\r
- * A pointer to the size of the packet .\r
- * packet_buf_p(out) void **\r
- * A pointer to the packet pointer(will be allocated by the function).\r
- * packet_place(IN) IB_pkt_place (enum).\r
- * FISRT_PACKET MIDDLE_PACKET LAST_PACKET (0,1,2).\r
- * \r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR if no packet was generated.\r
- *\r
- ******************************************************************************/ \r
-call_result_t\r
-MPGA_rc_rdma_r_resp(IB_BTH_st *bth_st_p, IB_AETH_st *aeth_st_p,\r
- u_int16_t payload_size, void *payload_buf_vp, u_int16_t *packet_size_p,\r
- void **packet_buf_vp, IB_pkt_place packet_place);\r
-\r
-/******************************************************************************\r
-* Function: reliable_rdma_read_response_only\r
-*\r
-* Description: This function generats IB packets (reliable rdma read response only)\r
-* for the transport layer only.\r
-* it appends the BTH and AETH field to the given payload ,\r
-* The function will make the malloc for the packet buffer.\r
-* and will update both packet_size_p and packet_buf_p\r
-*\r
-*\r
-* Parameters:\r
-* bth_st_p(in) IB_BTH_st *\r
-* Base transport header (no need for opcode field).\r
-* aeth_st_p(in) IB_AETH_st *\r
-* ACK Extended Transport Header\r
-* payload_size(in) u_int16_t\r
-* The size of the packet payload.\r
-* payload_buf_p(in) void *\r
-* A pointer to the payload buffer.\r
-* packet_size_p(out) u_int16_t *\r
-* A pointer to the size of the packet .\r
-* packet_buf_p(out) void **\r
-* A pointer to the packet pointer(will be allocated by the function).\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR if no packet was generated.\r
-*\r
-*****************************************************************************/\r
-call_result_t\r
-MPGA_rc_rdma_r_resp_only(IB_BTH_st *bth_st_p, IB_AETH_st *aeth_st_p,\r
- u_int16_t payload_size, void *payload_buf_p,\r
- u_int16_t *packet_size_p, void **packet_buf_p); \r
-\r
-/******************************************************************************\r
-* From this part the declaration of unreliable send IB packts functions\r
-******************************************************************************/\r
-\r
-/******************************************************************************\r
-* Function: unreliable_datagram_send_only (Send Only)\r
-*\r
-* Description: This function generats IB packets (unreliable datagram send only)\r
-* for the transport layer only.\r
-* it appends the BTH and DETH field to the given payload ,\r
-* The function will make the malloc for the packet buffer.\r
-* and will update both packet_size_p and packet_buf_p\r
-*\r
-* Parameters:\r
-* bth_st_p(in) IB_BTH_st *\r
-* Base transport header (no need for opcode field).\r
-* deth_st_p(in) IB_DETH_st *\r
-* Datagram Extended Transport Header\r
-* payload_size(in) u_int16_t\r
-* The size of the packet payload.\r
-* payload_buf_p(in) void *\r
-* A pointer to the payload buffer.\r
-* packet_size_p(out) u_int16_t *\r
-* A pointer to the size of the packet .\r
-* packet_buf_p(out) void **\r
-* A pointer to the packet pointer(will be allocated by the function).\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR if no packet was generated.\r
-*****************************************************************************/\r
-call_result_t\r
-MPGA_ud_send_only(IB_BTH_st *bth_st_p, IB_DETH_st *deth_st_p,\r
- u_int16_t payload_size, void *payload_buf_p,\r
- u_int16_t *packet_size_p, void **packet_buf_p); \r
-\r
-\r
-/************************************************************************/\r
-/* Bulding headers only */\r
-/************************************************************************/\r
-/******************************************************************************\r
-* Function: unreliable_datagram_send_only (Send Only)\r
-*\r
-* Description: This function generats IB packets (unreliable datagram send only)\r
-* for the transport layer and link layer.\r
-* it will create the LRH BTH and DETH field to the given payload ,\r
-* The function will make the malloc for the header.\r
-* and will update both packet_size_p and header_buf_p\r
-*\r
-* Parameters:\r
-* lrh_st_p(in) IB_LRH_st *\r
-* Local route header of the generated header.\r
-* bth_st_p(in) IB_BTH_st *\r
-* Base transport header (no need for opcode field).\r
-* deth_st_p(in) IB_DETH_st *\r
-* Datagram Extended Transport Header\r
-* payload_size(in) u_int16_t\r
-* The size of the packet payload.\r
-* header_size_p(out) u_int16_t *\r
-* A pointer to the size of the generated packet .\r
-* header_buf_p(out) void **\r
-* A pointer to the header pointer(will be allocated by the function).\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR if no packet was send.\r
-* MT_ENOSYS\r
-*****************************************************************************/\r
-call_result_t\r
-MPGA_fast_ud_send_only(IB_LRH_st *lrh_st_p, IB_BTH_st *bth_st_p,\r
- IB_DETH_st *deth_st_p, u_int16_t payload_size,\r
- u_int16_t *header_size_p, void **header_buf_p); \r
-\r
-\r
-/******************************************************************************\r
-* Function: unreliable_datagram_send_only (Send Only with grh)\r
-*\r
-* Description: This function generats IB packets (unreliable datagram send only)\r
-* for the transport layer and link layer.\r
-* it will create the LRH BTH and DETH field to the given payload ,\r
-* The function will make the malloc for the header.\r
-* and will update both packet_size_p and header_buf_p\r
-*\r
-* Parameters:\r
-* lrh_st_p(in) IB_LRH_st *\r
-* Local route header of the generated header.\r
-* grh_st_p(in) IB_GRH_st *\r
-* Global route header of the generated header.\r
-* bth_st_p(in) IB_BTH_st *\r
-* Base transport header (no need for opcode field).\r
-* deth_st_p(in) IB_DETH_st *\r
-* Datagram Extended Transport Header\r
-* payload_size(in) u_int16_t\r
-* The size of the packet payload.\r
-* header_size_p(out) u_int16_t *\r
-* A pointer to the size of the generated packet .\r
-* header_buf_p(out) void **\r
-* A pointer to the header pointer(will be allocated by the function).\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR if no packet was send.\r
-* MT_ENOSYS\r
-*****************************************************************************/\r
-call_result_t\r
-MPGA_fast_ud_send_grh(IB_LRH_st *lrh_st_p, IB_GRH_st *grh_st_p, \r
- IB_BTH_st *bth_st_p, IB_DETH_st *deth_st_p, \r
- u_int16_t payload_size, u_int16_t *header_size_p, \r
- void **header_buf_p);\r
-\r
-/******************************************************************************\r
-* Function: reliable_send (First)\r
-*\r
-* Description: This function generats IB packets header for the transport and link layers.\r
-* it appends the LRH BTH field to the given header ,\r
-* The function will make the malloc for the packet buffer.\r
-* and will update both header_size_p and header_buf_p\r
-*\r
-*\r
-* Parameters:\r
-* lrh_st_p(out) IB_LRH_st *\r
-* local route header.\r
-* grh_st_p(out) IB_GRH_st *\r
-* global route header. (not supported yet). \r
-* bth_st_p(out) IB_BTH_st *\r
-* Base transport header (no need for opcode field).\r
-* payload_size(in) u_int16_t\r
-* The size of the packet payload.\r
-* header_buf_p(in) void *\r
-* A pointer to the payload buffer.\r
-* header_size_p(out) u_int16_t *\r
-* A pointer to the size of the packet .\r
-* header_buf_p(out) void **\r
-* A pointer to the packet pointer (will be allocated by the function).\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR if no packet was generated.\r
-* MT_ENOSYS\r
-*\r
-*****************************************************************************/\r
-call_result_t \r
-MPGA_fast_rc_send_first(IB_LRH_st *lrh_st_p, IB_GRH_st *grh_st_p,\r
- IB_BTH_st *bth_st_p, LNH_t LNH, u_int16_t payload_size, \r
- u_int16_t *header_size_p, void **header_buf_p);\r
-\r
-/******************************************************************************\r
-* Function: reliable_send (middle)\r
-*\r
-* Description: This function generats IB packets header for the transport and link layers.\r
-* it appends the LRH BTH field to the given header ,\r
-* The function will make the malloc for the packet buffer.\r
-* and will update both header_size_p and header_buf_p\r
-*\r
-*\r
-* Parameters:\r
-* lrh_st_p(out) IB_LRH_st *\r
-* local route header.\r
-* grh_st_p(out) IB_GRH_st *\r
-* global route header. (not supported yet). \r
-* bth_st_p(out) IB_BTH_st *\r
-* Base transport header (no need for opcode field).\r
-* payload_size(in) u_int16_t\r
-* The size of the packet payload.\r
-* header_buf_p(in) void *\r
-* A pointer to the payload buffer.\r
-* header_size_p(out) u_int16_t *\r
-* A pointer to the size of the packet .\r
-* header_buf_p(out) void **\r
-* A pointer to the packet pointer (will be allocated by the function).\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR if no packet was generated.\r
-* MT_ENOSYS\r
-*\r
-*****************************************************************************/\r
-call_result_t \r
-MPGA_fast_rc_send_middle(IB_LRH_st *lrh_st_p, IB_GRH_st *grh_st_p,\r
- IB_BTH_st *bth_st_p, LNH_t LNH, u_int16_t payload_size, \r
- u_int16_t *header_size_p, void **header_buf_p);\r
-\r
-/******************************************************************************\r
-* Function: reliable_send (last)\r
-*\r
-* Description: This function generats IB packets header for the transport and link layers.\r
-* it appends the LRH BTH field to the given header ,\r
-* The function will make the malloc for the packet buffer.\r
-* and will update both header_size_p and header_buf_p\r
-*\r
-*\r
-* Parameters:\r
-* lrh_st_p(out) IB_LRH_st *\r
-* local route header.\r
-* grh_st_p(out) IB_GRH_st *\r
-* global route header. (not supported yet). \r
-* bth_st_p(out) IB_BTH_st *\r
-* Base transport header (no need for opcode field).\r
-* payload_size(in) u_int16_t\r
-* The size of the packet payload.\r
-* header_buf_p(in) void *\r
-* A pointer to the payload buffer.\r
-* header_size_p(out) u_int16_t *\r
-* A pointer to the size of the packet .\r
-* header_buf_p(out) void **\r
-* A pointer to the packet pointer (will be allocated by the function).\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR if no packet was generated.\r
-* MT_ENOSYS\r
-*\r
-*****************************************************************************/\r
-call_result_t \r
-MPGA_fast_rc_send_last(IB_LRH_st *lrh_st_p, IB_GRH_st *grh_st_p,\r
- IB_BTH_st *bth_st_p, LNH_t LNH, u_int16_t payload_size, \r
- u_int16_t *header_size_p, void **header_buf_p);\r
-\r
-\r
-/******************************************************************************\r
-* Function: reliable_send (only)\r
-*\r
-* Description: This function generats IB packets header for the transport and link layers.\r
-* it appends the LRH BTH field to the given header ,\r
-* The function will make the malloc for the packet buffer.\r
-* and will update both header_size_p and header_buf_p\r
-*\r
-*\r
-* Parameters:\r
-* lrh_st_p(out) IB_LRH_st *\r
-* local route header.\r
-* grh_st_p(out) IB_GRH_st *\r
-* global route header. (not supported yet). \r
-* bth_st_p(out) IB_BTH_st *\r
-* Base transport header (no need for opcode field).\r
-* payload_size(in) u_int16_t\r
-* The size of the packet payload.\r
-* header_buf_p(in) void *\r
-* A pointer to the payload buffer.\r
-* header_size_p(out) u_int16_t *\r
-* A pointer to the size of the packet .\r
-* header_buf_p(out) void **\r
-* A pointer to the packet pointer (will be allocated by the function).\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR if no packet was generated.\r
-* MT_ENOSYS\r
-*\r
-*****************************************************************************/\r
-call_result_t \r
-MPGA_fast_rc_send_only(IB_LRH_st *lrh_st_p, IB_GRH_st *grh_st_p,\r
- IB_BTH_st *bth_st_p, LNH_t LNH, u_int16_t payload_size, \r
- u_int16_t *header_size_p, void **header_buf_p);\r
-\r
-/******************************************************************************\r
-* Function: reliable_c RDMA READ RESPONSE (First)\r
-*\r
-* Description: This function generats IB packets header for the transport and link layers.\r
-* it appends the LRH BTH AETH field to the given header ,\r
-* The function will make the malloc for the packet buffer.\r
-* and will update both header_size_p and header_buf_p\r
-*\r
-*\r
-* Parameters:\r
-* lrh_st_p(out) IB_LRH_st *\r
-* local route header.\r
-* grh_st_p(out) IB_GRH_st *\r
-* global route header. (not supported yet). \r
-* aeth_st_p(out) IB_AETH_st *\r
-* Ack extended transport header.\r
-* bth_st_p(out) IB_BTH_st *\r
-* Base transport header (no need for opcode field).\r
-* payload_size(in) u_int16_t\r
-* The size of the packet payload.\r
-* header_buf_p(in) void *\r
-* A pointer to the payload buffer.\r
-* header_size_p(out) u_int16_t *\r
-* A pointer to the size of the packet .\r
-* header_buf_p(out) void **\r
-* A pointer to the packet pointer (will be allocated by the function).\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR if no packet was generated.\r
-* MT_ENOSY not supported. \r
-*\r
-*****************************************************************************/\r
-call_result_t \r
-MPGA_fast_rc_read_resp_first(IB_LRH_st *lrh_st_p, IB_GRH_st *grh_st_p,\r
- IB_BTH_st *bth_st_p, IB_AETH_st *aeth_st_p, LNH_t LNH, \r
- u_int16_t payload_size, u_int16_t *header_size_p, \r
- void **header_buf_p);\r
-\r
-/******************************************************************************\r
-* Function: reliable_c RDMA READ RESPONSE (middle)\r
-*\r
-* Description: This function generats IB packets header for the transport and link layers.\r
-* it appends the LRH BTH AETH field to the given header ,\r
-* The function will make the malloc for the packet buffer.\r
-* and will update both header_size_p and header_buf_p\r
-*\r
-*\r
-* Parameters:\r
-* lrh_st_p(out) IB_LRH_st *\r
-* local route header.\r
-* grh_st_p(out) IB_GRH_st *\r
-* global route header. (not supported yet). \r
-* bth_st_p(out) IB_BTH_st *\r
-* Base transport header (no need for opcode field).\r
-* payload_size(in) u_int16_t\r
-* The size of the packet payload.\r
-* header_buf_p(in) void *\r
-* A pointer to the payload buffer.\r
-* header_size_p(out) u_int16_t *\r
-* A pointer to the size of the packet .\r
-* header_buf_p(out) void **\r
-* A pointer to the packet pointer (will be allocated by the function).\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR if no packet was generated.\r
-* MT_ENOSY not supported. \r
-*\r
-*****************************************************************************/\r
-call_result_t \r
-MPGA_fast_rc_read_resp_middle(IB_LRH_st *lrh_st_p, IB_GRH_st *grh_st_p,\r
- IB_BTH_st *bth_st_p, LNH_t LNH, u_int16_t payload_size, \r
- u_int16_t *header_size_p, void **header_buf_p);\r
-\r
-/******************************************************************************\r
-* Function: reliable_c RDMA READ RESPONSE (last)\r
-*\r
-* Description: This function generats IB packets header for the transport and link layers.\r
-* it appends the LRH BTH AETH field to the given header ,\r
-* The function will make the malloc for the packet buffer.\r
-* and will update both header_size_p and header_buf_p\r
-*\r
-*\r
-* Parameters:\r
-* lrh_st_p(out) IB_LRH_st *\r
-* local route header.\r
-* grh_st_p(out) IB_GRH_st *\r
-* global route header. (not supported yet). \r
-* aeth_st_p(out) IB_AETH_st *\r
-* Ack extended transport header.\r
-* bth_st_p(out) IB_BTH_st *\r
-* Base transport header (no need for opcode field).\r
-* payload_size(in) u_int16_t\r
-* The size of the packet payload.\r
-* header_buf_p(in) void *\r
-* A pointer to the payload buffer.\r
-* header_size_p(out) u_int16_t *\r
-* A pointer to the size of the packet .\r
-* header_buf_p(out) void **\r
-* A pointer to the packet pointer (will be allocated by the function).\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR if no packet was generated.\r
-* MT_ENOSY not supported. \r
-*\r
-*****************************************************************************/\r
-call_result_t \r
-MPGA_fast_rc_read_resp_last(IB_LRH_st *lrh_st_p, IB_GRH_st *grh_st_p,\r
- IB_BTH_st *bth_st_p, IB_AETH_st *aeth_st_p, LNH_t LNH, \r
- u_int16_t payload_size, u_int16_t *header_size_p, \r
- void **header_buf_p);\r
-\r
-/******************************************************************************\r
-* Function: reliable_c RDMA READ RESPONSE (only)\r
-*\r
-* Description: This function generats IB packets header for the transport and link layers.\r
-* it appends the LRH BTH AETH field to the given header ,\r
-* The function will make the malloc for the packet buffer.\r
-* and will update both header_size_p and header_buf_p\r
-*\r
-*\r
-* Parameters:\r
-* lrh_st_p(out) IB_LRH_st *\r
-* local route header.\r
-* grh_st_p(out) IB_GRH_st *\r
-* global route header. (not supported yet). \r
-* aeth_st_p(out) IB_AETH_st *\r
-* Ack extended transport header.\r
-* bth_st_p(out) IB_BTH_st *\r
-* Base transport header (no need for opcode field).\r
-* payload_size(in) u_int16_t\r
-* The size of the packet payload.\r
-* header_buf_p(in) void *\r
-* A pointer to the payload buffer.\r
-* header_size_p(out) u_int16_t *\r
-* A pointer to the size of the packet .\r
-* header_buf_p(out) void **\r
-* A pointer to the packet pointer (will be allocated by the function).\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR if no packet was generated.\r
-* MT_ENOSY not supported. \r
-*\r
-*****************************************************************************/\r
-call_result_t \r
-MPGA_fast_rc_read_resp_only(IB_LRH_st *lrh_st_p, IB_GRH_st *grh_st_p,\r
- IB_BTH_st *bth_st_p, IB_AETH_st *aeth_st_p, LNH_t LNH, \r
- u_int16_t payload_size, u_int16_t *header_size_p, \r
- void **header_buf_p);\r
-\r
-\r
-\r
-\r
-call_result_t \r
-MPGA_fast_rc_acknowledge(IB_LRH_st *lrh_st_p, IB_GRH_st *grh_st_p,\r
- IB_BTH_st *bth_st_p, IB_AETH_st *aeth_st_p, LNH_t LNH,\r
- u_int16_t *header_size_p, void **header_buf_p);\r
-\r
-\r
-\r
-\r
-\r
-\r
-/*****************************************************************************/\r
-/* Analyzer functions */\r
-/*****************************************************************************/\r
-\r
-/******************************************************************************\r
-* Function: analyze_packet\r
-*\r
-* Description: This function Analyze IB packets .\r
-* and updates the needed structures acording to its content.\r
-*\r
-* Parameters:\r
-* pkt_st_p(out) IB_Pkt_st *\r
-* A pointer to a packet structure that will be update by the function.\r
-* packet_buf_p(in) void *\r
-* A pointer to the start of the packet that have LRH field .\r
-*\r
-* NOTE : the function will allocate mem for the inside buffers\r
-* and it is the user responsibility for free it.\r
-*\r
-* Returns:\r
-* call_result_t\r
-* MT_OK,\r
-* MT_ERROR\r
-*\r
-*****************************************************************************/\r
-call_result_t\r
-MPGA_analyze_packet(IB_PKT_st *pkt_st_p, void *packet_buf_p);\r
- \r
-/******************************************************************************\r
- * Function: Packet_generator\r
- *\r
- * Description: This function generats IB packets .\r
- * To use this function you must have a general packet struct,\r
- * with all the detailes to create the wanted packet.\r
- * The function will make the malloc for the packet buffer.\r
- * and will update both packet_size_p and packet_buf_p\r
- *\r
- * Parameters:\r
- * struct(in) packet_fields\r
- * A general packet struct.\r
- * payload_size(in) int32_t\r
- * The size of the packet payload.\r
- * payload_buf_p(in) void\r
- * A pointer to the payload buffer.\r
- * packet_size_p(out) int32_t *\r
- A pointer to the size of the packet .\r
- * packet_buf_p(out) void\r
- * A pointer to the full packet .\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR if no packet was generated.\r
- *****************************************************************************/\r
-/*call_result_t packet_generator ("struct packet_fields", int32_t payload_size,\r
- u_int8_t *payload_buf_p, int32_t *packet_size_p,\r
- u_int8_t *packet_buf_p);*/\r
- \r
- \r
-#endif /* H_PACKET_GEN_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-/************************************/\r
-#ifndef MT_KERNEL\r
-\r
- #include <stdio.h>\r
- #include <stdlib.h>\r
-\r
-#endif /* MT_KERNEL */ \r
-\r
-#include <time.h>\r
-\r
-#include <mpga_sv.h>\r
-#include <ib_opcodes.h>\r
-#include <packet_append.h>\r
-#include <internal_functions.h>\r
-\r
-/* Layers Includes */ \r
-#include <bit_ops.h>\r
-\r
-/************************************/\r
-\r
-\r
-/*********************************************************************************/\r
-/* build packet with lrh */\r
-/*********************************************************************************/\r
-call_result_t\r
-MPGA_build_pkt_lrh_sv (IB_LRH_st *lrh_st_p, u_int16_t t_packet_size, void *t_packet_buf_vp,\r
- u_int16_t *packet_size_p, void **packet_buf_vp,LNH_t LNH, struct MPGA_error_st error_st)\r
-{\r
- u_int8_t *start_LRH_p;\r
- u_int16_t TCRC_packet_size = 0;/*This arg will be send to the allocate function*/\r
- u_int32_t ICRC = 0, tmpICRC = 0; /*for making space for the crc fileds*/\r
- u_int16_t VCRC = 0, tmpVCRC = 0;\r
- u_int8_t *start_ICRC_p;\r
- u_int8_t *start_VCRC_p;\r
- u_int16_t **packet_buf_p;\r
- u_int16_t *t_packet_buf_p;\r
- u_int8_t align = 0;\r
-\r
-\r
- packet_buf_p = (u_int16_t**)packet_buf_vp; /*casting to u_int16_t */\r
- t_packet_buf_p = (u_int16_t*)t_packet_buf_vp;\r
-\r
- if(LNH == IBA_LOCAL) TCRC_packet_size = t_packet_size + ICRC_LEN + VCRC_LEN;\r
- else{\r
- if(LNH == RAW) align = (4 - (t_packet_size % IBWORD)) % IBWORD; /*should be a RAW packet at this stage*/\r
- TCRC_packet_size = t_packet_size + VCRC_LEN + align;/*for sending to the allocate functiom*/\r
- }\r
-\r
- (*packet_size_p) = TCRC_packet_size + LRH_LEN; /*CRC fields are included*/\r
-\r
-\r
- if((allocate_packet_LRH(TCRC_packet_size, t_packet_size, t_packet_buf_p,\r
- *packet_size_p, packet_buf_p)) != MT_OK) return(MT_EKMALLOC);\r
- /*packet_bup_p is a p2p*/\r
-\r
-/*Update the fields in the given lrh struct*/\r
- lrh_st_p->LNH = (u_int8_t)LNH;\r
- lrh_st_p->PktLen = (*packet_size_p - VCRC_LEN) / IBWORD;\r
- /*from the firest byte of the LRH till the VCRC in 4 byte word*/\r
- lrh_st_p->reserved1 = 0;\r
- lrh_st_p->reserved2 = 0;\r
-\r
- /*************************** random error **********************/\r
- srand((unsigned int)time((time_t *)NULL)); \r
-\r
- if(error_st.LNH == YES) lrh_st_p->LNH = (LNH + 1) % 4; /* LNH can be 0,1,2,3*/\r
- if(error_st.PktLen_long == YES) lrh_st_p->PktLen += (u_int16_t)((rand() % lrh_st_p->PktLen) + 1);\r
- if(error_st.PktLen_short == YES) lrh_st_p->PktLen -= (u_int16_t)((rand() % (lrh_st_p->PktLen - 1)) + 1); \r
- if(error_st.LVer == YES) lrh_st_p->LVer = rand() % MAX_LVer + 1; /* not zero (1-15)*/\r
- else lrh_st_p->LVer = 0;\r
- if(error_st.VL == YES) lrh_st_p->VL = (rand() % 7) + 8; /* 8 to 14 */\r
- else lrh_st_p->VL = 7;\r
- if(error_st.LNH == YES) lrh_st_p->LNH = ((rand() % 3 + 1) + LNH) % 4;/* every num 0 to 3 but not LNH*/ \r
- if(error_st.lrh_reserved1 == YES) lrh_st_p->reserved1 = (rand() % 4);\r
- if(error_st.lrh_reserved2 == YES) lrh_st_p->reserved2 = (rand() % 4);\r
- /*****************************************************************/\r
-\r
- start_LRH_p = (u_int8_t*)(*packet_buf_p) - LRH_LEN;\r
-\r
- start_LRH_p[0] = INSERTF(start_LRH_p[0],4,lrh_st_p->VL,0,4);\r
- start_LRH_p[0] = INSERTF(start_LRH_p[0],0,lrh_st_p->LVer,0,4);\r
- start_LRH_p[1] = INSERTF(start_LRH_p[1],4,lrh_st_p->SL,0,4);\r
- start_LRH_p[1] = INSERTF(start_LRH_p[1],2,lrh_st_p->reserved1,0,2);\r
- start_LRH_p[1] = INSERTF(start_LRH_p[1],0,lrh_st_p->LNH,0,2);\r
- start_LRH_p[2] = INSERTF(start_LRH_p[2],0,lrh_st_p->DLID,8,8);\r
- start_LRH_p[3] = INSERTF(start_LRH_p[3],0,lrh_st_p->DLID,0,8);\r
- start_LRH_p[4] = INSERTF(start_LRH_p[4],3,lrh_st_p->reserved2,0,5);\r
- start_LRH_p[4] = INSERTF(start_LRH_p[4],0,lrh_st_p->PktLen,8,3);\r
- start_LRH_p[5] = INSERTF(start_LRH_p[5],0,lrh_st_p->PktLen,0,8);\r
- start_LRH_p[6] = INSERTF(start_LRH_p[6],0,lrh_st_p->SLID,8,8);\r
- start_LRH_p[7] = INSERTF(start_LRH_p[7],0,lrh_st_p->SLID,0,8);\r
-\r
- (*packet_buf_p) = (u_int16_t*)start_LRH_p;\r
- /* calc ICRC */\r
- if(LNH == IBA_LOCAL){ /*appending the ICRC */\r
- start_ICRC_p = (u_int8_t*)start_LRH_p + LRH_LEN + t_packet_size;\r
- ICRC = fast_calc_ICRC(*packet_size_p, *packet_buf_p, LNH);\r
- /* rand error*/\r
- if(error_st.ICRC_IN == YES){ \r
- tmpICRC = ((rand()% 0xFFFFFFFE) + 1); /* IRCR will be higer or lower*/\r
- tmpICRC != ICRC ? ICRC = tmpICRC : ICRC++;\r
- }\r
- if(error_st.ICRC_OUT == YES) start_LRH_p[1] += 4; /*reserved will be chaged*/ \r
- append_ICRC((u_int16_t*)start_ICRC_p, ICRC);\r
- }\r
-\r
- /* calc VCRC */\r
- start_VCRC_p = (u_int8_t*)start_LRH_p + LRH_LEN + TCRC_packet_size -VCRC_LEN;\r
- VCRC = fast_calc_VCRC(*packet_size_p, *packet_buf_p); /* appendinf the VCRC*/\r
- /* rand error*/\r
- if(error_st.VCRC_IN == YES){\r
- tmpVCRC += (u_int16_t)((rand()% 0xFFFE) + 1); /* VRCR will be higer or lower*/\r
- tmpVCRC != VCRC ? VCRC = tmpVCRC : VCRC++;\r
- }\r
- if(error_st.VCRC_OUT == YES) start_LRH_p[1] += 4; /*reserved will be changed*/\r
- append_VCRC((u_int16_t*)start_VCRC_p, VCRC);\r
-\r
- return(MT_OK);\r
-}\r
-\r
-/*******************************************************************************/\r
-/* reliable send only */\r
-/*******************************************************************************/\r
-call_result_t\r
-MPGA_rc_send_only_sv(IB_BTH_st *bth_st_p, u_int16_t payload_size, void *payload_buf_vp,\r
- u_int16_t *packet_size_p, void **packet_buf_vp, struct MPGA_error_st error_st)\r
-{\r
- u_int16_t header_size;\r
- u_int16_t packet_size;\r
- u_int16_t *payload_buf_p;\r
- u_int16_t **packet_buf_p;\r
- \r
- packet_buf_p = (u_int16_t**)packet_buf_vp;\r
- payload_buf_p = (u_int16_t*)payload_buf_vp;/*casting the void to u_int16_t* ,data could be 4096B*/\r
- \r
- header_size = RC_SEND_ONLY_LEN; /*init parameters*/\r
- packet_size = header_size + payload_size + ((IBWORD - (payload_size % IBWORD)) % IBWORD);\r
-\r
- /*************************************/\r
- /* random error */\r
- /*************************************/\r
- if(error_st.PktLen_not_align == YES){\r
- packet_size += (rand() % 3) + 1;\r
- error_st.PktLen_long = YES;\r
- }\r
- \r
- /*Updating fields and given arguments*/\r
-(*packet_size_p) = packet_size;\r
- bth_st_p->OpCode = RC_SEND_ONLY_OP; /*opcode is 00000100 */\r
- \r
- if((allocate_packet(payload_size, payload_buf_p, packet_size, packet_buf_p)) != MT_OK)\r
- return(MT_EKMALLOC);\r
- \r
- /*packet_bup_p is a p2p*/\r
- /*printf("\n in before append bth reliable packet_buf_p is %d",(*packet_buf_p));*/\r
- \r
- if((append_BTH (bth_st_p, packet_buf_p, payload_size)) != MT_OK) return(MT_ERROR);\r
- /*appending the bth field */\r
- \r
- return(MT_OK);\r
-} \r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#ifndef _MPGA_SV_H\r
-#define _MPGA_SV_H\r
-\r
-/* Layers Includes */ \r
-#include <mtl_types.h>\r
-\r
-/* MPGA Includes */\r
-#include <ib_opcodes.h>\r
-#include <packet_append.h>\r
-#include <packet_utilities.h> \r
- \r
-/*****************************************************************************/\r
-/* This Struct defines the ERROR generator in the mpga lib */\r
-/*****************************************************************************/\r
-#define MAX_LVer 0xf\r
-\r
-typedef enum{\r
- YES = 0,\r
- NO = 1\r
-} mpga_error_gen;\r
-\r
-typedef struct MPGA_error_st MPGA_error_st; \r
-\r
-struct MPGA_error_st{\r
- mpga_error_gen PktLen_short;\r
- mpga_error_gen PktLen_long;\r
- mpga_error_gen PktLen_not_align; \r
- mpga_error_gen LVer; /* we support only Lver = 0*/\r
- mpga_error_gen VL;\r
- mpga_error_gen VCRC_IN;\r
- mpga_error_gen VCRC_OUT;\r
- mpga_error_gen ICRC_IN;\r
- mpga_error_gen ICRC_OUT;\r
-\r
- \r
- mpga_error_gen LNH; /* only tca will drop*/\r
- mpga_error_gen lrh_reserved1;\r
- mpga_error_gen lrh_reserved2;\r
- mpga_error_gen PadCnt;\r
- mpga_error_gen TVer;\r
- mpga_error_gen bth_reserved1;\r
- mpga_error_gen bth_reserved2;\r
- mpga_error_gen PSN;\r
-\r
- mpga_error_gen BAD_10_bit;\r
-}; \r
- \r
-/******************************************************************************\r
- * Function: MPGA_build_pkt_lrh_sv (build pakcet with lrh field for sv)\r
- *\r
- * Description: This function is appending LRH to IB packets .\r
- * To use this function you must have a LRH struct,\r
- * with all the detailes to create the wanted packet.\r
- * The function should generate an IB packet .\r
- *\r
- *\r
- * Parameters:\r
- * lrh_st_p(*in) IB_LRH_st *\r
- * Local route header of the generated packet.\r
- * t_packet_size(in) u_int16_t\r
- * The transport packet size in bytes.\r
- * t_packet_buf_p(in) u_int16_t *\r
- * A pointer to the transport packet buffer that the lrh will be appended on.\r
- * packet_size_p(out) u_int16_t *\r
- * A pointer to the size of the packet (will be calc by the func).\r
- * sould be allocted be the user .\r
- * packet_buf_p(out) void **\r
- * A pointer to the full packet .\r
- * The function will allocate this buf and apdate the pointer.\r
- * LNH(in) LNH_T\r
- * Link Next Header Definition.\r
- * * The LNH given will be placed on in the lrh_st_p->LNH field.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR if no packet was generated.\r
- *****************************************************************************/\r
-call_result_t\r
-MPGA_build_pkt_lrh_sv(IB_LRH_st *lrh_st_p, u_int16_t t_packet_size, void *t_packet_buf_p,\r
- u_int16_t *packet_size_p, void **packet_buf_p, LNH_t LNH, struct MPGA_error_st error_st);\r
-\r
-/******************************************************************************\r
- * * Function: reliable_send_only_sv (Send Only)\r
- * *\r
- * * Description: This function generats IB packets (reliable send only)\r
- * * for the transport layer only.\r
- * * it appends the BTH field to the given payload ,\r
- * * The function will make the malloc for the packet buffer.\r
- * * and will appdate both packet_size_p and packet_buf_p\r
- * *\r
- * *\r
- * * Parameters:\r
- * * bth_st_p(in) IB_BTH_st *\r
- * * Base transport header (no need for opcode field).\r
- * * payload_size(in) u_int16_t\r
- * * The size of the packet payload.\r
- * * payload_buf_p(in) void *\r
- * * A pointer to the payload buffer.\r
- * * packet_size_p(out) u_int16_t *\r
- * * A pointer to the size of the packet .\r
- * * packet_buf_p(out) void **\r
- * * A pointer to the packet pointer(will be allocated by the function).\r
- * *\r
- * * Returns:\r
- * * call_result_t\r
- * * MT_OK,\r
- * * MT_ERROR if no packet was generated.\r
- * *\r
- * *****************************************************************************/\r
-call_result_t\r
-MPGA_rc_send_only_sv(IB_BTH_st *bth_st_p, u_int16_t payload_size,\r
- void *payload_buf_p, u_int16_t *packet_size_p, \r
- void **packet_buf_p, struct MPGA_error_st error_st); \r
-#endif \r
- /* _MPGA_SV_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "nMPGA.h"\r
-#include "nMPGA_packet_append.h"\r
-#include <mpga.h>\r
-\r
-#undef MT_BIT_OFFSET\r
-#define MT_BIT_OFFSET(struct_ancore,reg_path) \\r
- ((MT_offset_t) &( ((struct struct_ancore *)(0))-> reg_path ))\r
-#undef MT_BIT_SIZE\r
-#define MT_BIT_SIZE(struct_ancore,reg_path) \\r
- ((MT_size_t) sizeof( ((struct struct_ancore *)(0))-> reg_path ))\r
-#undef MT_BIT_OFFSET_SIZE\r
-#define MT_BIT_OFFSET_SIZE(struct_ancore,reg_path) \\r
- MT_BIT_OFFSET(struct_ancore,reg_path) , MT_BIT_SIZE(struct_ancore,reg_path)\r
-\r
-call_result_t \r
-MPGA_get_headers_size(IB_opcode_t opcode, \r
- LNH_t LNH, \r
- u_int16_t payload_len, \r
- MT_bool icrc, /*if set - icrc exist*/ \r
- MT_bool vcrc, /*if set - vcrc exist*/ \r
- u_int16_t *packet_len) /*(OUT) packet length in bytes*/\r
-{\r
- *packet_len=0;\r
- switch (LNH)\r
- {\r
- case RAW: /* |LRH|... (Etertype)*/\r
- MTL_ERROR1("%s: Unsupported LNH (%d)\n", __func__, LNH);\r
- return(MT_ERROR); \r
- case IP_NON_IBA_TRANS: /* |LRH|GRH|... */\r
- MTL_ERROR1("%s: Unsupported LNH (%d)\n", __func__, LNH);\r
- return(MT_ERROR);\r
- case IBA_LOCAL: /* |LRH|BTH|... */\r
- break;\r
- case IBA_GLOBAL: /* |LRH|GRH|BTH|... */\r
- *packet_len = GRH_LEN;\r
- break;\r
- default:\r
- MTL_ERROR1("%s: Invalid LNH (%d)\n", __func__, LNH);\r
- return(MT_ERROR);\r
- break;\r
-\r
- }\r
-\r
- *packet_len += payload_len + ( icrc ? ICRC_LEN : 0 ) + ( vcrc ? VCRC_LEN : 0 );\r
-\r
- switch (opcode)\r
- {\r
-\r
- /***********************************************/\r
- /* reliable Connection (RC) */\r
- /***********************************************/\r
- \r
- case RC_SEND_FIRST_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN;\r
- return(MT_OK);\r
-\r
- case RC_SEND_MIDDLE_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN;\r
- return(MT_OK);\r
-\r
- case RC_SEND_LAST_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN;\r
- return(MT_OK);\r
-\r
- case RC_SEND_LAST_W_IM_OP: \r
- *packet_len+=LRH_LEN+BTH_LEN+ImmDt_LEN;\r
- return(MT_OK);\r
-\r
- case RC_SEND_ONLY_OP: \r
- *packet_len+=LRH_LEN+BTH_LEN;\r
- return(MT_OK);\r
-\r
- case RC_SEND_ONLY_W_IM_OP: \r
- *packet_len+=LRH_LEN+BTH_LEN+ImmDt_LEN;\r
- return(MT_OK);\r
-\r
- case RC_WRITE_FIRST_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RETH_LEN;\r
- return(MT_OK);\r
-\r
- case RC_WRITE_MIDDLE_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN;\r
- return(MT_OK);\r
-\r
- case RC_WRITE_LAST_OP: \r
- *packet_len+=LRH_LEN+BTH_LEN;\r
- return(MT_OK);\r
-\r
- case RC_WRITE_LAST_W_IM_OP: \r
- *packet_len+=LRH_LEN+BTH_LEN+ImmDt_LEN;\r
- return(MT_OK);\r
-\r
- case RC_WRITE_ONLY_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RETH_LEN;\r
- return(MT_OK);\r
-\r
- case RC_WRITE_ONLY_W_IM_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RETH_LEN+ImmDt_LEN;\r
- return(MT_OK);\r
-\r
- case RC_READ_REQ_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RETH_LEN;\r
- return(MT_OK);\r
-\r
- case RC_READ_RESP_FIRST_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+AETH_LEN;\r
- return(MT_OK);\r
-\r
- case RC_READ_RESP_MIDDLE_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN;\r
- return(MT_OK);\r
-\r
- case RC_READ_RESP_LAST_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+AETH_LEN;\r
- return(MT_OK);\r
-\r
- case RC_READ_RESP_ONLY_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+AETH_LEN;\r
- return(MT_OK);\r
-\r
- case RC_ACKNOWLEDGE_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+AETH_LEN;\r
- return(MT_OK);\r
-\r
- case RC_ATOMIC_ACKNOWLEDGE_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+AETH_LEN+AtomAETH_LEN;\r
- return(MT_OK);\r
-\r
- case RC_CMP_SWAP_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+AtomETH_LEN;\r
- return(MT_OK);\r
-\r
- case RC_FETCH_ADD_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+AtomETH_LEN;\r
- return(MT_OK);\r
-\r
-/***********************************************/\r
-/* Unreliable Connection (UC) */\r
-/***********************************************/\r
-\r
- case UC_SEND_FIRST_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN;\r
- return(MT_OK); \r
-\r
- case UC_SEND_MIDDLE_OP: \r
- *packet_len+=LRH_LEN+BTH_LEN;\r
- return(MT_OK);\r
-\r
- case UC_SEND_LAST_OP: \r
- *packet_len+=LRH_LEN+BTH_LEN;\r
- return(MT_OK);\r
-\r
- case UC_SEND_LAST_W_IM_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+ImmDt_LEN;\r
- return(MT_OK); \r
-\r
- case UC_SEND_ONLY_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN;\r
- return(MT_OK); \r
-\r
- case UC_SEND_ONLY_W_IM_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+ImmDt_LEN;\r
- return(MT_OK); \r
-\r
- case UC_WRITE_FIRST_OP: \r
- *packet_len+=LRH_LEN+BTH_LEN+RETH_LEN;\r
- return(MT_OK);\r
-\r
- case UC_WRITE_MIDDLE_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN;\r
- return(MT_OK); \r
-\r
- case UC_WRITE_LAST_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN;\r
- return(MT_OK);\r
-\r
- case UC_WRITE_LAST_W_IM_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+ImmDt_LEN;\r
- return(MT_OK); \r
-\r
- case UC_WRITE_ONLY_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RETH_LEN;\r
- return(MT_OK); \r
-\r
- case UC_WRITE_ONLY_W_IM_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RETH_LEN+ImmDt_LEN;\r
- return(MT_OK);\r
-\r
-/***********************************************/\r
-/* Reliable Datagram (RD) */\r
-/***********************************************/\r
-\r
- case RD_SEND_FIRST_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN;\r
- return(MT_OK);\r
-\r
- case RD_SEND_MIDDLE_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN;\r
- return(MT_OK);\r
-\r
- case RD_SEND_LAST_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN;\r
- return(MT_OK);\r
-\r
- case RD_SEND_LAST_W_IM_OP: \r
- *packet_len+=LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN+ImmDt_LEN;\r
- return(MT_OK);\r
-\r
- case RD_SEND_ONLY_OP: \r
- *packet_len+=LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN;\r
- return(MT_OK);\r
-\r
- case RD_SEND_ONLY_W_IM_OP: \r
- *packet_len+=LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN+ImmDt_LEN;\r
- return(MT_OK);\r
-\r
- case RD_WRITE_FIRST_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN+RETH_LEN;\r
- return(MT_OK);\r
-\r
- case RD_WRITE_MIDDLE_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN;\r
- return(MT_OK);\r
-\r
- case RD_WRITE_LAST_OP: \r
- *packet_len+=LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN;\r
- return(MT_OK);\r
-\r
- case RD_WRITE_LAST_W_IM_OP: \r
- *packet_len+=LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN+ImmDt_LEN;\r
- return(MT_OK);\r
-\r
- case RD_WRITE_ONLY_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN+RETH_LEN;\r
- return(MT_OK);\r
-\r
- case RD_WRITE_ONLY_W_IM_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN+RETH_LEN+ImmDt_LEN;\r
- return(MT_OK);\r
-\r
- case RD_READ_REQ_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN+RETH_LEN;\r
- return(MT_OK);\r
-\r
- case RD_READ_RESP_FIRST_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RDETH_LEN+AETH_LEN;\r
- return(MT_OK);\r
-\r
- case RD_READ_RESP_MIDDLE_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RDETH_LEN;\r
- return(MT_OK);\r
-\r
- case RD_READ_RESP_LAST_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RDETH_LEN+AETH_LEN;\r
- return(MT_OK);\r
-\r
- case RD_READ_RESP_ONLY_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RDETH_LEN+AETH_LEN;\r
- return(MT_OK);\r
-\r
- case RD_ACKNOWLEDGE_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RDETH_LEN+AETH_LEN;\r
- return(MT_OK);\r
-\r
- case RD_ATOMIC_ACKNOWLEDGE_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RDETH_LEN+AETH_LEN+AtomAETH_LEN;\r
- return(MT_OK);\r
-\r
- case RD_CMP_SWAP_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN+AtomETH_LEN;\r
- return(MT_OK);\r
-\r
- case RD_FETCH_ADD_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN+AtomETH_LEN;\r
- return(MT_OK);\r
-\r
-/***********************************************/\r
-/* Unreliable Datagram (UD) */\r
-/***********************************************/\r
-\r
- case UD_SEND_ONLY_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+DETH_LEN;\r
- return(MT_OK);\r
- case UD_SEND_ONLY_W_IM_OP:\r
- *packet_len+=LRH_LEN+BTH_LEN+DETH_LEN+ImmDt_LEN;\r
- return(MT_OK);\r
- default:\r
- MTL_ERROR1("%s: Invalid Opcode (%d)\n", __func__, opcode);\r
- return(MT_ERROR);\r
- break;\r
-\r
- }\r
-}\r
-\r
-call_result_t\r
-MPGA_make_fast(MPGA_headers_t *MPGA_headers_p,\r
- LNH_t LNH,\r
- u_int16_t payload_size,\r
- u_int8_t **packet_p_p)\r
-{ IB_LRH_st *LRH=NULL;\r
- IB_BTH_st *BTH=NULL;\r
- u_int16_t packet_len;\r
-\r
- /* Calculating headers position*/\r
- LRH = (IB_LRH_st*)MPGA_headers_p;\r
- BTH = (IB_BTH_st*)MPGA_headers_p + (LNH == IBA_GLOBAL ? GRH_LEN : 0);\r
-\r
- LRH->LNH = (u_int8_t)LNH;\r
- /* Calculating pad_count*/\r
- BTH->PadCnt = (IBWORD-payload_size%IBWORD)%IBWORD;\r
- /* Calculating pkt_len*/\r
- MPGA_get_headers_size(BTH->OpCode,LNH,0,TRUE,FALSE,&packet_len);\r
- LRH->PktLen = (packet_len + payload_size + BTH->PadCnt) / IBWORD;\r
-\r
- return(MPGA_make_headers(MPGA_headers_p,BTH->OpCode,LNH,FALSE,FALSE,packet_p_p));\r
-\r
-} \r
- \r
-\r
-call_result_t \r
-MPGA_make_headers(MPGA_headers_t *MPGA_headers_p, /*pointer to a headers union*/\r
- IB_opcode_t opcode,\r
- LNH_t LNH,\r
- MT_bool CRC,\r
- u_int16_t payload_size,\r
- u_int8_t **packet_p_p) /* pointer to packet buffer*/\r
-\r
-{ \r
- u_int8_t *start_ICRC;\r
- u_int16_t packet_len;\r
- u_int8_t *packet_p;\r
-\r
- packet_p=*packet_p_p;\r
- if ((LNH!=IBA_LOCAL) && (LNH!=IBA_GLOBAL)) return(MT_ERROR); /*only IBA_LOCAL and IBA_GLOBAL are supported by now*/\r
- if (CRC && (!payload_size)) return(MT_ERROR); /*payload_size must be provided if CRC append is asked*/\r
- if (CRC && (LNH!=IBA_LOCAL && LNH!=IBA_GLOBAL)) return(MT_ERROR); /*CRC calculation is supported only with IBA_LOCAL or IBA_GLOBAL*/\r
- else start_ICRC = packet_p + payload_size;\r
-\r
- switch (LNH)\r
- {\r
- case IBA_LOCAL:\r
- switch (opcode)\r
- {\r
-\r
- /***********************************************/\r
- /* reliable Connection (RC) */\r
- /***********************************************/\r
- \r
- case RC_SEND_FIRST_OP:\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rc_send_first.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rc_send_first.IB_LRH),packet_p-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case RC_SEND_MIDDLE_OP:\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rc_send_middle.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rc_send_middle.IB_LRH),packet_p-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case RC_SEND_LAST_OP:\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rc_send_last.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rc_send_last.IB_LRH),packet_p-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case RC_SEND_LAST_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_rc_send_last_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rc_send_last_ImmDt.IB_BTH),packet_p-ImmDt_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rc_send_last_ImmDt.IB_LRH),packet_p-ImmDt_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case RC_SEND_ONLY_OP: \r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rc_send_only.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rc_send_only.IB_LRH),packet_p-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case RC_SEND_ONLY_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_rc_send_only_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rc_send_only_ImmDt.IB_BTH),packet_p-ImmDt_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rc_send_only_ImmDt.IB_LRH),packet_p-ImmDt_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case RC_WRITE_FIRST_OP:\r
- nMPGA_append_RETH(&(MPGA_headers_p->MPGA_rc_write_first.IB_RETH),packet_p-RETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rc_write_first.IB_BTH),packet_p-RETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rc_write_first.IB_LRH),packet_p-RETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+RETH_LEN);\r
- break;\r
-\r
- case RC_WRITE_MIDDLE_OP:\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rc_write_middle.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rc_write_middle.IB_LRH),packet_p-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case RC_WRITE_LAST_OP: \r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rc_write_last.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rc_write_last.IB_LRH),packet_p-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case RC_WRITE_LAST_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_rc_write_last_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rc_write_last_ImmDt.IB_BTH),packet_p-ImmDt_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rc_write_last_ImmDt.IB_LRH),packet_p-ImmDt_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case RC_WRITE_ONLY_OP:\r
- nMPGA_append_RETH(&(MPGA_headers_p->MPGA_rc_write_only.IB_RETH),packet_p-RETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rc_write_only.IB_BTH),packet_p-RETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rc_write_only.IB_LRH),packet_p-RETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+RETH_LEN);\r
- break;\r
-\r
- case RC_WRITE_ONLY_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_rc_write_last_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_RETH(&(MPGA_headers_p->MPGA_rc_write_only.IB_RETH),packet_p-ImmDt_LEN-RETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rc_write_only.IB_BTH),packet_p-ImmDt_LEN-RETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rc_write_only.IB_LRH),packet_p-ImmDt_LEN-RETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+RETH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case RC_READ_REQ_OP: \r
- nMPGA_append_RETH(&(MPGA_headers_p->MPGA_rc_read_req.IB_RETH),packet_p-RETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rc_read_req.IB_BTH),packet_p-RETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rc_read_req.IB_LRH),packet_p-RETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+RETH_LEN);\r
- break;\r
-\r
- case RC_READ_RESP_FIRST_OP:\r
- nMPGA_append_AETH(&(MPGA_headers_p->MPGA_rc_read_res_first.IB_AETH),packet_p-AETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rc_read_res_first.IB_BTH),packet_p-AETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rc_read_res_first.IB_LRH),packet_p-AETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+AETH_LEN);\r
- break;\r
-\r
- case RC_READ_RESP_MIDDLE_OP: \r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rc_read_res_middle.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rc_read_res_middle.IB_LRH),packet_p-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+AETH_LEN);\r
- break;\r
-\r
- case RC_READ_RESP_LAST_OP: \r
- nMPGA_append_AETH(&(MPGA_headers_p->MPGA_rc_read_res_last.IB_AETH),packet_p-AETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rc_read_res_last.IB_BTH),packet_p-AETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rc_read_res_last.IB_LRH),packet_p-AETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+AETH_LEN);\r
- break;\r
-\r
- case RC_READ_RESP_ONLY_OP: \r
- nMPGA_append_AETH(&(MPGA_headers_p->MPGA_rc_read_res_only.IB_AETH),packet_p-AETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rc_read_res_only.IB_BTH),packet_p-AETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rc_read_res_only.IB_LRH),packet_p-AETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+AETH_LEN);\r
- break;\r
-\r
- case RC_ACKNOWLEDGE_OP: \r
- nMPGA_append_AETH(&(MPGA_headers_p->MPGA_rc_ack.IB_AETH),packet_p-AETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rc_ack.IB_BTH),packet_p-AETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rc_ack.IB_LRH),packet_p-AETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+AETH_LEN);\r
- break;\r
-\r
-\r
- case RC_ATOMIC_ACKNOWLEDGE_OP: \r
- MTL_ERROR1("%s: Unsupported packet type(opcode) (%d)\n", __func__, opcode);\r
- return(MT_ERROR);\r
-\r
- case RC_CMP_SWAP_OP: \r
- MTL_ERROR1("%s: Unsupported packet type(opcode) (%d)\n", __func__, opcode);\r
- return(MT_ERROR);\r
-\r
- case RC_FETCH_ADD_OP: \r
- MTL_ERROR1("%s: Unsupported packet type(opcode) (%d)\n", __func__, opcode);\r
- return(MT_ERROR);\r
-\r
-/***********************************************/\r
-/* Unreliable Connection (UC) */\r
-/***********************************************/\r
- case UC_SEND_FIRST_OP:\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_uc_send_first.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_uc_send_first.IB_LRH),packet_p-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case UC_SEND_MIDDLE_OP:\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_uc_send_middle.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_uc_send_middle.IB_LRH),packet_p-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case UC_SEND_LAST_OP:\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_uc_send_last.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_uc_send_last.IB_LRH),packet_p-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case UC_SEND_LAST_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_uc_send_last_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_uc_send_last_ImmDt.IB_BTH),packet_p-ImmDt_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_uc_send_last_ImmDt.IB_LRH),packet_p-ImmDt_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case UC_SEND_ONLY_OP: \r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_uc_send_only.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_uc_send_only.IB_LRH),packet_p-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case UC_SEND_ONLY_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_uc_send_only_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_uc_send_only_ImmDt.IB_BTH),packet_p-ImmDt_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_uc_send_only_ImmDt.IB_LRH),packet_p-ImmDt_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case UC_WRITE_FIRST_OP:\r
- nMPGA_append_RETH(&(MPGA_headers_p->MPGA_uc_write_first.IB_RETH),packet_p-RETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_uc_write_first.IB_BTH),packet_p-RETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_uc_write_first.IB_LRH),packet_p-RETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+RETH_LEN);\r
- break;\r
-\r
- case UC_WRITE_MIDDLE_OP:\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_uc_write_middle.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_uc_write_middle.IB_LRH),packet_p-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case UC_WRITE_LAST_OP: \r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_uc_write_last.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_uc_write_last.IB_LRH),packet_p-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case UC_WRITE_LAST_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_uc_write_last_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_uc_write_last_ImmDt.IB_BTH),packet_p-ImmDt_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_uc_write_last_ImmDt.IB_LRH),packet_p-ImmDt_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case UC_WRITE_ONLY_OP:\r
- nMPGA_append_RETH(&(MPGA_headers_p->MPGA_uc_write_only.IB_RETH),packet_p-RETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_uc_write_only.IB_BTH),packet_p-RETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_uc_write_only.IB_LRH),packet_p-RETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+RETH_LEN);\r
- break;\r
-\r
- case UC_WRITE_ONLY_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_uc_write_last_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_RETH(&(MPGA_headers_p->MPGA_uc_write_only.IB_RETH),packet_p-ImmDt_LEN-RETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_uc_write_only.IB_BTH),packet_p-ImmDt_LEN-RETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_uc_write_only.IB_LRH),packet_p-ImmDt_LEN-RETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+RETH_LEN+ImmDt_LEN);\r
- break;\r
-\r
-/***********************************************/\r
-/* Reliable Datagram (RD) */\r
-/***********************************************/\r
-\r
- case RD_SEND_FIRST_OP:\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_rd_send_first.IB_DETH),packet_p-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_rd_send_first.IB_RDETH),packet_p-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rd_send_first.IB_BTH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rd_send_first.IB_LRH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN);\r
- break;\r
-\r
- case RD_SEND_MIDDLE_OP:\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_rd_send_middle.IB_DETH),packet_p-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_rd_send_middle.IB_RDETH),packet_p-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rd_send_middle.IB_BTH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rd_send_middle.IB_LRH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN);\r
- break;\r
-\r
- case RD_SEND_LAST_OP:\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_rd_send_last.IB_DETH),packet_p-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_rd_send_last.IB_RDETH),packet_p-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rd_send_last.IB_BTH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rd_send_last.IB_LRH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN);\r
- break;\r
-\r
- case RD_SEND_LAST_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_rd_send_last_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_rd_send_last_ImmDt.IB_DETH),packet_p-ImmDt_LEN-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_rd_send_last_ImmDt.IB_RDETH),packet_p-ImmDt_LEN-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rd_send_last_ImmDt.IB_BTH),packet_p-ImmDt_LEN-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rd_send_last_ImmDt.IB_LRH),packet_p-ImmDt_LEN-DETH_LEN-RDETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case RD_SEND_ONLY_OP: \r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_rd_send_only.IB_DETH),packet_p-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_rd_send_only.IB_RDETH),packet_p-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rd_send_only.IB_BTH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rd_send_only.IB_LRH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN);\r
- break;\r
-\r
- case RD_SEND_ONLY_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_rd_send_only_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_rd_send_only_ImmDt.IB_DETH),packet_p-ImmDt_LEN-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_rd_send_only_ImmDt.IB_RDETH),packet_p-ImmDt_LEN-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rd_send_only_ImmDt.IB_BTH),packet_p-ImmDt_LEN-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rd_send_only_ImmDt.IB_LRH),packet_p-ImmDt_LEN-DETH_LEN-RDETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case RD_WRITE_FIRST_OP:\r
- nMPGA_append_RETH(&(MPGA_headers_p->MPGA_rd_write_first.IB_RETH),packet_p-RETH_LEN);\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_rd_write_first.IB_DETH),packet_p-RETH_LEN-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_rd_write_first.IB_RDETH),packet_p-RETH_LEN-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rd_write_first.IB_BTH),packet_p-RETH_LEN-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rd_write_first.IB_LRH),packet_p-RETH_LEN-DETH_LEN-RDETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN+RETH_LEN);\r
- break;\r
-\r
- case RD_WRITE_MIDDLE_OP:\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_rd_write_middle.IB_DETH),packet_p-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_rd_write_middle.IB_RDETH),packet_p-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rd_write_middle.IB_BTH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rd_write_middle.IB_LRH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN);\r
- break;\r
-\r
- case RD_WRITE_LAST_OP: \r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_rd_write_last.IB_DETH),packet_p-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_rd_write_last.IB_RDETH),packet_p-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rd_write_last.IB_BTH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rd_write_last.IB_LRH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN);\r
- break;\r
-\r
- case RD_WRITE_LAST_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_rd_write_last_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_rd_write_last_ImmDt.IB_DETH),packet_p-ImmDt_LEN-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_rd_write_last_ImmDt.IB_RDETH),packet_p-ImmDt_LEN-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rd_write_last_ImmDt.IB_BTH),packet_p-ImmDt_LEN-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rd_write_last_ImmDt.IB_LRH),packet_p-ImmDt_LEN-DETH_LEN-RDETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case RD_WRITE_ONLY_OP:\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_rd_write_only.IB_DETH),packet_p-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_rd_write_only.IB_RDETH),packet_p-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rd_write_only.IB_BTH),packet_p-DETH_LEN-RDETH_LEN-RETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rd_write_only.IB_LRH),packet_p-DETH_LEN-RDETH_LEN-RETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN+RETH_LEN);\r
- break;\r
-\r
- case RD_WRITE_ONLY_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_rd_write_only_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_RETH(&(MPGA_headers_p->MPGA_rd_write_only_ImmDt.IB_RETH),packet_p-ImmDt_LEN-RETH_LEN);\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_rd_write_only_ImmDt.IB_DETH),packet_p-ImmDt_LEN-RETH_LEN-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_rd_write_only_ImmDt.IB_RDETH),packet_p-ImmDt_LEN-RETH_LEN-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rd_write_only_ImmDt.IB_BTH),packet_p-ImmDt_LEN-RETH_LEN-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rd_write_only_ImmDt.IB_LRH),packet_p-ImmDt_LEN-RETH_LEN-DETH_LEN-RDETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN+RETH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case RD_READ_REQ_OP: \r
- nMPGA_append_RETH(&(MPGA_headers_p->MPGA_rd_read_req.IB_RETH),packet_p-RETH_LEN);\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_rd_read_req.IB_DETH),packet_p-RETH_LEN-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_rd_read_req.IB_RDETH),packet_p-RETH_LEN-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rd_read_req.IB_BTH),packet_p-RETH_LEN-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rd_read_req.IB_LRH),packet_p-RETH_LEN-DETH_LEN-RDETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+RETH_LEN);\r
- break;\r
-\r
- case RD_READ_RESP_FIRST_OP:\r
- nMPGA_append_AETH(&(MPGA_headers_p->MPGA_rd_read_res_first.IB_AETH),packet_p-AETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_rd_read_res_first.IB_RDETH),packet_p-AETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rd_read_res_first.IB_BTH),packet_p-AETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rd_read_res_first.IB_LRH),packet_p-AETH_LEN-RDETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+AETH_LEN);\r
- break;\r
-\r
- case RD_READ_RESP_MIDDLE_OP: \r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_rd_read_res_first.IB_RDETH),packet_p-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rc_read_res_middle.IB_BTH),packet_p-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rc_read_res_middle.IB_LRH),packet_p-RDETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+AETH_LEN);\r
- break;\r
-\r
- case RD_READ_RESP_LAST_OP: \r
- nMPGA_append_AETH(&(MPGA_headers_p->MPGA_rc_read_res_last.IB_AETH),packet_p-AETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_rd_read_res_first.IB_RDETH),packet_p-AETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rc_read_res_last.IB_BTH),packet_p-AETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rc_read_res_last.IB_LRH),packet_p-AETH_LEN-RDETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+AETH_LEN);\r
- break;\r
-\r
- case RD_READ_RESP_ONLY_OP: \r
- nMPGA_append_AETH(&(MPGA_headers_p->MPGA_rc_read_res_only.IB_AETH),packet_p-AETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_rd_read_res_first.IB_RDETH),packet_p-AETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rc_read_res_only.IB_BTH),packet_p-AETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rc_read_res_only.IB_LRH),packet_p-AETH_LEN-RDETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+AETH_LEN);\r
- break;\r
-\r
- case RD_ACKNOWLEDGE_OP:\r
- nMPGA_append_AETH(&(MPGA_headers_p->MPGA_rd_ack.IB_AETH),packet_p-AETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_rd_ack.IB_RDETH),packet_p-AETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_rd_ack.IB_BTH),packet_p-AETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_rd_ack.IB_LRH),packet_p-AETH_LEN-RDETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+RDETH_LEN+AETH_LEN);\r
- break;\r
- case RD_ATOMIC_ACKNOWLEDGE_OP:\r
- case RD_CMP_SWAP_OP:\r
- case RD_FETCH_ADD_OP:\r
- MTL_ERROR1("%s: Unsupported packet type(opcode) (%d)\n", __func__, opcode);\r
- return(MT_ERROR);\r
-\r
-/***********************************************/\r
-/* Unreliable Datagram (UD) */\r
-/***********************************************/\r
-\r
- case UD_SEND_ONLY_OP:\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_ud_send_only.IB_DETH),packet_p-DETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_ud_send_only.IB_BTH),packet_p-DETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_ud_send_only.IB_LRH),packet_p-DETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+DETH_LEN);\r
- break;\r
-\r
- case UD_SEND_ONLY_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_ud_send_only_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_ud_send_only_ImmDt.IB_DETH),packet_p-ImmDt_LEN-DETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_ud_send_only_ImmDt.IB_BTH),packet_p-ImmDt_LEN-DETH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_ud_send_only_ImmDt.IB_LRH),packet_p-ImmDt_LEN-DETH_LEN-BTH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+BTH_LEN+DETH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- default:\r
- MTL_ERROR1("%s: Invalid Opcode (%d)\n", __func__, opcode);\r
- return(MT_ERROR);\r
- break;\r
-\r
- }\r
- break;\r
- case IBA_GLOBAL:\r
- switch (opcode)\r
- {\r
-\r
- /***********************************************/\r
- /* reliable Connection (RC) */\r
- /***********************************************/\r
- \r
- case RC_SEND_FIRST_OP:\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rc_send_first.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rc_send_first.IB_GRH),packet_p-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rc_send_first.IB_LRH),packet_p-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case RC_SEND_MIDDLE_OP:\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rc_send_middle.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rc_send_middle.IB_GRH),packet_p-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rc_send_middle.IB_LRH),packet_p-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case RC_SEND_LAST_OP:\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rc_send_last.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rc_send_last.IB_GRH),packet_p-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rc_send_last.IB_LRH),packet_p-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case RC_SEND_LAST_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_G_rc_send_last_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rc_send_last_ImmDt.IB_BTH),packet_p-ImmDt_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rc_send_last_ImmDt.IB_GRH),packet_p-ImmDt_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rc_send_last_ImmDt.IB_LRH),packet_p-ImmDt_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case RC_SEND_ONLY_OP: \r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rc_send_only.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rc_send_only.IB_GRH),packet_p-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rc_send_only.IB_LRH),packet_p-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case RC_SEND_ONLY_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_G_rc_send_only_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rc_send_only_ImmDt.IB_BTH),packet_p-ImmDt_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rc_send_only_ImmDt.IB_GRH),packet_p-ImmDt_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rc_send_only_ImmDt.IB_LRH),packet_p-ImmDt_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case RC_WRITE_FIRST_OP:\r
- nMPGA_append_RETH(&(MPGA_headers_p->MPGA_G_rc_write_first.IB_RETH),packet_p-RETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rc_write_first.IB_BTH),packet_p-RETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rc_write_first.IB_GRH),packet_p-RETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rc_write_first.IB_LRH),packet_p-RETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+RETH_LEN);\r
- break;\r
-\r
- case RC_WRITE_MIDDLE_OP:\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rc_write_middle.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rc_write_middle.IB_GRH),packet_p-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rc_write_middle.IB_LRH),packet_p-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case RC_WRITE_LAST_OP: \r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rc_write_last.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rc_write_last.IB_GRH),packet_p-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rc_write_last.IB_LRH),packet_p-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case RC_WRITE_LAST_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_G_rc_write_last_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rc_write_last_ImmDt.IB_BTH),packet_p-ImmDt_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rc_write_last_ImmDt.IB_GRH),packet_p-ImmDt_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rc_write_last_ImmDt.IB_LRH),packet_p-ImmDt_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case RC_WRITE_ONLY_OP:\r
- nMPGA_append_RETH(&(MPGA_headers_p->MPGA_G_rc_write_only.IB_RETH),packet_p-RETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rc_write_only.IB_BTH),packet_p-RETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rc_write_only.IB_GRH),packet_p-RETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rc_write_only.IB_LRH),packet_p-RETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+RETH_LEN);\r
- break;\r
-\r
- case RC_WRITE_ONLY_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_G_rc_write_last_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_RETH(&(MPGA_headers_p->MPGA_G_rc_write_only.IB_RETH),packet_p-ImmDt_LEN-RETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rc_write_only.IB_BTH),packet_p-ImmDt_LEN-RETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rc_write_only.IB_GRH),packet_p-ImmDt_LEN-RETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rc_write_only.IB_LRH),packet_p-ImmDt_LEN-RETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+RETH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case RC_READ_REQ_OP: \r
- nMPGA_append_RETH(&(MPGA_headers_p->MPGA_G_rc_read_req.IB_RETH),packet_p-RETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rc_read_req.IB_BTH),packet_p-RETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rc_read_req.IB_GRH),packet_p-RETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rc_read_req.IB_LRH),packet_p-RETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+RETH_LEN);\r
- break;\r
-\r
- case RC_READ_RESP_FIRST_OP:\r
- nMPGA_append_AETH(&(MPGA_headers_p->MPGA_G_rc_read_res_first.IB_AETH),packet_p-AETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rc_read_res_first.IB_BTH),packet_p-AETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rc_read_res_first.IB_GRH),packet_p-AETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rc_read_res_first.IB_LRH),packet_p-AETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+AETH_LEN);\r
- break;\r
-\r
- case RC_READ_RESP_MIDDLE_OP: \r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rc_read_res_middle.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rc_read_res_middle.IB_GRH),packet_p-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rc_read_res_middle.IB_LRH),packet_p-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+AETH_LEN);\r
- break;\r
-\r
- case RC_READ_RESP_LAST_OP: \r
- nMPGA_append_AETH(&(MPGA_headers_p->MPGA_G_rc_read_res_last.IB_AETH),packet_p-AETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rc_read_res_last.IB_BTH),packet_p-AETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rc_read_res_last.IB_GRH),packet_p-AETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rc_read_res_last.IB_LRH),packet_p-AETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+AETH_LEN);\r
- break;\r
-\r
- case RC_READ_RESP_ONLY_OP: \r
- nMPGA_append_AETH(&(MPGA_headers_p->MPGA_G_rc_read_res_only.IB_AETH),packet_p-AETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rc_read_res_only.IB_BTH),packet_p-AETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rc_read_res_only.IB_GRH),packet_p-AETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rc_read_res_only.IB_LRH),packet_p-AETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+AETH_LEN);\r
- break;\r
-\r
- case RC_ACKNOWLEDGE_OP: \r
- nMPGA_append_AETH(&(MPGA_headers_p->MPGA_G_rc_ack.IB_AETH),packet_p-AETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rc_ack.IB_BTH),packet_p-AETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rc_ack.IB_GRH),packet_p-AETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rc_ack.IB_LRH),packet_p-AETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+AETH_LEN);\r
- break;\r
-\r
-\r
- case RC_ATOMIC_ACKNOWLEDGE_OP: \r
- MTL_ERROR1("%s: Unsupported packet type(opcode) (%d)\n", __func__, opcode);\r
- return(MT_ERROR);\r
-\r
- case RC_CMP_SWAP_OP: \r
- MTL_ERROR1("%s: Unsupported packet type(opcode) (%d)\n", __func__, opcode);\r
- return(MT_ERROR);\r
-\r
- case RC_FETCH_ADD_OP: \r
- MTL_ERROR1("%s: Unsupported packet type(opcode) (%d)\n", __func__, opcode);\r
- return(MT_ERROR);\r
-\r
-/***********************************************/\r
-/* Unreliable Connection (UC) */\r
-/***********************************************/\r
- case UC_SEND_FIRST_OP:\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_uc_send_first.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_uc_send_first.IB_GRH),packet_p-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_uc_send_first.IB_LRH),packet_p-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case UC_SEND_MIDDLE_OP:\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_uc_send_middle.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_uc_send_middle.IB_GRH),packet_p-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_uc_send_middle.IB_LRH),packet_p-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case UC_SEND_LAST_OP:\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_uc_send_last.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_uc_send_last.IB_GRH),packet_p-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_uc_send_last.IB_LRH),packet_p-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case UC_SEND_LAST_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_G_uc_send_last_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_uc_send_last_ImmDt.IB_BTH),packet_p-ImmDt_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_uc_send_last_ImmDt.IB_GRH),packet_p-ImmDt_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_uc_send_last_ImmDt.IB_LRH),packet_p-ImmDt_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case UC_SEND_ONLY_OP: \r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_uc_send_only.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_uc_send_only.IB_GRH),packet_p-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_uc_send_only.IB_LRH),packet_p-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case UC_SEND_ONLY_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_G_uc_send_only_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_uc_send_only_ImmDt.IB_BTH),packet_p-ImmDt_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_uc_send_only_ImmDt.IB_GRH),packet_p-ImmDt_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_uc_send_only_ImmDt.IB_LRH),packet_p-ImmDt_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case UC_WRITE_FIRST_OP:\r
- nMPGA_append_RETH(&(MPGA_headers_p->MPGA_G_uc_write_first.IB_RETH),packet_p-RETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_uc_write_first.IB_BTH),packet_p-RETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_uc_write_first.IB_GRH),packet_p-RETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_uc_write_first.IB_LRH),packet_p-RETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+RETH_LEN);\r
- break;\r
-\r
- case UC_WRITE_MIDDLE_OP:\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_uc_write_middle.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_uc_write_middle.IB_GRH),packet_p-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_uc_write_middle.IB_LRH),packet_p-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case UC_WRITE_LAST_OP: \r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_uc_write_last.IB_BTH),packet_p-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_uc_write_last.IB_GRH),packet_p-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_uc_write_last.IB_LRH),packet_p-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN);\r
- break;\r
-\r
- case UC_WRITE_LAST_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_G_uc_write_last_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_uc_write_last_ImmDt.IB_BTH),packet_p-ImmDt_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_uc_write_last_ImmDt.IB_GRH),packet_p-ImmDt_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_uc_write_last_ImmDt.IB_LRH),packet_p-ImmDt_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case UC_WRITE_ONLY_OP:\r
- nMPGA_append_RETH(&(MPGA_headers_p->MPGA_G_uc_write_only.IB_RETH),packet_p-RETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_uc_write_only.IB_BTH),packet_p-RETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_uc_write_only.IB_GRH),packet_p-RETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_uc_write_only.IB_LRH),packet_p-RETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+RETH_LEN);\r
- break;\r
-\r
- case UC_WRITE_ONLY_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_G_uc_write_last_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_RETH(&(MPGA_headers_p->MPGA_G_uc_write_only.IB_RETH),packet_p-ImmDt_LEN-RETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_uc_write_only.IB_BTH),packet_p-ImmDt_LEN-RETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_uc_write_only.IB_GRH),packet_p-ImmDt_LEN-RETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_uc_write_only.IB_LRH),packet_p-ImmDt_LEN-RETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+RETH_LEN+ImmDt_LEN);\r
- break;\r
-\r
-/***********************************************/\r
-/* Reliable Datagram (RD) */\r
-/***********************************************/\r
-\r
- case RD_SEND_FIRST_OP:\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_G_rd_send_first.IB_DETH),packet_p-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_G_rd_send_first.IB_RDETH),packet_p-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rd_send_first.IB_BTH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rd_send_first.IB_GRH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rd_send_first.IB_LRH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN);\r
- break;\r
-\r
- case RD_SEND_MIDDLE_OP:\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_G_rd_send_middle.IB_DETH),packet_p-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_G_rd_send_middle.IB_RDETH),packet_p-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rd_send_middle.IB_BTH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rd_send_middle.IB_GRH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rd_send_middle.IB_LRH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN);\r
- break;\r
-\r
- case RD_SEND_LAST_OP:\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_G_rd_send_last.IB_DETH),packet_p-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_G_rd_send_last.IB_RDETH),packet_p-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rd_send_last.IB_BTH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rd_send_last.IB_GRH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rd_send_last.IB_LRH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN);\r
- break;\r
-\r
- case RD_SEND_LAST_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_G_rd_send_last_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_G_rd_send_last_ImmDt.IB_DETH),packet_p-ImmDt_LEN-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_G_rd_send_last_ImmDt.IB_RDETH),packet_p-ImmDt_LEN-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rd_send_last_ImmDt.IB_BTH),packet_p-ImmDt_LEN-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rd_send_last_ImmDt.IB_GRH),packet_p-ImmDt_LEN-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rd_send_last_ImmDt.IB_LRH),packet_p-ImmDt_LEN-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case RD_SEND_ONLY_OP: \r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_G_rd_send_only.IB_DETH),packet_p-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_G_rd_send_only.IB_RDETH),packet_p-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rd_send_only.IB_BTH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rd_send_only.IB_GRH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rd_send_only.IB_LRH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN);\r
- break;\r
-\r
- case RD_SEND_ONLY_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_G_rd_send_only_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_G_rd_send_only_ImmDt.IB_DETH),packet_p-ImmDt_LEN-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_G_rd_send_only_ImmDt.IB_RDETH),packet_p-ImmDt_LEN-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rd_send_only_ImmDt.IB_BTH),packet_p-ImmDt_LEN-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rd_send_only_ImmDt.IB_GRH),packet_p-ImmDt_LEN-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rd_send_only_ImmDt.IB_LRH),packet_p-ImmDt_LEN-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case RD_WRITE_FIRST_OP:\r
- nMPGA_append_RETH(&(MPGA_headers_p->MPGA_G_rd_write_first.IB_RETH),packet_p-RETH_LEN);\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_G_rd_write_first.IB_DETH),packet_p-RETH_LEN-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_G_rd_write_first.IB_RDETH),packet_p-RETH_LEN-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rd_write_first.IB_BTH),packet_p-RETH_LEN-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rd_write_first.IB_GRH),packet_p-RETH_LEN-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rd_write_first.IB_LRH),packet_p-RETH_LEN-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN+RETH_LEN);\r
- break;\r
-\r
- case RD_WRITE_MIDDLE_OP:\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_G_rd_write_middle.IB_DETH),packet_p-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_G_rd_write_middle.IB_RDETH),packet_p-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rd_write_middle.IB_BTH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rd_write_middle.IB_GRH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rd_write_middle.IB_LRH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN);\r
- break;\r
-\r
- case RD_WRITE_LAST_OP: \r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_G_rd_write_last.IB_DETH),packet_p-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_G_rd_write_last.IB_RDETH),packet_p-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rd_write_last.IB_BTH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rd_write_last.IB_GRH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rd_write_last.IB_LRH),packet_p-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN);\r
- break;\r
-\r
- case RD_WRITE_LAST_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_G_rd_write_last_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_G_rd_write_last_ImmDt.IB_DETH),packet_p-ImmDt_LEN-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_G_rd_write_last_ImmDt.IB_RDETH),packet_p-ImmDt_LEN-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rd_write_last_ImmDt.IB_BTH),packet_p-ImmDt_LEN-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rd_write_last_ImmDt.IB_GRH),packet_p-ImmDt_LEN-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rd_write_last_ImmDt.IB_LRH),packet_p-ImmDt_LEN-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case RD_WRITE_ONLY_OP:\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_G_rd_write_only.IB_DETH),packet_p-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_G_rd_write_only.IB_RDETH),packet_p-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rd_write_only.IB_BTH),packet_p-DETH_LEN-RDETH_LEN-RETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rd_write_only.IB_GRH),packet_p-DETH_LEN-RDETH_LEN-RETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rd_write_only.IB_LRH),packet_p-DETH_LEN-RDETH_LEN-RETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN+RETH_LEN);\r
- break;\r
-\r
- case RD_WRITE_ONLY_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_G_rd_write_only_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_RETH(&(MPGA_headers_p->MPGA_G_rd_write_only_ImmDt.IB_RETH),packet_p-ImmDt_LEN-RETH_LEN);\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_G_rd_write_only_ImmDt.IB_DETH),packet_p-ImmDt_LEN-RETH_LEN-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_G_rd_write_only_ImmDt.IB_RDETH),packet_p-ImmDt_LEN-RETH_LEN-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rd_write_only_ImmDt.IB_BTH),packet_p-ImmDt_LEN-RETH_LEN-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rd_write_only_ImmDt.IB_GRH),packet_p-ImmDt_LEN-RETH_LEN-DETH_LEN-RDETH_LEN-BTH_LEN-BTH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rd_write_only_ImmDt.IB_LRH),packet_p-ImmDt_LEN-RETH_LEN-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+RDETH_LEN+DETH_LEN+RETH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- case RD_READ_REQ_OP: \r
- nMPGA_append_RETH(&(MPGA_headers_p->MPGA_G_rd_read_req.IB_RETH),packet_p-RETH_LEN);\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_G_rd_read_req.IB_DETH),packet_p-RETH_LEN-DETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_G_rd_read_req.IB_RDETH),packet_p-RETH_LEN-DETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rd_read_req.IB_BTH),packet_p-RETH_LEN-DETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rd_read_req.IB_GRH),packet_p-RETH_LEN-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rd_read_req.IB_LRH),packet_p-RETH_LEN-DETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+RETH_LEN);\r
- break;\r
-\r
- case RD_READ_RESP_FIRST_OP:\r
- nMPGA_append_AETH(&(MPGA_headers_p->MPGA_G_rd_read_res_first.IB_AETH),packet_p-AETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_G_rd_read_res_first.IB_RDETH),packet_p-AETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rd_read_res_first.IB_BTH),packet_p-AETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rd_read_res_first.IB_GRH),packet_p-AETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rd_read_res_first.IB_LRH),packet_p-AETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+AETH_LEN);\r
- break;\r
-\r
- case RD_READ_RESP_MIDDLE_OP: \r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_G_rd_read_res_first.IB_RDETH),packet_p-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rc_read_res_middle.IB_BTH),packet_p-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rc_read_res_middle.IB_GRH),packet_p-RDETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rc_read_res_middle.IB_LRH),packet_p-RDETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+AETH_LEN);\r
- break;\r
-\r
- case RD_READ_RESP_LAST_OP: \r
- nMPGA_append_AETH(&(MPGA_headers_p->MPGA_G_rc_read_res_last.IB_AETH),packet_p-AETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_G_rd_read_res_first.IB_RDETH),packet_p-AETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rc_read_res_last.IB_BTH),packet_p-AETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rc_read_res_last.IB_GRH),packet_p-AETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rc_read_res_last.IB_LRH),packet_p-AETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+AETH_LEN);\r
- break;\r
-\r
- case RD_READ_RESP_ONLY_OP: \r
- nMPGA_append_AETH(&(MPGA_headers_p->MPGA_G_rc_read_res_only.IB_AETH),packet_p-AETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_G_rd_read_res_first.IB_RDETH),packet_p-AETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rc_read_res_only.IB_BTH),packet_p-AETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rc_read_res_only.IB_GRH),packet_p-AETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rc_read_res_only.IB_LRH),packet_p-AETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+AETH_LEN);\r
- break;\r
-\r
- case RD_ACKNOWLEDGE_OP:\r
- nMPGA_append_AETH(&(MPGA_headers_p->MPGA_G_rd_ack.IB_AETH),packet_p-AETH_LEN);\r
- nMPGA_append_RDETH(&(MPGA_headers_p->MPGA_G_rd_ack.IB_RDETH),packet_p-AETH_LEN-RDETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_rd_ack.IB_BTH),packet_p-AETH_LEN-RDETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_rd_ack.IB_GRH),packet_p-AETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_rd_ack.IB_LRH),packet_p-AETH_LEN-RDETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+RDETH_LEN+AETH_LEN);\r
- break;\r
- case RD_ATOMIC_ACKNOWLEDGE_OP:\r
- case RD_CMP_SWAP_OP:\r
- case RD_FETCH_ADD_OP:\r
- MTL_ERROR1("%s: Unsupported packet type(opcode) (%d)\n", __func__, opcode);\r
- return(MT_ERROR);\r
-\r
-/***********************************************/\r
-/* Unreliable Datagram (UD) */\r
-/***********************************************/\r
-\r
- case UD_SEND_ONLY_OP:\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_G_ud_send_only.IB_DETH),packet_p-DETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_ud_send_only.IB_BTH),packet_p-DETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_ud_send_only.IB_GRH),packet_p-DETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_ud_send_only.IB_LRH),packet_p-DETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+DETH_LEN);\r
- break;\r
-\r
- case UD_SEND_ONLY_W_IM_OP: \r
- nMPGA_append_ImmDt(&(MPGA_headers_p->MPGA_G_ud_send_only_ImmDt.IB_ImmDt),packet_p-ImmDt_LEN);\r
- nMPGA_append_DETH(&(MPGA_headers_p->MPGA_G_ud_send_only_ImmDt.IB_DETH),packet_p-ImmDt_LEN-DETH_LEN);\r
- nMPGA_append_BTH(&(MPGA_headers_p->MPGA_G_ud_send_only_ImmDt.IB_BTH),packet_p-ImmDt_LEN-DETH_LEN-BTH_LEN);\r
- nMPGA_append_GRH(&(MPGA_headers_p->MPGA_G_ud_send_only_ImmDt.IB_GRH),packet_p-ImmDt_LEN-DETH_LEN-BTH_LEN-GRH_LEN);\r
- nMPGA_append_LRH(&(MPGA_headers_p->MPGA_G_ud_send_only_ImmDt.IB_LRH),packet_p-ImmDt_LEN-DETH_LEN-BTH_LEN-GRH_LEN-LRH_LEN);\r
- packet_p-=(LRH_LEN+GRH_LEN+BTH_LEN+DETH_LEN+ImmDt_LEN);\r
- break;\r
-\r
- default:\r
- MTL_ERROR1("%s: Invalid Opcode (%d)\n", __func__, opcode);\r
- return(MT_ERROR);\r
- break;\r
-\r
- }\r
- default:\r
- break;\r
- }\r
- if (CRC)\r
- {\r
- MPGA_get_headers_size(opcode,LNH,payload_size,FALSE,FALSE,&packet_len);\r
- append_ICRC((u_int16_t*)start_ICRC,fast_calc_ICRC(packet_len,(u_int16_t*)packet_p,LNH));\r
- append_VCRC((u_int16_t*)start_ICRC + ICRC_LEN,fast_calc_VCRC(packet_len,(u_int16_t*)packet_p));\r
- }\r
- *packet_p_p=packet_p;\r
- return(MT_OK);\r
-}\r
-\r
-\r
-\r
-\r
-//call_result_t MPGA_set_field(u_int8_t *packet, /*pointer to packet buffer*/\r
-// MT_offset_t bit_offset,/*bit offset*/\r
-// MT_size_t bit_size, /*bit size*/\r
-// u_int32_t data)\r
-//{\r
-// /* dividing into 3 parts: */\r
-// /* :01234567:01234567:01234567:01234567: */\r
-// /* : *****: : : : First part */\r
-// /* : :********:********: : Second part*/\r
-// /* : : : :** : Last part */\r
-//\r
-// u_int8_t length1,length2,length3;\r
-// u_int8_t offset1;\r
-// u_int8_t *address1,*address2,*address3;\r
-//\r
-// /* Part One*/\r
-// length1 = (8-bit_offset%8)%8 < bit_size ? (8-bit_offset%8)%8 : bit_size;\r
-// offset1 = bit_offset%8;\r
-// address1 = &(packet[bit_offset/8]);\r
-// if (length1>0) INSERTF(*address1,offset1,data,0,length1);\r
-// if (length1>=bit_size) return MT_OK; /*finished*/\r
-// data=data >> length1;\r
-// /* Part Two*/\r
-// length3 = (bit_size - length1) % 8;\r
-// length2 = bit_size - length1 - length3;\r
-// address2 = &(packet[(bit_offset/8)+ (length1&&1)]);\r
-// if(length2>0) memcpy(address2, &data, length2/8);\r
-// if (length1+length2>=bit_size) return MT_OK; /*finished*/\r
-// data=data >> length2;\r
-// /* Part Three */\r
-// address3 = length2 > 0 ? (address2 + 1) : (address1 + 1);\r
-// INSERTF(*address3,0,data , 0,length3);\r
-// return MT_OK;\r
-// \r
-//}\r
-\r
-call_result_t \r
-MPGA_set_field(u_int8_t *packet, /*pointer to packet buffer*/\r
- MT_offset_t bit_offset,/*bit offset*/ \r
- MT_size_t bit_size, /*bit size*/ \r
- u_int32_t data)\r
-{\r
- u_int32_t temp=0;\r
- u_int32_t bit_offset2;\r
- if ( (bit_size+bit_offset/32) > 31) return MT_ERROR;\r
- bit_offset2=(u_int32_t)(32-bit_offset%32-bit_size);\r
-\r
- temp=0; /*this is done in order to avoid compile error of unused variable*/\r
-#ifdef MT_LITTLE_ENDIAN\r
- temp=((u_int32_t*)packet)[bit_offset/32];\r
- temp=mswab32(temp);\r
- MT_INSERT32(temp,data,bit_offset2%32,bit_size);\r
- temp=mswab32(temp);\r
- ((u_int32_t*)packet)[bit_offset/32]=temp;\r
- return MT_OK;\r
-#else\r
- MT_INSERT32(((u_int32_t*)packet)[bit_offset/32],data,bit_offset%32,bit_size);\r
- return MT_OK;\r
-#endif\r
-}\r
-\r
-\r
-call_result_t \r
-MPGA_read_field(u_int8_t *packet, /*pointer to packet buffer*/\r
- MT_offset_t bit_offset,/*bit offset*/\r
- MT_size_t bit_size, /*bit size*/\r
- u_int32_t *data)\r
-{\r
-#ifdef MT_LITTLE_ENDIAN\r
- u_int32_t temp;\r
- if ( (bit_size+bit_offset/32) > 31) return MT_ERROR;\r
- temp=((u_int32_t*)packet)[bit_offset/32];\r
- temp=mswab32(temp);\r
- bit_offset=32-bit_offset%32-bit_size;\r
- *data=MT_EXTRACT32(temp,bit_offset%32,bit_size);\r
- return MT_OK;\r
-#else\r
- if ( (bit_size+bit_offset/32) > 31) return MT_ERROR;\r
- *data=MT_EXTRACT32((packet[bit_offset/32]),bit_offset%32,bit_size);\r
- return MT_OK;\r
-#endif\r
-}\r
-\r
-call_result_t \r
-MPGA_extract_LNH(u_int8_t *packet, /*pointer to packet buffer*/\r
- LNH_t *LNH)\r
-{\r
- if (packet) MPGA_read_field(packet,MT_BIT_OFFSET_SIZE(IB_LRH_p_t,LNH),LNH);\r
- else return(MT_ERROR);\r
- return(MT_OK);\r
-}\r
-\r
-call_result_t \r
-MPGA_get_BTH_offset(u_int8_t *packet,\r
- u_int32_t *offset)\r
-{\r
- LNH_t LNH;\r
- if (!packet) return(MT_ERROR);\r
- MPGA_extract_LNH(packet,&LNH);\r
- switch (LNH)\r
- {\r
- case RAW: /* |LRH|... (Etertype)*/\r
- MTL_ERROR1("%s: Unsupported LNH (%d)\n", __func__, LNH);\r
- return(MT_ERROR); \r
- case IP_NON_IBA_TRANS: /* |LRH|GRH|... */\r
- MTL_ERROR1("%s: Unsupported LNH (%d)\n", __func__, LNH);\r
- return(MT_ERROR);\r
- case IBA_LOCAL: /* |LRH|BTH|... */\r
- *offset = LRH_LEN*8;\r
- break;\r
- case IBA_GLOBAL: /* |LRH|GRH|BTH|... */\r
- *offset = LRH_LEN*8 + GRH_LEN*8;\r
- break;\r
- default:\r
- MTL_ERROR1("%s: Invalid LNH (%d)\n", __func__, LNH);\r
- return(MT_ERROR);\r
- break;\r
- }\r
- return(MT_OK); \r
-}\r
-\r
-call_result_t \r
-MPGA_extract_opcode(u_int8_t *packet,\r
- IB_opcode_t *opcode)\r
-{\r
- u_int32_t BTH_offset;\r
- u_int32_t data=0;\r
- if (!packet) return(MT_ERROR);\r
- MPGA_get_BTH_offset(packet,&BTH_offset);\r
- MPGA_read_field(packet,MT_BIT_OFFSET(IB_BTH_p_t,OpCode)+BTH_offset,MT_BIT_SIZE(IB_BTH_p_t,OpCode),&data);\r
- *opcode=(IB_opcode_t)data;\r
- return(MT_OK); \r
-}\r
-\r
-call_result_t \r
-MPGA_extract_PadCnt(u_int8_t *packet,\r
- u_int8_t *PadCnt)\r
-{\r
- u_int32_t BTH_offset;\r
- u_int32_t data=0;\r
- if (!packet) return(MT_ERROR);\r
- MPGA_get_BTH_offset(packet,&BTH_offset);\r
- MPGA_read_field(packet,MT_BIT_OFFSET(IB_BTH_p_t,OpCode)+BTH_offset,MT_BIT_SIZE(IB_BTH_p_t,OpCode),&data);\r
- *PadCnt=(u_int8_t)data;\r
- return(MT_OK); \r
-}\r
-\r
-call_result_t \r
-MPGA_new_from_old(u_int8_t *old_packet, /*pointer to the buffer where the old headers are*/\r
- u_int8_t *new_packet, /*pointer to the buffer where the new headers should be*/\r
- u_int16_t buffer_size) /*total byte size allocated for headers starting from packet_p*/\r
-/*will be used to avoid illegal memory access*/\r
-{\r
- u_int16_t headers_size;\r
- IB_opcode_t opcode;\r
- LNH_t LNH;\r
-\r
- MPGA_extract_LNH(old_packet,&LNH);\r
- MPGA_extract_opcode(old_packet,&opcode);\r
- MPGA_get_headers_size(opcode,LNH,0,0,0,&headers_size);\r
- if (buffer_size<headers_size)\r
- {\r
- MTL_ERROR1("%s: buffer size is not sufficiant\n", __func__);\r
- return(MT_ERROR); /*Not enough memory*/\r
- }\r
- memcpy(new_packet,old_packet,headers_size);\r
- return(MT_OK);\r
-} \r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-/* MPGA Includes */\r
-#include <mpga.h>\r
-#include <packet_append.h>\r
-#include <internal_functions.h>\r
-#include <MPGA_headers.h>\r
-\r
-\r
-#define nMPGA_MT_BIT_OFFSET(reg_path) \\r
- ((MT_offset_t) &( ((union MPGA_headers_p_t *)(0))-> (reg_path) ))\r
-#define nMPGA_MT_BIT_SIZE(reg_path) \\r
- ((MT_size_t) sizeof( ((union MPGA_headers_p_t *)(0))-> (reg_path) ))\r
-#define nMPGA_MT_BIT_OFFSET_SIZE(reg_path) \\r
- nMPGA_MT_BIT_OFFSET(reg_path) , nMPGA_MT_BIT_SIZE(reg_path)\r
-\r
-/*\r
-#define MT_BIT_OFFSET(struct_ancore,reg_path) \\r
- ((MT_offset_t) &( ((struct (struct_ancore), *)(0))-> (reg_path) ))\r
-#define MT_BIT_SIZE(reg_path) \\r
- ((MT_size_t) sizeof( ((struct (struct_ancore) *)(0))-> (reg_path) ))\r
-#define MT_BIT_OFFSET_SIZE(struct_ancore,reg_path) \\r
- nMPGA_MT_BIT_OFFSET((struct_ancore),(reg_path)) , nMPGA_MT_BIT_SIZE((struct_ancore),(reg_path))\r
-\r
-*/\r
-\r
-\r
-/******************************************************************************************\r
-* Function: MPGA_make_headers\r
-*\r
-* Description: Packs the headers according to the given opcode into the given buffer\r
-* , ICRC/VCRC will be added if asked . The packing does not modify the\r
-* headers themselves or in their packed state.\r
-* \r
-* Supported types:\r
-* All IBA_LOCAL and IBA_GLOBAL except:\r
-* ATOMIC_ACKNOWLEDGE_OP, RD_CMP_SWAP_OP, RD_FETCH_ADD_OP\r
-*\r
-* Parameters: \r
-* \r
-* MPGA_headers_t *MPGA_headers_p (IN) - Pointer to union which include the headers of the packet.\r
-* IB_opcode_t opcode (IN) - The headers will be build accordinly to the opcode\r
-* LNH_t LNH (IN) - idetify next header (e.g IBA_LOCAL)\r
-* MT_bool CRC (IN) - if true then ICRC and VCRC will be added after the payload\r
-* In this case the payload length should be provided\r
-* And the packet should be contiguous(*) in the buffer.\r
-* (*):packet_p (explained later) should point to a buffer with \r
-* sufficiant space before it for the headers (as usuall),\r
-* payload immediatly after it and after the payload 6 allocated free bytes \r
-* for the I/VCRC.\r
-* u_int16_t payload_size (IN) - Used only if CRC==true\r
-* u_int8_t packet_p (OUT)- Pointer to pre-alocated buffer - SHOULDN'T point to the buffer start,\r
-* instead should have 126 free and allocated bytes before it,this is\r
-* where the headers will be written.the headers end will be where \r
-* the given pointer is.the pointer will be modified to point to \r
-* the start of the packed headers.(READ the NOTE!)\r
-* Example:\r
-* Before: | 126 bytes buffer P |\r
-* ^Pointer\r
-*\r
-* After: | P(P.H)-(P.H) |\r
-* Pointer^||||||||||\r
-* Packed Headers \r
-* NOTE FOR ADVANCED USERS: the headers will be built from this pointer \r
-* backwards. a good way to use it is give a pointer with atleast \r
-* 128 bytes free for use behind it,so it would fit to any kind \r
-* of headers.If one wishes to allocate exactly the space needed \r
-* he can use the function MPGA_get_headers_size\r
-*\r
-* Returns:\r
-* MT_OK\r
-* MT_ERROR\r
-*\r
-*****************************************************************************/ \r
-call_result_t MPGA_make_headers(MPGA_headers_t *MPGA_headers_p, /*pointer to a headers union*/\r
- IB_opcode_t opcode,\r
- LNH_t LNH,\r
- MT_bool CRC,\r
- u_int16_t payload_size,\r
- u_int8_t **packet_p_p); /* pointer to packet buffer*/\r
-/*********************************************************************************\r
-* Function: MPGA_make_fast\r
-*\r
-*Description: Generaly the same as MPGA_make_headers, with some enhancment.\r
-* LNH,pad_count and packet length field are filled automaticaly.\r
-* The packet will be build acording to given fields but will overrun the automatic calculated fields.\r
-* MPGA_headers_t *MPGA_headers_p (IN) - Pointer to union which include the headers of the packet.\r
-* LNH_t LNH (IN) - idetify next header (e.g IBA_LOCAL)\r
-* u_int16_t payload_size (IN) - Used only if CRC==true\r
-* u_int8_t packet_p (OUT)- Pointer to pre-alocated buffer - SHOULDN'T point to the buffer start,\r
-*********************************************************************************/\r
-call_result_t MPGA_make_fast(MPGA_headers_t *MPGA_headers_p, /*pointer to headers union*/\r
- LNH_t LNH,\r
- u_int16_t payload_size,\r
- u_int8_t **packet_p_p);\r
-\r
-/******************************************************************************************\r
-* Function: MPGA_set_field\r
-*\r
-* Description: updates a field within a packed packet,the field is stated using\r
-* bit_offset (counting from the packet start) and bit_size.\r
-* It's advicable to use the macro nMPGA_MT_BIT_OFFSET_SIZE or like.\r
-* \r
-* Parameters: \r
-* u_int8_t *packet (IN) pointer to packet buffer\r
-* MT_offset_t bit_offset (IN) \r
-* MT_size_t bit_size (IN) \r
-* u_int32_t data (OUT) \r
-*\r
-* Returns:\r
-* MT_OK\r
-* MT_ERROR\r
-*\r
-*****************************************************************************/\r
-call_result_t MPGA_set_field(u_int8_t *packet, /*pointer to packet buffer*/\r
- MT_offset_t bit_offset,/*bit offset*/\r
- MT_size_t bit_size, /*bit size*/\r
- u_int32_t data);\r
-\r
-/******************************************************************************************\r
-* Function: MPGA_read_field\r
-*\r
-* Description: read a field within a packed packet,the field is stated using\r
-* bit_offset (counting from the packet start) and bit_size.\r
-* It's advicable to use the macro nMPGA_MT_BIT_OFFSET_SIZE or like.\r
-* \r
-* Parameters: \r
-* u_int8_t *packet (IN) pointer to packet buffer\r
-* MT_offset_t bit_offset (IN) \r
-* MT_size_t bit_size (IN) \r
-* u_int32_t *data (OUT) \r
-*\r
-* Returns:\r
-* MT_OK\r
-* MT_ERROR\r
-*\r
-*****************************************************************************/\r
-call_result_t MPGA_read_field(u_int8_t *packet, /*pointer to packet buffer*/\r
- MT_offset_t bit_offset,/*bit offset*/\r
- MT_size_t bit_size, /*bit size*/\r
- u_int32_t *data);\r
-\r
-/******************************************************************************************\r
-* Function: MPGA_new_from_old\r
-*\r
-* Description: Copies the headers of an already packed packet to a new buffer\r
-* \r
-* Supported types: same as MPGA_get_headers_size\r
-* \r
-* Parameters: \r
-* u_int8_t *old_packet pointer to the buffer where the old headers are\r
-* u_int8_t *new_packet pointer to the buffer where the new headers should be\r
-* u_int16_t buffer_size total byte size allocated for headers starting from packet_p\r
-* will be used to avoid illegal memory access\r
-*\r
-* Returns:\r
-* MT_OK\r
-* MT_ERROR\r
-*\r
-*****************************************************************************/\r
-call_result_t MPGA_new_from_old(u_int8_t *old_packet, /*pointer to the buffer where the old headers are*/\r
- u_int8_t *new_packet, /*pointer to the buffer where the new headers should be*/\r
- u_int16_t buffer_size);/*total byte size allocated for headers starting from packet_p*/\r
- /*will be used to avoid illegal memory access*/\r
-/***************************************************************************************\r
- * Function: MPGA_get_headers_size\r
- * Description: Returns the size of the buffer that is need to hold a given packet\r
- * NOTE: This isn't equal to the Pkt_Len field in LRH header, no padding is\r
- * added and VCRC shouldn't be counted (if not explicitly asked)\r
- * supported types: IBA_LOCA - send and RDMA_write\r
- * parameters:\r
- * IB_opcode_t opcode (IN)\r
- * LNH_t LNH (IN)\r
- * u_int16_t payload_len (IN)\r
- * MT_bool icrc (IN) if set - icrc exist \r
- * MT_bool vcrc (IN) if set - vcrc exist\r
- * u_int16_t *packet_len(OUT) packet length in bytes\r
- * Returns:\r
- * MT_OK\r
- * MT_ERROR\r
- ***************************************************************************************/\r
-call_result_t MPGA_get_headers_size(IB_opcode_t opcode,\r
- LNH_t LNH,\r
- u_int16_t payload_len, \r
- MT_bool icrc, /*if set - icrc exist*/\r
- MT_bool vcrc, /*if set - vcrc exist*/\r
- u_int16_t *packet_len); /*packet length in bytes*/\r
-\r
-/***************************************************************************************\r
- * Function: MPGA_extract_LNH\r
- * Description: extract the LNH field from a given packed packet (pointer is to the packet start)\r
- * Parameters: \r
- * u_int8_t *packet (OUT) pointer to packet buffer\r
- * LNH_t *LNH (IN/OUT) will be modified (but not allocated!) \r
- * Returns:\r
- * MT_OK\r
- * MT_ERROR\r
- ***************************************************************************************/\r
-call_result_t MPGA_extract_LNH(u_int8_t *packet, /*pointer to packet buffer*/\r
- LNH_t *LNH);\r
-\r
-/***************************************************************************************\r
- * Function: MPGA_extract_opcode\r
- * Description: extract the opcode field from a given packed packet (pointer is to the packet start)\r
- * Parameters: \r
- * u_int8_t *packet (OUT) pointer to packet buffer\r
- * IB_opcode_t *opcode (IN/OUT) will be modified (but not allocated!) \r
- * Returns:\r
- * MT_OK\r
- * MT_ERROR\r
-***************************************************************************************/\r
-call_result_t MPGA_extract_opcode(u_int8_t *packet,\r
- IB_opcode_t *opcode);\r
-\r
-/***************************************************************************************\r
- * Function: MPGA_extract_PadCnt\r
- * Description: extract the PadCnt field from a given packed packet (pointer is to the packet start)\r
- * Parameters: \r
- * u_int8_t *packet (OUT) pointer to packet buffer\r
- * u_int8_t *PadCnt (IN/OUT) will be modified (but not allocated!) \r
- * Returns:\r
- * MT_OK\r
- * MT_ERROR\r
- ***************************************************************************************/\r
-call_result_t MPGA_extract_PadCnt(u_int8_t *packet,\r
- u_int8_t *PadCnt);\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#include <bit_ops.h>\r
-\r
-/* Layers Include */\r
-#include <mtl_common.h>\r
-#ifdef __WIN__\r
-#include <mosal.h>\r
-#endif\r
-#include <ib_defs.h>\r
-\r
-/* MPGA Includes */ \r
-#include "nMPGA_packet_append.h"\r
-#include <packet_append.h>\r
-#include <internal_functions.h>\r
-\r
-\r
-\r
-/*************************************************************************/\r
-/* nMPGA_append lrh */\r
-/*************************************************************************/\r
-call_result_t\r
-nMPGA_append_LRH (IB_LRH_st *lrh_st_p, \r
- u_int8_t *start_LRH_p)\r
-{\r
- INSERTF(start_LRH_p[0],4,lrh_st_p->VL,0,4);\r
- INSERTF(start_LRH_p[0],0,lrh_st_p->LVer,0,4);\r
- INSERTF(start_LRH_p[1],4,lrh_st_p->SL,0,4);\r
- INSERTF(start_LRH_p[1],2,lrh_st_p->reserved1,0,2);\r
- INSERTF(start_LRH_p[1],0,lrh_st_p->LNH,0,2);\r
- INSERTF(start_LRH_p[2],0,lrh_st_p->DLID,8,8);\r
- INSERTF(start_LRH_p[3],0,lrh_st_p->DLID,0,8);\r
- INSERTF(start_LRH_p[4],3,lrh_st_p->reserved2,0,5);\r
- INSERTF(start_LRH_p[4],0,lrh_st_p->PktLen,8,3);\r
- INSERTF(start_LRH_p[5],0,lrh_st_p->PktLen,0,8);\r
- INSERTF(start_LRH_p[6],0,lrh_st_p->SLID,8,8);\r
- INSERTF(start_LRH_p[7],0,lrh_st_p->SLID,0,8);\r
- return(MT_OK);\r
-}\r
-\r
-/*************************************************************************/\r
-/* nMPGA_append grh */\r
-/*************************************************************************/\r
-call_result_t\r
-nMPGA_append_GRH (IB_GRH_st *grh_st_p,\r
- u_int8_t *start_GRH_p)\r
-{\r
- INSERTF(start_GRH_p[0],4,grh_st_p->IPVer,0,4);\r
- INSERTF(start_GRH_p[0],0,grh_st_p->TClass,4,4);\r
- INSERTF(start_GRH_p[1],4,grh_st_p->TClass,0,4);\r
- INSERTF(start_GRH_p[1],0,grh_st_p->FlowLabel,16,4);\r
- INSERTF(start_GRH_p[2],0,grh_st_p->FlowLabel,8,8);\r
- INSERTF(start_GRH_p[3],0,grh_st_p->FlowLabel,0,8);\r
- INSERTF(start_GRH_p[4],0,grh_st_p->PayLen,8,8);\r
- INSERTF(start_GRH_p[5],0,grh_st_p->PayLen,0,8);\r
- start_GRH_p[6] = grh_st_p->NxtHdr;\r
- start_GRH_p[7] = grh_st_p->HopLmt;\r
- memcpy(&(start_GRH_p[8]), grh_st_p->SGID, sizeof(IB_gid_t));\r
- memcpy(&(start_GRH_p[24]), grh_st_p->DGID, sizeof(IB_gid_t));\r
- return(MT_OK);\r
-}\r
-/*********************************************************************************/\r
-/* nMPGA_append BTH */\r
-/*********************************************************************************/\r
-call_result_t\r
-nMPGA_append_BTH (IB_BTH_st *bth_st_p, u_int8_t *start_BTH_p)\r
-{\r
- INSERTF(start_BTH_p[0],0,bth_st_p->OpCode,0,8);\r
- INSERTF(start_BTH_p[1],7,bth_st_p->SE,0,1);\r
- INSERTF(start_BTH_p[1],6,bth_st_p->M,0,1);\r
- INSERTF(start_BTH_p[1],4,bth_st_p->PadCnt,0,2);\r
- INSERTF(start_BTH_p[1],0,bth_st_p->TVer,0,4);\r
- INSERTF(start_BTH_p[2],0,bth_st_p->P_KEY,8,8);\r
- INSERTF(start_BTH_p[3],0,bth_st_p->P_KEY,0,8);\r
- INSERTF(start_BTH_p[4],0,bth_st_p->reserved1,0,8);\r
- INSERTF(start_BTH_p[5],0,bth_st_p->DestQP,16,8);\r
- INSERTF(start_BTH_p[6],0,bth_st_p->DestQP,8,8);\r
- INSERTF(start_BTH_p[7],0,bth_st_p->DestQP,0,8);\r
- INSERTF(start_BTH_p[8],7,bth_st_p->A,0,1);\r
- INSERTF(start_BTH_p[8],0,bth_st_p->reserved2,0,7);\r
- INSERTF(start_BTH_p[9],0,bth_st_p->PSN,16,8);\r
- INSERTF(start_BTH_p[10],0,bth_st_p->PSN,8,8);\r
- INSERTF(start_BTH_p[11],0,bth_st_p->PSN,0,8);\r
- return(MT_OK);\r
-}\r
-\r
-/*********************************************************************************/\r
-/* nMPGA_append RETH */\r
-/*********************************************************************************/\r
-call_result_t\r
-nMPGA_append_RETH (IB_RETH_st *reth_st_p, u_int8_t *start_RETH_p)\r
-{\r
- u_int8_t *start_VA_p;\r
- u_int8_t *start_R_Key_p;\r
- u_int8_t *start_DMALen_p;\r
-\r
- start_VA_p = start_RETH_p;/*The first field*/\r
- start_R_Key_p = start_RETH_p + 8; /*1st field 8 byte long*/\r
- start_DMALen_p = start_RETH_p + 12;/*2nd fiels 4 byte + 12 1st*/\r
-\r
- (*((u_int64_t*)start_VA_p)) = MOSAL_cpu_to_be64(reth_st_p->VA); /*64bit field (big endian)*/\r
- (*((u_int32_t*)start_R_Key_p)) = MOSAL_cpu_to_be32(reth_st_p->R_Key);/*32bit field (big endian)*/\r
- (*((u_int32_t*)start_DMALen_p)) = MOSAL_cpu_to_be32(reth_st_p->DMALen);/*32bit field (big e)*/\r
- return(MT_OK);\r
-}\r
-\r
-/*********************************************************************************/\r
-/* nMPGA_append AETH */\r
-/*********************************************************************************/\r
-call_result_t\r
-nMPGA_append_AETH (IB_AETH_st *aeth_st_p, u_int8_t *start_AETH_p)\r
-{\r
- INSERTF(start_AETH_p[0],0,aeth_st_p->Syndrome,0,8);/*8 bitf (big endain)*/\r
- INSERTF(start_AETH_p[1],0,aeth_st_p->MSN,16,8);/*24 bitf (big endain)*/\r
- INSERTF(start_AETH_p[2],0,aeth_st_p->MSN,8,8); /*it is dangerus to use bm*/\r
- INSERTF(start_AETH_p[3],0,aeth_st_p->MSN,0,8);\r
- return(MT_OK);\r
-}\r
-\r
-/*********************************************************************************/\r
-/* nMPGA_append RDETH */\r
-/*********************************************************************************/\r
-call_result_t\r
-nMPGA_append_RDETH (IB_RDETH_st *rdeth_st_p, u_int8_t *start_RDETH_p)\r
-{\r
- start_RDETH_p[0] = rdeth_st_p->reserved1;/*8bit field (big endian)*/\r
- INSERTF(start_RDETH_p[1],0,rdeth_st_p->EECnxt,16,8);/*24bit field (big endian)*/\r
- INSERTF(start_RDETH_p[2],0,rdeth_st_p->EECnxt,8,8);\r
- INSERTF(start_RDETH_p[3],0,rdeth_st_p->EECnxt,0,8);\r
- return(MT_OK);\r
-}\r
-\r
-/*********************************************************************************/\r
-/* nMPGA_append DETH */\r
-/*********************************************************************************/\r
-call_result_t\r
-nMPGA_append_DETH (IB_DETH_st *deth_st_p, u_int8_t *start_DETH_p)\r
-{\r
- u_int8_t *start_Q_Key_p;\r
-\r
- start_Q_Key_p = start_DETH_p;\r
-\r
- (*((u_int32_t*)start_Q_Key_p)) = MOSAL_cpu_to_be32(deth_st_p->Q_Key); /*32bit field (big endian)*/\r
- start_DETH_p[4] = deth_st_p->reserved1;/*8bit field (big endian)*/\r
- INSERTF(start_DETH_p[5],0,deth_st_p->SrcQP,16,8);/*24bit field (big endian)*/\r
- INSERTF(start_DETH_p[6],0,deth_st_p->SrcQP,8,8);\r
- INSERTF(start_DETH_p[7],0,deth_st_p->SrcQP,0,8);\r
- return(MT_OK);\r
-}\r
-/*********************************************************************************/\r
-/* nMPGA_append ImmDt */\r
-/*********************************************************************************/\r
-call_result_t\r
-nMPGA_append_ImmDt (IB_ImmDt_st *ImmDt_st_p, u_int8_t *start_ImmDt_p)\r
-{\r
- (*((u_int32_t*)start_ImmDt_p)) = MOSAL_cpu_to_be32(ImmDt_st_p->ImmDt); /*32bit field (big endian)*/\r
- return(MT_OK);\r
-}\r
- \r
-/*********************************************************************************/\r
-/* nMPGA_append ICRC */\r
-/*********************************************************************************/\r
-call_result_t\r
-nMPGA_append_ICRC(u_int16_t *start_ICRC, u_int32_t ICRC)\r
-{\r
- *((u_int32_t*)start_ICRC) = MOSAL_cpu_to_le32(ICRC);\r
- return(MT_OK);\r
-}\r
-\r
-/*********************************************************************************/\r
-/* nMPGA_append VCRC */\r
-/*********************************************************************************/\r
-call_result_t\r
-nMPGA_append_VCRC(u_int16_t *start_VCRC, u_int16_t VCRC)\r
-{\r
- *((u_int16_t*)start_VCRC) = MOSAL_cpu_to_le16(VCRC);\r
- return(MT_OK);\r
-}\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#ifndef H_nMPGA_PACKET_APPEND_H\r
-#define H_nMPGA_PACKET_APPEND_H\r
-\r
-/* Layers Includes */ \r
-#include <mtl_types.h>\r
-\r
-/*******************/\r
-\r
-#ifdef __WIN__\r
-#include <string.h>\r
-#endif\r
-\r
-#if !defined(__DARWIN__) && defined(__LINUX__) && !defined(__KERNEL__)\r
- #include <endian.h>\r
-#endif\r
-\r
-#include <mpga.h>\r
-\r
-/*Start of function declarations*/\r
-/******************************************************************************\r
- * Function: nMPGA_append_LRH\r
- *\r
- * Description: This function is appending LRH to IB packets .\r
- * To use this function you must have a LRH struct,\r
- * with all the detailes to create the wanted packet.\r
- * additionaly you should give a pointer for the new appended LRH\r
- *\r
- * Parameters:\r
- * IB_LRH_st *lrh_st_p(IN) Link next header .\r
- * u_int8_t *start_LRH_p(OUT) preallocated buffer\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR if no packet was generated.\r
- *****************************************************************************/\r
-call_result_t\r
-nMPGA_append_LRH(IB_LRH_st *lrh_st_p, u_int8_t *start_LRH_p);\r
-/******************************************************************************\r
- * Function: nMPGA_append_GRH\r
- *\r
- * Description: This function is appending GRH to IB packets .\r
- * To use this function you must have a GRH struct,\r
- * with all the detailes to create the wanted packet.\r
- * and an allocated area with free space for the GRH field\r
- *\r
- * Parameters:\r
- * IB_GRH_st *grh_st_p(IN) Global Route Header.\r
- * u_int8_t *start_GRH_p(OUT) preallocated buffer.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR if the field was not appended.\r
- *****************************************************************************/\r
-call_result_t\r
-nMPGA_append_GRH(IB_GRH_st *grh_st_p,u_int8_t *start_GRH_p);\r
-\r
-/******************************************************************************\r
- * Function: nMPGA_append_BTH\r
- *\r
- * Description: This function is appending BTH to IB packets .\r
- * To use this function you must have a BTH struct,\r
- * with all the detailes to create the wanted packet.\r
- * and an allocated area with free space for the BTH field\r
- *\r
- * Parameters:\r
- * IB_BTH_st *bth_st_p(out) \r
- * u_int8_t *start_BTH_p(IN)\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR if no packet was generated.\r
- *****************************************************************************/\r
-call_result_t\r
-nMPGA_append_BTH(IB_BTH_st *bth_st_p, u_int8_t *start_BTH_p);\r
-\r
-/******************************************************************************\r
- * Function: nMPGA_append_RETH\r
- *\r
- * Description: This function is appending RETH to IB packets .\r
- * To use this function you must have a RETH struct,\r
- * with all the detailes to create the wanted packet.\r
- * and an allocated area with a free space for the RETH field.\r
- *\r
- * Parameters:\r
- * IB_RETH_st *reth_st_p(in)\r
- * u_int8_t *start_RETH_p(out)\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR if no packet was generated.\r
- *****************************************************************************/\r
-call_result_t\r
-nMPGA_append_RETH(IB_RETH_st *reth_st_p, u_int8_t *start_RETH_p);\r
-\r
-/******************************************************************************\r
- * Function: nMPGA_append_AETH\r
- *\r
- * Description: This function is appending AETH to IB packets .\r
- * To use this function you must have a AETH struct,\r
- * with all the detailes to create the wanted packet.\r
- * and an allocated area with a free space for the AETH field.\r
- *\r
- * Parameters:\r
- * IB_AETH_st *aeth_st_p(in) \r
- * u_int8_t *start_AETH_p(out)\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR if no packet was generated.\r
- *****************************************************************************/\r
-call_result_t\r
-nMPGA_append_AETH(IB_AETH_st *aeth_st_p, u_int8_t *start_AETH_p);\r
-\r
-/*****************************************************************************/\r
-/* From this point the function is Datagram */\r
-/*****************************************************************************/\r
-\r
-/******************************************************************************\r
- * Function: nMPGA_append_DETH\r
- *\r
- * Description: This function is appending DETH to IB packets .\r
- * To use this function you must have a DETH struct,\r
- * with all the detailes to create the wanted packet.\r
- * and an allocated area with a free space for the DETH field.\r
- *\r
- * Parameters:\r
- * IB_DETH_st *deth_st_p(in)\r
- * u_int8_t *start_DETH_p(out)\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR .\r
- *****************************************************************************/\r
-call_result_t\r
-nMPGA_append_DETH(IB_DETH_st *deth_st_p, u_int8_t *start_DETH_p);\r
-\r
-/******************************************************************************\r
- * Function: nMPGA_append_RDETH\r
- *\r
- * Description: This function is appending RDETH to IB packets .\r
- * To use this function you must have a RDETH struct,\r
- * with all the detailes to create the wanted packet.\r
- * and an allocated area with a free space for the RDETH field.\r
- *\r
- * Parameters:\r
- * IB_RDETH_st *deth_st_p(in)\r
- * u_int8_t *start_RDETH_p(out)\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR .\r
- *****************************************************************************/\r
-call_result_t\r
-nMPGA_append_RDETH(IB_RDETH_st *deth_st_p, u_int8_t *start_RDETH_p);\r
-\r
-/******************************************************************************\r
- * Function: nMPGA_append_ImmDt\r
- *\r
- * Description: This function is appending ImmDt to IB packets .\r
- * To use this function you must have a ImmDt struct,\r
- * with all the detailes to create the wanted packet.\r
- * and an allocated area with a free space for the ImmDt field.\r
- *\r
- * Parameters:\r
- * IB_ImmDt_st *ImmDt_st_p(in)\r
- * u_int8_t *start_ImmDt_p(out)\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR .\r
- *****************************************************************************/ \r
-call_result_t\r
-nMPGA_append_ImmDt(IB_ImmDt_st *ImmDt_st_p, u_int8_t *start_ImmDt_p); \r
-\r
- /******************************************************************************\r
- * Function: nMPGA_append_ICRC\r
- *\r
- * Description: This function is appending the ICRC to the IB packets .\r
- *\r
- * Parameters:\r
- * start_ICRC(in) u_int16_t *\r
- * pointer to the start of the ICRC field\r
- * ICRC(in) u_int32_t\r
- * The ICRC to insert\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR\r
- *****************************************************************************/\r
-call_result_t\r
-nMPGA_append_ICRC(u_int16_t *start_ICRC, u_int32_t ICRC);\r
-\r
- /******************************************************************************\r
- * Function: nMPGA_append_VCRC\r
- *\r
- * Description: This function is appending the VCRC to the IB packets .\r
- *\r
- * Parameters:\r
- * start_VCRC(in) u_int16_t *\r
- * pointer to the start of the VCRC field\r
- * VCRC(in) u_int32_t\r
- * The VCRC to insert\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR\r
- *****************************************************************************/\r
-call_result_t\r
-nMPGA_append_VCRC(u_int16_t *start_VCRC, u_int16_t VCRC);\r
-\r
-#endif /* H_nMPGA_PACKET_APPEND_H */\r
-EXPORTS\r
- MPGA_build_pkt_lrh\r
- MPGA_reliable_send\r
- MPGA_rc_send_only\r
- MPGA_rc_rdma_w_only\r
- MPGA_rc_rdma_w_first\r
- MPGA_rc_rdma_w_middle\r
- MPGA_rc_rdma_w_last\r
- MPGA_rc_rdma_r_req\r
- MPGA_rc_rdma_r_resp\r
- MPGA_rc_rdma_r_resp_only\r
- MPGA_ud_send_only\r
- MPGA_fast_ud_send_only\r
- MPGA_fast_rc_send_first\r
- MPGA_fast_rc_send_middle\r
- MPGA_fast_rc_send_last\r
- MPGA_fast_rc_send_only\r
- MPGA_fast_rc_read_resp_first\r
- MPGA_fast_rc_read_resp_middle\r
- MPGA_fast_rc_read_resp_last\r
- MPGA_fast_rc_read_resp_only\r
- MPGA_fast_rc_acknowledge\r
- MPGA_analyze_packet\r
- MPGA_print_pkt\r
- MPGA_free_pkt_st_fields\r
-\r
- MPGA_build_pkt_lrh_sv\r
- MPGA_rc_send_only_sv\r
- MPGA_fast_ud_send_grh\r
- extract_RETH\r
- extract_BTH\r
- extract_GRH\r
- fast_calc_VCRC\r
- extract_VCRC\r
- fast_calc_ICRC\r
- extract_ICRC\r
- extract_LRH\r
- MPGA_new_from_old\r
- MPGA_set_field\r
- MPGA_read_field\r
- MPGA_extract_LNH\r
- MPGA_extract_opcode\r
- MPGA_make_headers\r
- MPGA_get_headers_size \r
-/*\r
- This software is available to you under a choice of one of two\r
- licenses. You may choose to be licensed under the terms of the GNU\r
- General Public License (GPL) Version 2, available at\r
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD\r
- license, available in the LICENSE.TXT file accompanying this\r
- software. These details are also available at\r
- <http://openib.org/license.html>.\r
-\r
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- SOFTWARE.\r
-\r
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.\r
-*/\r
-#ifdef __KERNEL__\r
-\r
-#include "mtl_types.h"\r
-\r
-/* ----- Kernel Space ----- */\r
-\r
-NTSTATUS \r
-DriverEntry(\r
- IN PDRIVER_OBJECT pi_pDriverObject,\r
- IN PUNICODE_STRING pi_pRegistryPath\r
- )\r
-{ /* DriverEntry */\r
-\r
- DbgPrint("\n***** MPGA_KL: DriverEntry()");\r
- return STATUS_SUCCESS;\r
-\r
-} /* DriverEntry */\r
-\r
-NTSTATUS DllInitialize(PUNICODE_STRING RegistryPath)\r
-{\r
- DbgPrint("\n***** MPGA_KL: DllInitialize()");\r
- return STATUS_SUCCESS;\r
-}\r
-\r
-NTSTATUS DllUnload()\r
-{\r
- DbgPrint("\n***** MPGA_KL: DllUnload()");\r
- return STATUS_SUCCESS;\r
-}\r
-#endif\r
\r
-EXPORTS\r
- DllInitialize private\r
- DllUnload private\r
- MPGA_init_module=init_module\r
- MPGA_cleanup_module=cleanup_module\r
- MPGA_build_pkt_lrh\r
- MPGA_reliable_send\r
- MPGA_rc_send_only\r
- MPGA_rc_rdma_w_only\r
- MPGA_rc_rdma_w_first\r
- MPGA_rc_rdma_w_middle\r
- MPGA_rc_rdma_w_last\r
- MPGA_rc_rdma_r_req\r
- MPGA_rc_rdma_r_resp\r
- MPGA_rc_rdma_r_resp_only\r
- MPGA_ud_send_only\r
- MPGA_fast_ud_send_only\r
- MPGA_fast_rc_send_first\r
- MPGA_fast_rc_send_middle\r
- MPGA_fast_rc_send_last\r
- MPGA_fast_rc_send_only\r
- MPGA_fast_rc_read_resp_first\r
- MPGA_fast_rc_read_resp_middle\r
- MPGA_fast_rc_read_resp_last\r
- MPGA_fast_rc_read_resp_only\r
- MPGA_fast_rc_acknowledge\r
- MPGA_analyze_packet\r
- MPGA_print_pkt\r
- MPGA_free_pkt_st_fields\r
- MPGA_fast_ud_send_grh\r
- extract_RETH\r
- extract_BTH\r
- extract_GRH\r
- fast_calc_VCRC\r
- extract_VCRC\r
- fast_calc_ICRC\r
- extract_ICRC\r
- extract_LRH\r
- MPGA_new_from_old\r
- MPGA_set_field\r
- MPGA_read_field\r
- MPGA_extract_LNH\r
- MPGA_extract_opcode\r
- MPGA_make_headers\r
- MPGA_get_headers_size \r
- \r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#include <bit_ops.h>\r
-\r
-/* Layers Include */\r
-#include <mtl_common.h>\r
-#ifdef __WIN__\r
-#include <mosal.h>\r
-#endif\r
-#include <ib_defs.h>\r
-\r
-/* MPGA Includes */ \r
-#include <packet_append.h>\r
-#include <internal_functions.h>\r
-\r
-\r
-/*************************************************************************/\r
-/* append lrh */\r
-/*************************************************************************/\r
-call_result_t\r
-append_LRH (IB_LRH_st *lrh_st_p, u_int16_t packet_size,\r
- u_int16_t **packet_buf_vp,LNH_t LNH)\r
-{\r
- u_int8_t *start_LRH_p;\r
- u_int16_t **packet_buf_p;\r
-\r
- packet_buf_p = (u_int16_t**)packet_buf_vp; /*casting to u_int16_t */\r
-\r
-/*Update the fields in the given lrh struct*/\r
- lrh_st_p->LNH = (u_int8_t)LNH;\r
- lrh_st_p->PktLen = (packet_size - VCRC_LEN) / IBWORD;\r
- /*from the firest byte of the LRH till the VCRC in 4 byte word*/\r
- lrh_st_p->reserved1 = 0;\r
- lrh_st_p->reserved2 = 0;\r
-\r
- start_LRH_p = (u_int8_t*)(*packet_buf_p) - LRH_LEN;\r
-\r
- start_LRH_p[0] = INSERTF(start_LRH_p[0],4,lrh_st_p->VL,0,4);\r
- start_LRH_p[0] = INSERTF(start_LRH_p[0],0,lrh_st_p->LVer,0,4);\r
- start_LRH_p[1] = INSERTF(start_LRH_p[1],4,lrh_st_p->SL,0,4);\r
- start_LRH_p[1] = INSERTF(start_LRH_p[1],2,lrh_st_p->reserved1,0,2);\r
- start_LRH_p[1] = INSERTF(start_LRH_p[1],0,lrh_st_p->LNH,0,2);\r
- start_LRH_p[2] = INSERTF(start_LRH_p[2],0,lrh_st_p->DLID,8,8);\r
- start_LRH_p[3] = INSERTF(start_LRH_p[3],0,lrh_st_p->DLID,0,8);\r
- start_LRH_p[4] = INSERTF(start_LRH_p[4],3,lrh_st_p->reserved2,0,5);\r
- start_LRH_p[4] = INSERTF(start_LRH_p[4],0,lrh_st_p->PktLen,8,3);\r
- start_LRH_p[5] = INSERTF(start_LRH_p[5],0,lrh_st_p->PktLen,0,8);\r
- start_LRH_p[6] = INSERTF(start_LRH_p[6],0,lrh_st_p->SLID,8,8);\r
- start_LRH_p[7] = INSERTF(start_LRH_p[7],0,lrh_st_p->SLID,0,8);\r
-\r
- (*packet_buf_p) = (u_int16_t*)start_LRH_p;\r
-\r
- return(MT_OK);\r
-}\r
-\r
-/*********************************************************************************/\r
-/* Extract LRH */\r
-/*********************************************************************************/\r
-call_result_t\r
-extract_LRH(IB_LRH_st *lrh_st_p, u_int16_t **packet_buf_p)\r
-{\r
- u_int8_t *start_LRH_p;\r
- u_int8_t *end_LRH_p;\r
-\r
-\r
- memset(lrh_st_p, 0, sizeof(IB_LRH_st));\r
-\r
- start_LRH_p = (u_int8_t*)(*packet_buf_p);\r
- end_LRH_p = (u_int8_t*)(*packet_buf_p) + LRH_LEN;\r
-\r
-\r
-\r
- lrh_st_p->VL = INSERTF(lrh_st_p->VL,0,start_LRH_p[0],4,4);\r
- lrh_st_p->LVer = INSERTF(lrh_st_p->LVer,0,start_LRH_p[0],0,4);\r
- lrh_st_p->SL = INSERTF(lrh_st_p->SL,0,start_LRH_p[1],4,4);\r
- lrh_st_p->reserved1 = INSERTF(lrh_st_p->reserved1,0,start_LRH_p[1],2,2);\r
- lrh_st_p->LNH = INSERTF(lrh_st_p->LNH,0,start_LRH_p[1],0,2);\r
- lrh_st_p->DLID = INSERTF(lrh_st_p->DLID,8,start_LRH_p[2],0,8);\r
- lrh_st_p->DLID = INSERTF(lrh_st_p->DLID,0,start_LRH_p[3],0,8);\r
- lrh_st_p->reserved2 = INSERTF(lrh_st_p->reserved2,0,start_LRH_p[4],3,5);\r
- lrh_st_p->PktLen = INSERTF(lrh_st_p->PktLen,8,start_LRH_p[4],0,3);\r
- lrh_st_p->PktLen = INSERTF(lrh_st_p->PktLen,0,start_LRH_p[5],0,8);\r
- lrh_st_p->SLID = INSERTF(lrh_st_p->SLID,8,start_LRH_p[6],0,8);\r
- lrh_st_p->SLID = INSERTF(lrh_st_p->SLID,0,start_LRH_p[7],0,8);\r
-\r
- (*packet_buf_p) = (u_int16_t *)end_LRH_p;\r
- /*Updating The packet_puf_p to be at the end of the LRH field*/\r
- return(MT_OK);\r
-}\r
-\r
-\r
-/*************************************************************************/\r
-/* append grh */\r
-/*************************************************************************/\r
-call_result_t\r
-append_GRH (IB_GRH_st *grh_st_p, u_int16_t packet_size,\r
- u_int16_t **packet_buf_vp)\r
-{\r
- u_int8_t *start_GRH_p;\r
- u_int16_t **packet_buf_p;\r
-\r
- packet_buf_p = (u_int16_t**)packet_buf_vp; /*casting to u_int16_t */\r
-\r
-/*Update the fields in the given grh struct*/\r
- grh_st_p->NxtHdr = NON_RAW_IBA; /* it is static for now */\r
- grh_st_p->PayLen = packet_size - LRH_LEN - GRH_LEN - VCRC_LEN; \r
- /*from the firest byte of the end of the GRH till the VCRC in bytes*/\r
- \r
- start_GRH_p = (u_int8_t*)(*packet_buf_p) - GRH_LEN;\r
-\r
- start_GRH_p[0] = INSERTF(start_GRH_p[0],4,grh_st_p->IPVer,0,4);\r
- start_GRH_p[0] = INSERTF(start_GRH_p[0],0,grh_st_p->TClass,4,4);\r
- start_GRH_p[1] = INSERTF(start_GRH_p[1],4,grh_st_p->TClass,0,4);\r
- start_GRH_p[1] = INSERTF(start_GRH_p[1],0,grh_st_p->FlowLabel,16,4);\r
- start_GRH_p[2] = INSERTF(start_GRH_p[2],0,grh_st_p->FlowLabel,8,8);\r
- start_GRH_p[3] = INSERTF(start_GRH_p[3],0,grh_st_p->FlowLabel,0,8);\r
-\r
-\r
- start_GRH_p[4] = INSERTF(start_GRH_p[4],0,grh_st_p->PayLen,8,8);\r
- start_GRH_p[5] = INSERTF(start_GRH_p[5],0,grh_st_p->PayLen,0,8);\r
-\r
- start_GRH_p[6] = grh_st_p->NxtHdr;\r
- start_GRH_p[7] = grh_st_p->HopLmt;\r
-\r
- memcpy(&(start_GRH_p[8]), grh_st_p->SGID, sizeof(IB_gid_t));\r
- memcpy(&(start_GRH_p[24]), grh_st_p->DGID, sizeof(IB_gid_t));\r
- \r
- (*packet_buf_p) = (u_int16_t*)start_GRH_p;\r
-\r
- return(MT_OK);\r
-}\r
-\r
-/*********************************************************************************/\r
-/* Extract GRH */\r
-/*********************************************************************************/\r
-call_result_t\r
-extract_GRH(IB_GRH_st *grh_st_p, u_int16_t **packet_buf_p)\r
-{\r
- u_int8_t *start_GRH_p;\r
- u_int8_t *end_GRH_p;\r
-\r
-\r
- memset(grh_st_p, 0, sizeof(IB_GRH_st));\r
-\r
- start_GRH_p = (u_int8_t*)(*packet_buf_p);\r
- end_GRH_p = (u_int8_t*)(*packet_buf_p) + GRH_LEN;\r
-\r
- grh_st_p->IPVer = INSERTF(grh_st_p->IPVer,0,start_GRH_p[0],4,4);\r
- grh_st_p->TClass = INSERTF(grh_st_p->TClass,4,start_GRH_p[0],0,4);\r
- grh_st_p->TClass = INSERTF(grh_st_p->TClass,0,start_GRH_p[1],4,4);\r
- grh_st_p->FlowLabel = INSERTF(grh_st_p->FlowLabel,16,start_GRH_p[1],0,4);\r
- grh_st_p->FlowLabel = INSERTF(grh_st_p->FlowLabel,8,start_GRH_p[2],0,8);\r
- grh_st_p->FlowLabel = INSERTF(grh_st_p->FlowLabel,0,start_GRH_p[3],0,8);\r
-\r
- grh_st_p->PayLen = INSERTF(grh_st_p->PayLen,8,start_GRH_p[4],0,8);\r
- grh_st_p->PayLen = INSERTF(grh_st_p->PayLen,0,start_GRH_p[5],0,8);\r
-\r
- grh_st_p->NxtHdr = start_GRH_p[6];\r
- grh_st_p->HopLmt = start_GRH_p[7]; \r
-\r
- memcpy(grh_st_p->SGID, &(start_GRH_p[8]), sizeof(IB_gid_t));\r
- memcpy(grh_st_p->DGID, &(start_GRH_p[24]), sizeof(IB_gid_t));\r
-\r
- \r
- (*packet_buf_p) = (u_int16_t *)end_GRH_p;\r
- /*Updating The packet_puf_p to be at the end of the GRH field*/\r
- return(MT_OK);\r
-}\r
-\r
-\r
-\r
-/*********************************************************************************/\r
-/* Append BTH */\r
-/*********************************************************************************/\r
-call_result_t\r
-append_BTH (IB_BTH_st *bth_st_p, u_int16_t **packet_buf_p,u_int16_t payload_size)\r
-{\r
- u_int8_t *start_BTH_p;\r
-\r
- start_BTH_p = (u_int8_t*)(*packet_buf_p) - BTH_LEN;\r
- /*Assuming that the pointer is BTH_LEN (12) bytes ahead*/\r
- bth_st_p->PadCnt = (IBWORD - (payload_size % IBWORD)) % IBWORD; /*To align to 4 byte boundary*/\r
- bth_st_p->reserved1 = 0 ;\r
- bth_st_p->reserved2 = 0 ;\r
- bth_st_p->TVer = IBA_TRANSPORT_HEADER_VERSION;\r
-\r
- start_BTH_p[0] = INSERTF(start_BTH_p[0],0,bth_st_p->OpCode,0,8);\r
- start_BTH_p[1] = INSERTF(start_BTH_p[1],7,bth_st_p->SE,0,1);\r
- start_BTH_p[1] = INSERTF(start_BTH_p[1],6,bth_st_p->M,0,1);\r
- start_BTH_p[1] = INSERTF(start_BTH_p[1],4,bth_st_p->PadCnt,0,2);\r
- start_BTH_p[1] = INSERTF(start_BTH_p[1],0,bth_st_p->TVer,0,4);\r
- start_BTH_p[2] = INSERTF(start_BTH_p[2],0,bth_st_p->P_KEY,8,8);\r
- start_BTH_p[3] = INSERTF(start_BTH_p[3],0,bth_st_p->P_KEY,0,8);\r
- start_BTH_p[4] = INSERTF(start_BTH_p[4],0,bth_st_p->reserved1,0,8);\r
- start_BTH_p[5] = INSERTF(start_BTH_p[5],0,bth_st_p->DestQP,16,8);\r
- start_BTH_p[6] = INSERTF(start_BTH_p[6],0,bth_st_p->DestQP,8,8);\r
- start_BTH_p[7] = INSERTF(start_BTH_p[7],0,bth_st_p->DestQP,0,8);\r
- start_BTH_p[8] = INSERTF(start_BTH_p[8],7,bth_st_p->A,0,1);\r
- start_BTH_p[8] = INSERTF(start_BTH_p[8],0,bth_st_p->reserved2,0,7);\r
- start_BTH_p[9] = INSERTF(start_BTH_p[9],0,bth_st_p->PSN,16,8);\r
- start_BTH_p[10] = INSERTF(start_BTH_p[10],0,bth_st_p->PSN,8,8);\r
- start_BTH_p[11] = INSERTF(start_BTH_p[11],0,bth_st_p->PSN,0,8);\r
- (*packet_buf_p) = (u_int16_t*)start_BTH_p;/*Update the pointer to the start of the BTH field*/\r
- return(MT_OK);\r
-}\r
-\r
-/*********************************************************************************/\r
-/* Extract BTH */\r
-/*********************************************************************************/\r
-call_result_t\r
-extract_BTH(IB_BTH_st *bth_st_p, u_int16_t **packet_buf_p)\r
-{\r
- u_int8_t *start_BTH_p;\r
- u_int8_t *end_BTH_p;\r
-\r
-\r
- memset(bth_st_p, 0, sizeof(IB_BTH_st));\r
-\r
- start_BTH_p = (u_int8_t*)(*packet_buf_p);\r
- end_BTH_p = (u_int8_t*)(*packet_buf_p) + BTH_LEN;\r
-\r
- bth_st_p->OpCode = INSERTF(bth_st_p->OpCode,0,start_BTH_p[0],0,8);\r
- bth_st_p->SE = INSERTF(bth_st_p->SE,0,start_BTH_p[1],7,1);\r
- bth_st_p->M = INSERTF(bth_st_p->M,0,start_BTH_p[1],6,1);\r
- bth_st_p->PadCnt = INSERTF(bth_st_p->PadCnt,0,start_BTH_p[1],4,2);\r
- bth_st_p->TVer = INSERTF(bth_st_p->TVer,0,start_BTH_p[1],0,4);\r
- bth_st_p->P_KEY = INSERTF(bth_st_p->P_KEY,8,start_BTH_p[2],0,8);\r
- bth_st_p->P_KEY = INSERTF(bth_st_p->P_KEY,0,start_BTH_p[3],0,8);\r
- bth_st_p->reserved1 = INSERTF(bth_st_p->reserved1,0,start_BTH_p[4],0,8);\r
- bth_st_p->DestQP = INSERTF(bth_st_p->DestQP,16,start_BTH_p[5],0,8);\r
- bth_st_p->DestQP = INSERTF(bth_st_p->DestQP,8,start_BTH_p[6],0,8);\r
- bth_st_p->DestQP = INSERTF(bth_st_p->DestQP,0,start_BTH_p[7],0,8);\r
- bth_st_p->A = INSERTF(bth_st_p->A,0,start_BTH_p[8],7,1);\r
- bth_st_p->reserved2 = INSERTF(bth_st_p->reserved2,0,start_BTH_p[8],0,7);\r
- bth_st_p->PSN = INSERTF(bth_st_p->PSN,16,start_BTH_p[9],0,8);\r
- bth_st_p->PSN = INSERTF(bth_st_p->PSN,8,start_BTH_p[10],0,8);\r
- bth_st_p->PSN = INSERTF(bth_st_p->PSN,0,start_BTH_p[11],0,8);\r
-\r
- (*packet_buf_p) = (u_int16_t *)end_BTH_p;\r
- /*Updating The packet_puf_p to be at the end of the DETH field*/\r
- return(MT_OK);\r
-}\r
-\r
-\r
-/*********************************************************************************/\r
-/* Append RETH */\r
-/*********************************************************************************/\r
-call_result_t\r
-append_RETH (IB_RETH_st *reth_st_p, u_int16_t **packet_buf_p)\r
-{\r
- u_int8_t *start_RETH_p;\r
- u_int8_t *start_VA_p;\r
- u_int8_t *start_R_Key_p;\r
- u_int8_t *start_DMALen_p;\r
-\r
- start_RETH_p = (u_int8_t*)(*packet_buf_p) - RETH_LEN;\r
-\r
- start_VA_p = start_RETH_p;/*The first field*/\r
- start_R_Key_p = start_RETH_p + 8; /*1st field 8 byte long*/\r
- start_DMALen_p = start_RETH_p + 12;/*2nd fiels 4 byte + 12 1st*/\r
-\r
- (*((u_int64_t*)start_VA_p)) = MOSAL_cpu_to_be64(reth_st_p->VA); /*64bit field (big endian)*/\r
- (*((u_int32_t*)start_R_Key_p)) = MOSAL_cpu_to_be32(reth_st_p->R_Key);/*32bit field (big endian)*/\r
- (*((u_int32_t*)start_DMALen_p)) = MOSAL_cpu_to_be32(reth_st_p->DMALen);/*32bit field (big e)*/\r
-\r
- (*packet_buf_p) = (u_int16_t *)start_RETH_p;\r
- /*Updating The packet_puf_p to be at the start of the RETH field*/\r
- return(MT_OK);\r
-}\r
-\r
-/*********************************************************************************/\r
-/* Extract RETH */\r
-/*********************************************************************************/\r
-call_result_t\r
-extract_RETH(IB_RETH_st *reth_st_p, u_int16_t **packet_buf_p)\r
-{\r
- u_int8_t *start_RETH_p;\r
- u_int8_t *start_VA_p;\r
- u_int8_t *start_R_Key_p;\r
- u_int8_t *start_DMALen_p;\r
- u_int8_t *end_RETH_p;\r
-\r
- memset(reth_st_p, 0, sizeof(IB_RETH_st));\r
-\r
- start_RETH_p = (u_int8_t*)(*packet_buf_p);\r
- end_RETH_p = (u_int8_t*)(*packet_buf_p) + RETH_LEN;\r
- start_VA_p = start_RETH_p;/*The first field*/\r
- start_R_Key_p = start_RETH_p + 8; /*1st field 8 byte long*/\r
- start_DMALen_p = start_RETH_p + 12;/*2nd fiels 4 byte + 12 1st*/\r
-\r
- reth_st_p->VA = MOSAL_be64_to_cpu(*((u_int64_t*)start_VA_p)); /*64bit field(big endain)*/\r
- reth_st_p->R_Key = MOSAL_be32_to_cpu(*((u_int32_t*)start_R_Key_p)); /*32bit field(big endain)*/\r
- reth_st_p->DMALen = MOSAL_be32_to_cpu(*((u_int32_t*)start_DMALen_p)); /*32bit field(big endain)*/\r
-\r
- (*packet_buf_p) = (u_int16_t *)end_RETH_p;\r
- /*Updating The packet_puf_p to be at the end of the DETH field*/\r
- return(MT_OK);\r
-}\r
-/*********************************************************************************/\r
-/* Append AETH */\r
-/*********************************************************************************/\r
-call_result_t\r
-append_AETH (IB_AETH_st *aeth_st_p, u_int16_t **packet_buf_p)\r
-{\r
- u_int8_t *start_AETH_p;\r
-\r
- start_AETH_p = (u_int8_t*)(*packet_buf_p) - AETH_LEN;\r
-\r
- start_AETH_p[0] = INSERTF(start_AETH_p[0],0,aeth_st_p->Syndrome,0,8);/*8 bitf (big endain)*/\r
-\r
- start_AETH_p[1] = INSERTF(start_AETH_p[1],0,aeth_st_p->MSN,16,8);/*24 bitf (big endain)*/\r
- start_AETH_p[2] = INSERTF(start_AETH_p[2],0,aeth_st_p->MSN,8,8); /*it is dangerus to use bm*/\r
- start_AETH_p[3] = INSERTF(start_AETH_p[3],0,aeth_st_p->MSN,0,8);\r
-\r
- (*packet_buf_p) = (u_int16_t *)start_AETH_p;\r
- /*Updating The packet_puf_p to be at the start of the AETH field*/\r
- return(MT_OK);\r
-}\r
-\r
-/*********************************************************************************/\r
-/* Extract AETH */\r
-/*********************************************************************************/\r
-call_result_t\r
-extract_AETH (IB_AETH_st *aeth_st_p, u_int16_t **packet_buf_p)\r
-{\r
- u_int8_t *start_AETH_p;\r
- u_int8_t *end_AETH_p;\r
- u_int8_t *start_MSN_p;\r
- u_int32_t temp32;\r
-\r
- memset(aeth_st_p, 0, sizeof(IB_AETH_st)); \r
- \r
- start_AETH_p = (u_int8_t*)(*packet_buf_p);\r
- start_MSN_p = start_AETH_p + 1;/*2nd field 1 byte after Syndrome*/\r
- end_AETH_p = (u_int8_t*)(*packet_buf_p) + AETH_LEN;\r
-\r
- aeth_st_p->Syndrome = start_AETH_p[0];/*8bit field (big endian)*/\r
-\r
- temp32 = *((u_int32_t*)start_MSN_p);/*24bit field (big endian)*/\r
-\r
-#ifdef MT_LITTLE_ENDIAN\r
- temp32 <<= 8;\r
- \r
-#else\r
- temp32 >>= 8;\r
-#endif\r
-\r
- aeth_st_p->MSN = MOSAL_be32_to_cpu(temp32);\r
-\r
- (*packet_buf_p) = (u_int16_t *)end_AETH_p;\r
- /*Updating The packet_puf_p to be at the start of the AETH field*/\r
- return(MT_OK);\r
-}\r
-\r
-/*********************************************************************************/\r
-/* Append DETH */\r
-/*********************************************************************************/\r
-call_result_t\r
-append_DETH (IB_DETH_st *deth_st_p, u_int16_t **packet_buf_p)\r
-{\r
- u_int8_t *start_DETH_p;\r
- u_int8_t *start_Q_Key_p;\r
-\r
- start_DETH_p = (u_int8_t*)(*packet_buf_p) - DETH_LEN;\r
- start_Q_Key_p = start_DETH_p;\r
-\r
- (*((u_int32_t*)start_Q_Key_p)) = MOSAL_cpu_to_be32(deth_st_p->Q_Key); /*32bit field (big endian)*/\r
-\r
- start_DETH_p[4] = deth_st_p->reserved1;/*8bit field (big endian)*/\r
-\r
- start_DETH_p[5] = INSERTF(start_DETH_p[5],0,deth_st_p->SrcQP,16,8);/*24bit field (big endian)*/\r
- start_DETH_p[6] = INSERTF(start_DETH_p[6],0,deth_st_p->SrcQP,8,8);\r
- start_DETH_p[7] = INSERTF(start_DETH_p[7],0,deth_st_p->SrcQP,0,8);\r
-\r
- (*packet_buf_p) = (u_int16_t *)start_DETH_p;\r
- /*Updating The packet_puf_p to be at the start of the DETH field*/\r
- return(MT_OK);\r
-}\r
-\r
-/*********************************************************************************/\r
-/* Extract DETH */\r
-/*********************************************************************************/\r
-call_result_t\r
-extract_DETH(IB_DETH_st *deth_st_p, u_int16_t **packet_buf_p)\r
-{\r
- u_int8_t *start_DETH_p;\r
- u_int8_t *end_DETH_p;\r
- u_int8_t *start_SrcQP_p;\r
- u_int32_t temp32;\r
-\r
- memset(deth_st_p, 0, sizeof(IB_DETH_st)); \r
-\r
-\r
- start_DETH_p = (u_int8_t*)(*packet_buf_p);\r
- start_SrcQP_p = start_DETH_p + 5; /*The start of the SrcQP field*/\r
- end_DETH_p = start_DETH_p + DETH_LEN;\r
-\r
- deth_st_p->Q_Key = MOSAL_be32_to_cpu(*((u_int32_t*)start_DETH_p));/*32bit field (big endian)*/\r
- deth_st_p->reserved1 = *((u_int8_t*)(start_DETH_p + 4));/*8bit field (big endian)*/\r
-\r
- temp32 = *((u_int32_t*)start_SrcQP_p); /*24bit field (big endian)*/\r
-\r
-#ifdef MT_LITTLE_ENDIAN\r
- MTL_TRACE('5', "\nLittle Endian\n"); \r
- temp32 <<= 8;\r
-#else\r
- temp32 >>= 8;\r
- MTL_TRACE('5', "\nBig Endian \n"); \r
-#endif\r
-\r
- deth_st_p->SrcQP = MOSAL_be32_to_cpu(temp32);\r
-\r
- (*packet_buf_p) = (u_int16_t *)end_DETH_p;\r
- /*Updating The packet_puf_p to be at the end of the DETH field*/\r
- return(MT_OK);\r
-}\r
-\r
-/*********************************************************************************/\r
-/* Append ImmDt */\r
-/*********************************************************************************/\r
-call_result_t\r
-append_ImmDt (IB_ImmDt_st *ImmDt_st_p, u_int16_t **packet_buf_p)\r
-{\r
- u_int8_t *start_ImmDt_p;\r
- \r
- start_ImmDt_p = (u_int8_t*)(*packet_buf_p) - ImmDt_LEN;\r
- (*((u_int32_t*)start_ImmDt_p)) = MOSAL_cpu_to_be32(ImmDt_st_p->ImmDt); /*32bit field (big endian)*/\r
- \r
- (*packet_buf_p) = (u_int16_t *)start_ImmDt_p;\r
- /*Updating The packet_puf_p to be at the start of the ImmDt field*/\r
- return(MT_OK);\r
-}\r
- \r
-/*********************************************************************************/\r
-/* Extract ImmDt */\r
-/*********************************************************************************/\r
-call_result_t\r
-extract_ImmDt(IB_ImmDt_st *ImmDt_st_p, u_int16_t **packet_buf_p)\r
-{\r
- u_int8_t *start_ImmDt_p;\r
- u_int8_t *end_ImmDt_p;\r
-\r
- memset(ImmDt_st_p, 0, sizeof(IB_ImmDt_st)); \r
- \r
- start_ImmDt_p = (u_int8_t*)(*packet_buf_p);\r
- end_ImmDt_p = start_ImmDt_p + ImmDt_LEN;\r
- \r
- ImmDt_st_p->ImmDt = MOSAL_be32_to_cpu(*((u_int32_t*)start_ImmDt_p));/*32bit field (big endian)*/\r
- \r
- (*packet_buf_p) = (u_int16_t *)end_ImmDt_p;\r
- /*Updating The packet_puf_p to be at the end of the ImmDt field*/\r
- return(MT_OK);\r
-} \r
-\r
-/*********************************************************************************/\r
-/* Append ICRC */\r
-/*********************************************************************************/\r
-call_result_t\r
-append_ICRC(u_int16_t *start_ICRC, u_int32_t ICRC)\r
-{\r
- *((u_int32_t*)start_ICRC) = MOSAL_cpu_to_le32(ICRC);\r
- return(MT_OK);\r
-}\r
-\r
-/*********************************************************************************/\r
-/* Extract ICRC */\r
-/*********************************************************************************/\r
-call_result_t\r
-extract_ICRC(u_int16_t *start_ICRC, u_int32_t *ICRC)\r
-{\r
- *ICRC = MOSAL_le32_to_cpu(*((u_int32_t*)start_ICRC));\r
- return(MT_OK);\r
-}\r
-\r
-/*********************************************************************************/\r
-/* Append VCRC */\r
-/*********************************************************************************/\r
-call_result_t\r
-append_VCRC(u_int16_t *start_VCRC, u_int16_t VCRC)\r
-{\r
- *((u_int16_t*)start_VCRC) = MOSAL_cpu_to_le16(VCRC);\r
- return(MT_OK);\r
-}\r
-\r
-/*********************************************************************************/\r
-/* Extract VCRC */\r
-/*********************************************************************************/\r
-call_result_t\r
-extract_VCRC(u_int16_t *start_VCRC, u_int16_t *VCRC)\r
-{\r
- *VCRC = MOSAL_le16_to_cpu(*((u_int16_t*)start_VCRC));\r
- return(MT_OK);\r
-}\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_PACKET_APPEND_H\r
-#define H_PACKET_APPEND_H\r
-\r
-/* Layers Includes */ \r
-#include <mtl_types.h>\r
-\r
-/*******************/\r
-\r
-#ifdef __WIN__\r
-#include <string.h>\r
-#endif\r
-\r
-#if !defined(__DARWIN__) && defined(__LINUX__) && !defined(__KERNEL__)\r
- #include <endian.h>\r
-#endif\r
-\r
-#if defined(VXWORKS_OS) && defined(MT_BIG_ENDIAN)\r
-#define __cpu_to_le32(x) (x)\r
-#define __cpu_to_le16(x) (x)\r
-#endif \r
-\r
-#define IBA_TRANSPORT_HEADER_VERSION 0\r
-/*Define of all fields length*/\r
-#define IBWORD 4 /* 4 bytes */\r
-#define LRH_LEN 8 /* (LRH_LEN = 8 byte) */\r
-#define RWH_LEN 4\r
-#define GRH_LEN 40\r
-#define BTH_LEN 12\r
-#define RDETH_LEN 4\r
-#define DETH_LEN 8\r
-#define RETH_LEN 16\r
-#define AETH_LEN 4\r
-#define ImmDt_LEN 4\r
-#define AtomETH_LEN 28\r
-#define AtomAETH_LEN 8\r
-#define ICRC_LEN 4\r
-#define VCRC_LEN 2\r
-\r
-/*Define all transport layer packet length with out LRH or GRH*/\r
-\r
-/********************* Reliable Connection (RC) *************************/\r
-\r
-#define RC_SEND_FIRST_LEN (BTH_LEN)\r
-#define RC_SEND_MIDDLE_LEN (BTH_LEN)\r
-#define RC_SEND_LAST_LEN (BTH_LEN)\r
-#define RC_SEND_ONLY_LEN (BTH_LEN) /*need to write all the relavent packets*/\r
-#define RC_WRITE_ONLY_LEN (BTH_LEN + RETH_LEN)\r
-#define RC_WRITE_FIRST_LEN (BTH_LEN + RETH_LEN)\r
-#define RC_WRITE_MIDDLE_LEN (BTH_LEN)\r
-#define RC_WRITE_LAST_LEN (BTH_LEN)\r
-#define RC_READ_REQ_LEN (BTH_LEN + RETH_LEN)\r
-#define RC_READ_RESP_FIRST_LEN (BTH_LEN + AETH_LEN)\r
-#define RC_READ_RESP_MIDDLE_LEN (BTH_LEN)\r
-#define RC_READ_RESP_LAST_LEN (BTH_LEN + AETH_LEN) \r
-#define RC_READ_RESP_ONLY_LEN (BTH_LEN + AETH_LEN)\r
-#define RC_ACKNOWLEDGE_LEN (BTH_LEN + AETH_LEN)\r
-\r
-/********************* Unreliable Connection (UC) ************************/\r
-\r
-\r
-/********************* Reliable Datagram (RD) ****************************/\r
-\r
-\r
-/********************* Unreliable Datagram (UD) ***************************/\r
-\r
-#define UD_SEND_ONLY_LEN (BTH_LEN + DETH_LEN)\r
-\r
-/*Define Link Next Header Definition */\r
-enum {\r
- RAW = 0x0, /* |LRH|... (Etertype)*/\r
- IP_NON_IBA_TRANS = 0x1, /* |LRH|GRH|... */\r
- IBA_LOCAL = 0x2, /* |LRH|BTH|... */\r
- IBA_GLOBAL = 0x3 /* |LRH|GRH|BTH|... */\r
-}; \r
-typedef u_int32_t LNH_t;\r
- \r
-typedef enum{\r
- NON_RAW_IBA = 0x1B /* |LRH|GRH|BTH|...*/\r
- /* TBD IETF RFC 1700 et.seq*/\r
- /* All the rest is ipver6 headers*/\r
-} NxtHdr_t;\r
- \r
-\r
-typedef enum{\r
- FIRST_PACKET=0,\r
- MIDDLE_PACKET=1,\r
- LAST_PACKET=2\r
-} IB_pkt_place;\r
-\r
-/**************************************** fields structures define *******************************/ \r
-typedef struct IB_LRH_st IB_LRH_st;\r
-\r
-struct IB_LRH_st{ /* ***** LRH ***** Local Route Header(8 bytes)*/\r
- u_int8_t VL; /*"Only 4 LS-bits"The virtual lane that the packet is using */\r
- u_int8_t LVer; /*"Only 4 LS-bits"Link level protocol of the packet*/\r
- u_int8_t SL; /*"Only 4 LS-bits"Service level requested within the subnet*/\r
- u_int8_t reserved1; /*"Only 2 LS-bits"Transmitted as 0,ignored on receive. **internally modified** */\r
- u_int8_t LNH; /*"Only 2 LS-bits"Identifies the headers that follow the LRH. **internally modified** */\r
- u_int16_t DLID; /*The destination port and path on the local subnet*/\r
- u_int8_t reserved2; /*"Only 5 LS-bits"Transmitted as 0,ignored on receive.**internally modified** */\r
- u_int16_t PktLen; /*"Only 11 LS-bits"The size of tha packet in four-byte words. **internally modified** */\r
- u_int16_t SLID; /*The source port (injection point) on the local subnet*/\r
- };\r
-\r
-typedef struct IB_GRH_st IB_GRH_st;\r
-\r
-struct IB_GRH_st{ /* **** GRH **** Global Route Header(40 bytes)*/\r
- u_int8_t IPVer; /*"Only 4 LS-bits"The version og the GRH*/\r
- u_int8_t TClass; /*Used by IBA to communicate global service level*/\r
- u_int32_t FlowLabel; /*"Only 20 LS-bits"Sequences of packets requiring special handl*/\r
- u_int16_t PayLen; /*The length of the packet in bytes **internally modified** */\r
- u_int8_t NxtHdr; /*Identifies the headers that follow the GRH*/\r
- u_int8_t HopLmt; /*Bound on the number of hops between subnets*/\r
- u_int8_t SGID[16]; /*Global indentifier for the source port*/\r
- u_int8_t DGID[16]; /*Global indentifier for the detination port*/\r
-};\r
-\r
-typedef struct IB_BTH_st IB_BTH_st;\r
-\r
-struct IB_BTH_st{ /* **** BTH **** Base Transport Header (12 bytes)*/\r
- u_int8_t OpCode; /*IBA packet type and which extentions follows **internally modified** */\r
- u_int8_t SE; /*"Only 1 LS-bit"If an event sould be gen by responder or not*/\r
- u_int8_t M; /*"Only 1 LS-bit"Communication migration state*/\r
- u_int8_t PadCnt; /*"Only 2 LS-bits"Number of bytes that align to 4 byte boundary **internally modified** */\r
- u_int8_t TVer; /*"Only 4 LS-bits"IBA transport headers version. **internally modified** */\r
- u_int16_t P_KEY; /*Logical partition associated with this packet*/\r
- u_int8_t reserved1; /*Transmitted as 0,ignored on receive. Not included in the icrc. **internally modified** */\r
- u_int32_t DestQP; /*"Only 24 LS-bits"Destination work queu pair number*/\r
- u_int8_t A; /*"Only 1 LS-bit"If an ack should be returnd by the responder*/\r
- u_int8_t reserved2; /*"only 7 LS-bits"Transmitted as 0,ignored .included in icrc. **internally modified** */\r
- u_int32_t PSN; /*"Only 24 LS-bits"detect a missing or duplicate packet*/\r
-};\r
-\r
-typedef struct IB_RDETH_st IB_RDETH_st;\r
-\r
-struct IB_RDETH_st{ /* **** RDETH **** (4 bytes)*/\r
- /*Reliable Datagram Extended Transport Header*/\r
- u_int8_t reserved1; /*Transmitted as 0,ignored on receive.*/\r
- u_int32_t EECnxt; /*"Only 24 LS-bits"Which end to end context for this packet*/\r
-};\r
-\r
-typedef struct IB_DETH_st IB_DETH_st;\r
-\r
-struct IB_DETH_st{ /* **** DETH ****(8 bytes)*/\r
- /*Datagram Extended Transport Header */\r
- u_int32_t Q_Key; /*For an authorize access to destination queue*/\r
- u_int8_t reserved1; /*ransmitted as 0,ignored on receive.*/\r
- u_int32_t SrcQP; /*"Only 24 LS-bits"Work queu nuber at the source*/\r
-};\r
- \r
-typedef struct IB_RETH_st IB_RETH_st;\r
-\r
-struct IB_RETH_st{ /* **** RETH ****(16 bytes)*/\r
- /*RDMA Extended Transport Header */\r
- u_int64_t VA; /*Virtual address of the RDMA operation*/\r
- u_int32_t R_Key; /*Remote key that authorize access for the RDMA operation*/\r
- u_int32_t DMALen; /*The length of the DMA operation*/\r
-};\r
-\r
-typedef struct IB_AtomicETH_st IB_AtomicETH_st;\r
-\r
-struct IB_AtomicETH_st{ /* **** AtomicETH ****(28 bytes)*/\r
- /*Atomic Extended Transport Header */\r
- u_int64_t VA; /*Remote virtual address */\r
- u_int32_t R_Key; /*Remote key that authorize access to the remote virtual address*/\r
- u_int64_t SwapDt; /*An operand in atomic operations*/\r
- u_int64_t CmpDt; /*An operand in cmpswap atomic operation*/\r
-};\r
-\r
-typedef struct IB_AETH_st IB_AETH_st;\r
-\r
-struct IB_AETH_st{ /* **** AETH ****(4 bytes)*/\r
- /*ACK Extended Transport Header */\r
- u_int8_t Syndrome; /*Indicates if NAK or ACK and additional info about ACK & NAK*/\r
- u_int32_t MSN; /*"Only 24 Ls-bit"Sequence number of the last message comleted*/\r
-}; \r
-\r
-typedef struct IB_AtomicAckETH_st IB_AtomicAckETH_st;\r
-\r
-struct IB_AtomicAckETH_st{ /* **** AtomicAckETH ****(8 bytes)*/\r
- /* Atomic ACK Extended Transport Header */\r
- u_int64_t OrigRemDt; /*Return oprand in atomic operation and contains the data*/\r
- /*in the remote memory location before the atomic operation*/\r
-};\r
-\r
-typedef struct IB_ImmDt_st IB_ImmDt_st;\r
-\r
-struct IB_ImmDt_st{ /* **** Immediate Data **** (4 bytes)*/\r
- /* Contains the additional data that is placed in the */\r
- u_int32_t ImmDt; /* received Completion Queue Element (CQE). */\r
- /* The ImmDt is Only in Send or RDMA-Write packets. */\r
-}; \r
-\r
-typedef struct IB_PKT_st IB_PKT_st;\r
-\r
-struct IB_PKT_st{ /*IB packet structure Analayze structure*/\r
- IB_LRH_st *lrh_st_p;\r
- IB_GRH_st *grh_st_p;\r
- IB_BTH_st *bth_st_p;\r
- IB_RDETH_st *rdeth_st_p;\r
- IB_DETH_st *deth_st_p;\r
- IB_RETH_st *reth_st_p;\r
- IB_AtomicETH_st *atomic_eth_st_p;\r
- IB_AETH_st *aeth_st_p;\r
- IB_AtomicAckETH_st *atomic_acketh_st_p;\r
- IB_ImmDt_st *immdt_st_p;\r
- u_int16_t packet_size;\r
- u_int16_t *payload_buf;\r
- u_int16_t payload_size;\r
-};\r
-\r
-\r
-/*Start of function declarations*/\r
-/******************************************************************************\r
- * Function: append_LRH\r
- *\r
- * Description: This function is appending LRH to IB packets .\r
- * To use this function you must have a LRH struct,\r
- * with all the detailes to create the wanted packet.\r
- * and an allocated area with free space for the LRH field\r
- * The function Ignores the OpCode,PadCnt,reserved1,reserved2 fields it overwrite\r
- * The given information.\r
- *\r
- * Parameters:\r
- * lrh_st_p(IN) IB_LRH_st *\r
- * Link next header .\r
- * packet_size (out) u_int16_t.\r
- * Full packet size include ICRC VCRC;\r
- * packet_buf_p(out) u_int16_t **\r
- * pointer to the pointer of the full packet .\r
- * The function will return the pointer 8 bytes back).\r
- * LNH ( out) LNH_t\r
- * Link next header IB local , global , RAW ...\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR if no packet was generated.\r
- *****************************************************************************/\r
-call_result_t\r
-append_LRH (IB_LRH_st *lrh_st_p, u_int16_t packet_size,\r
- u_int16_t **packet_buf_p,LNH_t LNH);\r
-\r
-/******************************************************************************\r
- * Function: extract_LRH\r
- *\r
- * Description: This function is extractinging the LRH from the IB packets .\r
- * The function will update all the members in the IB_LRH struct.\r
- *\r
- * Parameters:\r
- * lrh_st_p(out) IB_LRH_st *\r
- * Local route header of the generated packet.\r
- * packet_buf_p(out) u_int16_t **\r
- * pointer to the pointer of the full packet .\r
- * (The function will return the pointer 8 bytes forward).\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR\r
- *****************************************************************************/\r
-call_result_t\r
-extract_LRH(IB_LRH_st *lrh_st_p, u_int16_t **packet_buf_p);\r
-\r
-/******************************************************************************\r
- * Function: append_GRH\r
- *\r
- * Description: This function is appending GRH to IB packets .\r
- * To use this function you must have a GRH struct,\r
- * with all the detailes to create the wanted packet.\r
- * and an allocated area with free space for the GRH field\r
- * Note : The function Ignores the PayLen and NxtHdr fields it overwrite\r
- * The given information.\r
- *\r
- *\r
- * Parameters:\r
- * grh_st_p(IN) IB_GRH_st *\r
- * Global Route Header.\r
- * packet_size (out) u_int16_t.\r
- * Full packet size include ICRC VCRC;\r
- * packet_buf_p(out) u_int16_t **\r
- * pointer to the pointer of the full packet .\r
- * The function will return the pointer 40 bytes back).\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR if the field was not appended.\r
- *****************************************************************************/\r
-call_result_t\r
-append_GRH (IB_GRH_st *grh_st_p, u_int16_t packet_size,\r
- u_int16_t **packet_buf_vp);\r
-\r
-/******************************************************************************\r
- * Function: extract_GRH\r
- *\r
- * Description: This function is extractinging the GRH from the IB packets .\r
- * The function will update all the members in the IB_GRH struct.\r
- *\r
- * Parameters:\r
- * grh_st_p(out) IB_GRH_st *\r
- * Global route header of the generated packet.\r
- * packet_buf_p(out) u_int16_t **\r
- * pointer to the pointer of the full packet .\r
- * (The function will return the pointer 40 bytes forward).\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR\r
- *****************************************************************************/\r
-call_result_t\r
-extract_GRH(IB_GRH_st *grh_st_p, u_int16_t **packet_buf_p);\r
-\r
-/******************************************************************************\r
- * Function: append_BTH\r
- *\r
- * Description: This function is appending BTH to IB packets .\r
- * To use this function you must have a BTH struct,\r
- * with all the detailes to create the wanted packet.\r
- * and an allocated area with free space for the BTH field\r
- * The function Ignores the OpCode,PadCnt,reserved1,reserved2 fields it overwrite\r
- * The given information.\r
- *\r
- * Parameters:\r
- * bth_st_p(out) IB_BTH_st *\r
- * Base trasport header of the generated packet. (the func ignores the reserved1/2 fields).\r
- * packet_buf_p(out) u_int16_t **\r
- * pointer to the pointer of the full packet .\r
- * The function will return the pointer 12 bytes back).\r
- * payload_size(in) u_int16_t\r
- * The payload_size in bytes for calc the PadCnt.\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR if no packet was generated.\r
- *****************************************************************************/\r
-call_result_t\r
-append_BTH (IB_BTH_st *bth_st_p, u_int16_t **packet_buf_p, u_int16_t payload_size);\r
-\r
-/******************************************************************************\r
- * Function: extract_BTH\r
- *\r
- * Description: This function is extractinging the BTH from the IB packets .\r
- * The function will update all the members in the IB_BTH struct.\r
- *\r
- * Parameters:\r
- * bth_st_p(out) IB_BTH_st *\r
- * Base trasport header of the generated packet.\r
- * packet_buf_p(out) u_int16_t **\r
- * pointer to the pointer of the full packet .\r
- * (The function will return the pointer 12 bytes forward).\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR\r
- *****************************************************************************/\r
-call_result_t\r
-extract_BTH(IB_BTH_st *bth_st_p, u_int16_t **packet_buf_p);\r
-\r
-/******************************************************************************\r
- * Function: append_RETH\r
- *\r
- * Description: This function is appending RETH to IB packets .\r
- * To use this function you must have a RETH struct,\r
- * with all the detailes to create the wanted packet.\r
- * and an allocated area with a free space for the RETH field.\r
- *\r
- * Parameters:\r
- * reth_st_p(in) IB_RETH_st *\r
- * RDMA Extended Transport Header.\r
- * packet_buf_p(out) u_int16_t **\r
- * pointer to the pointer of the full packet .\r
- * The function will move the pointer 16 bytes back).\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR if no packet was generated.\r
- *****************************************************************************/\r
-call_result_t\r
-append_RETH (IB_RETH_st *reth_st_p, u_int16_t **packet_buf_p);\r
-\r
-/******************************************************************************\r
- * Function: extract_RETH\r
- *\r
- * Description: This function is extractinging the RETH from the IB packets .\r
- * The function will update all the members in the IB_RETH struct.\r
- *\r
- * Parameters:\r
- * reth_st_p(out) IB_RETH_st *\r
- * RDMA Extended Trasport header of the generated packet.\r
- * packet_buf_p(out) u_int16_t **\r
- * pointer to the pointer of the full packet .\r
- * (The function will return the pointer 16 bytes forward).\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR\r
- *****************************************************************************/\r
-call_result_t\r
-extract_RETH(IB_RETH_st *reth_st_p, u_int16_t **packet_buf_p);\r
-\r
-/******************************************************************************\r
- * Function: append_AETH\r
- *\r
- * Description: This function is appending AETH to IB packets .\r
- * To use this function you must have a AETH struct,\r
- * with all the detailes to create the wanted packet.\r
- * and an allocated area with a free space for the AETH field.\r
- *\r
- * Parameters:\r
- * aeth_st_p(in) IB_AETH_st *\r
- * ACK Extended Trasport Header.\r
- * packet_buf_p(out) u_int16_t **\r
- * pointer to the pointer of the full packet .\r
- * (The function will move the pointer 4 bytes back).\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR if no packet was generated.\r
- *****************************************************************************/\r
-call_result_t\r
-append_AETH (IB_AETH_st *aeth_st_p, u_int16_t **packet_buf_p);\r
-\r
-/******************************************************************************\r
- * Function: extract_AETH\r
- *\r
- * Description: This function is extractinging the AETH from the IB packets .\r
- * The function will update all the members in the IB_AETH struct.\r
- *\r
- * Parameters:\r
- * aeth_st_p(out) IB_AETH_st *\r
- * ACK Extended Trasport header of the generated packet.\r
- * packet_buf_p(out) u_int16_t **\r
- * pointer to the pointer of the full packet .\r
- * (The function will return the pointer 4 bytes forward).\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR\r
- *****************************************************************************/\r
-call_result_t\r
-extract_AETH (IB_AETH_st *aeth_st_p, u_int16_t **packet_buf_p);\r
-\r
-/*****************************************************************************/\r
-/* From this point the functiom is Datagram */\r
-/*****************************************************************************/\r
-\r
-/******************************************************************************\r
- * Function: append_DETH\r
- *\r
- * Description: This function is appending DETH to IB packets .\r
- * To use this function you must have a DETH struct,\r
- * with all the detailes to create the wanted packet.\r
- * and an allocated area with a free space for the DETH field.\r
- *\r
- * Parameters:\r
- * deth_st_p(in) IB_DETH_st *\r
- * Datagram Extended Trasport Header. (the func ignores the reserved1 field).\r
- * packet_buf_p(out) u_int16_t **\r
- * pointer to the pointer of the full packet .\r
- * (The function will move the pointer 8 bytes back).\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR .\r
- *****************************************************************************/\r
-call_result_t\r
-append_DETH (IB_DETH_st *deth_st_p, u_int16_t **packet_buf_p);\r
-\r
-/******************************************************************************\r
- * Function: extract_DETH\r
- *\r
- * Description: This function is extractinging the DETH from the IB packets .\r
- * The function will update all the members in the IB_DETH struct.\r
- *\r
- * Parameters:\r
- * deth_st_p(out) IB_DETH_st *\r
- * Datagram Extended Trasport header of the generated packet.\r
- * packet_buf_p(out) u_int16_t **\r
- * pointer to the pointer of the full packet .\r
- * (The function will return the pointer 8 bytes forward).\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR\r
- *****************************************************************************/\r
-call_result_t\r
-extract_DETH(IB_DETH_st *deth_st_p, u_int16_t **packet_buf_p);\r
-\r
-/******************************************************************************\r
- * Function: append_ImmDt\r
- *\r
- * Description: This function is appending ImmDt to IB packets .\r
- * To use this function you must have a ImmDt struct,\r
- * with all the detailes to create the wanted packet.\r
- * and an allocated area with a free space for the ImmDt field.\r
- *\r
- * Parameters:\r
- * ImmDt_st_p(in) IB_ImmDt_st *\r
- * Contains the additional data of the generated packet.\r
- * packet_buf_p(out) u_int16_t **\r
- * pointer to the pointer of the full packet .\r
- * (The function will move the pointer 8 bytes back).\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR .\r
- *****************************************************************************/ \r
-call_result_t\r
-append_ImmDt(IB_ImmDt_st *ImmDt_st_p, u_int16_t **packet_buf_p); \r
-\r
-/******************************************************************************\r
- * Function: extract_ImmDt\r
- *\r
- * Description: This function is extractinging the ImmDt from the IB packets .\r
- * The function will update all the members in the IB_ImmDt struct.\r
- *\r
- * Parameters:\r
- * ImmDt_st_p(out) IB_ImmDt_st *\r
- * Contains the additional data of the generated packet.\r
- * packet_buf_p(out) u_int16_t **\r
- * pointer to the pointer of the full packet .\r
- * (The function will return the pointer 4 bytes forward).\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR\r
- *****************************************************************************/\r
-call_result_t\r
-extract_ImmDt(IB_ImmDt_st *ImmDt_st_p, u_int16_t **packet_buf_p); \r
-\r
- /******************************************************************************\r
- * Function: append_ICRC\r
- *\r
- * Description: This function is appending the ICRC to the IB packets .\r
- *\r
- * Parameters:\r
- * start_ICRC(in) u_int16_t *\r
- * pointer to the start of the ICRC field\r
- * ICRC(in) u_int32_t\r
- * The ICRC to insert\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR\r
- *****************************************************************************/\r
-call_result_t\r
-append_ICRC(u_int16_t *start_ICRC, u_int32_t ICRC);\r
-\r
- /******************************************************************************\r
- * Function: V\r
- *\r
- * Description: This function is extractinging the ICRC from the IB packets .\r
- *\r
- * Parameters:\r
- * start_ICRC(in) u_int16_t *\r
- * pointer to the start of the ICRC field\r
- * ICRC(out) u_int32_t *\r
- * The ICRC to extract\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR\r
- *****************************************************************************/\r
-call_result_t\r
-extract_ICRC(u_int16_t *start_ICRC, u_int32_t *ICRC);\r
-\r
- /******************************************************************************\r
- * Function: append_VCRC\r
- *\r
- * Description: This function is appending the VCRC to the IB packets .\r
- *\r
- * Parameters:\r
- * start_VCRC(in) u_int16_t *\r
- * pointer to the start of the VCRC field\r
- * VCRC(in) u_int32_t\r
- * The VCRC to insert\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR\r
- *****************************************************************************/\r
-call_result_t\r
-append_VCRC(u_int16_t *start_VCRC, u_int16_t VCRC);\r
-\r
-/******************************************************************************\r
- * Function: extract_ICRC\r
- *\r
- * Description: This function is extractinging the ICRC from the IB packets .\r
- *\r
- * Parameters:\r
- * start_ICRC(in) u_int16_t *\r
- * pointer to the start of the ICRC field\r
- * ICRC(out) u_int32_t *\r
- * The ICRC to extract\r
- *\r
- * Returns:\r
- * call_result_t\r
- * MT_OK,\r
- * MT_ERROR\r
- *****************************************************************************/\r
-call_result_t\r
-extract_VCRC(u_int16_t *start_VCRC, u_int16_t *VCRC);\r
-\r
-\r
-#endif /* H_PACKET_APPEND_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-/***************************/\r
-#ifndef MT_KERNEL\r
-\r
- #include <stdio.h>\r
- #include <stdlib.h>\r
-\r
-#endif /* MT_KERNEL */ \r
-\r
-/* MPGA Includes */ \r
-#include <packet_utilities.h>\r
-#include <mpga.h>\r
-#include <packet_append.h>\r
-#include <internal_functions.h>\r
-/***************************/\r
-\r
-#define FREE_PKT_FIELD(_parm) if ( _parm != NULL ) FREE(_parm) \r
-#define BYTES_IN_LINE 4\r
-\r
-/*************************************************************************************/\r
-/* print packet */\r
-/*************************************************************************************/\r
-void\r
-MPGA_print_pkt( u_int8_t *packet_buf_p, u_int16_t packet_size)\r
-{\r
- int index = 0;\r
- int pad = 0;\r
- int gap = 0;\r
- pad = packet_size % BYTES_IN_LINE ;\r
- gap = (packet_size / BYTES_IN_LINE) + 1 ;\r
- packet_size = (packet_size / BYTES_IN_LINE) + 1 ;\r
- MTL_TRACE('1', "\n Packet \n ----------------------------------------------------\n");\r
-\r
- while(packet_size--){\r
- MTL_TRACE('1', "\b %d) \b 0x%02X\t %d) 0x%02X\t %d) 0x%02X\t %d) 0x%02X \n",index, packet_buf_p[index],\r
- index+gap, packet_buf_p[index+gap], index+(2*gap), packet_buf_p[index+(2*gap)],\r
- index+(3*gap), packet_buf_p[index+(3*gap)]);\r
- if(packet_size == pad){\r
- index++;\r
- while(pad--){\r
- MTL_TRACE('1', " %d) 0x%02X\t %d) 0x%02X\t %d) 0x%02X \n",index, packet_buf_p[index],\r
- index+gap, packet_buf_p[index+gap], index+(2*gap), packet_buf_p[index+(2*gap)]);\r
- index++;\r
- }\r
- packet_size = 0;\r
- }\r
- index++;\r
- }\r
-}\r
-\r
-/*************************************************************************************/\r
-/* FREE IB_PKT_st */\r
-/*************************************************************************************/\r
-call_result_t\r
-MPGA_free_pkt_st_fields(IB_PKT_st *pkt_st_p)\r
-{\r
- FREE_PKT_FIELD(pkt_st_p->lrh_st_p);\r
- FREE_PKT_FIELD(pkt_st_p->grh_st_p);\r
- FREE_PKT_FIELD(pkt_st_p->bth_st_p);\r
- FREE_PKT_FIELD(pkt_st_p->rdeth_st_p);\r
- FREE_PKT_FIELD(pkt_st_p->deth_st_p);\r
- FREE_PKT_FIELD(pkt_st_p->reth_st_p);\r
- FREE_PKT_FIELD(pkt_st_p->atomic_eth_st_p);\r
- FREE_PKT_FIELD(pkt_st_p->aeth_st_p);\r
- FREE_PKT_FIELD(pkt_st_p->atomic_acketh_st_p);\r
-\r
- /*FREE_PKT_FIELD(pkt_st_p->payload_buf_p);*/\r
- /*No need to free the payload it is a pointer to the packet payload the user must free himself*/\r
- return(MT_OK);\r
-}\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#ifndef H_PACKET_UTILITIES_H\r
-#define H_PACKET_UTILITIES_H\r
-\r
-/**************************************/\r
-#ifndef MT_KERNEL\r
-\r
- #include <stdio.h>\r
- #include <stdlib.h>\r
-\r
-#endif /* MT_KERNEL */ \r
-\r
-/* MPGA Includes */ \r
-#include <mpga.h>\r
-#include <packet_append.h>\r
-/**************************************/\r
-\r
-\r
-/******************************************************************************\r
- * Function: Print Packet\r
- *\r
- * Description: This function is printing the given packet .\r
- *\r
- * Parameters:\r
- * packet_buf_p(IN) u_int8_t *\r
- * A pointer to the first byte in the packet.\r
- * packet_size(IN) u_int16_t\r
- * The packet size in bytes\r
- *\r
- * Returns: (void function)\r
- *\r
- *****************************************************************************/\r
-void\r
-MPGA_print_pkt( u_int8_t *packet_buf_p, u_int16_t packet_size);\r
-\r
-/******************************************************************************\r
- * Function: free PKT struct fields\r
- *\r
- * Description: This function will free all the allocted structures .\r
- * in the IB_PKT_st (IB packet struct).\r
- * Parameters:\r
- * pkt_st_p(out) IB_PKT_st *\r
- * A pointer to the IB packet struct.\r
- *\r
- * Returns:\r
- * MT_OK\r
- * MT_ERROR\r
- *****************************************************************************/\r
-call_result_t\r
-MPGA_free_pkt_st_fields(IB_PKT_st *pkt_st_p);\r
-\r
-\r
-#endif /* PACKET_UTILITIES */\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_IBPACKET_H\r
-#define H_IBPACKET_H\r
-\r
-#define IBPCK_GRH_IPVER 6\r
-#define IBPCK_GRH_NEXT_HEADER 0x1B\r
-\r
-/* 5.2.5 Table 8 */\r
-\r
-typedef struct datagram_extended_transport_header_le {\r
- unsigned int Q_Key;\r
-\r
-\r
-#ifdef MT_LITTLE_ENDIAN\r
-/* --------------------------------------------------------- */\r
- unsigned int SrcQP:24;\r
- unsigned int :8;\r
-/* --------------------------------------------------------- */\r
-#else\r
-/* --------------------------------------------------------- */\r
- unsigned int :8;\r
- unsigned int SrcQP:24;\r
-/* --------------------------------------------------------- */\r
-#endif\r
-} IBPCK_deth_le_t; \r
-\r
-/* 5.2.3 Table 6 */\r
-\r
-typedef struct base_transport_header_le {\r
-#ifdef MT_LITTLE_ENDIAN\r
- unsigned int P_KEY:16;\r
- unsigned int TVer:4;\r
- unsigned int PadCnt:2;\r
- unsigned int M:1;\r
- unsigned int SE:1;\r
- unsigned int OpCode:8;\r
-/* --------------------------------------------------------- */\r
- unsigned int DestQP:24;\r
- unsigned int :8;\r
-/* --------------------------------------------------------- */\r
- unsigned int PSN:24;\r
- unsigned int :7;\r
- unsigned int A:1;\r
-/* --------------------------------------------------------- */\r
-#else\r
- unsigned int OpCode:8;\r
- unsigned int SE:1;\r
- unsigned int M:1;\r
- unsigned int PadCnt:2;\r
- unsigned int TVer:4;\r
- unsigned int P_KEY:16;\r
-/* --------------------------------------------------------- */\r
- unsigned int :8;\r
- unsigned int DestQP:24;\r
-/* --------------------------------------------------------- */\r
- unsigned int A:1;\r
- unsigned int :7;\r
- unsigned int PSN:24;\r
-/* --------------------------------------------------------- */\r
-#endif\r
-} IBPCK_bth_le_t; \r
-\r
-/* 5.2.1 Table 4 */\r
-\r
-typedef struct local_route_header_le {\r
-#ifdef MT_LITTLE_ENDIAN\r
- unsigned int DLID:16;\r
- unsigned int LNH:2;\r
- unsigned int :2;\r
- unsigned int SL:4;\r
- unsigned int LVer:4;\r
- unsigned int VL:4;\r
-/* --------------------------------------------------------- */\r
- unsigned int SLID:16;\r
- unsigned int PktLen:11;\r
- unsigned int :5;\r
-/* --------------------------------------------------------- */\r
-#else\r
- unsigned int VL:4;\r
- unsigned int LVer:4;\r
- unsigned int SL:4;\r
- unsigned int :2;\r
- unsigned int LNH:2;\r
- unsigned int DLID:16;\r
-/* --------------------------------------------------------- */\r
- unsigned int :5;\r
- unsigned int PktLen:11;\r
- unsigned int SLID:16;\r
-/* --------------------------------------------------------- */\r
-#endif\r
-} IBPCK_lrh_le_t; \r
-\r
-/* 5.2.2 Table 5 */\r
-\r
-typedef struct global_route_header_le {\r
-#ifdef MT_LITTLE_ENDIAN\r
- unsigned int flow_lable:20;\r
- unsigned int traffic_class:8;\r
- unsigned int IPvers:4;\r
-\r
- unsigned int hop_limit:8;\r
- unsigned int next_hdr:8;\r
- unsigned int pay_len:16;\r
- \r
- unsigned int sgid_3;\r
- unsigned int sgid_2;\r
- unsigned int sgid_1;\r
- unsigned int sgid_0;\r
-\r
- unsigned int dgid_3;\r
- unsigned int dgid_2;\r
- unsigned int dgid_1;\r
- unsigned int dgid_0;\r
-#else\r
- unsigned int IPvers:4;\r
- unsigned int traffic_class:8;\r
- unsigned int flow_lable:20;\r
-\r
- unsigned int pay_len:16;\r
- unsigned int next_hdr:8;\r
- unsigned int hop_limit:8;\r
-\r
- unsigned int sgid_3;\r
- unsigned int sgid_2;\r
- unsigned int sgid_1;\r
- unsigned int sgid_0;\r
-\r
- unsigned int dgid_3;\r
- unsigned int dgid_2;\r
- unsigned int dgid_1;\r
- unsigned int dgid_0;\r
-\r
-#endif\r
-} IBPCK_grh_le_t;\r
-\r
-typedef struct\r
-{\r
- struct local_route_header_le lrh;\r
- struct base_transport_header_le bth;\r
- struct datagram_extended_transport_header_le deth;\r
-\r
-} IBPCK_local_udh_t;\r
-\r
-typedef struct\r
-{\r
- struct local_route_header_le lrh;\r
- struct global_route_header_le grh;\r
- struct base_transport_header_le bth;\r
- struct datagram_extended_transport_header_le deth;\r
-\r
-} IBPCK_global_udh_t;\r
-\r
-\r
-\r
-/*Define Link Next Header Definition */\r
-typedef enum{\r
- IBPCK_RAW = 0x0, /* |LRH|... (Etertype)*/\r
- IBPCK_IP_NON_IBA_TRANS = 0x1, /* |LRH|GRH|... */\r
- IBPCK_IBA_LOCAL = 0x2, /* |LRH|BTH|... */\r
- IBPCK_IBA_GLOBAL = 0x3 /* |LRH|GRH|BTH|... */\r
-} IBPCK_LNH_t;\r
-\r
-\r
-\r
-\r
-#endif /* H_IB_PACKET_H */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-/*\r
- * Save log at DRAM and not file system.\r
- */\r
-#ifndef MT_KERNEL\r
-\r
-#if defined( __LINUX__ ) || defined( __DARWIN__ )\r
-#include <pthread.h>\r
-#elif defined (__WIN__ )\r
-#include <windows.h>\r
-HANDLE log_lock;\r
-#endif\r
-\r
-#define MAX_FILENAME 256\r
-#define MTL_LOG_ENV "MTL_LOG"\r
-#define MTL_LOG_DEF "-"\r
-\r
-\r
-# ifdef __DARWIN__\r
-# include <string.h>\r
-# include <sys/systm.h>\r
- /* The function is not supplied in kernel, so it is added \r
- * here below for Darwin Kernel */\r
- static char *strstr (const char *phaystack, const char *pneedle);\r
-# define printk(...) IOLog(__VA_ARGS__) \r
-# endif /* defined __DARWIN__ */\r
-\r
-#endif /* MT_KERNEL */\r
-\r
-\r
-/* Here we force this feature out */\r
-#undef MTL_LOG_MALLOC\r
-\r
-/* Take local header before getting it from the release. */\r
-#if MT_KERNEL\r
-#include "mtl_sys_defs.h"\r
-#else\r
-#include "mtl_sys_defs.h"\r
-#include "complib/cl_debug.h"\r
-#endif\r
-\r
-#include "mtl_common.h"\r
-\r
-#ifdef __WIN__\r
-char *cur_module;\r
-#endif\r
-\r
-\r
-const char* mtl_strerror( call_result_t errnum)\r
-{\r
- switch (errnum) {\r
-#define INFO(A, B, C) case A: return C;\r
- ERROR_LIST\r
-#undef INFO\r
- default: return "Unknown error";\r
- }\r
-}\r
-\r
-const char* mtl_strerror_sym( call_result_t errnum)\r
-{\r
- switch (errnum) {\r
-#define INFO(A, B, C) case A: return #A;\r
- ERROR_LIST\r
-#undef INFO\r
- default: return "Unknown error";\r
- }\r
-}\r
-\r
-const char* mtl_basename(const char* filename)\r
-{\r
- const char* slash_p = strchr(filename, '/');\r
- if (slash_p)\r
- {\r
- filename = slash_p + 1;\r
- }\r
- return filename;\r
-} /* mtl_basename */\r
-\r
-\r
-static MT_bool extract_key(const char *str, const char *key, const char *suffix,\r
- char *result, const int result_max_len)\r
-{\r
- char *p, *pstr = (char *)str;\r
- int i=0;\r
-\r
- if (!pstr)\r
- return FALSE;\r
-\r
- while ((p = strstr(pstr, key)))\r
- {\r
- if (!strncmp(p + strlen(key), suffix, strlen(suffix)))\r
- {\r
- char *q = p+strlen(key)+strlen(suffix);\r
- while (*q && *q != ' ')\r
- {\r
- *result++ = *q++;\r
- if (++i >= result_max_len)\r
- break;\r
- }\r
- *result = '\0';\r
- return TRUE;\r
- }\r
- else\r
- pstr = p + strlen(key);\r
- }\r
- return FALSE;\r
-}\r
-\r
-/************** Kernel Specific Code ************************/\r
-\r
-#ifdef MT_KERNEL\r
-\r
-static struct log_info {\r
- char *name; // Module name\r
- struct log_info *next; // Pointer to next record\r
- struct print_info {\r
- char *name;\r
- char sevs[MAX_MTL_LOG_SEVERITIES+1];\r
- } print_info[MAX_MTL_LOG_TYPES];\r
-} *log_first = (struct log_info *)NULL,\r
- log_default = {\r
- NULL, NULL,\r
- {\r
- { "trace", "" },\r
- { "debug", "" },\r
- { "error", "1234" }\r
- }\r
- };\r
-\r
-//TODO: Bug: strlen run on user space buffer!\r
-//static char *mtl_strdup(const char *str)\r
-// return s ? strcpy(s, str) : NULL;\r
-//#define mtl_strdup(str) ({ char *s = (char*)MALLOC(strlen(str)+1); s? strcpy(s, (str)) : NULL; })\r
-static __INLINE__ char *mtl_strdup(const char *str)\r
-{\r
- char *s = (char*)MALLOC(strlen(str)+1); \r
- return s? strcpy(s, (str)) : NULL; \r
-}\r
-\r
-\r
-static int debug_print = 0;\r
-\r
-void mtl_log_set(char* layer, char *info)\r
-{\r
- struct log_info *p, *prev;\r
-\r
- printk("mtl_log_set: layer '%s', info '%s'\n", layer, info );\r
- \r
- if (!strcmp( layer, "mtl_log_dbg_print" )) {\r
- debug_print ^= 1;\r
- return;\r
- }\r
-\r
- if (strcmp(layer, "print"))\r
- {\r
- /*\r
- * Find necessary record\r
- */\r
- for(prev = p = log_first; p; prev = p, p = p->next)\r
- {\r
- if (!strcmp(layer, p->name))\r
- break;\r
- }\r
- if (!p)\r
- {\r
- /* Not found - create */\r
- /* Do not use MALLOC macro to avoid infinite recursion */\r
- p = (struct log_info *)QMALLOC(sizeof(struct log_info));\r
- memcpy(p, &log_default, sizeof(struct log_info));\r
- p->name = mtl_strdup(layer);\r
- if (prev)\r
- prev->next = p;\r
- else\r
- log_first = p;\r
- }\r
- /*\r
- * Now "p" is a pointer to corresponding record, either existed\r
- * or created just now\r
- */\r
- extract_key(info, "trace", ":", p->print_info[mtl_log_trace].sevs,\r
- MAX_MTL_LOG_SEVERITIES);\r
- extract_key(info, "debug", ":", p->print_info[mtl_log_debug].sevs,\r
- MAX_MTL_LOG_SEVERITIES);\r
- extract_key(info, "error", ":",p->print_info[mtl_log_error].sevs,\r
- MAX_MTL_LOG_SEVERITIES);\r
-\r
- }\r
- else\r
- {\r
- printk("<1>\n");\r
- printk("<1> Layers and severities for print\n");\r
- printk("<1> -------------------------------\n");\r
- for(p=log_first; p; p = p->next)\r
- {\r
- int i;\r
- \r
- printk("<1> Layer - \"%s\":\n", p->name);\r
- for (i=0; i<MAX_MTL_LOG_TYPES; i++)\r
- {\r
- printk("<1> Name=\"%s\", severities=\"%s\"\n",\r
- p->print_info[i].name, p->print_info[i].sevs);\r
- }\r
- }\r
- printk("<1>\n");\r
- }\r
-}\r
-\r
-/*\r
- * mtl_common_cleanup\r
- */\r
-void mtl_common_cleanup(void)\r
-{\r
- struct log_info *p = log_first, *next;\r
-\r
- while ( p ) {\r
- if ( p->name ) {\r
- FREE(p->name);\r
- p->name = NULL;\r
- }\r
- next = p->next;\r
- FREE(p);\r
- p = next;\r
- }\r
-}\r
-\r
-void mtl_log(const char* layer, mtl_log_types log_type, char sev, \r
- const char *fmt, ...)\r
-{\r
- char pbuff[MAX_MTL_LOG_LEN];\r
- struct log_info *p, *prev;\r
- va_list ap;\r
- if (debug_print)\r
- printk("***** mtl_log:DEBUG: layer '%s', type %d, sev '%c'\n", layer, log_type, sev);\r
-\r
- /*\r
- * Find necessary record\r
- */\r
- for(prev = p = log_first; p; prev = p, p = p->next)\r
- {\r
- if (!strcmp(layer, p->name))\r
- break;\r
- }\r
- \r
- if (!p)\r
- {\r
- if (debug_print)\r
- printk("***** mtl_log:DEBUG: Not found layer '%s' - create\n", layer);\r
- \r
- // Not found - create\r
- // Avoid call to MALLOC to avoid infinite recursion\r
- p = (struct log_info *)QMALLOC(sizeof(struct log_info));\r
- if (p == NULL) {\r
- /* malloc failure. just return */\r
- return;\r
- }\r
- memcpy(p, &log_default, sizeof(struct log_info));\r
- p->name = mtl_strdup(layer);\r
- if (p->name == NULL) {\r
- FREE(p);\r
- return;\r
- }\r
- if (prev)\r
- prev->next = p;\r
- else\r
- log_first = p;\r
- }\r
- else\r
- {\r
- if (debug_print)\r
- printk("***** mtl_log:DEBUG: Found layer '%s', Name=\"%s\", sev=\"%s\"\n", \r
- p->name, p->print_info[log_type].name, p->print_info[log_type].sevs );\r
- }\r
-\r
- /*\r
- * Now "p" is a pointer to corresponding record, either existed\r
- * or created just now\r
- */\r
-\r
-\r
- /*\r
- * Log printing\r
- */\r
- if (strchr(p->print_info[log_type].sevs, sev))\r
- {\r
- if (debug_print)\r
- printk("***** mtl_log:DEBUG: print string\n" );\r
- va_start (ap, fmt);\r
- vsprintf (pbuff, fmt, ap);\r
- va_end (ap);\r
- printk("<1> %s(%c): %s", layer, sev, pbuff);\r
- }\r
-}\r
-\r
-/************************************************************************/\r
-/* Kernel memory allocation logging/debugging */\r
-\r
-#if 0\r
-/* Alas, we do not have such machinery for the kernel (yet?) */\r
-\r
-/* #include <execinfo.h> */\r
-static const char* getBackTrace(char* buf, int bufLen)\r
-{\r
- enum {Depth = 5};\r
- char* pBuf = buf;\r
- void* array[Depth];\r
- size_t size = backtrace(array, Depth);\r
- if (size > 0)\r
- {\r
- char* pBufLimit = buf + bufLen - 2;\r
- char** syms = backtrace_symbols(array, size);\r
- char** symsEnd = syms += size;\r
- char* sym = syms[0];\r
- char* pBufNext = pBuf + strlen(sym);\r
- while ((syms != symsEnd) && (pBufNext < pBufLimit))\r
- {\r
- strcpy(pBuf, sym);\r
- pBuf = pBufNext;\r
- *pBuf++ = '|'; \r
- ++syms;\r
- if (syms != symsEnd)\r
- {\r
- sym = *syms;\r
- pBufNext += strlen(sym);\r
- }\r
- }\r
- }\r
- *pBuf = '\0';\r
- return buf;\r
-} /* getBackTrace */\r
-#endif\r
-\r
-static const char* mtl_malloc_modname = "MEMCHECK";\r
-static const char* mallog_magic = "takeme4memcheck";\r
-\r
-void* mtl_log_vmalloc(const char* fn, int ln, int bsize)\r
-{\r
- /* char symTrace[256]; \r
- * getBackTrace(symTrace, sizeof(symTrace)); */\r
- void* ptr = (void*)QVMALLOC(bsize);\r
- mtl_log(mtl_malloc_modname, mtl_log_debug, '1', \r
- "%s[%d]: 0x%p := vmalloc(%d) %s %s\n", \r
- fn, ln, ptr, bsize, mallog_magic, "");\r
- return ptr;\r
-}\r
-\r
-void mtl_log_vfree(const char* fn, int ln, void* ptr)\r
-{\r
- mtl_log(mtl_malloc_modname, mtl_log_debug, '1', \r
- "%s[%d]: vfree(0x%p) %s\n", fn, ln, ptr, mallog_magic);\r
- QVFREE(ptr);\r
-}\r
-\r
-void* mtl_log_kmalloc(const char* fn, int ln, int bsize, unsigned g)\r
-{\r
- /* char symTrace[256];\r
- * getBackTrace(symTrace, sizeof(symTrace)); */\r
- void* ptr = (void*)QCMALLOC(bsize, g);\r
- mtl_log(mtl_malloc_modname, mtl_log_debug, '1', \r
- "%s[%d]: 0x%p := kmalloc(%d, 0x%x) %s %s\n", \r
- fn, ln, ptr, bsize, g, mallog_magic, "");\r
- return ptr;\r
-}\r
-\r
-void mtl_log_kfree(const char* fn, int ln, void *ptr)\r
-{\r
- mtl_log(mtl_malloc_modname, mtl_log_debug, '1', \r
- "%s[%d]: kfree(0x%p) %s\n", fn, ln, ptr, mallog_magic);\r
- QFREE(ptr);\r
-}\r
-\r
-/* */\r
-/************************************************************************/\r
-#else /* not defined MT_KERNEL */\r
-\r
-/************** User Specific Code ************************/\r
-\r
-static struct log_info {\r
- char *name; // Module name\r
- FILE *fp; // File for output\r
- int first; // first usage == 1\r
- struct log_info *next; // Pointer to next record\r
- struct print_info {\r
- char *name;\r
- char sevs[MAX_MTL_LOG_SEVERITIES+1];\r
- } print_info[MAX_MTL_LOG_TYPES];\r
-} *log_first = (struct log_info *)NULL,\r
- log_default = {\r
- NULL, NULL, 1, NULL,\r
- {\r
- { "trace", "" },\r
- { "debug", "" },\r
- { "error", "" }\r
- }\r
- };\r
-\r
-static FILE *open_logfile(const char *fname)\r
-{\r
- FILE *rc;\r
-/*\r
- if (!lstrcmp(fname, "-") || !lstrcmp(fname, "&"))\r
- rc = stderr;\r
- else if (!lstrcmp(fname, ">"))\r
- rc = stdout;\r
- else if ((rc = fopen(fname, "w")) == NULL)\r
- {\r
- fprintf(stderr, "Can't open \"%s\" - %s\nUse stderr instead.\n",\r
- fname, strerror(errno));\r
- rc = stderr;\r
- }\r
- */\r
- return stdout;\r
-}\r
-\r
-void mtl_log_DB_print()\r
-{\r
- struct log_info *p;\r
- DebugPrint("<1>\n");\r
- DebugPrint("<1> Layers and severities for print\n");\r
- DebugPrint("<1> -------------------------------\n");\r
- for(p=log_first; p; p = p->next)\r
- {\r
- int i;\r
- \r
- DebugPrint("<1> Layer - \"%s\":\n", p->name);\r
- for (i=0; i<MAX_MTL_LOG_TYPES; i++)\r
- {\r
- DebugPrint("<1> Name=\"%s\", severities=\"%s\"\n",\r
- p->print_info[i].name, p->print_info[i].sevs);\r
- }\r
- }\r
- DebugPrint("<1>\n");\r
-}\r
-\r
-static __INLINE__ char *mtl_strdup(const char *str)\r
-{\r
- char *s = (char*)MALLOC(strlen(str)+1); \r
- return s? lstrcpy(s, (str)) : NULL; \r
-}\r
-\r
-\r
-\r
-void mtl_log(const char* layer, mtl_log_types log_type, char sev, \r
- const char *fmt, ...)\r
-{\r
- char pbuff[MAX_MTL_LOG_LEN];\r
- struct log_info *p, *prev;\r
- va_list ap;\r
- /*\r
- * Find necessary record\r
- */\r
- for(prev = p = log_first; p; prev = p, p = p->next)\r
- {\r
- if (!lstrcmpi(layer, p->name))\r
- break;\r
- }\r
- \r
- if (!p)\r
- {\r
- \r
- // Not found - create\r
- // Avoid call to MALLOC to avoid infinite recursion\r
- p = (struct log_info *)MALLOC(sizeof(struct log_info));\r
- if (p == NULL) {\r
- /* malloc failure. just return */\r
- return;\r
- }\r
- CopyMemory(p, &log_default, sizeof(struct log_info));\r
- p->name = mtl_strdup(layer);\r
- if (p->name == NULL) {\r
- FREE(p);\r
- return;\r
- }\r
- if (prev)\r
- prev->next = p;\r
- else\r
- log_first = p;\r
- }\r
-\r
- /*\r
- * Now "p" is a pointer to corresponding record, either existed\r
- * or created just now\r
- */\r
-\r
-\r
- /*\r
- * Log printing\r
- */\r
- //if (strchr(p->print_info[log_type].sevs, sev))\r
- \r
- va_start (ap, fmt);\r
- wvsprintf (pbuff, fmt, ap);\r
- va_end (ap);\r
- DebugPrint(" %s(%c): %s", layer, sev, pbuff);\r
- }\r
-\r
-#endif /* __KERNEL__ */\r
-\r
-\r
-\r
-#if defined(__WIN__) || defined(VXWORKS_OS)\r
-\r
-#define MAX_MOD_NAME_LEN 32\r
-\r
-/*\r
- * The only reason why mt_strtoull function is here\r
- * - I didn't find such function in MSDN library.\r
- *\r
- * The code of mt_strtoull borrowed from glibc library\r
- * with small changes\r
- */\r
-/* Convert NPTR to an `unsigned long int' or `long int' in base BASE.\r
- If BASE is 0 the base is determined by the presence of a leading\r
- zero, indicating octal or a leading "0x" or "0X", indicating hexadecimal.\r
- If BASE is < 2 or > 36, it is reset to 10.\r
- If ENDPTR is not NULL, a pointer to the character after the last\r
- one converted is stored in *ENDPTR. */\r
-#if 0\r
-u_int64_t mt_strtoull (const char *nptr, char **endptr, int base)\r
-{\r
- int overflow, negative;\r
- u_int64_t i, cutlim, cutoff;\r
- const char *s;\r
- char c;\r
- const char *save;\r
-\r
- if (base < 0 || base == 1 || base > 36)\r
- base = 10;\r
-\r
- s = nptr;\r
-\r
- /* Skip white space. */\r
- while (isspace (*s))\r
- ++s;\r
- if (*s == '\0')\r
- goto noconv;\r
-\r
- /* Check for a sign. */\r
- if (*s == '-')\r
- {\r
- negative = 1;\r
- ++s;\r
- }\r
- else if (*s == '+')\r
- {\r
- negative = 0;\r
- ++s;\r
- }\r
- else\r
- negative = 0;\r
-\r
- if (base == 16 && s[0] == '0' && toupper (s[1]) == 'X')\r
- s += 2;\r
-\r
- /* If BASE is zero, figure it out ourselves. */\r
- if (base == 0)\r
- {\r
- if (*s == '0')\r
- {\r
- if (toupper (s[1]) == 'X')\r
- {\r
- s += 2;\r
- base = 16;\r
- }\r
- else\r
- base = 8;\r
- }\r
- else\r
- base = 10;\r
- }\r
-\r
- /* Save the pointer so we can check later if anything happened. */\r
- save = s;\r
-\r
- cutoff = _UI64_MAX / (u_int32_t) base;\r
- cutlim = _UI64_MAX % (u_int32_t) base;\r
-\r
- overflow = 0;\r
- i = 0;\r
- for (c = *s; c != '\0'; c = *++s)\r
- {\r
- if (isdigit (c))\r
- c -= '0';\r
- else if (isalpha (c))\r
- c = toupper (c) - 'A' + 10;\r
- else\r
- break;\r
- if (c >= base)\r
- break;\r
- /* Check for overflow. */\r
- if (i > cutoff || (i == cutoff && c > cutlim))\r
- overflow = 1;\r
- else\r
- {\r
- i *= (unsigned long int) base;\r
- i += c;\r
- }\r
- }\r
-\r
- /* Check if anything actually happened. */\r
- if (s == save)\r
- goto noconv;\r
-\r
- /* Store in ENDPTR the address of one character\r
- past the last character we converted. */\r
- if (endptr != NULL)\r
- *endptr = (char *) s;\r
-\r
- if (overflow)\r
- return _UI64_MAX;\r
-\r
- /* Return the result of the appropriate sign. */\r
- return (negative ? (u_int64_t)(-(int64_t)i) : i);\r
-\r
-noconv:\r
- /* There was no number to convert. */\r
- if (endptr != NULL)\r
- *endptr = (char *) nptr;\r
- return 0L;\r
-}\r
-#endif // 0\r
-\r
-#endif \r
-\r
-#if defined(__WIN__)\r
-\r
-#ifdef __KERNEL__\r
-\r
-\r
-static KSPIN_LOCK s_mod_name_sp;\r
-static char s_mod_name[MAX_MOD_NAME_LEN];\r
-static KIRQL s_irql=0;\r
-static KIRQL s_irql_synch=0;\r
-\r
-#ifdef USE_RELAY_MOD_NAME\r
-#define NT_CALL_MT_LOG(sev,type) \\r
- char mod_name[MAX_MOD_NAME_LEN]; \\r
- char pbuff[MAX_MTL_LOG_LEN]; \\r
- va_list ap; \\r
- mtl_log_get_name(mod_name); \\r
- va_start (ap, fmt); \\r
- vsprintf (pbuff, fmt, ap); \\r
- va_end (ap); \\r
- mtl_log( mod_name, type, sev, "%s", pbuff)\r
-#else\r
-#define NT_CALL_MT_LOG(sev,type) \\r
- char pbuff[MAX_MTL_LOG_LEN]; \\r
- va_list ap; \\r
- va_start (ap, fmt); \\r
- vsprintf (pbuff, fmt, ap); \\r
- va_end (ap); \\r
- mtl_log( MAKE_MOD_NAME, type, sev, "%s", pbuff)\r
-#endif\r
-\r
-\r
-NTKERNELAPI\r
-KIRQL\r
-FASTCALL\r
-KeAcquireSpinLockRaiseToSynch (\r
- PKSPIN_LOCK SpinLock\r
- );\r
-\r
-void mtl_log_set_name( char * mod_name )\r
-{\r
-#ifndef USE_RELAY_MOD_NAME\r
- DbgPrint( "mtl_log_set_name: can't be here, irql = %d!!!\n", KeGetCurrentIrql());\r
- ASSERT(0);\r
-#endif\r
- s_irql = KeAcquireSpinLockRaiseToSynch(&s_mod_name_sp); \r
- strcpy( s_mod_name, mod_name );\r
-}\r
-\r
-static __inline void mtl_log_get_name( char * mod_name )\r
-{\r
- KIRQL irql = KeGetCurrentIrql();\r
-#ifndef USE_RELAY_MOD_NAME\r
- DbgPrint( "mtl_log_set_name: can't be here, irql = %d!!!\n", irql);\r
- ASSERT(0);\r
-#endif\r
- if (irql != s_irql_synch) {\r
- DbgPrint( "MDT.SYS: mtl_log_get_name: WARNING: unexpected current IRQL (%d), new (=prev) irql = %d!!\n", irql, s_irql);\r
- ASSERT(0);\r
- }\r
- irql = s_irql; \r
- strcpy( mod_name, s_mod_name ); \r
- s_irql = 0;\r
- KeReleaseSpinLock(&s_mod_name_sp, irql ); \r
-}\r
-\r
-#ifndef MT_BUILD_LIB\r
-NTSTATUS DllInitialize(PUNICODE_STRING RegistryPath)\r
-{\r
-#ifdef USE_RELAY_MOD_NAME\r
- KIRQL irql;\r
- // init spinlock\r
- KeInitializeSpinLock(&s_mod_name_sp);\r
- // find SYNC IRQL\r
- irql = KeAcquireSpinLockRaiseToSynch(&s_mod_name_sp); \r
- s_irql_synch = KeGetCurrentIrql();\r
- KeReleaseSpinLock(&s_mod_name_sp, irql ); \r
-#endif\r
-\r
- DbgPrint("\n***** MTL_COMMON_KL: DllInitialize()");\r
- return STATUS_SUCCESS;\r
-}\r
-\r
-NTSTATUS DllUnload()\r
-{\r
- DbgPrint("\n***** MTL_COMMON_KL: DllUnload()");\r
- return STATUS_SUCCESS;\r
-}\r
-\r
-NTSTATUS \r
-DriverEntry(\r
- IN PDRIVER_OBJECT pi_pDriverObject,\r
- IN PUNICODE_STRING pi_pRegistryPath\r
- )\r
-{ /* DriverEntry */\r
-\r
- DbgPrint("\n***** MTL_COMMON_KL: DriverEntry()");\r
- return STATUS_SUCCESS;\r
-\r
-} /* DriverEntry */\r
-#endif /* ifndef MT_BUILD_LIB */\r
-\r
-\r
-#else /* ifdef __KERNEL__ */\r
-\r
-/* ----- User Space ----- */\r
-\r
-\r
-#include <windows.h>\r
-\r
-int s_mod_name_init = 1;\r
-HANDLE s_mod_name_mutex = NULL;\r
-char s_mod_name[MAX_MOD_NAME_LEN];\r
-\r
-#ifdef USE_RELAY_MOD_NAME\r
-#define NT_CALL_MT_LOG(sev,type) \\r
- char mod_name[MAX_MOD_NAME_LEN]; \\r
- char pbuff[MAX_MTL_LOG_LEN]; \\r
- va_list ap; \\r
- mtl_log_get_name(mod_name); \\r
- va_start (ap, fmt); \\r
- wvsprintf (pbuff, fmt, ap); \\r
- va_end (ap); \\r
- mtl_log( mod_name, type, sev, "%s", pbuff)\r
-#else\r
-#define NT_CALL_MT_LOG(sev,type) \\r
- char pbuff[MAX_MTL_LOG_LEN]; \\r
- va_list ap; \\r
- va_start (ap, fmt); \\r
- wvsprintf (pbuff, fmt, ap); \\r
- va_end (ap); \\r
- mtl_log( MAKE_MOD_NAME, type, sev, "%s", pbuff)\r
-#endif\r
-\r
-void mtl_log_get_name( char * mod_name )\r
-{\r
-#ifndef USE_RELAY_MOD_NAME\r
- DebugPrint( "MTL_COMMON: mtl_log_get_name: error in build - we can't get here !!!\n");\r
-#endif\r
- lstrcpy( mod_name, s_mod_name ); \r
- if (s_mod_name_mutex != NULL) \r
- ReleaseMutex( s_mod_name_mutex ); \r
-}\r
-\r
-void mtl_log_set_name( char * mod_name )\r
-{\r
-#ifndef USE_RELAY_MOD_NAME\r
- DebugPrint( "MTL_COMMON: mtl_log_set_name: error in build - we can't get here !!!\n");\r
-#endif\r
- if (s_mod_name_init) {\r
- s_mod_name_mutex = CreateMutex(\r
- NULL, // default security descriptor\r
- FALSE, // not to acquire on creation\r
- "MOD_NAME_MUTEX" // object name: unnamed\r
- );\r
- if (s_mod_name_mutex == NULL) {\r
- mtl_log( "MTLCOMMON", mtl_log_error, 1, "(mtl_log_set_name) CreateMutex failed (0x%x)\n", GetLastError() );\r
- }\r
- s_mod_name_init = 0;\r
- }\r
-\r
- if (s_mod_name_mutex != NULL) {\r
- WaitForSingleObject(\r
- s_mod_name_mutex, // handle to object\r
- INFINITE // time-out interval\r
- );\r
- }\r
- strcpy( s_mod_name, mod_name ); \r
-}\r
-\r
-\r
-BOOL mtl_common_main( HANDLE hModule, \r
- DWORD ul_reason_for_call, \r
- LPVOID lpReserved\r
- )\r
-{\r
- BOOL l_fRetCode = TRUE;\r
-\r
- switch (ul_reason_for_call)\r
- {\r
- case DLL_PROCESS_ATTACH:\r
- log_lock = CreateMutex( NULL, FALSE, NULL );\r
- break;\r
-\r
- case DLL_PROCESS_DETACH:\r
- if (log_lock != NULL)\r
- CloseHandle(log_lock);\r
- break;\r
- \r
- case DLL_THREAD_ATTACH:\r
- case DLL_THREAD_DETACH:\r
- break;\r
- }\r
- return l_fRetCode;\r
-}\r
-\r
-VOID \r
-DebugPrint(\r
- IN PUCHAR pi_szFormat,\r
- ...\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- Writes a formatted ( printf() like ) string to output\r
-\r
-Arguments:\r
-\r
- pi_nDbgLogLevel...... Level of debugging log.\r
- pi_szFormat.......... The format of the log.\r
-\r
-Return Value:\r
-\r
- None .\r
-\r
---*/\r
-{ /* DebugPrint */\r
-\r
- /* Log buffer for DebugPrint */\r
- static CHAR l_vLogBuff[ 1024 ];\r
- /* Formatted string length */\r
- int l_nStrLen ;\r
-\r
- /* Variable argument list */ \r
- va_list l_Argptr;\r
-\r
- /* Init the variable argument list */ \r
- va_start(l_Argptr, pi_szFormat);\r
-\r
- /* Build the formatted string */\r
- l_nStrLen = wvsprintf((char*)&l_vLogBuff[0] , (const char *)pi_szFormat , l_Argptr);\r
-\r
- /* If debug mode , print to debug window*/\r
- OutputDebugString(l_vLogBuff);\r
-\r
- /* Term the variable argument list */ \r
- va_end(l_Argptr);\r
-\r
-} /* DebugPrint */\r
-\r
-#endif /* ifdef __KERNEL__ */\r
-\r
-#if defined(_M_IX86)\r
-#pragma message( "***** The code is being built for __i386__ architecture *****" )\r
-#elif defined(_M_IA64)\r
-#pragma message( "***** The code is being built for __ia64__ architecture *****" )\r
-#elif defined(_M_AMD64)\r
-#pragma message( "***** The code is being built for __amd64__ architecture *****" )\r
-#else\r
-#error Platform is not supported yet\r
-#endif\r
-\r
-\r
-void NT_trace(char sev, char *fmt, ...) { NT_CALL_MT_LOG(sev,mtl_log_trace); }\r
-void NT_trace1(char *fmt, ...) { NT_CALL_MT_LOG('1',mtl_log_trace); }\r
-void NT_trace2(char *fmt, ...) { NT_CALL_MT_LOG('2',mtl_log_trace); }\r
-void NT_trace3(char *fmt, ...) { NT_CALL_MT_LOG('3',mtl_log_trace); }\r
-void NT_trace4(char *fmt, ...) { NT_CALL_MT_LOG('4',mtl_log_trace); }\r
-void NT_trace5(char *fmt, ...) { NT_CALL_MT_LOG('5',mtl_log_trace); }\r
-void NT_trace6(char *fmt, ...) { NT_CALL_MT_LOG('6',mtl_log_trace); }\r
-void NT_trace7(char *fmt, ...) { NT_CALL_MT_LOG('7',mtl_log_trace); }\r
-void NT_trace8(char *fmt, ...) { NT_CALL_MT_LOG('8',mtl_log_trace); }\r
-void NT_trace9(char *fmt, ...) { NT_CALL_MT_LOG('9',mtl_log_trace); }\r
-void NT_debug(char sev, char *fmt, ...) { NT_CALL_MT_LOG(sev,mtl_log_debug); }\r
-void NT_debug1(char *fmt, ...) { NT_CALL_MT_LOG('1',mtl_log_debug); }\r
-void NT_debug2(char *fmt, ...) { NT_CALL_MT_LOG('2',mtl_log_debug); }\r
-void NT_debug3(char *fmt, ...) { NT_CALL_MT_LOG('3',mtl_log_debug); }\r
-void NT_debug4(char *fmt, ...) { NT_CALL_MT_LOG('4',mtl_log_debug); }\r
-void NT_debug5(char *fmt, ...) { NT_CALL_MT_LOG('5',mtl_log_debug); }\r
-void NT_debug6(char *fmt, ...) { NT_CALL_MT_LOG('6',mtl_log_debug); }\r
-void NT_debug7(char *fmt, ...) { NT_CALL_MT_LOG('7',mtl_log_debug); }\r
-void NT_debug8(char *fmt, ...) { NT_CALL_MT_LOG('8',mtl_log_debug); }\r
-void NT_debug9(char *fmt, ...) { NT_CALL_MT_LOG('9',mtl_log_debug); }\r
-void NT_error(char sev, char *fmt, ...) { NT_CALL_MT_LOG(sev,mtl_log_error); }\r
-void NT_error1(char *fmt, ...) { NT_CALL_MT_LOG('1',mtl_log_error); }\r
-void NT_error2(char *fmt, ...) { NT_CALL_MT_LOG('2',mtl_log_error); }\r
-void NT_error3(char *fmt, ...) { NT_CALL_MT_LOG('3',mtl_log_error); }\r
-void NT_error4(char *fmt, ...) { NT_CALL_MT_LOG('4',mtl_log_error); }\r
-void NT_error5(char *fmt, ...) { NT_CALL_MT_LOG('5',mtl_log_error); }\r
-void NT_error6(char *fmt, ...) { NT_CALL_MT_LOG('6',mtl_log_error); }\r
-void NT_error7(char *fmt, ...) { NT_CALL_MT_LOG('7',mtl_log_error); }\r
-void NT_error8(char *fmt, ...) { NT_CALL_MT_LOG('8',mtl_log_error); }\r
-void NT_error9(char *fmt, ...) { NT_CALL_MT_LOG('9',mtl_log_error); }\r
-\r
-\r
-#endif /* defined(__WIN__)*/\r
-\r
-#if defined(__DARWIN__) && defined(MT_KERNEL)\r
-\r
-/* copy paste function implementation for strstr */\r
-static char *strstr (const char *phaystack, const char *pneedle)\r
-{\r
- const unsigned char *haystack, *needle;\r
- char b, c;\r
- \r
- haystack = (const unsigned char *) phaystack;\r
- needle = (const unsigned char *) pneedle;\r
- \r
- b = *needle;\r
- if (b != '\0')\r
- {\r
- haystack--;\r
- do\r
- {\r
- c = *++haystack;\r
- if (c == '\0')\r
- goto ret0;\r
- }\r
- while (c != b);\r
- \r
- c = *++needle;\r
- if (c == '\0')\r
- goto foundneedle;\r
- ++needle;\r
- goto jin;\r
-\r
- for (;;)\r
- {\r
- char a;\r
- const unsigned char *rhaystack, *rneedle;\r
- \r
- do\r
- {\r
- a = *++haystack;\r
- if (a == '\0')\r
- goto ret0;\r
- if (a == b)\r
- break;\r
- a = *++haystack;\r
- if (a == '\0')\r
- goto ret0;\r
-shloop:; }\r
- while (a != b);\r
-\r
-jin: a = *++haystack;\r
- if (a == '\0')\r
- goto ret0;\r
-\r
- if (a != c)\r
- goto shloop;\r
-\r
- rhaystack = haystack-- + 1;\r
- rneedle = needle;\r
- a = *rneedle;\r
-\r
- if (*rhaystack == a)\r
- do\r
- {\r
- if (a == '\0')\r
- goto foundneedle;\r
- ++rhaystack;\r
- a = *++needle;\r
- if (*rhaystack != a)\r
- break;\r
- if (a == '\0')\r
- goto foundneedle;\r
- ++rhaystack;\r
- a = *++needle;\r
- }\r
- while (*rhaystack == a);\r
-\r
- needle = rneedle; \r
-\r
- if (a == '\0')\r
- break;\r
- }\r
- }\r
-foundneedle:\r
- return (char*) haystack;\r
-ret0:\r
- return 0;\r
-}\r
-\r
-#endif\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#ifndef H_MTL_COMMON_H\r
-#define H_MTL_COMMON_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-#if defined(__mppc__) && ! defined(MT_BIG_ENDIAN)\r
-#define MT_BIG_ENDIAN 1\r
-#endif\r
-\r
-#ifdef VXWORKS_OS\r
-\r
-/*\r
- * General include files required by VxWorks applications.\r
- */ \r
-#include "vxWorks.h"\r
-#include "stdio.h"\r
-#include "stdlib.h"\r
-#include "string.h"\r
-#include "stdarg.h"\r
-#include "errno.h"\r
-#include "taskLib.h"\r
-#include "semLib.h"\r
-\r
-/*\r
- * No print kernel under VxWorks.\r
- */\r
-#define printk printf\r
-\r
-/* \r
- * MDDK assumes that random returns values upto 32k which is true only to rand. \r
- */ \r
-#define random rand\r
-#define srandom srand\r
-\r
-/*\r
- * If CPU is already big endian, degenerate big endian macros.\r
- */\r
-#ifdef MT_BIG_ENDIAN\r
-#error MT_BIG_ENDIAN defined\r
-#define __cpu_to_be32(x) (x)\r
-#define __be32_to_cpu(x) (x)\r
-#define __cpu_to_be64(x) (x)\r
-#define __be64_to_cpu(x) (x)\r
-#define __cpu_to_be16(x) (x)\r
-#define __be16_to_cpu(x) (x)\r
-#endif /* MT_BIG_ENDIAN */\r
-\r
-/*\r
- * Limits definitions.\r
- */\r
-#include "limits.h"\r
-\r
-/*\r
- * Global semaphore which prevents more than one application to access CR space.\r
- */\r
-extern SEM_ID appl_is_running_sem;\r
-\r
-#endif /* VXWORKS_OS */\r
-\r
-#include <mtl_types.h>\r
-#include <bit_ops.h>\r
-\r
-#define MAX_MTL_LOG_TYPES 3\r
-#define MAX_MTL_LOG_SEVERITIES 8\r
-#define MAX_MTL_LOG_LEN 512\r
-#define MAX_MTL_LOG_LAYER 32\r
-#define MAX_MTL_LOG_INFO 512\r
-typedef enum {\r
- mtl_log_trace=0,\r
- mtl_log_debug=1,\r
- mtl_log_error=2\r
-} mtl_log_types;\r
-\r
-/* Prepend File-name + Line-number to formatted message.\r
- * Example: MTL_DEBUG4(MT_FLFMT("(1+1/n)^n -> %g (%s)"), M_E, "Euler")\r
- */\r
-#define MT_FLFMT(fmt) "%s[%d]: " fmt "\n", mtl_basename(__FILE__), __LINE__\r
-\r
-/* OS-dependent stuff */\r
-#include <mtl_sys_defs.h>\r
-\r
-/* Convenient macros doing cast & sizeof */\r
-#define TNMALLOC(t, n) (t*)MALLOC((n) * sizeof(t))\r
-#define TMALLOC(t) TNMALLOC(t, 1)\r
-#define TNVMALLOC(t, n) (t*)VMALLOC((n) * sizeof(t))\r
-#define TVMALLOC(t) TNVMALLOC(t, 1)\r
-#define TNINTR_MALLOC(t, n) (t*)INTR_MALLOC((n) * sizeof(t))\r
-#define TINTR_MALLOC(t) TNINTR_MALLOC(t, 1)\r
-\r
-\r
-#ifndef POWER2\r
-#define POWER2(power) (1 << (power))\r
-#else\r
-#error use different name for power of 2\r
-#endif\r
-\r
-#ifdef USE_RELAY_MOD_NAME\r
-extern void mtl_log_set_name( char * mod_name );\r
-#endif\r
-\r
-\r
-extern const char* mtl_strerror( call_result_t errnum);\r
-extern const char* mtl_strerror_sym( call_result_t errnum);\r
-extern const char* mtl_basename(const char* filename); /* trim dir-path */\r
-\r
-/******************************************************************************\r
- * Function: mtl_log_set\r
- *\r
- * Description: Setup log print in kernel module.\r
- *\r
- * Parameters:\r
- * layer(IN) (LEN s) char*\r
- * info(IN) (LEN s) char*\r
- *\r
- * Returns:\r
- ******************************************************************************/\r
-void mtl_log_set(char* layer, char *info);\r
-\r
-\r
-extern void mtl_log(const char* layer, mtl_log_types log_type, char sev,\r
- const char *fmt, ...) __attribute__ ((format (printf, 4, 5)));\r
-\r
-extern void mtl_common_cleanup(void);\r
-\r
-/**\r
- * MT_DOWN_XXX\r
- *\r
- * Clears lower 'mask' bit of 'value'.\r
- * \r
- * e.g. MT_MASKX(0xFFFFF,8) -> 0xFFF00\r
- */\r
- \r
-/**\r
- * MT_UP_XXX\r
- *\r
- * Upward aligns 'value' to is lower 'mask' bits.\r
- * \r
- * e.g. MT_UP_ALIGNX(0x1002, 8) -> 0x1100\r
- */\r
-\r
-/* for MT_virt_addr_t type of value */\r
-#define MT_DOWN_ALIGNX_VIRT(value, mask) ((MT_virt_addr_t)(value) & (~((MT_virt_addr_t)0) << (mask)))\r
-#define MT_UP_ALIGNX_VIRT(value, mask) MT_DOWN_ALIGNX_VIRT(((value) + ~(~((MT_virt_addr_t)0) << (mask))), (mask))\r
-\r
-/* for MT_phys_addr_t type of value */\r
-#define MT_DOWN_ALIGNX_PHYS(value, mask) ((MT_phys_addr_t)(value) & (~((MT_phys_addr_t)0) << (mask)))\r
-#define MT_UP_ALIGNX_PHYS(value, mask) MT_DOWN_ALIGNX_PHYS(((value) + ~(~((MT_phys_addr_t)0) << (mask))), (mask))\r
-\r
-/* for u_int32_t type of value */\r
-#define MT_DOWN_ALIGNX_U32(value, mask) ((u_int32_t)(value) & (~((u_int32_t)0) << (mask)))\r
-#define MT_UP_ALIGNX_U32(value, mask) MT_DOWN_ALIGNX_U32(((value) + ~(~((u_int32_t)0) << (mask))), (mask))\r
-\r
-/* for u_int64_t type of value */\r
-#define MT_DOWN_ALIGNX_U64(value, mask) ((u_int64_t)(value) & (~((u_int64_t)0) << (mask)))\r
-#define MT_UP_ALIGNX_U64(value, mask) MT_DOWN_ALIGNX_U64(((value) + ~(~((u_int64_t)0) << (mask))), (mask))\r
-\r
-/* for MT_ulong_ptr_t type of value */\r
-#define MT_DOWN_ALIGNX_ULONG_PTR(value, mask) ((MT_ulong_ptr_t)(value) & (~((MT_ulong_ptr_t)0) << (mask)))\r
-#define MT_UP_ALIGNX_ULONG_PTR(value, mask) MT_DOWN_ALIGNX_ULONG_PTR(((value) + ~(~((MT_ulong_ptr_t)0) << (mask))), (mask))\r
-\r
-/* for MT_size_t type of value */\r
-#define MT_DOWN_ALIGNX_SIZE(value, mask) ((MT_size_t)(value) & (~((MT_size_t)0) << (mask)))\r
-#define MT_UP_ALIGNX_SIZE(value, mask) MT_DOWN_ALIGNX_SIZE(((value) + ~(~((MT_size_t)0) << (mask))), (mask))\r
-\r
-/* for unsigned long type of value */\r
-#define MT_DOWN_ALIGNX_ULONG(value, mask) ((unsigned long)(value) & (~((unsigned long)0) << (mask)))\r
-#define MT_UP_ALIGNX_ULONG(value, mask) MT_DOWN_ALIGNX_ULONG(((value) + ~(~((unsigned long)0) << (mask))), (mask))\r
-\r
-/* for unsigned long type of value , */\r
-/* PLEASE DON'T USE THIS MACRO. IT's KEPT JUST FOR BACKWARD COMPATABILITY REASONS */\r
-#define MT_DOWN_ALIGNX(value, mask) ((unsigned long)(value) & (~((unsigned long)0) << (mask)))\r
-#define MT_UP_ALIGNX(value, mask) MT_DOWN_ALIGNX(((value) + ~(~((unsigned long)0) << (mask))), (mask))\r
-\r
-\r
-enum {\r
- MT_MELLANOX_IEEE_VENDOR_ID = 0x02c9,\r
- MT_MELLANOX_PCI_VENDOR_ID = 0x15B3,\r
- MT_TOPSPIN_PCI_VENDOR_ID = 0x1867\r
-};\r
-\r
-/* some standard macros for tracing */\r
-#define FUNC_IN MTL_DEBUG2("==> %s\n", __func__)\r
-#define FUNC_OUT MTL_DEBUG2("<== %s\n", __func__)\r
-#define MT_RETURN(rc) { FUNC_OUT; \\r
- return (rc); }\r
- \r
-#define MT_RETV { FUNC_OUT ; \\r
- return; }\r
-\r
-\r
-\r
-#if defined(__LINUX__) && defined(MT_KERNEL) && defined(__i386__)\r
-#define STACK_OK ( \\r
- { \\r
- u_int32_t vsp=0, left, ret; \\r
- asm ("movl %%esp, %0;" \\r
- : "=r"(vsp) \\r
- : ); \\r
- left = vsp-((u_int32_t)current+sizeof(struct task_struct)); \\r
- if ( left < 0x400 ) { \\r
- MTL_ERROR1("you have less then 0x400 bytes of stack left\n"); \\r
- ret = 0; \\r
- } \\r
- else { \\r
- MTL_DEBUG1("%s: stack depth left = %d bytes\n", __FUNCTION__, left); \\r
- ret = 1; \\r
- } \\r
- ret; \\r
-} \\r
-)\r
-\r
-#define MT_RETURN_IF_LOW_STACK(stack_watermark) {\\r
- u_int32_t vsp=0, left; \\r
- asm ("movl %%esp, %0;" \\r
- : "=r"(vsp) \\r
- : ); \\r
- left = vsp-((u_int32_t)current+sizeof(struct task_struct)); \\r
- if ( left < stack_watermark) { \\r
- MTL_ERROR1(MT_FLFMT("%s: you have less then %u bytes of stack left (%uB left)\n"),__func__,\\r
- stack_watermark,left); \\r
- return -255;\\r
- }\\r
-}\r
-\r
-#else /* __LINUX__ && defined MT_KERNEL */\r
-#define STACK_OK 1\r
-#define MT_RETURN_IF_LOW_STACK(stack_watermark) do {} while (0)\r
-#endif\r
-\r
-/* an empty macro */\r
-#define EMPTY\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* H_MTL_COMMON_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#ifndef H_MTL_LOG_H\r
-#define H_MTL_LOG_H\r
-\r
-#define MTL_TRACE(S, F, A...) _MTL_TRACE(MTL_MODULE, S, F, ## A)\r
-#define _MTL_TRACE(M, S, F, A...) __MTL_TRACE(M, S, F, ## A)\r
-#define __MTL_TRACE(M, S, F, A...) ___MTL_TRACE(#M, S, F, ## A)\r
-#if 1 <= MAX_TRACE\r
-#define ___MTL_TRACE(M, S, F, A...) mtl_log(M, mtl_log_trace, S, F, ## A)\r
-#else\r
-#define ___MTL_TRACE(M, S, F, A...)\r
-#endif\r
-\r
-#define MTL_TRACE1(F, A...) _MTL_TRACE1(MTL_MODULE, F, ## A)\r
-#define _MTL_TRACE1(M, F, A...) __MTL_TRACE1(M, F, ## A)\r
-#define __MTL_TRACE1(M, F, A...) ___MTL_TRACE1(#M, F, ## A)\r
-#if 1 <= MAX_TRACE\r
-#define ___MTL_TRACE1(M, F, A...) mtl_log(M, mtl_log_trace, '1', F, ## A)\r
-#else\r
-#define ___MTL_TRACE1(M, F, A...)\r
-#endif\r
-\r
-#define MTL_TRACE2(F, A...) _MTL_TRACE2(MTL_MODULE, F, ## A)\r
-#define _MTL_TRACE2(M, F, A...) __MTL_TRACE2(M, F, ## A)\r
-#define __MTL_TRACE2(M, F, A...) ___MTL_TRACE2(#M, F, ## A)\r
-#if 2 <= MAX_TRACE\r
-#define ___MTL_TRACE2(M, F, A...) mtl_log(M, mtl_log_trace, '2', F, ## A)\r
-#else\r
-#define ___MTL_TRACE2(M, F, A...)\r
-#endif\r
-\r
-#define MTL_TRACE3(F, A...) _MTL_TRACE3(MTL_MODULE, F, ## A)\r
-#define _MTL_TRACE3(M, F, A...) __MTL_TRACE3(M, F, ## A)\r
-#define __MTL_TRACE3(M, F, A...) ___MTL_TRACE3(#M, F, ## A)\r
-#if 3 <= MAX_TRACE\r
-#define ___MTL_TRACE3(M, F, A...) mtl_log(M, mtl_log_trace, '3', F, ## A)\r
-#else\r
-#define ___MTL_TRACE3(M, F, A...)\r
-#endif\r
-\r
-#define MTL_TRACE4(F, A...) _MTL_TRACE4(MTL_MODULE, F, ## A)\r
-#define _MTL_TRACE4(M, F, A...) __MTL_TRACE4(M, F, ## A)\r
-#define __MTL_TRACE4(M, F, A...) ___MTL_TRACE4(#M, F, ## A)\r
-#if 4 <= MAX_TRACE\r
-#define ___MTL_TRACE4(M, F, A...) mtl_log(M, mtl_log_trace, '4', F, ## A)\r
-#else\r
-#define ___MTL_TRACE4(M, F, A...)\r
-#endif\r
-\r
-#define MTL_TRACE5(F, A...) _MTL_TRACE5(MTL_MODULE, F, ## A)\r
-#define _MTL_TRACE5(M, F, A...) __MTL_TRACE5(M, F, ## A)\r
-#define __MTL_TRACE5(M, F, A...) ___MTL_TRACE5(#M, F, ## A)\r
-#if 5 <= MAX_TRACE\r
-#define ___MTL_TRACE5(M, F, A...) mtl_log(M, mtl_log_trace, '5', F, ## A)\r
-#else\r
-#define ___MTL_TRACE5(M, F, A...)\r
-#endif\r
-\r
-#define MTL_TRACE6(F, A...) _MTL_TRACE6(MTL_MODULE, F, ## A)\r
-#define _MTL_TRACE6(M, F, A...) __MTL_TRACE6(M, F, ## A)\r
-#define __MTL_TRACE6(M, F, A...) ___MTL_TRACE6(#M, F, ## A)\r
-#if 6 <= MAX_TRACE\r
-#define ___MTL_TRACE6(M, F, A...) mtl_log(M, mtl_log_trace, '6', F, ## A)\r
-#else\r
-#define ___MTL_TRACE6(M, F, A...)\r
-#endif\r
-\r
-#define MTL_TRACE7(F, A...) _MTL_TRACE7(MTL_MODULE, F, ## A)\r
-#define _MTL_TRACE7(M, F, A...) __MTL_TRACE7(M, F, ## A)\r
-#define __MTL_TRACE7(M, F, A...) ___MTL_TRACE7(#M, F, ## A)\r
-#if 7 <= MAX_TRACE\r
-#define ___MTL_TRACE7(M, F, A...) mtl_log(M, mtl_log_trace, '7', F, ## A)\r
-#else\r
-#define ___MTL_TRACE7(M, F, A...)\r
-#endif\r
-\r
-#define MTL_TRACE8(F, A...) _MTL_TRACE8(MTL_MODULE, F, ## A)\r
-#define _MTL_TRACE8(M, F, A...) __MTL_TRACE8(M, F, ## A)\r
-#define __MTL_TRACE8(M, F, A...) ___MTL_TRACE8(#M, F, ## A)\r
-#if 8 <= MAX_TRACE\r
-#define ___MTL_TRACE8(M, F, A...) mtl_log(M, mtl_log_trace, '8', F, ## A)\r
-#else\r
-#define ___MTL_TRACE8(M, F, A...)\r
-#endif\r
-\r
-#define MTL_TRACE9(F, A...) _MTL_TRACE9(MTL_MODULE, F, ## A)\r
-#define _MTL_TRACE9(M, F, A...) __MTL_TRACE9(M, F, ## A)\r
-#define __MTL_TRACE9(M, F, A...) ___MTL_TRACE9(#M, F, ## A)\r
-#if 9 <= MAX_TRACE\r
-#define ___MTL_TRACE9(M, F, A...) mtl_log(M, mtl_log_trace, '9', F, ## A)\r
-#else\r
-#define ___MTL_TRACE9(M, F, A...)\r
-#endif\r
-\r
-#define MTL_DEBUG(S, F, A...) _MTL_DEBUG(MTL_MODULE, S, F, ## A)\r
-#define _MTL_DEBUG(M, S, F, A...) __MTL_DEBUG(M, S, F, ## A)\r
-#define __MTL_DEBUG(M, S, F, A...) ___MTL_DEBUG(#M, S, F, ## A)\r
-#if 1 <= MAX_DEBUG\r
-#define ___MTL_DEBUG(M, S, F, A...) mtl_log(M, mtl_log_debug, S, F, ## A)\r
-#else\r
-#define ___MTL_DEBUG(M, S, F, A...)\r
-#endif\r
-\r
-#define MTL_DEBUG1(F, A...) _MTL_DEBUG1(MTL_MODULE, F, ## A)\r
-#define _MTL_DEBUG1(M, F, A...) __MTL_DEBUG1(M, F, ## A)\r
-#define __MTL_DEBUG1(M, F, A...) ___MTL_DEBUG1(#M, F, ## A)\r
-#if 1 <= MAX_DEBUG\r
-#define ___MTL_DEBUG1(M, F, A...) mtl_log(M, mtl_log_debug, '1', F, ## A)\r
-#else\r
-#define ___MTL_DEBUG1(M, F, A...)\r
-#endif\r
-\r
-#define MTL_DEBUG2(F, A...) _MTL_DEBUG2(MTL_MODULE, F, ## A)\r
-#define _MTL_DEBUG2(M, F, A...) __MTL_DEBUG2(M, F, ## A)\r
-#define __MTL_DEBUG2(M, F, A...) ___MTL_DEBUG2(#M, F, ## A)\r
-#if 2 <= MAX_DEBUG\r
-#define ___MTL_DEBUG2(M, F, A...) mtl_log(M, mtl_log_debug, '2', F, ## A)\r
-#else\r
-#define ___MTL_DEBUG2(M, F, A...)\r
-#endif\r
-\r
-#define MTL_DEBUG3(F, A...) _MTL_DEBUG3(MTL_MODULE, F, ## A)\r
-#define _MTL_DEBUG3(M, F, A...) __MTL_DEBUG3(M, F, ## A)\r
-#define __MTL_DEBUG3(M, F, A...) ___MTL_DEBUG3(#M, F, ## A)\r
-#if 3 <= MAX_DEBUG\r
-#define ___MTL_DEBUG3(M, F, A...) mtl_log(M, mtl_log_debug, '3', F, ## A)\r
-#else\r
-#define ___MTL_DEBUG3(M, F, A...)\r
-#endif\r
-\r
-#define MTL_DEBUG4(F, A...) _MTL_DEBUG4(MTL_MODULE, F, ## A)\r
-#define _MTL_DEBUG4(M, F, A...) __MTL_DEBUG4(M, F, ## A)\r
-#define __MTL_DEBUG4(M, F, A...) ___MTL_DEBUG4(#M, F, ## A)\r
-#if 4 <= MAX_DEBUG\r
-#define ___MTL_DEBUG4(M, F, A...) mtl_log(M, mtl_log_debug, '4', F, ## A)\r
-#else\r
-#define ___MTL_DEBUG4(M, F, A...)\r
-#endif\r
-\r
-#define MTL_DEBUG5(F, A...) _MTL_DEBUG5(MTL_MODULE, F, ## A)\r
-#define _MTL_DEBUG5(M, F, A...) __MTL_DEBUG5(M, F, ## A)\r
-#define __MTL_DEBUG5(M, F, A...) ___MTL_DEBUG5(#M, F, ## A)\r
-#if 5 <= MAX_DEBUG\r
-#define ___MTL_DEBUG5(M, F, A...) mtl_log(M, mtl_log_debug, '5', F, ## A)\r
-#else\r
-#define ___MTL_DEBUG5(M, F, A...)\r
-#endif\r
-\r
-#define MTL_DEBUG6(F, A...) _MTL_DEBUG6(MTL_MODULE, F, ## A)\r
-#define _MTL_DEBUG6(M, F, A...) __MTL_DEBUG6(M, F, ## A)\r
-#define __MTL_DEBUG6(M, F, A...) ___MTL_DEBUG6(#M, F, ## A)\r
-#if 6 <= MAX_DEBUG\r
-#define ___MTL_DEBUG6(M, F, A...) mtl_log(M, mtl_log_debug, '6', F, ## A)\r
-#else\r
-#define ___MTL_DEBUG6(M, F, A...)\r
-#endif\r
-\r
-#define MTL_DEBUG7(F, A...) _MTL_DEBUG7(MTL_MODULE, F, ## A)\r
-#define _MTL_DEBUG7(M, F, A...) __MTL_DEBUG7(M, F, ## A)\r
-#define __MTL_DEBUG7(M, F, A...) ___MTL_DEBUG7(#M, F, ## A)\r
-#if 7 <= MAX_DEBUG\r
-#define ___MTL_DEBUG7(M, F, A...) mtl_log(M, mtl_log_debug, '7', F, ## A)\r
-#else\r
-#define ___MTL_DEBUG7(M, F, A...)\r
-#endif\r
-\r
-#define MTL_DEBUG8(F, A...) _MTL_DEBUG8(MTL_MODULE, F, ## A)\r
-#define _MTL_DEBUG8(M, F, A...) __MTL_DEBUG8(M, F, ## A)\r
-#define __MTL_DEBUG8(M, F, A...) ___MTL_DEBUG8(#M, F, ## A)\r
-#if 8 <= MAX_DEBUG\r
-#define ___MTL_DEBUG8(M, F, A...) mtl_log(M, mtl_log_debug, '8', F, ## A)\r
-#else\r
-#define ___MTL_DEBUG8(M, F, A...)\r
-#endif\r
-\r
-#define MTL_DEBUG9(F, A...) _MTL_DEBUG9(MTL_MODULE, F, ## A)\r
-#define _MTL_DEBUG9(M, F, A...) __MTL_DEBUG9(M, F, ## A)\r
-#define __MTL_DEBUG9(M, F, A...) ___MTL_DEBUG9(#M, F, ## A)\r
-#if 9 <= MAX_DEBUG\r
-#define ___MTL_DEBUG9(M, F, A...) mtl_log(M, mtl_log_debug, '9', F, ## A)\r
-#else\r
-#define ___MTL_DEBUG9(M, F, A...)\r
-#endif\r
-\r
-#define MTL_ERROR(S, F, A...) _MTL_ERROR(MTL_MODULE, S, F, ## A)\r
-#define _MTL_ERROR(M, S, F, A...) __MTL_ERROR(M, S, F, ## A)\r
-#define __MTL_ERROR(M, S, F, A...) ___MTL_ERROR(#M, S, F, ## A)\r
-#if 1 <= MAX_ERROR\r
-#define ___MTL_ERROR(M, S, F, A...) mtl_log(M, mtl_log_error, S, F, ## A)\r
-#else\r
-#define ___MTL_ERROR(M, S, F, A...)\r
-#endif\r
-\r
-#define MTL_ERROR1(F, A...) _MTL_ERROR1(MTL_MODULE, F, ## A)\r
-#define _MTL_ERROR1(M, F, A...) __MTL_ERROR1(M, F, ## A)\r
-#define __MTL_ERROR1(M, F, A...) ___MTL_ERROR1(#M, F, ## A)\r
-#if 1 <= MAX_ERROR\r
-#define ___MTL_ERROR1(M, F, A...) mtl_log(M, mtl_log_error, '1', F, ## A)\r
-#else\r
-#define ___MTL_ERROR1(M, F, A...)\r
-#endif\r
-\r
-#define MTL_ERROR2(F, A...) _MTL_ERROR2(MTL_MODULE, F, ## A)\r
-#define _MTL_ERROR2(M, F, A...) __MTL_ERROR2(M, F, ## A)\r
-#define __MTL_ERROR2(M, F, A...) ___MTL_ERROR2(#M, F, ## A)\r
-#if 2 <= MAX_ERROR\r
-#define ___MTL_ERROR2(M, F, A...) mtl_log(M, mtl_log_error, '2', F, ## A)\r
-#else\r
-#define ___MTL_ERROR2(M, F, A...)\r
-#endif\r
-\r
-#define MTL_ERROR3(F, A...) _MTL_ERROR3(MTL_MODULE, F, ## A)\r
-#define _MTL_ERROR3(M, F, A...) __MTL_ERROR3(M, F, ## A)\r
-#define __MTL_ERROR3(M, F, A...) ___MTL_ERROR3(#M, F, ## A)\r
-#if 3 <= MAX_ERROR\r
-#define ___MTL_ERROR3(M, F, A...) mtl_log(M, mtl_log_error, '3', F, ## A)\r
-#else\r
-#define ___MTL_ERROR3(M, F, A...)\r
-#endif\r
-\r
-#define MTL_ERROR4(F, A...) _MTL_ERROR4(MTL_MODULE, F, ## A)\r
-#define _MTL_ERROR4(M, F, A...) __MTL_ERROR4(M, F, ## A)\r
-#define __MTL_ERROR4(M, F, A...) ___MTL_ERROR4(#M, F, ## A)\r
-#if 4 <= MAX_ERROR\r
-#define ___MTL_ERROR4(M, F, A...) mtl_log(M, mtl_log_error, '4', F, ## A)\r
-#else\r
-#define ___MTL_ERROR4(M, F, A...)\r
-#endif\r
-\r
-#define MTL_ERROR5(F, A...) _MTL_ERROR5(MTL_MODULE, F, ## A)\r
-#define _MTL_ERROR5(M, F, A...) __MTL_ERROR5(M, F, ## A)\r
-#define __MTL_ERROR5(M, F, A...) ___MTL_ERROR5(#M, F, ## A)\r
-#if 5 <= MAX_ERROR\r
-#define ___MTL_ERROR5(M, F, A...) mtl_log(M, mtl_log_error, '5', F, ## A)\r
-#else\r
-#define ___MTL_ERROR5(M, F, A...)\r
-#endif\r
-\r
-#define MTL_ERROR6(F, A...) _MTL_ERROR6(MTL_MODULE, F, ## A)\r
-#define _MTL_ERROR6(M, F, A...) __MTL_ERROR6(M, F, ## A)\r
-#define __MTL_ERROR6(M, F, A...) ___MTL_ERROR6(#M, F, ## A)\r
-#if 6 <= MAX_ERROR\r
-#define ___MTL_ERROR6(M, F, A...) mtl_log(M, mtl_log_error, '6', F, ## A)\r
-#else\r
-#define ___MTL_ERROR6(M, F, A...)\r
-#endif\r
-\r
-#define MTL_ERROR7(F, A...) _MTL_ERROR7(MTL_MODULE, F, ## A)\r
-#define _MTL_ERROR7(M, F, A...) __MTL_ERROR7(M, F, ## A)\r
-#define __MTL_ERROR7(M, F, A...) ___MTL_ERROR7(#M, F, ## A)\r
-#if 7 <= MAX_ERROR\r
-#define ___MTL_ERROR7(M, F, A...) mtl_log(M, mtl_log_error, '7', F, ## A)\r
-#else\r
-#define ___MTL_ERROR7(M, F, A...)\r
-#endif\r
-\r
-#define MTL_ERROR8(F, A...) _MTL_ERROR8(MTL_MODULE, F, ## A)\r
-#define _MTL_ERROR8(M, F, A...) __MTL_ERROR8(M, F, ## A)\r
-#define __MTL_ERROR8(M, F, A...) ___MTL_ERROR8(#M, F, ## A)\r
-#if 8 <= MAX_ERROR\r
-#define ___MTL_ERROR8(M, F, A...) mtl_log(M, mtl_log_error, '8', F, ## A)\r
-#else\r
-#define ___MTL_ERROR8(M, F, A...)\r
-#endif\r
-\r
-#define MTL_ERROR9(F, A...) _MTL_ERROR9(MTL_MODULE, F, ## A)\r
-#define _MTL_ERROR9(M, F, A...) __MTL_ERROR9(M, F, ## A)\r
-#define __MTL_ERROR9(M, F, A...) ___MTL_ERROR9(#M, F, ## A)\r
-#if 9 <= MAX_ERROR\r
-#define ___MTL_ERROR9(M, F, A...) mtl_log(M, mtl_log_error, '9', F, ## A)\r
-#else\r
-#define ___MTL_ERROR9(M, F, A...)\r
-#endif\r
-\r
-#endif /* H_MTL_LOG_H */\r
-EXPORTS\r
- mt_strtoull\r
- mtl_log\r
- mtl_basename\r
- mtl_strerror\r
- mtl_strerror_sym\r
- DebugPrint\r
-; windows implementation of tracing\r
- mtl_log_set_name\r
- NT_trace\r
- NT_trace1\r
- NT_trace2\r
- NT_trace3\r
- NT_trace4\r
- NT_trace5\r
- NT_trace6\r
- NT_trace7\r
- NT_trace8\r
- NT_trace9\r
- NT_error\r
- NT_error1\r
- NT_error2\r
- NT_error3\r
- NT_error4\r
- NT_error5\r
- NT_error6\r
- NT_error7\r
- NT_error8\r
- NT_error9\r
- NT_debug\r
- NT_debug1\r
- NT_debug2\r
- NT_debug3\r
- NT_debug4\r
- NT_debug5\r
- NT_debug6\r
- NT_debug7\r
- NT_debug8\r
- NT_debug9\r
- cur_module\r
-EXPORTS\r
- DllInitialize private\r
- DllUnload private\r
- mtl_basename\r
- mtl_strerror\r
- mtl_strerror_sym\r
- mtl_log_set\r
- mtl_log\r
- mtl_log_vmalloc\r
- mtl_log_vfree\r
- mtl_log_kmalloc\r
- mtl_log_kfree\r
-; windows implementation of tracing \r
- mtl_log_set_name\r
- NT_trace\r
- NT_trace1\r
- NT_trace2\r
- NT_trace3\r
- NT_trace4\r
- NT_trace5\r
- NT_trace6\r
- NT_trace7\r
- NT_trace8\r
- NT_trace9\r
- NT_error\r
- NT_error1\r
- NT_error2\r
- NT_error3\r
- NT_error4\r
- NT_error5\r
- NT_error6\r
- NT_error7\r
- NT_error8\r
- NT_error9\r
- NT_debug\r
- NT_debug1\r
- NT_debug2\r
- NT_debug3\r
- NT_debug4\r
- NT_debug5\r
- NT_debug6\r
- NT_debug7\r
- NT_debug8\r
- NT_debug9\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MTL_LOG_WIN_H\r
-#define H_MTL_LOG_WIN_H\r
-\r
-#ifndef MTL_MODULE \r
-#define MTL_MODULE __FILE__\r
-#endif\r
-#define MAKE_MOD_NAME _MAKE_MOD_NAME(MTL_MODULE)\r
-#define _MAKE_MOD_NAME(a) __MAKE_MOD_NAME(a)\r
-#define __MAKE_MOD_NAME(a) #a\r
-\r
-#ifdef USE_RELAY_MOD_NAME\r
-#define RELAY_MOD_NAME mtl_log_set_name( MAKE_MOD_NAME );\r
-#else\r
-#define RELAY_MOD_NAME\r
-#endif\r
-\r
-void NT_trace(char sev, char *fmt, ...);\r
-void NT_trace1(char *fmt, ...);\r
-void NT_trace2(char *fmt, ...);\r
-void NT_trace3(char *fmt, ...);\r
-void NT_trace4(char *fmt, ...);\r
-void NT_trace5(char *fmt, ...);\r
-void NT_trace6(char *fmt, ...);\r
-void NT_trace7(char *fmt, ...);\r
-void NT_trace8(char *fmt, ...);\r
-void NT_trace9(char *fmt, ...);\r
-void NT_debug(char sev, char *fmt, ...);\r
-void NT_debug1(char *fmt, ...);\r
-void NT_debug2(char *fmt, ...);\r
-void NT_debug3(char *fmt, ...);\r
-void NT_debug4(char *fmt, ...);\r
-void NT_debug5(char *fmt, ...);\r
-void NT_debug6(char *fmt, ...);\r
-void NT_debug7(char *fmt, ...);\r
-void NT_debug8(char *fmt, ...);\r
-void NT_debug9(char *fmt, ...);\r
-void NT_error(char sev, char *fmt, ...);\r
-void NT_error1(char *fmt, ...);\r
-void NT_error2(char *fmt, ...);\r
-void NT_error3(char *fmt, ...);\r
-void NT_error4(char *fmt, ...);\r
-void NT_error5(char *fmt, ...);\r
-void NT_error6(char *fmt, ...);\r
-void NT_error7(char *fmt, ...);\r
-void NT_error8(char *fmt, ...);\r
-void NT_error9(char *fmt, ...);\r
-\r
-static inline void empty_function( char *fmt, ... ) { UNREFERENCED_PARAMETER( fmt ); }\r
-static inline void empty_function1( const int level, ... ) { UNREFERENCED_PARAMETER( level ); }\r
-\r
-\r
-#if 1 <= MAX_TRACE\r
-#define MTL_TRACE RELAY_MOD_NAME NT_trace\r
-#else\r
-#define MTL_TRACE empty_function1\r
-#endif\r
-\r
-#if 1 <= MAX_TRACE\r
-#define MTL_TRACE1 RELAY_MOD_NAME NT_trace1\r
-#else\r
-#define MTL_TRACE1 empty_function\r
-#endif\r
-\r
-#if 2 <= MAX_TRACE\r
-#define MTL_TRACE2 RELAY_MOD_NAME NT_trace2\r
-#else\r
-#define MTL_TRACE2 empty_function\r
-#endif\r
-\r
-#if 3 <= MAX_TRACE\r
-#define MTL_TRACE3 RELAY_MOD_NAME NT_trace3\r
-#else\r
-#define MTL_TRACE3 empty_function\r
-#endif\r
-\r
-#if 4 <= MAX_TRACE\r
-#define MTL_TRACE4 RELAY_MOD_NAME NT_trace4\r
-#else\r
-#define MTL_TRACE4 empty_function\r
-#endif\r
-\r
-#if 5 <= MAX_TRACE\r
-#define MTL_TRACE5 RELAY_MOD_NAME NT_trace5\r
-#else\r
-#define MTL_TRACE5 empty_function\r
-#endif\r
-\r
-#if 6 <= MAX_TRACE\r
-#define MTL_TRACE6 RELAY_MOD_NAME NT_trace6\r
-#else\r
-#define MTL_TRACE6 empty_function\r
-#endif\r
-\r
-#if 7 <= MAX_TRACE\r
-#define MTL_TRACE7 RELAY_MOD_NAME NT_trace7\r
-#else\r
-#define MTL_TRACE7 empty_function\r
-#endif\r
-\r
-#if 8 <= MAX_TRACE\r
-#define MTL_TRACE8 RELAY_MOD_NAME NT_trace8\r
-#else\r
-#define MTL_TRACE8 empty_function\r
-#endif\r
-\r
-#if 9 <= MAX_TRACE\r
-#define MTL_TRACE9 RELAY_MOD_NAME NT_trace9\r
-#else\r
-#define MTL_TRACE9 empty_function\r
-#endif\r
-\r
-#if 1 <= MAX_DEBUG\r
-#define MTL_DEBUG RELAY_MOD_NAME NT_debug\r
-#else\r
-#define MTL_DEBUG empty_function1\r
-#endif\r
-\r
-#if 1 <= MAX_DEBUG\r
-#define MTL_DEBUG1 RELAY_MOD_NAME NT_debug1\r
-#else\r
-#define MTL_DEBUG1 empty_function\r
-#endif\r
-\r
-#if 2 <= MAX_DEBUG\r
-#define MTL_DEBUG2 RELAY_MOD_NAME NT_debug2\r
-#else\r
-#define MTL_DEBUG2 empty_function\r
-#endif\r
-\r
-#if 3 <= MAX_DEBUG\r
-#define MTL_DEBUG3 RELAY_MOD_NAME NT_debug3\r
-#else\r
-#define MTL_DEBUG3 empty_function\r
-#endif\r
-\r
-#if 4 <= MAX_DEBUG\r
-#define MTL_DEBUG4 RELAY_MOD_NAME NT_debug4\r
-#else\r
-#define MTL_DEBUG4 empty_function\r
-#endif\r
-\r
-#if 5 <= MAX_DEBUG\r
-#define MTL_DEBUG5 RELAY_MOD_NAME NT_debug5\r
-#else\r
-#define MTL_DEBUG5 empty_function\r
-#endif\r
-\r
-#if 6 <= MAX_DEBUG\r
-#define MTL_DEBUG6 RELAY_MOD_NAME NT_debug6\r
-#else\r
-#define MTL_DEBUG6 empty_function\r
-#endif\r
-\r
-#if 7 <= MAX_DEBUG\r
-#define MTL_DEBUG7 RELAY_MOD_NAME NT_debug7\r
-#else\r
-#define MTL_DEBUG7 empty_function\r
-#endif\r
-\r
-#if 8 <= MAX_DEBUG\r
-#define MTL_DEBUG8 RELAY_MOD_NAME NT_debug8\r
-#else\r
-#define MTL_DEBUG8 empty_function\r
-#endif\r
-\r
-#if 9 <= MAX_DEBUG\r
-#define MTL_DEBUG9 RELAY_MOD_NAME NT_debug9\r
-#else\r
-#define MTL_DEBUG9 empty_function\r
-#endif\r
-\r
-#if 1 <= MAX_ERROR\r
-#define MTL_ERROR RELAY_MOD_NAME NT_error\r
-#else\r
-#define MTL_ERROR empty_function1\r
-#endif\r
-\r
-#if 1 <= MAX_ERROR\r
-#define MTL_ERROR1 RELAY_MOD_NAME NT_error1\r
-#else\r
-#define MTL_ERROR1 empty_function\r
-#endif\r
-\r
-#if 2 <= MAX_ERROR\r
-#define MTL_ERROR2 RELAY_MOD_NAME NT_error2\r
-#else\r
-#define MTL_ERROR2 empty_function\r
-#endif\r
-\r
-#if 3 <= MAX_ERROR\r
-#define MTL_ERROR3 RELAY_MOD_NAME NT_error3\r
-#else\r
-#define MTL_ERROR3 empty_function\r
-#endif\r
-\r
-#if 4 <= MAX_ERROR\r
-#define MTL_ERROR4 RELAY_MOD_NAME NT_error4\r
-#else\r
-#define MTL_ERROR4 empty_function\r
-#endif\r
-\r
-#if 5 <= MAX_ERROR\r
-#define MTL_ERROR5 RELAY_MOD_NAME NT_error5\r
-#else\r
-#define MTL_ERROR5 empty_function\r
-#endif\r
-\r
-#if 6 <= MAX_ERROR\r
-#define MTL_ERROR6 RELAY_MOD_NAME NT_error6\r
-#else\r
-#define MTL_ERROR6 empty_function\r
-#endif\r
-\r
-#if 7 <= MAX_ERROR\r
-#define MTL_ERROR7 RELAY_MOD_NAME NT_error7\r
-#else\r
-#define MTL_ERROR7 empty_function\r
-#endif\r
-\r
-#if 8 <= MAX_ERROR\r
-#define MTL_ERROR8 RELAY_MOD_NAME NT_error8\r
-#else\r
-#define MTL_ERROR8 empty_function\r
-#endif\r
-\r
-#if 9 <= MAX_ERROR\r
-#define MTL_ERROR9 RELAY_MOD_NAME NT_error9\r
-#else\r
-#define MTL_ERROR9 empty_function\r
-#endif\r
-\r
-#endif\r
-/*\r
- This software is available to you under a choice of one of two\r
- licenses. You may choose to be licensed under the terms of the GNU\r
- General Public License (GPL) Version 2, available at\r
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD\r
- license, available in the LICENSE.TXT file accompanying this\r
- software. These details are also available at\r
- <http://openib.org/license.html>.\r
-\r
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- SOFTWARE.\r
-\r
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.\r
-*/\r
-\r
-\r
-\r
-#ifndef H_MT_BIT_OPS_H\r
-#define H_MT_BIT_OPS_H\r
-\r
-#include <complib/cl_byteswap.h>\r
-\r
-\r
-/*****************************************************************************************\r
- * Bit manipulation macros\r
- *****************************************************************************************/\r
-\r
-/* MASK generate a bit mask S bits width */\r
-#define MASK32(S) ( ((u_int32_t) ~0L) >> (32-(S)) )\r
-\r
-/*\r
- * BITS generate a bit mask with bits O+S..O set (assumes 32 bit integer).\r
- * numbering bits as following: 31........................76543210\r
- */\r
-#define BITS32(O,S) ( MASK32(S) << (O) )\r
-\r
-/* \r
- * MT_EXTRACT32 macro extracts S bits from (u_int32_t)W with offset O \r
- * and shifts them O places to the right (right justifies the field extracted).\r
- */\r
-#define MT_EXTRACT32(W,O,S) ( ((W)>>(O)) & MASK32(S) )\r
-\r
-/*\r
- * MT_INSERT32 macro inserts S bits with offset O from field F into word W (u_int32_t)\r
- */\r
-#define MT_INSERT32(W,F,O,S) ((W)= ( ( (W) & (~BITS32(O,S)) ) | (((F) & MASK32(S))<<(O)) ))\r
-\r
-/*\r
- * MT_INSERT32 macro inserts S bits with offset O from field F into word W (u_int32_t)\r
- */\r
-#define MT_INSERT32_BE(W,F,O,S) ((W)= ( ( (W) & CL_HTON32(~BITS32(O,S)) ) | cl_ntoh32(((F) & MASK32(S))<<(O)) ))\r
-\r
-/*\r
- * MT_EXTRACT_ARRAY32 macro is similar to EXTRACT but works on an array of (u_int32_t),\r
- * thus offset may be larger than 32 (but not size).\r
- */\r
-#define MT_EXTRACT_ARRAY32(A,O,S) MT_EXTRACT32(((u_int32_t*)A)[O >> 5],(O & MASK32(5)),S)\r
-\r
-/*\r
- * MT_INSERT_ARRAY32 macro is similar to INSERT but works on an array of (u_int32_t),\r
- * thus offset may be larger than 32 (but not size).\r
- */\r
-#define MT_INSERT_ARRAY32(A,F,O,S) MT_INSERT32(((u_int32_t*)A)[O >> 5],F,(O & MASK32(5)),S)\r
-\r
-/*\r
- * MT_INSERT_ARRAY32 macro is similar to INSERT but works on an array of (u_int32_t),\r
- * thus offset may be larger than 32 (but not size).\r
- */\r
-#define MT_INSERT_ARRAY32_BE(A,F,O,S) MT_INSERT32_BE(((u_int32_t*)A)[O >> 5],F,(O & MASK32(5)),S)\r
-\r
-\r
-/* swap 32 bit number */\r
-#define mswab32(x) ((((x) >> 24)&0xff) | (((x) >> 8)&0xff00) | (((x) << 8)&0xff0000) | (((x) << 24)&0xff000000))\r
-\r
-\r
-#endif /* H_MTL_COMMON_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_IB_DEFS_H\r
-#define H_IB_DEFS_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-#include <mtl_types.h>\r
-\r
-typedef u_int8_t IB_port_t;\r
-#define NULL_IB_PORT 0xFF\r
-\r
-typedef u_int16_t IB_lid_t;\r
-typedef u_int8_t IB_gid_t[16]; /* GID (aka IPv6) H-to-L (big) (network) endianess */\r
-\r
-/* IB-spec. Vol.1 (chapter 4): LID ranges */\r
-#define MIN_UC_LID 0x0001 /* Unicast LID limits */\r
-#define MAX_UC_LID 0xBFFF\r
-#define MIN_MC_LID 0xC000 /* Multicast limits */\r
-#define MAX_MC_LID 0xFFFE\r
-#define PERMIS_LID 0xFFFF /* Permissive DLID */\r
-\r
-/* Special Multicast QP num */\r
-#define IB_MULTICAST_QP 0xFFFFFF\r
-#define IB_VALID_MULTICAST_GID(gid) ((gid)[0] == 0xFF)\r
-#define IB_VALID_MULTICAST_LID(lid) (((lid) >= MIN_MC_LID) && ((lid) <= MIN_MC_LID))\r
-\r
-\r
-typedef u_int32_t IB_wqpn_t; /* Work QP number: Only 24 LSbits */\r
-typedef u_int32_t IB_eecn_t; /* EE Context number: Only 24 LSbits */\r
-typedef u_int8_t IB_guid_t[8]; /* EUI-64: Big-Endinan (H-to-L) */\r
-typedef u_int8_t IB_gid_prefix_t[8]; /* EUI-64: Big-Endinan (H-to-L) */\r
-typedef u_int8_t IB_sl_t; /* 0-15 */\r
-typedef u_int8_t IB_vl_t; /* 0-15 */\r
-typedef u_int8_t IB_arbitration_weight_t;\r
-typedef enum{PRIO_HIGH=0,PRIO_LOW=1} IB_arbitration_prio_t;\r
-typedef u_int8_t IB_high_prio_limit_t;\r
-typedef u_int64_t IB_virt_addr_t;\r
-typedef u_int32_t IB_rkey_t;\r
-typedef u_int16_t IB_pkey_t;\r
-typedef u_int32_t IB_qkey_t;\r
-\r
-/*** Note *** The following enum must be maintained zero based without holes */\r
-enum { IB_TS_RC, IB_TS_RD, IB_TS_UC, IB_TS_UD, IB_TS_RAW };\r
-typedef u_int32_t IB_ts_t;\r
-\r
-\r
-\r
-#define INVALID_PKEY ((IB_pkey_t)0) /* invalid PKEY. 0x8000 is also invalid but we'll use 0 */\r
-\r
-typedef u_int32_t IB_psn_t;\r
-\r
-typedef u_int8_t IB_link_width_t; /* Set to a combination of following masks ("OR"ed) */\r
-#define W1X 1\r
-#define W4X 2\r
-#define W12X 8\r
-#define W_SET2SUPPORTED 255 /* Set LinkWidthEnabled to LinkWidthSupported */\r
-\r
-/* 9.7.6.1.3 DETECTING LOST ACKNOWLEDGE MESSAGES AND TIMEOUTS (C9-140)*/\r
-#define IB_LOCAL_ACK_TIMEOUT_NUM_BITS 5\r
-\r
-/* IB-spec. 9.7.5.2.8, table 45 \r
- * RNR timer values symbols/macros use the convention: IB_RNR_NAK_TIMER_MMM_mm\r
- * for the encoding of MMM.mm milliseconds\r
- */\r
-#define IB_RNR_NAK_TIMER_NUM_BITS 5\r
-enum {\r
- IB_RNR_NAK_TIMER_655_36 = 0,\r
- IB_RNR_NAK_TIMER_0_01 = 1,\r
- IB_RNR_NAK_TIMER_0_02 = 2,\r
- IB_RNR_NAK_TIMER_0_03 = 3,\r
- IB_RNR_NAK_TIMER_0_04 = 4,\r
- IB_RNR_NAK_TIMER_0_06 = 5,\r
- IB_RNR_NAK_TIMER_0_08 = 6,\r
- IB_RNR_NAK_TIMER_0_12 = 7,\r
- IB_RNR_NAK_TIMER_0_16 = 8,\r
- IB_RNR_NAK_TIMER_0_24 = 9,\r
- IB_RNR_NAK_TIMER_0_32 = 10,\r
- IB_RNR_NAK_TIMER_0_48 = 11,\r
- IB_RNR_NAK_TIMER_0_64 = 12,\r
- IB_RNR_NAK_TIMER_0_96 = 13,\r
- IB_RNR_NAK_TIMER_1_28 = 14,\r
- IB_RNR_NAK_TIMER_1_92 = 15,\r
- IB_RNR_NAK_TIMER_2_56 = 16,\r
- IB_RNR_NAK_TIMER_3_84 = 17,\r
- IB_RNR_NAK_TIMER_5_12 = 18,\r
- IB_RNR_NAK_TIMER_7_68 = 19,\r
- IB_RNR_NAK_TIMER_10_24 = 20,\r
- IB_RNR_NAK_TIMER_15_36 = 21,\r
- IB_RNR_NAK_TIMER_20_48 = 22,\r
- IB_RNR_NAK_TIMER_30_72 = 23,\r
- IB_RNR_NAK_TIMER_40_96 = 24,\r
- IB_RNR_NAK_TIMER_61_44 = 25,\r
- IB_RNR_NAK_TIMER_81_92 = 26,\r
- IB_RNR_NAK_TIMER_122_88 = 27,\r
- IB_RNR_NAK_TIMER_163_84 = 28,\r
- IB_RNR_NAK_TIMER_245_76 = 29,\r
- IB_RNR_NAK_TIMER_327_68 = 30,\r
- IB_RNR_NAK_TIMER_491_52 = 31\r
-};\r
-typedef u_int32_t IB_rnr_nak_timer_code_t;\r
-\r
-typedef enum {\r
- S_NOP=0,\r
- S2GB5=1\r
-} IB_link_speed_t;\r
-\r
-typedef enum {\r
- PORT_NOP=0, /* No state change */\r
- PORT_DOWN=1,\r
- PORT_INITIALIZE=2,\r
- PORT_ARMED=3,\r
- PORT_ACTIVE=4\r
-} IB_port_state_t;\r
-\r
-typedef enum {\r
- PHY_NOP=0, /* No state change */\r
- PHY_SLEEP=1,\r
- PHY_POLLING=2,\r
- PHY_DISABLED=3,\r
- PHY_PORT_CONF_TRAINING=4,\r
- PHY_LINK_UP=5,\r
- PHY_LINK_ERR_REC0=6\r
-} IB_phy_state_t;\r
-\r
-enum{MTU256=1,MTU512=2,MTU1024=3,MTU2048=4,MTU4096=5};\r
-typedef u_int32_t IB_mtu_t;\r
-\r
-typedef enum{VL0=1,VL0_1=2,VL0_3=3,VL0_7=4,VL0_14=5} IB_vl_cap_t;\r
-\r
-typedef u_int8_t IB_static_rate_t; /* IPD encoding: IB-spec. 9.11.1, table 63 */\r
-\r
-typedef enum{NODE_CA=1,NODE_SWITCH=2,NODE_ROUTER=3} IB_node_type_t;\r
- \r
-typedef u_int16_t IB_dev_id_t;\r
- \r
-typedef enum {\r
-/* 0: Reserved */\r
-/* 1: */ IB_CAP_MASK_IS_SM = (1<<1),\r
-/* 2: */ IB_CAP_MASK_IS_NOTICE_SUP = (1<<2),\r
-/* 3: */ IB_CAP_MASK_IS_TRAP_SUP = (1<<3),\r
-/* 4:Reserved */\r
-/* 5: */ IB_CAP_MASK_IS_AUTO_MIGR_SUP = (1<<5),\r
-/* 6: */ IB_CAP_MASK_IS_SL_MAP_SUP = (1<<6),\r
-/* 7: */ IB_CAP_MASK_IS_MKEY_NVRAM = (1<<7),\r
-/* 8: */ IB_CAP_MASK_IS_PKEY_NVRAM = (1<<8),\r
-/* 9: */ IB_CAP_MASK_IS_LED_INFO_SUP = (1<<9),\r
-/*10: */ IB_CAP_MASK_IS_SM_DISABLED = (1<<10),\r
-/*11: */ IB_CAP_MASK_IS_SYS_IMAGE_GUID_SUP = (1<<11),\r
-/*12: */ IB_CAP_MASK_IS_PKEY_SW_EXT_PORT_TRAP_SUP = (1<<12),\r
-/*13 - 15: RESERVED */\r
-/*16: */ IB_CAP_MASK_IS_CONN_MGMT_SUP = (1<<16),\r
-/*17: */ IB_CAP_MASK_IS_SNMP_TUNN_SUP = (1<<17),\r
-/*18: */ IB_CAP_MASK_IS_REINIT_SUP = (1<<18),\r
-/*19: */ IB_CAP_MASK_IS_DEVICE_MGMT_SUP = (1<<19),\r
-/*20: */ IB_CAP_MASK_IS_VENDOR_CLS_SUP = (1<<20),\r
-/*21: */ IB_CAP_MASK_IS_DR_NOTICE_SUP = (1<<21),\r
-/*22: */ IB_CAP_MASK_IS_CAP_MASK_NOTICE_SUP = (1<<22),\r
-/*23: */ IB_CAP_MASK_IS_BOOT_MGMT_SUP = (1<<23),\r
-/*24: */ IB_CAP_MASK_IS_LINK_ROUND_TRIP_LATENCY_SUP = (1<<24), //???? NEW\r
-/*25: */ IB_CAP_MASK_IS_CLIENT_REREGISTRATION_SUP = (1<<25)\r
-/*26 - 31: RESERVED */\r
-\r
-} IB_capability_mask_bits_t;\r
-\r
-\r
-typedef u_int32_t IB_port_cap_mask_t; /* To be used with flags in IB_capability_mask_bits_t */\r
-\r
-#define IB_CAP_MASK_CLR_ALL(mask) ((mask)=0)\r
-#define IB_CAP_MASK_SET(mask,attr) ((mask)|=(attr))\r
-#define IB_CAP_MASK_CLR(mask,attr) ((mask)&=(~(attr)))\r
-#define IB_CAP_IS_SET(mask,attr) (((mask)&(attr))!=0)\r
-/*\r
- * This is an internal representation of PortInfo. \r
- * It does not map directly to PortInfo bits.\r
- */\r
-struct IB_port_info_st {\r
- u_int64_t m_key;\r
- IB_gid_prefix_t gid_prefix; /* Big-endinan (H-to-L) */\r
- IB_lid_t lid;\r
- IB_lid_t master_sm_lid;\r
- IB_port_cap_mask_t capability_mask;\r
- u_int16_t diag_code;\r
- u_int16_t m_key_lease_period;\r
- IB_port_t local_port_num;\r
- IB_link_width_t link_width_enabled;\r
- IB_link_width_t link_width_supported;\r
- IB_link_width_t link_width_active;\r
- IB_link_speed_t link_speed_supported;\r
- IB_port_state_t port_state;\r
- IB_phy_state_t phy_state;\r
- IB_phy_state_t down_default_state;\r
- u_int8_t m_key_protect; /* 0-3 */\r
- u_int8_t lmc; /* 0-7 */\r
- IB_link_speed_t link_speed_active;\r
- IB_link_speed_t link_speed_enabled;\r
- IB_mtu_t neighbor_mtu;\r
- IB_sl_t master_sm_sl; /* 0-15 */\r
- IB_vl_cap_t vl_cap;\r
- u_int8_t vl_high_limit;\r
- u_int8_t vl_arbitration_high_cap;\r
- u_int8_t vl_arbitration_low_cap;\r
- IB_mtu_t mtu_cap;\r
- u_int8_t vl_stall_count; /* 0-7 */\r
- u_int8_t hoq_life; /* 0-31 */\r
- IB_vl_cap_t operational_vl;\r
- MT_bool partition_enforcement_inbound;\r
- MT_bool partition_enforcement_outbound;\r
- MT_bool filter_raw_inbound;\r
- MT_bool filter_raw_outbound;\r
- u_int16_t m_key_violations;\r
- u_int16_t p_key_violations;\r
- u_int16_t q_key_violations;\r
- u_int8_t guid_cap; /* 0-15 */\r
- u_int8_t subnet_t_o; /* SubnetTimeOut: 0-31 */\r
- u_int8_t resp_time_val; /* 0-15 */\r
- u_int8_t local_phy_errs; /* 0-15 */\r
- u_int8_t overrun_errs; /* 0-15 */\r
-};\r
- \r
-struct IB_node_info_st {\r
- u_int8_t base_version;\r
- u_int8_t class_version;\r
- IB_node_type_t node_type;\r
- u_int8_t num_ports;\r
- IB_guid_t node_guid;\r
- IB_guid_t port_guid;\r
- u_int16_t partition_cap;\r
- IB_dev_id_t dev_id;\r
- u_int32_t dev_rev;\r
- IB_port_t local_port_num;\r
- u_int32_t vendor_id; /* Only 24 LS-bits are valid */\r
-};\r
-\r
-typedef u_int8_t IB_node_description_t[64]; /* consider other UNICODE string representation */\r
-\r
-struct IB_switch_info_st {\r
- u_int16_t linear_fdb_cap;\r
- u_int16_t random_fdb_cap;\r
- u_int16_t mcast_fdb_cap;\r
- u_int16_t linear_fdb_top;\r
- IB_port_t default_port;\r
- IB_port_t default_mcast_primary_port;\r
- IB_port_t default_mcast_not_primary_port;\r
- u_int8_t lifetime_val; /* Only 5 LS-bits are valid */\r
- MT_bool port_state_change;\r
- u_int16_t lids_per_port;\r
- u_int16_t partition_enforcement_cap;\r
- MT_bool inbound_enforcement_cap;\r
- MT_bool outbound_enforcement_cap;\r
- MT_bool filter_raw_packet_inbound_cap;\r
- MT_bool filter_raw_packet_outbound_cap;\r
-};\r
-\r
-typedef struct IB_grh_st {\r
- u_int8_t IP_version; /* Only 4 LS-bits */\r
- u_int8_t traffic_class;\r
- u_int32_t flow_label; /* Only 20 LS-bits */\r
- u_int16_t payload_length;\r
- u_int8_t next_header;\r
- u_int8_t hop_limit;\r
- IB_gid_t sgid; /* H-to-L (big) (network) endianess */\r
- IB_gid_t dgid; \r
-}IB_grh_t;\r
-\r
-/* IB headers sizes in bytes */\r
-#define IB_LRH_LEN 8\r
-#define IB_GRH_LEN 40 /* size of the GRH (in the actual packet) */\r
-#define IB_BTH_LEN 12\r
-#define IB_DETH_LEN 8\r
-#define IB_MAD_LEN 256 /* size of a MAD payload */\r
-\r
-\r
-struct IB_vl_weight_element_st {\r
- IB_vl_t vl;\r
- IB_arbitration_weight_t weight;\r
-};\r
-#define SET_END_OF_VL_WEIGHT_TAB(vlw) (vlw).weight = 0\r
-#define IS_END_OF_VL_WEIGHT_TAB(vlw) ((vlw).weight == 0)\r
-#define IB_MAX_VL_ARBITRATION_ENTRIES 64\r
-\r
-\r
-typedef enum {\r
- IB_COMP_SUCCESS,\r
- IB_COMP_LOC_LEN_ERR,\r
- IB_COMP_LOC_QP_OP_ERR,\r
- IB_COMP_LOC_EE_OP_ERR,\r
- IB_COMP_LOC_PROT_ERR,\r
- IB_COMP_WR_FLUSH_ERR,\r
- IB_COMP_MW_BIND_ERR,\r
- IB_COMP_BAD_RESP_ERR,\r
- IB_COMP_LOC_ACCS_ERR,\r
- IB_COMP_REM_INV_REQ_ERR,\r
- IB_COMP_REM_ACCESS_ERR,\r
- IB_COMP_REM_OP_ERR,\r
- IB_COMP_RETRY_EXC_ERR,\r
- IB_COMP_RNR_RETRY_EXC_ERR,\r
- IB_COMP_LOC_RDD_VIOL_ERR,\r
- IB_COMP_REM_INV_RD_REQ_ERR,\r
- IB_COMP_REM_ABORT_ERR,\r
- IB_COMP_INV_EECN_ERR,\r
- IB_COMP_INV_EEC_STATE_ERR,\r
-/* IB_COMP_LOC_TOUT,*/ /* Use IB_COMP_RETRY_EXC_ERR instead */\r
-/* IB_COMP_RNR_TOUT,*/ /* Use IB_COMP_RNR_RETRY_EXC_ERR instead */\r
-\r
- IB_COMP_FATAL_ERR,\r
- IB_COMP_GENERAL_ERR\r
-} IB_comp_status_t;\r
-\r
-#define IB_PSN_MAX ((int32_t)0xffffff)\r
-#define IB_PSN_ADD(a,b) (((int32_t)(a)+(int32_t)(b))& IB_PSN_MAX)\r
-#define IB_PSN_SUB(a,b) (((int32_t)(a)-(int32_t)(b))& IB_PSN_MAX)\r
-/* a <= b, that is b follows a: FIXME: might be off by one here */\r
-#define IB_PSN_LE(a,b) (IB_PSN_SUB((b),(a)) <= IB_PSN_MAX/2)\r
-#define IB_PSN_GE(a,b) (IB_PSN_LE((b),(a)))\r
-\r
-#define IB_PSN_IS_VALID(a) ((((int32_t)(a)) & (~ IB_PSN_MAX)) == 0 ) \r
-#define IB_PSN_IS_INVALID(a) (((int32_t)(a)) & (~ IB_PSN_MAX))\r
-\r
-\r
-/*\r
- * xCA interface general data strcutures.\r
- *\r
- */\r
-\r
-\r
-\r
-typedef void* IB_wrid_t;\r
-#define IB_INVALID_WRID 0\r
-\r
-typedef struct {\r
- u_int64_t ibva;\r
- \r
- u_int32_t ibva_l; /* TBD - remove this in the future */\r
- u_int32_t ibva_h; /* TBD - remove this in the near future */\r
-\r
- IB_rkey_t rkey;\r
-} IB_raddr_t;\r
-\r
-typedef struct {\r
- union\r
- {\r
- MT_virt_addr_t va;\r
- MT_phys_addr_t pa;\r
- } addr;\r
-\r
- u_int32_t lkey;\r
- u_int32_t size;\r
-} IB_sge_t;\r
-\r
-typedef struct {\r
- u_int32_t byte_count; /* Sum of size of all s/g entries */\r
- u_int32_t entry_count; /* Number of s/g entries in list */\r
-\r
- enum {IB_SGE_VIRT, IB_SGE_PHYS} addr_type;\r
- \r
- IB_sge_t *list;\r
- \r
-} IB_sge_list_t;\r
-\r
-\r
-typedef enum {\r
- IB_WR_RDMA_WRITE,\r
- IB_WR_RDMA_WRITE_WITH_IMM,\r
- IB_WR_SEND,\r
- IB_WR_SEND_WITH_IMM,\r
- IB_WR_RDMA_READ,\r
- IB_WR_ATOMIC_CMP_AND_SWP,\r
- IB_WR_ATOMIC_FETCH_AND_ADD,\r
- IB_WR_RECEIVE\r
-} IB_wr_opcode_t;\r
-\r
-/* Address Vector */\r
-typedef struct {\r
- IB_sl_t sl; /* Service Level 4 bits */\r
- IB_lid_t dlid; /* Destination LID */\r
- u_int8_t src_path_bits; /* Source path bits 7 bits */\r
- IB_static_rate_t static_rate; /* Maximum static rate : 6 bits */\r
-\r
- MT_bool grh_flag; /* Send GRH flag */\r
- /* For global destination or Multicast address:*/ \r
- u_int8_t traffic_class; /* TClass 8 bits */\r
- u_int32_t flow_label; /* Flow Label 20 bits */\r
- u_int8_t hop_limit; /* Hop Limit 8 bits */\r
- u_int8_t sgid_index; /* SGID index in SGID table */\r
- IB_gid_t dgid; /* Destination GID */\r
-\r
-} IB_ud_av_t; \r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* H_IB_DEFS_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#ifndef H_MTL_ERRNO_H\r
-#define H_MTL_ERRNO_H\r
-\r
-#ifndef __DARWIN__\r
- #if defined(__KERNEL__) && defined(__LINUX__)\r
- #include <asm/errno.h>\r
- #else\r
- #include <errno.h>\r
- #endif\r
-#else\r
- #include <sys/errno.h>\r
-#endif\r
-\r
- /****************** General Purpose Error Codes (0 to -999) *****************/\r
-#ifndef ETIMEDOUT\r
-#define ETIMEDOUT (110)\r
-#endif\r
-\r
-#ifndef ENOSYS\r
-#define ENOSYS 38 /* Function not implemented */\r
-#endif\r
-\r
-#ifndef EINVAL\r
-#define EINVAL 22 /* Invalid argument */\r
-#endif\r
-\r
-\r
-\r
-#define ERROR_LIST_GENERAL \\r
- INFO( MT_OK, 0, "success" ) \\r
- INFO( MT_ERROR, -1, "generic error" ) \\r
- INFO( MT_ENOINIT, -2, "module not initialized" ) \\r
- INFO( MT_EINVAL, -3, "invalid argument" ) \\r
- INFO( MT_ENORSC, -4, "No such resource (probably out of range)" ) \\r
- INFO( MT_EPERM, -5, "Not enough permissions to perform operation" ) \\r
- INFO( MT_ENOSYS, -6, "The system doesn't support requested operation" ) \\r
- INFO( MT_EAGAIN, -7, "Resource temporarily unavailable" ) \\r
- INFO( MT_EALIGN, -8, "Alignment error (offset/size not aligned)" ) \\r
- INFO( MT_EDEADLK, -9, "Resource deadlock avoided" ) \\r
- INFO( MT_ENOENT, -10, "No such file or directory" ) \\r
- INFO( MT_EACCES, -11, "Permission denied" ) \\r
- INFO( MT_EINTR, -12, "process received interrupt") \\r
- INFO( MT_ESTATE, -13, "Invalid state") \\r
- INFO( MT_ESYSCALL, -14,"Error in an underlying O/S call") \\r
- INFO( MT_ETIMEDOUT, -ETIMEDOUT,"Operation timed out" ) \\r
- INFO( MT_SYS_EINVAL, -EINVAL, "Invalid argument")\\r
- INFO( MT_ENOMOD, -ENOSYS, "module not loaded") /* When module not loaded, syscall return ENOSYS */\r
-\r
-\r
-\r
- /**************** Memory Handling Error Codes (-1000 to -1199) **************/\r
-\r
-\r
-#define ERROR_LIST_MEMORY \\r
- INFO( MT_EKMALLOC, -1000, "Can't allocate kernel memory" ) \\r
- INFO( MT_ENOMEM, -1001, "Given address doesn't match process address space" ) \\r
- INFO( MT_EMALLOC, -1002, "malloc fail") \\r
- INFO( MT_EFAULT, -1003, "Bad address" )\r
-\r
- /****************** General Device Error Codes (-1200 to -1399) *************/\r
-\r
-#define ERROR_LIST_DEVICE \\r
- INFO( MT_ENODEV, -1200, "No such device" ) \\r
- INFO( MT_EBUSY, -1201, "Device or resource busy (or used by another)" ) \\r
- INFO( MT_EBUSBUSY, -1202, "Bus busy" )\r
-\r
- /*********************** I2C Error Codes (-1400 to -1499) *******************/\r
-\r
-#define ERROR_LIST_I2C \\r
- INFO( MT_EI2CNACK, -1400, "I2C: received NACK from slave" ) \\r
- INFO( MT_EI2PINHI, -1401, "I2C: Pending Interrupt Not does no become low" ) \\r
- INFO( MT_EI2TOUT, -1402, "I2C: Operation has been timed out" ) \r
- \r
-#define ERROR_LIST ERROR_LIST_GENERAL ERROR_LIST_MEMORY ERROR_LIST_DEVICE ERROR_LIST_I2C\r
-\r
- /** \r
- ** See at end of file the full list of POSIX errors\r
- **/\r
-\r
-\r
-typedef enum {\r
-#define INFO(A,B,C) A = B,\r
- ERROR_LIST\r
-#undef INFO\r
- MT_DUMMY_ERROR /* this one is needed to quite warning by -pedantic */\r
-} call_result_t;\r
-\r
-#endif /* H_MTL_ERRNO_H */\r
-\r
-#if 0\r
-\r
- The following list derrived automatically from\r
- ISO/IEC 9945-1: 1996 ANSI/IEEE Std 1003.1, 1996 Edition\r
- Chapter 2.4 Error Numbers\r
-\r
-\r
- If you add a new MT_ error please consider one from this list\r
-\r
- INFO( E2BIG, xxx, "Arg list too long" ) \\r
- INFO( EAGAIN, xxx, "Resource temporarily unavailable" ) \\r
- INFO( EBADF, xxx, "Bad file descriptor" ) \\r
- INFO( EBADMSG, xxx, "Bad message" ) \\r
- INFO( EBUSY, xxx, "Resource busy" ) \\r
- INFO( ECANCELED, xxx, "Operation canceled" ) \\r
- INFO( ECHILD, xxx, "No child processes" ) \\r
- INFO( EDEADLK, xxx, "Resource deadlock avoided" ) \\r
- INFO( EDOM, xxx, "Domain error" ) \\r
- INFO( EEXIST, xxx, "File exists" ) \\r
- INFO( EFAULT, xxx, "Bad address" ) \\r
- INFO( EFBIG, xxx, "File too large" ) \\r
- INFO( EINPROGRESS, xxx, "Operation in progress" ) \\r
- INFO( EINTR, xxx, "Interrupted function call" ) \\r
- INFO( EINVAL, xxx, "Invalid argument" ) \\r
- INFO( EISDIR, xxx, "Is a directory" ) \\r
- INFO( EMFILE, xxx, "Too many open files" ) \\r
- INFO( EMLINK, xxx, "Too many links" ) \\r
- INFO( EMSGSIZE, xxx, "Inappropriate message buffer length" ) \\r
- INFO( ENAMETOOLONG, xxx, "Filename too long" ) \\r
- INFO( ENFILE, xxx, "Too many open files in system" ) \\r
- INFO( ENODEV, xxx, "No such device" ) \\r
- INFO( ENOEXEC, xxx, "Exec format error" ) \\r
- INFO( ENOLCK, xxx, "No locks available" ) \\r
- INFO( ENOMEM, xxx, "Not enough space" ) \\r
- INFO( ENOSPC, xxx, "No space left on device" ) \\r
- INFO( ENOSYS, xxx, "Function not implemented" ) \\r
- INFO( ENOTDIR, xxx, "Not a directory" ) \\r
- INFO( ENOTEMPTY, xxx, "Directory not empty" ) \\r
- INFO( ENOTSUP, xxx, "Not supported" ) \\r
- INFO( ENOTTY, xxx, "Inappropriate I/O control operation" ) \\r
- INFO( ENXIO, xxx, "No such device or address" ) \\r
- INFO( EPERM, xxx, "Operation not permitted" ) \\r
- INFO( EPIPE, xxx, "Broken pipe" ) \\r
- INFO( ERANGE, xxx, "Result too large" ) \\r
- INFO( EROFS, xxx, "Read-only file system" ) \\r
- INFO( ESPIPE, xxx, "Invalid seek" ) \\r
- INFO( ESRCH, xxx, "No such process" ) \\r
- INFO( EXDEV, xxx, "Improper link" ) \\r
-\r
-#endif\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include <mtl_types.h>\r
-\r
-#define MOSAL_PCI_HEADER_TYPE1 0x01 /* Bridge type device */\r
-#define MOSAL_PCI_HEADER_TYPE0 0x00 /* Normal type device */\r
- \r
- \r
-#ifdef MT_LITTLE_ENDIAN\r
-\r
-typedef struct {\r
- u_int16_t vid; /* vendor ID */\r
- u_int16_t devid; /* device ID */\r
- u_int16_t cmd; /* command register */\r
- u_int16_t status; /* status register */\r
- u_int8_t revid; /* revision ID */\r
- u_int8_t class_code; /* class code */\r
- u_int8_t subclass; /* sub class code */\r
- u_int8_t progif; /* programming interface */\r
- u_int8_t cache_line; /* cache line */\r
- u_int8_t latency; /* latency time */\r
- u_int8_t header_type; /* header type */\r
- u_int8_t bist; /* BIST */\r
- u_int32_t base0; /* base address 0 */\r
- u_int32_t base1; /* base address 1 */\r
- u_int32_t base2; /* base address 2 */\r
- u_int32_t base3; /* base address 3 */\r
- u_int32_t base4; /* base address 4 */\r
- u_int32_t base5; /* base address 5 */\r
- u_int32_t cis; /* cardBus CIS pointer */\r
- u_int16_t sub_vid; /* sub system vendor ID */\r
- u_int16_t sub_sysid; /* sub system ID */\r
- u_int32_t rom_base; /* expansion ROM base address */\r
- u_int32_t reserved0; /* reserved */\r
- u_int32_t reserved1; /* reserved */\r
- u_int8_t int_line; /* interrupt line */\r
- u_int8_t int_pin; /* interrupt pin */\r
- u_int8_t min_grant; /* min Grant */\r
- u_int8_t max_latency; /* max Latency */\r
-} MOSAL_PCI_hdr_type0_t;\r
-\r
-\r
-\r
-typedef struct {\r
- u_int16_t vid; /* vendor ID */\r
- u_int16_t devid; /* device ID */\r
- u_int16_t cmd; /* command register */\r
- u_int16_t status; /* status register */\r
- u_int8_t revid; /* revision ID */\r
- u_int8_t class_code; /* class code */\r
- u_int8_t sub_class; /* sub class code */\r
- u_int8_t progif; /* programming interface */\r
- u_int8_t cache_line; /* cache line */\r
- u_int8_t latency; /* latency time */\r
- u_int8_t header_type; /* header type */\r
- u_int8_t bist; /* BIST */\r
- u_int32_t base0; /* base address 0 */\r
- u_int32_t base1; /* base address 1 */\r
- u_int8_t pri_bus; /* primary bus number */\r
- u_int8_t sec_bus; /* secondary bus number */\r
- u_int8_t sub_bus; /* subordinate bus number */\r
- u_int8_t sec_latency; /* secondary latency timer */\r
- u_int8_t iobase; /* IO base */\r
- u_int8_t iolimit; /* IO limit */\r
- u_int16_t sec_status; /* secondary status */\r
- u_int16_t mem_base; /* memory base */\r
- u_int16_t mem_limit; /* memory limit */\r
- u_int16_t pre_base; /* prefetchable memory base */\r
- u_int16_t pre_limit; /* prefetchable memory limit */\r
- u_int32_t pre_base_upper; /* prefetchable memory base upper 32 bits */\r
- u_int32_t pre_limit_upper; /* prefetchable memory base upper 32 bits */\r
- u_int16_t io_base_upper; /* IO base upper 16 bits */\r
- u_int16_t io_limit_upper; /* IO limit upper 16 bits */\r
- u_int32_t reserved; /* reserved */\r
- u_int32_t rom_base; /* expansion ROM base address */\r
- u_int8_t int_line; /* interrupt line */\r
- u_int8_t int_pin; /* interrupt pin */\r
- u_int16_t control; /* bridge control */\r
-\r
-} MOSAL_PCI_hdr_type1_t;\r
-\r
-#else /* MT_BIG_ENDIAN */\r
-\r
-typedef struct {\r
- \r
- u_int16_t devid; /* device ID */\r
- u_int16_t vid; /* vendor ID */\r
- \r
- u_int16_t status; /* status register */\r
- u_int16_t cmd; /* command register */\r
- \r
- u_int8_t progif; /* programming interface */\r
- u_int8_t subclass; /* sub class code */\r
- u_int8_t class_code; /* class code */\r
- u_int8_t revid; /* revision ID */\r
-\r
- u_int8_t bist; /* BIST */\r
- u_int8_t header_type; /* header type */\r
- u_int8_t latency; /* latency time */\r
- u_int8_t cache_line; /* cache line */\r
- \r
- u_int32_t base0; /* base address 0 */\r
- u_int32_t base1; /* base address 1 */\r
- u_int32_t base2; /* base address 2 */\r
- u_int32_t base3; /* base address 3 */\r
- u_int32_t base4; /* base address 4 */\r
- u_int32_t base5; /* base address 5 */\r
- \r
- u_int32_t cis; /* cardBus CIS pointer */\r
-\r
- u_int16_t sub_sysid; /* sub system ID */\r
- u_int16_t sub_vid; /* sub system vendor ID */\r
- \r
- u_int32_t rom_base; /* expansion ROM base address */\r
- u_int32_t reserved0; /* reserved */\r
- u_int32_t reserved1; /* reserved */\r
-\r
- u_int8_t max_latency; /* max Latency */\r
- u_int8_t min_grant; /* min Grant */\r
- u_int8_t int_pin; /* interrupt pin */\r
- u_int8_t int_line; /* interrupt line */\r
-\r
-} MOSAL_PCI_hdr_type0_t;\r
-\r
-\r
-\r
-typedef struct {\r
- u_int16_t devid; /* device ID */\r
- u_int16_t vid; /* vendor ID */\r
- \r
- u_int16_t status; /* status register */\r
- u_int16_t cmd; /* command register */\r
-\r
- u_int8_t progif; /* programming interface */\r
- u_int8_t sub_class; /* sub class code */\r
- u_int8_t class_code; /* class code */\r
- u_int8_t revid; /* revision ID */\r
- \r
- u_int8_t bist; /* BIST */\r
- u_int8_t header_type; /* header type */\r
- u_int8_t latency; /* latency time */\r
- u_int8_t cache_line; /* cache line */\r
- \r
- \r
- u_int32_t base0; /* base address 0 */\r
- u_int32_t base1; /* base address 1 */\r
- \r
- u_int8_t sec_latency; /* secondary latency timer */\r
- u_int8_t sub_bus; /* subordinate bus number */\r
- u_int8_t sec_bus; /* secondary bus number */\r
- u_int8_t pri_bus; /* primary bus number */\r
- \r
- u_int16_t sec_status; /* secondary status */\r
- u_int8_t iolimit; /* IO limit */\r
- u_int8_t iobase; /* IO base */\r
-\r
- u_int16_t mem_limit; /* memory limit */\r
- u_int16_t mem_base; /* memory base */\r
- \r
- u_int16_t pre_limit; /* prefetchable memory limit */\r
- u_int16_t pre_base; /* prefetchable memory base */\r
-\r
- u_int32_t pre_base_upper; /* prefetchable memory base upper 32 bits */\r
- u_int32_t pre_limit_upper; /* prefetchable memory base upper 32 bits */\r
-\r
- u_int16_t io_limit_upper; /* IO limit upper 16 bits */\r
- u_int16_t io_base_upper; /* IO base upper 16 bits */\r
- \r
- u_int32_t reserved; /* reserved */\r
- u_int32_t rom_base; /* expansion ROM base address */\r
-\r
- u_int16_t control; /* bridge control */\r
- u_int8_t int_pin; /* interrupt pin */\r
- u_int8_t int_line; /* interrupt line */\r
-\r
-} MOSAL_PCI_hdr_type1_t;\r
-\r
-#endif\r
-\r
-typedef union {\r
- MOSAL_PCI_hdr_type0_t type0;\r
- MOSAL_PCI_hdr_type1_t type1;\r
-} MOSAL_PCI_cfg_hdr_t;\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MTL_TYPES_H\r
-#define H_MTL_TYPES_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-#if (defined(__KERNEL__) || defined(KERNEL)) && ! defined(MT_KERNEL)\r
-#define MT_KERNEL 1\r
-#endif\r
-\r
-\r
- \r
-#include <mtl_sys_types.h>\r
-#include <mtl_errno.h>\r
-\r
-typedef unsigned char MT_bool;\r
-typedef unsigned int MT_u_int_t;\r
-#ifndef __cplusplus\r
-/* avoid collision with curses.h */\r
-#ifndef bool\r
-#define bool MT_bool\r
-#endif\r
-#endif\r
-\r
-#ifndef MT_KERNEL\r
-#ifndef FALSE\r
-#define FALSE 0\r
-#undef TRUE\r
-#define TRUE (!FALSE)\r
-#endif\r
-#endif\r
-\r
-#define IS_FALSE(b) ((b) == FALSE)\r
-#define IS_TRUE(b) ((b) != FALSE)\r
-\r
-typedef enum{LOGIC_LOW = 0, LOGIC_HIGH = 1} logic_t;\r
-\r
-typedef u_int32_t MT_dev_id_t;\r
-\r
-#define EMPTY\r
-\r
-#define MT_BUS_LIST \\r
-MT_BUS_ELEM(MEM, =0, "Memory") \\r
-MT_BUS_ELEM(PCI, EMPTY, "PCI") \\r
-MT_BUS_ELEM(I2C, EMPTY, "I2C") \\r
-MT_BUS_ELEM(MPC860, EMPTY, "MPC860") \\r
-MT_BUS_ELEM(SIM, EMPTY, "SIM")\r
-\r
-\r
-\r
-\r
-typedef enum {\r
-#define MT_BUS_ELEM(x,y,z) x y,\r
- MT_BUS_LIST\r
-#undef MT_BUS_ELEM\r
- MT_DUMMY_BUS\r
-} MT_bus_t;\r
-\r
-\r
-static inline const char* MT_strbus( MT_bus_t bustype)\r
-{\r
- switch (bustype) {\r
-#define MT_BUS_ELEM(A, B, C) case A: return C;\r
- MT_BUS_LIST\r
-#undef MT_BUS_ELEM\r
- default: return "Unknown bus";\r
- }\r
-}\r
-\r
-\r
-\r
-\r
-typedef void (*void_func_t)(void);\r
-typedef void (*rx_func_t)(MT_virt_addr_t data, u_int32_t size, void *priv);\r
-\r
-#ifndef NULL\r
-#define NULL 0\r
-#endif /*NULL*/\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* H_MTL_TYPES_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef _MD_IOCTL_H_\r
-#define _MD_IOCTL_H_\r
-\r
-\r
-/* \r
- * Driver control device name\r
- */\r
-#define MD_CTL_DEVICE_NAME "MDCTL"\r
-\r
-\r
-/* Base and offset for IO controls codes */\r
-#define MD_IOCTL_BASE 2050 /* Base code for kernel mode drivers */\r
-\r
-//\r
-// special ("tools") ioctls \r
-//\r
-\r
-#define MD_SPECIAL_BASE MD_IOCTL_BASE /* 2050 */\r
-#define MD_SPECIAL_RSRV 10\r
-\r
-/* common ioctls */\r
-#define MD_COMMON_NUM 5\r
-#define MD_COMMON_BASE MD_SPECIAL_BASE /* 2050 */\r
-#define MD_COMMON_END (MD_COMMON_BASE + MD_COMMON_NUM) /* 2055 */\r
-\r
- #define WIN_SOFT_RESET (MD_COMMON_BASE + 0)\r
-\r
-/* PCICONF ioctls */\r
-#define MD_PCICONF_NUM 5\r
-#define MD_PCICONF_BASE MD_COMMON_END /* 2055 */\r
-#define MD_PCICONF_END (MD_PCICONF_BASE + MD_PCICONF_NUM) /* 2060 */\r
-\r
- #define WIN_PCICONF_READ4 (MD_PCICONF_BASE + 0)\r
- #define WIN_PCICONF_WRITE4 (MD_PCICONF_BASE + 1)\r
- #define WIN_PCICONF_MODIFY (MD_PCICONF_BASE + 2)\r
-\r
-/* PCI ioctls */\r
-#define MD_PCI_NUM 5\r
-#define MD_PCI_BASE MD_PCICONF_END /* 2060 */\r
-#define MD_PCI_END (MD_PCI_BASE + MD_PCI_NUM) /* 2065 */\r
-\r
- #define WIN_PCI_GET_BAR_INFO (MD_PCI_BASE + 0)\r
-\r
-/* common ioctls */\r
-#define MD_CTL_NUM 5\r
-#define MD_CTL_BASE MD_PCI_END /* 2065 */\r
-#define MD_CTL_END (MD_CTL_BASE + MD_CTL_NUM) /* 2070 */\r
-\r
- #define WIN_CTL_ENUM (MD_CTL_BASE + 0)\r
-\r
-#define MD_SPECIAL_END (MD_CTL_END + MD_SPECIAL_RSRV) /* 2080 */\r
-\r
-//\r
-// Tavor ioctls \r
-//\r
-\r
-#define MD_TAVOR_BASE MD_SPECIAL_END /* 2080 */\r
-#define MD_TAVOR_RSRV 200\r
-\r
-/* MOSAL ioctls */\r
-#define MOSAL_FUNC_NUM 150\r
-#define MOSAL_FUNC_MANUAL_NUM 10 /* 2220 */\r
-#define MOSAL_FUNC_BASE MD_TAVOR_BASE /* 2080 */\r
-#define MOSAL_FUNC_MANUAL (MOSAL_FUNC_BASE + MOSAL_FUNC_NUM - MOSAL_FUNC_MANUAL_NUM)\r
-\r
- #define K2U_CBK_CBK_INIT (MOSAL_FUNC_MANUAL + 0) /* 2220 */\r
- #define K2U_CBK_CBK_CLEANUP (MOSAL_FUNC_MANUAL + 1) /* 2221 */\r
-\r
-\r
-#define MOSAL_FUNC_END (MOSAL_FUNC_BASE + MOSAL_FUNC_NUM) /* 2230 */\r
-\r
-/* VAPI ioctls */\r
-#define VAPI_FUNC_NUM 100\r
-#define VAPI_FUNC_BASE MOSAL_FUNC_END /* 2230 */\r
-#define VAPI_FUNC_END (VAPI_FUNC_BASE + VAPI_FUNC_NUM) /* 2330 */\r
-\r
-/* IB_MGT ioctls */\r
-#define IBMGT_FUNC_NUM 50\r
-#define IBMGT_FUNC_BASE VAPI_FUNC_END /* 2330 */\r
-\r
-#define IBMGT_FUNC_END (IBMGT_FUNC_BASE + IBMGT_FUNC_NUM) /* 2380 */\r
-\r
-\r
-#define MD_TAVOR_END (IBMGT_FUNC_END + MD_TAVOR_RSRV)\r
-\r
-\r
-//\r
-// Gamla ioctls \r
-//\r
-\r
-#define MD_GAMLA_BASE MD_TAVOR_END \r
-#define MD_GAMLA_RSRV 100\r
-\r
-/* MDD ioctls */\r
-#define MDD_FUNC_NUM 200\r
-#define MDD_FUNC_BASE MD_GAMLA_BASE\r
-#define MDD_FUNC_END (MDD_FUNC_BASE + MDD_FUNC_NUM)\r
-\r
- #undef MDD_SYS_BASE\r
- #define MDD_SYS_BASE MDD_FUNC_BASE\r
-\r
-#define MD_GAMLA_END (MDD_FUNC_END + MD_GAMLA_RSRV) \r
-\r
-\r
-/* create function number from IOCTL */\r
-#define UDLL_MAKE_FUNC(code) ((code >> 2) & 0x00000fff)\r
- \r
-/* create IOCTL from function number - OUT_DIRECT method */\r
-#define UDLL_MAKE_IOCTL(code) \\r
- ((FILE_DEVICE_UNKNOWN) << 16) | ((FILE_ANY_ACCESS) << 14) | ((code) << 2) | (METHOD_OUT_DIRECT)\r
-\r
-/* create IOCTL from function number - BUFFERED method */\r
-#define UDLL_MAKE_IOCTL_BUF(code) \\r
- ((FILE_DEVICE_UNKNOWN) << 16) | ((FILE_ANY_ACCESS) << 14) | ((code) << 2) | (METHOD_BUFFERED)\r
-\r
-/* MdMosalHelper typedef */\r
-typedef int (*Md_Mosal_Helper_t)(void *, int );\r
-\r
-/* commands for MdMosalHelper */\r
-#define MD_HELPER_CARD_RESET 1\r
-\r
-#endif // end, #ifndef _MD_IOCTL_H_\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef _MD_IOCTL_SPEC_H_\r
-#define _MD_IOCTL_SPEC_H_\r
-\r
-/* structures */\r
-typedef struct PCICONF_WRITE4_S {\r
- unsigned long offset;\r
- unsigned long data;\r
-} PCICONF_WRITE4_T, * PPCICONF_WRITE4_T;\r
-\r
-typedef struct PCICONF_MODIFY_S {\r
- unsigned long offset;\r
- unsigned long data;\r
- unsigned long mask;\r
-} PCICONF_MODIFY_T, * PPCICONF_MODIFY_T;\r
-\r
-typedef struct PCI_BAR_INFO_S {\r
- MT_ulong_ptr_t ptr;\r
- MT_ulong_ptr_t size;\r
- unsigned long LowPhysAddr;\r
- long HighPhysAddr;\r
- unsigned long TotalMemSize;\r
- unsigned long MappedSize;\r
- unsigned long MappedOffset;\r
-} PCICONF_BAR_INFO_T, * PPCICONF_BAR_INFO_T;\r
-\r
-typedef struct CTL_ENUM_S {\r
- unsigned long size;\r
- unsigned long cnt;\r
- unsigned char data[1];\r
-} CTL_ENUM_T, * PCTL_ENUM_T;\r
-\r
-\r
-#endif\r
-\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifdef __WIN__\r
-#include <mtl_common.h>\r
-#else\r
-#error "Mustn't be included. Something get wrong !\r
-#endif
\ No newline at end of file
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MTL_SYS_DEFS_H\r
-#define H_MTL_SYS_DEFS_H\r
-\r
-\r
-#include <mtl_types.h>\r
-#include <limits.h>\r
-#include <complib/cl_memory.h>\r
-#include <complib/cl_byteswap.h>\r
-\r
-\r
-#ifdef MT_KERNEL\r
- /* include common things */\r
- #include <stdio.h>\r
- #include <stdarg.h>\r
- #include <string.h>\r
- #include <stdlib.h>\r
-#else\r
- /* replace non-ANSI to the ANSI call */\r
- #define strdup _strdup\r
-\r
- /*\r
- * Includes\r
- */\r
- #include <stdlib.h>\r
- #include <stdio.h>\r
- #include <stdarg.h>\r
- #include <string.h>\r
-\r
- /* usleep */\r
- #ifndef usleep\r
- #include <windows.h>\r
- //#define usleep(x) Sleep((x)/1000)\r
- #endif\r
-#endif\r
-\r
-/* definitions both for Kernel and User space */\r
-\r
-/* export attribute */\r
-#ifdef __DLL_EXPORTS__\r
-#define DLL_API __declspec(dllexport)\r
-#else\r
-#define DLL_API \r
-//#define DLL_API __declspec(dllimport)\r
-#endif\r
-#define DLL_INLINE DLL_API inline\r
-\r
-/* no bool type */\r
-#ifndef __cplusplus\r
-#ifndef bool\r
-#define bool BOOLEAN\r
-#endif\r
-#endif\r
-\r
-/* variable for log implmentation in NT */\r
-extern char * cur_module;\r
-\r
-/* inline */\r
-#define __INLINE__ _inline \r
-#ifndef inline\r
-#define inline _inline \r
-#endif\r
-\r
-/* MODULE_LICENSE */\r
-#define MODULE_LICENSE(a)\r
-\r
-/* MTL_LOG */\r
-/* common for kernel and user */\r
-#include <mtl_log_win.h>\r
-\r
-#define __attribute__(a)\r
-#define asmlinkage\r
-\r
-\r
-/* long long constants */\r
-#define MAKE_LONGLONG(a) (a##i64)\r
-#define MAKE_ULONGLONG(a) (a##ui64)\r
-\r
-/* replace not ANSI function */\r
-#define strcasecmp stricmp\r
-\r
-/* MS compiler doesn't understand the usage of the macro */\r
-#define MODULE_PARM(p,a) \r
-\r
-/* no PVOID arithmetic in cl */\r
-#define PCHAR_CAST (char *)\r
-\r
-/* allocation on stack */\r
-#define ALLOCA(a) _alloca(a)\r
-#define FREEA(a) \r
-\r
-/* no __func__ in cl */\r
-#define __func__ __FUNCTION__\r
-\r
-/* rename functions */\r
-#define srandom srand\r
-#define random rand\r
-#define vsnprintf _vsnprintf\r
-\r
-/* Endian Conversions */\r
-#if defined(MT_LITTLE_ENDIAN) || defined (__LITTLE_ENDIAN) \r
- #define mt_swap64be(x) letobe64(x)\r
- #define mt_swap32be(x) letobe32(x)\r
- #define mt_swap16be(x) letobe16(x)\r
- #define mt_swap64le(x) (x)\r
- #define mt_swap32le(x) (x)\r
- #define mt_swap16le(x) (x)\r
-#else \r
- #define mt_swap64le(x) letobe64(x)\r
- #define mt_swap32le(x) letobe32(x)\r
- #define mt_swap16le(x) letobe16(x)\r
- #define mt_swap64be(x) (x)\r
- #define mt_swap32be(x) (x)\r
- #define mt_swap16be(x) (x)\r
-#endif\r
-\r
-#define MOSAL_cpu_to_be64(x) mt_swap64be(x)\r
-#define MOSAL_be64_to_cpu(x) mt_swap64be(x)\r
-#define MOSAL_cpu_to_be32(x) mt_swap32be(x)\r
-#define MOSAL_be32_to_cpu(x) mt_swap32be(x)\r
-#define MOSAL_cpu_to_be16(x) mt_swap16be(x)\r
-#define MOSAL_be16_to_cpu(x) mt_swap16be(x)\r
-\r
-#define MOSAL_cpu_to_le64(x) mt_swap64le(x)\r
-#define MOSAL_le64_to_cpu(x) mt_swap64le(x)\r
-#define MOSAL_cpu_to_le32(x) mt_swap32le(x)\r
-#define MOSAL_le32_to_cpu(x) mt_swap32le(x)\r
-#define MOSAL_cpu_to_le16(x) mt_swap16le(x)\r
-#define MOSAL_le16_to_cpu(x) mt_swap16le(x)\r
-\r
-#define __cpu_to_be64(x) mt_swap64be(x)\r
-#define __be64_to_cpu(x) mt_swap64be(x)\r
-#define __cpu_to_be32(x) mt_swap32be(x)\r
-#define __be32_to_cpu(x) mt_swap32be(x)\r
-#define __cpu_to_be16(x) mt_swap16be(x)\r
-#define __be16_to_cpu(x) mt_swap16be(x)\r
-\r
-#define __cpu_to_le64(x) mt_swap64le(x)\r
-#define __le64_to_cpu(x) mt_swap64le(x)\r
-#define __cpu_to_le32(x) mt_swap32le(x)\r
-#define __le32_to_cpu(x) mt_swap32le(x)\r
-#define __cpu_to_le16(x) mt_swap16le(x)\r
-#define __le16_to_cpu(x) mt_swap16le(x)\r
-\r
-\r
-/* functions */\r
-u_int64_t MOSAL_nsecs(void);\r
-static __INLINE__ u_int64_t win_get_time_counter(void)\r
-{\r
- return MOSAL_nsecs();\r
-}\r
-\r
-\r
-u_int64_t mt_strtoull (const char *nptr, char **endptr, int base);\r
-#define strtoull mt_strtoull\r
-\r
-#ifndef MIN\r
-#define MIN(a,b) (((a) < (b)) ? (a) : (b))\r
-#endif\r
-#define MT_MIN(a,b) (((a) < (b)) ? (a) : (b))\r
-\r
-#ifndef MAX\r
-#define MAX(a,b) (((a) > (b)) ? (a) : (b))\r
-#endif\r
-#define MT_MAX(a,b) (((a) > (b)) ? (a) : (b))\r
-\r
-//\r
-// Calculate the byte offset of a field in a structure of type type.\r
-//\r
-\r
-#ifndef FIELD_OFFSET\r
-#define FIELD_OFFSET(type, field) ((LONG)(LONG_PTR)&(((type *)0)->field))\r
-#endif\r
-\r
-\r
-//\r
-// Calculate the address of the base of the structure given its type, and an\r
-// address of a field within the structure.\r
-//\r
-\r
-#ifndef CONTAINING_RECORD\r
-#define CONTAINING_RECORD(address, type, field) ((type *)( (PCHAR)(address) - (ULONG_PTR)(&((type *)0)->field)))\r
-#endif \r
-\r
-\r
-\r
-/* definitions for KERNEL space */\r
-\r
-#ifdef MT_KERNEL\r
-\r
-/*\r
- * Includes\r
- */\r
-\r
-/*\r
- * general\r
- */\r
-\r
-/* replace direct call to a Linux function 'printk' */\r
-#define printk DbgPrint\r
-// #include "..\MDD\mosal\mosal.h"\r
-\r
-\r
-/*\r
- * Defines\r
- */\r
-#define MT_WIN_SYSTEM_SPACE_START (MM_LOWEST_SYSTEM_ADDRESS)\r
-#define VMALLOC(bsize) QVMALLOC(bsize)\r
-#define VFREE(ptr) QVFREE(ptr)\r
-#define MALLOC(bsize) QMALLOC(bsize)\r
-#define INTR_MALLOC(bsize) QINTR_MALLOC(bsize)\r
-#define FREE(ptr) QFREE(ptr)\r
-\r
-//DLL_API void MOSAL_mem_free( MT_virt_addr_t addr );\r
-//DLL_API MT_virt_addr_t MOSAL_mem_alloc( MT_size_t size, u_int32_t flags );\r
-#define QMALLOC(bsize) cl_malloc(bsize)\r
-//(void*)MOSAL_mem_alloc((bsize),0)\r
-#define QINTR_MALLOC(bsize) cl_malloc(bsize)\r
-//(void*)MOSAL_mem_alloc((bsize),1)\r
-#define QFREE(ptr) cl_free((void*)ptr)\r
-//MOSAL_mem_free(ptr)\r
-#define QVMALLOC(bsize) cl_malloc(bsize)\r
-//(void*)MOSAL_mem_alloc((bsize),0)\r
-#define QVFREE(ptr) cl_free((void*)ptr)\r
-//MOSAL_mem_free(ptr)\r
-#define QCMALLOC(bsize,g) cl_malloc(bsize)\r
-//(void*)MOSAL_mem_alloc((bsize),g)\r
-\r
-/* no isalpha() in NTOSKRNL.EXE */\r
-#ifndef isalpha\r
-#define isalpha(c) (((c) >= 'a' && (c) <= 'z') || ((c) >= 'A' && (c) <= 'Z'))\r
-#endif\r
-\r
-/* swap */\r
-#define letobe64(x) RtlUlonglongByteSwap(x)\r
-//#define letobe32(x) USER_letobe32(x) // MOSAL_letobe32(x)\r
-#define letobe32(x) RtlUlongByteSwap(x)\r
-#define letobe16(x) RtlUshortByteSwap(x)\r
-\r
-/* functions */\r
-static inline void MOSAL_rdtsc(volatile u_int64_t *arg) \r
-{\r
- *arg = KeQueryPerformanceCounter( NULL ).QuadPart;\r
-}\r
-\r
-/* end of Kernel-space stuff */\r
-\r
-#else\r
-\r
-/* definitions for User space */\r
- \r
-\r
-u_int64_t MOSAL_get_counts_per_sec(void);\r
- \r
-/* functions */\r
-static inline void MOSAL_rdtsc(volatile u_int64_t *arg) \r
-{\r
- QueryPerformanceCounter( (LARGE_INTEGER*)arg );\r
-}\r
-\r
-_inline void usleep( unsigned long x) \r
-{ \r
- #define MOSAL_CALL_TIME_USECS 110\r
- #define MIN_TIME_FOR_LONG_SLEEP_USECS 5000\r
- \r
- static u_int64_t clocks_per_sec = 0;\r
- volatile u_int64_t m1, m2;\r
- u_int32_t elapsed_time_usecs;\r
-\r
- if (x > MIN_TIME_FOR_LONG_SLEEP_USECS) {\r
- Sleep(x / 1000); \r
- return;\r
- }\r
- \r
- /* get CPU calibration value the first time */\r
- while (!clocks_per_sec) {\r
- \r
- /* get CPU calibration value from MOSAL - it takes around MOSAL_CALL_TIME_USECS */\r
- clocks_per_sec = MOSAL_get_counts_per_sec();\r
- \r
- /* if we failed for some reason - try it once more - just to spend the time */\r
- if (!clocks_per_sec) {\r
- if (x > MOSAL_CALL_TIME_USECS) {\r
- x -= MOSAL_CALL_TIME_USECS;\r
- continue;\r
- }\r
- else\r
- return;\r
- }\r
- else {\r
- if (x > MOSAL_CALL_TIME_USECS) {\r
- x -= MOSAL_CALL_TIME_USECS;\r
- break;\r
- }\r
- else \r
- return;\r
- }\r
- }\r
-\r
- /* wait for the rest time */\r
- m1 = win_get_time_counter();\r
- do {\r
- m2 = win_get_time_counter();\r
- elapsed_time_usecs = (u_int32_t)(((m2 - m1) * 1000000) / clocks_per_sec);\r
- }\r
- while (elapsed_time_usecs < x);\r
- \r
-}\r
-\r
-/*\r
- * Defines\r
- */\r
-\r
-#define MALLOC(bsize) cl_malloc(bsize)\r
-#define INTR_MALLOC(bsize) cl_malloc(bsize)\r
-#define FREE(ptr) cl_free(ptr)\r
-#define VMALLOC(bsize) cl_malloc(bsize)\r
-#define VFREE(ptr) cl_free(ptr)\r
-\r
-/* swap */\r
-\r
-#define letobe64(x) cl_hton64(x)\r
-#define letobe32(x) cl_hton32(x)\r
-#define letobe16(x) cl_hton16(x)\r
-\r
-\r
-/*\r
- * prototypes \r
- */\r
- VOID \r
-DebugPrint(\r
- IN PUCHAR pi_szFormat,\r
- ...\r
- );\r
-\r
-\r
-/* end of User-space stuff */\r
-\r
-#endif\r
-\r
-#endif /* H_MTL_SYS_DEFS_H */\r
-\r
-\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#ifndef H_MTL_SYS_TYPES_H\r
-#define H_MTL_SYS_TYPES_H\r
-\r
-#include <complib/cl_types.h>\r
-\r
-#ifndef MT_KRNL_CALL \r
-#define MT_KRNL_CALL __stdcall\r
-#endif\r
-\r
-#ifndef MT_USER_CALL \r
-#define MT_USER_CALL __cdecl\r
-#endif\r
-\r
-#ifdef __KERNEL__\r
-#define MT_API MT_KRNL_CALL\r
-#else\r
-#define MT_API MT_USER_CALL\r
-#endif\r
-\r
-//typedef char int8_t;\r
-typedef uint8_t u_int8_t;\r
-//typedef short int int16_t;\r
-typedef uint16_t u_int16_t;\r
-//typedef int int32_t;\r
-typedef uint32_t u_int32_t;\r
-//typedef __int64 int64_t;\r
-typedef uint64_t u_int64_t;\r
-//typedef _W64 __int3264 intn_t;\r
-typedef uintn_t u_intn_t;\r
-\r
-\r
-/*\r
- * arch_types are defined in such a way that the build environment\r
- * will automatically size things properly.\r
- */\r
-#include <mtl_arch_types.h>\r
-\r
-#define MT_BYTE_ALIGN(n)\r
-#define MT_PID_FMT MT_ULONG_PTR_FMT\r
-\r
-#endif /* H_MTL_SYS_TYPES_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifdef __WIN__\r
-#include <mtl_common.h>\r
-#else\r
-#error "It shouldn't be included. Call Leonid"\r
-#endif
\ No newline at end of file
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MTL_ARCH_TYPES_H\r
-#define H_MTL_ARCH_TYPES_H\r
-\r
-\r
-#if defined( i386 )\r
-#define __i386__\r
-#elif defined( IA64 )\r
-#define __ia64__\r
-#elif defined( AMD64 )\r
-#define __x86_64__\r
-#endif\r
-\r
-/*\r
- * Memory sizes\r
- *\r
- */\r
-\r
-#define PAGESHIFT PAGE_SHIFT\r
-#define PAGESIZE PAGE_SIZE\r
-\r
-#define __ARCH_MIN_PAGE_SIZE PAGESIZE \r
-\r
-/*\r
- * Mosal memory managment types\r
- */\r
-\r
-#ifdef _WIN64\r
-#define SIZE_T_XFMT "0x%I64X"\r
-#define SIZE_T_DFMT "%I64"\r
-#define OFF_T_FMT "%I64"\r
-#define MT_ULONG_PTR_FMT "0x%I64X"\r
-#else\r
-#define SIZE_T_XFMT "0x%X"\r
-#define SIZE_T_DFMT "%u"\r
-#define OFF_T_FMT "%u"\r
-#define MT_ULONG_PTR_FMT "0x%X"\r
-#endif\r
-\r
-\r
-#define SIZE_T_FMT SIZE_T_XFMT\r
-#define U64_FMT "0x%I64X"\r
-#define VIRT_ADDR_FMT "%p"\r
-/*\r
- * Physical addresses are always 64-bits. There is no difference \r
- * between PAE and non-PAE drivers in Windows.\r
- */\r
-#define PHYS_ADDR_FMT "%I64X"\r
-typedef u_int64_t MT_phys_addr_t;\r
-/* MT_virt_addr_t is a byte pointer to support arithmetic. */\r
-typedef u_intn_t MT_virt_addr_t;\r
-typedef u_intn_t MT_offset_t;\r
-typedef u_intn_t MT_size_t;\r
-typedef intn_t MT_long_ptr_t;\r
-typedef u_intn_t MT_ulong_ptr_t;\r
-\r
-#endif /* H_MTL_ARCH_TYPES_H */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#define _MD_C_\r
-\r
-#include "MdGen.h"\r
-#include "thh_hob.h"\r
-#include <complib/cl_init.h>\r
-\r
-\r
-#define CHECK_INIT(lbl) \\r
- if (l_MddkStatus != MT_OK) \\r
- { \\r
- l_Status = (NTSTATUS)l_MddkStatus; \\r
- goto lbl; \\r
- }\r
-\r
-/* extern functions */\r
-void MPGA_init_module(void);\r
-int MPGA_cleanup_module(void);\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-// buf_p points to the buffer of the following format:\r
-// <layer> tNdNeN[;...] , meaning\r
-// <layer> trace:12...N debug:12...N error:12...N\r
-// N:0..9\r
-//\r
-// Returns 0 on OK\r
-int make_log_str(PCHAR buf_p,PCHAR layer_p,PCHAR log_str_p)\r
-{\r
- char *ptr, *str, *scale="123456789";\r
- int i, cnt;\r
-\r
- *log_str_p = '\0';\r
- ptr = strchr( buf_p, ' ');\r
- if (ptr == NULL) {\r
- MdKdPrint( DBGLVL_MINIMUM ,("(make_log_str) DebugString - illegal format (%s)\n", buf_p));\r
- return 1;\r
- }\r
- *ptr = '\0';\r
- strcpy( layer_p, buf_p );\r
- buf_p = ptr + 1;\r
- for (i=0; i<3 && *buf_p && *buf_p !='\n'; i++,buf_p+=2) {\r
- switch (*buf_p) {\r
- case 'T': case 't':\r
- str = "trace:";\r
- break;\r
- \r
- case 'D': case 'd':\r
- str = "debug:";\r
- break;\r
- \r
- case 'E': case 'e':\r
- str = "error:";\r
- break;\r
- \r
- default:\r
- MdKdPrint( DBGLVL_MINIMUM ,("(make_log_str) DebugString - illegal format (%s)\n", buf_p));\r
- return 1;\r
- }\r
- cnt = *(buf_p+1) - '0';\r
- if (cnt < 0 || cnt > 9) {\r
- MdKdPrint( DBGLVL_MINIMUM ,("(make_log_str) DebugString - illegal format (%s)\n", buf_p));\r
- return 1;\r
- }\r
- strcat( log_str_p, str );\r
- ptr = log_str_p + strlen(log_str_p);\r
- memcpy( ptr, scale, cnt );\r
- ptr += cnt;\r
- *ptr = ' ';\r
- *(ptr+1) = '\0';\r
- }\r
- return 0;\r
-}\r
-\r
-void CallMtlLogSet(PANSI_STRING aStr) \r
-{\r
- char *ptr, *ptr1;\r
- ptr = aStr->Buffer;\r
- ptr1 = strchr(ptr, ' ');\r
- if (ptr1 == NULL) {\r
- MdKdPrint( DBGLVL_MINIMUM ,("(CallMtlLogSet) DebugMultiString - illegal format (%s)\n", ptr));\r
- }\r
- else {\r
- *ptr1 = '\0';\r
- ptr1 += 1;\r
- mtl_log_set( ptr, ptr1 ); /* there was a value - set it */\r
- }\r
-}\r
-\r
-NTSTATUS\r
-GetRegistryParameters()\r
-{\r
- /* debug break */\r
- ULONG l_uDebugBreak;\r
- /* buffer for Registry string parameter */\r
- /* temp */\r
- ULONG val;\r
-\r
- MD_GET_REGISTRY_DWORD(L"DebugBreak",0,l_uDebugBreak);\r
- if (l_uDebugBreak)\r
- DbgBreakPoint();\r
- \r
-#if DBG \r
- /* "DebugLevel" - set debug print level in the Driver */\r
- MD_GET_REGISTRY_DWORD(L"DebugLevel",DBGLVL_DEFAULT,g_pDrvContext->m_nDebugPrintLevel);\r
- \r
- /* "DebugString" - Debug Print for Tavor - old format */\r
- {\r
- char *ptr1,*ptr2;\r
- UCHAR l_sBuf[250];\r
- MD_GET_REGISTRY_STR(L"DebugString",l_sBuf,sizeof(l_sBuf));\r
- \r
- // Buffer format: <layer> tNdNeN[;...] (N:0..9), meaning\r
- // <layer> trace:12...N debug:12...N error:12...N\r
- for (ptr1=l_sBuf; *ptr1; ptr1=ptr2+1)\r
- {\r
- char log_str[60], layer[20]; \r
- ptr2 = strchr( ptr1, ';' );\r
- if (ptr2 == NULL) {\r
- ptr2 = strchr( ptr1, '\0' );\r
- if (ptr2 == NULL)\r
- break;\r
- else\r
- *(ptr2+1) = '\0';\r
- }\r
- *ptr2='\0';\r
- if (!make_log_str(ptr1,layer, log_str))\r
- mtl_log_set( layer, log_str ); /* there was a value - set it */\r
- }\r
-\r
- }\r
-\r
- /* "DebugMultiString" - Debug Print for Tavor - new format */\r
- {\r
- WCHAR Defaults[] = { L"\0" };\r
- MD_GET_REGISTRY_MULTI_STR(L"DebugMultiString",Defaults,sizeof(Defaults), CallMtlLogSet);\r
- }\r
-\r
-\r
-#endif\r
-\r
- /* "UseIbMgt" - run IbMgt module */\r
- MD_GET_REGISTRY_DWORD(L"UseIbMgt",TRUE,val);\r
- g_pDrvContext->m_fSupportIbMgt = (BOOLEAN)val;\r
-\r
- /* "ThhLegacySqp" - work in 'legacy sqp mode' */\r
- MD_GET_REGISTRY_DWORD(L"ThhLegacySqp",0,g_pDrvContext->m_ThhLegacySqp);\r
- if (g_pDrvContext->m_ThhLegacySqp)\r
- g_pDrvContext->m_fSupportIbMgt = FALSE;\r
-\r
- /* "AvInHostMem" - AV in host memory' */\r
- MD_GET_REGISTRY_DWORD(L"AvInHostMem",0,g_pDrvContext->m_AvInHostMem);\r
-\r
- /* "InfiniteCmdTimeout" */\r
- MD_GET_REGISTRY_DWORD(L"InfiniteCmdTimeout",0,g_pDrvContext->m_InfiniteCmdTimeout);\r
-\r
- /* "IbMgtQp0Only" - for IB_MGT: use only QP0 */\r
- MD_GET_REGISTRY_DWORD(L"IbMgtQp0Only",0,g_pDrvContext->m_IbMgtQp0Only);\r
- \r
- /* "NumCmdsOuts" - number of outstanding commands' */\r
- MD_GET_REGISTRY_DWORD(L"NumCmdsOuts",0,g_pDrvContext->m_NumCmdsOuts);\r
- \r
- /* Other THH params */\r
- MD_GET_REGISTRY_DWORD(L"FatalDelayHalt",0,g_pDrvContext->m_FatalDelayHalt);\r
- MD_GET_REGISTRY_DWORD(L"AsyncEqSize",0,g_pDrvContext->m_AsyncEqSize);\r
- MD_GET_REGISTRY_DWORD(L"CmdifUseUar0",0,g_pDrvContext->m_CmdifUseUar0);\r
- MD_GET_REGISTRY_DWORD(L"IgnoreSubsystemId",0,g_pDrvContext->m_IgnoreSubsystemId);\r
- \r
- /* "SupportTavor" - support Tavor functionality; otherwise - only tools (InfinBurn etc.) */\r
- MD_GET_REGISTRY_DWORD(L"SupportTavor",TRUE,val);\r
- g_pDrvContext->m_fSupportTavor = (BOOLEAN)val;\r
- if (!g_pDrvContext->m_fSupportTavor)\r
- g_pDrvContext->m_fSupportIbMgt = FALSE;\r
-\r
- return STATUS_SUCCESS;\r
-}\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-NTSTATUS\r
-DriverEntry(\r
- IN PDRIVER_OBJECT pi_pDriverObject,\r
- IN PUNICODE_STRING pi_pwsRegistryPath\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Perform the following actions:\r
- - create Control Device names; \r
- - allocate and init Driver context;\r
- - read Registry parameters, if any;\r
- - call MdDevInit to create and init Control Device context;\r
- - init MDDK;\r
- - register Driver entry points with IO manager\r
-\r
-Arguments:\r
-\r
- pi_pDriverObject - pointer to the driver object\r
-\r
- pi_pwsRegistryPath - pointer to a unicode string representing the path\r
- to driver-specific key in the registry\r
-\r
-Return Value:\r
-\r
- STATUS_SUCCESS if successful,\r
- STATUS_UNSUCCESSFUL otherwise\r
-\r
---*/\r
-{\r
- NTSTATUS l_Status = STATUS_SUCCESS;\r
- PDEVICE_OBJECT l_pFdo = NULL;\r
- /* driver context */\r
- PMD_DRV_CONTEXT_T l_pDrvContext = NULL;\r
- /* device context */\r
- PMD_DEV_CONTEXT_T l_pCtrlDevContext;\r
- /* The device Win32 name as unicde string */\r
- UNICODE_STRING l_usNtDeviceName = { 0 , 0 , NULL };\r
- /* The Dos device name as unicde string */\r
- UNICODE_STRING l_usDosDeviceName = { 0 , 0 , NULL };\r
- /* MDDK status */\r
- call_result_t l_MddkStatus;\r
- /* logging */\r
- char * l_pReason = "Unknown";\r
- /* THH params */\r
- THH_module_params_t l_ThhParams;\r
- \r
- /* no context yet */\r
- g_pDrvContext = NULL;\r
- \r
- l_Status = CL_INIT;\r
- if( !NT_SUCCESS(l_Status) )\r
- return l_Status;\r
-\r
- /* create Control Device names */\r
- if (!MdCreateDeviceNames(MD_CTL_DEVICE_NAME, &l_usNtDeviceName, &l_usDosDeviceName))\r
- { /* failed - no resources */\r
-\r
- l_pReason = "Failed creation of name for the Control Device";\r
- l_Status = STATUS_INSUFFICIENT_RESOURCES;\r
- goto err;\r
- \r
- } /* failed - no resources */\r
-\r
- // Allocate memory for Driver Context \r
- l_pDrvContext = (PMD_DRV_CONTEXT_T)MdExAllocatePool( NonPagedPool , sizeof(MD_DRV_CONTEXT_T));\r
-\r
- if (l_pDrvContext == NULL)\r
- { /* allocation failed */\r
- \r
- l_pReason = "Failed allocation memory for Driver Context";\r
- l_Status = STATUS_INSUFFICIENT_RESOURCES;\r
- goto ErrExit1;\r
-\r
- } /* allocation failed */\r
-\r
- /* store it in global variable */\r
- g_pDrvContext = l_pDrvContext;\r
-\r
- /* Clear local device info memory */\r
- RtlZeroMemory(l_pDrvContext, sizeof(MD_DRV_CONTEXT_T));\r
-\r
- // store driver object\r
- l_pDrvContext->m_pDrvObject = pi_pDriverObject;\r
-\r
- // get parameters\r
- \r
- /* break - for debugging */\r
- GetRegistryParameters();\r
- \r
- // Only now one can start debug printing\r
- MdKdPrint( DBGLVL_LOW,("(DriverEntry) MDT started **********\n"));\r
- MdKdPrint( DBGLVL_MINIMUM ,("(DriverEntry) Enter: RegistryPath=\n %ws\n", pi_pwsRegistryPath->Buffer ));\r
-\r
- /*\r
- * Init the fields of the driver context\r
- */ \r
-\r
- /* prottection */\r
- INIT_LOCK_IT( &l_pDrvContext->m_SpinLock );\r
-\r
- // init queue header\r
- InitializeListHead( &l_pDrvContext->m_DevQue );\r
-\r
- /* create control device */\r
- l_Status = MdDevInit( l_pDrvContext, MD_DEV_IX_CTRL, &l_usNtDeviceName, &l_usDosDeviceName, &l_pCtrlDevContext); \r
-\r
- if (!NT_SUCCESS(l_Status)) \r
- { /* device creation failed */\r
-\r
- l_Status = STATUS_INSUFFICIENT_RESOURCES;\r
- goto ErrExit1;\r
-\r
- } /* device creation failed */\r
-\r
- /* store control device in the driver context */\r
- l_pDrvContext->m_pCtlDevContext = l_pCtrlDevContext;\r
-\r
- /* MOSAL */\r
- l_MddkStatus = MOSAL_init(0);\r
- CHECK_INIT(ErrExit1)\r
-\r
- if (g_pDrvContext->m_fSupportTavor) \r
- { /* init Tavor modules */\r
- \r
- /* init mpga_kl */\r
- MPGA_init_module();\r
-\r
- /* init HH modules: vapi_common_kl, hh_kl */\r
- l_MddkStatus = HH_init_module();\r
- CHECK_INIT(ErrExit3)\r
- \r
- /* init Tavor modules: thh_kl, vip_kl, vapi_kl */\r
- /* set DEBUG level: logset THH all */\r
- mtl_log_set( "THH", "all"); \r
-\r
- /* init THH */\r
- l_ThhParams.thh_legacy_sqp = g_pDrvContext->m_ThhLegacySqp;\r
- l_ThhParams.av_in_host_mem = g_pDrvContext->m_AvInHostMem;\r
- l_ThhParams.infinite_cmd_timeout = g_pDrvContext->m_InfiniteCmdTimeout;\r
- l_ThhParams.num_cmds_outs = g_pDrvContext->m_NumCmdsOuts;\r
- l_ThhParams.fatal_delay_halt = g_pDrvContext->m_FatalDelayHalt;\r
- l_ThhParams.async_eq_size = g_pDrvContext->m_AsyncEqSize;\r
- l_ThhParams.cmdif_use_uar0 = g_pDrvContext->m_CmdifUseUar0;\r
- l_ThhParams.ignore_subsystem_id = g_pDrvContext->m_IgnoreSubsystemId;\r
- \r
- l_MddkStatus = THH_init_module( &l_ThhParams );\r
- CHECK_INIT(ErrExit4)\r
- \r
- /* VIP */\r
- // l_MddkStatus = VIPKL_init_module();\r
- // CHECK_INIT(ErrExit1)\r
- // \r
- ///* VAPI */\r
- // l_MddkStatus = VAPI_init_module();\r
- // CHECK_INIT(ErrExit1)\r
-\r
- } /* init Tavor modules */\r
-\r
- // resource tracking\r
-\r
- // Create dispatch points for create, close, unload\r
- pi_pDriverObject->DriverUnload = MdUnload;\r
- pi_pDriverObject->MajorFunction[IRP_MJ_CREATE] = MdCreate;\r
- pi_pDriverObject->MajorFunction[IRP_MJ_CLOSE] = MdClose;\r
- pi_pDriverObject->MajorFunction[IRP_MJ_DEVICE_CONTROL] = MdProcessIoctl;\r
-#ifdef MD_RW_SUPPORT\r
- pi_pDriverObject->MajorFunction[IRP_MJ_WRITE] = MdWrite;\r
- pi_pDriverObject->MajorFunction[IRP_MJ_READ] = MdRead;\r
-#endif\r
- pi_pDriverObject->MajorFunction[IRP_MJ_SYSTEM_CONTROL] = MdProcessSysControlIrp;\r
- pi_pDriverObject->MajorFunction[IRP_MJ_PNP] = MdProcessPnPIrp;\r
- pi_pDriverObject->MajorFunction[IRP_MJ_POWER] = MdProcessPowerIrp;\r
- pi_pDriverObject->DriverExtension->AddDevice = MdPnPAddDevice;\r
-\r
- // Debug print\r
- MdKdPrint( DBGLVL_DEFAULT,("(DriverEntry) Exit: Status %x\n", l_Status));\r
-\r
- return l_Status;\r
-\r
-ErrExit4:\r
- HH_cleanup_module();\r
-\r
-ErrExit3:\r
- MPGA_cleanup_module();\r
- MOSAL_cleanup();\r
-\r
-ErrExit1:\r
- /* Free the NT device name path buffer */\r
- if (l_usNtDeviceName.Buffer)\r
- MdExFreePool(l_usNtDeviceName.Buffer);\r
-\r
- /* Free the Dos device name path buffer */\r
- if (l_usDosDeviceName.Buffer)\r
- MdExFreePool(l_usDosDeviceName.Buffer);\r
-\r
- /* release driver context */\r
- if (l_pDrvContext != NULL)\r
- {\r
- g_pDrvContext = NULL;\r
- MdExFreePool( l_pDrvContext );\r
- }\r
- \r
-err:\r
-#pragma warning( push )\r
-#pragma warning( disable:4296 )\r
- MdKdPrint( DBGLVL_ALWAYS ,("(MdDeviceInit) Device failed to initialize \n"));\r
-#pragma warning( pop )\r
-\r
- CL_DEINIT;\r
-\r
- /* Write to event log */\r
- WriteEventLogEntry( pi_pDriverObject, MD_EVENT_LOG_LOAD_ERROR,\r
- 0, l_Status, 1, l_Status );\r
- return STATUS_UNSUCCESSFUL;\r
-}\r
-\r
-\r
-\r
-NTSTATUS DllInitialize(PUNICODE_STRING RegistryPath)\r
-{\r
- DbgPrint("\n***** MT23108: DllInitialize()\n");\r
- return STATUS_SUCCESS;\r
-}\r
-\r
-NTSTATUS DllUnload()\r
-{\r
- DbgPrint("\n***** MT23108: DllUnload()\n");\r
- return STATUS_SUCCESS;\r
-}\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-NTSTATUS\r
-MdProcessSysControlIrp(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN PIRP Irp\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Main dispatch table routine for IRP_MJ_SYSTEM_CONTROL\r
- We basically just pass these down to the PDO\r
-\r
-Arguments:\r
-\r
- DeviceObject - pointer to FDO device object\r
-\r
- Irp - pointer to an I/O Request Packet\r
-\r
-Return Value:\r
-\r
- Status returned from lower driver\r
-\r
-\r
---*/\r
-{\r
-\r
- PIO_STACK_LOCATION irpStack;\r
- PMD_DEV_CONTEXT_T l_pMdDevContext; \r
- NTSTATUS l_Status = STATUS_SUCCESS;\r
- PDEVICE_OBJECT stackDeviceObject;\r
-\r
- //Irp->IoStatus.Status = STATUS_SUCCESS;\r
- //Irp->IoStatus.Information = 0;\r
-\r
- //\r
- // Get a pointer to the current location in the Irp. This is where\r
- // the function codes and parameters are located.\r
- //\r
-\r
- irpStack = IoGetCurrentIrpStackLocation (Irp);\r
-\r
- //\r
- // Get a pointer to the device extension\r
- //\r
-\r
- l_pMdDevContext = DeviceObject->DeviceExtension;\r
- stackDeviceObject = l_pMdDevContext->m_pLdo;\r
-\r
- MdKdPrint( DBGLVL_HIGH, ( "(MdProcessSysControlIrp) enter \n") );\r
-\r
- MdIncrementIoCount(l_pMdDevContext);\r
-\r
- MDASSERT( IRP_MJ_SYSTEM_CONTROL == irpStack->MajorFunction );\r
-\r
- IoCopyCurrentIrpStackLocationToNext(Irp);\r
-\r
-\r
- l_Status = IoCallDriver(stackDeviceObject,\r
- Irp);\r
-\r
- MdDecrementIoCount(l_pMdDevContext);\r
-\r
- MdKdPrint( DBGLVL_HIGH,("(MdProcessSysControlIrp) Exit: MdProcessSysControlIrp %x\n", l_Status));\r
-\r
- return l_Status;\r
-}\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-VOID\r
-MdUnload(\r
- IN PDRIVER_OBJECT pi_pDriverObject\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Free all the allocated resources, etc.\r
-\r
-Arguments:\r
-\r
- pi_pDriverObject - pointer to a driver object\r
-\r
-Return Value:\r
-\r
-\r
---*/\r
-{\r
- /* driver context */\r
- PMD_DRV_CONTEXT_T l_pDrvContext = g_pDrvContext;\r
- PRE_LOCK_IT;\r
-\r
- MdKdPrint( DBGLVL_HIGH,("(MdUnload) enter \n"));\r
-\r
- // resources tracking\r
-\r
-\r
-if (l_pDrvContext->m_fSupportTavor) \r
-{ /* cleanup Tavor modules */\r
- //VAPI_cleanup_module();\r
- //VIPKL_cleanup_module();\r
- THH_cleanup_module();\r
- HH_cleanup_module();\r
- MPGA_cleanup_module();\r
-} /* cleanup Tavor modules */\r
-\r
- // de-init MOSAL\r
- MOSAL_cleanup();\r
-\r
- // remove control device\r
- if (l_pDrvContext->m_pCtlDevContext != NULL)\r
- MdDevDeInit( l_pDrvContext->m_pCtlDevContext );\r
- l_pDrvContext->m_pCtlDevContext = NULL;\r
-\r
- // check whether there are more devices \r
- LOCK_IT( &l_pDrvContext->m_SpinLock );\r
- if ( !IsListEmpty( &l_pDrvContext->m_DevQue ) )\r
- { /* not all the devices removed - error */\r
-\r
- UNLOCK_IT( &l_pDrvContext->m_SpinLock );\r
- MdKdPrint( DBGLVL_HIGH,("(MdUnload) Error - not all the devices removed\n"));\r
- return;\r
-\r
- } /* not all the devices removed - error */\r
- UNLOCK_IT( &l_pDrvContext->m_SpinLock );\r
-\r
- MdKdPrint( DBGLVL_DEFAULT,("(MdUnload) exit \n"));\r
-\r
- /* Cleanup mtl_common */\r
- mtl_common_cleanup();\r
-\r
- /* free the driver context */\r
- MdExFreePool( l_pDrvContext );\r
-\r
- CL_DEINIT;\r
-\r
- g_pDrvContext = NULL;\r
- \r
- MDASSERT( g_pDbgData->m_nExAllocCount == 0 );\r
-\r
-\r
-}\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-LONG\r
-MdDecrementIoCount(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- We keep a pending IO count ( extension->PendingIoCount ) in the device extension.\r
- The first increment of this count is done on adding the device.\r
- Subsequently, the count is incremented for each new IRP received and\r
- decremented when each IRP is completed or passed on.\r
-\r
- Transition to 'one' therefore indicates no IO is pending and signals\r
- deviceExtension->NoPendingIoEvent. This is needed for processing\r
- IRP_MN_QUERY_REMOVE_DEVICE\r
-\r
- Transition to 'zero' signals an event ( deviceExtension->RemoveEvent )\r
- to enable device removal. This is used in processing for IRP_MN_REMOVE_DEVICE\r
- \r
-Arguments:\r
-\r
- pi_pMdDevContext...... The device context\r
-\r
-Return Value:\r
-\r
- pi_pMdDevContext->PendingIoCount\r
-\r
-\r
---*/\r
-\r
-{\r
- KIRQL oldIrql;\r
- LONG ioCnt;\r
- MdKdPrint( DBGLVL_MAXIMUM,("(MdDecrementIoCount) Enter: Pending io count = %x\n", pi_pMdDevContext->m_nPendingIoCnt));\r
-\r
- KeAcquireSpinLock (&pi_pMdDevContext->m_IoCntSpinLock, &oldIrql);\r
- ioCnt = InterlockedDecrement( &pi_pMdDevContext->m_nPendingIoCnt );\r
-\r
- MdTrapCond( DBGLVL_HIGH,( 0 > pi_pMdDevContext->m_nPendingIoCnt ) );\r
- if (ioCnt == 1) \r
- KeSetEvent(&pi_pMdDevContext->m_NoPendingIoEvent, 1, FALSE); // trigger no pending io\r
-\r
- if (ioCnt == 0) \r
- KeSetEvent(&pi_pMdDevContext->m_RemoveEvent, 1, FALSE); // trigger remove-device event\r
- \r
- KeReleaseSpinLock (&pi_pMdDevContext->m_IoCntSpinLock, oldIrql);\r
- MdKdPrint( DBGLVL_HIGH,("(MdDecrementIoCount) Exit: Pending io count = %x\n", pi_pMdDevContext->m_nPendingIoCnt));\r
- return pi_pMdDevContext->m_nPendingIoCnt;\r
-}\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-VOID\r
-MdIncrementIoCount(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- We keep a pending IO count ( extension->PendingIoCount ) in the device extension.\r
- The first increment of this count is done on adding the device.\r
- Subsequently, the count is incremented for each new IRP received and\r
- decremented when each IRP is completed or passed on.\r
-\r
-\r
-Arguments:\r
-\r
- pi_pMdDevContext...... The device context\r
-\r
-Return Value:\r
-\r
- none.\r
-\r
---*/\r
-{\r
- KIRQL oldIrql;\r
- LONG ioCnt;\r
- MdKdPrint( DBGLVL_MAXIMUM,("(MdIncrementIoCount) Enter: Pending io count = %x\n", pi_pMdDevContext->m_nPendingIoCnt));\r
- KeAcquireSpinLock (&pi_pMdDevContext->m_IoCntSpinLock, &oldIrql);\r
- ioCnt = InterlockedIncrement( &pi_pMdDevContext->m_nPendingIoCnt );\r
-\r
- if (ioCnt > 1) \r
- KeClearEvent(&pi_pMdDevContext->m_NoPendingIoEvent); // trigger pending io\r
-\r
- KeReleaseSpinLock (&pi_pMdDevContext->m_IoCntSpinLock, oldIrql);\r
- MdKdPrint( DBGLVL_HIGH,("MdIncrementIoCount) Exit: Pending io count = %x\n", pi_pMdDevContext->m_nPendingIoCnt));\r
-}\r
-\r
-\r
-#undef _MD_C_\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef _MD_H_\r
-#define _MD_H_\r
-\r
-/* Base and offset for IO controls codes */\r
-#define MD_IOCTL_BASE 2050 /* Base code for kernel mode drivers */\r
-\r
-/*\r
-==============================================================================\r
-|Description : Defines the control codes passed to the adapter using the DLL |\r
-==============================================================================\r
-*/\r
-#define MD_RESET_DEVICE ( MD_IOCTL_BASE+0 )\r
-#define MD_READ ( MD_IOCTL_BASE+1 )\r
-#define MD_WRITE ( MD_IOCTL_BASE+2 )\r
-\r
-/*\r
-==============================================================================\r
-|Description : NT format of IO control codes based on the GSS codes. |\r
-==============================================================================\r
-*/\r
-#define MD_IOCTL_RESET_DEVICE CTL_CODE(FILE_DEVICE_UNKNOWN, MD_RESET_DEVICE, METHOD_BUFFERED, FILE_ANY_ACCESS)\r
-#define MD_IOCTL_READ CTL_CODE(FILE_DEVICE_UNKNOWN, MD_READ, METHOD_IN_DIRECT, FILE_ANY_ACCESS)\r
-#define MD_IOCTL_WRITE CTL_CODE(FILE_DEVICE_UNKNOWN, MD_WRITE, METHOD_OUT_DIRECT, FILE_ANY_ACCESS)\r
- \r
-\r
-\r
-#endif /* end, #ifndef _MD_H_ */\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-//Microsoft Developer Studio generated resource script.\r
-//\r
-#include "resource.h"\r
-#include "version.h"\r
-\r
-#define APSTUDIO_READONLY_SYMBOLS\r
-/////////////////////////////////////////////////////////////////////////////\r
-//\r
-// Generated from the TEXTINCLUDE 2 resource.\r
-//\r
-#define APSTUDIO_HIDDEN_SYMBOLS\r
-#include "windows.h"\r
-#undef APSTUDIO_HIDDEN_SYMBOLS\r
-#include "ntverp.h"\r
-\r
-/////////////////////////////////////////////////////////////////////////////\r
-#undef APSTUDIO_READONLY_SYMBOLS\r
-\r
-/////////////////////////////////////////////////////////////////////////////\r
-// English (U.S.) resources\r
-\r
-#if !defined(AFX_RESOURCE_DLL) || defined(AFX_TARG_ENU)\r
-#ifdef _WIN32\r
-LANGUAGE LANG_ENGLISH, SUBLANG_ENGLISH_US\r
-#pragma code_page(1252)\r
-#endif //_WIN32\r
-\r
-#ifndef _MAC\r
-/////////////////////////////////////////////////////////////////////////////\r
-//\r
-// Version\r
-//\r
-\r
-VS_VERSION_INFO VERSIONINFO\r
- FILEVERSION FV1,FV2,FV3,FV4\r
- PRODUCTVERSION PV1,PV2,PV3,PV4\r
- FILEFLAGSMASK 0x3fL\r
-#ifdef _DEBUG\r
- FILEFLAGS 0x1L\r
-#else\r
- FILEFLAGS 0x0L\r
-#endif\r
- FILEOS 0x40004L\r
- FILETYPE 0x2L\r
- FILESUBTYPE 0x0L\r
-BEGIN\r
- BLOCK "StringFileInfo"\r
- BEGIN\r
- BLOCK "040904b0"\r
- BEGIN\r
- VALUE "Comments", "\0"\r
- VALUE "CompanyName", "Mellanox Technologies Ltd.\0"\r
- VALUE "FileDescription", FILE_DESCRIPTION\r
- VALUE "FileVersion", FILE_VERSION\r
- VALUE "InternalName", INTERNAL_NAME\r
- VALUE "LegalCopyright", "Copyright (C) Mellanox Technologies Ltd. 2001\0"\r
- VALUE "LegalTrademarks", "\0"\r
- VALUE "OriginalFilename", ORIGINAL_NAME\r
- VALUE "PrivateBuild", PRIVATE_BUILD\r
- VALUE "ProductName", PRODUCT_NAME\r
- VALUE "ProductVersion", PRODUCT_VERSION\r
- VALUE "SpecialBuild", SPECIAL_BUILD\r
- END\r
- END\r
- BLOCK "VarFileInfo"\r
- BEGIN\r
- VALUE "Translation", 0x409, 1200\r
- END\r
-END\r
-\r
-#endif // !_MAC\r
-\r
-\r
-#ifdef APSTUDIO_INVOKED\r
-/////////////////////////////////////////////////////////////////////////////\r
-//\r
-// TEXTINCLUDE\r
-//\r
-\r
-1 TEXTINCLUDE DISCARDABLE \r
-BEGIN\r
- "resource.h\0"\r
-END\r
-\r
-2 TEXTINCLUDE DISCARDABLE \r
-BEGIN\r
- "#define APSTUDIO_HIDDEN_SYMBOLS\r\n"\r
- "#include ""windows.h""\r\n"\r
- "#undef APSTUDIO_HIDDEN_SYMBOLS\r\n"\r
- "#include ""ntverp.h""\r\n"\r
- "\0"\r
-END\r
-\r
-3 TEXTINCLUDE DISCARDABLE \r
-BEGIN\r
- "\r\n"\r
- "\0"\r
-END\r
-\r
-#endif // APSTUDIO_INVOKED\r
-\r
-\r
-/////////////////////////////////////////////////////////////////////////////\r
-//\r
-// Dialog\r
-//\r
-\r
-IDD_DIALOG1 DIALOG DISCARDABLE 0, 0, 186, 95\r
-STYLE DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU\r
-CAPTION "Dialog"\r
-FONT 8, "MS Sans Serif"\r
-BEGIN\r
- DEFPUSHBUTTON "OK",IDOK,129,7,50,14\r
- PUSHBUTTON "Cancel",IDCANCEL,129,24,50,14\r
-END\r
-\r
-\r
-/////////////////////////////////////////////////////////////////////////////\r
-//\r
-// DESIGNINFO\r
-//\r
-\r
-#ifdef APSTUDIO_INVOKED\r
-GUIDELINES DESIGNINFO DISCARDABLE \r
-BEGIN\r
- IDD_DIALOG1, DIALOG\r
- BEGIN\r
- LEFTMARGIN, 7\r
- RIGHTMARGIN, 179\r
- TOPMARGIN, 7\r
- BOTTOMMARGIN, 88\r
- END\r
-END\r
-#endif // APSTUDIO_INVOKED\r
-\r
-#endif // English (U.S.) resources\r
-/////////////////////////////////////////////////////////////////////////////\r
-\r
-\r
-\r
-#ifndef APSTUDIO_INVOKED\r
-/////////////////////////////////////////////////////////////////////////////\r
-//\r
-// Generated from the TEXTINCLUDE 3 resource.\r
-//\r
-\r
-\r
-/////////////////////////////////////////////////////////////////////////////\r
-#endif // not APSTUDIO_INVOKED\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef _MD_CARD_H\r
-#define _MD_CARD_H\r
-\r
-#include <ntddk.h>\r
-#include <mtl_common.h>\r
-#include "MdDbg.h"\r
-#include "mosal.h"\r
-#include "mosal_util.h"\r
-#include <vapi_common.h>\r
-#include <hh.h>\r
-\r
-////////////////////////////////////////////////////////////////////////////\r
-// RESTRICTIONS\r
-////////////////////////////////////////////////////////////////////////////\r
-\r
-/* \r
- * Maximal device name length \r
- */\r
-#define MD_MAX_DEV_NAME_LEN 255\r
-\r
-/* \r
- * Maximal device params length \r
- */\r
-#define MD_MAX_DEV_PARAMS_LEN 255\r
-\r
-/* \r
- * Device name DB size\r
- */\r
- #define MD_MAX_DEV_DB_SIZE 1024\r
-\r
-/* \r
- * PCI header size\r
- */\r
- #define PCI_HDR_SIZE 64\r
- \r
-////////////////////////////////////////////////////////////////////////////\r
-// DEFAULTS\r
-////////////////////////////////////////////////////////////////////////////\r
-#define MD_DFLT_CONF_ADDR 88\r
-#define MD_DFLT_CONF_DATA 92\r
-#define MD_DFLT_DDR_OFFSET 0\r
-#define MD_DFLT_DDR_SIZE 0x10000000\r
-\r
-\r
-////////////////////////////////////////////////////////////////////////////\r
-// CONSTANTS\r
-////////////////////////////////////////////////////////////////////////////\r
-\r
-/* \r
- * Driver control device name\r
- */\r
-#define MD_CTL_DEVICE_NAME "MDCTL"\r
-#define MLX_VENDOR_ID 0x15B3\r
-\r
-////////////////////////////////////////////////////////////////////////////\r
-// ENUMERATIONS\r
-////////////////////////////////////////////////////////////////////////////\r
-\r
-// Device Ids \r
-typedef enum { \r
- MD_DEV_ID_CTRL=0, \r
- MD_DEV_ID_TAVOR=23108, \r
- MD_DEV_ID_TAVOR_BD=23109, \r
- MD_DEV_ID_TAVOR_SD=23130, \r
- MD_DEV_ID_ARBEL_TM=25208 /* ARBEL in TAvor mode */\r
-} MD_DEV_ID_E;\r
-\r
-// IB Device type\r
-typedef enum { \r
- MD_DEV_IX_CTRL=0, \r
- MD_DEV_IX_TAVOR, \r
- MD_DEV_IX_TAVOR_BD, \r
- MD_DEV_IX_TAVOR_SD, \r
- MD_DEV_IX_ARBEL_TM, /* ARBEL in TAvor mode */\r
- MD_DEV_IX_LAST \r
-} MD_DEV_IX_E;\r
-\r
- \r
-////////////////////////////////////////////////////////////////////////////\r
-// MACROS\r
-////////////////////////////////////////////////////////////////////////////\r
- \r
-\r
-/*\r
- * Work with CR_SPACE\r
- */\r
-#define MD_CR_DWORD_WRITE(dev,addr,value) \\r
- if (dev->m_fUsePorts) ? WRITE_PORT_ULONG((addr),(value)) : WRITE_REGISTER_ULONG((addr),(value))\r
-#define MD_CR_DWORD_READ(dev,addr,value) \\r
- value = (dev->m_fUsePorts) ? READ_PORT_ULONG((addr)) : READ_REGISTER_ULONG((addr))\r
-\r
-// for WinNt\r
-#define PRE_LOCK_IT KIRQL l_OldIrql\r
-#define INIT_LOCK_IT(a) KeInitializeSpinLock(a)\r
-#define LOCK_IT(a) KeAcquireSpinLock((a),&l_OldIrql)\r
-#define UNLOCK_IT(a) KeReleaseSpinLock((a),l_OldIrql)\r
-\r
-// mutexes\r
-#define KMUTEX_INIT(a) KeInitializeMutex(a,0)\r
-#define KMUTEX_ACQ(a) KeWaitForMutexObject( a, Executive, KernelMode, FALSE, NULL )\r
-#define KMUTEX_REL(a) KeReleaseMutex(a, FALSE)\r
-\r
-#define FMUTEX_INIT(a) ExInitializeFastMutex(a)\r
-#define FMUTEX_ACQ(a) ExAcquireFastMutex(a)\r
-#define FMUTEX_REL(a) ExReleaseFastMutex(a)\r
-\r
-// semaphores\r
-#define KSEM_INIT(a) KeInitializeSemaphore(a,1,1)\r
-#define KSEM_ACQ(a) KeWaitForSingleObject( a, Executive, KernelMode, FALSE, NULL )\r
-#define KSEM_REL(a) KeReleaseSemaphore(a, 0, 1, FALSE)\r
-\r
-\r
-\r
-////////////////////////////////////////////////////////////////////////////\r
-// STRUCTURES\r
-////////////////////////////////////////////////////////////////////////////\r
-\r
-//\r
-// MDHAL DB \r
-//\r
-typedef struct MD_HAL_DEV_PARAMS_S {\r
-\r
- /* buffer for DevId string */\r
- WCHAR m_DevIdWstr[5];\r
- // format string for building internal name\r
- PCHAR m_Format; \r
- // format string for building exported name\r
- PCHAR m_ExFormat; \r
- // Device ID (in PCI configuration) \r
- MD_DEV_ID_E m_DevId; \r
- // Device IX (in PCI configuration) \r
- MD_DEV_IX_E m_DevIx; \r
- // export to user\r
- BOOLEAN m_fExpose;\r
- // BAR sizes (approximately)\r
- ULONG m_SizeBar0;\r
- ULONG m_SizeBar1;\r
- ULONG m_SizeBar2;\r
- // the device clock frequency \r
- u_int32_t m_ClockFreq; \r
- // number of bits per device word \r
- u_int8_t m_WordSize; \r
- // 1 means opposite to platform endianess \r
- u_int8_t m_Endianess; \r
-\r
-} MD_HAL_DEV_PARAMS_T, *PMD_HAL_DEV_PARAMS_T;\r
-\r
-\r
-typedef struct MD_DEV_CONTEXT_S *PMD_DEV_CONTEXT_T;\r
-\r
-typedef PFILE_OBJECT PCS_HANDLE_T;\r
-\r
-//\r
-// Process context - saved in PFILE_OBJECT->FsContext\r
-//\r
-typedef struct MD_PCS_CONTEXT_S {\r
-\r
- // TAVOR (VIPKL) info\r
- // IB_MGT resource tracking\r
- PVOID m_hIbMgt;\r
- // VIPKL resource tracking\r
- PVOID m_hVipkl;\r
- // MOSAL info\r
- PVOID m_hMosal;\r
-\r
- // IB_MGT info\r
- \r
- // MDCTL info\r
- // MDL for CR\r
- PMDL m_pCrMdl;\r
- // MDL for UAR\r
- PMDL m_pUarMdl;\r
- // MDL for DDR\r
- PMDL m_pDdrMdl;\r
-\r
- // SANITY CHECK info\r
- // PID\r
- MOSAL_pid_t m_Pid;\r
-\r
-} MD_PCS_CONTEXT_T, *PMD_PCS_CONTEXT_T;\r
-\r
-#define MAKE_PCS(a) ((PMD_PCS_CONTEXT_T)(a))\r
-\r
-\r
-//\r
-// Driver context\r
-//\r
-typedef struct MD_DRV_CONTEXT_S {\r
-\r
- // driver object\r
- PDRIVER_OBJECT m_pDrvObject;\r
-\r
- // Debug Print Level\r
- ULONG m_nDebugPrintLevel;\r
-\r
- // FIFO queue of devices, added (for debug purposes)\r
- LIST_ENTRY m_DevQue;\r
-\r
- // current number of devices\r
- ULONG m_uDevNo;\r
- \r
- // current number of adapters\r
- ULONG m_uCardNo;\r
- \r
-\r
- /* control device context */\r
- PMD_DEV_CONTEXT_T m_pCtlDevContext;\r
-\r
- /* device name DB */\r
- ULONG m_DevNamesDbSize;\r
- ULONG m_DevNamesDbCnt;\r
- char m_DevNamesDb[MD_MAX_DEV_DB_SIZE];\r
-\r
- /* protection */\r
- KSPIN_LOCK m_SpinLock;\r
- \r
- /* various features support */\r
- ULONG m_ThhLegacySqp;\r
- BOOLEAN m_fSupportIbMgt;\r
- BOOLEAN m_fSupportTavor;\r
- ULONG m_AvInHostMem; /* AV in host memory (and not in DDR) */ \r
- ULONG m_InfiniteCmdTimeout; /* when 1 we use inifinite timeouts on commands completion */\r
- ULONG m_NumCmdsOuts; /* max number of outstanding commands */\r
- ULONG m_FatalDelayHalt;\r
- ULONG m_AsyncEqSize;\r
- ULONG m_CmdifUseUar0;\r
- ULONG m_IgnoreSubsystemId;\r
-\r
- int m_IbMgtQp0Only; /* for IB_MGT: use QP0 only */\r
-\r
-} MD_DRV_CONTEXT_T, *PMD_DRV_CONTEXT_T;\r
-\r
-//\r
-// Control device context\r
-//\r
-typedef struct MD_CTL_DEV_CONTEXT_S {\r
- int m_DummyCtl;\r
-} MD_CTL_DEV_CONTEXT_T, *PMD_CTL_DEV_CONTEXT_T;\r
-\r
-typedef struct MD_IB_DEV_TAVOR_S {\r
- VAPI_hca_hndl_t m_hHca;\r
- HH_hca_hndl_t m_hHhHca;\r
-} MD_IB_DEV_TAVOR_T, *PMD_IB_DEV_TAVOR_T;\r
-\r
-typedef struct MD_IB_DEV_TAVOR_BD_S {\r
- int m_DummyTavorBd;\r
-} MD_IB_DEV_TAVOR_BD_T, *PMD_IB_DEV_TAVOR_BD_T;\r
-\r
-typedef struct MD_IB_DEV_TAVOR_SD_S {\r
- PMD_DEV_CONTEXT_T m_pBdDevContext;\r
-} MD_IB_DEV_TAVOR_SD_T, *PMD_IB_DEV_TAVOR_SD_T;\r
-\r
-//\r
-// PCI Header info\r
-//\r
-typedef struct MD_PCI_HDR_S {\r
- ULONG m_Hdr[PCI_HDR_SIZE];\r
- ULONG m_Bus;\r
- ULONG m_Slot;\r
-} MD_PCI_HDR_T, *PMD_PCI_HDR_T;\r
-\r
-//\r
-// IB device context\r
-//\r
-typedef struct MD_IB_DEV_CONTEXT_S {\r
-\r
-\r
- ////////////////////////////////////////////////////////////////////////////\r
- // Device stack information\r
- ////////////////////////////////////////////////////////////////////////////\r
- \r
- // next-lower driver's device object, representing the target device \r
- PDEVICE_OBJECT m_pLdo;\r
-\r
- // The bus driver object\r
- PDEVICE_OBJECT m_pPdo;\r
-\r
- /* buffer for ASCII device name */\r
- char m_AsciiDevName[MD_MAX_DEV_NAME_LEN + 1];\r
-\r
- /* card number */\r
- ULONG m_uCardNo;\r
- \r
- ////////////////////////////////////////////////////////////////////////////\r
- // Device configuration information\r
- ////////////////////////////////////////////////////////////////////////////\r
- \r
- // device location\r
- ULONG m_BusNumber;\r
- ULONG m_DevNumber;\r
- ULONG m_Function;\r
- \r
- // IRQL\r
- ULONG m_ulIntVector;\r
- KIRQL m_ulIntLevel;\r
- KAFFINITY m_Affinity;\r
- BOOLEAN m_fIntShared;\r
- KINTERRUPT_MODE m_IntMode;\r
-\r
- // CR space\r
- MD_BAR_T m_Cr;\r
-\r
- // UAR-space region\r
- MD_BAR_T m_Uar;\r
-\r
- // memory range\r
- MD_BAR_T m_Ddr;\r
- ULONG m_ulDdrMapOffset;\r
- ULONG m_ulDdrMapSize;\r
- \r
- // register offsets\r
- ULONG m_ulAddrOffset;\r
- ULONG m_ulDataOffset;\r
-\r
- // PCI headers\r
- BOOLEAN m_fMayReset;\r
- MD_PCI_HDR_T m_MyHdr;\r
- MD_PCI_HDR_T m_HcaHdr;\r
- MD_PCI_HDR_T m_BridgeHdr;\r
- ULONG m_PerformReset;\r
- \r
- ////////////////////////////////////////////////////////////////////////////\r
- // Power management\r
- ////////////////////////////////////////////////////////////////////////////\r
-\r
- // current device power state\r
- DEVICE_POWER_STATE m_CurrentDevicePowerState;\r
-\r
- //Bus drivers set the appropriate values in this structure in response\r
- //to an IRP_MN_QUERY_CAPABILITIES IRP. Function and filter drivers might\r
- //alter the capabilities set by the bus driver.\r
- DEVICE_CAPABILITIES m_DeviceCapabilities;\r
-\r
- // used to save the currently-being-handled system-requested power irp request\r
- PIRP m_PowerIrp;\r
-\r
- // set to signal driver-generated power request is finished\r
- KEVENT m_SelfRequestedPowerIrpEvent;\r
-\r
- // flag set when IRP_MN_WAIT_WAKE is received and we're in a power state\r
- // where we can signal a wait\r
- BOOLEAN m_EnabledForWakeup;\r
-\r
- // used to flag that we're currently handling a self-generated power request\r
- BOOLEAN m_SelfPowerIrp;\r
-\r
- // default power state to power down to on self-suspend \r
- ULONG m_PowerDownLevel; \r
-\r
- ////////////////////////////////////////////////////////////////////////////\r
- // PnP handling\r
- ////////////////////////////////////////////////////////////////////////////\r
-\r
- //flag set when processing IRP_MN_REMOVE_DEVICE\r
- BOOLEAN m_DeviceRemoved;\r
-\r
- // flag set when driver has answered success to IRP_MN_QUERY_REMOVE_DEVICE\r
- BOOLEAN m_RemoveDeviceRequested;\r
-\r
- // flag set when driver has answered success to IRP_MN_QUERY_STOP_DEVICE\r
- BOOLEAN m_StopDeviceRequested;\r
-\r
- // MOSAL device handle\r
- MOSAL_dev_handle_t m_hMosal;\r
- \r
- // pointer to device parameters\r
- PMD_HAL_DEV_PARAMS_T m_pMdhalParams;\r
- \r
- /* DEVICE SPECIFIC PART */\r
- union {\r
- MD_IB_DEV_TAVOR_T;\r
- MD_IB_DEV_TAVOR_BD_T;\r
- MD_IB_DEV_TAVOR_SD_T;\r
- };\r
-\r
-} MD_IB_DEV_CONTEXT_T, *PMD_IB_DEV_CONTEXT_T;\r
-\r
-//\r
-// A structure representing the instance information associated with\r
-// this particular device.\r
-//\r
-\r
-typedef struct MD_DEV_CONTEXT_S {\r
-\r
- // FIFO queue of devices\r
- LIST_ENTRY m_Link;\r
-\r
- // global context\r
- PMD_DRV_CONTEXT_T m_pDrvContext;\r
-\r
- // device type\r
- MD_DEV_IX_E m_eDevType;\r
-\r
- // NT device handle\r
- PDEVICE_OBJECT m_pFdo;\r
-\r
- /* NT device name */\r
- UNICODE_STRING m_usNtDeviceName;\r
-\r
- /* DOS device name */\r
- UNICODE_STRING m_usDosDeviceName;\r
-\r
- /* device level spinlock */\r
- KSPIN_LOCK m_SpinLock;\r
-\r
- /* signature - for checking the handle */\r
- ULONG m_Signature;\r
-\r
- // spinlock used to protect inc/dec iocount logic\r
- KSPIN_LOCK m_IoCntSpinLock;\r
-\r
- /* pending IRP count */\r
- int m_nPendingIoCnt;\r
-\r
- // set when PendingIoCount goes to 0; flags device can be removed\r
- KEVENT m_RemoveEvent;\r
- \r
- // set when PendingIoCount goes to 1 ( 1st increment was on add device )\r
- // this indicates no IO requests outstanding, either user, system, or self-staged\r
- KEVENT m_NoPendingIoEvent;\r
-\r
- // flag set when device has been successfully started\r
- BOOLEAN m_DeviceStarted;\r
-\r
- // process list\r
- LIST_ENTRY m_PcsQue;\r
- \r
- // flag\r
- BOOLEAN m_fDeletePending;\r
-\r
- // semaphore\r
- KSEMAPHORE m_Sem;\r
- \r
- // mutex\r
- KMUTEX m_Mutex;\r
- \r
- // number of OPENs for this device\r
- int m_nOpenCount;\r
-\r
- // interface for r/w to PCI config space\r
- BUS_INTERFACE_STANDARD m_Interface;\r
- \r
- /* DEVICE SPECIFIC PART */\r
- union {\r
- MD_CTL_DEV_CONTEXT_T;\r
- MD_IB_DEV_CONTEXT_T;\r
- };\r
-\r
-} MD_DEV_CONTEXT_T, *PMD_DEV_CONTEXT_T;\r
-\r
-\r
-////////////////////////////////////////////////////////////////////////////\r
-// GLOBAL VARIABLES\r
-////////////////////////////////////////////////////////////////////////////\r
-\r
-#ifdef _MD_C_\r
- PMD_DRV_CONTEXT_T g_pDrvContext = NULL;\r
- MD_HAL_DEV_PARAMS_T g_DevParams[MD_DEV_IX_LAST] = {\r
- /* for CTRL */\r
- { L"0000", "", "", MD_DEV_ID_CTRL, MD_DEV_IX_CTRL, FALSE, 0,0,0, 0, 0, 0 },\r
- /* for TAVOR */\r
- { L"5A44", "InfiniHost%d", "InfiniHost%d", MD_DEV_ID_TAVOR, MD_DEV_IX_TAVOR, TRUE, 0x00100000, 0x01000000, 0x00000000, 167000000, 4, 0 },\r
- /* for TAVOR_BD */\r
- { L"5A45","mt%d_pciconf%d", "mt%d_pciconf%d", MD_DEV_ID_TAVOR_BD, MD_DEV_IX_TAVOR_BD, TRUE, 0x00000000, 0x00000000, 0x00000000, 167000000, 4, 0 },\r
- /* for TAVOR_SD */\r
- { L"5A5A", "mt%d_pci%d", "mt%d_pci%d", MD_DEV_ID_TAVOR_SD, MD_DEV_IX_TAVOR_SD, TRUE, 0x00100000, 0x01000000, 0x00000000, 167000000, 4, 0 },\r
- /* for TAVOR_SD */\r
- { L"6278", "InfiniHostEx%d", "InfiniHosEx%d", MD_DEV_ID_ARBEL_TM, MD_DEV_IX_ARBEL_TM, TRUE, 0x00100000, 0x01000000, 0x00000000, 167000000, 4, 0 },\r
- };\r
-\r
-#else\r
- extern PMD_DRV_CONTEXT_T g_pDrvContext;\r
- extern MD_HAL_DEV_PARAMS_T g_DevParams[MD_DEV_IX_LAST];\r
-#endif\r
-\r
-////////////////////////////////////////////////////////////////////////////\r
-// function prototypes\r
-////////////////////////////////////////////////////////////////////////////\r
-\r
-NTSTATUS\r
-MdProcessPnPIrp(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN PIRP Irp\r
- );\r
-\r
-NTSTATUS\r
-MdProcessSysControlIrp(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN PIRP Irp\r
- );\r
-\r
-VOID\r
-MdUnload(\r
- IN PDRIVER_OBJECT DriverObject\r
- );\r
-\r
-NTSTATUS\r
-MdStartDevice(\r
- IN PDEVICE_OBJECT pi_pFdo,\r
- IN PIRP pi_pIrp\r
- );\r
-\r
-NTSTATUS\r
-MdStopDevice(\r
- IN PDEVICE_OBJECT DeviceObject\r
- );\r
-\r
-NTSTATUS\r
-MdRemoveDevice(\r
- IN PDEVICE_OBJECT DeviceObject\r
- );\r
-\r
-NTSTATUS\r
-MdPnPAddDevice(\r
- IN PDRIVER_OBJECT DriverObject,\r
- IN PDEVICE_OBJECT pi_pPdo\r
- );\r
-\r
-NTSTATUS\r
-MdCreateDeviceObject(\r
- IN PDRIVER_OBJECT DriverObject,\r
- IN PDEVICE_OBJECT pi_pPdo,\r
- IN PDEVICE_OBJECT *DeviceObject\r
- );\r
-\r
-NTSTATUS\r
-MdConfigureDevice(\r
- IN PDEVICE_OBJECT DeviceObject\r
- );\r
-\r
-NTSTATUS\r
-MdIrpCompletionRoutine(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN PIRP Irp,\r
- IN PVOID Context\r
- );\r
-\r
-NTSTATUS\r
-MdPoRequestCompletion(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN UCHAR MinorFunction,\r
- IN POWER_STATE PowerState,\r
- IN PVOID Context,\r
- IN PIO_STATUS_BLOCK IoStatus\r
- );\r
-\r
-NTSTATUS\r
-MdPoSelfRequestCompletion(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN UCHAR MinorFunction,\r
- IN POWER_STATE PowerState,\r
- IN PVOID Context,\r
- IN PIO_STATUS_BLOCK IoStatus\r
- );\r
-\r
-NTSTATUS\r
-MdGetPortStatus(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN PULONG PortStatus\r
- );\r
-\r
-NTSTATUS\r
-MdResetParentPort(\r
- IN IN PDEVICE_OBJECT DeviceObject\r
- );\r
-\r
-NTSTATUS\r
-MdSelfRequestPowerIrp(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN POWER_STATE PowerState\r
- );\r
-\r
-BOOLEAN\r
-MdSetDevicePowerState(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN DEVICE_POWER_STATE DeviceState\r
- );\r
-\r
-NTSTATUS\r
-MdAsyncReadWrite_Complete(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN PIRP Irp,\r
- IN PVOID Context\r
- );\r
-\r
-NTSTATUS\r
-MdSimpleReadWrite_Complete(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN PIRP Irp,\r
- IN PVOID Context\r
- );\r
-\r
-\r
-NTSTATUS\r
-MdPowerIrp_Complete(\r
- IN PDEVICE_OBJECT NullDeviceObject,\r
- IN PIRP Irp,\r
- IN PVOID Context\r
- );\r
-\r
-NTSTATUS\r
-MdQueryCapabilities(\r
- IN PDEVICE_OBJECT pi_pLowerDevObject,\r
- OUT PDEVICE_CAPABILITIES po_pDeviceCapabilities\r
- );\r
-\r
-\r
-NTSTATUS\r
-MdWrite(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN PIRP Irp\r
- );\r
-\r
-NTSTATUS\r
-MdCreate(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN PIRP Irp\r
- );\r
-\r
-\r
-NTSTATUS\r
-MdRead(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN PIRP Irp\r
- );\r
-\r
-\r
-NTSTATUS\r
-MdAbortInPgsReqs(\r
- IN PDEVICE_OBJECT DeviceObject\r
- );\r
-\r
-\r
-NTSTATUS\r
-MdProcessIoctl(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN PIRP Irp\r
- );\r
-\r
-\r
-NTSTATUS\r
-MdResetDevice(\r
- IN PDEVICE_OBJECT DeviceObject\r
- );\r
-\r
-NTSTATUS\r
-MdClose(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN PIRP Irp\r
- );\r
-\r
-\r
-VOID\r
-MdIncrementIoCount(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext\r
- );\r
-\r
-LONG\r
-MdDecrementIoCount(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext\r
- );\r
-\r
-\r
-NTSTATUS\r
-MdProcessPowerIrp(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN PIRP Irp\r
- ); \r
-\r
-\r
-NTSTATUS\r
-MdStagedReadWrite(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN PIRP Irp,\r
- IN BOOLEAN Read\r
- );\r
-\r
-NTSTATUS\r
-MdSelfSuspendOrActivate(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN BOOLEAN fSuspend\r
- );\r
-\r
-NTSTATUS \r
-MdSymbolicLink(\r
- IN PDEVICE_OBJECT DeviceObject, \r
- IN OUT PUNICODE_STRING deviceLinkUnicodeString\r
- );\r
-\r
-\r
-BOOLEAN\r
-MdCancelPendingIo(\r
- IN PDEVICE_OBJECT DeviceObject\r
- );\r
-\r
-BOOLEAN\r
-MdCanAcceptIoRequests(\r
- IN PDEVICE_OBJECT DeviceObject\r
- );\r
-\r
-#endif // already included\r
-\r
-/*\r
- * Interface GUID - defined outside of conditional include statement on purpose.\r
- */\r
-// {4FAD14C1-D7D3-40bc-9C83-88498FE114F3}\r
-DEFINE_GUID(GUID_MD_INTERFACE, \r
-0x4fad14c1, 0xd7d3, 0x40bc, 0x9c, 0x83, 0x88, 0x49, 0x8f, 0xe1, 0x14, 0xf3);\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "MdGen.h"\r
-#include "MdConfPriv.h"\r
-#include "MdIoctlSpec.h"\r
-#include <initguid.h>\r
-#include <wdmguid.h> \r
-\r
-// select implementation of PciHdrWrite\r
-//#define USE_HalSetBusData 1\r
-//#define USE_HalSetBusDataByOffset 1\r
-#define USE_ReadWritePciConfig 1\r
-\r
-\r
-#define NOT_USE_MDNTDDK 1\r
-//#ifdef NOT_USE_MDNTDDK \r
-///* from ntddk.h */\r
-////\r
-//// Define types of bus information.\r
-////\r
-//\r
-//typedef enum _BUS_DATA_TYPE {\r
-// ConfigurationSpaceUndefined = -1,\r
-// Cmos,\r
-// EisaConfiguration,\r
-// Pos,\r
-// CbusConfiguration,\r
-// PCIConfiguration,\r
-// VMEConfiguration,\r
-// NuBusConfiguration,\r
-// PCMCIAConfiguration,\r
-// MPIConfiguration,\r
-// MPSAConfiguration,\r
-// PNPISAConfiguration,\r
-// SgiInternalConfiguration,\r
-// MaximumBusDataType\r
-//} BUS_DATA_TYPE, *PBUS_DATA_TYPE;\r
-//#ifdef __i386__\r
-//NTHALAPI\r
-//ULONG \r
-//HalGetBusData(\r
-// IN BUS_DATA_TYPE BusDataType,\r
-// IN ULONG BusNumber,\r
-// IN ULONG SlotNumber,\r
-// IN PVOID Buffer,\r
-// IN ULONG Length\r
-// );\r
-//\r
-//NTHALAPI\r
-//ULONG\r
-//HalGetBusDataByOffset(\r
-// IN BUS_DATA_TYPE BusDataType,\r
-// IN ULONG BusNumber,\r
-// IN ULONG SlotNumber,\r
-// IN PVOID Buffer,\r
-// IN ULONG Offset,\r
-// IN ULONG Length\r
-// );\r
-// \r
-//NTHALAPI\r
-//ULONG\r
-//HalSetBusData(\r
-// IN BUS_DATA_TYPE BusDataType,\r
-// IN ULONG BusNumber,\r
-// IN ULONG SlotNumber,\r
-// IN PVOID Buffer,\r
-// IN ULONG Length\r
-// );\r
-//\r
-//NTHALAPI\r
-//ULONG\r
-//HalSetBusDataByOffset(\r
-// IN BUS_DATA_TYPE BusDataType,\r
-// IN ULONG BusNumber,\r
-// IN ULONG SlotNumber,\r
-// IN PVOID Buffer,\r
-// IN ULONG Offset,\r
-// IN ULONG Length\r
-// );\r
-//#endif\r
-//#endif\r
-\r
-#ifndef USE_MOSAL\r
-/******************************************************************************\r
- * Function:\r
- * SendAwaitIrpCompletion\r
- *\r
- * Description:\r
- * IRP completion routine \r
- *\r
- * Parameters:\r
- *\r
- * Returns:\r
- * pointer to the entry on SUCCESS\r
- * NULL - otherwise\r
- *\r
- ******************************************************************************/\r
-NTSTATUS\r
-SendAwaitIrpCompletion (\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN PIRP Irp,\r
- IN PVOID Context\r
- )\r
-{\r
- UNREFERENCED_PARAMETER (DeviceObject); \r
- KeSetEvent ((PKEVENT) Context, IO_NO_INCREMENT, FALSE);\r
- return STATUS_MORE_PROCESSING_REQUIRED; // Keep this IRP\r
-}\r
-\r
-/******************************************************************************\r
- * Function:\r
- * SendAwaitIrp\r
- *\r
- * Description:\r
- * Create and send IRP stack down the stack and wait for the response (Blocking Mode)\r
- *\r
- * Parameters:\r
- * pi_pDeviceExt.......... ointer to USB device extension\r
- * pi_MajorCode........... IRP major code\r
- * pi_MinorCode........... IRP minor code\r
- * pi_pBuffer............. parameter buffer\r
- * pi_nSize............... size of the buffer\r
- *\r
- * Returns:\r
- * pointer to the entry on SUCCESS\r
- * NULL - otherwise\r
- *\r
- ******************************************************************************/\r
-NTSTATUS \r
-SendAwaitIrp(\r
- IN PDEVICE_OBJECT pi_pFdo,\r
- IN PDEVICE_OBJECT pi_pLdo,\r
- IN ULONG pi_MajorCode,\r
- IN ULONG pi_MinorCode,\r
- IN PVOID pi_pBuffer,\r
- IN int pi_nSize\r
- )\r
-/*++\r
-\r
- Routine Description: \r
-\r
- Create and send IRP stack down the stack and wait for the response (\r
-Blocking Mode)\r
-\r
- Arguments: \r
- \r
- pi_pFdo................ our device\r
- pi_pLdo................ lower device\r
- pi_MajorCode........... IRP major code\r
- pi_MinorCode........... IRP minor code\r
- pi_pBuffer............. parameter buffer\r
- pi_nSize............... size of the buffer\r
-\r
- Returns: \r
- \r
- standard NTSTATUS return codes.\r
-\r
- Notes:\r
-\r
---*/\r
-{ /* SendAwaitIrp */\r
- // Event\r
- KEVENT l_hEvent;\r
- // Pointer to IRP\r
- PIRP l_pIrp;\r
- // Stack location\r
- PIO_STACK_LOCATION l_pStackLocation;\r
- // Returned status\r
- NTSTATUS l_Status;\r
-\r
- // call validation\r
- if(KeGetCurrentIrql() != PASSIVE_LEVEL)\r
- return STATUS_SUCCESS;\r
-\r
- // create event\r
- KeInitializeEvent(&l_hEvent, NotificationEvent, FALSE);\r
-\r
- // build IRP request to USBD driver\r
- l_pIrp = IoAllocateIrp( pi_pFdo->StackSize, FALSE );\r
-\r
- // validate request\r
- if (!l_pIrp)\r
- {\r
- //MdKdPrint( DBGLVL_MAXIMUM, ("(SendAwaitIrp) Unable to allocate IRP !\n"));\r
- return STATUS_INSUFFICIENT_RESOURCES;\r
- }\r
-\r
- // fill IRP\r
- l_pIrp->IoStatus.Status = STATUS_NOT_SUPPORTED;\r
-\r
- // set completion routine\r
- IoSetCompletionRoutine(l_pIrp,SendAwaitIrpCompletion, &l_hEvent, TRUE, TRUE, TRUE);\r
-\r
- // fill stack location\r
- l_pStackLocation = IoGetNextIrpStackLocation(l_pIrp);\r
- l_pStackLocation->MajorFunction= (UCHAR)pi_MajorCode;\r
- l_pStackLocation->MinorFunction= (UCHAR)pi_MinorCode;\r
- RtlCopyMemory( &l_pStackLocation->Parameters, pi_pBuffer, pi_nSize );\r
-\r
- // Call lower driver perform request\r
- l_Status = IoCallDriver( pi_pLdo, l_pIrp ); \r
-\r
- // if the request not performed --> wait\r
- if (l_Status == STATUS_PENDING)\r
- {\r
- // Wait until the IRP will be complete\r
- KeWaitForSingleObject(\r
- &l_hEvent, // event to wait for\r
- Executive, // thread type (to wait into its context)\r
- KernelMode, // mode of work\r
- FALSE, // alertable\r
- NULL // timeout\r
- );\r
- l_Status = l_pIrp->IoStatus.Status;\r
- }\r
-\r
- IoFreeIrp(l_pIrp);\r
-\r
- return l_Status;\r
-\r
-} /* SendAwaitIrp */\r
-\r
-\r
-#endif\r
-\r
-/******************************************************************************\r
- * Function:\r
- * DrvReadWritePciConfig\r
- *\r
- * Description:\r
- * Create and send IRP stack down the stack and wait for the response (Blocking Mode)\r
- *\r
- * Parameters:\r
- *\r
- * Returns:\r
- * pointer to the entry on SUCCESS\r
- * NULL - otherwise\r
- *\r
- ******************************************************************************/\r
-NTSTATUS\r
-DrvReadWritePciConfig(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext,\r
- IN PVOID pi_pDataBuffer,\r
- IN ULONG pi_nPciSpaceOffset,\r
- IN ULONG pi_nDataLength,\r
- IN BOOLEAN pi_fReadConfig\r
- )\r
-\r
-{ /* DrvReadWritePciConfig */ \r
-\r
- // parameter buffer for the request\r
- DrvReadWriteConfig_t l_RwParams;\r
- ULONG l_nBytes;\r
-\r
- // parameter validation\r
- //MDASSERT(pi_pDataBuffer);\r
- //MDASSERT(pi_nDataLength);\r
-\r
- // try to do it directly\r
- if (pi_fReadConfig && pi_pMdDevContext->m_Interface.GetBusData) {\r
- l_nBytes = pi_pMdDevContext->m_Interface.GetBusData(\r
- pi_pMdDevContext->m_Interface.Context,\r
- PCI_WHICHSPACE_CONFIG,\r
- pi_pDataBuffer,\r
- pi_nPciSpaceOffset,\r
- pi_nDataLength\r
- ); \r
- return (l_nBytes != pi_nDataLength) ? STATUS_UNSUCCESSFUL : STATUS_SUCCESS;\r
- }\r
- else\r
- if (!pi_fReadConfig && pi_pMdDevContext->m_Interface.SetBusData) {\r
- pi_pMdDevContext->m_Interface.SetBusData(\r
- pi_pMdDevContext->m_Interface.Context,\r
- PCI_WHICHSPACE_CONFIG,\r
- pi_pDataBuffer,\r
- pi_nPciSpaceOffset,\r
- pi_nDataLength\r
- ); \r
- return STATUS_SUCCESS;\r
- }\r
- else { \r
- // fill request parameters\r
- l_RwParams.Buffer = pi_pDataBuffer;\r
- l_RwParams.Length = pi_nDataLength;\r
- l_RwParams.Offset = pi_nPciSpaceOffset;\r
- l_RwParams.WhichSpace = PCI_WHICHSPACE_CONFIG;\r
- \r
- return SendAwaitIrp( pi_pMdDevContext->m_pFdo, pi_pMdDevContext->m_pLdo, IRP_MJ_PNP, \r
- pi_fReadConfig ? IRP_MN_READ_CONFIG : IRP_MN_WRITE_CONFIG, &l_RwParams, sizeof(DrvReadWriteConfig_t));\r
- }\r
-\r
-} /* DrvReadWritePciConfig */ \r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-NTSTATUS\r
-PciIfOpen(\r
- IN PDEVICE_OBJECT pi_pFdo,\r
- IN PDEVICE_OBJECT pi_pLdo,\r
- IN PBUS_INTERFACE_STANDARD pi_pInterface\r
- )\r
-\r
-{ /* GetDirectPciInterface */ \r
-\r
- // parameter buffer for the request\r
- IO_STACK_LOCATION l_Stack;\r
-\r
- // clean interface data\r
- RtlZeroMemory( (PCHAR)pi_pInterface, sizeof(BUS_INTERFACE_STANDARD) );\r
-\r
- // fill request parameters\r
- l_Stack.Parameters.QueryInterface.InterfaceType = (LPGUID) &GUID_BUS_INTERFACE_STANDARD;\r
- l_Stack.Parameters.QueryInterface.Size = sizeof(BUS_INTERFACE_STANDARD);\r
- l_Stack.Parameters.QueryInterface.Version = 1;\r
- l_Stack.Parameters.QueryInterface.Interface = (PINTERFACE)pi_pInterface;\r
- l_Stack.Parameters.QueryInterface.InterfaceSpecificData = NULL;\r
- \r
- return SendAwaitIrp( pi_pFdo, pi_pLdo, IRP_MJ_PNP, \r
- IRP_MN_QUERY_INTERFACE, &l_Stack.Parameters, sizeof(l_Stack.Parameters));\r
-\r
-} /* GetDirectPciInterface */ \r
-\r
-PciIfClose(\r
- IN PBUS_INTERFACE_STANDARD pi_pInterface\r
- )\r
-{\r
- if (pi_pInterface->InterfaceDereference)\r
- pi_pInterface->InterfaceDereference((PVOID)pi_pInterface->Context);\r
-}\r
-\r
-#ifdef NOT_USE_MDNTDDK \r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-/* from wdm.h\r
-typedef struct _PCI_SLOT_NUMBER {\r
- union {\r
- struct {\r
- ULONG DeviceNumber:5;\r
- ULONG FunctionNumber:3;\r
- ULONG Reserved:24;\r
- } bits;\r
- ULONG AsULONG;\r
- } u;\r
-} PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER;\r
-*/\r
-\r
-#ifdef __i386__\r
-BOOLEAN PciFindDeviceByBusAndId( \r
- IN ULONG pi_MyBus, \r
- IN ULONG pi_DevId, \r
- IN OUT PULONG po_pSlot )\r
-{\r
-#define N_SLOTS 32\r
- ULONG l_Slot;\r
- ULONG l_DevId;\r
- ULONG l_Bytes;\r
-\r
- for (l_Slot = *po_pSlot; l_Slot < N_SLOTS; l_Slot++ ) {\r
-#pragma warning( push )\r
-#pragma warning( disable:4996 )\r
- l_Bytes = HalGetBusDataByOffset(\r
- PCIConfiguration,\r
- pi_MyBus,\r
- l_Slot,\r
- (PVOID)&l_DevId,\r
- 0,\r
- sizeof(ULONG)\r
- );\r
-#pragma warning( pop )\r
- if (l_Bytes != sizeof(ULONG)) \r
- continue; /* as if - "not found" */\r
- if (l_DevId == pi_DevId)\r
- break;\r
- }\r
- \r
- if (l_DevId == pi_DevId) {\r
- *po_pSlot = l_Slot;\r
- return TRUE;\r
- }\r
- else\r
- return FALSE;\r
-}\r
-\r
-BOOLEAN PciFindDeviceById( \r
- IN ULONG pi_DevId, \r
- IN OUT PULONG po_pBus, \r
- IN OUT PULONG po_pSlot )\r
-{\r
-#define N_BUSES 16\r
- ULONG l_Bus;\r
- ULONG l_Slot = *po_pSlot;\r
- \r
- for (l_Bus= *po_pBus; l_Bus < N_BUSES; l_Bus++, l_Slot=0) {\r
- if (PciFindDeviceByBusAndId(l_Bus, pi_DevId, &l_Slot))\r
- break;\r
- }\r
- if (l_Bus >= N_BUSES)\r
- return FALSE;\r
- *po_pBus = l_Bus;\r
- *po_pSlot = l_Slot;\r
- return TRUE;\r
-}\r
-\r
-BOOLEAN PciFindBridgeByBus( \r
- IN ULONG pi_SecBus, \r
- OUT PULONG po_pBus, \r
- OUT PULONG po_pSlot )\r
-{\r
-#define N_CARDS 8\r
- ULONG l_CardNo;\r
- ULONG l_Slot=0, l_Bus=0;\r
- ULONG l_DevId = ((int)(23110) << 16) | MLX_VENDOR_ID; \r
- ULONG l_SecBus, l_tmp, l_Bytes;\r
- \r
- for (l_CardNo= 0; l_CardNo < N_CARDS; l_CardNo++, l_Slot=0, l_Bus++) {\r
- if (PciFindDeviceById(l_DevId, &l_Bus, &l_Slot)) {\r
- /* found a bridge */\r
-#pragma warning( push )\r
-#pragma warning( disable:4996 )\r
- l_Bytes = HalGetBusDataByOffset(\r
- PCIConfiguration,\r
- l_Bus,\r
- l_Slot,\r
- (PVOID)&l_tmp,\r
- 24, /* 24 - PrimaryBus, 25 - SecondaryBus, 26 - SubordinateBus */\r
- sizeof(ULONG)\r
- );\r
-#pragma warning( pop )\r
- if (l_Bytes != sizeof(ULONG)) \r
- continue; /* as if - "not found" */\r
- l_SecBus = (l_tmp >> 16) & 255;\r
- if ( l_SecBus == pi_SecBus )\r
- break; /* found !!! */\r
- }\r
- }\r
- if (l_CardNo >= N_CARDS)\r
- return FALSE;\r
- *po_pBus = l_Bus;\r
- *po_pSlot = l_Slot;\r
- return TRUE;\r
-}\r
-#endif\r
-\r
-BOOLEAN PciFindPdoByPdoAndLocation( \r
- IN PDEVICE_OBJECT pi_pPdo,\r
- IN ULONG pi_Bus, \r
- IN ULONG pi_Slot,\r
- IN ULONG pi_Function,\r
- OUT PDEVICE_OBJECT * po_pPdo )\r
-{\r
- PDRIVER_OBJECT l_pDrv;\r
- PDEVICE_OBJECT l_pPdo;\r
- NTSTATUS l_Status;\r
- ULONG l_Slot, l_Bus, l_Function;\r
- \r
- // get to the PCI driver\r
- l_pDrv = pi_pPdo->DriverObject;\r
- \r
- // loop over all the PCI driver devices\r
- for ( l_pPdo = l_pDrv->DeviceObject; l_pPdo; l_pPdo = l_pPdo->NextDevice ) {\r
- // if it's not PDO - skip it\r
- if (!(l_pPdo->Flags & DO_BUS_ENUMERATED_DEVICE))\r
- continue;\r
- // get the location of the device of that PDO\r
- l_Status = MdGetDevLocation( l_pPdo, &l_Bus, &l_Slot, &l_Function );\r
- if (l_Status != STATUS_SUCCESS)\r
- continue;\r
- // check, whether it's our device\r
- if (l_Bus == pi_Bus && l_Slot == pi_Slot && l_Function == pi_Function)\r
- break;\r
- }\r
-\r
- // check whether we found the PDO\r
- if (!l_pPdo)\r
- return FALSE;\r
- *po_pPdo = l_pPdo;\r
- return TRUE; \r
-}\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-#ifdef __i386__\r
-\r
-NTSTATUS\r
-PciHdrRead(\r
- IN PVOID pi_pBuffer,\r
- IN ULONG pi_Bus,\r
- IN ULONG pi_Slot\r
- )\r
-{\r
- int l_Bytes;\r
- \r
-#pragma warning( push )\r
-#pragma warning( disable:4996 )\r
- l_Bytes = HalGetBusData(\r
- PCIConfiguration,\r
- pi_Bus,\r
- pi_Slot,\r
- pi_pBuffer,\r
- PCI_HDR_SIZE<<2\r
- );\r
-#pragma warning( pop )\r
- if (l_Bytes != PCI_HDR_SIZE<<2) {\r
- return STATUS_UNSUCCESSFUL;\r
- }\r
-\r
- return STATUS_SUCCESS;\r
-}\r
-#endif\r
-/*------------------------------------------------------------------------------------------------------*/\r
-NTSTATUS\r
-PciFixCmdReg(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext\r
- )\r
-{\r
- PDEVICE_OBJECT l_pLdo = pi_pMdDevContext->m_pLdo; /* Shrimp's PDO */\r
- BUS_INTERFACE_STANDARD l_Interface, *l_pInterface = &l_Interface;\r
- ULONG l_Value, l_NewValue;\r
- NTSTATUS l_Status = STATUS_SUCCESS;\r
- PDEVICE_OBJECT l_pFdo;\r
-\r
- if (pi_pMdDevContext->m_eDevType == MD_DEV_IX_TAVOR_SD) \r
- { /* fix HCA command register from SHRIMP */\r
- \r
- /* get the PDO of Bridge */\r
- if (!PciFindPdoByPdoAndLocation( l_pLdo, \r
- pi_pMdDevContext->m_BridgeHdr.m_Bus,\r
- pi_pMdDevContext->m_BridgeHdr.m_Slot,\r
- 0, &l_pLdo )) {\r
- MdKdPrint( DBGLVL_LOW,("(PciHdrWrite) Not found bridge PDO - can't restore the PCI header \n" ));\r
- return STATUS_UNSUCCESSFUL;\r
- }\r
- l_pFdo = l_pLdo->AttachedDevice;\r
-\r
- // open interface to PCI driver\r
- l_Status = PciIfOpen( l_pFdo, l_pLdo, l_pInterface );\r
- if (!NT_SUCCESS(l_Status)) {\r
- MdKdPrint( DBGLVL_LOW,("(PciFixCmdReg) PciIfOpen failed (0x%x) \n", l_Status ));\r
- return l_Status;\r
- }\r
- \r
- // read reg\r
- if (l_pInterface->GetBusData) \r
- l_pInterface->GetBusData( l_pInterface->Context, PCI_WHICHSPACE_CONFIG,\r
- (PVOID)&l_Value, 4, sizeof(ULONG) ); \r
-\r
- // fix\r
- l_NewValue = l_Value | 7;\r
- \r
- // write reg\r
- if (l_pInterface->SetBusData) \r
- l_pInterface->SetBusData( l_pInterface->Context, PCI_WHICHSPACE_CONFIG,\r
- (PVOID)&l_NewValue, 4, sizeof(ULONG) ); \r
-\r
- // close interface\r
- PciIfClose( l_pInterface );\r
-\r
- } /* fix HCA command register from SHRIMP */\r
-\r
- if (pi_pMdDevContext->m_eDevType == MD_DEV_IX_TAVOR \r
- || pi_pMdDevContext->m_eDevType ==MD_DEV_IX_ARBEL_TM) \r
- { /* fix command register for TAVOR */\r
-\r
- l_pInterface = &pi_pMdDevContext->m_Interface;\r
- // read reg\r
- if (l_pInterface->GetBusData) \r
- l_pInterface->GetBusData( l_pInterface->Context, PCI_WHICHSPACE_CONFIG,\r
- (PVOID)&l_Value, 4, sizeof(ULONG) ); \r
-\r
- // fix\r
- l_NewValue = l_Value | 7;\r
- \r
- // write reg\r
- if (l_pInterface->SetBusData) \r
- l_pInterface->SetBusData( l_pInterface->Context, PCI_WHICHSPACE_CONFIG,\r
- (PVOID)&l_NewValue, 4, sizeof(ULONG) ); \r
- \r
- } /* fix command register for TAVOR */\r
- \r
- MdKdPrint( DBGLVL_LOW,("(PciFixCmdReg) Cmd register: Old 0x%x New 0x%x \n", \r
- l_Value, l_NewValue ));\r
-\r
- return STATUS_SUCCESS;\r
-}\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-#ifdef __i386__\r
-typedef enum { WRITE_WITH_SET_BUS, WRITE_WITH_SET_BUS_BY_OFFSET, WRITE_WITH_PCI_CONFIG } PCI_WRITE_T;\r
-\r
-NTSTATUS\r
-PciHdrWrite(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext,\r
- IN PCHAR pi_pBuffer,\r
- IN ULONG pi_Bus,\r
- IN ULONG pi_Slot,\r
- IN PCI_WRITE_T pi_Technique\r
- )\r
-{\r
- if (pi_Technique == WRITE_WITH_PCI_CONFIG) {\r
- NTSTATUS l_Status = STATUS_SUCCESS;\r
- PDEVICE_OBJECT l_pLdo = pi_pMdDevContext->m_pLdo; /* Shrimp's PDO */\r
- BUS_INTERFACE_STANDARD l_Interface;\r
- PDEVICE_OBJECT l_pFdo;\r
-\r
- /* the following algorithm sutes only for SD */\r
- if (pi_pMdDevContext->m_eDevType == MD_DEV_IX_TAVOR_SD) {\r
-\r
- /* protect */\r
- KSEM_ACQ(&pi_pMdDevContext->m_Sem);\r
-\r
- /* get the PDO of Bridge */\r
- if (!PciFindPdoByPdoAndLocation( l_pLdo, \r
- pi_pMdDevContext->m_BridgeHdr.m_Bus,\r
- pi_pMdDevContext->m_BridgeHdr.m_Slot,\r
- 0, &l_pLdo )) {\r
- MdKdPrint( DBGLVL_LOW,("(PciHdrWrite) Not found bridge PDO - can't restore the PCI header \n" ));\r
- KSEM_REL(&pi_pMdDevContext->m_Sem);\r
- return STATUS_UNSUCCESSFUL;\r
- }\r
- l_pFdo = l_pLdo->AttachedDevice;\r
-\r
- // open interface to PCI driver\r
- l_Status = PciIfOpen( l_pFdo, l_pLdo, &l_Interface );\r
- if (!NT_SUCCESS(l_Status)) {\r
- MdKdPrint( DBGLVL_LOW,("(PciHdrWrite) PciIfOpen failed (0x%x) \n", l_Status ));\r
- KSEM_REL(&pi_pMdDevContext->m_Sem);\r
- return l_Status;\r
- }\r
-\r
- // write header\r
- if (l_Interface.SetBusData) {\r
- l_Interface.SetBusData( l_Interface.Context, PCI_WHICHSPACE_CONFIG,\r
- pi_pBuffer + 0x08, 0x08, PCI_HDR_SIZE - 0x08 );\r
- }\r
- \r
- // write some fields once more\r
- if (l_Interface.SetBusData) {\r
- /* Bridge Control Register */ \r
- l_Interface.SetBusData( l_Interface.Context, PCI_WHICHSPACE_CONFIG,\r
- pi_pBuffer + 0x3c, 0x3c, 4 ); \r
- /* The rest of header, including PCIX command register */ \r
- l_Interface.SetBusData( l_Interface.Context, PCI_WHICHSPACE_CONFIG,\r
- pi_pBuffer + PCI_HDR_SIZE, PCI_HDR_SIZE, (PCI_HDR_SIZE<<2) - PCI_HDR_SIZE );\r
- /* Command Register */\r
- l_Interface.SetBusData( l_Interface.Context, PCI_WHICHSPACE_CONFIG,\r
- pi_pBuffer + 0x04, 0x04, 4 ); \r
- } \r
- \r
- // close interface\r
- PciIfClose( &l_Interface );\r
-\r
- KSEM_REL(&pi_pMdDevContext->m_Sem);\r
- return l_Status;\r
- } \r
- else\r
- if (pi_pMdDevContext->m_eDevType == MD_DEV_IX_TAVOR || \r
- pi_pMdDevContext->m_eDevType == MD_DEV_IX_ARBEL_TM) {\r
-\r
- /* protect */\r
- KSEM_ACQ(&pi_pMdDevContext->m_Sem);\r
-\r
- /* get the PDO of Bridge */\r
- if (!PciFindPdoByPdoAndLocation( l_pLdo, \r
- pi_pMdDevContext->m_BridgeHdr.m_Bus,\r
- pi_pMdDevContext->m_BridgeHdr.m_Slot,\r
- 0, &l_pLdo )) {\r
- MdKdPrint( DBGLVL_LOW,("(PciHdrWrite) Not found bridge PDO - can't restore the PCI header \n" ));\r
- KSEM_REL(&pi_pMdDevContext->m_Sem);\r
- return STATUS_UNSUCCESSFUL;\r
- }\r
- l_pFdo = l_pLdo->AttachedDevice;\r
-\r
- // open interface to PCI driver\r
- l_Status = PciIfOpen( l_pFdo, l_pLdo, &l_Interface );\r
- if (!NT_SUCCESS(l_Status)) {\r
- MdKdPrint( DBGLVL_LOW,("(PciHdrWrite) PciIfOpen failed (0x%x) \n", l_Status ));\r
- KSEM_REL(&pi_pMdDevContext->m_Sem);\r
- return l_Status;\r
- }\r
-\r
- // write header\r
- if (l_Interface.SetBusData) {\r
- l_Interface.SetBusData( l_Interface.Context, PCI_WHICHSPACE_CONFIG,\r
- pi_pBuffer + 0x08, 0x08, PCI_HDR_SIZE - 0x08 );\r
- }\r
- \r
- // write some fields once more\r
- if (l_Interface.SetBusData) {\r
- /* Bridge Control Register */ \r
- l_Interface.SetBusData( l_Interface.Context, PCI_WHICHSPACE_CONFIG,\r
- pi_pBuffer + 0x3c, 0x3c, 4 ); \r
- /* The rest of header, including PCIX command register */ \r
- l_Interface.SetBusData( l_Interface.Context, PCI_WHICHSPACE_CONFIG,\r
- pi_pBuffer + PCI_HDR_SIZE, PCI_HDR_SIZE, (PCI_HDR_SIZE<<2) - PCI_HDR_SIZE );\r
- /* Command Register */\r
- l_Interface.SetBusData( l_Interface.Context, PCI_WHICHSPACE_CONFIG,\r
- pi_pBuffer + 0x04, 0x04, 4 ); \r
- } \r
- \r
- // close interface\r
- PciIfClose( &l_Interface );\r
- KSEM_REL(&pi_pMdDevContext->m_Sem);\r
- return l_Status;\r
- }\r
- else\r
- return STATUS_UNSUCCESSFUL;\r
-\r
- } \r
- \r
- else \r
- \r
- if (pi_Technique == WRITE_WITH_SET_BUS) {\r
- int l_Bytes;\r
-\r
-#pragma warning( push )\r
-#pragma warning( disable:4996 )\r
- l_Bytes = HalSetBusData(\r
- PCIConfiguration,\r
- pi_Bus,\r
- pi_Slot,\r
- pi_pBuffer,\r
- PCI_HDR_SIZE<<2\r
- );\r
-#pragma warning( pop )\r
- return STATUS_SUCCESS;\r
- } \r
- \r
- else\r
- \r
- if (pi_Technique == WRITE_WITH_SET_BUS_BY_OFFSET) {\r
- int l_Bytes;\r
- int i;\r
- \r
- PULONG l_pBuf = (PULONG)pi_pBuffer;\r
- \r
- for (i = 0; i < PCI_HDR_SIZE; i++) {\r
-#pragma warning( push )\r
-#pragma warning( disable:4996 )\r
- l_Bytes = HalSetBusDataByOffset(\r
- PCIConfiguration,\r
- pi_Bus,\r
- pi_Slot,\r
- &l_pBuf[i],\r
- i<<2,\r
- sizeof(ULONG)\r
- );\r
-#pragma warning( pop )\r
- }\r
- return STATUS_SUCCESS;\r
- }\r
-\r
- else\r
- return STATUS_UNSUCCESSFUL;\r
-}\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-NTSTATUS\r
-PciHdrSave(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext\r
- )\r
-{\r
- ULONG l_MyBus = pi_pMdDevContext->m_BusNumber;\r
- ULONG l_Slot, l_SecBus;\r
- ULONG l_DevId;\r
- NTSTATUS l_Status = STATUS_SUCCESS;\r
-\r
- /* prevent RESET if header not saved */\r
- pi_pMdDevContext->m_fMayReset = FALSE;\r
-\r
- /* NB: functionality supported only for MD_DEV_IX_TAVOR_SD and MD_DEV_IX_TAVOR_BD */\r
- if ((pi_pMdDevContext->m_eDevType == MD_DEV_IX_TAVOR_SD) || \r
- (pi_pMdDevContext->m_eDevType == MD_DEV_IX_TAVOR_BD)) {\r
- \r
- /* \r
- * My device\r
- */\r
- l_DevId = (pi_pMdDevContext->m_eDevType == MD_DEV_IX_TAVOR_BD) ? \r
- (((int)(MD_DEV_ID_TAVOR_BD) << 16) | MLX_VENDOR_ID) :\r
- (((int)(MD_DEV_ID_TAVOR_SD) << 16) | MLX_VENDOR_ID); \r
- l_Slot = 0;\r
- if (PciFindDeviceByBusAndId( l_MyBus, l_DevId, &l_Slot )) {\r
- l_Status = PciHdrRead( &pi_pMdDevContext->m_MyHdr.m_Hdr[0], l_MyBus, l_Slot); \r
- if (l_Status != STATUS_SUCCESS)\r
- return l_Status;\r
- }\r
- else { /* not found my device */\r
- return STATUS_UNSUCCESSFUL;\r
- }\r
- pi_pMdDevContext->m_MyHdr.m_Bus = l_MyBus;\r
- pi_pMdDevContext->m_MyHdr.m_Slot = l_Slot;\r
- \r
- \r
- /* \r
- * HCA device\r
- */\r
- l_DevId = ((int)(MD_DEV_ID_TAVOR) << 16) | MLX_VENDOR_ID; \r
- l_Slot = 0;\r
- if (PciFindDeviceByBusAndId( l_MyBus, l_DevId, &l_Slot )) {\r
- l_Status = PciHdrRead( &pi_pMdDevContext->m_HcaHdr.m_Hdr[0], l_MyBus, l_Slot); \r
- if (l_Status != STATUS_SUCCESS)\r
- return l_Status;\r
- }\r
- else { /* not found HCA device */\r
- if (pi_pMdDevContext->m_eDevType == MD_DEV_IX_TAVOR_SD) \r
- return STATUS_UNSUCCESSFUL;\r
- pi_pMdDevContext->m_HcaHdr.m_Hdr[0] = 0; /* mark, that PCI header was not saved */\r
- }\r
- pi_pMdDevContext->m_HcaHdr.m_Bus = l_MyBus;\r
- pi_pMdDevContext->m_HcaHdr.m_Slot = l_Slot;\r
- \r
- /* \r
- * Bridge device\r
- */\r
- l_SecBus = l_MyBus;\r
- if (PciFindBridgeByBus( l_SecBus, &l_MyBus, &l_Slot )) {\r
- l_Status = PciHdrRead( &pi_pMdDevContext->m_BridgeHdr.m_Hdr[0], l_MyBus, l_Slot); \r
- if (l_Status != STATUS_SUCCESS)\r
- return l_Status;\r
- }\r
- else { /* not found Bridge device */\r
- return STATUS_UNSUCCESSFUL;\r
- }\r
- pi_pMdDevContext->m_BridgeHdr.m_Bus = l_MyBus;\r
- pi_pMdDevContext->m_BridgeHdr.m_Slot = l_Slot;\r
-\r
- }\r
- else\r
- if (pi_pMdDevContext->m_eDevType == MD_DEV_IX_TAVOR ||\r
- pi_pMdDevContext->m_eDevType == MD_DEV_IX_ARBEL_TM) {\r
- \r
- /* \r
- * HCA device\r
- */\r
- l_DevId = ((int)(MD_DEV_ID_TAVOR) << 16) | MLX_VENDOR_ID; \r
- pi_pMdDevContext->m_HcaHdr.m_Hdr[0] = 0; /* mark, that PCI header was not saved */\r
- l_Slot = 0;\r
- if (PciFindDeviceByBusAndId( l_MyBus, l_DevId, &l_Slot )) {\r
- l_Status = PciHdrRead( &pi_pMdDevContext->m_HcaHdr.m_Hdr[0], l_MyBus, l_Slot); \r
- if (l_Status != STATUS_SUCCESS)\r
- return l_Status;\r
- }\r
- else { /* not found HCA device */\r
- return STATUS_UNSUCCESSFUL;\r
- }\r
- pi_pMdDevContext->m_HcaHdr.m_Bus = l_MyBus;\r
- pi_pMdDevContext->m_HcaHdr.m_Slot = l_Slot;\r
-\r
- /* \r
- * Bridge device\r
- */\r
- l_SecBus = l_MyBus;\r
- if (PciFindBridgeByBus( l_SecBus, &l_MyBus, &l_Slot )) {\r
- l_Status = PciHdrRead( &pi_pMdDevContext->m_BridgeHdr.m_Hdr[0], l_MyBus, l_Slot); \r
- if (l_Status != STATUS_SUCCESS)\r
- return l_Status;\r
- }\r
- else { /* not found Bridge device */\r
- return STATUS_UNSUCCESSFUL;\r
- }\r
- pi_pMdDevContext->m_BridgeHdr.m_Bus = l_MyBus;\r
- pi_pMdDevContext->m_BridgeHdr.m_Slot = l_Slot;\r
- }\r
- else\r
- return STATUS_UNSUCCESSFUL;\r
-\r
- /* enable Reset */\r
- pi_pMdDevContext->m_fMayReset = TRUE;\r
-\r
- return STATUS_SUCCESS;\r
-}\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-NTSTATUS\r
-PciHdrRestore(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext\r
- )\r
-{\r
-\r
- if (((pi_pMdDevContext->m_eDevType == MD_DEV_IX_TAVOR_SD) || \r
- (pi_pMdDevContext->m_eDevType == MD_DEV_IX_TAVOR_BD))) {\r
- /* \r
- * Bridge device\r
- */\r
- if (pi_pMdDevContext->m_BridgeHdr.m_Hdr[0]) {\r
- PciHdrWrite( pi_pMdDevContext, \r
- (PCHAR)&pi_pMdDevContext->m_BridgeHdr.m_Hdr[0], \r
- pi_pMdDevContext->m_BridgeHdr.m_Bus, \r
- pi_pMdDevContext->m_BridgeHdr.m_Slot,\r
- WRITE_WITH_PCI_CONFIG); \r
- }\r
- \r
- /* \r
- * My device\r
- */\r
- if (pi_pMdDevContext->m_MyHdr.m_Hdr[0]) {\r
- PciHdrWrite( pi_pMdDevContext, \r
- (PCHAR)&pi_pMdDevContext->m_MyHdr.m_Hdr[0], \r
- pi_pMdDevContext->m_MyHdr.m_Bus, \r
- pi_pMdDevContext->m_MyHdr.m_Slot,\r
- WRITE_WITH_SET_BUS); \r
- }\r
- \r
- /* \r
- * HCA device\r
- */\r
- if (pi_pMdDevContext->m_HcaHdr.m_Hdr[0]) {\r
- PciHdrWrite( pi_pMdDevContext, \r
- (PCHAR)&pi_pMdDevContext->m_HcaHdr.m_Hdr[0], \r
- pi_pMdDevContext->m_HcaHdr.m_Bus, \r
- pi_pMdDevContext->m_HcaHdr.m_Slot,\r
- WRITE_WITH_SET_BUS); \r
- }\r
- }\r
- else\r
- if (pi_pMdDevContext->m_eDevType == MD_DEV_IX_TAVOR ||\r
- pi_pMdDevContext->m_eDevType == MD_DEV_IX_ARBEL_TM) {\r
- \r
- /* \r
- * Bridge device\r
- */\r
- if (pi_pMdDevContext->m_BridgeHdr.m_Hdr[0]) {\r
- PciHdrWrite( pi_pMdDevContext, \r
- (PCHAR)&pi_pMdDevContext->m_BridgeHdr.m_Hdr[0], \r
- pi_pMdDevContext->m_BridgeHdr.m_Bus, \r
- pi_pMdDevContext->m_BridgeHdr.m_Slot,\r
- WRITE_WITH_PCI_CONFIG); \r
- }\r
- \r
- /* \r
- * HCA device\r
- */\r
- if (pi_pMdDevContext->m_HcaHdr.m_Hdr[0]) {\r
- PciHdrWrite( pi_pMdDevContext, \r
- (PCHAR)&pi_pMdDevContext->m_HcaHdr.m_Hdr[0], \r
- pi_pMdDevContext->m_HcaHdr.m_Bus, \r
- pi_pMdDevContext->m_HcaHdr.m_Slot,\r
- WRITE_WITH_SET_BUS); \r
- }\r
- }\r
- else\r
- return STATUS_UNSUCCESSFUL;\r
- \r
- return STATUS_SUCCESS;\r
-}\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-NTSTATUS\r
-PciReset(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext\r
- )\r
-{\r
- ULONG l_ResetOffset = 0x0f0010;\r
- ULONG l_ResetValue = 0x01000000; /* 1 in BigEndian */\r
- NTSTATUS l_Status;\r
- \r
- /* \r
- * RESET\r
- */\r
- if (pi_pMdDevContext->m_eDevType == MD_DEV_IX_TAVOR_BD) { /* we are burner device */\r
- PCICONF_WRITE( pi_pMdDevContext, \r
- l_ResetOffset, \r
- l_ResetValue, \r
- l_Status );\r
- }\r
- else \r
- if (pi_pMdDevContext->m_eDevType == MD_DEV_IX_TAVOR ||\r
- pi_pMdDevContext->m_eDevType == MD_DEV_IX_ARBEL_TM) { /* we are Tavor device */\r
- l_Status = PciDevReset(pi_pMdDevContext, l_ResetOffset, l_ResetValue );\r
- }\r
- else\r
- if (pi_pMdDevContext->m_eDevType == MD_DEV_IX_TAVOR_SD) { /* we are service device */\r
- l_Status = PciDevReset(pi_pMdDevContext, l_ResetOffset, l_ResetValue );\r
- }\r
- else { /* other devices not supported */\r
- l_Status = STATUS_UNSUCCESSFUL;\r
- }\r
-\r
- /* \r
- * wait for RESET end\r
- */\r
- {\r
- #define TIMEOUT_IN_USECS 1500000 /* 1.5 sec */\r
- LARGE_INTEGER timeout;\r
- timeout.QuadPart = - 10 * TIMEOUT_IN_USECS;\r
- KeDelayExecutionThread( KernelMode, FALSE, &timeout );\r
- }\r
- \r
- /* \r
- * Restore\r
- */\r
- l_Status = PciHdrRestore( pi_pMdDevContext );\r
-\r
- return l_Status;\r
-\r
-}\r
-\r
-#endif\r
-#endif\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-NTSTATUS ReadBarInfo( \r
- PMD_DEV_CONTEXT_T pi_pMdDevContext, \r
- ULONG pi_LowOffset,\r
- ULONG pi_HighOffset,\r
- ULONG pi_SizeOffset,\r
- PMD_BAR_T pi_pBar,\r
- PCHAR pi_BarName,\r
- ULONG pi_BarNum\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This routine reads BAR inforamtion from CR-space and stores it to device context\r
-\r
-Arguments:\r
-\r
- pi_pMdDevContext....... My device context\r
- pi_LowOffset........... offset of low part of BAR address\r
- pi_HighOffset.......... offset of high part of BAR address\r
- pi_SizeOffset.......... offset of BAR size\r
- pi_pBar ............... pointer to BAR descriptor\r
- pi_BarName............. BAR name for debug print \r
- pi_BarNum.............. BAR number\r
- \r
-Return Value:\r
-\r
- ERROR code.\r
-\r
---*/\r
-{ /* ReadBarInfo */\r
-\r
- ULONG l_LowPart, l_HighPart, l_Size;\r
- NTSTATUS l_Status;\r
- LARGE_INTEGER l_Offset = { 0,0 };\r
- \r
- //\r
- // read BAR0 \r
- //\r
- \r
- /* read CR-space */\r
- PCICONF_READ( pi_pMdDevContext, pi_LowOffset, &l_LowPart, l_Status );\r
- if (!NT_SUCCESS(l_Status))\r
- return l_Status;\r
- PCICONF_READ( pi_pMdDevContext, pi_HighOffset, &l_HighPart, l_Status );\r
- if (!NT_SUCCESS(l_Status))\r
- return l_Status;\r
- PCICONF_READ( pi_pMdDevContext, pi_SizeOffset, &l_Size, l_Status );\r
- if (!NT_SUCCESS(l_Status))\r
- return l_Status;\r
- \r
- /* store BAR parameters */\r
- pi_pBar->m_MemPhysAddr.LowPart = l_LowPart & 0xfff00000;\r
- pi_pBar->m_MemPhysAddr.HighPart = l_HighPart;\r
- pi_pBar->m_ulMemSize = 1 << ((l_Size & 63) + 20); /* l_size is 6 bit field */\r
- pi_pBar->m_usMemFlags = 0;\r
- pi_pBar->m_ulKernelSize = pi_pBar->m_ulMemSize;\r
- pi_pBar->m_ulKernelOffset = 0;\r
- \r
- /* recalculate boudaries of mapped memory for DDR */\r
- if (pi_BarNum == 2 && pi_pMdDevContext->m_ulDdrMapSize != -1) {\r
- pi_pBar->m_ulKernelSize = pi_pMdDevContext->m_ulDdrMapSize;\r
- pi_pBar->m_ulKernelOffset = pi_pMdDevContext->m_ulDdrMapOffset;\r
- l_Offset.LowPart = pi_pMdDevContext->m_ulDdrMapOffset;\r
- } /* for DDR - map some subset of memory */\r
- \r
- /* map physical address into virtual kernel one */\r
- l_Offset.QuadPart += pi_pBar->m_MemPhysAddr.QuadPart;\r
- pi_pBar->m_pKernelAddr = (PUCHAR) MmMapIoSpace(\r
- l_Offset, pi_pBar->m_ulKernelSize, MmNonCached);\r
- if (!pi_pBar->m_pKernelAddr) return STATUS_NO_MEMORY;\r
- \r
- /* debug print */\r
- MdKdPrint( DBGLVL_LOW ,("(ReadBarInfo) Dev %d %s: Phys 0x%I64x Size 0x%x, Virt 0x%x Size 0x%x \n", \r
- g_DevParams[pi_pMdDevContext->m_eDevType].m_DevId, \r
- pi_BarName, pi_pBar->m_MemPhysAddr, pi_pBar->m_ulMemSize, \r
- pi_pBar->m_pKernelAddr, pi_pBar->m_ulKernelSize ));\r
- \r
- return STATUS_SUCCESS;\r
-}\r
-\r
-NTSTATUS ReadBars(PMD_DEV_CONTEXT_T pi_pMdDevContext)\r
-{\r
- NTSTATUS l_Status;\r
- PMD_BAR_T l_pBar; \r
- \r
- /* BAR0 */\r
- l_pBar = &pi_pMdDevContext->m_Cr;\r
- l_Status = ReadBarInfo( pi_pMdDevContext, \r
- BYTE_OFFSET_A(Tavor->pcu0.pcu_address_decoder.hca_bar_0_lsbs),\r
- BYTE_OFFSET_A(Tavor->pcu0.pcu_address_decoder.hca_bar_0_msbs),\r
- BYTE_OFFSET_A(Tavor->pcu0.pcu_address_decoder.hca_bar_size_0),\r
- l_pBar, "CR", 0 );\r
- if (!NT_SUCCESS(l_Status))\r
- return l_Status;\r
- \r
- /* BAR1 */\r
- l_pBar = &pi_pMdDevContext->m_Uar;\r
- l_Status = ReadBarInfo( pi_pMdDevContext, \r
- BYTE_OFFSET_A(Tavor->pcu0.pcu_address_decoder.hca_bar_1_lsbs),\r
- BYTE_OFFSET_A(Tavor->pcu0.pcu_address_decoder.hca_bar_1_msbs),\r
- BYTE_OFFSET_A(Tavor->pcu0.pcu_address_decoder.hca_bar_size_1),\r
- l_pBar, "UAR", 1 );\r
- if (!NT_SUCCESS(l_Status))\r
- return l_Status;\r
- \r
- /* BAR2 */\r
- l_pBar = &pi_pMdDevContext->m_Ddr;\r
- l_Status = ReadBarInfo( pi_pMdDevContext, \r
- BYTE_OFFSET_A(Tavor->pcu0.pcu_address_decoder.dmu_bar_0_lsbs),\r
- BYTE_OFFSET_A(Tavor->pcu0.pcu_address_decoder.dmu_bar_0_msbs),\r
- BYTE_OFFSET_A(Tavor->pcu0.pcu_address_decoder.dmu_bar_size_0),\r
- l_pBar, "DDR", 2 );\r
- if (!NT_SUCCESS(l_Status))\r
- return l_Status;\r
-\r
- return STATUS_SUCCESS; \r
-} \r
- \r
-NTSTATUS ConfIoctl( \r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext, \r
- IN PMD_PCS_CONTEXT_T pi_pPcsContext,\r
- IN ULONG pi_nIoControlCode, \r
- IN PVOID pi_pInBuffer, \r
- IN ULONG pi_nInBufLength,\r
- IN PVOID pi_pOutBuffer, \r
- IN ULONG pi_nOutBufLength, \r
- OUT PULONG po_pnBytes \r
- )\r
-{\r
- NTSTATUS l_Status;\r
- PULONG l_pOffset;\r
- PULONG l_pData, l_Data;\r
- PPCICONF_MODIFY_T pm;\r
- PPCICONF_WRITE4_T pw;\r
-\r
- *po_pnBytes = 0;\r
- \r
- switch (pi_nIoControlCode)\r
- { /* handle Ioctls */\r
- \r
- case UDLL_MAKE_IOCTL(WIN_PCICONF_READ4):\r
- /* call_result_t PciConfRead4( HANDLE h, DWORD offset, DWORD * p_data ) */\r
- l_pOffset = (PULONG)pi_pInBuffer;\r
- l_pData = (PULONG)pi_pOutBuffer;\r
- PCICONF_READ( pi_pMdDevContext, *l_pOffset, l_pData, l_Status );\r
- if (!NT_SUCCESS(l_Status)) *po_pnBytes = sizeof(ULONG);\r
- break;\r
- \r
- case UDLL_MAKE_IOCTL(WIN_PCICONF_WRITE4):\r
- /* call_result_t PciConfWrite4( HANDLE h, PPCICONF_WRITE4_T params ) */\r
- pw =(PPCICONF_WRITE4_T)pi_pInBuffer;\r
- PCICONF_WRITE( pi_pMdDevContext, pw->offset, pw->data, l_Status );\r
- break;\r
- \r
- case UDLL_MAKE_IOCTL(WIN_PCICONF_MODIFY):\r
- /* call_result_t PciConfModify( HANDLE h, PPCICONF_MODIFY_T params, DWORD * p_old_data ) */\r
- pm = (PPCICONF_MODIFY_T)pi_pInBuffer;\r
- l_pData = (PULONG)pi_pOutBuffer;\r
-\r
- PCICONF_READ( pi_pMdDevContext, pm->offset, &l_Data, l_Status );\r
- if (!NT_SUCCESS(l_Status)) break;\r
- *l_Data = (*l_Data & ~pm->mask) | (pm->data & pm->mask);\r
- l_Status = PCICONF_DATA_WRITE(pi_pMdDevContext, l_Data );\r
- if (!NT_SUCCESS(l_Status)) *po_pnBytes = sizeof(ULONG);\r
- break;\r
-\r
- case UDLL_MAKE_IOCTL(WIN_SOFT_RESET):\r
- #ifdef __i386__\r
- l_Status = PciReset( pi_pMdDevContext );\r
- #endif\r
- break;\r
- \r
- default:\r
- MdKdPrint( DBGLVL_DEFAULT,("(ConfIoctl) Unsupported Ioctl 0x%x\n", pi_nIoControlCode));\r
- l_Status = STATUS_NOT_IMPLEMENTED;\r
- break;\r
-\r
- } /* handle Ioctls */\r
-\r
- return l_Status;\r
-}\r
-\r
-NTSTATUS\r
-ConfIoctlFast(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext,\r
- IN PIRP pi_pIrp\r
- )\r
-{\r
- NTSTATUS l_Status;\r
- PIO_STACK_LOCATION l_pIrpStack;\r
- \r
- /* get pointer to IRP stack */\r
- l_pIrpStack = IoGetCurrentIrpStackLocation (pi_pIrp);\r
- \r
- switch (l_pIrpStack->Parameters.DeviceIoControl.IoControlCode)\r
- { /* handle Ioctls */\r
- \r
- case UDLL_MAKE_IOCTL_BUF(WIN_PCICONF_READ4):\r
- /* call_result_t PciConfRead4( HANDLE h, DWORD offset, DWORD * p_data ) */\r
- PCICONF_READ( pi_pMdDevContext, \r
- *(PULONG)pi_pIrp->AssociatedIrp.SystemBuffer, \r
- (PULONG)pi_pIrp->AssociatedIrp.SystemBuffer, \r
- l_Status );\r
- if (NT_SUCCESS(l_Status)) \r
- pi_pIrp->IoStatus.Information = sizeof(ULONG);\r
- else \r
- pi_pIrp->IoStatus.Information = 0;\r
- break;\r
- \r
- case UDLL_MAKE_IOCTL_BUF(WIN_PCICONF_WRITE4):\r
- /* call_result_t PciConfWrite4( HANDLE h, PPCICONF_WRITE4_T params ) */\r
- PCICONF_WRITE( pi_pMdDevContext, \r
- *((PULONG)pi_pIrp->AssociatedIrp.SystemBuffer + 0), \r
- *((PULONG)pi_pIrp->AssociatedIrp.SystemBuffer + 1), \r
- l_Status );\r
- pi_pIrp->IoStatus.Information = 0;\r
- break;\r
- \r
- case UDLL_MAKE_IOCTL(WIN_SOFT_RESET):\r
- #ifdef __i386__\r
- l_Status = PciReset( pi_pMdDevContext );\r
- #endif\r
- pi_pIrp->IoStatus.Information = 0;\r
- break;\r
- \r
- default:\r
- MdKdPrint( DBGLVL_DEFAULT,("(ConfIoctl) Unsupported Ioctl 0x%x\n", \r
- l_pIrpStack->Parameters.DeviceIoControl.IoControlCode));\r
- pi_pIrp->IoStatus.Information = 0;\r
- l_Status = STATUS_NOT_IMPLEMENTED;\r
- break;\r
-\r
- } /* handle Ioctls */\r
-\r
- return l_Status;\r
-}\r
-\r
-void SetPciMasterBit(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext\r
-)\r
-{\r
- ULONG l_Data;\r
- ULONG l_Offset = 4;\r
- \r
- PCICONF_DWORD_READ( pi_pMdDevContext, &l_Data, l_Offset );\r
- MdKdPrint( DBGLVL_LOW,("(SetPciMasterBit) CmdStatus Reg 0x%x\n",l_Data)); \r
- l_Data |= 4;\r
- PCICONF_DWORD_WRITE( pi_pMdDevContext, l_Data, l_Offset );\r
- PCICONF_DWORD_READ( pi_pMdDevContext, &l_Data, l_Offset );\r
- MdKdPrint( DBGLVL_LOW,("(SetPciMasterBit) CmdStatus Reg 0x%x\n",l_Data)); \r
-}\r
-\r
-NTSTATUS MdMosalHelper( \r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext,\r
- IN int cmd\r
-)\r
-{\r
- NTSTATUS l_Status = STATUS_NOT_IMPLEMENTED; \r
- switch (cmd) {\r
- case MD_HELPER_CARD_RESET:\r
-#ifdef __i386__\r
- //l_Status = PciReset( pi_pMdDevContext );\r
-#endif\r
- break;\r
- default:\r
- break;\r
- }\r
- return l_Status;\r
-}\r
- \r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef _MD_CONF_H_\r
-#define _MD_CONF_H_\r
-\r
-NTSTATUS ReadBars(PMD_DEV_CONTEXT_T pi_pMdDevContext);\r
-\r
-NTSTATUS ConfIoctl( \r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext, \r
- IN PMD_PCS_CONTEXT_T pi_pPcsContext,\r
- IN ULONG pi_nIoControlCode, \r
- IN PVOID pi_pInBuffer, \r
- IN ULONG pi_nInBufLength,\r
- IN PVOID pi_pOutBuffer, \r
- IN ULONG pi_nOutBufLength, \r
- OUT PULONG po_pnBytes \r
- );\r
-\r
-NTSTATUS\r
-ConfIoctlFast(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext,\r
- IN PIRP pi_pIrp\r
- );\r
-\r
-NTSTATUS\r
-PciIfOpen(\r
- IN PDEVICE_OBJECT pi_pFdo,\r
- IN PDEVICE_OBJECT pi_pLdo,\r
- IN PBUS_INTERFACE_STANDARD pi_pInterface\r
- );\r
-\r
-PciIfClose(\r
- IN PBUS_INTERFACE_STANDARD pi_pInterface\r
- );\r
-\r
-void SetPciMasterBit(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext\r
-);\r
-\r
-NTSTATUS\r
-PciReset(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext\r
- );\r
-\r
-NTSTATUS\r
-PciHdrSave(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext\r
- );\r
-\r
-NTSTATUS\r
-PciFixCmdReg(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext\r
- );\r
-\r
-NTSTATUS\r
-DrvReadWritePciConfig(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext,\r
- IN PVOID pi_pDataBuffer,\r
- IN ULONG pi_nPciSpaceOffset,\r
- IN ULONG pi_nDataLength,\r
- IN BOOLEAN pi_fReadConfig\r
- );\r
-\r
-NTSTATUS MdMosalHelper( \r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext,\r
- IN int cmd\r
-);\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef _MD_CONF_PRIV_H_\r
-#define _MD_CONF_PRIV_H_\r
-\r
-#include <cr_types.h>\r
-#include <tavor_csp.h>\r
-/* #include <tavor_types.h> */\r
-typedef u_int32_t tavor_offset_t;\r
-\r
-static struct Tavor_st* const Tavor = (struct Tavor_st*)0;\r
-\r
-#define TAVOR_BIT_OFFSET(reg_path) \\r
- ((tavor_offset_t)(MT_ulong_ptr_t)&(reg_path ))\r
-\r
-/*************************************************\r
-*returned offset is in bytes align to word.....!!!!!!!!!!!!!!\r
-*************************************************/ \r
-#define BYTE_OFFSET_A(reg_path) \\r
- ((tavor_offset_t)((TAVOR_BIT_OFFSET(reg_path)>>5)<<2))\r
-\r
-\r
-#define PCICONF_DWORD_READ(dev,buf,offset) DrvReadWritePciConfig(dev,buf,(offset),sizeof(long), TRUE )\r
-#define PCICONF_DWORD_WRITE(dev,buf,offset) DrvReadWritePciConfig(dev,&buf,(offset),sizeof(long), FALSE )\r
-\r
-#define PCICONF_SET_ADDR(dev,buf) PCICONF_DWORD_WRITE(dev, (buf), dev->m_ulAddrOffset)\r
-#define PCICONF_DATA_READ(dev,buf) PCICONF_DWORD_READ(dev, (buf), dev->m_ulDataOffset)\r
-#define PCICONF_DATA_WRITE(dev,buf) PCICONF_DWORD_WRITE(dev, (buf), dev->m_ulDataOffset)\r
-\r
-#define PCICONF_READ(dev,off,buf,rc) \\r
- { \\r
- rc = PCICONF_SET_ADDR( (dev), (off) ); \\r
- if (NT_SUCCESS(rc)) \\r
- rc = PCICONF_DATA_READ((dev), (buf) ); \\r
- }\r
- \r
-#define PCICONF_WRITE(dev,off,buf,rc) \\r
- { \\r
- rc = PCICONF_SET_ADDR( (dev), (off) ); \\r
- if (NT_SUCCESS(rc)) \\r
- rc = PCICONF_DATA_WRITE((dev), (buf) ); \\r
- }\r
- \r
-typedef struct {\r
- ULONG WhichSpace;\r
- PVOID Buffer;\r
- ULONG Offset;\r
- ULONG POINTER_ALIGNMENT Length;\r
-} DrvReadWriteConfig_t, *PDrvReadWriteConfig_t;\r
-\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "MdGen.h"\r
-#include "MdIoctlSpec.h"\r
-\r
-call_result_t MOSAL_ioctl(int ops, void *pi, u_int32_t pi_sz, void *po, u_int32_t po_sz, u_int32_t* ret_po_sz_p );\r
-VIP_ret_t VIPKL_ioctl(int ops, void* rsct_arr, void *pi, u_int32_t isz, void *po, \r
- u_int32_t osz, u_int32_t* bs_p );\r
-int IB_MGT_sys(int ops, void *proc_state_p, void *pi, u_int32_t pi_sz, \r
- void *po, u_int32_t po_sz, u_int32_t* ret_po_sz_p );\r
-call_result_t MOSAL_manual_wrapper( void *res_p, int cmd, void *pi, void * po);\r
-\r
-\r
-\r
-\r
-NTSTATUS CtlIoctl( \r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext, \r
- IN PMD_PCS_CONTEXT_T pi_pPcsContext,\r
- IN ULONG pi_nIoControlCode, \r
- IN PVOID pi_pInBuffer, \r
- IN ULONG pi_nInBufLength,\r
- IN PVOID pi_pOutBuffer, \r
- IN ULONG pi_nOutBufLength, \r
- OUT PULONG po_pnBytes \r
- )\r
-{\r
- NTSTATUS l_Status;\r
- PULONG l_BufSize;\r
- PCTL_ENUM_T l_pBuf;\r
- int cmd = UDLL_MAKE_FUNC(pi_nIoControlCode);\r
-\r
- *po_pnBytes = 0;\r
-\r
- /* handle MOSAL requests */\r
- if (cmd >= MOSAL_FUNC_BASE && cmd < MOSAL_FUNC_MANUAL)\r
- { /* call MOSAL wrapper */ \r
- l_Status = (NTSTATUS)MOSAL_ioctl(cmd, pi_pInBuffer, pi_nInBufLength, \r
- pi_pOutBuffer, pi_nOutBufLength, po_pnBytes);\r
- if (!l_Status)\r
- *po_pnBytes = pi_nOutBufLength;\r
- return l_Status;\r
- } /* call MOSAL wrapper */\r
- \r
- if (cmd >= MOSAL_FUNC_MANUAL && cmd < MOSAL_FUNC_END)\r
- { /* call MOSAL manual wrapper */ \r
- l_Status = (NTSTATUS)MOSAL_manual_wrapper(pi_pPcsContext->m_hMosal, cmd, pi_pInBuffer, pi_pOutBuffer);\r
- if (!l_Status)\r
- *po_pnBytes = pi_nOutBufLength;\r
- return l_Status;\r
- } /* call MOSAL manual wrapper */\r
- \r
- /* handle VAPI requests */\r
- if (cmd >= VAPI_FUNC_BASE && cmd < VAPI_FUNC_END)\r
- { /* call VAPI wrapper */ \r
- return VIPKL_ioctl(cmd, pi_pPcsContext->m_hVipkl, pi_pInBuffer, pi_nInBufLength, \r
- pi_pOutBuffer, pi_nOutBufLength, po_pnBytes );\r
- } /* call VAPI wrapper */\r
- \r
- /* handle IB_MGT requests */\r
- if (cmd >= IBMGT_FUNC_BASE && cmd < IBMGT_FUNC_END)\r
- { /* call IB_MGT wrapper */ \r
- return IB_MGT_sys(cmd, pi_pPcsContext->m_hIbMgt, pi_pInBuffer, pi_nInBufLength, \r
- pi_pOutBuffer, pi_nOutBufLength, po_pnBytes );\r
- } /* call IB_MGT wrapper */\r
-\r
- switch (pi_nIoControlCode)\r
- { /* handle Ioctls */\r
- \r
- case UDLL_MAKE_IOCTL(WIN_CTL_ENUM):\r
- /* call_result_t CtlEnum( HANDLE h, DWORD data_size, PCTL_ENUM_T p_data ) */\r
- l_BufSize = (PULONG)pi_pInBuffer;\r
- l_pBuf = (PCTL_ENUM_T)pi_pOutBuffer;\r
- l_pBuf->size = g_pDrvContext->m_DevNamesDbSize;\r
- if (*l_BufSize < l_pBuf->size) {\r
- MdKdPrint( DBGLVL_DEFAULT,("(CtlIoctl) Buffer too small: given %d, req-d %d\n", \r
- *l_BufSize, l_pBuf->size));\r
- *po_pnBytes = sizeof(ULONG);\r
- l_Status = STATUS_BUFFER_TOO_SMALL; \r
- }\r
- else {\r
- RtlCopyMemory( &l_pBuf->data[0], &g_pDrvContext->m_DevNamesDb[0], l_pBuf->size );\r
- l_pBuf->cnt = g_pDrvContext->m_DevNamesDbCnt;\r
- *po_pnBytes = sizeof(ULONG) + sizeof(ULONG) + l_pBuf->size;\r
- l_Status = STATUS_SUCCESS;\r
- }\r
- break;\r
-\r
- default:\r
- MdKdPrint( DBGLVL_DEFAULT,("(CtlIoctl) Unsupported Ioctl 0x%x\n", pi_nIoControlCode));\r
- l_Status = STATUS_NOT_IMPLEMENTED;\r
- break;\r
-\r
- } /* handle Ioctls */\r
-\r
- return l_Status;\r
-}\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef _MD_CTL_H_\r
-#define _MD_CTL_H_\r
-\r
-NTSTATUS CtlIoctl( \r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext, \r
- IN PMD_PCS_CONTEXT_T pi_pPcsContext,\r
- IN ULONG pi_nIoControlCode, \r
- IN PVOID pi_pInBuffer, \r
- IN ULONG pi_nInBufLength,\r
- IN PVOID pi_pOutBuffer, \r
- IN ULONG pi_nOutBufLength, \r
- OUT PULONG po_pnBytes \r
- );\r
-\r
-#endif\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#if DBG\r
-\r
-#include "MdGen.h"\r
-\r
-\r
-// begin, data/code used only in DBG build\r
-/* global data */\r
-MD_DBG_DATA_T g_DbgData = { 0, 0 };\r
-PMD_DBG_DATA_T g_pDbgData = &g_DbgData;\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-PVOID \r
-MdExAllocatePool(\r
- IN POOL_TYPE PoolType,\r
- IN ULONG NumberOfBytes\r
- )\r
-{\r
- g_pDbgData->m_nExAllocCount++;\r
- MdKdPrint( DBGLVL_HIGH,("MdExAllocatePool() nExAllocCount = %d\n", g_pDbgData->m_nExAllocCount ));\r
- return ExAllocatePoolWithTag( PoolType, NumberOfBytes, 'xEdM' );\r
-\r
-}\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-\r
-VOID \r
-MdExFreePool(\r
- IN PVOID p\r
- )\r
-{\r
- g_pDbgData->m_nExAllocCount--;\r
- MdKdPrint( DBGLVL_HIGH,("MdExFreePool() nExAllocCount = %d\n", g_pDbgData->m_nExAllocCount ));\r
- ExFreePoolWithTag( p, 'xEdM' );\r
-}\r
-\r
-\r
-#endif // end , if DBG\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef _MD_DBG_H_\r
-#define _MD_DBG_H_\r
-\r
-\r
-#if DBG\r
-\r
-\r
-/* The above will print if g_pDrvContext->m_nDebugPrintLevel >= DBGLVL_MEDIUM */\r
-\r
-#define DBGLVL_ALWAYS 0 /* always printed */\r
-#define DBGLVL_MINIMUM 1 /* minimum verbosity */\r
-#define DBGLVL_LOW 2 /* medium verbosity */\r
-#define DBGLVL_MEDIUM 3 /* medium verbosity */\r
-#define DBGLVL_HIGH 4 /* highest 'safe' level (without severely affecting timing ) */\r
-#define DBGLVL_MAXIMUM 5 /* maximum level, may be dangerous */\r
-#define DBGLVL_DEFAULT DBGLVL_LOW /* default verbosity level if no registry override */\r
-\r
-\r
-\r
-#ifndef DBGSTR_PREFIX\r
-#define DBGSTR_PREFIX "Mdt: " \r
-#endif\r
-\r
-\r
-\r
-\r
-#define DPRINT DbgPrint\r
-\r
-#define TRAP() DbgBreakPoint();\r
-\r
-\r
-#define MdDBGOUTSIZE 512\r
-\r
-\r
-typedef struct MD_DBG_DATA_S {\r
-\r
- /* mirrors device extension pending io count */\r
- ULONG m_nPendingIoCount;\r
-\r
- /* allocations counter */\r
- ULONG m_nExAllocCount;\r
-\r
-} MD_DBG_DATA_T, *PMD_DBG_DATA_T;\r
-\r
-/* these declared in debug 'c' file */\r
-extern PMD_DBG_DATA_T g_pDbgData; \r
-\r
-\r
-static const PCHAR szIrpMajFuncDesc[] =\r
-{ /* note this depends on corresponding values to the indexes in wdm.h */\r
- "IRP_MJ_CREATE",\r
- "IRP_MJ_CREATE_NAMED_PIPE",\r
- "IRP_MJ_CLOSE",\r
- "IRP_MJ_READ",\r
- "IRP_MJ_WRITE",\r
- "IRP_MJ_QUERY_INFORMATION",\r
- "IRP_MJ_SET_INFORMATION",\r
- "IRP_MJ_QUERY_EA",\r
- "IRP_MJ_SET_EA",\r
- "IRP_MJ_FLUSH_BUFFERS",\r
- "IRP_MJ_QUERY_VOLUME_INFORMATION",\r
- "IRP_MJ_SET_VOLUME_INFORMATION",\r
- "IRP_MJ_DIRECTORY_CONTROL",\r
- "IRP_MJ_FILE_SYSTEM_CONTROL",\r
- "IRP_MJ_DEVICE_CONTROL",\r
- "IRP_MJ_INTERNAL_DEVICE_CONTROL",\r
- "IRP_MJ_SHUTDOWN",\r
- "IRP_MJ_LOCK_CONTROL",\r
- "IRP_MJ_CLEANUP",\r
- "IRP_MJ_CREATE_MAILSLOT",\r
- "IRP_MJ_QUERY_SECURITY",\r
- "IRP_MJ_SET_SECURITY",\r
- "IRP_MJ_POWER", \r
- "IRP_MJ_SYSTEM_CONTROL", \r
- "IRP_MJ_DEVICE_CHANGE", \r
- "IRP_MJ_QUERY_QUOTA", \r
- "IRP_MJ_SET_QUOTA", \r
- "IRP_MJ_PNP" \r
-};\r
-/* IRP_MJ_MAXIMUM_FUNCTION defined in wdm.h */\r
-\r
-\r
-static const PCHAR szPnpMnFuncDesc[] =\r
-{ /* note this depends on corresponding values to the indexes in wdm.h */\r
-\r
- "IRP_MN_START_DEVICE",\r
- "IRP_MN_QUERY_REMOVE_DEVICE",\r
- "IRP_MN_REMOVE_DEVICE",\r
- "IRP_MN_CANCEL_REMOVE_DEVICE",\r
- "IRP_MN_STOP_DEVICE",\r
- "IRP_MN_QUERY_STOP_DEVICE",\r
- "IRP_MN_CANCEL_STOP_DEVICE",\r
- "IRP_MN_QUERY_DEVICE_RELATIONS",\r
- "IRP_MN_QUERY_INTERFACE",\r
- "IRP_MN_QUERY_CAPABILITIES",\r
- "IRP_MN_QUERY_RESOURCES",\r
- "IRP_MN_QUERY_RESOURCE_REQUIREMENTS",\r
- "IRP_MN_QUERY_DEVICE_TEXT",\r
- "IRP_MN_FILTER_RESOURCE_REQUIREMENTS",\r
- "IRP_MN_??? Unsupported code 0x0E",\r
- "IRP_MN_READ_CONFIG",\r
- "IRP_MN_WRITE_CONFIG",\r
- "IRP_MN_EJECT",\r
- "IRP_MN_SET_LOCK",\r
- "IRP_MN_QUERY_ID",\r
- "IRP_MN_QUERY_PNP_DEVICE_STATE",\r
- "IRP_MN_QUERY_BUS_INFORMATION",\r
- "IRP_MN_DEVICE_USAGE_NOTIFICATION",\r
- "IRP_MN_SURPRISE_REMOVAL",\r
- "IRP_MN_??? Unsupported code 0x18",\r
- "IRP_MN_??? Unsupported code 0x19"\r
-};\r
-\r
-\r
-#define IRP_PNP_MN_FUNCMAX IRP_MN_SURPRISE_REMOVAL\r
-\r
-\r
-\r
-static const PCHAR szSystemPowerState[] = \r
-{\r
- "PowerSystemUnspecified",\r
- "PowerSystemWorking",\r
- "PowerSystemSleeping1",\r
- "PowerSystemSleeping2",\r
- "PowerSystemSleeping3",\r
- "PowerSystemHibernate",\r
- "PowerSystemShutdown",\r
- "PowerSystemMaximum"\r
-};\r
-\r
-static const PCHAR szDevicePowerState[] = \r
-{\r
- "PowerDeviceUnspecified",\r
- "PowerDeviceD0",\r
- "PowerDeviceD1",\r
- "PowerDeviceD2",\r
- "PowerDeviceD3",\r
- "PowerDeviceMaximum"\r
-};\r
-\r
- \r
- \r
-\r
-#define MdKdPrintCond( ilev, cond, _x_) \\r
- if(( g_pDrvContext && ilev <= g_pDrvContext->m_nDebugPrintLevel ) && ( cond )) { \\r
- DPRINT( DBGSTR_PREFIX ); \\r
- DPRINT _x_ ; \\r
- }\r
-\r
-\r
-\r
-#define MdKdPrint( ilev, _x_) MdKdPrintCond( ilev, TRUE, _x_ )\r
-\r
-\r
-#define MdTrapCond( ilev, cond ) if (( ilev <= g_pDrvContext->m_nDebugPrintLevel ) && (cond) ) TRAP()\r
-#define MdTrap( ilev ) MdTrapCond( ilev, TRUE )\r
-\r
-\r
-#define MDASSERT( cond ) ASSERT( cond )\r
-\r
-#define MdStringForDevState( devState ) szDevicePowerState[ devState ] \r
-\r
-#define MdStringForSysState( sysState ) szSystemPowerState[ sysState ] \r
-\r
-#define MdStringForPnpMnFunc( mnfunc ) szPnpMnFuncDesc[ mnfunc ]\r
-\r
-#define MdStringForIrpMjFunc( mjfunc ) szIrpMajFuncDesc[ mjfunc ]\r
-\r
-PVOID \r
- MdExAllocatePool(\r
- IN POOL_TYPE PoolType,\r
- IN ULONG NumberOfBytes\r
- );\r
-\r
-\r
-VOID \r
- MdExFreePool(\r
- IN PVOID p\r
- );\r
-\r
-\r
-\r
-#else /* if not DBG */\r
-\r
-/* dummy definitions that go away in the retail build */\r
-\r
-#define MdKdPrintCond( ilev, cond, _x_) \r
-#define MdKdPrint( ilev, _x_) \r
-#define MdTrapCond( ilev, cond ) \r
-#define MdTrap( ilev )\r
-#define MDASSERT( cond )\r
-#define MdStringForDevState( devState )\r
-#define MdStringForSysState( sysState ) \r
-#define MdStringForPnpMnFunc( mnfunc )\r
-#define MdStringForIrpMjFunc( mjfunc ) \r
-\r
-#define MdExAllocatePool( typ, siz ) ExAllocatePoolWithTag( typ, siz, 'xEdM' )\r
-#define MdExFreePool( p ) ExFreePoolWithTag( p, 'xEdM' )\r
-\r
-\r
-#endif /* DBG */\r
-\r
-#endif /* included */\r
-\r
-\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef _MD_GEN_H_\r
-#define _MD_GEN_H_\r
-\r
-/* system files */\r
-#include <ntddk.h>\r
-#include <stdarg.h>\r
-#include <stdio.h>\r
-#include <string.h>\r
-\r
-/* driver files */\r
-#include "MdCard.h"\r
-#include "MdDbg.h"\r
-#include "MdUtil.h"\r
-#include "MdIoctl.h"\r
-#include "MdMsg.h"\r
-#include "MdConf.h"\r
-#include "MdCtl.h"\r
-#include "MdPci.h"\r
-\r
-/* DLL API header files */\r
-#include "mosal.h"\r
-#include "infinihost.h"\r
-\r
-/* macros */\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef GUID829H_INC\r
-#define GUID829H_INC\r
-\r
-//#include <initguid.h>\r
-\r
-\r
-/* {FF836FB3-142B-4f52-8404-40F59CCBC8BD} */\r
-DEFINE_GUID(GUID_CLASS_GAMLA_CARD, \r
-0xff836fb3, 0x142b, 0x4f52, 0x84, 0x4, 0x40, 0xf5, 0x9c, 0xcb, 0xc8, 0xbd);\r
-\r
-#endif /* end, #ifndef GUID829H_INC */\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include <MdGen.h>\r
-#undef BYTE_OFFSET\r
-//#include <MT21108.h>\r
-//#include "mtib.h"\r
-\r
-\r
-NTSTATUS\r
-MdProcessIoctl(\r
- IN PDEVICE_OBJECT pi_pDeviceObject,\r
- IN PIRP pi_pIrp\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Dispatch table handler for IRP_MJ_DEVICE_CONTROL; \r
- Handle DeviceIoControl() calls from User mode\r
-\r
-\r
-Arguments:\r
-\r
- DeviceObject - pointer to the FDO for this instance of the 82930 device.\r
-\r
-\r
-Return Value:\r
-\r
- NT status code\r
-\r
---*/\r
-{ /* MdProcessIoctl */\r
- \r
- NTSTATUS l_Status;\r
- PIO_STACK_LOCATION l_pIrpStack;\r
- PVOID l_pInBuffer;\r
- PVOID l_pOutBuffer;\r
- ULONG l_nInBufLength;\r
- ULONG l_nOutBufLength;\r
- PMD_DEV_CONTEXT_T l_pMdDevContext = (PMD_DEV_CONTEXT_T)pi_pDeviceObject->DeviceExtension;\r
- ULONG l_nIoControlCode;\r
- PCHAR l_pTmp;\r
- PFILE_OBJECT l_pFileObject;\r
- PMD_PCS_CONTEXT_T l_pPcs;\r
-\r
- /* register ioctl */\r
- MdKdPrint( DBGLVL_MAXIMUM,("(MdProcessIoctl) Enter\n"));\r
- MdIncrementIoCount(l_pMdDevContext);\r
-\r
- /* handle service call */ \r
- if ( l_pMdDevContext->m_eDevType == MD_DEV_IX_TAVOR_SD ) {\r
- KSEM_ACQ(&l_pMdDevContext->m_Sem);\r
- l_Status = PciIoctlFast( l_pMdDevContext, pi_pIrp );\r
- KSEM_REL(&l_pMdDevContext->m_Sem);\r
- goto Done;\r
- }\r
- if (l_pMdDevContext->m_eDevType == MD_DEV_IX_TAVOR_BD) {\r
- KSEM_ACQ(&l_pMdDevContext->m_Sem);\r
- l_Status = ConfIoctlFast( l_pMdDevContext, pi_pIrp );\r
- KSEM_REL(&l_pMdDevContext->m_Sem);\r
- goto Done;\r
- }\r
-\r
- /* handle functional call */ \r
-\r
- /* set default status */\r
- pi_pIrp->IoStatus.Status = STATUS_SUCCESS;\r
- pi_pIrp->IoStatus.Information = 0;\r
-\r
- // Can't accept a new io request if:\r
- // 1) device is removed, \r
- // 2) has never been started, \r
- // 3) is stopped,\r
- // 4) has a remove request pending,\r
- // 5) has a stop device pending\r
- if ( !MdCanAcceptIoRequests( pi_pDeviceObject ) ) \r
- { /* the request can't be accepted */\r
-\r
- l_Status = STATUS_DELETE_PENDING;\r
- goto Done;\r
-\r
- } /* the request can't be accepted */\r
-\r
- /* get pointer to IRP stack */\r
- l_pIrpStack = IoGetCurrentIrpStackLocation (pi_pIrp);\r
-\r
- /* get file handle, serving as Process Id */\r
- l_pFileObject = l_pIrpStack->FileObject;\r
- l_pPcs = (PMD_PCS_CONTEXT_T) l_pFileObject->FsContext;\r
- MdKdPrint( DBGLVL_HIGH,("(RunRequest) File Object 0x%x, Pid 0x%x\n", l_pFileObject, MOSAL_getpid() ));\r
-\r
- // get pointers and lengths of the caller's (user's) IO buffer\r
- l_nOutBufLength = l_pIrpStack->Parameters.DeviceIoControl.OutputBufferLength;\r
- l_pOutBuffer = l_nOutBufLength ? MmGetSystemAddressForMdlSafe(pi_pIrp->MdlAddress, HighPagePriority ) : NULL; \r
- l_nInBufLength = l_pIrpStack->Parameters.DeviceIoControl.InputBufferLength;\r
- l_pInBuffer = l_nInBufLength ? pi_pIrp->AssociatedIrp.SystemBuffer : NULL;\r
- l_nIoControlCode = l_pIrpStack->Parameters.DeviceIoControl.IoControlCode;\r
- l_pTmp = l_pInBuffer;\r
-\r
-\r
- //\r
- // Handle Ioctls from User mode\r
- //\r
-\r
- switch (l_pMdDevContext->m_eDevType) \r
- { /* handle Ioctls */\r
- case MD_DEV_IX_TAVOR_BD:\r
- l_Status = ConfIoctl( l_pMdDevContext, l_pPcs, l_nIoControlCode, l_pInBuffer, \r
- l_nInBufLength, l_pOutBuffer, l_nOutBufLength, (PULONG)&pi_pIrp->IoStatus.Information );\r
- break;\r
- \r
- case MD_DEV_IX_TAVOR_SD:\r
- case MD_DEV_IX_TAVOR:\r
- case MD_DEV_IX_ARBEL_TM:\r
- l_Status = PciIoctl( l_pMdDevContext, l_pPcs, l_nIoControlCode, l_pInBuffer, \r
- l_nInBufLength, l_pOutBuffer, l_nOutBufLength, (PULONG)&pi_pIrp->IoStatus.Information );\r
- break;\r
- \r
- //case MD_DEV_IX_CTRL:\r
- // l_Status = CtlIoctl( l_pMdDevContext, l_pPcs, l_nIoControlCode, l_pInBuffer, \r
- // l_nInBufLength, l_pOutBuffer, l_nOutBufLength, (PULONG)&pi_pIrp->IoStatus.Information );\r
- // break;\r
-\r
- default:\r
- MdKdPrint( DBGLVL_DEFAULT,("(RunRequest) Internal error - unknown device type %d\n", l_pMdDevContext->m_eDevType));\r
- l_Status = STATUS_NOT_IMPLEMENTED;\r
- break;\r
- \r
- } /* handle Ioctls */\r
- \r
- \r
-Done:\r
-\r
- /* store status */\r
- pi_pIrp->IoStatus.Status = l_Status;\r
-\r
- /* complete IRP */\r
- IoCompleteRequest( pi_pIrp, IO_NO_INCREMENT );\r
-\r
- /* de-register ioctl */\r
- MdDecrementIoCount(l_pMdDevContext); \r
- \r
- return l_Status;\r
-\r
-} /* MdProcessIoctl */\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-NTSTATUS\r
-MdResetDevice(\r
- IN PDEVICE_OBJECT DeviceObject\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- Checks port status; if OK, return success and do no more;\r
- If bad, attempt reset\r
-\r
-Arguments:\r
-\r
- DeviceObject - pointer to the device object for this instance of the 82930\r
- device.\r
-\r
-\r
-Return Value:\r
-\r
- NT status code\r
-\r
---*/\r
-{\r
- NTSTATUS ntStatus = STATUS_SUCCESS;\r
-\r
- MdKdPrint(DBGLVL_MAXIMUM,("(MdResetDevice) Enter \n"));\r
- return ntStatus;\r
-}\r
-\r
-\r
-\r
-\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "MdGen.h"\r
-#include "MdConfPriv.h"\r
-#include "MdIoctlSpec.h"\r
-\r
-void PciRelease(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext, \r
- IN PMD_PCS_CONTEXT_T pi_pPcsContext\r
- )\r
-{\r
- PMDL l_pMdl;\r
- \r
- /* release CR */\r
- l_pMdl = pi_pPcsContext->m_pCrMdl;\r
- pi_pPcsContext->m_pCrMdl = NULL;\r
-#ifdef DO_USER_UNMAP \r
- if (l_pMdl)\r
- MmUnlockPages(l_pMdl);\r
-#endif \r
- if (l_pMdl)\r
- IoFreeMdl( l_pMdl );\r
- \r
- /* release UAR */\r
- l_pMdl = pi_pPcsContext->m_pUarMdl;\r
- pi_pPcsContext->m_pUarMdl = NULL;\r
-#ifdef DO_USER_UNMAP \r
- if (l_pMdl)\r
- MmUnlockPages(l_pMdl);\r
-#endif \r
- if (l_pMdl)\r
- IoFreeMdl( l_pMdl );\r
- \r
- /* release CR */\r
- l_pMdl = pi_pPcsContext->m_pDdrMdl;\r
- pi_pPcsContext->m_pDdrMdl = NULL;\r
-#ifdef DO_USER_UNMAP \r
- if (l_pMdl)\r
- MmUnlockPages(l_pMdl);\r
-#endif \r
- if (l_pMdl)\r
- IoFreeMdl( l_pMdl );\r
- \r
-}\r
-\r
-NTSTATUS PciIoctl( \r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext, \r
- IN PMD_PCS_CONTEXT_T pi_pPcsContext,\r
- IN ULONG pi_nIoControlCode, \r
- IN PVOID pi_pInBuffer, \r
- IN ULONG pi_nInBufLength,\r
- IN PVOID pi_pOutBuffer, \r
- IN ULONG pi_nOutBufLength, \r
- OUT PULONG po_pnBytes \r
- )\r
-{\r
- NTSTATUS l_Status = STATUS_SUCCESS;\r
-\r
- /* prepare for error exit */\r
- *po_pnBytes = 0;\r
- \r
- switch (pi_nIoControlCode)\r
- { /* handle Ioctls */\r
- \r
- case UDLL_MAKE_IOCTL(WIN_PCI_GET_BAR_INFO):\r
- { /* call_result_t PciGetBarInfo( HANDLE h, ULONG num, PPCICONF_BAR_INFO_T bar_p ) */\r
- \r
- PULONG l_pBarNum = (PULONG)pi_pInBuffer;\r
- PPCICONF_BAR_INFO_T l_pInfo = (PPCICONF_BAR_INFO_T)pi_pOutBuffer;\r
- PMD_BAR_T l_pBar;\r
- PCHAR l_pUserAddr;\r
- PMDL l_pMdl, *l_ppSavedMdl;\r
-\r
- /* find bar descriptor */\r
- switch (*l_pBarNum) {\r
- case 0: l_pBar = &pi_pMdDevContext->m_Cr; l_ppSavedMdl = &pi_pPcsContext->m_pCrMdl; break;\r
- case 1: l_pBar = &pi_pMdDevContext->m_Uar; l_ppSavedMdl = &pi_pPcsContext->m_pUarMdl; break;\r
- case 2: l_pBar = &pi_pMdDevContext->m_Ddr; l_ppSavedMdl = &pi_pPcsContext->m_pDdrMdl; break;\r
- default: \r
- MdKdPrint( DBGLVL_LOW,("(PciIoctl) Illegal BAR number %d\n", *l_pBarNum));\r
- return STATUS_INVALID_PARAMETER;\r
- }\r
-\r
- /* prepare for mapping to user space */\r
- l_pMdl = IoAllocateMdl( l_pBar->m_pKernelAddr, l_pBar->m_ulKernelSize, FALSE,FALSE,NULL);\r
- if (l_pMdl == NULL) {\r
- MdKdPrint( DBGLVL_LOW,("(PciIoctl) IoAllocateMdl failed\n"));\r
- return STATUS_INSUFFICIENT_RESOURCES;\r
- }\r
- MmBuildMdlForNonPagedPool(l_pMdl); /* fill MDL */\r
- \r
- /* map the buffer into user space */\r
- l_pUserAddr = MmMapLockedPagesSpecifyCache( l_pMdl, UserMode, MmNonCached, \r
- NULL, FALSE, NormalPagePriority );\r
- if (l_pUserAddr == NULL) {\r
- MdKdPrint( DBGLVL_LOW,("(PciIoctl) MmMapLockedPagesSpecifyCache failed\n"));\r
- IoFreeMdl( l_pMdl );\r
- return STATUS_UNSUCCESSFUL;\r
- }\r
- *l_ppSavedMdl = l_pMdl;\r
- \r
- /* store the results */\r
- l_pInfo->ptr = (MT_ulong_ptr_t)l_pUserAddr;\r
- l_pInfo->size = l_pBar->m_ulKernelSize;\r
- l_pInfo->LowPhysAddr = l_pBar->m_MemPhysAddr.LowPart;\r
- l_pInfo->HighPhysAddr = l_pBar->m_MemPhysAddr.HighPart;\r
- l_pInfo->TotalMemSize = l_pBar->m_ulMemSize;\r
- l_pInfo->MappedSize = l_pBar->m_ulKernelSize;\r
- l_pInfo->MappedOffset = l_pBar->m_ulKernelOffset;\r
- *po_pnBytes = sizeof(PCICONF_BAR_INFO_T);\r
- l_Status = STATUS_SUCCESS;\r
- }\r
- break;\r
-\r
- case UDLL_MAKE_IOCTL(WIN_SOFT_RESET):\r
- #ifdef __i386__\r
- l_Status = PciReset( pi_pMdDevContext );\r
- #endif\r
- break;\r
-\r
- default:\r
- MdKdPrint( DBGLVL_DEFAULT,("(PciIoctl) Unsupported Ioctl 0x%x\n", pi_nIoControlCode));\r
- l_Status = STATUS_NOT_IMPLEMENTED;\r
- break;\r
-\r
- } /* handle Ioctls */\r
-\r
- return l_Status;\r
-}\r
-\r
-NTSTATUS\r
-PciDevReset(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext,\r
- IN ULONG pi_Offset,\r
- IN ULONG pi_Value\r
-)\r
-{\r
- PMD_BAR_T l_pBar = &pi_pMdDevContext->m_Cr;\r
- PULONG l_pResetReg;\r
- if (!l_pBar->m_pKernelAddr)\r
- return STATUS_UNSUCCESSFUL;\r
-\r
- l_pResetReg = (PULONG)(l_pBar->m_pKernelAddr + pi_Offset);\r
- WRITE_REGISTER_ULONG( l_pResetReg, pi_Value ); \r
- return STATUS_SUCCESS;\r
-}\r
-\r
-NTSTATUS\r
-PciIoctlFast(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext,\r
- IN PIRP pi_pIrp\r
- )\r
-{\r
- NTSTATUS l_Status = STATUS_SUCCESS;\r
- PIO_STACK_LOCATION l_pIrpStack;\r
-\r
- /* get pointer to IRP stack */\r
- l_pIrpStack = IoGetCurrentIrpStackLocation (pi_pIrp);\r
- \r
- switch (l_pIrpStack->Parameters.DeviceIoControl.IoControlCode)\r
- { /* handle Ioctls */\r
- \r
- case UDLL_MAKE_IOCTL_BUF(WIN_PCICONF_READ4):\r
- /* call_result_t PciConfRead4( HANDLE h, DWORD offset, DWORD * p_data ) */\r
- PCICONF_READ( pi_pMdDevContext, \r
- *(PULONG)pi_pIrp->AssociatedIrp.SystemBuffer, \r
- (PULONG)pi_pIrp->AssociatedIrp.SystemBuffer, \r
- l_Status );\r
- if (NT_SUCCESS(l_Status)) \r
- pi_pIrp->IoStatus.Information = sizeof(ULONG);\r
- else \r
- pi_pIrp->IoStatus.Information = 0;\r
- break;\r
- \r
- case UDLL_MAKE_IOCTL_BUF(WIN_PCICONF_WRITE4):\r
- /* call_result_t PciConfWrite4( HANDLE h, PPCICONF_WRITE4_T params ) */\r
- PCICONF_WRITE( pi_pMdDevContext, \r
- *((PULONG)pi_pIrp->AssociatedIrp.SystemBuffer + 0), \r
- *((PULONG)pi_pIrp->AssociatedIrp.SystemBuffer + 1), \r
- l_Status );\r
- pi_pIrp->IoStatus.Information = 0;\r
- break;\r
- \r
- case UDLL_MAKE_IOCTL(WIN_PCI_GET_BAR_INFO):\r
- { /* call_result_t PciGetBarInfo( HANDLE h, ULONG num, PPCICONF_BAR_INFO_T bar_p ) */\r
- \r
- PULONG l_pBarNum = (PULONG)pi_pIrp->AssociatedIrp.SystemBuffer;\r
- PPCICONF_BAR_INFO_T l_pInfo = (PPCICONF_BAR_INFO_T)MmGetSystemAddressForMdlSafe(pi_pIrp->MdlAddress, HighPagePriority );\r
- PMD_BAR_T l_pBar;\r
- PCHAR l_pUserAddr;\r
- PMDL l_pMdl, *l_ppSavedMdl;\r
- PFILE_OBJECT l_pFileObject;\r
- PMD_PCS_CONTEXT_T l_pPcs;\r
-\r
- pi_pIrp->IoStatus.Information = 0;\r
-\r
- /* get file handle, serving as Process Id */\r
- l_pFileObject = l_pIrpStack->FileObject;\r
- l_pPcs = (PMD_PCS_CONTEXT_T) l_pFileObject->FsContext;\r
- MdKdPrint( DBGLVL_HIGH,("(PciIoctlFast) File Object 0x%x, Pid 0x%x\n", l_pFileObject, MOSAL_getpid()));\r
-\r
- \r
- /* find bar descriptor */\r
- switch (*l_pBarNum) {\r
- case 0: l_pBar = &pi_pMdDevContext->m_Cr; l_ppSavedMdl = &l_pPcs->m_pCrMdl; break;\r
- case 1: l_pBar = &pi_pMdDevContext->m_Uar; l_ppSavedMdl = &l_pPcs->m_pUarMdl; break;\r
- case 2: l_pBar = &pi_pMdDevContext->m_Ddr; l_ppSavedMdl = &l_pPcs->m_pDdrMdl; break;\r
- default: \r
- MdKdPrint( DBGLVL_LOW,("(PciIoctl) Illegal BAR number %d\n", *l_pBarNum));\r
- l_Status = STATUS_INVALID_PARAMETER;\r
- break;\r
- }\r
-\r
- /* prepare for mapping to user space */\r
- l_pMdl = IoAllocateMdl( l_pBar->m_pKernelAddr, l_pBar->m_ulKernelSize, FALSE,FALSE,NULL);\r
- if (l_pMdl == NULL) {\r
- MdKdPrint( DBGLVL_LOW,("(PciIoctl) IoAllocateMdl failed\n"));\r
- l_Status = STATUS_INSUFFICIENT_RESOURCES;\r
- break;\r
- }\r
- MmBuildMdlForNonPagedPool(l_pMdl); /* fill MDL */\r
- \r
- /* map the buffer into user space */\r
- l_pUserAddr = MmMapLockedPagesSpecifyCache( l_pMdl, UserMode, MmNonCached, \r
- NULL, FALSE, NormalPagePriority );\r
- if (l_pUserAddr == NULL) {\r
- MdKdPrint( DBGLVL_LOW,("(PciIoctl) MmMapLockedPagesSpecifyCache failed\n"));\r
- IoFreeMdl( l_pMdl );\r
- l_Status = STATUS_UNSUCCESSFUL;\r
- break;\r
- }\r
- *l_ppSavedMdl = l_pMdl;\r
-\r
- /* store the results */\r
- l_pInfo->ptr = (MT_ulong_ptr_t)l_pUserAddr;\r
- l_pInfo->size = l_pBar->m_ulKernelSize;\r
- l_pInfo->LowPhysAddr = l_pBar->m_MemPhysAddr.LowPart;\r
- l_pInfo->HighPhysAddr = l_pBar->m_MemPhysAddr.HighPart;\r
- l_pInfo->TotalMemSize = l_pBar->m_ulMemSize;\r
- l_pInfo->MappedSize = l_pBar->m_ulKernelSize;\r
- l_pInfo->MappedOffset = l_pBar->m_ulKernelOffset;\r
- pi_pIrp->IoStatus.Information = sizeof(PCICONF_BAR_INFO_T);\r
- l_Status = STATUS_SUCCESS;\r
- break;\r
- }\r
-\r
- case UDLL_MAKE_IOCTL(WIN_SOFT_RESET):\r
- #ifdef __i386__\r
- l_Status = PciReset( pi_pMdDevContext );\r
- #endif\r
- break;\r
-\r
- \r
- default:\r
- MdKdPrint( DBGLVL_DEFAULT,("(PciIoctlFast) Unsupported Ioctl 0x%x\n", \r
- l_pIrpStack->Parameters.DeviceIoControl.IoControlCode));\r
- pi_pIrp->IoStatus.Information = 0;\r
- l_Status = STATUS_NOT_IMPLEMENTED;\r
- break;\r
-\r
- } /* handle Ioctls */\r
-\r
- return l_Status;\r
-}\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef _MD_PCI_H_\r
-#define _MD_PCI_H_\r
-\r
-NTSTATUS PciIoctl( \r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext, \r
- IN PMD_PCS_CONTEXT_T pi_pPcsContext,\r
- IN ULONG pi_nIoControlCode, \r
- IN PVOID pi_pInBuffer, \r
- IN ULONG pi_nInBufLength,\r
- IN PVOID pi_pOutBuffer, \r
- IN ULONG pi_nOutBufLength, \r
- OUT PULONG po_pnBytes \r
- );\r
-\r
-void PciRelease(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext, \r
- IN PMD_PCS_CONTEXT_T pi_pPcsContext\r
- );\r
-\r
-NTSTATUS\r
-PciDevReset(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext,\r
- IN ULONG pi_Offset,\r
- IN ULONG pi_Value\r
-);\r
-\r
-NTSTATUS\r
-PciIoctlFast(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext,\r
- IN PIRP pi_pIrp\r
- );\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#include "MdGen.h"\r
-#include <initguid.h>\r
-#include "MdCard.h"\r
-#include "mosal_util.h"\r
-\r
-static int IB_MGT_started = 0;\r
-extern NTSTATUS MdMosalHelper( \r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext,\r
- IN int cmd\r
-);\r
-\r
-int IsIbMgtOn() { return (IB_MGT_started>0) ? 1 : 0; }\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-NTSTATUS\r
-MdProcessPnPIrp(\r
- IN PDEVICE_OBJECT pi_pFdo,\r
- IN PIRP pi_pIrp\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Dispatch table routine for IRP_MJ_PNP.\r
- Process the Plug and Play IRPs sent to this device.\r
-\r
-Arguments:\r
-\r
- pi_pFdo - pointer to our FDO (Functional Device Object)\r
-\r
- pi_pIrp - pointer to an I/O Request Packet\r
-\r
-Return Value:\r
-\r
- NT status code\r
-\r
---*/\r
-{\r
-\r
- PIO_STACK_LOCATION l_pIrpStack;\r
- PMD_DEV_CONTEXT_T l_pMdDevContext;\r
- NTSTATUS l_Status = STATUS_SUCCESS;\r
- NTSTATUS l_WaitStatus;\r
- PDEVICE_OBJECT l_pLdo;\r
- KEVENT startDeviceEvent;\r
-\r
-\r
- //\r
- // Get a pointer to the current location in the Irp. This is where\r
- // the function codes and parameters are located.\r
- //\r
- l_pIrpStack = IoGetCurrentIrpStackLocation (pi_pIrp);\r
-\r
- //\r
- // Get a pointer to the device extension\r
- //\r
-\r
- l_pMdDevContext = (PMD_DEV_CONTEXT_T)pi_pFdo->DeviceExtension;\r
- l_pLdo = l_pMdDevContext->m_pLdo;\r
-\r
- MdKdPrint( DBGLVL_MEDIUM, ( "enter MdProcessPnPIrp() IRP_MJ_PNP, minor %s\n",\r
- MdStringForPnpMnFunc( l_pIrpStack->MinorFunction ) ));\r
-\r
- // inc the FDO device extension's pending IO count for this Irp\r
- MdIncrementIoCount(l_pMdDevContext);\r
-\r
- MDASSERT( IRP_MJ_PNP == l_pIrpStack->MajorFunction );\r
-\r
- switch (l_pIrpStack->MinorFunction) {\r
- case IRP_MN_START_DEVICE:\r
-\r
- // The PnP Manager sends this IRP after it has assigned resources,\r
- // if any, to the device. The device may have been recently enumerated\r
- // and is being started for the first time, or the device may be\r
- // restarting after being stopped for resource reconfiguration.\r
-\r
- // Initialize an event we can wait on for the PDO to be done with this irp\r
- KeInitializeEvent(&startDeviceEvent, NotificationEvent, FALSE);\r
- IoCopyCurrentIrpStackLocationToNext(pi_pIrp);\r
-\r
- // Set a completion routine so it can signal our event when\r
- // the PDO is done with the Irp\r
- IoSetCompletionRoutine(pi_pIrp,\r
- MdIrpCompletionRoutine,\r
- &startDeviceEvent, // pass the event to the completion routine as the Context\r
- TRUE, // invoke on success\r
- TRUE, // invoke on error\r
- TRUE); // invoke on cancellation\r
-\r
- // let the PDO process the IRP\r
- l_Status = IoCallDriver(l_pLdo,\r
- pi_pIrp);\r
-\r
- // if PDO is not done yet, wait for the event to be set in our completion routine\r
- if (l_Status == STATUS_PENDING) {\r
- // wait for irp to complete\r
-\r
- l_WaitStatus = KeWaitForSingleObject(\r
- &startDeviceEvent,\r
- Suspended,\r
- KernelMode,\r
- FALSE,\r
- NULL);\r
-\r
- l_Status = pi_pIrp->IoStatus.Status;\r
- }\r
-\r
- if (NT_SUCCESS(l_Status)) {\r
-\r
- // Now we're ready to do our own startup processing.\r
- // USB client drivers such as us set up URBs (USB Request Packets) to send requests\r
- // to the host controller driver (HCD). The URB structure defines a format for all\r
- // possible commands that can be sent to a USB device.\r
- // Here, we request the device descriptor and store it,\r
- // and configure the device.\r
- l_Status = MdStartDevice(pi_pFdo, pi_pIrp);\r
- pi_pIrp->IoStatus.Status = l_Status;\r
- }\r
-\r
- IoCompleteRequest (pi_pIrp,\r
- IO_NO_INCREMENT\r
- );\r
-\r
- MdDecrementIoCount(l_pMdDevContext);\r
- return l_Status; // end, case IRP_MN_START_DEVICE\r
-\r
- case IRP_MN_QUERY_STOP_DEVICE:\r
-\r
- // The IRP_MN_QUERY_STOP_DEVICE/IRP_MN_STOP_DEVICE sequence only occurs\r
- // during "polite" shutdowns, such as the user explicitily requesting the\r
- // service be stopped in, or requesting unplug from the Pnp tray icon.\r
- // This sequence is NOT received during "impolite" shutdowns,\r
- // such as someone suddenly yanking the USB cord or otherwise\r
- // unexpectedly disabling/resetting the device.\r
-\r
- // If a driver sets STATUS_SUCCESS for this IRP,\r
- // the driver must not start any operations on the device that\r
- // would prevent that driver from successfully completing an IRP_MN_STOP_DEVICE\r
- // for the device.\r
- // For mass storage devices such as disk drives, while the device is in the\r
- // stop-pending state,the driver holds IRPs that require access to the device,\r
- // but for most USB devices, there is no 'persistent storage', so we will just\r
- // refuse any more IO until restarted or the stop is cancelled\r
-\r
- // If a driver in the device stack determines that the device cannot be\r
- // stopped for resource reconfiguration, the driver is not required to pass\r
- // the IRP down the device stack. If a query-stop IRP fails,\r
- // the PnP Manager sends an IRP_MN_CANCEL_STOP_DEVICE to the device stack,\r
- // notifying the drivers for the device that the query has been cancelled\r
- // and that the device will not be stopped.\r
-\r
-\r
- // It is possible to receive this irp when the device has not been started\r
- // ( as on a boot device )\r
- if (!l_pMdDevContext->m_DeviceStarted) { // if get when never started, just pass on\r
- MdKdPrint( DBGLVL_MEDIUM,("MdProcessPnPIrp() IRP_MN_QUERY_STOP_DEVICE when device not started\n"));\r
- IoSkipCurrentIrpStackLocation (pi_pIrp);\r
- l_Status = IoCallDriver (l_pMdDevContext->m_pLdo, pi_pIrp);\r
- MdDecrementIoCount(l_pMdDevContext);\r
-\r
- return l_Status;\r
- }\r
-\r
-\r
- // fail the request if we have any IRPS in progress\r
- if( g_pDrvContext->m_pCtlDevContext->m_nPendingIoCnt > 1) {\r
- l_Status = STATUS_UNSUCCESSFUL;\r
- }\r
- else {\r
- // We'll not veto it; pass it on and flag that stop was requested.\r
- // Once m_StopDeviceRequested is set no new IOCTL or read/write irps will be passed\r
- // down the stack to lower drivers; all will be quickly failed\r
- l_pMdDevContext->m_StopDeviceRequested = TRUE;\r
- pi_pIrp->IoStatus.Status = STATUS_SUCCESS;\r
- }\r
-\r
- break; // end, case IRP_MN_QUERY_STOP_DEVICE\r
-\r
- case IRP_MN_CANCEL_STOP_DEVICE:\r
-\r
- // The PnP Manager uses this IRP to inform the drivers for a device\r
- // that the device will not be stopped for resource reconfiguration.\r
- // This should only be received after a successful IRP_MN_QUERY_STOP_DEVICE.\r
-\r
-\r
- // It is possible to receive this irp when the device has not been started\r
- if (!l_pMdDevContext->m_DeviceStarted) { // if get when never started, just pass on\r
- MdKdPrint( DBGLVL_MEDIUM,("MdProcessPnPIrp() IRP_MN_CANCEL_STOP_DEVICE when device not started\n"));\r
- IoSkipCurrentIrpStackLocation (pi_pIrp);\r
- l_Status = IoCallDriver (l_pMdDevContext->m_pLdo, pi_pIrp);\r
- MdDecrementIoCount(l_pMdDevContext);\r
- return l_Status;\r
- }\r
-\r
- // Reset this flag so new IOCTL and IO Irp processing will be re-enabled\r
- l_pMdDevContext->m_StopDeviceRequested = FALSE;\r
- pi_pIrp->IoStatus.Status = STATUS_SUCCESS;\r
- break; // end, case IRP_MN_CANCEL_STOP_DEVICE\r
-\r
- case IRP_MN_STOP_DEVICE:\r
-\r
- // The PnP Manager sends this IRP to stop a device so it can reconfigure\r
- // its hardware resources. The PnP Manager only sends this IRP if a prior\r
- // IRP_MN_QUERY_STOP_DEVICE completed successfully.\r
-\r
-\r
- // Cancel any pending io requests. (there shouldn't be any)\r
- MdCancelPendingIo( pi_pFdo );\r
- //\r
- // stop the device\r
- //\r
- l_Status = MdStopDevice(pi_pFdo);\r
- pi_pIrp->IoStatus.Status = l_Status;\r
-\r
- break; // end, case IRP_MN_STOP_DEVICE\r
-\r
-\r
-\r
- case IRP_MN_QUERY_REMOVE_DEVICE:\r
-\r
- // In response to this IRP, drivers indicate whether the device can be\r
- // removed without disrupting the system.\r
- // If a driver determines it is safe to remove the device,\r
- // the driver completes any outstanding I/O requests, arranges to hold any subsequent\r
- // read/write requests, and sets pi_pIrp->IoStatus.Status to STATUS_SUCCESS. Function\r
- // and filter drivers then pass the IRP to the next-lower driver in the device stack.\r
- // The underlying bus driver calls IoCompleteRequest.\r
-\r
- // If a driver sets STATUS_SUCCESS for this IRP, the driver must not start any\r
- // operations on the device that would prevent that driver from successfully completing\r
- // an IRP_MN_REMOVE_DEVICE for the device. If a driver in the device stack determines\r
- // that the device cannot be removed, the driver is not required to pass the\r
- // query-remove IRP down the device stack. If a query-remove IRP fails, the PnP Manager\r
- // sends an IRP_MN_CANCEL_REMOVE_DEVICE to the device stack, notifying the drivers for\r
- // the device that the query has been cancelled and that the device will not be removed.\r
-\r
- // It is possible to receive this irp when the device has not been started\r
- if (!l_pMdDevContext->m_DeviceStarted) { // if get when never started, just pass on\r
- MdKdPrint( DBGLVL_MEDIUM,("MdProcessPnPIrp() IRP_MN_QUERY_STOP_DEVICE when device not started\n"));\r
- IoSkipCurrentIrpStackLocation (pi_pIrp);\r
- l_Status = IoCallDriver (l_pMdDevContext->m_pLdo, pi_pIrp);\r
- MdDecrementIoCount(l_pMdDevContext);\r
-\r
- return l_Status;\r
- }\r
-\r
- // Once m_RemoveDeviceRequested is set no new IOCTL or read/write irps will be passed\r
- // down the stack to lower drivers; all will be quickly failed\r
- l_pMdDevContext->m_RemoveDeviceRequested = TRUE;\r
-\r
- // Wait for any io request pending in our driver to\r
- // complete before returning success.\r
- // This event is set when l_pMdDevContext->PendingIoCount goes to 1\r
-#if 0\r
- l_WaitStatus = KeWaitForSingleObject(\r
- &l_pMdDevContext->m_NoPendingIoEvent,\r
- Suspended,\r
- KernelMode,\r
- FALSE,\r
- NULL);\r
-\r
-#else\r
- { // wait for all applications IRPs to all cards and all PnP and Power IRPs to this card to be finished \r
- PVOID l_Objects[] = { &g_pDrvContext->m_pCtlDevContext->m_NoPendingIoEvent, &l_pMdDevContext->m_NoPendingIoEvent };\r
-\r
- // Leo: match the inc at the begining of the dispatch routine to get signal from MdDecrementIoCount()\r
- MdDecrementIoCount(l_pMdDevContext);\r
-\r
- // wait\r
- l_WaitStatus = KeWaitForMultipleObjects( 2, l_Objects, WaitAll, Executive, KernelMode, FALSE, NULL, NULL );\r
-\r
- // Leo: return the inc at the begining of the dispatch routine\r
- MdIncrementIoCount(l_pMdDevContext);\r
- }\r
-#endif\r
-\r
- pi_pIrp->IoStatus.Status = STATUS_SUCCESS;\r
- break; // end, case IRP_MN_QUERY_REMOVE_DEVICE\r
-\r
- case IRP_MN_CANCEL_REMOVE_DEVICE:\r
-\r
- // The PnP Manager uses this IRP to inform the drivers\r
- // for a device that the device will not be removed.\r
- // It is sent only after a successful IRP_MN_QUERY_REMOVE_DEVICE.\r
-\r
- if (!l_pMdDevContext->m_DeviceStarted) { // if get when never started, just pass on\r
- MdKdPrint( DBGLVL_MEDIUM,("MdProcessPnPIrp() IRP_MN_CANCEL_REMOVE_DEVICE when device not started\n"));\r
- IoSkipCurrentIrpStackLocation (pi_pIrp);\r
- l_Status = IoCallDriver (l_pMdDevContext->m_pLdo, pi_pIrp);\r
- MdDecrementIoCount(l_pMdDevContext);\r
- return l_Status;\r
- }\r
-\r
- // Reset this flag so new IOCTL and IO Irp processing will be re-enabled\r
- l_pMdDevContext->m_RemoveDeviceRequested = FALSE;\r
- pi_pIrp->IoStatus.Status = STATUS_SUCCESS;\r
-\r
- break; // end, case IRP_MN_CANCEL_REMOVE_DEVICE\r
-\r
- case IRP_MN_SURPRISE_REMOVAL:\r
- MdKdPrint( DBGLVL_MEDIUM,("MdProcessPnPIrp() IRP_MN_SURPRISE_REMOVAL\n"));\r
-\r
- // For a surprise-style device removal ( i.e. sudden cord yank ),\r
- // the physical device has already been removed so the PnP Manager sends\r
- // the remove IRP without a prior query-remove. A device can be in any state\r
- // when it receives a remove IRP as a result of a surprise-style removal.\r
-\r
- // match the inc at the begining of the dispatch routine\r
- MdDecrementIoCount(l_pMdDevContext);\r
-\r
- //\r
- // Once m_DeviceRemoved is set no new IOCTL or read/write irps will be passed\r
- // down the stack to lower drivers; all will be quickly failed\r
- //\r
- l_pMdDevContext->m_DeviceRemoved = TRUE;\r
-\r
- // Cancel any pending io requests; we may not have gotten a query first!\r
- MdCancelPendingIo( pi_pFdo );\r
-\r
- // Cancels all in progress requests.\r
- MdAbortInPgsReqs( pi_pFdo );\r
-\r
- //\r
- // Mark this handled\r
- //\r
- pi_pIrp->IoStatus.Status = STATUS_SUCCESS;\r
-\r
- // We don't explicitly wait for the below driver to complete, but just make\r
- // the call and go on, finishing cleanup\r
- IoCopyCurrentIrpStackLocationToNext(pi_pIrp);\r
-\r
- l_Status = IoCallDriver(l_pLdo,\r
- pi_pIrp);\r
-\r
- return l_Status;\r
-\r
- case IRP_MN_REMOVE_DEVICE:\r
-\r
-\r
- // The PnP Manager uses this IRP to direct drivers to remove a device.\r
- // For a "polite" device removal, the PnP Manager sends an\r
- // IRP_MN_QUERY_REMOVE_DEVICE prior to the remove IRP. In this case,\r
- // the device is in the remove-pending state when the remove IRP arrives.\r
- // For a surprise-style device removal ( i.e. sudden cord yank ),\r
- // the physical device has already been removed and the PnP Manager may not\r
- // have sent IRP_MN_SURPRISE_REMOVAL. A device can be in any state\r
- // when it receives a remove IRP as a result of a surprise-style removal.\r
-\r
- // match the inc at the begining of the dispatch routine\r
- MdDecrementIoCount(l_pMdDevContext);\r
-\r
- //\r
- // Once m_DeviceRemoved is set no new IOCTL or read/write irps will be passed\r
- // down the stack to lower drivers; all will be quickly failed\r
- //\r
- l_pMdDevContext->m_DeviceRemoved = TRUE;\r
-\r
- // Cancel any pending io requests; we may not have gotten a query first!\r
- MdCancelPendingIo( pi_pFdo );\r
-\r
- // Cancels all in progress requests.\r
- MdAbortInPgsReqs( pi_pFdo );\r
-\r
- //\r
- // Delete MDDK device\r
- //\r
- MdStopDevice(pi_pFdo);\r
-\r
- // We don't explicitly wait for the below driver to complete, but just make\r
- // the call and go on, finishing cleanup\r
- IoCopyCurrentIrpStackLocationToNext(pi_pIrp);\r
-\r
- l_Status = IoCallDriver(l_pLdo,\r
- pi_pIrp);\r
- //\r
- // The final decrement to device extension PendingIoCount == 0\r
- // will set l_pMdDevContext->m_RemoveEvent, enabling device removal.\r
- // If there is no pending IO at this point, the below decrement will be it.\r
- //\r
- MdDecrementIoCount(l_pMdDevContext);\r
-\r
- // wait for any io request pending in our driver to\r
- // complete for finishing the remove\r
-\r
-#if 0\r
- KeWaitForSingleObject(\r
- &l_pMdDevContext->m_RemoveEvent,\r
- Suspended,\r
- KernelMode,\r
- FALSE,\r
- NULL);\r
-\r
-#else\r
- { // wait for all applications IRPs to all cards and all PnP and Power IRPs to this card to be finished \r
- PVOID l_Objects[] = { &g_pDrvContext->m_pCtlDevContext->m_NoPendingIoEvent, &l_pMdDevContext->m_RemoveEvent };\r
-\r
- KeWaitForMultipleObjects( 2, l_Objects, WaitAll, Executive, KernelMode, FALSE, NULL, NULL );\r
- }\r
-#endif\r
-\r
- //\r
- // Detach the device\r
- //\r
- MdKdPrint( DBGLVL_DEFAULT,("MdProcessPnPIrp() Detaching from %08X\n",\r
- l_pMdDevContext->m_pLdo));\r
-\r
- IoDetachDevice(l_pMdDevContext->m_pLdo);\r
-\r
- //\r
- // Delete the link and FDO we created\r
- //\r
- MdRemoveDevice(pi_pFdo);\r
-\r
- //\r
- // if it was the last device - remove also the control device\r
- //\r
- if (g_pDrvContext->m_uDevNo == 1 )\r
- { /* it was the last IB device */\r
- \r
- PMD_DEV_CONTEXT_T l_pCtlDevContext = g_pDrvContext->m_pCtlDevContext;\r
-\r
- KMUTEX_ACQ(&l_pCtlDevContext->m_Mutex);\r
- if (l_pCtlDevContext->m_nOpenCount > 0)\r
- { /* there is open handles - postpone removing */\r
-\r
- // mark delete pending\r
- l_pCtlDevContext->m_fDeletePending = TRUE;\r
- KMUTEX_REL(&l_pCtlDevContext->m_Mutex);\r
-\r
- // wait for handles to be closed\r
- KeWaitForSingleObject(\r
- &l_pCtlDevContext->m_RemoveEvent,\r
- Suspended,\r
- KernelMode,\r
- FALSE,\r
- NULL);\r
-\r
- } /* there is open handles - postpone removing */\r
- else\r
- KMUTEX_REL(&l_pCtlDevContext->m_Mutex);\r
-\r
- // remove control device\r
- if (l_pCtlDevContext != NULL)\r
- MdDevDeInit( l_pCtlDevContext );\r
- g_pDrvContext->m_pCtlDevContext = NULL;\r
-\r
-\r
- } /* it was the last IB device */\r
-\r
- return l_Status; // end, case IRP_MN_REMOVE_DEVICE\r
-\r
- case IRP_MN_QUERY_INTERFACE:\r
- // Handle the query interface call to retrieve the HH handle for\r
- // our HCA instance.\r
- if( IsEqualGUID( l_pIrpStack->Parameters.QueryInterface.InterfaceType,\r
- &GUID_MD_INTERFACE ) )\r
- {\r
- if( l_pIrpStack->Parameters.QueryInterface.InterfaceSpecificData )\r
- {\r
- struct _hca_if {\r
- HH_hca_hndl_t hh_hndl;\r
- void * kernel_crspace_addr;\r
- ULONG kernel_crspace_size;\r
- } *if_p = l_pIrpStack->Parameters.QueryInterface.InterfaceSpecificData;\r
- \r
- // Our interface. Return the HH HCA handle and other data \r
- if_p->hh_hndl = l_pMdDevContext->m_hHhHca;\r
- if_p->kernel_crspace_addr = l_pMdDevContext->m_Cr.m_pKernelAddr;\r
- if_p->kernel_crspace_size = l_pMdDevContext->m_Cr.m_ulKernelSize;\r
- \r
- pi_pIrp->IoStatus.Status = STATUS_SUCCESS;\r
- l_Status = STATUS_SUCCESS;\r
- break;\r
- }\r
- }\r
- // Fall through.\r
- \r
- default:\r
-\r
- //\r
- // In this case we must not touch the status. As l_Status is\r
- // STATUS_SUCCESS, we will skip the failure case and pass down the IRP\r
- // untouched.\r
- //\r
- MdKdPrint( DBGLVL_MEDIUM,("MdProcessPnPIrp() Minor PnP IOCTL 0x%x not handled\n", l_pIrpStack->MinorFunction));\r
- } /* case MinorFunction */\r
-\r
-\r
- if (!NT_SUCCESS(l_Status)) {\r
-\r
- // if anything went wrong, return failure without passing Irp down\r
- pi_pIrp->IoStatus.Status = l_Status;\r
- IoCompleteRequest (pi_pIrp,\r
- IO_NO_INCREMENT\r
- );\r
-\r
- MdDecrementIoCount(l_pMdDevContext);\r
-\r
- MdKdPrint( DBGLVL_MINIMUM,("MdProcessPnPIrp() Exit MdProcessPnPIrp FAILURE %x\n", l_Status));\r
- return l_Status;\r
- }\r
-\r
- IoCopyCurrentIrpStackLocationToNext(pi_pIrp);\r
-\r
- //\r
- // All PNP_POWER messages get passed to the m_pLdo\r
- // we were given in PnPAddDevice\r
- //\r
-\r
- MdKdPrint( DBGLVL_MAXIMUM,("MdProcessPnPIrp() Passing PnP Irp down, status = %x\n", l_Status));\r
-\r
- l_Status = IoCallDriver(l_pLdo,\r
- pi_pIrp);\r
-\r
- MdDecrementIoCount(l_pMdDevContext);\r
-\r
- MdKdPrint( DBGLVL_MAXIMUM,("MdProcessPnPIrp() Exit MdProcessPnPIrp %x\n", l_Status));\r
-\r
- return l_Status;\r
-}\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-NTSTATUS\r
-MdPnPAddDevice(\r
- IN PDRIVER_OBJECT pi_pDrvObject,\r
- IN PDEVICE_OBJECT pi_pPdo\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This routine is called to create and initialize our Functional Device Object (FDO).\r
-\r
-Arguments:\r
-\r
- pi_pDrvObject - pointer to the driver object for this instance of BulkUsb\r
- pi_pPdo - pointer to a device object created by the bus\r
-\r
-Return Value:\r
-\r
- STATUS_SUCCESS if successful,\r
- STATUS_UNSUCCESSFUL otherwise\r
-\r
---*/\r
-{\r
- /* status */\r
- NTSTATUS l_Status = STATUS_SUCCESS;\r
- /* device object we create for the added device */\r
- PDEVICE_OBJECT l_pFdo = NULL;\r
- /* our context to this device */\r
- PMD_DEV_CONTEXT_T l_pMdDevContext;\r
- /* index */\r
- ULONG l_nIx;\r
- /* The device Win32 name as unicode string */\r
- UNICODE_STRING l_usNtDeviceName = { 0 , 0 , NULL };\r
- /* The Dos device name as unicde string */\r
- UNICODE_STRING l_usDosDeviceName = { 0 , 0 , NULL };\r
- // size of the returned DevId string\r
- ULONG l_DevIdWstrSize;\r
- // size of the returned DevId string\r
- ULONG l_DevIdWstrSizeReqd;\r
- /* buffer for DevId string */\r
- WCHAR l_DevIdWstr[5];\r
- /* pointer to buffer for all Hardware ID strings */\r
- WCHAR * l_pDevIdWstr;\r
- /* Device BD id */\r
- int l_DevIx;\r
- /* Logging */\r
- char * l_pReason = "Unknown";\r
- char l_Buf[120];\r
- \r
- /* debug print */\r
- MdKdPrint( DBGLVL_DEFAULT,("(MdPnPAddDevice) enter \n"));\r
-\r
- do\r
- { /* find out the type of the device */\r
-\r
-\r
- //\r
- // get the Device ID \r
- //\r
- l_DevIdWstrSize = 512;\r
- while (1)\r
- { /* get device ID */ \r
- \r
- /* allocate buffer */\r
- l_pDevIdWstr = (WCHAR *)MdExAllocatePool( PagedPool , l_DevIdWstrSize);\r
- if (l_pDevIdWstr == NULL)\r
- { /* error */\r
- MdKdPrint( DBGLVL_LOW,("(MdPnPAddDevice) MdExAllocatePool failed req-d size %d \n", \r
- l_DevIdWstrSize ));\r
- sprintf( l_Buf, "MdExAllocatePool failed req-d size %d \n", l_DevIdWstrSize);\r
- l_pReason = l_Buf;\r
- l_Status = STATUS_INSUFFICIENT_RESOURCES;\r
- goto err;\r
- } /* error */\r
- \r
- /* Get the device Hardware ID */\r
- l_Status = IoGetDeviceProperty(pi_pPdo, DevicePropertyHardwareID , \r
- l_DevIdWstrSize, (void*)l_pDevIdWstr, &l_DevIdWstrSizeReqd);\r
-\r
- if (NT_SUCCESS(l_Status)) \r
- { /* suceeded - get Device ID */\r
-\r
- /* print the first string */\r
- MdKdPrint( DBGLVL_LOW,("(MdPnPAddDevice) first Device HW ID %ws, total size %d \n",\r
- l_pDevIdWstr, l_DevIdWstrSizeReqd));\r
- \r
- /* extract DevId */\r
- memcpy( l_DevIdWstr, l_pDevIdWstr + 17, 8 );\r
- l_DevIdWstr[4] = 0;\r
-\r
- /* free all the buffer */\r
- MdExFreePool(l_pDevIdWstr);\r
- break;\r
- \r
- } /* suceeded - get Device ID */\r
- else\r
- if (l_Status == STATUS_BUFFER_TOO_SMALL)\r
- { /* prepare for reallocate */\r
-\r
- MdExFreePool(l_pDevIdWstr);\r
- l_DevIdWstrSize = l_DevIdWstrSizeReqd;\r
- continue;\r
- \r
- } /* prepare for reallocate */\r
- else\r
- { /* error */\r
- \r
- MdKdPrint( DBGLVL_LOW,("(MdPnPAddDevice) getting of DevicePropertyHardwareID failed (0x%x): ID %ws, size %d, req-d size %d \n", \r
- l_Status, sizeof(l_DevIdWstr), l_DevIdWstrSize ));\r
- sprintf( l_Buf, "Getting of DevicePropertyHardwareID failed (0x%x): ID %ws, size %d, req-d size %d \n", \r
- l_Status, l_pDevIdWstr, sizeof(l_DevIdWstr), l_DevIdWstrSize);\r
- l_pReason = l_Buf;\r
- goto err;\r
- \r
- } /* error */\r
- \r
- } /* get device ID */ \r
-\r
- /* find TAVOR device */\r
- for (l_DevIx=0; l_DevIx<(int)MD_DEV_IX_LAST; l_DevIx++) {\r
- \r
- if (NULL != wcsstr( l_DevIdWstr, g_DevParams[l_DevIx].m_DevIdWstr ))\r
- { \r
- MdKdPrint( DBGLVL_LOW,("(MdPnPAddDevice) Found device with ID %ws ! \n", \r
- g_DevParams[l_DevIx].m_DevIdWstr));\r
- break;\r
- }\r
- } \r
-\r
- /* get at the device */\r
- if (l_DevIx >= MD_DEV_IX_LAST) {\r
- MdKdPrint( DBGLVL_LOW,("(MdPnPAddDevice) Failed to identify device with ID %ws ! \n", l_DevIdWstr));\r
- sprintf( l_Buf, "Failed to identify device with ID %ws ! \n", l_DevIdWstr);\r
- l_pReason = l_Buf;\r
- l_Status = STATUS_NOT_SUPPORTED;\r
- goto err;\r
- }\r
- \r
- } /* find out the type of the device */\r
- while (0);\r
-\r
- l_Status = CreateOneDevice( l_DevIx, &l_usNtDeviceName, &l_usDosDeviceName, &l_pMdDevContext); \r
- if (!NT_SUCCESS(l_Status)) {\r
- sprintf( l_Buf, "Failed to create device '%s' ! \n", g_DevParams[l_DevIx].m_Format);\r
- l_pReason = l_Buf;\r
- goto err;\r
- }\r
-\r
- // store card number\r
- l_pMdDevContext->m_uCardNo = g_pDrvContext->m_uCardNo;\r
- \r
- //\r
- // remember the Physical device Object\r
- //\r
- l_pMdDevContext->m_pPdo = pi_pPdo;\r
-\r
- //\r
- // Attach to the PDO\r
- //\r
- l_pFdo = l_pMdDevContext->m_pFdo;\r
- l_pMdDevContext->m_pLdo = IoAttachDeviceToDeviceStack(l_pFdo, pi_pPdo);\r
-\r
- /* open direct PCI interface */\r
- PciIfOpen( l_pMdDevContext->m_pFdo, l_pMdDevContext->m_pLdo, &l_pMdDevContext->m_Interface );\r
-\r
- /* fix command register of HCA */\r
- PciFixCmdReg( l_pMdDevContext );\r
- \r
- /* set PCI master bit: no need for aux drivers */\r
- //SetPciMasterBit( l_pMdDevContext );\r
- \r
- // Get a copy of the physical device's capabilities into a\r
- // DEVICE_CAPABILITIES struct in our device extension;\r
- // We are most interested in learning which system power states\r
- // are to be mapped to which device power states for handling\r
- // IRP_MJ_SET_POWER Irps.\r
- MdQueryCapabilities(l_pMdDevContext->m_pLdo, &l_pMdDevContext->m_DeviceCapabilities);\r
-\r
-\r
- // We want to determine what level to auto-powerdown to; This is the lowest\r
- // sleeping level that is LESS than D3;\r
- // If all are set to D3, auto powerdown/powerup will be disabled.\r
-\r
- l_pMdDevContext->m_PowerDownLevel = PowerDeviceUnspecified; // init to disabled\r
-\r
- for (l_nIx=PowerSystemSleeping1; l_nIx<= PowerSystemSleeping3; l_nIx++) \r
- {\r
- if ( l_pMdDevContext->m_DeviceCapabilities.DeviceState[l_nIx] < PowerDeviceD3 )\r
- l_pMdDevContext->m_PowerDownLevel = l_pMdDevContext->m_DeviceCapabilities.DeviceState[l_nIx];\r
- }\r
-\r
-#if DBG\r
- {\r
- PDEVICE_CAPABILITIES l_pCap = &l_pMdDevContext->m_DeviceCapabilities;\r
- //\r
- // display the device caps\r
- //\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,(" >>>>>> ---------- DeviceCaps -----------\n"));\r
- MdKdPrint( DBGLVL_MEDIUM,(" Version %d, Address 0x%x, UINum 0x%x, D1Lat %d, D2Lat %d, D3Lat %d\n",\r
- l_pCap->Version, l_pCap->Address, l_pCap->UINumber, l_pCap->D1Latency, l_pCap->D2Latency, l_pCap->D3Latency ));\r
- MdKdPrint( DBGLVL_MEDIUM,(" DevD1 %d, DevD2 %d, Lock %d, Eject %d, Removable %d, Dock %d\n",\r
- l_pCap->DeviceD1, l_pCap->DeviceD2, l_pCap->LockSupported, \r
- l_pCap->EjectSupported, l_pCap->Removable, l_pCap->DockDevice ));\r
- MdKdPrint( DBGLVL_MEDIUM,(" UniqueId %d, Silent %d, RawDevOK %d, SurpriseRmvOK %d, HwDis %d, NonDyn %d\n",\r
- l_pCap->UniqueID, l_pCap->SilentInstall, l_pCap->RawDeviceOK, \r
- l_pCap->SurpriseRemovalOK, l_pCap->HardwareDisabled, l_pCap->NonDynamic ));\r
- MdKdPrint( DBGLVL_MEDIUM,(" WakeD0 %d, WakeD1 %d, WakeD2 %d, WakeD3 %d WarmEject %d\n",\r
- l_pCap->WakeFromD0, l_pCap->WakeFromD1, l_pCap->WakeFromD2, \r
- l_pCap->WakeFromD3, l_pCap->WarmEjectSupported ));\r
- MdKdPrint( DBGLVL_MEDIUM,(" SystemWake = %s\n", MdStringForSysState( l_pCap->SystemWake ) ));\r
- MdKdPrint( DBGLVL_MEDIUM,(" DeviceWake = %s\n", MdStringForDevState( l_pCap->DeviceWake) ));\r
-\r
- for (l_nIx=PowerSystemUnspecified; l_nIx< PowerSystemMaximum; l_nIx++) \r
- {\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,(" Device State Map: sysstate %s = devstate %s\n",\r
- MdStringForSysState( l_nIx ),\r
- MdStringForDevState( l_pCap->DeviceState[l_nIx] ) ));\r
-\r
- }\r
- MdKdPrint( DBGLVL_MEDIUM,(" <<<<<<<< ---------- DeviceCaps -----------\n"));\r
-\r
- }\r
-\r
-#endif\r
- // We keep a pending IO count ( extension->PendingIoCount ) in the device extension.\r
- // The first increment of this count is done on adding the device.\r
- // Subsequently, the count is incremented for each new IRP received and\r
- // decremented when each IRP is completed or passed on.\r
-\r
- // Transition to 'one' therefore indicates no IO is pending and signals\r
- // l_pMdDevContext->NoPendingIoEvent. This is needed for processing\r
- // IRP_MN_QUERY_REMOVE_DEVICE\r
-\r
- // Transition to 'zero' signals an event ( l_pMdDevContext->m_RemoveEvent )\r
- // to enable device removal. This is used in processing for IRP_MN_REMOVE_DEVICE\r
- //\r
- MdIncrementIoCount(l_pMdDevContext);\r
-\r
- if( NT_SUCCESS( l_Status ) )\r
- {\r
- NTSTATUS l_ActStat;\r
-\r
- // try to power down device until IO actually requested\r
- l_ActStat = MdSelfSuspendOrActivate( l_pFdo, TRUE );\r
- }\r
-\r
- // init DPC object\r
- //IoInitializeDpcRequest(l_pFdo, MdDpcForIsr); \r
-\r
- // unmark delete pending\r
- if ( g_pDrvContext->m_pCtlDevContext ) \r
- {\r
- KMUTEX_ACQ(&g_pDrvContext->m_pCtlDevContext->m_Mutex);\r
- g_pDrvContext->m_pCtlDevContext->m_fDeletePending = FALSE;\r
- KMUTEX_REL(&g_pDrvContext->m_pCtlDevContext->m_Mutex);\r
- } \r
-\r
- // mark the end of device init\r
- l_pFdo->Flags &= ~DO_DEVICE_INITIALIZING;\r
-\r
- MdKdPrint( DBGLVL_DEFAULT,("(MdPnPAddDevice) exit: (%x)\n", l_Status));\r
- return l_Status;\r
-\r
-err:\r
-#pragma warning( push )\r
-#pragma warning( disable:4296 )\r
- MdKdPrint( DBGLVL_ALWAYS ,("(MdDeviceInit) Device failed to initialize \n"));\r
-#pragma warning( pop )\r
-\r
- /* Write to event log */\r
- WriteEventLogEntry( g_pDrvContext->m_pDrvObject, MD_EVENT_LOG_LOAD_ERROR,\r
- 0, l_Status, 1, l_Status );\r
- return STATUS_UNSUCCESSFUL;\r
-}\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-NTSTATUS\r
-MdStartDevice(\r
- IN PDEVICE_OBJECT pi_pFdo,\r
- IN PIRP pi_pIrp\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Called from MdProcessPnPIrp(), the dispatch routine for IRP_MJ_PNP.\r
- Performs:\r
- - re-read cards PCI configuration data and stores on the device context;\r
- - add device to MDDK\r
-\r
-Arguments:\r
-\r
- pi_pFdo - pointer to FDO\r
- pi_pIrp - pointer to IRP\r
-\r
-Return Value:\r
-\r
- NT status code\r
-\r
---*/\r
-{\r
- PMD_DEV_CONTEXT_T l_pMdDevContext = (PMD_DEV_CONTEXT_T)pi_pFdo->DeviceExtension;\r
- NTSTATUS l_Status;\r
- PIO_STACK_LOCATION l_pIrpStack = IoGetCurrentIrpStackLocation (pi_pIrp);\r
- int l_nDevIx;\r
- call_result_t l_MddkStatus;\r
- MOSAL_dev_t l_MosalDevParams;\r
- /* Logging */\r
- char * l_pReason = "Unknown";\r
- char l_Buf[120];\r
- ULONG l_EventCode = MD_EVENT_LOG_LOAD_ERROR;\r
- card_hw_props_t l_HwProps;\r
-\r
- MdKdPrint( DBGLVL_DEFAULT,("(MdStartDevice) enter \n"));\r
-\r
- // init PCI card resources\r
- l_Status = MdInitPciCfgCard( l_pMdDevContext, \r
- l_pIrpStack->Parameters.StartDevice.AllocatedResources,\r
- l_pIrpStack->Parameters.StartDevice.AllocatedResourcesTranslated );\r
-\r
- // check the results\r
- if (!NT_SUCCESS(l_Status)) {\r
- l_pReason = "Read Pci Card Configuration failed";\r
- goto err;\r
- }\r
-\r
-#ifdef __i386__\r
- /* save PCI header */\r
- PciHdrSave( l_pMdDevContext );\r
-\r
- /* Reset the card */ \r
- if (l_pMdDevContext->m_PerformReset == 1 && l_pMdDevContext->m_fMayReset) \r
- PciReset( l_pMdDevContext );\r
-#endif \r
-\r
- /*\r
- * add device to MOSAL\r
- */ \r
-\r
- /* fill specific params */\r
- memset( &l_MosalDevParams, 0, sizeof(MOSAL_dev_t) );\r
- l_MosalDevParams.irq_num = (MOSAL_IRQ_ID_t)l_pMdDevContext->m_ulIntVector;\r
- l_MosalDevParams.irql = l_pMdDevContext->m_ulIntLevel;\r
- l_MosalDevParams.affinity = l_pMdDevContext->m_Affinity;\r
- l_MosalDevParams.int_shared = l_pMdDevContext->m_fIntShared;\r
- l_MosalDevParams.int_mode = l_pMdDevContext->m_IntMode;\r
- l_MosalDevParams.fdo_p = l_pMdDevContext->m_pFdo;\r
- l_MosalDevParams.ldo_p = l_pMdDevContext->m_pLdo;\r
- l_MosalDevParams.bus = (u_int8_t)l_pMdDevContext->m_BusNumber;\r
- l_MosalDevParams.dev_func = (u_int8_t)((l_pMdDevContext->m_DevNumber << 3) | l_pMdDevContext->m_Function);\r
- strcpy( l_MosalDevParams.name, l_pMdDevContext->m_AsciiDevName );\r
- memcpy( (PVOID)&l_MosalDevParams.m_Cr, (PVOID)&l_pMdDevContext->m_Cr, sizeof(MD_BAR_T));\r
- memcpy( (PVOID)&l_MosalDevParams.m_Uar, (PVOID)&l_pMdDevContext->m_Uar, sizeof(MD_BAR_T));\r
- memcpy( (PVOID)&l_MosalDevParams.m_Ddr, (PVOID)&l_pMdDevContext->m_Ddr, sizeof(MD_BAR_T));\r
- l_MosalDevParams.drv_helper = (void*)MdMosalHelper;\r
- l_MosalDevParams.drv_helper_ctx = (void*)l_pMdDevContext;\r
-\r
- /* add specific parameters to MOSAL */\r
- l_MddkStatus = MOSAL_add_device( &l_pMdDevContext->m_hMosal, &l_MosalDevParams );\r
-\r
- /* find the device parameters table by PCI configuration Device ID */\r
- l_pMdDevContext->m_pMdhalParams = NULL;\r
- for (l_nDevIx=0; l_nDevIx < MD_DEV_IX_LAST; l_nDevIx++)\r
- { /* find the type */\r
-\r
- if (g_DevParams[l_nDevIx].m_DevIx == l_pMdDevContext->m_eDevType)\r
- { /* found the device type */\r
- l_pMdDevContext->m_pMdhalParams = &g_DevParams[l_nDevIx];\r
- break;\r
- } /* found the device type */\r
-\r
- } /* find the type */\r
-\r
- if ( l_pMdDevContext->m_pMdhalParams == NULL ) {\r
- l_Status = STATUS_NOT_SUPPORTED;\r
- goto err;\r
- }\r
- \r
- /*\r
- * add device to TAVOR\r
- */ \r
-\r
- if ((l_pMdDevContext->m_eDevType == MD_DEV_IX_TAVOR || \r
- l_pMdDevContext->m_eDevType == MD_DEV_IX_ARBEL_TM)\r
- && g_pDrvContext->m_fSupportTavor)\r
- { /* add HCA to Tavor functional DLLs */\r
- \r
- unsigned char l_RevId = 0;\r
- char l_IntPin = 1;\r
- HH_ret_t l_HhRet;\r
- VAPI_ret_t l_VapiRet;\r
- VAPI_hca_hndl_t l_hVapiHca;\r
- HH_hca_hndl_t l_hHhHca;\r
- \r
- /* get hw revision id */\r
- DrvReadWritePciConfig( l_pMdDevContext, \r
- &l_RevId, FIELD_OFFSET( PCI_COMMON_CONFIG, RevisionID ), \r
- sizeof(l_RevId), IRP_MN_READ_CONFIG );\r
-\r
- /* get interrupt pin (Who, the hell, needs it ?) */\r
- DrvReadWritePciConfig( l_pMdDevContext, \r
- &l_IntPin, \r
- FIELD_OFFSET( PCI_COMMON_CONFIG, u ) + \r
- FIELD_OFFSET( struct _PCI_HEADER_TYPE_0, InterruptPin ), \r
- sizeof(l_IntPin), IRP_MN_READ_CONFIG );\r
-\r
- /* add HCA */\r
- l_pMdDevContext->m_hHca = VAPI_INVAL_HNDL;\r
- l_pMdDevContext->m_hHhHca = (HH_hca_hndl_t)NULL;\r
- l_HwProps.bus = (u_int8_t)l_pMdDevContext->m_BusNumber;\r
- l_HwProps.dev_func = (u_int8_t)((l_pMdDevContext->m_DevNumber << 3) | l_pMdDevContext->m_Function);\r
- l_HwProps.device_id = g_DevParams[l_pMdDevContext->m_eDevType].m_DevId;\r
- l_HwProps.pci_vendor_id = MLX_VENDOR_ID;\r
- l_HwProps.hw_ver = l_RevId;\r
- l_HwProps.cr_base = (MT_phys_addr_t)l_pMdDevContext->m_Cr.m_MemPhysAddr.QuadPart & 0xFFF00000;\r
- l_HwProps.uar_base = (MT_phys_addr_t)l_pMdDevContext->m_Uar.m_MemPhysAddr.QuadPart & 0xFFF00000;\r
- l_HwProps.ddr_base = (MT_phys_addr_t)l_pMdDevContext->m_Ddr.m_MemPhysAddr.QuadPart & 0xFFF00000;\r
- l_HwProps.interrupt_props.irq = (MOSAL_IRQ_ID_t)l_pMdDevContext->m_ulIntVector;\r
- l_HwProps.interrupt_props.intr_pin = l_IntPin;\r
-\r
- l_HhRet = THH_add_hca( l_pMdDevContext->m_uCardNo-1, &l_HwProps, &l_hHhHca );\r
- if (l_HhRet != MT_OK) {\r
- l_Status = l_HhRet;\r
- l_pReason = "THH_add_hca failed. Check FW";\r
- l_EventCode = MD_EVENT_LOG_LOAD_ERROR_FW;\r
- goto err;\r
- }\r
-\r
- /* open HCA */\r
- // l_VapiRet = VAPI_open_hca(l_pMdDevContext->m_AsciiDevName, &l_hVapiHca); \r
- // if (l_VapiRet == VAPI_EBUSY) {\r
- // MdKdPrint( DBGLVL_LOW,("HCA [%s] is already open.\n",l_pMdDevContext->m_AsciiDevName));\r
- // l_Status = l_VapiRet;\r
- // sprintf( l_Buf, "HCA [%s] is already open.\n",l_pMdDevContext->m_AsciiDevName);\r
- // l_pReason = l_Buf;\r
- // goto err;\r
- // } \r
- // else \r
- // if (l_VapiRet != VAPI_OK) {\r
- // MdKdPrint( DBGLVL_LOW,("Failed opening HCA [%s] - %s\n",\r
- // l_pMdDevContext->m_AsciiDevName, VAPI_strerror_sym(l_VapiRet) ));\r
- // l_Status = l_VapiRet;\r
- // sprintf( l_Buf, "Failed opening HCA [%s] - %s\n",\r
- // l_pMdDevContext->m_AsciiDevName, VAPI_strerror_sym(l_VapiRet) );\r
- // l_pReason = l_Buf;\r
- // } else {\r
- // MdKdPrint( DBGLVL_LOW,("HCA [%s] is open \n", l_pMdDevContext->m_AsciiDevName));\r
- // } \r
- //\r
- ///* save HCA handles */\r
- //l_pMdDevContext->m_hHca = l_hVapiHca;\r
- l_pMdDevContext->m_hHhHca = l_hHhHca;\r
- \r
-\r
- /* init IB_MGT */\r
- //if (g_pDrvContext->m_fSupportIbMgt) {\r
- // if (IB_MGT_started) {\r
- // l_MddkStatus = IB_MGT_reattach_hca( l_pMdDevContext->m_AsciiDevName );\r
- // if (l_MddkStatus != MT_OK) \r
- // { \r
- // MdKdPrint( DBGLVL_LOW,("IB_MGT_reattach_hca failed (%d)\n",l_MddkStatus));\r
- // sprintf( l_Buf, "IB_MT init failed (%d)\n",l_MddkStatus );\r
- // l_pReason = l_Buf;\r
- // }\r
- // else {\r
- // MdKdPrint( DBGLVL_LOW,("'%s' attached to IB_MGT\n",l_pMdDevContext->m_AsciiDevName));\r
- // IB_MGT_started++;\r
- // }\r
- // }\r
- // else {\r
- // l_MddkStatus = IB_MGT_init_module(g_pDrvContext->m_IbMgtQp0Only);\r
- // if (l_MddkStatus != MT_OK) \r
- // { \r
- // MdKdPrint( DBGLVL_LOW,("IB_MGT_init_module failed (%d)\n",l_MddkStatus));\r
- // sprintf( l_Buf, "IB_MGT_init_module failed (%d)\n",l_MddkStatus );\r
- // l_pReason = l_Buf;\r
- // }\r
- // else {\r
- // IB_MGT_started++;\r
- // MdKdPrint( DBGLVL_LOW,("IB_MGT started over '%s'\n",l_pMdDevContext->m_AsciiDevName));\r
- // }\r
- // }\r
- //}\r
- \r
- } /* add HCA to Tavor functional DLLs */\r
- \r
- // mark device started\r
- l_pMdDevContext->m_DeviceStarted = TRUE;\r
-\r
- // exit\r
- /* Write to event log */\r
- WriteEventLogEntry( g_pDrvContext->m_pDrvObject, MD_EVENT_LOG_LOAD_OK, 0, 0, 0 );\r
- MdKdPrint( DBGLVL_DEFAULT, ("(MdStartDevice) exit (%x)\n", l_Status));\r
- return l_Status;\r
- \r
-err:\r
-#pragma warning( push )\r
-#pragma warning( disable:4296 )\r
- MdKdPrint( DBGLVL_ALWAYS ,("(MdStartDevice) Device failed to initialize \n"));\r
-#pragma warning( pop )\r
-\r
- /* Write to event log */\r
- WriteEventLogEntry( g_pDrvContext->m_pDrvObject, l_EventCode,\r
- 0, l_Status, 1, l_Status );\r
- return STATUS_UNSUCCESSFUL;\r
-}\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-NTSTATUS\r
-MdRemoveDevice(\r
- IN PDEVICE_OBJECT pi_pFdo\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Called from MdProcessPnPIrp() to\r
- clean up our device instance's allocated buffers; free symbolic links\r
-\r
-Arguments:\r
-\r
- pi_pFdo - pointer to the FDO\r
-\r
-Return Value:\r
-\r
- NT status code from free symbolic link operation\r
-\r
---*/\r
-{\r
- PMD_DEV_CONTEXT_T l_pMdDevContext = (PMD_DEV_CONTEXT_T)pi_pFdo->DeviceExtension;\r
- NTSTATUS l_Status = STATUS_SUCCESS;\r
-\r
- MdKdPrint( DBGLVL_DEFAULT,("enter MdRemoveDevice\n"));\r
-\r
- /* remove functional device object (FDO) */\r
- MdDevDeInit( l_pMdDevContext ); \r
- \r
- MdKdPrint( DBGLVL_DEFAULT,("exit MdRemoveDevice() status = 0x%x\n", l_Status ));\r
-\r
- return l_Status;\r
-}\r
-\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-NTSTATUS\r
-MdStopDevice(\r
- IN PDEVICE_OBJECT pi_pFdo\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Stops a given instance of a 82930 device on the USB.\r
- We basically just tell USB this device is now 'unconfigured'\r
-\r
-Arguments:\r
-\r
- pi_pFdo - pointer to the device object for this instance of a 82930\r
-\r
-Return Value:\r
-\r
- NT status code\r
-\r
---*/\r
-{\r
- PMD_DEV_CONTEXT_T l_pMdDevContext = pi_pFdo->DeviceExtension;\r
- NTSTATUS l_Status = STATUS_SUCCESS;\r
- HH_hca_hndl_t l_hHhHca = l_pMdDevContext->m_hHhHca;\r
-\r
- MdKdPrint( DBGLVL_DEFAULT,("enter MdStopDevice\n"));\r
-\r
- // mark device stopping\r
- l_pMdDevContext->m_StopDeviceRequested = TRUE;\r
-\r
- // TBD\r
- // stop the card by sending some commands to it or suspend all new requests and wait for the end of in-progress ones\r
- //\r
-\r
- if ((l_pMdDevContext->m_eDevType == MD_DEV_IX_TAVOR ||\r
- l_pMdDevContext->m_eDevType == MD_DEV_IX_ARBEL_TM)&& g_pDrvContext->m_fSupportTavor)\r
- { /* remove HCA from Tavor functional DLLs */\r
- \r
- HH_ret_t l_HhRet;\r
- //VAPI_ret_t l_VapiRet;\r
-\r
- /* de-init IB_MGT */\r
- //if (g_pDrvContext->m_fSupportIbMgt) {\r
- // if (--IB_MGT_started > 0) {\r
-// if (l_pMdDevContext->m_hHca != VAPI_INVAL_HNDL)\r
- // IB_MGT_fatal_delete_hca( l_pMdDevContext->m_hHca );\r
- // MdKdPrint( DBGLVL_LOW,("'%s' detached from IB_MGT\n",l_pMdDevContext->m_AsciiDevName));\r
- // }\r
- // else {\r
- // IB_MGT_cleanup_module();\r
- // MdKdPrint( DBGLVL_LOW,("The last HCA '%s' detached from IB_MGT\n",l_pMdDevContext->m_AsciiDevName));\r
- // }\r
- //}\r
- \r
- /* close HCA handle */\r
- //if (l_pMdDevContext->m_hHca != VAPI_INVAL_HNDL)\r
- // l_VapiRet = VAPI_close_hca( l_pMdDevContext->m_hHca ); \r
- //if (l_VapiRet) {\r
- // DbgPrint("MdStopDevice: error 0x%x on VAPI_close_hca\n", l_VapiRet);\r
- //}\r
- \r
- /* remove HCA */\r
- //l_HhRet = THH_rmv_hca( l_pMdDevContext->m_uCardNo-1 );\r
- l_pMdDevContext->m_hHhHca = (HH_hca_hndl_t)NULL;\r
- if ( l_hHhHca != (HH_hca_hndl_t)NULL)\r
- l_HhRet = THH_hob_destroy( l_hHhHca );\r
- if (l_HhRet) {\r
- DbgPrint("MdStopDevice: error 0x%x on THH_rmv_hca\n", l_HhRet);\r
- }\r
- \r
- /* save HCA handle */\r
- l_pMdDevContext->m_hHca = VAPI_INVAL_HNDL;\r
- \r
- } /* remove HCA from Tavor functional DLLs */\r
- \r
- // remove device from MOSAL\r
- MOSAL_remove_device( l_pMdDevContext->m_hMosal );\r
-\r
- // release PCI card resources\r
- MdDeInitPciCfgCard( l_pMdDevContext );\r
-\r
- // mark device stopping\r
- l_pMdDevContext->m_DeviceStarted = FALSE;\r
- l_pMdDevContext->m_StopDeviceRequested = FALSE;\r
-\r
- MdKdPrint( DBGLVL_DEFAULT,("exit MdStopDevice() (%x)\n", l_Status));\r
-\r
- return l_Status;\r
-}\r
-\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-NTSTATUS\r
-MdIrpCompletionRoutine(\r
- IN PDEVICE_OBJECT pi_pFdo,\r
- IN PIRP pi_pIrp,\r
- IN PVOID Context\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Used as a general purpose completion routine so it can signal an event,\r
- passed as the Context, when the next lower driver is done with the input Irp.\r
- This routine is used by both PnP and Power Management logic.\r
-\r
- Even though this routine does nothing but set an event, it must be defined and\r
- prototyped as a completetion routine for use as such\r
-\r
-\r
-Arguments:\r
-\r
- pi_pFdo - Pointer to the device object for the class device.\r
-\r
- pi_pIrp - Irp completed.\r
-\r
- Context - Driver defined context, in this case a pointer to an event.\r
-\r
-Return Value:\r
-\r
- The function value is the final status from the operation.\r
-\r
---*/\r
-{\r
- PKEVENT event = Context;\r
-\r
- // Set the input event\r
- KeSetEvent(event,\r
- 1, // Priority increment for waiting thread.\r
- FALSE); // Flag this call is not immediately followed by wait.\r
-\r
- // This routine must return STATUS_MORE_PROCESSING_REQUIRED because we have not yet called\r
- // IoFreeIrp() on this IRP.\r
- return STATUS_MORE_PROCESSING_REQUIRED;\r
-\r
-}\r
-\r
\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#include "MdGen.h"\r
-\r
- \r
-\r
-NTSTATUS\r
-MdProcessPowerIrp(\r
- IN PDEVICE_OBJECT pi_pFdo,\r
- IN PIRP pi_pIrp\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This is our FDO's dispatch table function for IRP_MJ_POWER.\r
- It processes the Power IRPs sent to the PDO for this device.\r
-\r
- For every power IRP, drivers must call PoStartNextPowerIrp and use PoCallDriver\r
- to pass the IRP all the way down the driver stack to the underlying PDO.\r
-\r
-\r
-Arguments:\r
-\r
- pi_pFdo - pointer to our device object (FDO)\r
-\r
- pi_pIrp - pointer to an I/O Request Packet\r
-\r
-Return Value:\r
-\r
- NT status code\r
-\r
---*/\r
-{\r
-\r
- PIO_STACK_LOCATION l_pIrpStack;\r
- NTSTATUS l_Status = STATUS_SUCCESS;\r
- PMD_DEV_CONTEXT_T l_pMdDevContext;\r
- BOOLEAN fGoingToD0 = FALSE;\r
- POWER_STATE l_SysPowerState, l_DesiredDevicePowerState;\r
- KEVENT l_Event;\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,(" MdProcessPowerIrp() IRP_MJ_POWER\n"));\r
-\r
- l_pMdDevContext = (PMD_DEV_CONTEXT_T) pi_pFdo->DeviceExtension;\r
- l_pIrpStack = IoGetCurrentIrpStackLocation (pi_pIrp);\r
- MdIncrementIoCount(l_pMdDevContext);\r
-\r
- switch (l_pIrpStack->MinorFunction) {\r
- case IRP_MN_WAIT_WAKE:\r
- MdKdPrint( DBGLVL_MEDIUM,("MdProcessPowerIrp() Enter IRP_MN_WAIT_WAKE\n"));\r
-\r
- // A driver sends IRP_MN_WAIT_WAKE to indicate that the system should\r
- // wait for its device to signal a wake l_Event. The exact nature of the l_Event\r
- // is device-dependent.\r
- // Drivers send this IRP for two reasons:\r
- // 1) To allow a device to wake the system\r
- // 2) To wake a device that has been put into a sleep state to save power\r
- // but still must be able to communicate with its driver under certain circumstances.\r
- // When a wake l_Event occurs, the driver completes the IRP and returns\r
- // STATUS_SUCCESS. If the device is sleeping when the l_Event occurs,\r
- // the driver must first wake up the device before completing the IRP.\r
- // In a completion routine, the driver calls PoRequestPowerIrp to send a\r
- // PowerDeviceD0 request. When the device has powered up, the driver can\r
- // handle the IRP_MN_WAIT_WAKE request.\r
-\r
- // l_pMdDevContext->m_DeviceCapabilities.DeviceWake specifies the lowest device power state (least powered)\r
- // from which the device can signal a wake l_Event\r
- l_pMdDevContext->m_PowerDownLevel = l_pMdDevContext->m_DeviceCapabilities.DeviceWake;\r
-\r
-\r
- if ( ( PowerDeviceD0 == l_pMdDevContext->m_CurrentDevicePowerState ) ||\r
- ( l_pMdDevContext->m_DeviceCapabilities.DeviceWake > l_pMdDevContext->m_CurrentDevicePowerState ) ) {\r
- //\r
- // STATUS_INVALID_DEVICE_STATE is returned if the device in the PowerD0 state\r
- // or a state below which it can support waking, or if the SystemWake state\r
- // is below a state which can be supported. A pending IRP_MN_WAIT_WAKE will complete\r
- // with this error if the device's state is changed to be incompatible with the wake\r
- // request.\r
-\r
- // If a driver fails this IRP, it should complete the IRP immediately without\r
- // passing the IRP to the next-lower driver.\r
- l_Status = STATUS_INVALID_DEVICE_STATE;\r
- pi_pIrp->IoStatus.Status = l_Status;\r
- IoCompleteRequest (pi_pIrp,IO_NO_INCREMENT );\r
- MdKdPrint( DBGLVL_HIGH, ( "Exit MdProcessPowerIrp(), l_Status STATUS_INVALID_DEVICE_STATE\n" ) );\r
- MdDecrementIoCount(l_pMdDevContext);\r
- return l_Status;\r
- }\r
-\r
- // flag we're enabled for wakeup\r
- l_pMdDevContext->m_EnabledForWakeup = TRUE;\r
-\r
- // init an l_Event for our completion routine to signal when PDO is done with this Irp\r
- KeInitializeEvent(&l_Event, NotificationEvent, FALSE);\r
-\r
- // If not failing outright, pass this on to our PDO for further handling\r
- IoCopyCurrentIrpStackLocationToNext(pi_pIrp);\r
-\r
- // Set a completion routine so it can signal our l_Event when\r
- // the PDO is done with the Irp\r
- IoSetCompletionRoutine(pi_pIrp,\r
- MdIrpCompletionRoutine,\r
- &l_Event, // pass the l_Event to the completion routine as the Context\r
- TRUE, // invoke on success\r
- TRUE, // invoke on error\r
- TRUE); // invoke on cancellation\r
-\r
- PoStartNextPowerIrp(pi_pIrp);\r
- l_Status = PoCallDriver(l_pMdDevContext->m_pLdo,\r
- pi_pIrp);\r
-\r
- // if PDO is not done yet, wait for the l_Event to be set in our completion routine\r
- if (l_Status == STATUS_PENDING) {\r
- // wait for irp to complete\r
-\r
- NTSTATUS waitStatus = KeWaitForSingleObject(\r
- &l_Event,\r
- Suspended,\r
- KernelMode,\r
- FALSE,\r
- NULL);\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,("MdProcessPowerIrp() done waiting for PDO to finish IRP_MN_WAIT_WAKE\n"));\r
- }\r
-\r
- // now tell the device to actually wake up\r
- MdSelfSuspendOrActivate( pi_pFdo, FALSE );\r
-\r
- // flag we're done with wakeup irp\r
- l_pMdDevContext->m_EnabledForWakeup = FALSE;\r
-\r
- MdDecrementIoCount(l_pMdDevContext);\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,("MdProcessPowerIrp() Exit IRP_MN_WAIT_WAKE\n"));\r
- break;\r
-\r
- case IRP_MN_SET_POWER:\r
- {\r
-\r
- // The system power policy manager sends this IRP to set the system power state.\r
- // A device power policy manager sends this IRP to set the device power state for a device.\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,("MdProcessPowerIrp() Enter IRP_MN_SET_POWER\n"));\r
-\r
- // Set Irp->IoStatus.Status to STATUS_SUCCESS to indicate that the device\r
- // has entered the requested state. Drivers cannot fail this IRP.\r
-\r
- switch (l_pIrpStack->Parameters.Power.Type) {\r
- case SystemPowerState:\r
-\r
- // Get input system power state\r
- l_SysPowerState.SystemState = l_pIrpStack->Parameters.Power.State.SystemState;\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,("MdProcessPowerIrp() Set Power, type SystemPowerState = %s\n",\r
- MdStringForSysState( l_SysPowerState.SystemState ) ));\r
-\r
- // If system is in working state always set our device to D0\r
- // regardless of the wait state or system-to-device state power map\r
- if ( l_SysPowerState.SystemState == PowerSystemWorking) {\r
- l_DesiredDevicePowerState.DeviceState = PowerDeviceD0;\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,("MdProcessPowerIrp() PowerSystemWorking, will set D0, not use state map\n"));\r
-\r
-\r
- } else {\r
- // set to corresponding system state if IRP_MN_WAIT_WAKE pending\r
- if ( l_pMdDevContext->m_EnabledForWakeup ) { // got a WAIT_WAKE IRP pending?\r
-\r
- // Find the device power state equivalent to the given system state.\r
- // We get this info from the DEVICE_CAPABILITIES struct in our device\r
- // extension (initialized in MdPnPAddDevice() )\r
- l_DesiredDevicePowerState.DeviceState =\r
- l_pMdDevContext->m_DeviceCapabilities.DeviceState[ l_SysPowerState.SystemState ];\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,("MdProcessPowerIrp() IRP_MN_WAIT_WAKE pending, will use state map\n"));\r
-\r
- } else {\r
- // if no wait pending and the system's not in working state, just turn off\r
- l_DesiredDevicePowerState.DeviceState = PowerDeviceD3;\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,("MdProcessPowerIrp() Not m_EnabledForWakeup and the system's not in working state,\n settting PowerDeviceD3 (off )\n"));\r
- }\r
- }\r
-\r
- //\r
- // We've determined the desired device state; are we already in this state?\r
- //\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,("MdProcessPowerIrp() Set Power, l_DesiredDevicePowerState = %s\n",\r
- MdStringForDevState( l_DesiredDevicePowerState.DeviceState ) ));\r
-\r
- if (l_DesiredDevicePowerState.DeviceState !=\r
- l_pMdDevContext->m_CurrentDevicePowerState) {\r
-\r
- // MdIncrementIoCount(l_pMdDevContext);\r
-\r
- // No, request that we be put into this state\r
- // by requesting a new Power Irp from the Pnp manager\r
- l_pMdDevContext->m_PowerIrp = pi_pIrp;\r
- l_Status = PoRequestPowerIrp(l_pMdDevContext->m_pPdo,\r
- IRP_MN_SET_POWER,\r
- l_DesiredDevicePowerState,\r
- // completion routine will pass the Irp down to the PDO\r
- MdPoRequestCompletion,\r
- pi_pFdo,\r
- NULL);\r
-\r
- } else {\r
- // Yes, just pass it on to PDO (Physical Device Object)\r
- IoCopyCurrentIrpStackLocationToNext(pi_pIrp);\r
- PoStartNextPowerIrp(pi_pIrp);\r
- l_Status = PoCallDriver(l_pMdDevContext->m_pLdo,\r
- pi_pIrp);\r
-\r
- MdDecrementIoCount(l_pMdDevContext);\r
- MdKdPrint( DBGLVL_MEDIUM,("MdProcessPowerIrp() Exit IRP_MN_SET_POWER\n"));\r
-\r
- }\r
- break;\r
-\r
- case DevicePowerState:\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,("MdProcessPowerIrp() Set Power, type DevicePowerState = %s\n",\r
- MdStringForDevState( l_pIrpStack->Parameters.Power.State.DeviceState ) ));\r
-\r
- // For requests to D1, D2, or D3 ( sleep or off states ),\r
- // sets l_pMdDevContext->m_CurrentDevicePowerState to DeviceState immediately.\r
- // This enables any code checking state to consider us as sleeping or off\r
- // already, as this will imminently become our state.\r
-\r
- // For requests to DeviceState D0 ( fully on ), sets fGoingToD0 flag TRUE\r
- // to flag that we must set a completion routine and update\r
- // l_pMdDevContext->m_CurrentDevicePowerState there.\r
- // In the case of powering up to fully on, we really want to make sure\r
- // the process is completed before updating our m_CurrentDevicePowerState,\r
- // so no IO will be attempted or accepted before we're really ready.\r
-\r
- fGoingToD0 = MdSetDevicePowerState(pi_pFdo,\r
- l_pIrpStack->Parameters.Power.State.DeviceState\r
- ); // returns TRUE for D0\r
-\r
- IoCopyCurrentIrpStackLocationToNext(pi_pIrp);\r
-\r
- if (fGoingToD0) {\r
- MdKdPrint( DBGLVL_MEDIUM,("MdProcessPowerIrp() Set m_PowerIrp Completion Routine, fGoingToD0 =%d\n", fGoingToD0));\r
- IoSetCompletionRoutine(pi_pIrp,\r
- MdPowerIrp_Complete,\r
- // Always pass FDO to completion routine as its Context;\r
- // This is because the DriverObject passed by the system to the routine\r
- // is the Physical Device Object ( PDO ) not the Functional Device Object ( FDO )\r
- pi_pFdo,\r
- TRUE, // invoke on success\r
- TRUE, // invoke on error\r
- TRUE); // invoke on cancellation of the Irp\r
- }\r
-\r
- PoStartNextPowerIrp(pi_pIrp);\r
- l_Status = PoCallDriver(l_pMdDevContext->m_pLdo,\r
- pi_pIrp);\r
-\r
- if ( !fGoingToD0 ) // completion routine will decrement\r
- MdDecrementIoCount(l_pMdDevContext);\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,("MdProcessPowerIrp() Exit IRP_MN_SET_POWER\n"));\r
- break;\r
- } /* case irpStack->Parameters.Power.Type */\r
-\r
- }\r
- break; /* IRP_MN_SET_POWER */\r
-\r
- case IRP_MN_QUERY_POWER:\r
- //\r
- // A power policy manager sends this IRP to determine whether it can change\r
- // the system or device power state, typically to go to sleep.\r
- //\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,("MdProcessPowerIrp() IRP_MN_QUERY_POWER\n"));\r
-\r
- // We do nothing special here, just let the PDO handle it\r
- IoCopyCurrentIrpStackLocationToNext(pi_pIrp);\r
- PoStartNextPowerIrp(pi_pIrp);\r
- l_Status = PoCallDriver(l_pMdDevContext->m_pLdo,\r
- pi_pIrp);\r
-\r
-\r
- MdDecrementIoCount(l_pMdDevContext);\r
-\r
- break; /* IRP_MN_QUERY_POWER */\r
-\r
- default:\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,("MdProcessPowerIrp() UNKNOWN POWER MESSAGE (%x)\n", l_pIrpStack->MinorFunction));\r
-\r
- //\r
- // All unhandled power messages are passed on to the PDO\r
- //\r
-\r
- IoCopyCurrentIrpStackLocationToNext(pi_pIrp);\r
- PoStartNextPowerIrp(pi_pIrp);\r
- l_Status = PoCallDriver(l_pMdDevContext->m_pLdo, pi_pIrp);\r
-\r
- MdDecrementIoCount(l_pMdDevContext);\r
-\r
- } /* l_pIrpStack->MinorFunction */\r
-\r
- MdKdPrint( DBGLVL_MEDIUM, ( "Exit MdProcessPowerIrp() l_Status = 0x%x\n", l_Status ) );\r
- return l_Status;\r
-}\r
-\r
-\r
-NTSTATUS\r
-MdPoRequestCompletion(\r
- IN PDEVICE_OBJECT pi_pDeviceObject,\r
- IN UCHAR pi_MinorFunction,\r
- IN POWER_STATE pi_PowerState,\r
- IN PVOID pi_pContext,\r
- IN PIO_STATUS_BLOCK pi_pIoStatus\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This is the completion routine set in a call to PoRequestPowerIrp()\r
- that was made in MdProcessPowerIrp() in response to receiving\r
- an IRP_MN_SET_POWER of type 'SystemPowerState' when the device was\r
- not in a compatible device power state. In this case, a pointer to\r
- the IRP_MN_SET_POWER Irp is saved into the FDO device extension\r
- (l_pMdDevContext->m_PowerIrp), and then a call must be\r
- made to PoRequestPowerIrp() to put the device into a proper power state,\r
- and this routine is set as the completion routine.\r
-\r
- We decrement our pending io count and pass the saved IRP_MN_SET_POWER Irp\r
- on to the next driver\r
-\r
-Arguments:\r
-\r
- pi_pDeviceObject - Pointer to the device object for the class device.\r
- Note that we must get our own device object from the Context\r
-\r
- pi_pContext - Driver defined context, in this case our own functional device object ( FDO )\r
-\r
-Return Value:\r
-\r
- The function value is the final status from the operation.\r
-\r
---*/\r
-{\r
- PIRP l_pIrp;\r
- PMD_DEV_CONTEXT_T l_pMdDevContext;\r
- PDEVICE_OBJECT l_pDeviceObject = pi_pContext;\r
- NTSTATUS l_Status;\r
-\r
- l_pMdDevContext = l_pDeviceObject->DeviceExtension;\r
-\r
- // Get the Irp we saved for later processing in MdProcessPowerIrp()\r
- // when we decided to request the Power Irp that this routine\r
- // is the completion routine for.\r
- l_pIrp = l_pMdDevContext->m_PowerIrp;\r
-\r
- // We will return the status set by the PDO for the power request we're completing\r
- l_Status = pi_pIoStatus->Status;\r
-\r
- MdKdPrint( DBGLVL_HIGH,("(MdPoRequestCompletion) Enter\n"));\r
-\r
- // we should not be in the midst of handling a self-generated power irp\r
- MDASSERT( !l_pMdDevContext->m_SelfPowerIrp );\r
-\r
- // we must pass down to the next driver in the stack\r
- IoCopyCurrentIrpStackLocationToNext(l_pIrp);\r
-\r
- // Calling PoStartNextPowerIrp() indicates that the driver is finished\r
- // with the previous power IRP, if any, and is ready to handle the next power IRP.\r
- // It must be called for every power IRP.Although power IRPs are completed only once,\r
- // typically by the lowest-level driver for a device, PoStartNextPowerIrp must be called\r
- // for every stack location. Drivers must call PoStartNextPowerIrp while the current IRP\r
- // stack location points to the current driver. Therefore, this routine must be called\r
- // before IoCompleteRequest, IoSkipCurrentStackLocation, and PoCallDriver.\r
-\r
- PoStartNextPowerIrp(l_pIrp);\r
-\r
- // PoCallDriver is used to pass any power IRPs to the PDO instead of IoCallDriver.\r
- // When passing a power IRP down to a lower-level driver, the caller should use\r
- // IoSkipCurrentIrpStackLocation or IoCopyCurrentIrpStackLocationToNext to copy the IRP to\r
- // the next stack location, then call PoCallDriver. Use IoCopyCurrentIrpStackLocationToNext\r
- // if processing the IRP requires setting a completion routine, or IoSkipCurrentStackLocation\r
- // if no completion routine is needed.\r
-\r
- PoCallDriver(l_pMdDevContext->m_pLdo, l_pIrp);\r
-\r
- MdDecrementIoCount(l_pMdDevContext);\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,("(MdPoRequestCompletion) Exit IRP_MN_SET_POWER\n"));\r
-\r
- l_pMdDevContext->m_PowerIrp = NULL;\r
-\r
- return l_Status;\r
-}\r
-\r
-\r
-NTSTATUS\r
-MdPowerIrp_Complete(\r
- IN PDEVICE_OBJECT pi_pNullDeviceObject,\r
- IN PIRP pi_pIrp,\r
- IN PVOID pi_pContext\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This routine is called when An IRP_MN_SET_POWER of type 'DevicePowerState'\r
- has been received by MdProcessPowerIrp(), and that routine has determined\r
- 1) the request is for full powerup ( to PowerDeviceD0 ), and\r
- 2) We are not already in that state\r
- A call is then made to PoRequestPowerIrp() with this routine set as the completion routine.\r
-\r
-\r
-Arguments:\r
-\r
- pi_pNullDeviceObject - Pointer to the device object for the class device.\r
-\r
- pi_pIrp - Irp completed.\r
-\r
- pi_pContext - Driver defined context.\r
-\r
-Return Value:\r
-\r
- The function value is the final status from the operation.\r
-\r
---*/\r
-{\r
- NTSTATUS l_Status = STATUS_SUCCESS;\r
- PDEVICE_OBJECT l_pDeviceObject;\r
- PIO_STACK_LOCATION l_pIrpStack;\r
- PMD_DEV_CONTEXT_T l_pMdDevContext;\r
-\r
- MdKdPrint( DBGLVL_HIGH,("(MdPowerIrp_Complete) enter\n"));\r
-\r
- l_pDeviceObject = (PDEVICE_OBJECT) pi_pContext;\r
-\r
- l_pMdDevContext = (PMD_DEV_CONTEXT_T)l_pDeviceObject->DeviceExtension;\r
-\r
- // If the lower driver returned PENDING, mark our stack location as pending also.\r
- if (pi_pIrp->PendingReturned) \r
- {\r
- IoMarkIrpPending(pi_pIrp);\r
- }\r
-\r
- l_pIrpStack = IoGetCurrentIrpStackLocation (pi_pIrp);\r
-\r
- // We can assert that we're a device powerup-to D0 request,\r
- // because that was the only type of request we set a completion routine\r
- // for in the first place\r
- MDASSERT(l_pIrpStack->MajorFunction == IRP_MJ_POWER);\r
- MDASSERT(l_pIrpStack->MinorFunction == IRP_MN_SET_POWER);\r
- MDASSERT(l_pIrpStack->Parameters.Power.Type==DevicePowerState);\r
- MDASSERT(l_pIrpStack->Parameters.Power.State.DeviceState==PowerDeviceD0);\r
-\r
- // Now that we know we've let the lower drivers do what was needed to power up,\r
- // we can set our device extension flags accordingly\r
- l_pMdDevContext->m_CurrentDevicePowerState = PowerDeviceD0;\r
-\r
- pi_pIrp->IoStatus.Status = l_Status;\r
-\r
- MdDecrementIoCount(l_pMdDevContext);\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,("exit MdPowerIrp_Complete Exit IRP_MN_SET_POWER D0 complete\n"));\r
- return l_Status;\r
-}\r
-\r
-\r
-\r
-NTSTATUS\r
-MdSelfSuspendOrActivate(\r
- IN PDEVICE_OBJECT pi_pDeviceObject,\r
- IN BOOLEAN pi_fSuspend\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Called on MdPnPAddDevice() to power down until needed (i.e., till a pipe is actually opened).\r
- Called on MdCreate() to power up device to D0 before opening 1st pipe.\r
- Called on MdClose() to power down device if this is the last pipe.\r
-\r
-Arguments:\r
-\r
- pi_pDeviceObject - Pointer to the device object\r
-\r
- pi_fSuspend; TRUE to Suspend, FALSE to acivate.\r
-\r
-\r
-Return Value:\r
-\r
- If the operation is not attemtped, SUCCESS is returned.\r
- If the operation is attemtped, the value is the final status from the operation.\r
-\r
---*/\r
-{\r
- NTSTATUS l_Status = STATUS_SUCCESS;\r
- POWER_STATE l_PowerState;\r
- PMD_DEV_CONTEXT_T l_pMdDevContext;\r
-\r
-\r
- l_pMdDevContext = pi_pDeviceObject->DeviceExtension;\r
- MdKdPrint( DBGLVL_MAXIMUM,("(MdSelfSuspendOrActivate) Enter: fSuspend = %d\n", pi_fSuspend));\r
-\r
-\r
- // Can't accept request if:\r
- // 1) device is removed,\r
- // 2) has never been started,\r
- // 3) is stopped,\r
- // 4) has a remove request pending,\r
- // 5) has a stop device pending\r
- if ( !MdCanAcceptIoRequests( pi_pDeviceObject ) ) {\r
- l_Status = STATUS_DELETE_PENDING;\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,("ABORTING MdSelfSuspendOrActivate()\n"));\r
- return l_Status;\r
- }\r
-\r
-\r
- // don't do anything if any System-generated Device Pnp irps are pending\r
- if ( NULL != l_pMdDevContext->m_PowerIrp ) {\r
- MdKdPrint( DBGLVL_MAXIMUM,("Exit MdSelfSuspendOrActivate(),refusing on pending l_pMdDevContext->m_PowerIrp 0x%x\n", l_pMdDevContext->m_PowerIrp));\r
- return l_Status;\r
- }\r
-\r
- // don't do anything if any self-generated Device Pnp irps are pending\r
- if ( l_pMdDevContext->m_SelfPowerIrp ) {\r
- MdKdPrint( DBGLVL_MAXIMUM,("Exit MdSelfSuspendOrActivate(),refusing on pending l_pMdDevContext->m_SelfPowerIrp\n" ));\r
- return l_Status;\r
- }\r
-\r
- // dont do anything if registry CurrentControlSet\Services\BulkUsb\Parameters\m_PowerDownLevel\r
- // has been set to zero, PowerDeviceD0 ( 1 ), or a bogus high value\r
- if ( ( l_pMdDevContext->m_PowerDownLevel == PowerDeviceD0 ) ||\r
- ( l_pMdDevContext->m_PowerDownLevel == PowerDeviceUnspecified) ||\r
- ( l_pMdDevContext->m_PowerDownLevel >= PowerDeviceMaximum ) ) {\r
- MdKdPrint( DBGLVL_MAXIMUM,("Exit MdSelfSuspendOrActivate(), refusing on l_pMdDevContext->m_PowerDownLevel == %d\n", l_pMdDevContext->m_PowerDownLevel));\r
- return l_Status;\r
- }\r
-\r
- if ( pi_fSuspend )\r
- l_PowerState.DeviceState = l_pMdDevContext->m_PowerDownLevel;\r
- else\r
- l_PowerState.DeviceState = PowerDeviceD0; // power up all the way; we're probably just about to do some IO\r
-\r
- l_Status = MdSelfRequestPowerIrp( pi_pDeviceObject, l_PowerState );\r
-\r
- MdKdPrint( DBGLVL_MAXIMUM,("MdSelfSuspendOrActivate() status 0x%x on setting dev state %s\n", l_Status, MdStringForDevState(l_PowerState.DeviceState ) ));\r
-\r
- return l_Status;\r
-\r
-}\r
-\r
-\r
-NTSTATUS\r
-MdSelfRequestPowerIrp(\r
- IN PDEVICE_OBJECT pi_pDeviceObject,\r
- IN POWER_STATE pi_PowerState\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This routine is called by MdSelfSuspendOrActivate() to\r
- actually make the system request for a powerdown/up to PowerState.\r
- It first checks to see if we are already in Powerstate and immediately\r
- returns SUCCESS with no further processing if so\r
-\r
-\r
-Arguments:\r
-\r
- pi_pDeviceObject - Pointer to the device object\r
-\r
- pi_PowerState. power state requested, e.g PowerDeviceD0.\r
-\r
-\r
-Return Value:\r
-\r
- The function value is the final status from the operation.\r
-\r
---*/\r
-{\r
- NTSTATUS l_Status = STATUS_SUCCESS;\r
- PMD_DEV_CONTEXT_T l_pMdDevContext;\r
- PIRP l_pIrp = NULL;\r
-\r
- l_pMdDevContext = pi_pDeviceObject->DeviceExtension;\r
-\r
- // This should have been reset in completion routine\r
- MDASSERT( !l_pMdDevContext->m_SelfPowerIrp );\r
-\r
- if ( l_pMdDevContext->m_CurrentDevicePowerState == pi_PowerState.DeviceState )\r
- return STATUS_SUCCESS; // nothing to do\r
-\r
- MdKdPrint( DBGLVL_HIGH,("Enter MdSelfRequestPowerIrp() will request power irp to state %s\n",\r
- MdStringForDevState( pi_PowerState.DeviceState )));\r
-\r
- MdIncrementIoCount(l_pMdDevContext);\r
-\r
- // flag we're handling a self-generated power irp\r
- l_pMdDevContext->m_SelfPowerIrp = TRUE;\r
-\r
- // actually request the Irp\r
- l_Status = PoRequestPowerIrp(l_pMdDevContext->m_pPdo,\r
- IRP_MN_SET_POWER,\r
- pi_PowerState,\r
- MdPoSelfRequestCompletion,\r
- pi_pDeviceObject,\r
- NULL);\r
-\r
-\r
- if ( l_Status == STATUS_PENDING ) {\r
- // status pending is the return code we wanted\r
-\r
- // We only need to wait for completion if we're powering up\r
- if ( (ULONG) pi_PowerState.DeviceState < l_pMdDevContext->m_PowerDownLevel ) {\r
-\r
- NTSTATUS waitStatus;\r
-\r
- waitStatus = KeWaitForSingleObject(\r
- &l_pMdDevContext->m_SelfRequestedPowerIrpEvent,\r
- Suspended,\r
- KernelMode,\r
- FALSE,\r
- NULL);\r
-\r
- }\r
-\r
- l_Status = STATUS_SUCCESS;\r
-\r
- l_pMdDevContext->m_SelfPowerIrp = FALSE;\r
-\r
- MdKdPrint( DBGLVL_HIGH, ("MdSelfRequestPowerIrp() SUCCESS\n IRP 0x%x to state %s\n",\r
- l_pIrp, MdStringForDevState(pi_PowerState.DeviceState) ));\r
-\r
-\r
- }\r
- else {\r
- // The return status was not STATUS_PENDING; any other codes must be considered in error here;\r
- // i.e., it is not possible to get a STATUS_SUCCESS or any other non-error return from this call;\r
- MdKdPrint( DBGLVL_HIGH, ("MdSelfRequestPowerIrp() to state %s FAILED, status = 0x%x\n",\r
- MdStringForDevState( pi_PowerState.DeviceState ),l_Status));\r
- }\r
-\r
- return l_Status;\r
-}\r
-\r
-\r
-\r
-NTSTATUS\r
-MdPoSelfRequestCompletion(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN UCHAR MinorFunction,\r
- IN POWER_STATE pi_PowerState,\r
- IN PVOID Context,\r
- IN PIO_STATUS_BLOCK IoStatus\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This routine is called when the driver completes a self-originated power IRP\r
- that was generated by a call to MdSelfSuspendOrActivate().\r
- We power down whenever the last pipe is closed and power up when the first pipe is opened.\r
-\r
- For power-up , we set an l_Event in our FDO extension to signal this IRP done\r
- so the power request can be treated as a synchronous call.\r
- We need to know the device is powered up before opening the first pipe, for example.\r
- For power-down, we do not set the l_Event, as no caller waits for powerdown complete.\r
-\r
-Arguments:\r
-\r
- DeviceObject - Pointer to the device object for the class device. ( Physical Device Object )\r
-\r
- Context - Driver defined context, in this case our FDO ( functional device object )\r
-\r
-Return Value:\r
-\r
- The function value is the final status from the operation.\r
-\r
---*/\r
-{\r
- PDEVICE_OBJECT deviceObject = Context;\r
- PMD_DEV_CONTEXT_T l_pMdDevContext = deviceObject->DeviceExtension;\r
- NTSTATUS l_Status = IoStatus->Status;\r
-\r
- // we should not be in the midst of handling a system-generated power irp\r
- MDASSERT( NULL == l_pMdDevContext->m_PowerIrp );\r
-\r
- // We only need to set the l_Event if we're powering up;\r
- // No caller waits on power down complete\r
- if ( (ULONG) pi_PowerState.DeviceState < l_pMdDevContext->m_PowerDownLevel ) {\r
-\r
- // Trigger Self-requested power irp completed l_Event;\r
- // The caller is waiting for completion\r
- KeSetEvent(&l_pMdDevContext->m_SelfRequestedPowerIrpEvent, 1, FALSE);\r
- }\r
-\r
- MdDecrementIoCount(l_pMdDevContext);\r
-\r
- MdKdPrintCond( DBGLVL_HIGH, !NT_SUCCESS(l_Status),("Exit MdPoSelfRequestCompletion() FAILED, l_Status = 0x%x\n", l_Status ));\r
-\r
- return l_Status;\r
-}\r
-\r
-\r
-BOOLEAN\r
-MdSetDevicePowerState(\r
- IN PDEVICE_OBJECT DeviceObject,\r
- IN DEVICE_POWER_STATE DeviceState\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This routine is called when An IRP_MN_SET_POWER of type 'DevicePowerState'\r
- has been received by MdProcessPowerIrp().\r
-\r
-\r
-Arguments:\r
-\r
- DeviceObject - Pointer to the device object for the class device.\r
-\r
- DeviceState - Device specific power state to set the device in to.\r
-\r
-\r
-Return Value:\r
-\r
- For requests to DeviceState D0 ( fully on ), returns TRUE to signal caller\r
- that we must set a completion routine and finish there.\r
-\r
---*/\r
-{\r
- NTSTATUS l_Status = STATUS_SUCCESS;\r
- PMD_DEV_CONTEXT_T l_pMdDevContext;\r
- BOOLEAN fRes = FALSE;\r
-\r
- l_pMdDevContext = (PMD_DEV_CONTEXT_T) DeviceObject->DeviceExtension;\r
-\r
- switch (DeviceState) {\r
- case PowerDeviceD3:\r
-\r
- //\r
- // Device will be going OFF,\r
- //\r
- MdKdPrint( DBGLVL_MEDIUM,("MdSetDevicePowerState() PowerDeviceD3 (OFF)\n"));\r
- MdStopDevice(DeviceObject);\r
- l_pMdDevContext->m_CurrentDevicePowerState = DeviceState;\r
- break;\r
-\r
- case PowerDeviceD1:\r
- case PowerDeviceD2:\r
- //\r
- // power states D1,D2 translate to USB suspend\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,("MdSetDevicePowerState() %s\n",\r
- MdStringForDevState(DeviceState) ));\r
-\r
- l_pMdDevContext->m_CurrentDevicePowerState = DeviceState;\r
- break;\r
-\r
- case PowerDeviceD0:\r
-\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,("MdSetDevicePowerState() PowerDeviceD0 (ON)\n"));\r
-\r
- // We'll need to finish the rest in the completion routine;\r
- // signal caller we're going to D0 and will need to set a completion routine\r
- fRes = TRUE;\r
-\r
- // Caller will pass on to PDO ( Physical Device object )\r
- break;\r
-\r
- default:\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,(" Bogus DeviceState = %x\n", DeviceState));\r
- }\r
-\r
- return fRes;\r
-}\r
-\r
-\r
-\r
-NTSTATUS\r
-MdQueryCapabilities(\r
- IN PDEVICE_OBJECT pi_pLowerDevObject,\r
- OUT PDEVICE_CAPABILITIES po_pm_DeviceCapabilities\r
- )\r
-\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This routine generates an internal IRP from this driver to the lower portion\r
- of the driver stack to obtain information on the Device Object's\r
- capabilities. We are most interested in learning which system power states\r
- are to be mapped to which device power states for honoring\r
- IRP_MJ_SET_POWER Irps.\r
-\r
- This is a blocking call which waits for the IRP completion routine\r
- to set an l_Event on finishing.\r
-\r
-Arguments:\r
-\r
- pi_pLowerDevObject - DeviceObject beneath this driver in the stack.\r
- po_pm_DeviceCapabilities - Device Capabilities structure\r
-\r
-Return Value:\r
-\r
- NTSTATUS value from the IoCallDriver() call.\r
-\r
---*/\r
-\r
-{\r
- PIO_STACK_LOCATION l_pNextStack;\r
- PIRP l_pIrp;\r
- NTSTATUS l_Status;\r
- KEVENT l_Event;\r
-\r
-\r
- // This is a DDK-defined DBG-only macro that ASSERTS we are not running pageable code\r
- // at higher than APC_LEVEL.\r
- PAGED_CODE();\r
-\r
-\r
- // Build an IRP for us to generate an internal query request to the PDO\r
- l_pIrp = IoAllocateIrp( pi_pLowerDevObject->StackSize, FALSE);\r
-\r
- if (!l_pIrp) \r
- {\r
- return STATUS_INSUFFICIENT_RESOURCES;\r
- }\r
-\r
- //\r
- // Preinit the device capability structures appropriately.\r
- //\r
- RtlZeroMemory( po_pm_DeviceCapabilities, sizeof(DEVICE_CAPABILITIES) );\r
- po_pm_DeviceCapabilities->Size = sizeof(DEVICE_CAPABILITIES);\r
- po_pm_DeviceCapabilities->Version = 1;\r
- po_pm_DeviceCapabilities->Address = -1;\r
- po_pm_DeviceCapabilities->UINumber = -1;\r
-\r
- // IoGetNextIrpStackLocation gives a higher level driver access to the next-lower\r
- // driver's I/O stack location in an IRP so the caller can set it up for the lower driver.\r
- l_pNextStack = IoGetNextIrpStackLocation(l_pIrp);\r
- l_pNextStack->MajorFunction= IRP_MJ_PNP;\r
- l_pNextStack->MinorFunction= IRP_MN_QUERY_CAPABILITIES;\r
-\r
- // init an l_Event to tell us when the completion routine's been called\r
- KeInitializeEvent(&l_Event, NotificationEvent, FALSE);\r
-\r
- // Set a completion routine so it can signal our l_Event when\r
- // the next lower driver is done with the Irp\r
- IoSetCompletionRoutine(l_pIrp,\r
- MdIrpCompletionRoutine,\r
- &l_Event, // pass the l_Event as Context to completion routine\r
- TRUE, // invoke on success\r
- TRUE, // invoke on error\r
- TRUE); // invoke on cancellation of the Irp\r
-\r
-\r
- // set our pointer to the DEVICE_CAPABILITIES struct\r
- l_pNextStack->Parameters.DeviceCapabilities.Capabilities = po_pm_DeviceCapabilities;\r
-\r
- // preset the irp to report not supported\r
- l_pIrp->IoStatus.Status = STATUS_NOT_SUPPORTED;\r
-\r
- l_Status = IoCallDriver(pi_pLowerDevObject, l_pIrp);\r
-\r
- MdKdPrint( DBGLVL_MEDIUM,("(MdQueryCapabilities) l_Status from IoCallDriver to PCI = 0x%x\n", l_Status));\r
-\r
- if (l_Status == STATUS_PENDING) \r
- { /* wait for irp to complete */\r
-\r
- KeWaitForSingleObject(\r
- &l_Event,\r
- Suspended,\r
- KernelMode,\r
- FALSE,\r
- NULL);\r
-\r
- l_Status = l_pIrp->IoStatus.Status;\r
-\r
- } /* wait for irp to complete */\r
-\r
- // failed? this is probably a bug\r
- MdKdPrintCond( DBGLVL_DEFAULT,(!NT_SUCCESS(l_Status)), ("(MdQueryCapabilities) failed\n"));\r
-\r
- IoFreeIrp(l_pIrp);\r
-\r
- return l_Status;\r
-} \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "MdGen.h"\r
-\r
-//void* VIPKL_open(void);\r
-//void VIPKL_close(void* hca_stat_p);\r
-//void * IB_MGT_dev_open(void);\r
-//void IB_MGT_dev_close(void * proc_state_p);\r
-void *MOSAL_rsct_open(MOSAL_pid_t pid);\r
-void MOSAL_rsct_close(void *p_rsct, MOSAL_pid_t pid);\r
-//int IsIbMgtOn();\r
-\r
-\r
-\r
-\r
-NTSTATUS\r
-MdClose(\r
- IN PDEVICE_OBJECT pi_pFdo,\r
- IN PIRP pi_pIrp\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This is the dispatch table routine for IRP_MJ_CLOSE.\r
- It handles user mode CloseHandle() calls for a pipe\r
- It closes the File Object for the pipe handle it represents.\r
-\r
-Arguments:\r
-\r
- pi_pFdo - pointer to our FDO (Functional Device Object )\r
-\r
-\r
-Return Value:\r
-\r
- NT status code\r
-\r
---*/\r
-{\r
- NTSTATUS l_Status= STATUS_SUCCESS;\r
- PFILE_OBJECT l_pFileObject;\r
- PIO_STACK_LOCATION l_pIrpStack;\r
- PMD_DEV_CONTEXT_T l_pMdDevContext = (PMD_DEV_CONTEXT_T)pi_pFdo->DeviceExtension;\r
- PMD_PCS_CONTEXT_T l_pPcs;\r
-\r
- MdKdPrint( DBGLVL_HIGH,("entering MdClose\n"));\r
- \r
- MdIncrementIoCount(l_pMdDevContext);\r
-\r
- // get file handle \r
- l_pIrpStack = IoGetCurrentIrpStackLocation (pi_pIrp);\r
- l_pFileObject = l_pIrpStack->FileObject;\r
-\r
- // sanity check\r
- if (l_pFileObject->FsContext == NULL)\r
- { /* unexpectable: noone is using this field ! We can't proceed !! */\r
-#pragma warning( push )\r
-#pragma warning( disable:4296 )\r
- MdKdPrint( DBGLVL_ALWAYS,("MdClose: Someone has taken our private file context (FsContext=%p)- can't proceed \n",\r
- l_pFileObject->FsContext));\r
-#pragma warning( pop )\r
- l_Status = STATUS_UNSUCCESSFUL;\r
- goto done;\r
- } /* unexpectable: someone is using this field ! We can't proceed !! */\r
-\r
- // get process context \r
- l_pPcs = (PMD_PCS_CONTEXT_T)l_pFileObject->FsContext;\r
-\r
- // resource tracking\r
- switch (l_pMdDevContext->m_eDevType) \r
- { /* handle Ioctls */\r
- case MD_DEV_IX_TAVOR_SD:\r
- PciRelease( l_pMdDevContext, l_pPcs );\r
- break;\r
- \r
- case MD_DEV_IX_TAVOR:\r
- case MD_DEV_IX_ARBEL_TM:\r
- // MDCTL\r
- PciRelease( l_pMdDevContext, l_pPcs );\r
- break;\r
- \r
- case MD_DEV_IX_TAVOR_BD:\r
- break;\r
- \r
- case MD_DEV_IX_CTRL:\r
- // IB_MGT\r
- //if (IsIbMgtOn()) \r
- // IB_MGT_dev_close(l_pPcs->m_hIbMgt);\r
- // VIPKL\r
- // VIPKL_close(l_pPcs->m_hVipkl);\r
- // MOSAL\r
- MOSAL_rsct_close(l_pPcs->m_hMosal, l_pPcs->m_Pid); \r
- break;\r
- \r
- default:\r
- MdKdPrint( DBGLVL_DEFAULT,("(MdClose) Internal error - unknown device type %d\n", l_pMdDevContext->m_eDevType));\r
- l_Status = STATUS_NOT_IMPLEMENTED;\r
- break;\r
- \r
- } /* handle Ioctls */\r
- \r
-\r
- // remove the process context \r
- MdExFreePool( (PVOID)l_pPcs );\r
-\r
- /* decrement reference counter */\r
- InterlockedDecrement( &l_pMdDevContext->m_nOpenCount );\r
-\r
- /* remove control device on need */\r
- if (l_pMdDevContext->m_fDeletePending == TRUE && l_pMdDevContext->m_nOpenCount == 0)\r
- { /* no applications - one can remove the control device */\r
-\r
- // The final decrement to device extension PendingIoCount == 0\r
- // will set l_pMdDevContext->m_RemoveEvent, enabling device removal.\r
- // If there is no pending IO at this point, the below decrement will be it.\r
- MdDecrementIoCount(l_pMdDevContext);\r
-\r
- } /* no applications - one can remove the control device */\r
-\r
-done:\r
- pi_pIrp->IoStatus.Status = l_Status;\r
- pi_pIrp->IoStatus.Information = 0;\r
-\r
- IoCompleteRequest (pi_pIrp,\r
- IO_NO_INCREMENT\r
- );\r
- \r
- MdDecrementIoCount(l_pMdDevContext);\r
-\r
- // try to power down device if this is the last pipe\r
- // ??? actStat = MdSelfSuspendOrActivate( DeviceObject, TRUE );\r
-\r
- MdKdPrint( DBGLVL_HIGH,("exit MdClose status %x\n", l_Status));\r
-\r
- return l_Status;\r
-}\r
-\r
-\r
-NTSTATUS\r
-MdCreate(\r
- IN PDEVICE_OBJECT pi_pFdo,\r
- IN PIRP pi_pIrp\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This is the dispatch table routine for IRP_MJ_CREATE.\r
- It's the entry point for CreateFile() calls\r
- user mode apps may open "<name genned fron GUID>.\yy"\r
- where yy is the internal pipe id\r
-\r
-Arguments:\r
-\r
- pi_pFdo - pointer to our FDO ( Functional Device Object )\r
-\r
-\r
-Return Value:\r
-\r
- NT status code\r
-\r
---*/\r
-{\r
- NTSTATUS l_Status = STATUS_SUCCESS;\r
- PIO_STACK_LOCATION l_pIrpStack;\r
- PMD_DEV_CONTEXT_T l_pMdDevContext = (PMD_DEV_CONTEXT_T)pi_pFdo->DeviceExtension;\r
- PFILE_OBJECT l_pFileObject;\r
- PMD_PCS_CONTEXT_T l_pPcs;\r
-\r
- MdKdPrint( DBGLVL_HIGH,("entering MdCreate\n"));\r
-\r
- MdIncrementIoCount(l_pMdDevContext);\r
-\r
- // Can't accept a new io request if:\r
- // 1) device is removed, \r
- // 2) has never been started, \r
- // 3) is stopped,\r
- // 4) has a remove request pending,\r
- // 5) has a stop device pending\r
- if ( !MdCanAcceptIoRequests( pi_pFdo ) ) {\r
- l_Status = STATUS_DELETE_PENDING;\r
- MdKdPrint( DBGLVL_DEFAULT,("ABORTING MdCreate\n"));\r
- goto done;\r
- }\r
- \r
- // get file handle \r
- l_pIrpStack = IoGetCurrentIrpStackLocation (pi_pIrp);\r
- l_pFileObject = l_pIrpStack->FileObject;\r
- //MdKdPrint( DBGLVL_ALWAYS,("MdCreate: file handle %p\n",l_pFileObject));\r
-\r
- // sanity check\r
- if (l_pFileObject->FsContext != NULL)\r
- { /* unexpectable: someone is using this field ! We can't proceed !! */\r
-#pragma warning( push )\r
-#pragma warning( disable:4296 )\r
- MdKdPrint( DBGLVL_ALWAYS,("MdCreate: Someone is using private file context (FsContext=%p)- can't proceed \n",l_pFileObject->FsContext));\r
-#pragma warning( pop )\r
- l_Status = STATUS_UNSUCCESSFUL;\r
- goto done;\r
- } /* unexpectable: someone is using this field ! We can't proceed !! */\r
- \r
- // create process context\r
- l_pPcs = (PMD_PCS_CONTEXT_T)MdExAllocatePool(NonPagedPool, sizeof(MD_PCS_CONTEXT_T));\r
- if (l_pPcs == NULL )\r
- {\r
- l_Status = STATUS_INSUFFICIENT_RESOURCES;\r
- goto done;\r
- }\r
- l_pFileObject->FsContext = (PVOID)l_pPcs;\r
-\r
- // fill process context\r
- RtlZeroMemory( l_pPcs, sizeof(MD_PCS_CONTEXT_T) );\r
- l_pPcs->m_Pid = MOSAL_getpid();\r
- \r
- // resource tracking\r
- if ( l_pMdDevContext->m_eDevType == MD_DEV_IX_CTRL ) {\r
- // MOSAL\r
- l_pPcs->m_hMosal = MOSAL_rsct_open(l_pPcs->m_Pid); \r
- // // VIPKL \r
- //l_pPcs->m_hVipkl = VIPKL_open(); \r
- // // IB_MGT\r
- // l_pPcs->m_hIbMgt = IB_MGT_dev_open();\r
- }\r
-\r
- // increment counter of open files (= counter of processes, working with this device)\r
- InterlockedIncrement( &l_pMdDevContext->m_nOpenCount );\r
-\r
- MdKdPrint( DBGLVL_HIGH,("(MdCreate) File Object 0x%x, Pcs 0x%x, Pid 0x%x \n", \r
- l_pFileObject, l_pPcs, l_pPcs->m_Pid ));\r
-done:\r
- pi_pIrp->IoStatus.Status = l_Status;\r
- pi_pIrp->IoStatus.Information = 0;\r
-\r
-\r
- IoCompleteRequest (pi_pIrp,\r
- IO_NO_INCREMENT\r
- );\r
-\r
- MdDecrementIoCount(l_pMdDevContext); \r
-\r
- MdKdPrint( DBGLVL_HIGH,("exit MdCreate %x\n", l_Status));\r
-\r
-\r
- return l_Status;\r
-}\r
-\r
-BOOLEAN\r
-MdCancelPendingIo(\r
- IN PDEVICE_OBJECT DeviceObject\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- Cancels pending IO, as on a sudden IRP_MN_REMOVE_DEVICE \r
-\r
-Arguments:\r
-\r
- DeviceObject - pointer to the device object for this instance of the 82930\r
- device.\r
-\r
-\r
-Return Value:\r
-\r
- TRUE if cancelled any, else FALSE\r
-\r
---*/\r
-{\r
- return TRUE;\r
-}\r
-\r
-\r
-\r
-NTSTATUS\r
-MdAbortInPgsReqs(\r
- IN PDEVICE_OBJECT DeviceObject\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Called as part of sudden device removal handling.\r
- Cancels all in progress requests. \r
-\r
-Arguments:\r
-\r
- Ptrs to our FDO\r
-\r
-Return Value:\r
-\r
- NT status code\r
-\r
---*/\r
-{\r
- NTSTATUS ntStatus = STATUS_SUCCESS;\r
- return ntStatus;\r
-}\r
-\r
-\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#include "MdGen.h" \r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-VOID\r
-WriteEventLogEntry(\r
- PVOID pi_pIoObject,\r
- ULONG pi_ErrorCode,\r
- ULONG pi_UniqueErrorCode,\r
- ULONG pi_FinalStatus,\r
- ULONG pi_nDataItems,\r
- ...\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- Writes an event log entry to the event log.\r
-\r
-Arguments:\r
-\r
- pi_pIoObject......... The IO object ( driver object or device object ).\r
- pi_ErrorCode......... The error code.\r
- pi_UniqueErrorCode... A specific error code.\r
- pi_FinalStatus....... The final status.\r
- pi_nDataItems........ Number of data items.\r
- .\r
- . data items values\r
- .\r
-\r
-Return Value:\r
-\r
- None .\r
-\r
---*/\r
-{ /* WriteEventLogEntry */\r
-\r
- /* Variable argument list */ \r
- va_list l_Argptr;\r
- /* Pointer to an error log entry */\r
- PIO_ERROR_LOG_PACKET l_pErrorLogEntry; \r
-\r
- /* Init the variable argument list */ \r
- va_start(l_Argptr, pi_nDataItems);\r
-\r
- /* Allocate an error log entry */ \r
- l_pErrorLogEntry = \r
- (PIO_ERROR_LOG_PACKET)IoAllocateErrorLogEntry(\r
- pi_pIoObject,\r
- (UCHAR)(sizeof(IO_ERROR_LOG_PACKET)+pi_nDataItems*sizeof(ULONG))\r
- ); \r
- /* Check allocation */\r
- if ( l_pErrorLogEntry != NULL) \r
- { /* OK */\r
-\r
- /* Data item index */\r
- USHORT l_nDataItem ;\r
-\r
- /* Set the error log entry header */\r
- l_pErrorLogEntry->ErrorCode = pi_ErrorCode; \r
- l_pErrorLogEntry->DumpDataSize = (USHORT) (pi_nDataItems*sizeof(ULONG)); \r
- l_pErrorLogEntry->SequenceNumber = 0; \r
- l_pErrorLogEntry->MajorFunctionCode = 0; \r
- l_pErrorLogEntry->IoControlCode = 0; \r
- l_pErrorLogEntry->RetryCount = 0; \r
- l_pErrorLogEntry->UniqueErrorValue = pi_UniqueErrorCode; \r
- l_pErrorLogEntry->FinalStatus = pi_FinalStatus; \r
-\r
- /* Insert the data items */\r
- for (l_nDataItem = 0; l_nDataItem < pi_nDataItems; l_nDataItem++) \r
- { /* Inset a data item */\r
-\r
- /* Current data item */\r
- int l_CurDataItem ;\r
- \r
- /* Get next data item */\r
- l_CurDataItem = va_arg( l_Argptr, int);\r
-\r
- /* Put it into the data array */\r
- l_pErrorLogEntry->DumpData[l_nDataItem] = l_CurDataItem ;\r
-\r
- } /* Inset a data item */\r
-\r
- /* Write the packet */\r
- IoWriteErrorLogEntry(l_pErrorLogEntry);\r
-\r
- } /* OK */\r
-\r
- /* Term the variable argument list */ \r
- va_end(l_Argptr);\r
-\r
-} /* WriteEventLogEntry */\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-\r
-NTSTATUS\r
-MdAddDevice(\r
- IN PDRIVER_OBJECT pi_pDriverObject,\r
- IN PUNICODE_STRING pi_pNtDeviceName,\r
- IN PUNICODE_STRING pi_pWin32DeviceName,\r
- IN int pi_nExtSize,\r
- OUT PMD_DEV_CONTEXT_T * po_ppMdDevContext\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- This routine creates a device object, the symbolic link in \DosDevices and allocates device extension\r
-\r
- A symbolic link must be created between the device name and an entry\r
- in \DosDevices in order to allow Win32 applications to open the device.\r
-\r
-\r
-Arguments:\r
-\r
- pi_pDriverObject........ pointer to driver object\r
- pi_pNtDeviceName........ NT device name\r
- pi_pWin32DeviceName..... Win32 device name\r
- pi_nExtSize............. Device xontext size\r
- po_ppMdDevContext....... The device context\r
-\r
-Return Value:\r
-\r
- STATUS_SUCCESS if the device and link are created correctly, otherwise\r
- an error indicating the reason for failure.\r
-\r
---*/\r
-{ /* MdAddDevice */\r
-\r
- /* Status of utility calls */\r
- NTSTATUS l_Status;\r
- /* The address of the new created device object */\r
- PDEVICE_OBJECT l_pFdo = NULL;\r
- /* The Md device context ( l_pDeviceObject extension ) */\r
- PMD_DEV_CONTEXT_T l_pMdDevContext;\r
-\r
- \r
- /* Create a new device */\r
- l_Status = IoCreateDevice(\r
- pi_pDriverObject,\r
- pi_nExtSize,\r
- pi_pNtDeviceName,\r
- FILE_DEVICE_UNKNOWN,\r
- 0,\r
- FALSE, /* Not Exclusive */\r
- &l_pFdo\r
- );\r
-\r
- /* If device creation failed return the error code */\r
- if ( !NT_SUCCESS(l_Status) )\r
- { /* Device creation failed */\r
-\r
- /* Return error code */\r
- return l_Status;\r
-\r
- } /* Device creation failed */\r
-\r
- /*\r
- * Create the symbolic link.\r
- */\r
- l_Status = IoCreateSymbolicLink( pi_pWin32DeviceName, pi_pNtDeviceName );\r
-\r
- /*\r
- * If we we couldn't create the link then\r
- * abort installation... delete the created device\r
- */\r
- if ( !NT_SUCCESS( l_Status ) )\r
- { /* Create symbolic link failed */\r
-\r
- /* Delete the created device */\r
- IoDeleteDevice( l_pFdo );\r
-\r
- return l_Status;\r
-\r
- } /* Create symbolic link failed */\r
-\r
- /*\r
- * Set up the rest of the device info :\r
- */\r
-\r
- /* Use direct IO */\r
-\r
- /* These are used for IRP_MJ_READ and IRP_MJ_WRITE which. */\r
- l_pFdo->Flags |= DO_DIRECT_IO ;\r
- l_pFdo->Flags &= ~DO_DEVICE_INITIALIZING;\r
-\r
- /* Word alignment */\r
- l_pFdo->AlignmentRequirement = FILE_BYTE_ALIGNMENT;\r
-\r
- /*\r
- * Set up some device context fields\r
- */\r
-\r
- /* get device context */\r
- l_pMdDevContext = (PMD_DEV_CONTEXT_T)l_pFdo->DeviceExtension;\r
-\r
- /* zero the context */\r
- RtlZeroMemory(l_pFdo->DeviceExtension, pi_nExtSize);\r
-\r
- /* store handle to device */\r
- l_pMdDevContext->m_pFdo = l_pFdo;\r
-\r
- /* Copy the Win32 device name */\r
- #if 0\r
- UCopyString( &l_pMdDevContext->m_usDosDeviceName, pi_pWin32DeviceName, TRUE );\r
- MdExFreePool( pi_pWin32DeviceName->Buffer );\r
- #else\r
- l_pMdDevContext->m_usDosDeviceName.Length = pi_pWin32DeviceName->Length;\r
- l_pMdDevContext->m_usDosDeviceName.MaximumLength = pi_pWin32DeviceName->MaximumLength;\r
- l_pMdDevContext->m_usDosDeviceName.Buffer = pi_pWin32DeviceName->Buffer;\r
- #endif\r
- pi_pWin32DeviceName->Buffer = NULL;\r
-\r
- /* Copy the Nt device name */\r
- #if 0\r
- UCopyString( &l_pMdDevContext->m_usNtDeviceName, pi_pNtDeviceName, TRUE );\r
- MdExFreePool( pi_pNtDeviceName->Buffer );\r
- #else\r
- l_pMdDevContext->m_usNtDeviceName.Length = pi_pNtDeviceName->Length;\r
- l_pMdDevContext->m_usNtDeviceName.MaximumLength = pi_pNtDeviceName->MaximumLength;\r
- l_pMdDevContext->m_usNtDeviceName.Buffer = pi_pNtDeviceName->Buffer;\r
- #endif\r
- pi_pNtDeviceName->Buffer = NULL;\r
-\r
- /* store the result */\r
- *po_ppMdDevContext = l_pMdDevContext;\r
- \r
- return STATUS_SUCCESS;\r
-\r
-} /* MdAddDevice */\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-VOID\r
-MdDelDevice(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- This routine is called to remove the device.\r
-\r
-\r
-Arguments:\r
-\r
- pi_pMdDevContext...... The device context\r
-\r
-Return Value:\r
-\r
- STATUS_SUCCESS if the device and link are created correctly, otherwise\r
- an error indicating the reason for failure.\r
-\r
---*/\r
-{ /* MdDelDevice */\r
-\r
- /* Delete the symbolic link */\r
- IoDeleteSymbolicLink(&pi_pMdDevContext->m_usDosDeviceName);\r
-\r
- /* Free the DOS device names string buffer */\r
- if (pi_pMdDevContext->m_usDosDeviceName.Buffer != NULL)\r
- {\r
- PUSHORT l_pBuf = pi_pMdDevContext->m_usDosDeviceName.Buffer;\r
- pi_pMdDevContext->m_usDosDeviceName.Buffer = NULL;\r
- MdExFreePool( l_pBuf );\r
- }\r
-\r
- /* Free the NT device names string buffer */\r
- if (pi_pMdDevContext->m_usNtDeviceName.Buffer != NULL)\r
- {\r
- PUSHORT l_pBuf = pi_pMdDevContext->m_usNtDeviceName.Buffer;\r
- pi_pMdDevContext->m_usNtDeviceName.Buffer = NULL;\r
- MdExFreePool( l_pBuf );\r
- }\r
-\r
- /* Delete the created device */\r
- if (pi_pMdDevContext->m_pFdo)\r
- {\r
- PDEVICE_OBJECT l_pFdo = pi_pMdDevContext->m_pFdo;\r
- pi_pMdDevContext->m_pFdo = NULL;\r
- IoDeleteDevice( l_pFdo );\r
- }\r
-\r
-} /* MdDelDevice */\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-static void GetRegistryDword(\r
- IN PWCHAR pi_ParamName,\r
- IN ULONG pi_DfltValue,\r
- OUT PLONG po_Result\r
-) \r
-{\r
- ULONG l_uValue = 0;\r
- \r
- // read parameter the registry\r
- MdGetRegistryDword( MD_REGISTRY_PARAMETERS_PATH, //absolute registry path\r
- pi_ParamName, // REG_DWORD ValueName\r
- &l_uValue ); // Value receiver\r
- \r
- if (!l_uValue)\r
- { /* no Registry value - set default */\r
- *po_Result = pi_DfltValue;\r
- } /* no Registry value - set default */\r
- else\r
- { /* store Registry value */\r
- *po_Result = l_uValue;\r
- } /* store Registry value */\r
-}\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-NTSTATUS\r
-MdCreateDevContext(\r
- IN PDRIVER_OBJECT pi_pDriverObject,\r
- IN MD_DEV_IX_E pi_eDevType,\r
- IN PUNICODE_STRING pi_pNtDeviceName,\r
- IN PUNICODE_STRING pi_pWin32DeviceName,\r
- IN OUT PVOID* pio_ppDevContext\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- This routine creates the device extension\r
-\r
-\r
-Arguments:\r
-\r
- pi_pDriverObject........ pointer to driver object\r
- pi_eDevType............. The device type.\r
- pi_pNtDeviceName........ The \Device\????\ name\r
- pi_pWin32DeviceName..... The \DosDevices\????\ name\r
- pio_ppDevContext........ Pointer to created device context.\r
-\r
-Return Value:\r
-\r
- STATUS_SUCCESS if the device extension was created correctly, otherwise\r
- an error indicating the reason for failure.\r
-\r
---*/\r
-{ /* MdCreateDevContext */\r
-\r
- /* Status of utility calls */\r
- NTSTATUS l_Status = STATUS_SUCCESS;\r
- /* The Md device context ( l_pDeviceObject extension ) */\r
- PMD_DEV_CONTEXT_T l_pMdDevContext;\r
-\r
- /*\r
- * Initialize the device context with the template device context\r
- */\r
-\r
- /* Create the device */\r
- l_Status = MdAddDevice(\r
- pi_pDriverObject,\r
- pi_pNtDeviceName,\r
- pi_pWin32DeviceName,\r
- sizeof(MD_DEV_CONTEXT_T),\r
- &l_pMdDevContext\r
- );\r
-\r
- /* Check if device create ok */\r
- if ( !NT_SUCCESS(l_Status) )\r
- { /* Device creation failed */\r
-\r
- /* Set the device context to 0 */\r
- *pio_ppDevContext = NULL;\r
-\r
- /* Return error code */\r
- return l_Status;\r
-\r
- } /* Device creation failed */\r
-\r
- /* Save device type/channel */\r
- l_pMdDevContext->m_eDevType = pi_eDevType;\r
-\r
- /*\r
- * Init the rest fields of the driver context\r
- */ \r
-\r
- /* spinlock */\r
- INIT_LOCK_IT( &l_pMdDevContext->m_SpinLock );\r
-\r
- // spinlock used to protect inc/dec iocount logic\r
- KeInitializeSpinLock (&l_pMdDevContext->m_IoCntSpinLock);\r
-\r
- // init events\r
- KeInitializeEvent(&l_pMdDevContext->m_RemoveEvent, NotificationEvent, FALSE);\r
- KeInitializeEvent(&l_pMdDevContext->m_NoPendingIoEvent, NotificationEvent, FALSE);\r
- KeSetEvent(&l_pMdDevContext->m_NoPendingIoEvent, 1, FALSE);\r
-\r
- // init queue header\r
- InitializeListHead( &l_pMdDevContext->m_PcsQue );\r
- \r
- // init semaphore\r
- KSEM_INIT( &l_pMdDevContext->m_Sem );\r
- \r
- // init mutex\r
- KMUTEX_INIT( &l_pMdDevContext->m_Mutex );\r
- \r
- // set flag\r
- l_pMdDevContext->m_fDeletePending = FALSE;\r
-\r
- switch (l_pMdDevContext->m_eDevType) \r
- { /* device-specific init */\r
-\r
- case MD_DEV_IX_TAVOR_BD:\r
- GetRegistryDword( L"ConfAddr", MD_DFLT_CONF_ADDR, &l_pMdDevContext->m_ulAddrOffset );\r
- GetRegistryDword( L"ConfData", MD_DFLT_CONF_DATA, &l_pMdDevContext->m_ulDataOffset );\r
- l_pMdDevContext->m_nPendingIoCnt = 0;\r
- break;\r
- \r
- case MD_DEV_IX_TAVOR_SD:\r
- GetRegistryDword( L"ConfAddr", MD_DFLT_CONF_ADDR, &l_pMdDevContext->m_ulAddrOffset );\r
- GetRegistryDword( L"ConfData", MD_DFLT_CONF_DATA, &l_pMdDevContext->m_ulDataOffset );\r
- GetRegistryDword( L"DdrMapOffset", MD_DFLT_CONF_DATA, &l_pMdDevContext->m_ulDdrMapOffset );\r
- GetRegistryDword( L"DdrMapSize", MD_DFLT_CONF_DATA, &l_pMdDevContext->m_ulDdrMapSize );\r
- l_pMdDevContext->m_nPendingIoCnt = 0;\r
- break;\r
-\r
- case MD_DEV_IX_TAVOR:\r
- case MD_DEV_IX_ARBEL_TM:\r
- GetRegistryDword( L"DdrMapOffset", MD_DFLT_CONF_DATA, &l_pMdDevContext->m_ulDdrMapOffset );\r
- GetRegistryDword( L"DdrMapSize", MD_DFLT_CONF_DATA, &l_pMdDevContext->m_ulDdrMapSize );\r
- GetRegistryDword( L"ResetCard", MD_DFLT_CONF_DATA, &l_pMdDevContext->m_PerformReset );\r
- l_pMdDevContext->m_nPendingIoCnt = 0;\r
- l_pMdDevContext->m_hHhHca = NULL;\r
- break;\r
- \r
- case MD_DEV_IX_CTRL:\r
- { /* specific Control device initialization */\r
- /* pending IO requests: setting 1 here for "adding" the Control device ('cause OS won't call to AddDevice) */\r
- l_pMdDevContext->m_nPendingIoCnt = 1;\r
-\r
- /* Device open counter */\r
- l_pMdDevContext->m_nOpenCount = 0;\r
- \r
- // mark device started\r
- l_pMdDevContext->m_DeviceStarted = TRUE;\r
- \r
- break;\r
- } /* specific Control device initialization */\r
-\r
- } /* device-specific init */\r
-\r
- /* Return the new created extension */\r
- *pio_ppDevContext = l_pMdDevContext;\r
-\r
- return l_Status;\r
-\r
-} /* MdCreateDevContext */\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-NTSTATUS\r
-MdRemoveDevContext (\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- This routine releases the device context resources and remove the device\r
-\r
-\r
-Arguments:\r
-\r
- pi_pMdDevContext........ Pointer to the device context.\r
-\r
-Return Value:\r
-\r
- STATUS_SUCCESS if the device extension was created correctly, otherwise\r
- an error indicating the reason for failure.\r
-\r
---*/\r
-{ /* MdRemoveDevContext */\r
-\r
- \r
- if (pi_pMdDevContext != NULL)\r
- {\r
- /* close direct PCI interface */\r
- if (pi_pMdDevContext->m_eDevType != MD_DEV_IX_CTRL)\r
- PciIfClose( &pi_pMdDevContext->m_Interface );\r
- \r
- /* Remove the device */\r
- MdDelDevice( pi_pMdDevContext );\r
- \r
- /* remove device context */\r
- /* NO NEED, BECAUSE IT WAS RELEASED ON IoDeleteDevice() ! \r
- MdExFreePool( pi_pMdDevContext );\r
- */\r
- }\r
-\r
- return STATUS_SUCCESS;\r
-\r
-} /* MdRemoveDevContext */\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-NTSTATUS \r
-MdDevInit(\r
- IN PMD_DRV_CONTEXT_T pi_pDrvContext,\r
- IN MD_DEV_IX_E pi_eDevType,\r
- IN PUNICODE_STRING pi_pNtDeviceName,\r
- IN PUNICODE_STRING pi_pWin32DeviceName,\r
- IN OUT PVOID* pio_ppDevContext\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- This routine creates the device and connect to the driver context\r
-\r
-\r
-Arguments:\r
-\r
- pi_pDrvContext.......... Driver context\r
- pi_eDevType............. Device type.\r
- pi_pNtDeviceName........ The \Device\????\ name\r
- pi_pWin32DeviceName..... The \DosDevices\????\ name\r
- pio_ppDevContext........ The device extension ofthe created object\r
-\r
-Return Value:\r
-\r
- STATUS_SUCCESS on success, otherwise an error indicating the reason for failure.\r
-\r
---*/\r
-{ /* MdDevInit */\r
-\r
- /* Local status variable */\r
- NTSTATUS l_Status;\r
- /* Default debug ON/OFF flag */\r
- ULONG l_nDfltDebugPrintLevel = FALSE ;\r
- /* Device context */\r
- PMD_DEV_CONTEXT_T l_pMdDevContext;\r
-\r
- MdKdPrint( DBGLVL_MINIMUM ,("(MdDevInit) init device '%ws'\n", pi_pWin32DeviceName->Buffer ));\r
-\r
- /*\r
- * Create the device and the device context\r
- */\r
- l_Status = MdCreateDevContext(\r
- pi_pDrvContext->m_pDrvObject,\r
- pi_eDevType,\r
- pi_pNtDeviceName,\r
- pi_pWin32DeviceName,\r
- &l_pMdDevContext\r
- );\r
-\r
- /* Check creation status */\r
- if ( NT_SUCCESS(l_Status) )\r
- { /* Loaded OK */\r
- PRE_LOCK_IT;\r
-\r
- MdKdPrint( DBGLVL_DEFAULT ,("(MdDeviceInit) Device successfuly initialized\n"));\r
-\r
- /* Store the device context */\r
- *pio_ppDevContext = l_pMdDevContext;\r
-\r
- /* Add the device context to the driver list */\r
- LOCK_IT( &pi_pDrvContext->m_SpinLock);\r
- InsertTailList( &pi_pDrvContext->m_DevQue, &l_pMdDevContext->m_Link );\r
- UNLOCK_IT( &pi_pDrvContext->m_SpinLock);\r
- \r
- /* connect device to driver */\r
- l_pMdDevContext->m_pDrvContext = pi_pDrvContext;\r
-\r
- /* Update number of device instances */\r
- InterlockedIncrement( &pi_pDrvContext->m_uDevNo );\r
-\r
- // increment the number of cards\r
- {\r
- int l_ix = (int)l_pMdDevContext->m_eDevType;\r
- PMD_HAL_DEV_PARAMS_T l_pDev = &g_DevParams[l_ix];\r
- if (l_pDev->m_fExpose)\r
- InterlockedIncrement( &g_pDrvContext->m_uCardNo );\r
- }\r
- } /* Loaded OK */\r
-\r
- return l_Status ;\r
-\r
-} /* MdDevInit */\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-void\r
-ReleasePendingRequests(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Release pending requests of the Control Device \r
-\r
-Arguments:\r
-\r
- pi_pMdDevContext - pointer to the Control Device\r
-\r
-Return Value:\r
-\r
---*/\r
-{ /* ReleasePendingRequests */\r
- MdKdPrint( DBGLVL_MINIMUM ,("(ReleasePendingRequests) Enter \n" ));\r
-} /* ReleasePendingRequests */\r
-\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-NTSTATUS \r
-MdDevDeInit(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext \r
- )\r
-/*++\r
-\r
-Routine Description:\r
- This routine DeInitialize the device setting and context\r
-\r
-\r
-Arguments:\r
-\r
- pi_pMdDevContext........The device context\r
-Return Value:\r
-\r
- None.\r
-\r
---*/\r
-{ /* MdDevDeInit */\r
- /* Current device object */\r
- PDEVICE_OBJECT l_pFdo ;\r
- /* The Driver context */\r
- PMD_DRV_CONTEXT_T l_pMdDrvContext;\r
- // prepare lock\r
- PRE_LOCK_IT;\r
-\r
- MdKdPrint( DBGLVL_MINIMUM ,("(MdDevDeInit) Unloading device '%ws' \n", pi_pMdDevContext->m_usDosDeviceName.Buffer));\r
-\r
- /* Parameter validation*/\r
- if ( pi_pMdDevContext == NULL )\r
- { /* no device context */\r
- return STATUS_UNSUCCESSFUL;\r
- } /* no device context */\r
-\r
- /* Get the first device object */\r
- l_pFdo = pi_pMdDevContext->m_pFdo;\r
-\r
- /* Check if driver has any device */\r
- if ( l_pFdo == NULL ) \r
- { /* no NT device object */\r
- return STATUS_UNSUCCESSFUL;\r
- } /* no NT device object */\r
-\r
- /* get driver context */\r
- l_pMdDrvContext = pi_pMdDevContext->m_pDrvContext;\r
-\r
- /*\r
- * Remove the device from the Driver device list\r
- */\r
-\r
- // acquire access to the critical section\r
- LOCK_IT( &pi_pMdDevContext->m_SpinLock );\r
-\r
- // disconnect the global context with device one\r
- RemoveEntryList( &pi_pMdDevContext->m_Link );\r
-\r
- // release access to the critical section\r
- UNLOCK_IT( &pi_pMdDevContext->m_SpinLock );\r
-\r
- // decrement the number of created devices\r
- LOCK_IT( &l_pMdDrvContext->m_SpinLock);\r
- if ( l_pMdDrvContext->m_uDevNo > 0)\r
- InterlockedDecrement( &l_pMdDrvContext->m_uDevNo );\r
- UNLOCK_IT( &l_pMdDrvContext->m_SpinLock);\r
-\r
- // decrement the number of cards\r
- {\r
- int l_ix = (int)pi_pMdDevContext->m_eDevType;\r
- PMD_HAL_DEV_PARAMS_T l_pDev = &g_DevParams[l_ix];\r
- if (l_pDev->m_fExpose && l_pMdDrvContext->m_uCardNo > 0)\r
- InterlockedDecrement( &l_pMdDrvContext->m_uCardNo );\r
- }\r
- /* Free the Device context */\r
- return MdRemoveDevContext( pi_pMdDevContext );\r
-\r
-} /* MdDevDeInit */\r
-\r
-NTSTATUS \r
-MdGetDevLocation(\r
- IN PDEVICE_OBJECT pi_pPdo,\r
- IN ULONG * pi_pBus,\r
- IN ULONG * pi_pSlot,\r
- IN ULONG * pi_pFunction\r
- )\r
-{\r
- ULONG l_BusNumber, l_DevNumber, l_Function, l_ResultLength = 0;\r
- WCHAR l_Buffer[40], *l_pEnd, *l_pBuf = l_Buffer, *l_pBufEnd = l_Buffer + sizeof(l_Buffer);\r
- NTSTATUS l_Status;\r
- UNICODE_STRING l_UnicodeNumber;\r
-\r
- /* prepare */\r
- l_ResultLength = 0;\r
- RtlZeroMemory( l_Buffer, sizeof(l_Buffer) );\r
-\r
- /* Get the device number */\r
- l_Status = IoGetDeviceProperty(pi_pPdo,\r
- DevicePropertyLocationInformation, sizeof(l_Buffer), &l_Buffer, &l_ResultLength);\r
-\r
- /* Verify if the function was successful */\r
- if ( !NT_SUCCESS(l_Status) || !l_ResultLength ) {\r
- MdKdPrint( DBGLVL_DEFAULT ,("(MdInitPciCfgCard) Unable to get device number: Status 0x%x, ResultSize %d \n", \r
- l_Status, l_ResultLength ));\r
- goto exit; \r
- }\r
-\r
- // ALL THE BELOW CRAP WE DO INSTEAD OF \r
- // sscanf(l_Buffer, "PCI bus %d, device %d, function %d", &l_BusNumber, &l_DevNumber, &l_Function );\r
-\r
- /* take bus number */\r
- l_pBuf = WcharFindChar( l_pBuf, l_pBufEnd, L'0', L'9' );\r
- if (l_pBuf == NULL) goto err;\r
- l_pEnd = WcharFindChar( l_pBuf, l_pBufEnd, L',', L',' );\r
- if (l_pEnd == NULL) goto err;\r
- l_UnicodeNumber.Length = l_UnicodeNumber.MaximumLength = (USHORT)((PCHAR)l_pEnd - (PCHAR)l_pBuf);\r
- l_UnicodeNumber.Buffer = l_pBuf; l_pBuf = l_pEnd;\r
- RtlUnicodeStringToInteger( &l_UnicodeNumber, 10, &l_BusNumber);\r
-\r
- /* take slot number */\r
- l_pBuf = WcharFindChar( l_pBuf, l_pBufEnd, L'0', L'9' );\r
- if (l_pBuf == NULL) goto err;\r
- l_pEnd = WcharFindChar( l_pBuf, l_pBufEnd, L',', L',' );\r
- if (l_pEnd == NULL) goto err;\r
- l_UnicodeNumber.Length = l_UnicodeNumber.MaximumLength = (USHORT)((PCHAR)l_pEnd - (PCHAR)l_pBuf);\r
- l_UnicodeNumber.Buffer = l_pBuf; l_pBuf = l_pEnd;\r
- RtlUnicodeStringToInteger( &l_UnicodeNumber, 10, &l_DevNumber);\r
-\r
- /* take function number */\r
- *(l_Buffer + (l_ResultLength>>1)) = 0; /* set end of string */\r
- l_pBuf = WcharFindChar( l_pBuf, l_pBufEnd, L'0', L'9' );\r
- if (l_pBuf == NULL) goto err;\r
- l_pEnd = WcharFindChar( l_pBuf, l_pBufEnd, 0, 0 );\r
- if (l_pEnd == NULL) goto err;\r
- l_UnicodeNumber.Length = l_UnicodeNumber.MaximumLength = (USHORT)((PCHAR)l_pEnd - (PCHAR)l_pBuf);\r
- l_UnicodeNumber.Buffer = l_pBuf; l_pBuf = l_pEnd;\r
- RtlUnicodeStringToInteger( &l_UnicodeNumber, 10, &l_Function);\r
-\r
- /* return the results */\r
- *pi_pBus = l_BusNumber;\r
- *pi_pSlot = l_DevNumber;\r
- *pi_pFunction = l_Function;\r
- \r
- goto exit;\r
-\r
-err:\r
- l_Status = STATUS_UNSUCCESSFUL;\r
-exit:\r
- return l_Status;\r
-}\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-NTSTATUS \r
-MdInitPciCfgCard(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext,\r
- IN PCM_RESOURCE_LIST pi_pRawResources,\r
- IN PCM_RESOURCE_LIST pi_pTranslatedResources\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This routine prepares the Driver to the work with a PCI card:\r
- - gets card resources from IRP;\r
- - store them on the device context;\r
- - translate physical address into virtual;\r
- - connect interrupt;\r
-\r
-Arguments:\r
-\r
- pi_pMdDevContext....... My device context\r
- pi_pRawResources....... Card raw resources\r
- pi_pTranslatedResources Card translated resources\r
-\r
-Return Value:\r
-\r
- None.\r
-\r
---*/\r
-{ /* MdInitPciCfgCard */\r
-\r
- /* full resource descriptor */\r
- PCM_FULL_RESOURCE_DESCRIPTOR l_pFullResDesc;\r
- /* partial resource list */\r
- PCM_PARTIAL_RESOURCE_LIST l_pPartResList;\r
- /* partial resource descriptor */\r
- PCM_PARTIAL_RESOURCE_DESCRIPTOR l_pPartResDesc;\r
- /* number of resources */\r
- ULONG l_nResCnt;\r
- /* current resource number */\r
- ULONG l_nCurResNum;\r
- /* temporary address */\r
- PUCHAR l_pPortAddr = NULL;\r
- /* status */\r
- NTSTATUS l_Status;\r
- // Device IX (in PCI configuration) \r
- MD_DEV_IX_E l_DevIx = pi_pMdDevContext->m_eDevType; \r
- // Device BD\r
- PMD_HAL_DEV_PARAMS_T l_pDev = &g_DevParams[l_DevIx];\r
- // current BAR descriptor \r
- PMD_BAR_T l_pBar; \r
- // for Debug \r
- char * l_BarName; \r
- \r
- MdKdPrint( DBGLVL_DEFAULT ,("(MdInitPciCfgCard) Enter \n" ));\r
-\r
- /* zero the fields */\r
-#define ZEROF(field) pi_pMdDevContext->field = 0;\r
- ZEROF(m_BusNumber);\r
- ZEROF(m_DevNumber);\r
- ZEROF(m_Function);\r
- ZEROF(m_ulIntVector);\r
- ZEROF(m_ulIntLevel);\r
- ZEROF(m_Affinity);\r
- ZEROF(m_fIntShared);\r
- ZEROF(m_IntMode);\r
- RtlZeroMemory( (void*)&pi_pMdDevContext->m_Cr, sizeof(MD_BAR_T));\r
- RtlZeroMemory( (void*)&pi_pMdDevContext->m_Uar, sizeof(MD_BAR_T));\r
- RtlZeroMemory( (void*)&pi_pMdDevContext->m_Ddr, sizeof(MD_BAR_T));\r
-\r
- if (l_DevIx == MD_DEV_IX_TAVOR_SD)\r
- { /* get BARs via PCI configuration header */\r
-\r
- l_Status = ReadBars( pi_pMdDevContext ); \r
- if (!NT_SUCCESS(l_Status))\r
- return l_Status;\r
-\r
- } /* get BARs via PCI configuration header */\r
- \r
- else\r
- { /* get resources from resource descriptors */\r
- \r
- /* validate parameters */\r
- if (pi_pTranslatedResources == NULL) {\r
- MdKdPrint( DBGLVL_LOW ,("(MdInitPciCfgCard) No resources ! \n" ));\r
- return STATUS_SUCCESS;\r
- }\r
- \r
- /* prepare for getting resources */\r
- l_pFullResDesc = &pi_pTranslatedResources->List[0];\r
- l_pPartResList = &l_pFullResDesc->PartialResourceList;\r
- l_pPartResDesc = &l_pPartResList->PartialDescriptors[0];\r
- l_nResCnt = l_pPartResList->Count;\r
-\r
- /* store other parameters */\r
- for (l_nCurResNum = 0; l_nCurResNum < l_nResCnt; ++l_nCurResNum, ++l_pPartResDesc)\r
- {\r
- switch (l_pPartResDesc->Type)\r
- {\r
- case CmResourceTypeBusNumber:\r
- /* Store IB card bus number */\r
- //MDASSERT( pi_pMdDevContext->m_ulBusNumber == l_pPartResDesc->u.BusNumber.Start );\r
- pi_pMdDevContext->m_BusNumber = l_pPartResDesc->u.BusNumber.Start;\r
- break;\r
-\r
- case CmResourceTypeInterrupt:\r
- pi_pMdDevContext->m_ulIntVector = l_pPartResDesc->u.Interrupt.Vector;\r
- pi_pMdDevContext->m_ulIntLevel = (KIRQL)l_pPartResDesc->u.Interrupt.Level;\r
- pi_pMdDevContext->m_Affinity = (KAFFINITY)l_pPartResDesc->u.Interrupt.Affinity;\r
- pi_pMdDevContext->m_fIntShared = l_pPartResDesc->ShareDisposition == CmResourceShareShared;\r
- pi_pMdDevContext->m_IntMode = (l_pPartResDesc->Flags == CM_RESOURCE_INTERRUPT_LATCHED) ? Latched : LevelSensitive;\r
- MdKdPrint( DBGLVL_LOW ,("(MdInitPciCfgCard) Dev %d Interrupt: Vector %d, Level %d, Affinity %d, Shared %d, Mode %d\n", \r
- l_pDev->m_DevId, pi_pMdDevContext->m_ulIntVector, pi_pMdDevContext->m_ulIntLevel, \r
- pi_pMdDevContext->m_Affinity, pi_pMdDevContext->m_fIntShared, pi_pMdDevContext->m_IntMode ));\r
- break;\r
- \r
- case CmResourceTypeMemory:\r
- {\r
- ULONG l_BarNum;\r
- LARGE_INTEGER l_Offset = { 0,0 };\r
- \r
- /* decide, what BAR is it about */\r
- if (l_pDev->m_SizeBar0 >= l_pPartResDesc->u.Memory.Length) {\r
- l_pBar = &pi_pMdDevContext->m_Cr; l_BarName = "CR"; l_BarNum = 0; }\r
- else \r
- if (l_pDev->m_SizeBar1 >= l_pPartResDesc->u.Memory.Length) {\r
- l_pBar = &pi_pMdDevContext->m_Uar; l_BarName = "UAR"; l_BarNum = 1; }\r
- else {\r
- l_pBar = &pi_pMdDevContext->m_Ddr; l_BarName = "DDR"; l_BarNum = 2; }\r
- \r
- /* store BAR parameters */\r
- l_pBar->m_MemPhysAddr = l_pPartResDesc->u.Memory.Start;\r
- l_pBar->m_ulMemSize = l_pPartResDesc->u.Memory.Length;\r
- l_pBar->m_usMemFlags = l_pPartResDesc->Flags;\r
- l_pBar->m_ulKernelSize = l_pBar->m_ulMemSize;\r
- l_pBar->m_ulKernelOffset = 0;\r
- \r
- /* recalculate boundaries of mapped mempry for DDR */\r
- if (l_BarNum == 2 && pi_pMdDevContext->m_ulDdrMapSize != -1) {\r
- l_pBar->m_ulKernelSize = pi_pMdDevContext->m_ulDdrMapSize;\r
- l_pBar->m_ulKernelOffset = pi_pMdDevContext->m_ulDdrMapOffset;\r
- l_Offset.LowPart = pi_pMdDevContext->m_ulDdrMapOffset;\r
- } /* for DDR - map some subset of memory */\r
- \r
- /* map physical address into virtual kernel one */\r
- if (l_pBar->m_ulKernelSize) {\r
- l_Offset.QuadPart += l_pBar->m_MemPhysAddr.QuadPart;\r
- l_pBar->m_pKernelAddr = (PUCHAR) MmMapIoSpace(\r
- l_Offset, \r
- l_pBar->m_ulKernelSize, MmNonCached);\r
- }\r
- if (!l_pBar->m_pKernelAddr) return STATUS_NO_MEMORY;\r
- \r
- /* debug print */\r
- MdKdPrint( DBGLVL_LOW ,("(MdInitPciCfgCard) Dev %d %s: Phys 0x%I64x Size 0x%x, Virt 0x%x Size 0x%x \n", \r
- l_pDev->m_DevId, l_BarName, l_pBar->m_MemPhysAddr, l_pBar->m_ulMemSize, \r
- l_pBar->m_pKernelAddr, l_pBar->m_ulKernelSize ));\r
- } \r
- break;\r
- \r
- default:\r
- MdKdPrint( DBGLVL_DEFAULT ,("(MdInitPciCfgCard) Unsupported resource type 0x%x \n", l_pPartResDesc->Type ));\r
- break;\r
- }\r
- }\r
-\r
- } /* get resources from resource descriptors */\r
- \r
- //\r
- // get the device location information\r
- //\r
- { \r
- ULONG l_BusNumber, l_DevNumber, l_Function;\r
- \r
- l_Status = MdGetDevLocation( pi_pMdDevContext->m_pPdo, &l_BusNumber, &l_DevNumber, &l_Function );\r
-\r
- if ( !NT_SUCCESS(l_Status) )\r
- { // fill default values \r
- l_BusNumber = g_pDrvContext->m_uDevNo;\r
- l_DevNumber = g_pDrvContext->m_uDevNo;\r
- l_Function = 0;\r
- }\r
-\r
- /* store the slot number */\r
- pi_pMdDevContext->m_BusNumber = l_BusNumber;\r
- pi_pMdDevContext->m_DevNumber = l_DevNumber;\r
- pi_pMdDevContext->m_Function = l_Function;\r
-\r
- MdKdPrint( DBGLVL_LOW ,("(MdInitPciCfgCard) Dev %d location is %d:%d:%d) \n", \r
- l_pDev->m_DevId, l_BusNumber, l_DevNumber, l_Function ));\r
- }\r
-\r
-\r
- return STATUS_SUCCESS;\r
-\r
-} /* MdInitPciCfgCard */\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-VOID \r
-MdDeInitPciCfgCard(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This routine releases OS resources, allocaetd for the work with a PCI card:\r
- - disconnect the interrupt;\r
- - unmap virtual address of the CR-space;\r
-\r
-\r
-Arguments:\r
-\r
- pi_pMdDevContext....... My device context\r
-\r
-Return Value:\r
-\r
- None.\r
-\r
---*/\r
-{ /* MdDeInitPciCfgCard */\r
-\r
- // current BAR descriptor \r
- PMD_BAR_T l_pBar; \r
- // CR space address \r
- PUCHAR l_pAddr;\r
-\r
- // unmap CR-space\r
- l_pBar = &pi_pMdDevContext->m_Cr;\r
- l_pAddr = l_pBar->m_pKernelAddr;\r
- l_pBar->m_pKernelAddr = NULL;\r
- if (l_pAddr)\r
- MmUnmapIoSpace(l_pAddr, l_pBar->m_ulKernelSize);\r
-\r
- // unmap UAR-space\r
- l_pBar = &pi_pMdDevContext->m_Uar;\r
- l_pAddr = l_pBar->m_pKernelAddr;\r
- l_pBar->m_pKernelAddr = NULL;\r
- if (l_pAddr)\r
- MmUnmapIoSpace(l_pAddr, l_pBar->m_ulKernelSize);\r
-\r
- // unmap DDR-space\r
- l_pBar = &pi_pMdDevContext->m_Ddr;\r
- l_pAddr = l_pBar->m_pKernelAddr;\r
- l_pBar->m_pKernelAddr = NULL;\r
- if (l_pAddr)\r
- MmUnmapIoSpace(l_pAddr, l_pBar->m_ulKernelSize);\r
-\r
-} /* MdDeInitPciCfgCard */\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-PCHAR\r
-WcharToAscii(\r
- OUT PUCHAR pi_TargetString,\r
- IN const USHORT * pi_SourceString,\r
- IN ULONG pi_Size\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- Converts wide-character string into ASCII\r
-\r
-Arguments:\r
-\r
- pi_TargetString...... result string\r
- pi_SourceString...... source string\r
- pi_Size.............. size of the source string\r
-\r
-Return Value:\r
-\r
- The result stringbytes.\r
-\r
---*/\r
-{ /* WcharToAscii */\r
- int i, size = (pi_Size + 1) >> 1;\r
- PCHAR l_pResult = pi_TargetString;\r
-\r
- for (i=0; i<size; i++)\r
- {\r
- if (*pi_SourceString == 0)\r
- break;\r
- *l_pResult++ = (char)*pi_SourceString++;\r
- }\r
- *l_pResult = '\0';\r
-\r
- return pi_TargetString;\r
-\r
-} /* WcharToAscii */\r
-\r
-PWCHAR \r
-WcharFindChar(\r
- IN PWCHAR pi_BufStart,\r
- IN PWCHAR pi_BufEnd,\r
- IN WCHAR pi_FromPattern,\r
- IN WCHAR pi_ToPattern\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- Converts wide-character string into ASCII\r
-\r
-Arguments:\r
-\r
- pi_BufStart.......... start of the source string\r
- pi_BufEnd............ end of the source string\r
- pi_FromPattern....... start of pattern range to find\r
- pi_ToPattern......... end of pattern range to find\r
-\r
-Return Value:\r
-\r
- pointer to the first pattern found or NULL (when reached the end)\r
-\r
---*/\r
-{ /* WcharFindChar */\r
-\r
- PWCHAR l_pResult = pi_BufStart;\r
-\r
- while (l_pResult < pi_BufEnd )\r
- {\r
- if (*l_pResult >= pi_FromPattern && *l_pResult <= pi_ToPattern)\r
- return l_pResult;\r
- l_pResult++;\r
- }\r
-\r
- return NULL;\r
-\r
-} /* WcharFindChar */\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-USHORT \r
-AsciiToUnicode(\r
- PUNICODE_STRING pi_puTargetString,\r
- PUCHAR pi_szFormat,\r
- ...\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- Writes a formatted ( printf like ) string to into a uniocde string.\r
-\r
-Arguments:\r
-\r
- pi_nDbgLogLevel...... Level of debugging log.\r
- pi_szFormat.......... The format of the log.\r
-\r
-Return Value:\r
-\r
- The formatted string length in bytes.\r
-\r
---*/\r
-{ /* AsciiToUnicode */\r
-\r
- /* Auxilary scratch buffer */\r
- static UCHAR s_vScratchBuff[1024];\r
-\r
- /* Variable argument list */ \r
- va_list l_Argptr;\r
- /* Length of the formated string in bytes */\r
- int l_nStrLenBytes ;\r
- /* Char index */\r
- USHORT l_nCharNo ;\r
- /* Maximum lemgth */\r
- USHORT l_nMaxLength;\r
-\r
- /* Init the variable argument list */ \r
- va_start(l_Argptr, pi_szFormat);\r
-\r
- /* Build the formatted string */\r
- l_nStrLenBytes = vsprintf(&s_vScratchBuff[0] , pi_szFormat , l_Argptr);\r
-\r
- /* Check if we need to allocate buffer */\r
- if ( pi_puTargetString->Buffer == NULL )\r
- { /* Need to allocate buffer */\r
-\r
- /* Allocate the UNICODE string buffer */\r
- pi_puTargetString->Buffer = \r
- (PWCHAR)MdExAllocatePool(NonPagedPool,(l_nStrLenBytes+1)*sizeof(WCHAR));\r
-\r
- /* If allocation failed return */\r
- if ( pi_puTargetString->Buffer == NULL ) return 0;\r
-\r
- /* Set the UNICODE string new parameters */\r
- pi_puTargetString->MaximumLength = (USHORT)((l_nStrLenBytes+1)*sizeof(WCHAR)) ;\r
-\r
- } /* Need to allocate buffer */\r
-\r
- /* Reset the string actual length */\r
- pi_puTargetString->Length = 0;\r
-\r
- /* Calc max length */\r
- l_nMaxLength = MT_MIN((pi_puTargetString->MaximumLength/sizeof(WCHAR) - 1),(USHORT)l_nStrLenBytes);\r
-\r
- /* Convert to UNICODE */\r
- for ( l_nCharNo=0; l_nCharNo<l_nMaxLength; l_nCharNo++ )\r
- { /* Convert a CHAR to WCHAR */\r
-\r
- /* Convert... */\r
- pi_puTargetString->Buffer[ l_nCharNo ] = (WCHAR)s_vScratchBuff[l_nCharNo] ;\r
-\r
- /* Update actual length */\r
- pi_puTargetString->Length += sizeof(WCHAR) ;\r
-\r
- } /* Convert a CHAR to WCHAR */\r
-\r
- /* NULL terminate */\r
- pi_puTargetString->Buffer[ l_nCharNo ] = (WCHAR)'\0';\r
-\r
- /* Term the variable argument list */ \r
- va_end(l_Argptr);\r
-\r
- return pi_puTargetString->Length ;\r
-\r
-} /* AsciiToUnicode */\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-BOOLEAN\r
-MdCanAcceptIoRequests(\r
- IN PDEVICE_OBJECT DeviceObject\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Check device extension status flags; \r
-\r
- Can't accept a new io request if device:\r
- 1) is removed, \r
- 2) has never been started, \r
- 3) is stopped,\r
- 4) has a remove request pending, or\r
- 5) has a stop device pending\r
-\r
-\r
-Arguments:\r
-\r
- DeviceObject - pointer to the device object for this instance of the 82930\r
- device.\r
-\r
-\r
-Return Value:\r
-\r
- return TRUE if can accept new io requests, else FALSE\r
-\r
---*/\r
-{\r
- PMD_DEV_CONTEXT_T l_pMdDevContext = (PMD_DEV_CONTEXT_T)DeviceObject->DeviceExtension;\r
- BOOLEAN l_fCan = FALSE;\r
-\r
-\r
- //flag set when processing IRP_MN_REMOVE_DEVICE\r
- if ( !l_pMdDevContext->m_DeviceRemoved &&\r
- // device must be started( enabled )\r
- l_pMdDevContext->m_DeviceStarted &&\r
- // flag set when driver has answered success to IRP_MN_QUERY_REMOVE_DEVICE\r
- !l_pMdDevContext->m_RemoveDeviceRequested &&\r
- // flag set when driver has answered success to IRP_MN_QUERY_STOP_DEVICE\r
- !l_pMdDevContext->m_StopDeviceRequested &&\r
- // control device (MDCTL) marked for deleting)\r
- !l_pMdDevContext->m_fDeletePending) {\r
- l_fCan = TRUE;\r
- }\r
-\r
- MdKdPrintCond( DBGLVL_MAXIMUM, !l_fCan, ("**** FALSE return from MdCanAcceptIoRequests()!\n"));\r
-\r
- return l_fCan;\r
-}\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-BOOLEAN\r
-MdCreateDeviceNames(\r
- IN PCHAR pi_pDevName,\r
- OUT PUNICODE_STRING po_pNtName,\r
- OUT PUNICODE_STRING po_pDosName\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Creates Nt and Dos names of the device;\r
- Convert them into Unicode format and put the results into given Unicode strings\r
- Allocates buffers for the Unicode strings from non-paged pool\r
-\r
-Arguments:\r
-\r
- pi_pDevName - ASCII name of the device without path.\r
- po_pNtName - pointer to Unicode string descriptor for NT device name\r
- po_pDosName - pointer to Unicode string descriptor for DOS device name\r
-\r
-\r
-Return Value:\r
-\r
- return TRUE if succeeded to create strings, else FALSE\r
-\r
---*/\r
-{ /* MdCreateDeviceNames */\r
-\r
- /* buffer for ASCII device name */\r
- char l_DevName[MD_MAX_DEV_NAME_LEN + 1];\r
- /* Unicode string length */\r
- int l_nUnicodeNameLen;\r
-\r
- /* build NT name */\r
- strcpy( l_DevName, "\\Device\\" );\r
- strcat( l_DevName, pi_pDevName );\r
-\r
- /* get the length */\r
- l_nUnicodeNameLen = (int)((strlen(l_DevName) + 1) * sizeof(WCHAR));\r
-\r
- /*\r
- * Init the NT device name\r
- */\r
- /* Allocate buffers for the NT device name */\r
- po_pNtName->Buffer = MdExAllocatePool(NonPagedPool, l_nUnicodeNameLen);\r
-\r
- /* Verify allocation */\r
- if ( po_pNtName->Buffer == NULL )\r
- { /* Allocation failed */\r
-\r
- return FALSE;\r
-\r
- } /* Allocation failed */\r
-\r
- /* store lengths */\r
- po_pNtName->Length = (USHORT)(l_nUnicodeNameLen - sizeof(WCHAR));\r
- po_pNtName->MaximumLength = (unsigned short)l_nUnicodeNameLen;\r
-\r
- /* Build Unicode NT device name */\r
- AsciiToUnicode( \r
- po_pNtName,\r
- l_DevName\r
- );\r
-\r
- /* build DOS name */\r
- strcpy( l_DevName, "\\DosDevices\\" );\r
- strcat( l_DevName, pi_pDevName );\r
-\r
- /* get the length */\r
- l_nUnicodeNameLen = (int)((strlen(l_DevName) + 1) * sizeof(WCHAR));\r
-\r
- /* Allocate buffers for the DOS device name */\r
- po_pDosName->Buffer = MdExAllocatePool(NonPagedPool, l_nUnicodeNameLen);\r
-\r
- /* Verify allocation */\r
- if ( po_pDosName->Buffer == NULL )\r
- { /* Allocation failed */\r
-\r
- /* Free the NT device name path buffer */\r
- MdExFreePool(po_pNtName->Buffer);\r
-\r
- return FALSE;\r
-\r
- } /* Allocation failed */\r
-\r
- /* store lengths */\r
- po_pDosName->Length = (USHORT)(l_nUnicodeNameLen - sizeof(WCHAR));\r
- po_pDosName->MaximumLength = (unsigned short)l_nUnicodeNameLen;\r
-\r
- /* Build the NT device name */\r
- AsciiToUnicode( \r
- po_pDosName,\r
- l_DevName\r
- );\r
-\r
- return TRUE;\r
-\r
-} /* MdCreateDeviceNames */\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-/**********************************\r
- * Device name DB handling *\r
- **********************************/\r
-int AddDevNameToDb(char *pi_DevName)\r
- {\r
- ULONG l_Size = (ULONG)strlen(pi_DevName) + 1;\r
- ULONG l_DbSize = g_pDrvContext->m_DevNamesDbSize;\r
-\r
- if ( l_DbSize + l_Size <= sizeof(g_pDrvContext->m_DevNamesDb))\r
- {\r
- RtlCopyMemory( &g_pDrvContext->m_DevNamesDb[l_DbSize], pi_DevName, l_Size);\r
- g_pDrvContext->m_DevNamesDbCnt++;\r
- g_pDrvContext->m_DevNamesDbSize += l_Size;\r
- return 0;\r
- }\r
- else\r
- { \r
- return 1;\r
- }\r
- }\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-/*------------------------------------------------------------------------------------------------------*/\r
-/*------------------------------------------------------------------------------------------------------*/\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-NTSTATUS CreateOneDevice(\r
- IN int pi_DevIx, /* index device BD info */\r
- UNICODE_STRING * pi_pusNtDeviceName, /* NT name */\r
- UNICODE_STRING * pi_pusDosDeviceName, /* Win32 name */\r
- OUT PMD_DEV_CONTEXT_T * pi_ppMdDevContext /* context of created device */\r
-)\r
-{\r
- /* status */\r
- NTSTATUS l_Status = STATUS_SUCCESS;\r
- /* our context to this device */\r
- PMD_DEV_CONTEXT_T l_pMdDevContext;\r
- /* device object we create for the added device */\r
- PDEVICE_OBJECT l_pFdo = NULL;\r
- /* dev info */\r
- PMD_HAL_DEV_PARAMS_T l_pDevInfo; /* device BD info */\r
- /* buffer for ASCII device name */\r
- char l_DevName[MD_MAX_DEV_NAME_LEN + 1];\r
- \r
- /* create and keep the exposed the name */\r
- l_pDevInfo = &g_DevParams[pi_DevIx];\r
- if (l_pDevInfo->m_DevId == MD_DEV_ID_TAVOR || l_pDevInfo->m_DevId == MD_DEV_ID_ARBEL_TM)\r
- sprintf( l_DevName, l_pDevInfo->m_ExFormat, g_pDrvContext->m_uCardNo );\r
- else\r
- sprintf( l_DevName, l_pDevInfo->m_ExFormat, l_pDevInfo->m_DevId, g_pDrvContext->m_uCardNo );\r
- if (l_pDevInfo->m_fExpose) {\r
- if (AddDevNameToDb(l_DevName))\r
- return STATUS_INSUFFICIENT_RESOURCES;\r
- }\r
-\r
- /* create Control Device names */\r
- /* !!! from now on work with ARBEL_TM as with TAVOR */\r
- //l_pDevInfo = (pi_DevIx == (int)MD_DEV_IX_ARBEL_TM) ? &g_DevParams[MD_DEV_IX_TAVOR] : &g_DevParams[pi_DevIx];\r
- l_pDevInfo = &g_DevParams[pi_DevIx];\r
- if (l_pDevInfo->m_DevId == MD_DEV_ID_TAVOR || l_pDevInfo->m_DevId == MD_DEV_ID_ARBEL_TM)\r
- sprintf( l_DevName, l_pDevInfo->m_Format, g_pDrvContext->m_uCardNo );\r
- else\r
- sprintf( l_DevName, l_pDevInfo->m_Format, l_pDevInfo->m_DevId, g_pDrvContext->m_uCardNo );\r
-\r
- if (!MdCreateDeviceNames(l_DevName, pi_pusNtDeviceName, pi_pusDosDeviceName))\r
- return STATUS_INSUFFICIENT_RESOURCES ;\r
- \r
- /* build NT name */\r
- MdKdPrint( DBGLVL_LOW,("(CreateOneDevice) Generated device name %s \n", l_DevName));\r
-\r
- /* create functional device object (FDO) */\r
- l_Status = MdDevInit( g_pDrvContext, l_pDevInfo->m_DevIx, pi_pusNtDeviceName, pi_pusDosDeviceName, &l_pMdDevContext); \r
-\r
- if (!NT_SUCCESS(l_Status)) \r
- { /* device creation failed */\r
-\r
- /* Free the NT device name path buffer */\r
- if (pi_pusNtDeviceName->Buffer)\r
- MdExFreePool(pi_pusNtDeviceName->Buffer);\r
-\r
- /* Free the Dos device name path buffer */\r
- if (pi_pusDosDeviceName->Buffer)\r
- MdExFreePool(pi_pusDosDeviceName->Buffer);\r
-\r
- return l_Status;\r
- } /* device creation failed */\r
-\r
- /* save ASCII name */\r
- strcpy ( l_pMdDevContext->m_AsciiDevName, l_DevName );\r
-\r
- /* get FDO handle */\r
- l_pFdo = l_pMdDevContext->m_pFdo;\r
-\r
- //Set this flag causes the driver to not receive a IRP_MN_STOP_DEVICE\r
- //during suspend and also not get an IRP_MN_START_DEVICE during resume.\r
- l_pFdo->Flags |= DO_POWER_PAGABLE;\r
-\r
- *pi_ppMdDevContext = l_pMdDevContext;\r
- return STATUS_SUCCESS;\r
-}\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-BOOLEAN\r
-MdGetRegistryDword(\r
- IN PWCHAR RegPath,\r
- IN PWCHAR ValueName,\r
- IN OUT PULONG Value\r
- )\r
-\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Obtain a Dword value from the registry\r
-\r
-\r
-Arguments:\r
-\r
- RegPath -- supplies absolute registry path\r
- ValueName - Supplies the Value Name.\r
- Value - receives the REG_DWORD value.\r
-\r
-Return Value:\r
-\r
- TRUE if successfull, FALSE on fail.\r
-\r
---*/\r
-\r
-{\r
- UNICODE_STRING path;\r
- RTL_QUERY_REGISTRY_TABLE paramTable[2]; //zero'd second table terminates parms\r
- ULONG lDef = *Value; // default\r
- NTSTATUS status;\r
- BOOLEAN fres;\r
- WCHAR wbuf[ MAXIMUM_FILENAME_LENGTH ];\r
-\r
- MdKdPrint( DBGLVL_HIGH,("Enter MdGetRegistryDword() RegPath = %ws\n ValueName =%ws\n", RegPath, ValueName));\r
- path.Length = 0;\r
- path.MaximumLength = MAXIMUM_FILENAME_LENGTH * sizeof( WCHAR ); // MAXIMUM_FILENAME_LENGTH defined in wdm.h\r
- path.Buffer = wbuf;\r
-\r
-\r
- RtlZeroMemory(path.Buffer, path.MaximumLength);\r
- RtlMoveMemory(path.Buffer, RegPath, wcslen( RegPath) * sizeof( WCHAR ));\r
-\r
- MdKdPrint( DBGLVL_HIGH,("MdGetRegistryDword() path= %ws\n", path.Buffer ));\r
-\r
- RtlZeroMemory(paramTable, sizeof(paramTable));\r
-\r
- paramTable[0].Flags = RTL_QUERY_REGISTRY_DIRECT;\r
-\r
- paramTable[0].Name = ValueName;\r
-\r
- paramTable[0].EntryContext = Value;\r
- paramTable[0].DefaultType = REG_DWORD;\r
- paramTable[0].DefaultData = &lDef;\r
- paramTable[0].DefaultLength = sizeof(ULONG);\r
-\r
-\r
- status = RtlQueryRegistryValues( RTL_REGISTRY_ABSOLUTE | RTL_REGISTRY_OPTIONAL,\r
- path.Buffer, paramTable, NULL, NULL);\r
-\r
- if (NT_SUCCESS(status)) {\r
- MdKdPrint( DBGLVL_MEDIUM,("Exit MdGetRegistryDWord() SUCCESS, value = decimal %d 0x%x\n", *Value, *Value));\r
- fres = TRUE;\r
-\r
- } else {\r
-\r
- MdKdPrintCond( DBGLVL_MEDIUM, (status == STATUS_INVALID_PARAMETER) ,("MdGetRegistryDWord() STATUS_INVALID_PARAMETER\n"));\r
- \r
- MdKdPrintCond( DBGLVL_MEDIUM, (status == STATUS_OBJECT_NAME_NOT_FOUND) ,("MdGetRegistryDWord() STATUS_OBJECT_NAME_NOT_FOUND\n"));\r
-\r
- fres = FALSE;\r
-\r
- }\r
-\r
- return fres;\r
-}\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-BOOLEAN\r
-MdGetRegistryString(\r
- IN PWCHAR RegPath,\r
- IN PWCHAR ValueName,\r
- IN PUNICODE_STRING DfltValue,\r
- IN OUT PUNICODE_STRING Value\r
- )\r
-\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Obtain a string value from the registry\r
-\r
-\r
-Arguments:\r
-\r
- RegPath -- supplies absolute registry path\r
- ValueName - Supplies the Value Name.\r
- Value - receives the REG_DWORD value.\r
-\r
-Return Value:\r
-\r
- TRUE if successfull, FALSE on fail.\r
-\r
---*/\r
-\r
-{\r
- UNICODE_STRING path;\r
- RTL_QUERY_REGISTRY_TABLE paramTable[2]; //zero'd second table terminates parms\r
- NTSTATUS status;\r
- BOOLEAN fres;\r
- WCHAR wbuf[ MAXIMUM_FILENAME_LENGTH ];\r
-\r
- MdKdPrint( DBGLVL_HIGH,("MdGetRegistryString(Enter) RegPath = %ws\n ValueName =%ws\n", RegPath, ValueName));\r
- path.Length = 0;\r
- path.MaximumLength = MAXIMUM_FILENAME_LENGTH * sizeof( WCHAR ); // MAXIMUM_FILENAME_LENGTH defined in wdm.h\r
- path.Buffer = wbuf;\r
-\r
-\r
- RtlZeroMemory(path.Buffer, path.MaximumLength);\r
- RtlMoveMemory(path.Buffer, RegPath, wcslen( RegPath) * sizeof( WCHAR ));\r
-\r
- MdKdPrint( DBGLVL_HIGH,("MdGetRegistryString() path= %ws\n", path.Buffer ));\r
-\r
- RtlZeroMemory(paramTable, sizeof(paramTable));\r
-\r
- paramTable[0].Flags = RTL_QUERY_REGISTRY_DIRECT;\r
- paramTable[0].Name = ValueName;\r
- paramTable[0].EntryContext = Value;\r
- paramTable[0].DefaultType = REG_SZ;\r
- paramTable[0].DefaultData = DfltValue;\r
- paramTable[0].DefaultLength = DfltValue->MaximumLength;\r
-\r
-\r
- status = RtlQueryRegistryValues( RTL_REGISTRY_ABSOLUTE | RTL_REGISTRY_OPTIONAL,\r
- path.Buffer, ¶mTable[0], NULL, NULL);\r
-\r
- if (NT_SUCCESS(status)) {\r
- MdKdPrint( DBGLVL_MEDIUM,("MdGetRegistryString(Exit) SUCCESS, value = %ws \n", Value));\r
- fres = TRUE;\r
-\r
- } else {\r
-\r
- MdKdPrintCond( DBGLVL_MEDIUM, (status == STATUS_INVALID_PARAMETER) ,("MdGetRegistryString(Exit) STATUS_INVALID_PARAMETER\n"));\r
- \r
- MdKdPrintCond( DBGLVL_MEDIUM, (status == STATUS_OBJECT_NAME_NOT_FOUND) ,("MdGetRegistryString(Exit) STATUS_OBJECT_NAME_NOT_FOUND\n"));\r
-\r
- fres = FALSE;\r
-\r
- }\r
-\r
- return fres;\r
-}\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-NTSTATUS\r
-RegistryMultiSzCallBack(\r
- IN PWSTR ValueName,\r
- IN ULONG ValueType,\r
- IN PVOID ValueData,\r
- IN ULONG ValueLength,\r
- IN PVOID Context,\r
- IN PVOID EntryContext\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This callback for a registry SZ or MULTI_SZ is called once for each\r
- SZ in the value. It will attempt to match the data with the\r
- UNICODE_STRING passed in as Context, and modify EntryContext if a\r
- match is found. Written for ClasspCheckRegistryForMediaChangeCompletion\r
-\r
-Arguments:\r
-\r
- ValueName - name of the key that was opened\r
- ValueType - type of data stored in the value (REG_SZ for this routine)\r
- ValueData - data in the registry, in this case a wide string\r
- ValueLength - length of the data including the terminating null\r
- Context - unicode string to compare against ValueData\r
- EntryContext - should be initialized to 0, will be set to 1 if match found\r
-\r
-Return Value:\r
-\r
- STATUS_SUCCESS\r
- EntryContext will be 1 if found\r
-\r
---*/\r
-{\r
- UNICODE_STRING uStr;\r
- ANSI_STRING aStr;\r
-\r
- PAGED_CODE();\r
- UNREFERENCED_PARAMETER(ValueName);\r
- UNREFERENCED_PARAMETER(ValueLength);\r
- UNREFERENCED_PARAMETER(EntryContext);\r
-\r
- // if the data is not a terminated string, exit\r
- if (ValueType != REG_SZ) return STATUS_SUCCESS;\r
-\r
- // convert wide string to ASCII\r
- RtlInitUnicodeString( &uStr, ValueData );\r
- RtlInitAnsiString( &aStr, NULL );\r
- RtlUnicodeStringToAnsiString( &aStr, &uStr, TRUE ); \\r
-\r
- // call user routine\r
- ((RegUserCallback_t)Context)(&aStr);\r
- \r
- // free resources\r
- RtlFreeAnsiString( &aStr );\r
- \r
- return STATUS_SUCCESS;\r
-}\r
-\r
-BOOLEAN\r
-MdGetRegistryMultiString(\r
- IN PWCHAR RegPath,\r
- IN PWCHAR ValueName,\r
- IN PVOID DfltValue,\r
- IN ULONG DfltValueSize,\r
- IN RegUserCallback_t Func\r
- )\r
-\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Obtain a string value from the registry\r
-\r
-\r
-Arguments:\r
-\r
- RegPath -- supplies absolute registry path\r
- ValueName - Supplies the Value Name.\r
- Value - receives the REG_DWORD value.\r
-\r
-Return Value:\r
-\r
- TRUE if successfull, FALSE on fail.\r
-\r
---*/\r
-\r
-{\r
- UNICODE_STRING path;\r
- RTL_QUERY_REGISTRY_TABLE paramTable[2]; //zero'd second table terminates parms\r
- NTSTATUS status;\r
- BOOLEAN fres;\r
- WCHAR wbuf[ MAXIMUM_FILENAME_LENGTH ];\r
- ULONG ulDummy;\r
- \r
- MdKdPrint( DBGLVL_HIGH,("MdGetRegistryString(Enter) RegPath = %ws\n ValueName =%ws\n", RegPath, ValueName));\r
- path.Length = 0;\r
- path.MaximumLength = MAXIMUM_FILENAME_LENGTH * sizeof( WCHAR ); // MAXIMUM_FILENAME_LENGTH defined in wdm.h\r
- path.Buffer = wbuf;\r
-\r
-\r
- RtlZeroMemory(path.Buffer, path.MaximumLength);\r
- RtlMoveMemory(path.Buffer, RegPath, wcslen( RegPath) * sizeof( WCHAR ));\r
-\r
- MdKdPrint( DBGLVL_HIGH,("MdGetRegistryString() path= %ws\n", path.Buffer ));\r
-\r
- RtlZeroMemory(paramTable, sizeof(paramTable));\r
-\r
- paramTable[0].QueryRoutine = RegistryMultiSzCallBack;\r
- paramTable[0].Flags = RTL_QUERY_REGISTRY_REQUIRED;\r
- paramTable[0].Name = ValueName;\r
- paramTable[0].EntryContext = &ulDummy;\r
- paramTable[0].DefaultType = REG_MULTI_SZ;\r
- paramTable[0].DefaultData = DfltValue;\r
- paramTable[0].DefaultLength = DfltValueSize;\r
-\r
-\r
- status = RtlQueryRegistryValues( RTL_REGISTRY_ABSOLUTE | RTL_REGISTRY_OPTIONAL,\r
- path.Buffer, ¶mTable[0], Func, NULL);\r
-\r
- if (NT_SUCCESS(status)) {\r
- fres = TRUE;\r
-\r
- } else {\r
-\r
- MdKdPrintCond( DBGLVL_MEDIUM, (status == STATUS_INVALID_PARAMETER) ,("MdGetRegistryString(Exit) STATUS_INVALID_PARAMETER\n"));\r
- \r
- MdKdPrintCond( DBGLVL_MEDIUM, (status == STATUS_OBJECT_NAME_NOT_FOUND) ,("MdGetRegistryString(Exit) STATUS_OBJECT_NAME_NOT_FOUND\n"));\r
-\r
- fres = FALSE;\r
-\r
- }\r
-\r
- return fres;\r
-}\r
-\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef _MT_UTIL_H\r
-#define _MT_UTIL_H\r
-\r
-/* registry path used for parameters global to all instances of the driver */\r
-#define MD_REGISTRY_PARAMETERS_PATH \\r
- L"\\REGISTRY\\Machine\\System\\CurrentControlSet\\SERVICES\\mt23108\\Parameters"\r
-\r
-\r
-/*\r
- * Copy a UNICODE_STRING\r
- */\r
-#define UCopyString(pi_pDestination,pi_pSource,pi_fAllocateDest) \\r
-{\\r
- PUNICODE_STRING _D = (pi_pDestination);\\r
- PUNICODE_STRING _S = (pi_pSource);\\r
- _D->Length = _S->Length;\\r
- _D->MaximumLength = _D->Length + sizeof(WCHAR);\\r
- if( pi_fAllocateDest ) _D->Buffer = (PWCHAR)MdExAllocatePool(NonPagedPool, _D->MaximumLength);\\r
- if ( _D->Buffer != NULL ){\\r
- RtlMoveMemory(_D->Buffer , _S->Buffer, _S->Length);\\r
- _D->Buffer[_D->Length/sizeof(WCHAR)] = UNICODE_NULL;\\r
- }\\r
- else {\\r
- _D->Length = _D->MaximumLength = 0;\\r
- }\\r
-}\r
-\r
-/* Get argument from va_list pointer */\r
-#define GET(VAR, TYPE) do { \\r
- RtlMoveMemory(&(VAR), l_pTmp, sizeof(TYPE)); \\r
- l_pTmp += sizeof(TYPE); \\r
- } while(0)\r
-\r
-/* read a DWORD from registry */\r
-#define MD_GET_REGISTRY_DWORD(name,dflt_val,result) \\r
- { \\r
- ULONG l_uValue = dflt_val; \\r
- if (MdGetRegistryDword( MD_REGISTRY_PARAMETERS_PATH, name, &l_uValue )) \\r
- result = l_uValue; \\r
- else \\r
- result = dflt_val; \\r
- }\r
-\r
-typedef void (*RegUserCallback_t)(PANSI_STRING);\r
-\r
-#define MD_GET_REGISTRY_STR(name,buf,size) \\r
- { \\r
- WCHAR l_swStr[250]; \\r
- UNICODE_STRING l_uStr = {0,sizeof(l_swStr),&l_swStr[0]}; \\r
- ANSI_STRING l_aStr = {0,size,buf}; \\r
- RtlZeroMemory( l_swStr, sizeof(l_swStr)); \\r
- MdGetRegistryString( MD_REGISTRY_PARAMETERS_PATH, name, &l_uStr, &l_uStr ); \\r
- RtlUnicodeStringToAnsiString( &l_aStr, &l_uStr, FALSE ); \\r
- }\r
-\r
-#define MD_GET_REGISTRY_MULTI_STR(name, dflt_buf, dflt_size, Func) \\r
- MdGetRegistryMultiString( MD_REGISTRY_PARAMETERS_PATH, name, dflt_buf, dflt_size,Func ) \r
-\r
-BOOLEAN\r
-MdGetRegistryDword(\r
- IN PWCHAR RegPath,\r
- IN PWCHAR ValueName,\r
- IN OUT PULONG Value\r
- );\r
-\r
-BOOLEAN\r
-MdGetRegistryString(\r
- IN PWCHAR RegPath,\r
- IN PWCHAR ValueName,\r
- IN PUNICODE_STRING DfltValue,\r
- IN OUT PUNICODE_STRING Value\r
- );\r
-\r
-BOOLEAN\r
-MdGetRegistryMultiString(\r
- IN PWCHAR RegPath,\r
- IN PWCHAR ValueName,\r
- IN PVOID DfltValue,\r
- IN ULONG DfltValueSize,\r
- IN RegUserCallback_t Func\r
- );\r
-\r
-\r
-VOID\r
-WriteEventLogEntry(\r
- PVOID pi_pIoObject,\r
- ULONG pi_ErrorCode,\r
- ULONG pi_UniqueErrorCode,\r
- ULONG pi_FinalStatus,\r
- ULONG pi_nDataItems,\r
- ...\r
- );\r
-\r
-\r
-PCHAR\r
-WcharToAscii(\r
- OUT PUCHAR pi_TargetString,\r
- IN const USHORT * pi_SourceString,\r
- IN ULONG pi_Size\r
- );\r
-/*++\r
-\r
-Routine Description:\r
- Converts wide-character string into ASCII\r
-\r
-Arguments:\r
-\r
- pi_TargetString...... result string\r
- pi_SourceString...... source string\r
- pi_Size.............. size of the source string\r
-\r
-Return Value:\r
-\r
- The result stringbytes.\r
-\r
---*/\r
-\r
-PWCHAR \r
-WcharFindChar(\r
- IN PWCHAR pi_BufStart,\r
- IN PWCHAR pi_BufEnd,\r
- IN WCHAR pi_FromPattern,\r
- IN WCHAR pi_ToPattern\r
- );\r
-/*++\r
-\r
-Routine Description:\r
- Converts wide-character string into ASCII\r
-\r
-Arguments:\r
-\r
- pi_BufStart.......... start of the source string\r
- pi_BufEnd............ end of the source string\r
- pi_FromPattern....... start of pattern range to find\r
- pi_ToPattern......... end of pattern range to find\r
-\r
-Return Value:\r
-\r
- pointer to the first pattern found or NULL (when reached the end)\r
-\r
---*/\r
-/*++\r
-\r
-Routine Description:\r
- Writes an event log entry to the event log.\r
-\r
-Arguments:\r
-\r
- pi_pIoObject......... The IO object ( driver object or device object ).\r
- pi_ErrorCode......... The error code.\r
- pi_UniqueErrorCode... A specific error code.\r
- pi_FinalStatus....... The final status.\r
- pi_nDataItems........ Number of data items.\r
- .\r
- . data items values\r
- .\r
-\r
-Return Value:\r
-\r
- None .\r
-\r
---*/\r
-\r
-USHORT \r
-AsciiToUnicode(\r
- PUNICODE_STRING pi_puTargetString,\r
- PUCHAR pi_szFormat,\r
- ...\r
- );\r
-/*++\r
-\r
-Routine Description:\r
- Writes a formatted ( printf like ) string to into a uniocde string.\r
-\r
-Arguments:\r
-\r
- pi_nDbgLogLevel...... Level of debugging log.\r
- pi_szFormat.......... The format of the log.\r
-\r
-Return Value:\r
-\r
- The formatted string length in bytes.\r
-\r
---*/\r
-\r
-\r
-NTSTATUS \r
-MdDevInit(\r
- IN PMD_DRV_CONTEXT_T pi_pDrvContext,\r
- IN MD_DEV_ID_E pi_eDevType,\r
- IN PUNICODE_STRING pi_pNtDeviceName,\r
- IN PUNICODE_STRING pi_pWin32DeviceName,\r
- IN OUT PVOID* pio_ppDevContext\r
- );\r
-/*++\r
-\r
-Routine Description:\r
- This routine creates the device and connect to the driver context\r
-\r
-\r
-Arguments:\r
-\r
- pi_pDrvContext.......... Driver context\r
- pi_eDevType............. Device type.\r
- pi_pNtDeviceName........ The \Device\????\ name\r
- pi_pWin32DeviceName..... The \DosDevices\????\ name\r
- pio_ppDevContext........ The device extension ofthe created object\r
-\r
-Return Value:\r
-\r
- STATUS_SUCCESS on success, otherwise an error indicating the reason for failure.\r
-\r
---*/\r
-\r
-NTSTATUS \r
-MdDevDeInit(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext \r
- );\r
-/*++\r
-\r
-Routine Description:\r
- This routine DeInitialize the device setting and context\r
-\r
-\r
-Arguments:\r
-\r
- pi_pMdDevContext........The device context\r
-Return Value:\r
-\r
- None.\r
-\r
---*/\r
-BOOLEAN\r
-MdCanAcceptIoRequests(\r
- IN PDEVICE_OBJECT DeviceObject\r
- );\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Check device extension status flags; \r
-\r
- Can't accept a new io request if device:\r
- 1) is removed, \r
- 2) has never been started, \r
- 3) is stopped,\r
- 4) has a remove request pending, or\r
- 5) has a stop device pending\r
-\r
-\r
-Arguments:\r
-\r
- DeviceObject - pointer to the device object for this instance of the 82930\r
- device.\r
-\r
-\r
-Return Value:\r
-\r
- return TRUE if can accept new io requests, else FALSE\r
-\r
---*/\r
-\r
-NTSTATUS \r
-MdInitPciCfgCard(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext,\r
- IN PCM_RESOURCE_LIST pi_pRawResources,\r
- IN PCM_RESOURCE_LIST pi_pTranslatedResources\r
- );\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This routine prepares the Driver to the work with a PCI card:\r
- - gets card resources from IRP;\r
- - store them on the device context;\r
- - translate physical address into virtual;\r
- - connect interrupt;\r
-\r
-Arguments:\r
-\r
- pi_pMdDevContext....... My device context\r
- pi_pRawResources....... Card raw resources\r
- pi_pTranslatedResources Card translated resources\r
-\r
-Return Value:\r
-\r
- None.\r
-\r
---*/\r
-\r
-VOID \r
-MdDeInitPciCfgCard(\r
- IN PMD_DEV_CONTEXT_T pi_pMdDevContext\r
- );\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This routine releases OS resources, allocaetd for the work with a PCI card:\r
- - disconnect the interrupt;\r
- - unmap virtual address of the CR-space;\r
-\r
-\r
-Arguments:\r
-\r
- pi_pMdDevContext....... My device context\r
-\r
-Return Value:\r
-\r
- None.\r
-\r
---*/\r
-\r
-BOOLEAN\r
-MdCreateDeviceNames(\r
- IN PCHAR pi_pDevName,\r
- OUT PUNICODE_STRING po_pNtName,\r
- OUT PUNICODE_STRING po_pDosName\r
- );\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Creates Nt and Dos names of the device;\r
- Convert them into Unicode format and put the results into given Unicode strings\r
- Allocates buffers for the Unicode strings from non-paged pool\r
-\r
-Arguments:\r
-\r
- pi_pDevName - ASCII name of the device without path.\r
- po_pNtName - pointer to Unicode string descriptor for NT device name\r
- po_pDosName - pointer to Unicode string descriptor for DOS device name\r
-\r
-\r
-Return Value:\r
-\r
- return TRUE if succeeded to create strings, else FALSE\r
-\r
---*/\r
-\r
-\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-NTSTATUS CreateOneDevice(\r
- IN int pi_DevIx, /* index device BD info */\r
- UNICODE_STRING * pi_pusNtDeviceName, /* NT name */\r
- UNICODE_STRING * pi_pusDosDeviceName, /* Win32 name */\r
- OUT PMD_DEV_CONTEXT_T * pi_ppMdDevContext /* context of created device */\r
-);\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-int AddDevNameToDb(char *pi_DevName);\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-NTSTATUS \r
-MdGetDevLocation(\r
- IN PDEVICE_OBJECT pi_pPdo,\r
- IN ULONG * pi_pBus,\r
- IN ULONG * pi_pSlot,\r
- IN ULONG * pi_pFunction\r
- );\r
-\r
-/*------------------------------------------------------------------------------------------------------*/\r
-/*------------------------------------------------------------------------------------------------------*/\r
-\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef _MDD_LIB_H_\r
-#define _MDD_LIB_H_\r
-\r
-/* no PVOID arithmetic in MS */\r
-#ifdef __WIN__\r
-#define PVOID_PTR char *\r
-#endif\r
-#ifdef __LINUX__\r
-#define PVOID_PTR void *\r
-#endif\r
-\r
-/*==========================================================================*/\r
-/*================== Only __WIN__ dependent stuff ==========================*/\r
-/*==========================================================================*/\r
-\r
-#ifdef __WIN__\r
-\r
-/*==========================================================================*/\r
-/*================================ Includes ================================*/\r
-/*==========================================================================*/\r
-\r
-/* \r
- * system\r
- */\r
-#include <ntddk.h>\r
-#include <limits.h>\r
-\r
-/* \r
- * proprietary\r
- */\r
-#include <mtl_common.h>\r
-#include <mdhal.h>\r
-#include <mdoal.h>\r
-#include <mosal.h>\r
-\r
-/*==========================================================================*/\r
-\r
-\r
-#endif /* __WIN__ */\r
-\r
-#endif /* _MDD_LIB_H_ */\r
-/*\r
- * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef _INFINIHOST_H_\r
-#define _INFINIHOST_H_\r
-\r
-/* headers */\r
-#include "thh_mod_obj.h"\r
-#include "thh_hob.h"\r
-#include <vapi.h>\r
-#include <evapi.h>\r
-//#include <vip.h>\r
-#include <vapi_common.h>\r
-\r
-/* exports */\r
-int HH_init_module(void);\r
-//int VIPKL_init_module(void);\r
-int VAPI_init_module(void);\r
-void VAPI_cleanup_module(void);\r
-//int VIPKL_cleanup_module(void);\r
-int HH_cleanup_module(void);\r
-int IB_MGT_init_module(int qp0_only);\r
-int IB_MGT_cleanup_module(void);\r
-int IB_MGT_reattach_hca( /* IN*/ const char * dev_name);\r
-void IB_MGT_fatal_delete_hca(VAPI_hca_hndl_t vapi_hca_hndl);\r
-//HH_ret_t THH_hob_destroy(HH_hca_hndl_t hca_hndl);\r
-\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-\r
-#include <windows.h>\r
-\r
-BOOL WINAPI \r
-DllMain(\r
- IN HANDLE pi_hInst, \r
- IN ULONG pi_nReason,\r
- IN LPVOID pi_pReserved\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- DLL main entry point.\r
-\r
-Arguments:\r
-\r
- pi_hInst..........\r
- pi_nReason........ \r
- pi_pReserved...... \r
-\r
-Return Value:\r
-\r
- Always TRUE\r
-\r
---*/\r
-{ /* DllMain */\r
-\r
- return TRUE ;\r
-\r
-} /* DllMain */\r
-;/*++\r
-;====================================================================================\r
-;Copyright (c) 2001 Mellanox Technologies\r
-;\r
-;Module Name:\r
-;\r
-; MdMsg.mc\r
-;\r
-;Abstract:\r
-;\r
-; MDDL Driver event log messages\r
-;\r
-;Authors:\r
-;\r
-; Leonid Keller\r
-;\r
-;Environment:\r
-;\r
-; User Mode .\r
-;\r
-;=====================================================================================\r
-;--*/\r
-;\r
-MessageIdTypedef = NTSTATUS\r
-\r
-SeverityNames = (\r
- Success = 0x0:STATUS_SEVERITY_SUCCESS\r
- Informational = 0x1:STATUS_SEVERITY_INFORMATIONAL\r
- Warning = 0x2:STATUS_SEVERITY_WARNING\r
- Error = 0x3:STATUS_SEVERITY_ERROR\r
- )\r
-\r
-FacilityNames = (\r
- System = 0x0\r
- RpcRuntime = 0x2:FACILITY_RPC_RUNTIME\r
- RpcStubs = 0x3:FACILITY_RPC_STUBS\r
- Io = 0x4:FACILITY_IO_ERROR_CODE\r
- Md = 0x7:FACILITY_MD_ERROR_CODE\r
- )\r
-\r
-\r
-MessageId=0x0001\r
-Facility=Md\r
-Severity=Informational\r
-SymbolicName=MD_EVENT_LOG_LOAD_OK\r
-Language=English\r
-The Mellanox InfiniHost Driver has loaded Successfully.\r
-.\r
-\r
-MessageId=+1\r
-Facility=Md\r
-Severity=Error\r
-SymbolicName=MD_EVENT_LOG_LOAD_ERROR\r
-Language=English\r
-The Mellanox InfiniHost Driver has failed to load\r
-.\r
-\r
-MessageId=+1\r
-Facility=Md\r
-Severity=Error\r
-SymbolicName=MD_EVENT_LOG_LOAD_ERROR_FW\r
-Language=English\r
-The Mellanox InfiniHost Driver has failed to load: THH_add_hca failed. Check FW.\r
-.\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-/* {{NO_DEPENDENCIES}} */\r
-/* Microsoft Developer Studio generated include file. */\r
-/* Used by Md.rc */\r
-\r
-#define IDD_DIALOG1 101\r
-\r
-/* Next default values for new objects */\r
-\r
-#ifdef APSTUDIO_INVOKED\r
-#ifndef APSTUDIO_READONLY_SYMBOLS\r
-#define _APS_NO_MFC 1\r
-#define _APS_NEXT_RESOURCE_VALUE 102\r
-#define _APS_NEXT_COMMAND_VALUE 40001\r
-#define _APS_NEXT_CONTROL_VALUE 1000\r
-#define _APS_NEXT_SYMED_VALUE 101\r
-#endif\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_bits_tav_csp_H\r
-#define H_bits_tav_csp_H\r
-\r
-\r
-/* */\r
-\r
-struct PCIX_Status_Reg_device_st { /* Little Endian */\r
- pseudo_bit_t func_num[0x00003];\r
- pseudo_bit_t dev_num[0x00005];\r
- pseudo_bit_t bus_num[0x00008];\r
- pseudo_bit_t dev_64bit[0x00001];\r
- pseudo_bit_t cap_133Mhz[0x00001];\r
- pseudo_bit_t splitc_discard[0x00001];\r
- pseudo_bit_t unexpected_splc[0x00001];\r
- pseudo_bit_t device_complex[0x00001];\r
- pseudo_bit_t designed_max_mem_r_bc[0x00002];\r
- pseudo_bit_t designed_max_outstand_splt[0x00003];\r
- pseudo_bit_t designed_max_cum_r_size[0x00003];\r
- pseudo_bit_t rec_splc_err_msg[0x00001];\r
- pseudo_bit_t reserved0[0x00002];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Pcix_command_reg_st { /* Little Endian */\r
- pseudo_bit_t data_perr_r_en[0x00001];\r
- pseudo_bit_t en_relaxed_order[0x00001];\r
- pseudo_bit_t max_mem_r_bc[0x00002];\r
- pseudo_bit_t max_outs_splt[0x00003];\r
- pseudo_bit_t resrvd[0x00009];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Message_Ctrl_Reg_st { /* Little Endian */\r
- pseudo_bit_t msi_en[0x00001];\r
- pseudo_bit_t multiple_msg_cap[0x00003];\r
- pseudo_bit_t multiple_msg_en[0x00003];\r
- pseudo_bit_t cap_64bit_addt[0x00001];\r
- pseudo_bit_t reserved0[0x00008];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct MSIX_Message_Ctrl_Reg_st { /* Little Endian */\r
- pseudo_bit_t Table_Size[0x0000b];\r
- pseudo_bit_t reserved0[0x00003];\r
- pseudo_bit_t function_mask[0x00001];\r
- pseudo_bit_t msix_en[0x00001];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Exp_ROM_st { /* Little Endian */\r
- pseudo_bit_t exp_rom_en[0x00001];\r
- pseudo_bit_t res[0x0000a];\r
- pseudo_bit_t addr[0x00015];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Bar_st { /* Little Endian */\r
- pseudo_bit_t memory_or_io[0x00001];\r
- pseudo_bit_t type[0x00002];\r
- pseudo_bit_t prefetchable[0x00001];\r
- pseudo_bit_t addr[0x0001c];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Status_Register_st { /* Little Endian */\r
- pseudo_bit_t rsv2[0x00003];\r
- pseudo_bit_t interrupt_status[0x00001];\r
- pseudo_bit_t capability_list[0x00001];\r
- pseudo_bit_t cap_66Mhz[0x00001];\r
- pseudo_bit_t rsv1[0x00001];\r
- pseudo_bit_t fast_b2b[0x00001];\r
- pseudo_bit_t master_data_perr[0x00001];\r
- pseudo_bit_t devsel_timing[0x00002];\r
- pseudo_bit_t sig_target_abort[0x00001];\r
- pseudo_bit_t rec_target_abort[0x00001];\r
- pseudo_bit_t rec_master_abort[0x00001];\r
- pseudo_bit_t sig_sys_err[0x00001];\r
- pseudo_bit_t detected_perr[0x00001];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Command_Register_st { /* Little Endian */\r
- pseudo_bit_t io_space[0x00001];\r
- pseudo_bit_t mem_space[0x00001];\r
- pseudo_bit_t bus_master[0x00001];\r
- pseudo_bit_t special_cycle[0x00001];\r
- pseudo_bit_t mem_w_and_invalid_en[0x00001];\r
- pseudo_bit_t vga_snoop_en[0x00001];\r
- pseudo_bit_t parity_err_response[0x00001];\r
- pseudo_bit_t stepping_ctrl[0x00001];\r
- pseudo_bit_t serr_en[0x00001];\r
- pseudo_bit_t fast_b2b[0x00001];\r
- pseudo_bit_t interrupt_disable[0x00001];\r
- pseudo_bit_t rsv0[0x00005];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct PCIX_Status_Reg_bridge_st { /* Little Endian */\r
- pseudo_bit_t func_num[0x00003];\r
- pseudo_bit_t dev_num[0x00005];\r
- pseudo_bit_t bus_num[0x00008];\r
- pseudo_bit_t dev_64bit[0x00001];\r
- pseudo_bit_t cap_133Mhz[0x00001];\r
- pseudo_bit_t splitc_discard[0x00001];\r
- pseudo_bit_t unexpected_splc[0x00001];\r
- pseudo_bit_t splc_overrun[0x00001];\r
- pseudo_bit_t splr_delayed[0x00001];\r
- pseudo_bit_t reserved0[0x0000a];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct PCIX_Sec_Status_Reg_st { /* Little Endian */\r
- pseudo_bit_t dev_64bit[0x00001];\r
- pseudo_bit_t cap_133Mhz[0x00001];\r
- pseudo_bit_t splitc_discard[0x00001];\r
- pseudo_bit_t unexpected_splc[0x00001];\r
- pseudo_bit_t splc_overrun[0x00001];\r
- pseudo_bit_t splr_delayed[0x00001];\r
- pseudo_bit_t sec_clock_freq[0x00003];\r
- pseudo_bit_t reserved0[0x00007];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Bridge_Ctrl_st { /* Little Endian */\r
- pseudo_bit_t parity_err_response[0x00001];\r
- pseudo_bit_t serr_en[0x00001];\r
- pseudo_bit_t isa_en[0x00001];\r
- pseudo_bit_t vga_en[0x00001];\r
- pseudo_bit_t res1[0x00001];\r
- pseudo_bit_t master_abort_mode[0x00001];\r
- pseudo_bit_t sec_bus_reset[0x00001];\r
- pseudo_bit_t fast_b2b_en[0x00001];\r
- pseudo_bit_t pri_discard_timeout[0x00001];\r
- pseudo_bit_t sec_discard_timeout[0x00001];\r
- pseudo_bit_t discard_timer_stat[0x00001];\r
- pseudo_bit_t discard_timer_serr_en[0x00001];\r
- pseudo_bit_t res0[0x00004];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Prefetch_mem_lsb_st { /* Little Endian */\r
- pseudo_bit_t addr_type[0x00004];\r
- pseudo_bit_t addr[0x0000c];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Secondary_Status_Reg_st { /* Little Endian */\r
- pseudo_bit_t res1[0x00004];\r
- pseudo_bit_t capability_list[0x00001];\r
- pseudo_bit_t cap_66Mhz[0x00001];\r
- pseudo_bit_t res0[0x00001];\r
- pseudo_bit_t fast_b2b[0x00001];\r
- pseudo_bit_t data_parity_reported[0x00001];\r
- pseudo_bit_t devsel_timing[0x00002];\r
- pseudo_bit_t sig_target_abort[0x00001];\r
- pseudo_bit_t rec_target_abort[0x00001];\r
- pseudo_bit_t rec_master_abort[0x00001];\r
- pseudo_bit_t rec_sys_err[0x00001];\r
- pseudo_bit_t detected_perr[0x00001];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct IO_lsb_st { /* Little Endian */\r
- pseudo_bit_t addr_type[0x00004];\r
- pseudo_bit_t addr[0x00004];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg29_device_st { /* Little Endian */\r
- struct PCIX_Status_Reg_device_st pcix_status_reg;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg28_device_st { /* Little Endian */\r
- pseudo_bit_t pcix_cap_id[0x00008];\r
- pseudo_bit_t pcix_next_cap_ptr[0x00008];\r
- struct Pcix_command_reg_st pcix_command;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg27_st { /* Little Endian */\r
- pseudo_bit_t message_data_reg[0x00010];\r
- pseudo_bit_t reserved0[0x00010];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg26_st { /* Little Endian */\r
- pseudo_bit_t message_addr_msb[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg25_st { /* Little Endian */\r
- pseudo_bit_t message_addr_lsb[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg24_st { /* Little Endian */\r
- pseudo_bit_t msi_cap_id[0x00008];\r
- pseudo_bit_t msi_next_cap_ptr[0x00008];\r
- struct Message_Ctrl_Reg_st message_control_reg;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg23_st { /* Little Endian */\r
- pseudo_bit_t cr_space_data[0x00020];/* Holds the data that should be put in cr space in address (from prev word) */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg22_st { /* Little Endian */\r
- pseudo_bit_t cr_space_addr[0x00020];/* Holds addres in cr-space .use to burn eprom */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg_vendor_st { /* Little Endian */\r
- pseudo_bit_t vendor_specific[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg18_device_st { /* Little Endian */\r
- pseudo_bit_t PBA_BIR[0x00003];\r
- pseudo_bit_t PBA_Offset[0x0001d];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg17_device_st { /* Little Endian */\r
- pseudo_bit_t Table_BIR[0x00003];\r
- pseudo_bit_t Table_Offset[0x0001d];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg16_device_st { /* Little Endian */\r
- pseudo_bit_t msix_cap_id[0x00008];\r
- pseudo_bit_t msix_next_cap_ptr[0x00008];\r
- struct MSIX_Message_Ctrl_Reg_st message_control_reg;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg15_device_st { /* Little Endian */\r
- pseudo_bit_t interrupt_line[0x00008];\r
- pseudo_bit_t interrupt_pin[0x00008];\r
- pseudo_bit_t min_gnt[0x00008];\r
- pseudo_bit_t max_latency[0x00008];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg14_device_st { /* Little Endian */\r
- pseudo_bit_t reserevd[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg13_st { /* Little Endian */\r
- pseudo_bit_t cap_ptr[0x00008];\r
- pseudo_bit_t reserevd[0x00018];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg12_device_st { /* Little Endian */\r
- struct Exp_ROM_st eprom_base_addr;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg11_device_st { /* Little Endian */\r
- pseudo_bit_t subsys_vendor_id[0x00010];\r
- pseudo_bit_t subsys_id[0x00010];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg10_device_st { /* Little Endian */\r
- pseudo_bit_t cardbus_cis_ptr[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg9_device_st { /* Little Endian */\r
- struct Bar_st bar5;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg8_device_st { /* Little Endian */\r
- struct Bar_st bar4;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg7_device_st { /* Little Endian */\r
- struct Bar_st bar3;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg6_device_st { /* Little Endian */\r
- struct Bar_st bar2;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg5_st { /* Little Endian */\r
- struct Bar_st bar1;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg4_st { /* Little Endian */\r
- struct Bar_st bar0;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg3_st { /* Little Endian */\r
- pseudo_bit_t cache_line_size[0x00008];\r
- pseudo_bit_t latency_timer[0x00008];\r
- pseudo_bit_t header_type[0x00008];\r
- pseudo_bit_t bist[0x00008];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg2_st { /* Little Endian */\r
- pseudo_bit_t revision_id[0x00008];\r
- pseudo_bit_t class_code[0x00018];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg1_st { /* Little Endian */\r
- struct Command_Register_st command_reg;\r
- struct Status_Register_st status_reg;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg0_st { /* Little Endian */\r
- pseudo_bit_t vendor_id[0x00010];\r
- pseudo_bit_t device_id[0x00010];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg31_bridge_st { /* Little Endian */\r
- pseudo_bit_t downstream_split_ctrl_reg[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg30_bridge_st { /* Little Endian */\r
- pseudo_bit_t upstream_split_ctrl_reg[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg29_bridge_st { /* Little Endian */\r
- struct PCIX_Status_Reg_bridge_st pcix_status_reg;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg28_bridge_st { /* Little Endian */\r
- pseudo_bit_t pcix_cap_id[0x00008];\r
- pseudo_bit_t pcix_next_cap_ptr[0x00008];\r
- struct PCIX_Sec_Status_Reg_st pcix_sec_status_reg;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg15_bridge_st { /* Little Endian */\r
- pseudo_bit_t interrupt_line[0x00008];\r
- pseudo_bit_t interrupt_pin[0x00008];\r
- struct Bridge_Ctrl_st bridge_ctrl;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg14_bridge_st { /* Little Endian */\r
- struct Exp_ROM_st eprom_base_addr;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg12_bridge_st { /* Little Endian */\r
- pseudo_bit_t io_base_upper16[0x00010];\r
- pseudo_bit_t io_limit_upper16[0x00010];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg11_bridge_st { /* Little Endian */\r
- pseudo_bit_t prefetch_limit_upper32[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg10_bridge_st { /* Little Endian */\r
- pseudo_bit_t prefetch_base_upper32[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg9_bridge_st { /* Little Endian */\r
- struct Prefetch_mem_lsb_st prefetch_mem_base;\r
- struct Prefetch_mem_lsb_st prefetch_mem_limit;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg8_bridge_st { /* Little Endian */\r
- pseudo_bit_t mem_base[0x00010];\r
- pseudo_bit_t mem_limit[0x00010];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg7_bridge_st { /* Little Endian */\r
- struct IO_lsb_st io_base;\r
- struct IO_lsb_st io_limit;\r
- struct Secondary_Status_Reg_st sec_status;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Reg6_bridge_st { /* Little Endian */\r
- pseudo_bit_t pri_bus_num[0x00008];\r
- pseudo_bit_t sec_bus_num[0x00008];\r
- pseudo_bit_t subo_bus_num[0x00008];\r
- pseudo_bit_t sec_latency_timer[0x00008];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Completion Engine CECC Debug */\r
-\r
-struct CECCDEBUG_st { /* Little Endian */\r
- pseudo_bit_t cc_agent[0x00002]; /* cc_agent */\r
- pseudo_bit_t cc_agentlast[0x00002]; /* cc_agentlast */\r
- pseudo_bit_t cccmd_ps[0x00003]; /* cccmd_ps fsm */\r
- pseudo_bit_t reserved0[0x00019];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Completion Engine EVENT Debug */\r
-\r
-struct CEEVENTDEBUG_st { /* Little Endian */\r
- pseudo_bit_t eve_agent[0x00002]; /* eve_agent */\r
- pseudo_bit_t eve_agentlast[0x00002];/* eve_agentlast */\r
- pseudo_bit_t reserved0[0x0001c];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Completion Engine CENSI Debug */\r
-\r
-struct CENSIDEBUG_st { /* Little Endian */\r
- pseudo_bit_t nsi_agent[0x00002]; /* nsi_agent */\r
- pseudo_bit_t nsi_agentlast[0x00002];/* nsi_agentlast */\r
- pseudo_bit_t reserved0[0x0001c];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Completion Engine TPT Debug */\r
-\r
-struct CETPTDEBUG_st { /* Little Endian */\r
- pseudo_bit_t tpt_agent[0x00002]; /* tpt_agent */\r
- pseudo_bit_t tpt_agentlast[0x00002];/* tpt_agentlast */\r
- pseudo_bit_t reserved0[0x0001c];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Completion Engine LDB Debug */\r
-\r
-struct CELDBDEBUG_st { /* Little Endian */\r
- pseudo_bit_t ldb_res_ps[0x00001]; /* ldb_res_ps fsm */\r
- pseudo_bit_t reserved0[0x0001f];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Completion Engine CEINSTAGE Debug */\r
-\r
-struct CEINSTAGEDEBUG_st { /* Little Endian */\r
- pseudo_bit_t rdexarb_ps[0x00001]; /* rdexarb_ps fsm */\r
- pseudo_bit_t fifopop_ps[0x00001]; /* fifopop_ps fsm */\r
- pseudo_bit_t reserved0[0x0001e];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Completion Engine FIFO Debug */\r
-\r
-struct CEINFIFODEBUG_st { /* Little Endian */\r
- pseudo_bit_t write_counter[0x00008];/* write counter */\r
- pseudo_bit_t read_counter[0x00008]; /* read counter */\r
- pseudo_bit_t fifo_empty[0x00001]; /* fifo empty signal */\r
- pseudo_bit_t reserved0[0x0000f];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Completion Engine CEINDRE Debug */\r
-\r
-struct CEINRDEDEBUG_st { /* Little Endian */\r
- pseudo_bit_t push_ps[0x00002]; /* push_ps fsm */\r
- pseudo_bit_t reserved0[0x0001e];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Completion Engine NSWR Debug */\r
-\r
-struct CENSWRDEBUG_st { /* Little Endian */\r
- pseudo_bit_t cens_corefree[0x00001];/* cens_corefree signal */\r
- pseudo_bit_t nswr_done[0x00001]; /* nswr_done signal */\r
- pseudo_bit_t cens_acknk[0x00002]; /* cens_acknk signals */\r
- pseudo_bit_t nswr_pushfifo_ps[0x00001];/* nswr_pushfifo_ps fsm */\r
- pseudo_bit_t reserved0[0x0001b];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Completion Engine Core Debug */\r
-\r
-struct CECOREDEBUG_st { /* Little Endian */\r
- pseudo_bit_t produceridx_reg[0x00020];/* producer index */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ldb_entry_idx[0x00018];/* ldb entry idx */\r
- pseudo_bit_t ldb_pop_counter[0x00004];/* ldb pop counter */\r
- pseudo_bit_t ldb_access_op_reg[0x00003];/* ldb access opcode */\r
- pseudo_bit_t reserved0[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t completion_counter[0x00011];/* completion_counter */\r
- pseudo_bit_t reserved1[0x0000f];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t event_generate[0x00003];/* event_generate by core */\r
- pseudo_bit_t solicitidx_update[0x00001];/* solicited index update indication */\r
- pseudo_bit_t lasteventidx_update[0x00001];/* last event index update indication */\r
- pseudo_bit_t cq_rep_around[0x00001];/* cq rep around occur */\r
- pseudo_bit_t reserved2[0x00006];\r
- pseudo_bit_t corestate_ps[0x00003]; /* corestate_ps fsm */\r
- pseudo_bit_t reserved3[0x00001];\r
- pseudo_bit_t rqst_state[0x00003]; /* Requester PS */\r
- pseudo_bit_t reserved4[0x00003];\r
- pseudo_bit_t coreldbin_ps[0x00001]; /* coreldbin_ps fsm */\r
- pseudo_bit_t corecccmd_ps[0x00002]; /* corecccmd_ps fsm */\r
- pseudo_bit_t coreccdata_ps[0x00002];/* coreccdat_ps fsm */\r
- pseudo_bit_t reserved5[0x00005];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t solicitidx[0x00020]; /* soilicited index */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t lasteventidx[0x00020]; /* last event index */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x00040];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* ce in fifo size */\r
-\r
-struct CEINFIFOCFG_st { /* Little Endian */\r
- pseudo_bit_t ceinfifo_addr[0x00008];/* last address - changing fifo size\r
- 0 means not using this value */\r
- pseudo_bit_t reserved0[0x00018];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* CE CQC Configuration */\r
-\r
-struct CECQCCFG_st { /* Little Endian */\r
- pseudo_bit_t cqc_credits[0x00005]; /* ce credits to CQC */\r
- pseudo_bit_t reserved0[0x0001b];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @clear nswr */\r
-\r
-struct CENSWRCFG_st { /* Little Endian */\r
- pseudo_bit_t erp_clr_nswr_ptr[0x00001];/* clear fifo ptr (reset fifo) */\r
- pseudo_bit_t nswr_nsi_ps[0x00003]; /* nswr_nsi_ps fsm */\r
- pseudo_bit_t nswr_tpt_ps[0x00002]; /* nswr_tpt_ps fsm */\r
- pseudo_bit_t nswr_cc_ps[0x00002]; /* nswr_cc_ps fsm */\r
- pseudo_bit_t reserved0[0x00018];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* CE Core Configuration */\r
-\r
-struct CECORECFG_st { /* Little Endian */\r
- pseudo_bit_t ver[0x00004]; /* version */\r
- pseudo_bit_t cfg_hcaid[0x00003]; /* hca id */\r
- pseudo_bit_t cfg_ignore_hdrx[0x00001];/* not to wait to hdrx for posted write to NSI */\r
- pseudo_bit_t nsb_page_size[0x00004];/* page_size encoding\r
- 0000 - reserved\r
- 0001 - reserved\r
- 0010 - 4K (default)\r
- 0011 - 8K\r
- 0100 - 16K\r
- 0101 - 32K\r
- 0110 - 64K\r
- Others - reserved\r
- */\r
- pseudo_bit_t rep_interrupt[0x00001];/* interrupt on rep or page boundry */\r
- pseudo_bit_t cfg_no_errpsn[0x00001];/* no modified errPSN command to LDB */\r
- pseudo_bit_t reserved0[0x00002];\r
- pseudo_bit_t cfg_ldb_pop_limit[0x00004];/* limit of ldb reads before doing pop. Max is 8 (which is also the default) */\r
- pseudo_bit_t reserved1[0x0000c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cecc_timer_limit[0x00010];/* read cqc timer */\r
- pseudo_bit_t cecc_timer_count_limit[0x00010];/* timer counter limit */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t stop_tpt_nsi[0x00001]; /* stop sending to tpt/nsi */\r
- pseudo_bit_t ce_stoped_tpt_nsi[0x00001];/* ce stoped sending to tpt/nsi */\r
- pseudo_bit_t reserved2[0x0001e];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct debug_bits_st { /* Little Endian */\r
- pseudo_bit_t remote[0x00001];\r
- pseudo_bit_t reserved0[0x00003];\r
- pseudo_bit_t dbg_en[0x00001];\r
- pseudo_bit_t dbg_crdy[0x00001];\r
- pseudo_bit_t dbg_ret[0x00001];\r
- pseudo_bit_t reserved1[0x00001];\r
- pseudo_bit_t int_d[0x00001];\r
- pseudo_bit_t rint[0x00001];\r
- pseudo_bit_t reserved2[0x00002];\r
- pseudo_bit_t code_bp_reg[0x00001];\r
- pseudo_bit_t read_bp_reg[0x00001];\r
- pseudo_bit_t write_bp_reg[0x00001];\r
- pseudo_bit_t rtrap_reg[0x00001];\r
- pseudo_bit_t misacc[0x00001];\r
- pseudo_bit_t reserved3[0x0000f];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Pop FIFO Control Register */\r
-\r
-struct Irisc_pop_fifo_ctrl_st { /* Little Endian */\r
- pseudo_bit_t f[0x00001]; /* Full */\r
- pseudo_bit_t af[0x00001]; /* Almost Full - Same as Full if FIFO does not implement AF output. */\r
- pseudo_bit_t e[0x00001]; /* Empty */\r
- pseudo_bit_t ae[0x00001]; /* Almost Empty - May be same as Empty if FIFO does not implement AE output. */\r
- pseudo_bit_t reserved0[0x00004];\r
- pseudo_bit_t state[0x00008]; /* number of free entries in fifo */\r
- pseudo_bit_t reserved1[0x00008];\r
- pseudo_bit_t pop[0x00001]; /* Write Only (not defined on read) - When a 1 is written a Pop will be done to the FIFO. */\r
- pseudo_bit_t poprd[0x00001]; /* PopRd - When set, every read from FIFO DWord 0 will result in a Pop to the FIFO. */\r
- pseudo_bit_t reserved2[0x00005];\r
- pseudo_bit_t flock[0x00001]; /* FIFOLocked - This bit is set when the gw is being used by some enitity. Sw is required to read the fifocontrol field before using a fifo. This field behaves as a semaphore, if it was cleared the read returns a 0 in this bit and the bit is set by the hw atomically. Every subsequent read access to the field will return 1 until the agent that locked the fifo writes a zero. */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* FIFO Control Register */\r
-\r
-struct FIFOCONTROL_st { /* Little Endian */\r
- pseudo_bit_t f[0x00001]; /* Full */\r
- pseudo_bit_t af[0x00001]; /* Almost Full - Same as Full if FIFO does not implement AF output. */\r
- pseudo_bit_t e[0x00001]; /* Empty */\r
- pseudo_bit_t ae[0x00001]; /* Almost Empty - May be same as Empty if FIFO does not implement AE output. */\r
- pseudo_bit_t reserved0[0x00004];\r
- pseudo_bit_t state[0x00008]; /* number of free entries in fifo */\r
- pseudo_bit_t reserved1[0x00008];\r
- pseudo_bit_t pop[0x00001]; /* Write Only (not defined on read) - When a 1 is written a Pop will be done to the FIFO. */\r
- pseudo_bit_t poprd[0x00001]; /* PopRd - When set, every read from FIFO DWord 0 will result in a Pop to the FIFO. */\r
- pseudo_bit_t reserved2[0x00005];\r
- pseudo_bit_t flock[0x00001]; /* FIFOLocked - This bit is set when the gw is being used by some enitity. Sw is required to read the fifocontrol field before using a fifo. This field behaves as a semaphore, if it was cleared the read returns a 0 in this bit and the bit is set by the hw atomically. Every subsequent read access to the field will return 1 until the agent that locked the fifo writes a zero. */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Gateway Control Register */\r
-\r
-struct GWCONTROL_st { /* Little Endian */\r
- pseudo_bit_t gwaddress[0x00018];\r
- pseudo_bit_t gwcmd[0x00006]; /* Command/Status - Sw writes to this field the desired command. Hw executes the cmd and returns in this field the status of the operation. For details on commands and status, see instance description. */\r
- pseudo_bit_t gwbusy[0x00001]; /* Written to 1 by SW together with command to trigger\r
- HW. It is cleared by hw after completing the required\r
- operation and seting the status in the Command/Status\r
- field. */\r
- pseudo_bit_t gwlocked[0x00001]; /* Gateway Locked - This bit is set when the gw is being used by some enitity. Sw is required to read the gwcontrol field before using a gw. This field behaves as a semaphore, if it was cleared the read returns a 0 in this bit and the bit is set by the hw atomically. Every subsequent read access to the field will return 1 until the agent that locked the gw writes a zero. */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Doorbell FIFO Controller */\r
-\r
-struct DB_FIFOCNTL_st { /* Little Endian */\r
- pseudo_bit_t f[0x00001]; /* fifo full */\r
- pseudo_bit_t af[0x00001]; /* almost_full */\r
- pseudo_bit_t e[0x00001]; /* fifo empty */\r
- pseudo_bit_t ae[0x00001]; /* almost_empty */\r
- pseudo_bit_t reserved0[0x00014];\r
- pseudo_bit_t pop[0x00001]; /* pop */\r
- pseudo_bit_t poprd[0x00001]; /* PopRd - When set, every read from FIFO DWord 0 will result in a Pop to the FIFO. */\r
- pseudo_bit_t reserved1[0x00005];\r
- pseudo_bit_t flock[0x00001]; /* FIFOLocked - This bit is set when the gw is being used by some enitity. Sw is required to read the fifocontrol field before using a fifo. This field behaves as a semaphore, if it was cleared the read returns a 0 in this bit and the bit is set by the hw atomically. Every subsequent read access to the field will return 1 until the agent that locked the fifo writes a zero. */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Performance Counters */\r
-\r
-struct QPC_Performance_Counters_st { /* Little Endian */\r
- pseudo_bit_t sqpc_miss_cnt[0x00020];/* SQPC cache miss count */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rqpc_miss_cnt[0x00020];/* RQPC cache miss count */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cqc_miss_cnt[0x00020]; /* CQC cache miss count */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Performance Counters */\r
-\r
-struct TPT_Performance_Counters_st { /* Little Endian */\r
- pseudo_bit_t mpt_miss_cnt[0x00020]; /* MPT cache miss count */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mtt_miss_cnt[0x00020]; /* MTT cache miss count */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Device_header_st { /* Little Endian */\r
- struct Reg0_st reg0;\r
-/* --------------------------------------------------------- */\r
- struct Reg1_st reg1;\r
-/* --------------------------------------------------------- */\r
- struct Reg2_st reg2;\r
-/* --------------------------------------------------------- */\r
- struct Reg3_st reg3;\r
-/* --------------------------------------------------------- */\r
- struct Reg4_st reg4;\r
-/* --------------------------------------------------------- */\r
- struct Reg5_st reg5;\r
-/* --------------------------------------------------------- */\r
- struct Reg6_device_st reg6;\r
-/* --------------------------------------------------------- */\r
- struct Reg7_device_st reg7;\r
-/* --------------------------------------------------------- */\r
- struct Reg8_device_st reg8;\r
-/* --------------------------------------------------------- */\r
- struct Reg9_device_st reg9;\r
-/* --------------------------------------------------------- */\r
- struct Reg10_device_st reg10;\r
-/* --------------------------------------------------------- */\r
- struct Reg11_device_st reg11;\r
-/* --------------------------------------------------------- */\r
- struct Reg12_device_st reg12;\r
-/* --------------------------------------------------------- */\r
- struct Reg13_st reg13;\r
-/* --------------------------------------------------------- */\r
- struct Reg14_device_st reg14;\r
-/* --------------------------------------------------------- */\r
- struct Reg15_device_st reg15;\r
-/* --------------------------------------------------------- */\r
- struct Reg16_device_st reg16;\r
-/* --------------------------------------------------------- */\r
- struct Reg17_device_st reg17;\r
-/* --------------------------------------------------------- */\r
- struct Reg18_device_st reg18;\r
-/* --------------------------------------------------------- */\r
- struct Reg_vendor_st reg19;\r
-/* --------------------------------------------------------- */\r
- struct Reg_vendor_st reg20;\r
-/* --------------------------------------------------------- */\r
- struct Reg_vendor_st reg21;\r
-/* --------------------------------------------------------- */\r
- struct Reg22_st reg22;\r
-/* --------------------------------------------------------- */\r
- struct Reg23_st reg23;\r
-/* --------------------------------------------------------- */\r
- struct Reg24_st reg24;\r
-/* --------------------------------------------------------- */\r
- struct Reg25_st reg25;\r
-/* --------------------------------------------------------- */\r
- struct Reg26_st reg26;\r
-/* --------------------------------------------------------- */\r
- struct Reg27_st reg27;\r
-/* --------------------------------------------------------- */\r
- struct Reg28_device_st reg28;\r
-/* --------------------------------------------------------- */\r
- struct Reg29_device_st reg29;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00060];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct Bridge_header_st { /* Little Endian */\r
- struct Reg0_st reg0;\r
-/* --------------------------------------------------------- */\r
- struct Reg1_st reg1;\r
-/* --------------------------------------------------------- */\r
- struct Reg2_st reg2;\r
-/* --------------------------------------------------------- */\r
- struct Reg3_st reg3;\r
-/* --------------------------------------------------------- */\r
- struct Reg4_st reg4;\r
-/* --------------------------------------------------------- */\r
- struct Reg5_st reg5;\r
-/* --------------------------------------------------------- */\r
- struct Reg6_bridge_st reg6;\r
-/* --------------------------------------------------------- */\r
- struct Reg7_bridge_st reg7;\r
-/* --------------------------------------------------------- */\r
- struct Reg8_bridge_st reg8;\r
-/* --------------------------------------------------------- */\r
- struct Reg9_bridge_st reg9;\r
-/* --------------------------------------------------------- */\r
- struct Reg10_bridge_st reg10;\r
-/* --------------------------------------------------------- */\r
- struct Reg11_bridge_st reg11;\r
-/* --------------------------------------------------------- */\r
- struct Reg12_bridge_st reg12;\r
-/* --------------------------------------------------------- */\r
- struct Reg13_st reg13;\r
-/* --------------------------------------------------------- */\r
- struct Reg14_bridge_st reg14;\r
-/* --------------------------------------------------------- */\r
- struct Reg15_bridge_st reg15;\r
-/* --------------------------------------------------------- */\r
- struct Reg_vendor_st reg16;\r
-/* --------------------------------------------------------- */\r
- struct Reg_vendor_st reg17;\r
-/* --------------------------------------------------------- */\r
- struct Reg_vendor_st reg18;\r
-/* --------------------------------------------------------- */\r
- struct Reg_vendor_st reg19;\r
-/* --------------------------------------------------------- */\r
- struct Reg_vendor_st reg20;\r
-/* --------------------------------------------------------- */\r
- struct Reg_vendor_st reg21;\r
-/* --------------------------------------------------------- */\r
- struct Reg22_st reg22;\r
-/* --------------------------------------------------------- */\r
- struct Reg23_st reg23;\r
-/* --------------------------------------------------------- */\r
- struct Reg24_st reg24;\r
-/* --------------------------------------------------------- */\r
- struct Reg25_st reg25;\r
-/* --------------------------------------------------------- */\r
- struct Reg26_st reg26;\r
-/* --------------------------------------------------------- */\r
- struct Reg27_st reg27;\r
-/* --------------------------------------------------------- */\r
- struct Reg28_bridge_st reg28;\r
-/* --------------------------------------------------------- */\r
- struct Reg29_bridge_st reg29;\r
-/* --------------------------------------------------------- */\r
- struct Reg30_bridge_st reg30;\r
-/* --------------------------------------------------------- */\r
- struct Reg31_bridge_st reg31;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct FW_IMAGE_st { /* Little Endian */\r
- pseudo_bit_t FIA[0x00020]; /* FW image address */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t LOG_DEV_SIZE[0x00020]; /* Log device size */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ROM[0x00020]; /* Expansion ROM offset */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t LAST[0x00020]; /* Last address read */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t START[0x00020]; /* Offset of static configuration in NVRAM */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t RET[0x00020]; /* Used by flash loader */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* DIMM info from DMU discovery */\r
-\r
-struct DIMM_REQ_st { /* Little Endian */\r
- pseudo_bit_t OFFSET[0x00020]; /* offset in CR-space */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t BAR[0x00020]; /* bar for this DIMM (bit[0] = dimm_en) */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t MASK[0x00020]; /* mask for this DIMM (-size) */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct DIMM_SYND_st { /* Little Endian */\r
- pseudo_bit_t SYND[0x00004]; /* Error syndrome */\r
- pseudo_bit_t reserved0[0x0001c];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Loader command interface. Built to match kast word of HCR */\r
-\r
-struct LOADER_CMD_IF_st { /* Little Endian */\r
- pseudo_bit_t opcode[0x0000c];\r
- pseudo_bit_t opcode_modifier[0x00004];\r
- pseudo_bit_t reserved0[0x00006];\r
- pseudo_bit_t e[0x00001];\r
- pseudo_bit_t go[0x00001];\r
- pseudo_bit_t status[0x00008];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Translate CAS latency from bit number to JEDEC encoding */\r
-\r
-struct CAS_TABLE_st { /* Little Endian */\r
- pseudo_bit_t CL1_0[0x00020]; /* CAS Latency = 1.0 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CL1_5[0x00020]; /* CAS Latency = 1.5 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CL2_0[0x00020]; /* CAS Latency = 2 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CL2_5[0x00020]; /* CAS Latency = 2.5 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CL3_0[0x00020]; /* CAS Latency = 3 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CL3_5[0x00020]; /* CAS Latency = 3.5 */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Table to translate Refresh Period to DRAM clock units\r
- 10000 * (val: usec) * dram_frequency / 10000 + 1 */\r
-\r
-struct TAR_TABLE_st { /* Little Endian */\r
- pseudo_bit_t NORMAL[0x00020]; /* Normal (15.625 usec) */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t REDUCED_25x[0x00020]; /* Reduced (.25x)... 3.9 usec */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t REDUCED_5x[0x00020]; /* Reduced (.5x) ... 7.8 usec */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t EXTENDED_2x[0x00020]; /* Extended (2x) ... 31.3 usec */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t EXTENDED_4x[0x00020]; /* Extended (4x) ... 62.5 usec */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t EXTENDED_8x[0x00020]; /* Extended (8x) ... 125 usec */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct FW_TRACE_MASK_L_st { /* Little Endian */\r
- pseudo_bit_t DB[0x00001]; /* Doorbells */\r
- pseudo_bit_t CMD_IF[0x00001]; /* Cmd I/F */\r
- pseudo_bit_t BP[0x00001]; /* Firmware Break Points */\r
- pseudo_bit_t CM[0x00001]; /* Internal Cache Misses */\r
- pseudo_bit_t MAD[0x00001]; /* MAD */\r
- pseudo_bit_t QP_FLUSH[0x00001]; /* QP Flush */\r
- pseudo_bit_t SCHD[0x00001]; /* Scheduler */\r
- pseudo_bit_t IT_INT[0x00001]; /* IR Interrupt */\r
- pseudo_bit_t TPT_XLATE[0x00001]; /* TPT Access */\r
- pseudo_bit_t INFO[0x00001]; /* Miscellaneous Info */\r
- pseudo_bit_t reserved0[0x00015];\r
- pseudo_bit_t DEBUG[0x00001]; /* DEBUG Msg. Not in release. */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* SDRAM Device Attributes: General */\r
-\r
-struct DEVATTR_st { /* Little Endian */\r
- pseudo_bit_t WEAKDRV[0x00001]; /* Includes Weak Driver */\r
- pseudo_bit_t QFC[0x00001]; /* Includes QFC Output */\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t reserved1[0x00001];\r
- pseudo_bit_t LOWVDD[0x00001]; /* Lower VDD tolerance: 0 = 0.2V 1 = TBD */\r
- pseudo_bit_t UPVDD[0x00001]; /* Upper VDD tolerance: 0 = 0.2V 1 = TBD */\r
- pseudo_bit_t CONCAP[0x00001]; /* Concurrent Auto- Precharge */\r
- pseudo_bit_t FASTAP[0x00001]; /* Supports Fast AP: 0 = tRAP is tRAS; 1 = tRAP is tRCD */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Depicts various aspects of the module */\r
-\r
-struct MODATTR_st { /* Little Endian */\r
- pseudo_bit_t BUF[0x00001]; /* Buffered address and control inputs */\r
- pseudo_bit_t REG[0x00001]; /* Registered address and control inputs */\r
- pseudo_bit_t PLL[0x00001]; /* On card PLL (Clock) */\r
- pseudo_bit_t FETCE[0x00001]; /* FET Switch On-Card enable */\r
- pseudo_bit_t FETEE[0x00001]; /* FET Switch External enable */\r
- pseudo_bit_t DIFCLK[0x00001]; /* Differential Clock Input */\r
- pseudo_bit_t reserved0[0x00002];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Which of the programmable CAS latencies (CAS to data out) are acceptable for the SDRAM devices used on the module. */\r
-\r
-struct CASLAT_st { /* Little Endian */\r
- pseudo_bit_t CL1_0[0x00001]; /* CAS Latency = 1 */\r
- pseudo_bit_t CL1_5[0x00001]; /* CAS Latency = 1.5 */\r
- pseudo_bit_t CL2_0[0x00001]; /* CAS Latency = 2 */\r
- pseudo_bit_t CL2_5[0x00001]; /* CAS Latency = 2.5 */\r
- pseudo_bit_t CL3_0[0x00001]; /* CAS Latency = 3 */\r
- pseudo_bit_t CL3_5[0x00001]; /* CAS Latency = 3.5 */\r
- pseudo_bit_t reserved0[0x00002];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* SDRAMs width */\r
-\r
-struct WIDTH_st { /* Little Endian */\r
- pseudo_bit_t PRIMARY[0x00007]; /* Indicates the primary width of the SDRAMs */\r
- pseudo_bit_t FLAG[0x00001]; /* Flag which is set to 1 when there is a second physical bank on the module which is of different size from the first physical bank (the second physical bank's SDRAMs are 2X the width of those on the first physical bank). */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* This byte describes the module's refresh rate and type. */\r
-\r
-struct REFRESH_st { /* Little Endian */\r
- pseudo_bit_t RATE[0x00007]; /* Refresh rate */\r
- pseudo_bit_t SLFR[0x00001]; /* Self refresh flag */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Number of addresses for physical banks 1/2 */\r
-\r
-struct NALEN_st { /* Little Endian */\r
- pseudo_bit_t BANK1[0x00004]; /* If there is one physical bank on the module or if there are two physical banks of the same size and organization, represents the number of addresses for each physical bank. If the module has two physical banks of asymmetric size, represents the number of addresses for physical bank 1 */\r
- pseudo_bit_t BANK2[0x00004]; /* If the module has two physical banks of asymmetric size, represents the number of row addresses for physical bank 2 */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct MSIX_TableEntry_st { /* Little Endian */\r
- pseudo_bit_t Msg_Addr[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Msg_Upper_Addr[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Msg_Data[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Vector_Control[0x00020];/* Only low bit is meaningful */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TCU Packet Buffer Debug */\r
-\r
-struct TCUPBDEBUG_st { /* Little Endian */\r
- pseudo_bit_t pb_lines[0x00009]; /* packet buffer lines in use */\r
- pseudo_bit_t reserved0[0x00017];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TCU Packet Checks Payload Debug */\r
-\r
-struct TCUDIPYLDDEBUG_st { /* Little Endian */\r
- pseudo_bit_t di_header_ngrh_ps[0x00005];/* header_ngrh_ps state */\r
- pseudo_bit_t reserved0[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t di_header_ygrh_ps[0x00005];/* header_ygrh_ps state */\r
- pseudo_bit_t reserved1[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t wait4credits_ps[0x00001];/* wait4credits_ps state */\r
- pseudo_bit_t reserved2[0x0001f];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TCU Packet Checks TCUDICMD Debug */\r
-\r
-struct TCUDICMDDEBUG_st { /* Little Endian */\r
- pseudo_bit_t popcmd_ps[0x00001]; /* popcmd_ps state */\r
- pseudo_bit_t reserved0[0x0001f];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TCU Packet Checks TCUTCQPCWR Debug */\r
-\r
-struct TCUTCQPCWRDEBUG_st { /* Little Endian */\r
- pseudo_bit_t qpcwr_ps[0x00004]; /* qpcwr_ps state */\r
- pseudo_bit_t reserved0[0x0001c];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TCU Packet Checks TCUTCQPCRD Debug */\r
-\r
-struct TCUTCQPCRDDEBUG_st { /* Little Endian */\r
- pseudo_bit_t qpcrd_ps[0x00002]; /* qpcrd_ps state */\r
- pseudo_bit_t reserved0[0x0001e];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TCU Packet Checks Header Debug */\r
-\r
-struct TCUTCHEADERDEBUG_st { /* Little Endian */\r
- pseudo_bit_t hdr_header_ngrh_ps[0x00005];/* header_ngrh_ps state */\r
- pseudo_bit_t reserved0[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t hdr_header_ygrh_ps[0x00005];/* header_ygrh_ps state */\r
- pseudo_bit_t reserved1[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t multicast_ps[0x00001]; /* multicast_ps state */\r
- pseudo_bit_t real_dqp_reg[0x00018]; /* real qp number from packet in the case of qp0, qp1, qp = ffffff */\r
- pseudo_bit_t reserved2[0x00007];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TCU Packet Checks TCUTCCHKDI Debug */\r
-\r
-struct TCUTCCHKDI_st { /* Little Endian */\r
- pseudo_bit_t cmd_ctr[0x00004]; /* command send to RDE command fifo counter */\r
- pseudo_bit_t dicmddest_ps[0x00001]; /* dicmddest_ps state */\r
- pseudo_bit_t dicmd_ps[0x00001]; /* dicmd_ps state */\r
- pseudo_bit_t dipyldest_ps[0x00001]; /* dipyldest_ps state */\r
- pseudo_bit_t reserved0[0x00019];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @TCU Packet Checker Debug */\r
-\r
-struct TCUTCCHKER_st { /* Little Endian */\r
- pseudo_bit_t drop_count[0x00020]; /* drop packets counter */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t checker_ps[0x00001]; /* checker_ps state */\r
- pseudo_bit_t reserved0[0x0001f];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TCU Packet Checks QP2EE Debug */\r
-\r
-struct TCUTCQP2EEDEBUG_st { /* Little Endian */\r
- pseudo_bit_t qp2ee_ps[0x00003]; /* qp2ee_ps state */\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t qp_not_exists_ff[0x00001];/* qp_not_exists_ff */\r
- pseudo_bit_t qp_ts_is_not_rd_ff[0x00001];/* qp_ts_is_not_rd_ff */\r
- pseudo_bit_t qp_state_is_not_ok_ff[0x00001];/* qp_state_is_not_ok_ff */\r
- pseudo_bit_t qp_locked_ff[0x00001]; /* qp_locked_ff */\r
- pseudo_bit_t ee_not_exists_ff[0x00001];/* ee_not_exists_ff */\r
- pseudo_bit_t rdd_miss_ff[0x00001]; /* rdd_miss_ff */\r
- pseudo_bit_t ee_last_op_not_last_ff[0x00001];/* ee_last_op_not_last_ff */\r
- pseudo_bit_t ee_lapsn_not_fits_epsn_ff[0x00001];/* ee_lapsn_not_fits_epsn_ff */\r
- pseudo_bit_t packet_psn_not_fits_epsn_ff[0x00001];/* packet_psn_not_fits_epsn_ff */\r
- pseudo_bit_t reserved1[0x00013];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TCU Packet Checks TCUCLI Debug */\r
-\r
-struct TCUCLIDEBUG_st { /* Little Endian */\r
- pseudo_bit_t txinprgrs_ps[0x00002]; /* txinprgrs_ps state */\r
- pseudo_bit_t drdy_1st_ps[0x00001]; /* drdy_1st_ps state */\r
- pseudo_bit_t cldataen_ps[0x00001]; /* cldataen_ps state */\r
- pseudo_bit_t reserved0[0x0001c];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct EXT_CAUSEREG_st { /* Little Endian */\r
- pseudo_bit_t clrcause[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t setcause[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t evtserviced[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t evtena0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t evtena1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00040];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Completion Engine Debug Status Registers */\r
-\r
-struct CEDEBUG_st { /* Little Endian */\r
- struct CECOREDEBUG_st cecoredebug; /* core debug */\r
-/* --------------------------------------------------------- */\r
- struct CENSWRDEBUG_st censwr1debug; /* nswr debug */\r
-/* --------------------------------------------------------- */\r
- struct CENSWRDEBUG_st censwr2debug; /* nswr debug */\r
-/* --------------------------------------------------------- */\r
- struct CEINRDEDEBUG_st ceinrdedebug;/* ceinrde debug */\r
-/* --------------------------------------------------------- */\r
- struct CEINFIFODEBUG_st ceinfifodebug;/* cein fifo debug */\r
-/* --------------------------------------------------------- */\r
- struct CEINSTAGEDEBUG_st ceinstagedebug;/* ceinstage debug */\r
-/* --------------------------------------------------------- */\r
- struct CELDBDEBUG_st celdbdebug; /* celdb debug */\r
-/* --------------------------------------------------------- */\r
- struct CETPTDEBUG_st cetptdebug; /* cetpt debug */\r
-/* --------------------------------------------------------- */\r
- struct CENSIDEBUG_st censidebug; /* censi debug */\r
-/* --------------------------------------------------------- */\r
- struct CEEVENTDEBUG_st ceeventdebug;/* ceevent debug */\r
-/* --------------------------------------------------------- */\r
- struct CECCDEBUG_st ceccdebug; /* cecc debug */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x005c0];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* CE Gateway for Exe to TCU (Farewell for Diego) */\r
-\r
-struct TCUCEEXEGW_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x0001d];\r
- pseudo_bit_t ceexegwctl[0x00003]; /* Control register:\r
- 31 - Semaphore\r
- 30 - Busy\r
- 29 - Cmd: go */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ceexegw0[0x00009]; /* 8 - EE/QP#\r
- 7:0 - QP[23:16] if RD Bind */\r
- pseudo_bit_t reserved1[0x00017];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ceexegw1[0x00020]; /* 31:16 - QP[15:0] if RD Bind\r
- 15:0 - QP[23:8]/EE[23:8] number */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ceexegw2[0x00020]; /* 31:24 - QP[7:0]/EE[7:0]\r
- 23:0 - CQ[23:0]\r
- */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Completion Engine General Configuration */\r
-\r
-struct CEGRLCFG_st { /* Little Endian */\r
- struct CECORECFG_st cecorecfg; /* ce core cfg */\r
-/* --------------------------------------------------------- */\r
- struct CENSWRCFG_st censwr1cfg; /* nswr clear */\r
-/* --------------------------------------------------------- */\r
- struct CENSWRCFG_st censwr2cfg; /* nswr clear */\r
-/* --------------------------------------------------------- */\r
- struct CECQCCFG_st cecqccfg; /* CQC cfg */\r
-/* --------------------------------------------------------- */\r
- struct CEINFIFOCFG_st ceinfifocfg;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00100];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Completion Engine LDB Entry */\r
-\r
-struct CELDB_st { /* Little Endian */\r
- pseudo_bit_t ldbsyndrome[0x00008]; /* The LDB entry syndrome */\r
- pseudo_bit_t ldbpsn[0x00018]; /* PSN this LDB entry relates to */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ldbdessize[0x00006]; /* LDB entry descriptor size (NDS) */\r
- pseudo_bit_t ldbdesaddr[0x0001a]; /* LDB entry descriptor address (NDA) */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ldbopcode[0x00005]; /* Descriptor opcode format */\r
- pseudo_bit_t ldbunreliable[0x00001];/* unreliable bit */\r
- pseudo_bit_t ldbsigcomp[0x00001]; /* signalled completion */\r
- pseudo_bit_t ldbeventreq[0x00001]; /* event request */\r
- pseudo_bit_t reserved0[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Completion Engine CQ Entry */\r
-\r
-struct CECQC_st { /* Little Endian */\r
- pseudo_bit_t cccqbaseaddr_63_32[0x00020];/* cq base address [58:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00005];\r
- pseudo_bit_t cccqbaseaddr31_5[0x0001b];/* cq base address [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cccqlkey[0x00020]; /* cq L-Key */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cceqn[0x00008]; /* event Q number */\r
- pseudo_bit_t ccpd[0x00018]; /* protection domain */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ccproduceridx[0x00020];/* Producer Index of the CQ */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ccconsumneridx[0x00020];/* CQ's Consumer pointer */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ccstatus[0x00008]; /* cq status */\r
- pseudo_bit_t cccqsize[0x00005]; /* cq size */\r
- pseudo_bit_t ccldtseqid[0x00006]; /* LDT sequence id */\r
- pseudo_bit_t cctr[0x00001]; /* translation required */\r
- pseudo_bit_t ccvl[0x00001]; /* vl */\r
- pseudo_bit_t ccnp[0x00001]; /* non-posted */\r
- pseudo_bit_t cccqbreakpoint[0x00001];/* BreakPoint indication on this CQ */\r
- pseudo_bit_t ccignoreoverrun[0x00001];/* ignore overrun bit */\r
- pseudo_bit_t ccstc[0x00002]; /* stc */\r
- pseudo_bit_t ccsts[0x00002]; /* sts */\r
- pseudo_bit_t reserved1[0x00003];\r
- pseudo_bit_t cclock[0x00001]; /* cqc is locked bit */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Completion Engine Input FIFO Entry */\r
-\r
-struct CEINFIFO_st { /* Little Endian */\r
- pseudo_bit_t ceincqn[0x00018]; /* CQ number this entry relates to */\r
- pseudo_bit_t ceinopcode[0x00008]; /* Opcode */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ceinqpn[0x00018]; /* QP number this entry relates to. */\r
- pseudo_bit_t ceinsyndrome[0x00008]; /* The syndrome of this entry */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ceindesctr[0x00020]; /* descriptor ptr */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ceinnbbytes[0x00020]; /* number of bytes transfered */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ceinimmdt[0x00020]; /* immediate value */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ceineen[0x00018]; /* ee context */\r
- pseudo_bit_t ceindlid[0x00007]; /* destination LID */\r
- pseudo_bit_t ceingrh[0x00001]; /* grh bit */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ceinsqpn[0x00018]; /* source qp number */\r
- pseudo_bit_t ceinde[0x00001]; /* descriptor event bit */\r
- pseudo_bit_t ceinsl[0x00004]; /* sl */\r
- pseudo_bit_t ceinsrc[0x00002]; /* 00 - RDE\r
- 10-EXE with QP\r
- 11-EXE with EE (this is bind on RD) */\r
- pseudo_bit_t ceinse[0x00001]; /* Solicited Event bit */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ceinpsn[0x00018]; /* psn */\r
- pseudo_bit_t reserved0[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ceinslid[0x00010]; /* source LID */\r
- pseudo_bit_t reserved1[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x000e0];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Multicast Cache QPN Table */\r
-\r
-struct MCCACHEQPN_st { /* Little Endian */\r
- pseudo_bit_t qpn00[0x00018]; /* qp number */\r
- pseudo_bit_t reserved0[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpn01[0x00018]; /* qp number */\r
- pseudo_bit_t reserved1[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpn02[0x00018]; /* qp number */\r
- pseudo_bit_t reserved2[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpn03[0x00018]; /* qp number */\r
- pseudo_bit_t reserved3[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpn04[0x00018]; /* qp number */\r
- pseudo_bit_t reserved4[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpn05[0x00018]; /* qp number */\r
- pseudo_bit_t reserved5[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpn06[0x00018]; /* qp number */\r
- pseudo_bit_t reserved6[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpn07[0x00018]; /* qp number */\r
- pseudo_bit_t reserved7[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpn08[0x00018]; /* qp number */\r
- pseudo_bit_t reserved8[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpn09[0x00018]; /* qp number */\r
- pseudo_bit_t reserved9[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpn10[0x00018]; /* qp number */\r
- pseudo_bit_t reserved10[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpn11[0x00018]; /* qp number */\r
- pseudo_bit_t reserved11[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpn12[0x00018]; /* qp number */\r
- pseudo_bit_t reserved12[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpn13[0x00018]; /* qp number */\r
- pseudo_bit_t reserved13[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpn14[0x00018]; /* qp number */\r
- pseudo_bit_t reserved14[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpn15[0x00018]; /* qp number */\r
- pseudo_bit_t reserved15[0x00008];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Multicast Cache GID Entry */\r
-\r
-struct MCCACHEGID_st { /* Little Endian */\r
- pseudo_bit_t gidh[0x00008]; /* Scope and Flag bits of GID */\r
- pseudo_bit_t reserved0[0x00017];\r
- pseudo_bit_t v[0x00001]; /* multicast entry is valid */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gidl[0x00020]; /* GID [31:0] */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @tcutcdigw ram */\r
-\r
-struct TCUDIGWRAM_st { /* Little Endian */\r
- pseudo_bit_t line0w0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line0w1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line1w0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line1w1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line2w0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line2w1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line3w0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line3w1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line4w0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line4w1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line5w0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line5w1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line6w0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line6w1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line7w0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line7w1[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TCU Packet Injection Gateway Control */\r
-\r
-struct TCUTCDIGW_st { /* Little Endian */\r
- pseudo_bit_t pkt_len[0x0000b]; /* packet length */\r
- pseudo_bit_t cmd[0x00012]; /* command to digw\r
- // 1. If destination is RDE\r
- //\r
- // ------------------------------------------------------------------------------------------------------------\r
- -------------------------------------------------------------------\r
- // | V | RESERVED | No PYLD | CMD destination | PYLD DESTINATION (source of data,destination of data) | RESERVE\r
- D |\r
- // ------------------------------------------------------------------------------------------------------------\r
- -------------------------------------------------------------------\r
- // 28 27:19 18 17:16 15:12 (15,14:12) 11\r
- //\r
- //\r
- // V - command is valid bit\r
- //\r
- // No PYLD - if set no push to pyld destination will be done\r
- //\r
- // PYLD DEST Parameters:\r
- // Destination\r
- // parameter DCRD = 3'b000; // Discard - Not valid from EB\r
- // parameter RDNG = 3'b001; // RDE, no GRH scatter\r
- // parameter RDYG = 3'b010; // RDE, GRH scatter\r
- // parameter EBMV = 3'b011; // EB - Not valid from EB\r
- // Source\r
- // parameter PBS = 1'b0; // source is PB\r
- // parameter EBS = 1'b1; // source is EB\r
-\r
- // CMD destination Parameters:\r
- //////////////////////////////\r
- //parameter NOCOMND = 2'b00; // no command (pyld will be discard) - Not valid from EB\r
- //parameter RDEATOM = 2'b01; // atomic request\r
- //parameter RDENATM = 2'b11; // no atomic request\r
-\r
- //\r
- // 2. If destination is CLI\r
- //\r
- // --------------------------------------\r
- // | LMC | STATUS (erorr , port number) |\r
- // --------------------------------------\r
- // 28:26 25:11 (25:15 , 14:11)\r
- */\r
- pseudo_bit_t dest[0x00001]; /* destination bit: CLI or RDE\r
- 0 - RDE\r
- 1 - CLI\r
- */\r
- pseudo_bit_t b[0x00001]; /* busy bit */\r
- pseudo_bit_t s[0x00001]; /* s bit */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* QPC Line */\r
-\r
-struct QPCLINE_st { /* Little Endian */\r
- pseudo_bit_t line_127_96_[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line_95_64_[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line_63_32_[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line_31_0_[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* QPC Command Header */\r
-\r
-struct QPC_command_header_st { /* Little Endian */\r
- pseudo_bit_t Token[0x00010];\r
- pseudo_bit_t Condition[0x00008];\r
- pseudo_bit_t CL[0x00003]; /* condition line */\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t WordSel[0x00002]; /* Word selector for condition evaluation.\r
- 00 - selected word = line[31:0]\r
- 01 - selected word = line[63:32]\r
- 10 - selected word = line[95:64]\r
- 11 - selected word = line[127:96] */\r
- pseudo_bit_t TimerState[0x00002]; /* State for Timer FSM. (Updated only by ERP) */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Mask[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CompareOperand[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t QPN[0x00018]; /* QPN- QP/EEC number. */\r
- pseudo_bit_t EE[0x00001]; /* `0': QP , `1':EE */\r
- pseudo_bit_t reserved1[0x00003];\r
- pseudo_bit_t Interrupt[0x00001];\r
- pseudo_bit_t reserved2[0x00003];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t OPLE[0x00008]; /* OpLE - Opcode Line Enable */\r
- pseudo_bit_t Opcode[0x00008]; /* HW Defined Opcodes:\r
- QPC_OPCODE_READ 0x41\r
- QPC_OPCODE_WRITE 0X81\r
- QPC_OPCODE_START_TIMER 0x02\r
- QPC_OPCODE_RESET_TIMER 0x03\r
- QPC_OPCODE_STOP_TIMER 0x04\r
- QPC_OPCODE_WRITE_TIMER 0x05\r
- QPC_OPCODE_ADD 0x82\r
- QPC_OPCODE_SUB 0x83\r
- QPC_OPCODE_AND 0x84\r
- QPC_OPCODE_OR 0x85\r
- QPC_OPCODE_XOR 0x86\r
- QPC_OPCODE_FETCH_ADD 0xc2\r
- QPC_OPCODE_FETCH_SUB 0xc3\r
- QPC_OPCODE_FETCH_AND 0xc4\r
- QPC_OPCODE_FETCH_OR 0xc5\r
- QPC_OPCODE_FETCH_XOR 0xc6\r
-\r
- FW Defined Opcodes (processed by FW through miss processing):\r
- QPC_OPCODE_CE 0x06\r
- QPC_OPCODE_WRITE_BACK_OP 0xc7\r
- QPC_OPCODE_HW2SW_EQ 0xc8\r
- QPC_OPCODE_SW2HW_EQ 0xc9\r
- QPC_OPCODE_MAP_EQ 0xca\r
- QPC_OPCODE_QUERY_EQC 0xcb\r
- QPC_OPCODE_UAR_BASE_ADX 0xcc\r
- QPC_OPCODE_EQC_TABLE_BASE_ADX 0xcd\r
- */\r
- pseudo_bit_t reserved3[0x00010];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* GID */\r
-\r
-struct GID_st { /* Little Endian */\r
- pseudo_bit_t gid_127_96_[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gid_95_64_[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gid_63_32_[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gid_31_0_[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Trapped Incoming Packet Link Layer Check Info */\r
-\r
-struct IBTCUdata_st { /* Little Endian */\r
- pseudo_bit_t portid[0x00004]; /* port number of the current packet */\r
- pseudo_bit_t ib_pktlen[0x0000b]; /* real packet length (as count in the CLI) */\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t ib_lmc[0x00003]; /* LMC of the current packet */\r
- pseudo_bit_t reserved1[0x00001];\r
- pseudo_bit_t ib_error_reg[0x0000b]; /* link errors (ib_status [14:4]) */\r
- pseudo_bit_t reserved2[0x00001];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Trapped Incoming Packet immDt Field */\r
-\r
-struct immDt_st { /* Little Endian */\r
- pseudo_bit_t immdt[0x00020]; /* immediate data */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Trapped Incoming Packet AtomicAckETH Fields */\r
-\r
-struct AtomicAckETH_st { /* Little Endian */\r
- pseudo_bit_t atmackh[0x00020]; /* original remote data [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t atmackl[0x00020]; /* original remote data [31:0] */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Trapped Incoming Packet AETH Fields */\r
-\r
-struct AETH_st { /* Little Endian */\r
- pseudo_bit_t msn[0x00018]; /* MSN */\r
- pseudo_bit_t syndrome[0x00008]; /* syndrome */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Trapped Incoming Packet AtomicETH Fields */\r
-\r
-struct AtomicETH_st { /* Little Endian */\r
- pseudo_bit_t vahi[0x00020]; /* virtual address [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t valo[0x00020]; /* virtual address [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t r_key[0x00020]; /* remote key */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t swaph[0x00020]; /* swap or add data [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t swapl[0x00020]; /* swap or add data [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cmph[0x00020]; /* compare data [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cmpl[0x00020]; /* compare data [31:0] */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Trapped Incoming Packet RETH Fields */\r
-\r
-struct RETH_st { /* Little Endian */\r
- pseudo_bit_t vahi[0x00020]; /* virtual address [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t valo[0x00020]; /* virtual address [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t r_key[0x00020]; /* remote key */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t dmalen[0x00020]; /* DMA length */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Trapped Incoming Packet DETH Fields */\r
-\r
-struct DETH_st { /* Little Endian */\r
- pseudo_bit_t qkey[0x00020]; /* Queue key */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sqp[0x00018]; /* source qp */\r
- pseudo_bit_t reserved0[0x00008];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Trapped Incoming Packet RDEHT Fields */\r
-\r
-struct RDETH_st { /* Little Endian */\r
- pseudo_bit_t eecnxt[0x00018]; /* EE-context */\r
- pseudo_bit_t reserved0[0x00008];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Trapped Incoming Packet BTH Fields */\r
-\r
-struct BTH_st { /* Little Endian */\r
- pseudo_bit_t p_key[0x00010]; /* patition key */\r
- pseudo_bit_t tver[0x00004]; /* TVER */\r
- pseudo_bit_t pad[0x00002]; /* pad count */\r
- pseudo_bit_t migreq[0x00001]; /* migreq */\r
- pseudo_bit_t se[0x00001]; /* solicited event */\r
- pseudo_bit_t opcode[0x00008]; /* opcode */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t dqp[0x00018]; /* destination qp */\r
- pseudo_bit_t reserved0[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t psn[0x00018]; /* PSN */\r
- pseudo_bit_t reserved1[0x00007];\r
- pseudo_bit_t ackreq[0x00001]; /* acknowledge request */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Trapped Incoming Packet GRH Fields */\r
-\r
-struct GRH_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00014];\r
- pseudo_bit_t tclass[0x00008]; /* traffic class */\r
- pseudo_bit_t ipver[0x00004]; /* IP version */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00008];\r
- pseudo_bit_t nxthdr[0x00008]; /* next header */\r
- pseudo_bit_t reserved2[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sgid_127_96[0x00020]; /* source GID [127:96] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sgid_95_64[0x00020]; /* source GID [95:64] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sgid_63_32[0x00020]; /* source GID [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sgid_31_0[0x00020]; /* source GID [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t dgid_127_96[0x00020]; /* destination GID [127:96] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t dgid_95_64[0x00020]; /* destination GID [95:64] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t dgid_63_32[0x00020]; /* destination GID [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t dgid_31_0[0x00020]; /* destination GID [31:0] */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Trapped Incoming Packet LRH Fields */\r
-\r
-struct LRH_st { /* Little Endian */\r
- pseudo_bit_t dlid[0x00010]; /* destination local id */\r
- pseudo_bit_t lnh[0x00002]; /* link next header */\r
- pseudo_bit_t reserved0[0x00002];\r
- pseudo_bit_t sl[0x00004]; /* service level */\r
- pseudo_bit_t reserved1[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t slid[0x00010]; /* source local id */\r
- pseudo_bit_t pkt_pktlen[0x0000b]; /* packet length as written in the LRH field */\r
- pseudo_bit_t reserved2[0x00005];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* RD Responder Copy QP to EE Machine Configuration */\r
-\r
-struct TCUTCQP2EE_st { /* Little Endian */\r
- pseudo_bit_t cs_syndrome_only[0x00001];/* if set qp2ee mechine will return only syndrome if copy has failed. if reset the mechine will return data strb as required with the syndrome. */\r
- pseudo_bit_t cs_ignore_a_w_r_copy[0x00001];/* when copy qp to ee , if set the fields A W and R will not be copy. */\r
- pseudo_bit_t cs_ignore_maxmsgsize_copy[0x00001];/* ignore max message size when copy qp to ee */\r
- pseudo_bit_t reserved0[0x0001d];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TCU CLI Packet Input Control */\r
-\r
-struct TCUTCCLI_st { /* Little Endian */\r
- pseudo_bit_t tcucli_erplock[0x00001];/* lock cli fron getting packets from CLI */\r
- pseudo_bit_t cli_is_locked_reg[0x00001];/* cli is lock indication */\r
- pseudo_bit_t reserved0[0x0001e];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TCU CLI */\r
-\r
-struct TCUCLI_st { /* Little Endian */\r
- pseudo_bit_t cfg_cli_no_pre_dlast[0x00001];/* not doing pre dlast "bring packet" */\r
- pseudo_bit_t reserved0[0x00003];\r
- pseudo_bit_t cfg_cli_drdy2dataen[0x00004];/* number of cycles for pre dlast operation */\r
- pseudo_bit_t reserved1[0x00018];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TCU Packet Checks Configuration */\r
-\r
-struct TCUTCCFG_st { /* Little Endian */\r
- pseudo_bit_t cfg_gid_prefix_63_32[0x00020];/* cfg gid prefix [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_gid_prefix_31_0[0x00020];/* cfg gid prefix [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_nxthdr[0x00008]; /* cfg nxthdr */\r
- pseudo_bit_t cfg_ipver[0x00004]; /* cfg ipver */\r
- pseudo_bit_t reserved0[0x00014];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_qp0[0x00018]; /* qp0 number - Replaces the QP number for packets destined to QP0. Packets coming from IB port1 will go to qp0_number, packets coming from IB port 2 will go to qp0_number + 1\r
-\r
- * Dest QP should not be configured to zero, see bug 4984 */\r
- pseudo_bit_t reserved1[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_qp1[0x00018]; /* qp1 number\r
-\r
- * Dest QP should not be configured to zero, see bug 4984 */\r
- pseudo_bit_t reserved2[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_unlock_timer[0x00010];/* cfg unlock timer. the time tcu wait before re-reading QPC because QP was locked. */\r
- pseudo_bit_t cfg_retry_counter[0x00010];/* number of retries in the case of qp is lock. If 0 then the retry counter is disable */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_mc_qp[0x00018]; /* cfg multicast qp tp change in the case of no multicast cache hit\r
-\r
- * Dest QP should not be configured to zero, see bug 4984 */\r
- pseudo_bit_t reserved3[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TCU Initial Credits */\r
-\r
-struct TCUINITCREDITS_st { /* Little Endian */\r
- pseudo_bit_t rde_pyld_credits[0x0000c];/* credits to RDE pyld fifo */\r
- pseudo_bit_t reserved0[0x00014];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rde_cmd_cred[0x00007]; /* credits to RDE command fifo */\r
- pseudo_bit_t reserved1[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pb_credits[0x00008]; /* PB credits to CLI */\r
- pseudo_bit_t reserved2[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sqpc_credits[0x00005]; /* credits for SQPC */\r
- pseudo_bit_t reserved3[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rqpc_credits[0x00005]; /* credits to RQPC */\r
- pseudo_bit_t reserved4[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_digw_initial_credits[0x00008];/* Intial credits to statrt pushing new packet to PB by TCUCLI. after starting pushing the packet, this value is not relevant. */\r
- pseudo_bit_t reserved5[0x00008];\r
- pseudo_bit_t cfg_digw_enough_credits[0x00008];/* the value that mean "zero" credits of PB. */\r
- pseudo_bit_t reserved6[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x00040];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* tcu checks cause data0 */\r
-\r
-struct TCUCHKCAUSE_REG3_st { /* Little Endian */\r
- pseudo_bit_t bad_syn_rnrnack[0x00001];\r
- pseudo_bit_t bad_syn_psn_seq_err[0x00001];\r
- pseudo_bit_t bad_syn_inv_req[0x00001];\r
- pseudo_bit_t bad_syn_rae[0x00001];\r
- pseudo_bit_t bad_syn_roe[0x00001];\r
- pseudo_bit_t bad_syn_inv_rd_req[0x00001];\r
- pseudo_bit_t bad_malformed_synd[0x00001];\r
- pseudo_bit_t bad_rdres_syn[0x00001];\r
- pseudo_bit_t reserved0[0x00018];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* tcu checks cause data0 */\r
-\r
-struct TCUCHKCAUSE_REG2_st { /* Little Endian */\r
- pseudo_bit_t bad_rel_dupl_psn[0x00001];\r
- pseudo_bit_t bad_rel_inv_psn[0x00001];\r
- pseudo_bit_t bad_qp2ee_eepsnerr[0x00001];\r
- pseudo_bit_t bad_qpstate_bit_req[0x00001];\r
- pseudo_bit_t bad_eestate_bit_req[0x00001];\r
- pseudo_bit_t bad_xxstate_psn_req[0x00001];\r
- pseudo_bit_t bad_req_supp_rel[0x00001];\r
- pseudo_bit_t bad_unrel_inv_psn[0x00001];\r
- pseudo_bit_t bad_uc_epsn[0x00001];\r
- pseudo_bit_t bad_ud_epsn[0x00001];\r
- pseudo_bit_t bad_req_supp_unrel[0x00001];\r
- pseudo_bit_t bad_opc_req_seq[0x00001];\r
- pseudo_bit_t bad_payload_req_pkt[0x00001];\r
- pseudo_bit_t bad_req_padcount[0x00001];\r
- pseudo_bit_t bad_e2ecredits_unrel[0x00001];\r
- pseudo_bit_t bad_e2ecredits_rel[0x00001];\r
- pseudo_bit_t bad_ghost_resp[0x00001];\r
- pseudo_bit_t unsolicited_ack[0x00001];\r
- pseudo_bit_t bad_qpstate_bit_res[0x00001];\r
- pseudo_bit_t bad_eestate_bit_res[0x00001];\r
- pseudo_bit_t bad_rdrsp_trash[0x00001];\r
- pseudo_bit_t bad_rdres_aack_mix[0x00001];\r
- pseudo_bit_t bad_opc_res_seq[0x00001];\r
- pseudo_bit_t bad_rsp_supp[0x00001];\r
- pseudo_bit_t bad_payload_res_pkt[0x00001];\r
- pseudo_bit_t bad_res_padcount[0x00001];\r
- pseudo_bit_t bad_rdrsp_implnck[0x00001];\r
- pseudo_bit_t bad_ack_implnck[0x00001];\r
- pseudo_bit_t reserved0[0x00004];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* tcu checks cause data0 */\r
-\r
-struct TCUCHKCAUSE_REG1_st { /* Little Endian */\r
- pseudo_bit_t bad_exception_qp[0x00001];\r
- pseudo_bit_t qp_is_qp1[0x00001];\r
- pseudo_bit_t qp_is_qp0[0x00001];\r
- pseudo_bit_t bad_opcode_int_erp[0x00001];\r
- pseudo_bit_t bad_router_packet[0x00001];\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t reserved1[0x00001];\r
- pseudo_bit_t bad_no_qpcrd[0x00001];\r
- pseudo_bit_t bad_qp2ee_eeisbusy[0x00001];\r
- pseudo_bit_t bad_migreq[0x00001];\r
- pseudo_bit_t bad_mygid_nrd[0x00001];\r
- pseudo_bit_t bad_rmtgid_nrd[0x00001];\r
- pseudo_bit_t bad_mylid_nrd[0x00001];\r
- pseudo_bit_t bad_rmtlid_nrd[0x00001];\r
- pseudo_bit_t bad_grhen[0x00001];\r
- pseudo_bit_t bad_qp2ee_qpnvalid[0x00001];\r
- pseudo_bit_t bad_qp2ee_qpstate[0x00001];\r
- pseudo_bit_t bad_qp2ee_rddmiss[0x00001];\r
- pseudo_bit_t bad_qp2ee_qptsnrd[0x00001];\r
- pseudo_bit_t bad_qp_is_lock[0x00001];\r
- pseudo_bit_t bad_eedestqp[0x00001];\r
- pseudo_bit_t bad_eesource[0x00001];\r
- pseudo_bit_t bad_mygid_rd[0x00001];\r
- pseudo_bit_t bad_rmtgid_rd[0x00001];\r
- pseudo_bit_t bad_mylid_rd[0x00001];\r
- pseudo_bit_t bad_rmtlid_rd[0x00001];\r
- pseudo_bit_t bad_pkey[0x00001];\r
- pseudo_bit_t bad_qkey[0x00001];\r
- pseudo_bit_t bad_multicast_pkt[0x00001];\r
- pseudo_bit_t bad_multicast_match[0x00001];\r
- pseudo_bit_t reserved2[0x00002];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* tcu checks cause data0 */\r
-\r
-struct TCUCHKCAUSE_REG0_st { /* Little Endian */\r
- pseudo_bit_t packet_is_raw_ipv6[0x00001];\r
- pseudo_bit_t packet_is_raw_ethertype[0x00001];\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t reserved1[0x00001];\r
- pseudo_bit_t bad_lrh_rsv[0x00001];\r
- pseudo_bit_t bad_pktlen[0x00001];\r
- pseudo_bit_t bad_icrc[0x00001];\r
- pseudo_bit_t bad_cli_check[0x00001];\r
- pseudo_bit_t bad_nxthdr[0x00001];\r
- pseudo_bit_t bad_ipver[0x00001];\r
- pseudo_bit_t bad_no_bth[0x00001];\r
- pseudo_bit_t bad_tver[0x00001];\r
- pseudo_bit_t bad_bth_rsv_var[0x00001];\r
- pseudo_bit_t bad_bth_rsv[0x00001];\r
- pseudo_bit_t bad_malformed_packet[0x00001];\r
- pseudo_bit_t bad_portid[0x00001];\r
- pseudo_bit_t bad_opcode_int_drop[0x00001];\r
- pseudo_bit_t bad_qpvalid[0x00001];\r
- pseudo_bit_t bad_qpstate[0x00001];\r
- pseudo_bit_t bad_opcode_ts[0x00001];\r
- pseudo_bit_t bad_eevalid[0x00001];\r
- pseudo_bit_t bad_eestate[0x00001];\r
- pseudo_bit_t bad_qp2ee_eenvalid[0x00001];\r
- pseudo_bit_t bad_qp2ee_eestate[0x00001];\r
- pseudo_bit_t reserved2[0x00001];\r
- pseudo_bit_t reserved3[0x00001];\r
- pseudo_bit_t reserved4[0x00001];\r
- pseudo_bit_t reserved5[0x00001];\r
- pseudo_bit_t reserved6[0x00001];\r
- pseudo_bit_t reserved7[0x00001];\r
- pseudo_bit_t reserved8[0x00001];\r
- pseudo_bit_t reserved9[0x00001];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* iRISC Debug Hooks */\r
-\r
-struct IRISCDEBUG_st { /* Little Endian */\r
- struct debug_bits_st debug; /* Debug hooks control and status */\r
-/* --------------------------------------------------------- */\r
- struct debug_bits_st setdebug; /* Set Debug hooks */\r
-/* --------------------------------------------------------- */\r
- struct debug_bits_st cleardebug; /* Clear Debug hooks */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t dbg_code[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t f_ip[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t last_e_ip[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Inter iRisc Communication FIFO */\r
-\r
-struct IPCFIFO_st { /* Little Endian */\r
- struct FIFOCONTROL_st ipcfifopushctrl;/* state field holds the number of free entries in the fifo */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ipcfifopushdata[0x00020];/* writing to this register, advances the fifo write pointer */\r
-/* --------------------------------------------------------- */\r
- struct Irisc_pop_fifo_ctrl_st ipcfifopopctrl;/* state field holds number of used entries in the fifo */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ipcfifopopdata[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* InfiniRISC Breakpoint */\r
-\r
-struct IRiscBP_st { /* Little Endian */\r
- pseudo_bit_t address[0x00020]; /* breakpoint address (see mask field) */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mask[0x00006]; /* Breakpoint is set to address specified in address field masked with 2^mask */\r
- pseudo_bit_t reserved0[0x00019];\r
- pseudo_bit_t valid[0x00001]; /* If set then breakpoint is valid */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct CCR_st { /* Little Endian */\r
- pseudo_bit_t cczero[0x00001]; /* Zero */\r
- pseudo_bit_t ccsl[0x00001]; /* Signed Less Than */\r
- pseudo_bit_t ccsg[0x00001]; /* Signed Greater Than */\r
- pseudo_bit_t ccul[0x00001]; /* Unsigned Less Than */\r
- pseudo_bit_t ccug[0x00001]; /* Unisgned Greater Than */\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t ccpsn0[0x00001]; /* PZ: PSN is Zero */\r
- pseudo_bit_t ccpsndup[0x00001]; /* PL: PSN is duplicate (less than) */\r
- pseudo_bit_t ccpsnoos[0x00001]; /* PG: PSN is out of sequence (greater than) */\r
- pseudo_bit_t reserved1[0x00001];\r
- pseudo_bit_t ccfieleq[0x00001]; /* Field is Equal */\r
- pseudo_bit_t reserved2[0x00001];\r
- pseudo_bit_t ccrl[0x00001]; /* msb of last operation */\r
- pseudo_bit_t ccrg[0x00001];\r
- pseudo_bit_t reserved3[0x00001];\r
- pseudo_bit_t cccarryo[0x00001]; /* Carry Out */\r
- pseudo_bit_t reserved4[0x0000f];\r
- pseudo_bit_t cctrue[0x00001]; /* This bit is always 1 */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* iRISC Cache Gateway */\r
-\r
-struct IRISCCACHEGW_st { /* Little Endian */\r
- struct GWCONTROL_st irisc_cache_gateway_control;/* Gateway command\r
-\r
- 0x00 Reserved\r
- 0x01 Code Tag Read\r
- 0x02 Code Tag Write\r
- 0x03 Code Read\r
- 0x04 Code Write\r
- 0x05-0x10 Reserved\r
- 0x11 Data Tag Read\r
- 0x12 Data Tag Write\r
- 0x13 Data Read\r
- 0x14 Data Write\r
- 0x15 Data Force Writeback\r
- 0x16-0x3F Reserved\r
-\r
- Address:\r
- [23:20] Way\r
- [19:0] Address LSb (bits 0 and 1 are ignored)\r
-\r
- For Data/Code Read/Write:\r
- gwdata[31:12] is Tag\r
- gwdata[2] is Lock\r
- gwdata[1] is Dirty\r
- gwdata[0] is Valid */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gwdata[0x00020]; /* when accessing Cache Data: Data to writeTo/readFrom cache.\r
- when accessing Cache Tags: tag[31:3],lock[2],dirty[1],valid[0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x000c0];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Execution Engine Fetch Descriptor Controller */\r
-\r
-struct EXEFDESCCTL_st { /* Little Endian */\r
- pseudo_bit_t fetchnds_plus_1[0x00006];/* Size of next descriptor to be fetched plus 1 entry - Initialized to the QPCNDS+1 when the command given to the execution engine is "with clear".\r
- */\r
- pseudo_bit_t reserved0[0x0000a];\r
- pseudo_bit_t descwrptr[0x00006]; /* Descriptor write pointer within the descriptor fifo of the execution engine. (in units of 16 bytes). Should point to the entry above the first free entry in the FIFO. Initialized by HW when the command is "with clear". */\r
- pseudo_bit_t reserved1[0x00002];\r
- pseudo_bit_t descwrptr_firstentry[0x00006];/* Descriptor write pointer within the descriptor fifo of the execution engine. (in units of 16 bytes). Should point to the first free entry in the FIFO. Initialized by HW when the command is "with clear". */\r
- pseudo_bit_t reserved2[0x00002];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t usedcredits[0x00006]; /* Number of used entries in the execution engine descriptor fifo (in units of 16 bytes) */\r
- pseudo_bit_t reserved3[0x0000a];\r
- pseudo_bit_t ftcnotexe[0x00004]; /* Number of descriptors fectched not yet executed in engine descriptor fifo */\r
- pseudo_bit_t reserved4[0x0000c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t fetchnopcode[0x00005]; /* This field holds the opcode for the next to be fetched descriptor. - Initialized to the QPCNOPCODE when the command given to the execution engine is "with clear". */\r
- pseudo_bit_t reserved5[0x00001];\r
- pseudo_bit_t fetchnda[0x0001a]; /* Address of Next Descriptor to be Fecthed - Initialized to the QPCNDA when the command given to the execution engine is "with clear". */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t fetchnds[0x00006]; /* Size of next descriptor to be fetched - Initialized to the QPCNDS when the command given to the execution engine is "with clear".\r
- */\r
- pseudo_bit_t fetchndfence[0x00001]; /* Initialized to the QPCNDFence when the command given to the execution engine is "with clear". */\r
- pseudo_bit_t fetchnddbd[0x00001]; /* This bit is set when the next descriptor to be fecthed was doorbelled. - Initialized to the QPCNDDBD when the command given to the execution engine is "with clear". */\r
- pseudo_bit_t ndee[0x00018]; /* Address of Next EE (for RD QPs) - Initialized to the QPCNEE when the command given to the execution engine is "with clear". */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x0000d];\r
- pseudo_bit_t rbfentry[0x00003]; /* Responder Blue Flame Entry in the internal BF fifo number */\r
- pseudo_bit_t fetchdbcnt[0x00010]; /* fetch doorbell counter - Initialized to the QPCdbcnt when the command given to the execution engine is "with clear". */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x00060];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Execution Engine Status */\r
-\r
-struct EXESTATUS_st { /* Little Endian */\r
- pseudo_bit_t busy[0x00001]; /* Execution engine is processing */\r
- pseudo_bit_t ldbentryavail[0x00001];/* Execution engine has a reserved credit in the LDB */\r
- pseudo_bit_t reserved0[0x0001d];\r
- pseudo_bit_t nonsiouts[0x00001]; /* This bit is set by the hw when there are no outstanding transactions to the nsi. All translated addresses have completed their respective nsw transactions. Writes have been transmitted. Read responses have been received.\r
- Clearing the tpt_stop bit in the fetchertptnsiif, will clear this bit.\r
- Setting tpt_stop in the fetchertptnsiif, will cause this bit to become set after all outstanding transactions have been completed.\r
-\r
- * This bit is used for TPT Flush completion indication, see bug 5064 */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Execution Engine Event Cause Register */\r
-\r
-struct EXEEVTCAUSE_st { /* Little Endian */\r
- pseudo_bit_t dbcntzero[0x00001]; /* Doorbell counter reached zero. */\r
- pseudo_bit_t preempted[0x00001];\r
- pseudo_bit_t error[0x00001]; /* Error while processing last descriptor. Error details are in errorsyndrome field. */\r
- pseudo_bit_t nullndsreached[0x00001];/* Next Descriptor Size is Zero */\r
- pseudo_bit_t reserved0[0x00003];\r
- pseudo_bit_t desccompleted[0x00001];/* Descriptor completed - valid only for responder. For requester use gather length committed. (see bug 5195) */\r
- pseudo_bit_t reserved1[0x00005];\r
- pseudo_bit_t bindisbusy[0x00001]; /* Next descriptor is Bind and Bind machine is busy */\r
- pseudo_bit_t noldbcredits[0x00001]; /* No LDB credits */\r
- pseudo_bit_t noscatterentries[0x00001];/* Next descriptor is read and there are not enough scatter entries in RDE to store the read scatter list. */\r
- pseudo_bit_t reserved2[0x00004];\r
- pseudo_bit_t opcodebp[0x00001]; /* opcode breakpoint */\r
- pseudo_bit_t fenced[0x00001]; /* Next descriptor is fenced and there are outstanding reads/atomics */\r
- pseudo_bit_t nordrqcredits[0x00001];/* No available outstanding read/atomic credits */\r
- pseudo_bit_t noe2ecredits[0x00001]; /* No available end to end credits */\r
- pseudo_bit_t reserved3[0x00004];\r
- pseudo_bit_t exebquotadone[0x00001];/* Programmed number of bytes was sent */\r
- pseudo_bit_t exepquotadone[0x00001];/* Programmed number of packets was sent */\r
- pseudo_bit_t exedquotadone[0x00001];/* Programmed number of descriptors was executed. */\r
- pseudo_bit_t ftcdquotadone[0x00001];/* Programmed number of descriptors was fetched */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t eu_status[0x00008]; /* EXE FSMs state:\r
- 0 EU_EXE_IDLE EU is not is used! (not scheduled)\r
- 1 EU_EXE_CHK EU is scheduled. Checking if can exe more\r
- 2 EU_EXE_REQ EU is requesting exe from the exeer\r
- 3 EU_EXE_EXTING EU is waiting for a descriptor to arrive\r
- 4 EU_EXE_W4_DESC no descs ready for execution.\r
- 5 EU_EXE_W4_BIND Waiting for TPT to finish bind\r
- 6 EU_EXE_ERROR Error in descriptor defined in error_vector\r
- 7 EU_EXE_DONE EU has finished exeing (quota/NULL)\r
- */\r
- pseudo_bit_t eu_fetch_status[0x00008];/* EU Fetcher Status:\r
- 0 EU_IDLE EU is not is used! (not scheduled)\r
- 1 EU_SCHEDULED EU is scheduled. Checking if can fetch more\r
- 2 EU_FETCH_W4CRD EU limit not expired, but need credits\r
- 3 EU_FETCH_REQ EU is requesting fetch from the fetcher\r
- 4 EU_FETCH_WAIT EU is waiting for a descriptor to arrive\r
- 5 EU_FETCH_LMT EU has finished fetching (QUOTA)\r
- 6 EU_FETCH_ERR EU has finished fetching (ERROR)\r
- 7 EU_FETCH_DONE EU has finished fetching (NULL)\r
-\r
- */\r
- pseudo_bit_t reserved4[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t errorsyndrome[0x00008];/* Execution Engine Event Error Syndrome\r
-\r
- 0x00 Reserved\r
- 0x02-0x07 TPT Access Syndrome in Descriptor Address Translation (see TPT syndrome coding in TPT MAS):\r
- 0x02 - PD Violation\r
- 0x03 - Access Rights Violation\r
- 0x04 - Length Violation\r
- 0x05 - Cross Page Boundary Violation\r
- 0x06 - Master abort\r
- 0x07 - Reserved\r
- 0x08 Opcode not supported by QP Service Type (e.g. RDMAR in UD QP)\r
- 0x09 Opcode not supported by QP (A,W,R)\r
- 0x0A Too Short NDS (e.g. Atomic with NDS equal to 1)\r
- 0x0B Last Immdt descriptor segment length exceeds descriptor size.\r
- 0x0C Bus Error while reading descriptor\r
- 0x0D Immdt segment when scatter entry was expected (e.g. Immdt in RDMAR descriptor)\r
- 0x0E Total descriptor byte count exceeds QP.maxmsgsize\r
- 0x0F Reserved\r
- 0x11 WQE Reserved Opcode\r
- 0x12-0x13 Reserved\r
- 0x14 Gather Engine Error (see extended syndrome in gather engine register)\r
- 0x15 UD AV PD Miss\r
- 0x16 UD AV Port Miss\r
- 0x17 UD Msg is larger than AV.MTU\r
- 0x18-0xFF Reserved\r
- */\r
- pseudo_bit_t reserved6[0x00018];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Exe GID entry (not really BIG endian) */\r
-\r
-struct EXE_GID_st { /* Little Endian */\r
- pseudo_bit_t gid_31_0_[0x00020]; /* This field is write only, see bug 5134 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gid_63_32_[0x00020]; /* This field is write only, see bug 5134 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gid_95_64_[0x00020]; /* This field is write only, see bug 5134 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gid_127_96_[0x00020]; /* This field is write only, see bug 5134 */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Internal Doorbells FIFO */\r
-\r
-struct INTDBFIFO_st { /* Little Endian */\r
- struct DB_FIFOCNTL_st internal_db_fifo;/* internal db fifo controler */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t intdbdata[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* QP Doorbell FIFO */\r
-\r
-struct QPDBFIFO_st { /* Little Endian */\r
- struct DB_FIFOCNTL_st qf_fifo_cntl;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t fifodata0[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TPT/NSI Interface and Status */\r
-\r
-struct TPTNSIIF_st { /* Little Endian */\r
- pseudo_bit_t stoptptaccess[0x00001];/* When set, the engine will not request any further translation from the tpt. (used for tpt flush)\r
- TPT Flush completion indication is obtaind in the nonsiouts bit in the execution engine status. (see bug 5064) */\r
- pseudo_bit_t reserved0[0x0001f];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Gather Engine Internal Logic - GeCtor Status */\r
-\r
-struct GECTORSTAT_st { /* Little Endian */\r
- pseudo_bit_t packets_inflight[0x00008];/* how many packets ar inserted to LinklList waiting to come from mem */\r
- pseudo_bit_t walk_ps[0x00003]; /* LinkList walking State Machine */\r
- pseudo_bit_t reserved0[0x00005];\r
- pseudo_bit_t snd_packets[0x0000c]; /* how many packets got YesUcan and not yes sent Lreq */\r
- pseudo_bit_t cloreq_ps[0x00002]; /* CLO request FSM state */\r
- pseudo_bit_t reserved1[0x00002];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Gather Agent Internal Status */\r
-\r
-struct GASTAT_st { /* Little Endian */\r
- pseudo_bit_t gb_4kb_base_ptr[0x0000d];/* byte pointer in RAM of Gather Buffer */\r
- pseudo_bit_t reserved0[0x00003];\r
- pseudo_bit_t gb_read_addr[0x00008]; /* Gather Buffer read address in Gather agent (1 of 4) */\r
- pseudo_bit_t gdpf_wm1_ctr[0x00007]; /* GDPF words counter.... minus 1.... */\r
- pseudo_bit_t reserved1[0x00001];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* NTU Gateway Control Register */\r
-\r
-struct GWCONTROL_NTU_st { /* Little Endian */\r
- pseudo_bit_t gwaddress[0x00018];\r
- pseudo_bit_t gwcmd[0x00006]; /* Command/Status - Sw writes to this field the desired command. Hw executes the cmd and returns in this field the status of the operation. For details on commands and status, see instance description. */\r
- pseudo_bit_t gwbusy[0x00001]; /* Written to 1 by SW together with command to trigger\r
- HW. It is cleared by hw after completing the required\r
- operation and seting the status in the Command/Status\r
- field. */\r
- pseudo_bit_t gwlocked[0x00001]; /* Gateway Locked - This bit is set when the gw is being used by some enitity. Sw is required to read the gwcontrol field before using a gw. This field behaves as a semaphore, if it was cleared the read returns a 0 in this bit and the bit is set by the hw atomically. Every subsequent read access to the field will return 1 until the agent that locked the gw writes a zero. */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Performance counters interrupt info register */\r
-\r
-struct NTU_PERF_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t qac_en[0x00001]; /* QLT Access count enable */\r
- pseudo_bit_t reserved1[0x00003];\r
- pseudo_bit_t qac_rst[0x00001]; /* QLT Access count reset */\r
- pseudo_bit_t reserved2[0x00003];\r
- pseudo_bit_t qac_int_en[0x00001]; /* QLT Access count interrupt enable */\r
- pseudo_bit_t reserved3[0x00003];\r
- pseudo_bit_t qac_ovf[0x00001]; /* QLT Access count overflow (write 1 to clear) */\r
- pseudo_bit_t reserved4[0x00002];\r
- pseudo_bit_t qlt_acc_cnt_ind[0x00005];/* QLT Access count indication (EvCnt1) */\r
- pseudo_bit_t reserved5[0x0000b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qlt_acc_cnt[0x00020]; /* QLT Access Counter */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpw_lst_miss_time_en[0x00001];/* QPW Last Miss time enable */\r
- pseudo_bit_t qpw_acc_cnt_en[0x00001];/* QPW access count enable */\r
- pseudo_bit_t qpw_miss_cnt_en[0x00001];/* QLT Miss Count Enable */\r
- pseudo_bit_t reserved8[0x00001];\r
- pseudo_bit_t qpw_lst_miss_time_rst[0x00001];/* QPW Last Miss Time Reset */\r
- pseudo_bit_t qpw_acc_cnt_rst[0x00001];/* QPW Access Count Reset */\r
- pseudo_bit_t qpw_miss_cnt_rst[0x00001];/* QPW Miss Count Reset */\r
- pseudo_bit_t reserved9[0x00001];\r
- pseudo_bit_t qpw_lst_miss_time_int_en[0x00001];/* QPW Last Miss Time Interrupt Enable */\r
- pseudo_bit_t qpw_acc_time_int_en[0x00001];/* QPW Access Time Interrupt Enable */\r
- pseudo_bit_t qpw_miss_cnt_int_en[0x00001];/* QPW Miss Count Interrupt Enable */\r
- pseudo_bit_t reserved10[0x00001];\r
- pseudo_bit_t qpw_lst_miss_time_ovf[0x00001];/* QPW Last Miss Time Overflow (write 1 to clear) */\r
- pseudo_bit_t qpw_access_cnt_ovf[0x00001];/* QPW Access Count Overflow (write 1 to clear) */\r
- pseudo_bit_t qpw_miss_cnt_ovf[0x00001];/* QPW Miss Count Overflow (write 1 to clear) */\r
- pseudo_bit_t reserved11[0x00001];\r
- pseudo_bit_t qpw_acc_cnt_ind[0x00005];/* QPW Access Count Indication (EvCnt1) */\r
- pseudo_bit_t reserved12[0x00003];\r
- pseudo_bit_t qpw_miss_cnt_ind[0x00005];/* QPW Miss Count Indication (EvCnt2) */\r
- pseudo_bit_t reserved13[0x00003];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpw_lst_miss_time_cnt[0x00020];/* QPW Last Miss Time Counter */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpw_acc_cnt[0x00020]; /* QPW Access Counter */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpw_miss_cnt[0x00020]; /* QPW Miss Counter */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @COMPERRINFO */\r
-\r
-struct COMPERRINFO_st { /* Little Endian */\r
- pseudo_bit_t cmp_syndrom[0x00008];\r
- pseudo_bit_t cmp_c[0x00001];\r
- pseudo_bit_t reserved0[0x00015];\r
- pseudo_bit_t int_clr[0x00001];\r
- pseudo_bit_t int_set[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cmp_qpn[0x00018];\r
- pseudo_bit_t reserved1[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00040];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @QLTMISSINFO */\r
-\r
-struct QLTMISSINFO_st { /* Little Endian */\r
- pseudo_bit_t q_nsb_addr_63_32[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t q_nsb_addr_31_0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t q_segment[0x00008];\r
- pseudo_bit_t reserved0[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x000a0];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* dmu wr calib. paramters */\r
-\r
-struct DMUWRCLB_st { /* Little Endian */\r
- pseudo_bit_t wr_dqs_dly[0x00005]; /* the dly on the written data strob of byte number X\r
- */\r
- pseudo_bit_t wr_dq_dly[0x00005]; /* the dly on the written data of byte number X\r
- */\r
- pseudo_bit_t reserved0[0x00016];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* the rd dqs en calib.parameters */\r
-\r
-struct DmuRdDqsenClb_st { /* Little Endian */\r
- pseudo_bit_t dqs_dqsendly_str[0x00004];\r
- pseudo_bit_t dqs_dqsendly[0x00004];\r
- pseudo_bit_t dqs_dqsdly_wind[0x00005];\r
- pseudo_bit_t reserved0[0x00013];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00060];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* the rd calib param */\r
-\r
-struct DMURDDQSCLB_st { /* Little Endian */\r
- pseudo_bit_t dqs_dqsdly_str[0x00006];\r
- pseudo_bit_t dqs_dqsdly[0x00006];\r
- pseudo_bit_t dqs_dqsdc[0x00003];\r
- pseudo_bit_t dqs_dqsdly_wind[0x00007];\r
- pseudo_bit_t reserved0[0x0000a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* DIMM Timing Configuration */\r
-\r
-struct DIMM_timimg_config_st { /* Little Endian */\r
- pseudo_bit_t tmrd[0x00003]; /* more register set command cycle time */\r
- pseudo_bit_t tras[0x00004]; /* Active to precharge command. Available from SPD. */\r
- pseudo_bit_t trap[0x00003]; /* ????? */\r
- pseudo_bit_t trc[0x00004]; /* Active to active/auto refresh command period. . Available from SPD. */\r
- pseudo_bit_t trfc[0x00004]; /* Auto refresh to active/auto refresh command period. . Available from SPD. */\r
- pseudo_bit_t trp[0x00003]; /* Precharge command period. Available from SPD. */\r
- pseudo_bit_t trcd[0x00003]; /* Active to read or write delay. Available from SPD */\r
- pseudo_bit_t trrd[0x00003]; /* Active bank A to active bank B command. Available from SPD */\r
- pseudo_bit_t twr[0x00003]; /* Write recovery time */\r
- pseudo_bit_t twtr[0x00002]; /* Internal write to read command delay */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tdal[0x00004]; /* Auto precharge write recovery + precharge time */\r
- pseudo_bit_t mode_register[0x0000c];/* [2:0] - burst len\r
- [3:3] - type of burst (sequencial / interleaved)\r
- [6:4] - CAS latency\r
- [11:7] - Operating mode */\r
- pseudo_bit_t extended_mode_register[0x0000c];/* Defined in JEDEC spec.\r
- controls DLL, drive strength, QFC and operating mode . */\r
- pseudo_bit_t reserved0[0x00004];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00040];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* DIMM General Configuration Registers */\r
-\r
-struct DIMMGeneralConfig_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t stop[0x00001]; /* When asserted, all access to DIMM is stoped.\r
- the dimm will no performed any NSB request only ! */\r
- pseudo_bit_t add_mode[0x00002]; /* address mode -> how to take BA,RA,CA from the 64 bit NSB address */\r
- pseudo_bit_t init_mode[0x00002]; /* Which DIMM initialization sequence is used\r
- TBD */\r
- pseudo_bit_t ca_length[0x00004]; /* Column address length:\r
- 0000 - 7 bits length, 0001 - 8 bits length\r
- 0010 - 9 bits length, 0011 - 10 bits length\r
- 0100 - 11 bits length, 0101 - 12 bits length\r
- 0110 - 13 bits length, 0111 - 14 bits length\r
- 1000 - 15 bits length, 1001 - 16 bits length\r
-\r
- */\r
- pseudo_bit_t ra_length[0x00004]; /* Row address length:\r
- 0000 - 7 bits length, 0001 - 8 bits length\r
- 0010 - 9 bits length, 0011 - 10 bits length\r
- 0100 - 11 bits length, 0101 - 12 bits length\r
- 0110 - 13 bits length, 0111 - 14 bits length\r
- 1000 - 15 bits length, 1001 - 16 bits length\r
-\r
- */\r
- pseudo_bit_t width[0x00003]; /* DIMM Data width:\r
- 000 - x4\r
- 001 - x8\r
- 010 - x16\r
- 011 - x32\r
- other - reserved */\r
- pseudo_bit_t reserved1[0x0000f];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00060];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* DIMM Statistics Counters */\r
-\r
-struct DIMMStatistics_st { /* Little Endian */\r
- pseudo_bit_t DIMM_Hit_Counter[0x00020];/* 32 bit counter for the numer of hit accesses to this DIMM. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DIMM_miss_counter[0x00020];/* 32 bit counter for the numer of miss accesses to this DIMM. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DIMM_Precharge_counter[0x00020];/* 32 bit counter for the numer of precharge accesses to this DIMM. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DIMM_DI_errors_counter[0x00020];/* 32 bit counter for the numer of data integrity errors for this DIMM. */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Open Pages Monitoring Register */\r
-\r
-struct statistics_openpages_st { /* Little Endian */\r
- pseudo_bit_t static_clr_req[0x00001];/* when HIGH are the statistical counter are cleared. */\r
- pseudo_bit_t op_count[0x00004]; /* current number of open pages */\r
- pseudo_bit_t max_op_count[0x00004]; /* maximum number of open pages (since the last req) */\r
- pseudo_bit_t reserved0[0x00017];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @PCIX only. Attributes of the configuration transaction for futher sending Split Completion transaction via SWCYCLES port. */\r
-\r
-struct cfg_attributes_st { /* Little Endian */\r
- pseudo_bit_t secondary_bus_number[0x00008];/* Secondary Bus Number. This field is valid in the case of Configuration Type 0 commands and undefined in the case of Configuration Type 1 commands. */\r
- pseudo_bit_t reqfuncnum[0x00003]; /* Requestor's function number */\r
- pseudo_bit_t reqdevnum[0x00005]; /* Requestor's Device Number */\r
- pseudo_bit_t reqbusnum[0x00008]; /* Requestor's Bus Number */\r
- pseudo_bit_t tag[0x00005]; /* Requestor's Tag */\r
- pseudo_bit_t ro[0x00001]; /* Requestor's Relaxed Ordering bit. */\r
- pseudo_bit_t ns[0x00001]; /* Requestor's No Snoop bit */\r
- pseudo_bit_t reserved0[0x00001];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Software Generation of PCI Cycles Status */\r
-\r
-struct swcycle_internal_st { /* Little Endian */\r
- pseudo_bit_t swce_sc_tag[0x00005]; /* Tag, which SWCE uses to its transactions. */\r
- pseudo_bit_t port[0x00001]; /* pmu port number */\r
- pseudo_bit_t rest_pops[0x00002]; /* number of expected pops from pmu */\r
- pseudo_bit_t first_data[0x00001];\r
- pseudo_bit_t pt_sce_bit[0x00001];\r
- pseudo_bit_t exec_status[0x00002];\r
- pseudo_bit_t sense_ps[0x00002];\r
- pseudo_bit_t main_ps[0x00002];\r
- pseudo_bit_t curr_retry_counter[0x00008];\r
- pseudo_bit_t reserved0[0x00003];\r
- pseudo_bit_t rec_ta[0x00001];\r
- pseudo_bit_t rec_ma[0x00001];\r
- pseudo_bit_t rec_mdpe[0x00001];\r
- pseudo_bit_t reserved1[0x00002];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct pcu_gp_cfg_h1_st { /* Little Endian */\r
- pseudo_bit_t pmu_rd_ptr[0x00001];\r
- pseudo_bit_t gp_cfg2[0x00001];\r
- pseudo_bit_t ptu_rd_ptr[0x00001];\r
- pseudo_bit_t gp_cfg3[0x00005];\r
- pseudo_bit_t pmu_mask[0x00005];\r
- pseudo_bit_t gp_cfg4[0x00003];\r
- pseudo_bit_t ptu_mask[0x00010];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct pcu_gp_cfg_st { /* Little Endian */\r
- pseudo_bit_t array_redundency0[0x00008];/*\r
-\r
- 31 - Enable cfg_cycle engine. When cleared, cfg cycles respond with retry */\r
- pseudo_bit_t pcma_use_one_port[0x00001];\r
- pseudo_bit_t target_abort_on_be_ff[0x00001];\r
- pseudo_bit_t gp_cfg0[0x00003];\r
- pseudo_bit_t virtual_fifo_size[0x00003];\r
- pseudo_bit_t min_prefetch_timeout[0x00004];\r
- pseudo_bit_t nsbtx_sw_usr[0x00001];\r
- pseudo_bit_t pxm_frameoe_s_en[0x00001];\r
- pseudo_bit_t sw_100m_en[0x00001];\r
- pseudo_bit_t sw_100m[0x00001];\r
- pseudo_bit_t page_disc_en[0x00001];\r
- pseudo_bit_t bug5275[0x00001];\r
- pseudo_bit_t gp_cfg1[0x00005];\r
- pseudo_bit_t en_cfg_cycle_engine[0x00001];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* NSI Gateway RAM */\r
-\r
-struct NSIGWRAM_st { /* Little Endian */\r
- pseudo_bit_t nsi_buffer0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer2[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer3[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer4[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer5[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer6[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer7[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer8[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer9[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer10[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer11[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer12[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer13[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer14[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer15[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer16[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer17[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer18[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer19[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer20[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer21[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer22[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer23[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer24[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer25[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer26[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer27[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer28[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer29[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer30[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer31[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer32[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer33[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer34[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer35[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer36[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer37[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer38[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer39[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer40[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer41[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffe42[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer43[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer44[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer45[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer46[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer47[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer48[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer49[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer50[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer51[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer52[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer53[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer54[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer55[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer56[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer57[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer58[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer59[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer60[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer61[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer62[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_buffer63[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* NSI Gateway Extended Control */\r
-\r
-struct NSIGWEXTCTRL_st { /* Little Endian */\r
- pseudo_bit_t address_63_32[0x00020];/* see details in address_31_0 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t address_31_0[0x00020]; /* Cmd: Read/Write\r
- Address[63:0] is the selected address (key,pd,te,nsvl,np,va_pa,nsq fields are used)\r
-\r
- Cmd: ReadQP/WriteQP\r
- Address[63:32] is reserved.\r
- Address[23:0] is QP#\r
- Address[24] is 1 for EE, 0 to QP\r
- Address[26:25] is 01 for Send, 10 for Receive, 11 for Completion\r
- (relevant base address,key,pd,te,nsvl,np,va_pa, and nsq fields are taken from the qpchost registers)\r
- Address[31:27] - Reserved\r
-\r
- Cmd: Swap\r
- Address[63:32] is reserved.\r
- Address[9:0] is Offset to Cache Array\r
- Address[24:10] is Reserved\r
- Address[26:25] is 01 for Send, 10 for Receive, 11 for Completion\r
- Address[31:27] - Reserved\r
-\r
- Cmd: Transmit\r
- Address[63:48] is Token\r
- Address[47:40] is QPState\r
- Address[39:32] is Syndrome\r
- Address[15:0] is Line Enable\r
- Address[24:16] is Reserved\r
- Address[26:25] is 01 for Send, 10 for Receive, 11 for Completion\r
- Address[31:27] - Reserved\r
- */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t key[0x00020]; /* Key for TPT access. Used for the Read and Write commands\r
- For ReadQP and WriteQP commands the key field in the qpcbase registers is used */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pd[0x00018]; /* Protection Domain used for TPT access for Read and Write commands.\r
- For ReadQP and WriteQP commands the pd field in the qpcbase registers is used */\r
- pseudo_bit_t te[0x00001]; /* TPT Access Enabled - When set, the TPT will be accessed. When cleared, the address will be regarded as physical and the nsq field will be used to access the NSI. This bit is relevant for Read and Write. For ReadQP and WriteQP commands this te bit is not relevant (the te bit in the qpcbase registers is used) */\r
- pseudo_bit_t reserved0[0x00004];\r
- pseudo_bit_t va_pa[0x00001]; /* 1 = virtual address\r
- 0 = physical address\r
- This bit does not control wether TPT is accessed or not (this is done by the te field). If te is set, TPT will be accessed (regardless of va_pa value) for address decoding purposes.\r
- This bit is relevant for Read and Write. For ReadQP and WriteQP commands this va_pa bit is not relevant (the va_pa bit in the qpcbase registers is used)\r
- */\r
- pseudo_bit_t np[0x00001]; /* When set, NP bit is set in TPT access.\r
- This bit is relevant for Read and Write. For ReadQP and WriteQP commands this np bit is not relevant (the np bit in the qpcbase registers is used) */\r
- pseudo_bit_t nsvl[0x00001]; /* VL to use in North Switch\r
- This bit is relevant for Read and Write. For ReadQP and WriteQP commands this nsvl bit is not relevant (the nsvl bit in the qpcbase registers is used) */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsq_for_reads[0x00006];/* This field is used to access the NSI when the TPT is not used (te field is cleared).\r
- For ReadQP commands the nsq for reads field in the qpcbase registers is used (when relevant).\r
-\r
- {VL,Nswitch lane[1:0],Nswitch destination id[2:0]};\r
-\r
- VL 0 is regular memory access\r
- VL 1 is privileged access (cache replacements)\r
-\r
- LANE_POSTED = 2'b01;\r
- LANE_NONPOSTED = 2'b10;\r
- LANE_RESPONSE = 2'b11;\r
-\r
- NTU = 3'b000;\r
- PCU = 3'b100;\r
- DMU = 3'b001;\r
- HCA = 3'b011;\r
- */\r
- pseudo_bit_t reserved1[0x00002];\r
- pseudo_bit_t nsq_for_writes[0x00006];/* This field is used to access the NSI when the TPT is not used (te field is cleared).\r
- For WriteQP commands the nsq for writes field in the qpcbase registers is used (when relevant).\r
-\r
- {VL,Nswitch lane[1:0],Nswitch destination id[2:0]};\r
-\r
- VL 0 is regular memory access\r
- VL 1 is privileged access (cache replacements)\r
-\r
- LANE_POSTED = 2'b01;\r
- LANE_NONPOSTED = 2'b10;\r
- LANE_RESPONSE = 2'b11;\r
-\r
- NTU = 3'b000;\r
- PCU = 3'b100;\r
- DMU = 3'b001;\r
- HCA = 3'b011;\r
- */\r
- pseudo_bit_t reserved2[0x00001];\r
- pseudo_bit_t mem_io[0x00001]; /* mem/io bit to be used in the NSI transaction if the te bit is cleared (no tpt access)\r
- mem = 0\r
- i/o = 1 */\r
- pseudo_bit_t nsi_syndrome[0x00008];\r
- pseudo_bit_t reserved3[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_token[0x00010];\r
- pseudo_bit_t reserved4[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t size[0x00010];\r
- pseudo_bit_t offset[0x00004]; /* offset within the data buffer (in units of 16 bytes)\r
- offset must be aligned to size */\r
- pseudo_bit_t reserved5[0x0000c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* NSI Gateway Main Control */\r
-\r
-struct NSIGWCTRL_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00018];\r
- pseudo_bit_t gwcmd[0x00006]; /* Command/Status - Sw writes to this field the desired command. Hw executes the cmd and returns in this field the status of the operation. For details on commands and status, see instance description. */\r
- pseudo_bit_t gwbusy[0x00001]; /* When set, it means the hw is executing a command. It is set by hw when the cmd field is written to a value different than zero. It is cleared by hw after completing the required operation and seting the status in the cmd field. */\r
- pseudo_bit_t gwlocked[0x00001]; /* Gateway Locked - This bit is set when the gw is being used by some enitity. Sw is required to read the gwcontrol field before using a gw. This field behaves as a semaphore, if it was cleared the read returns a 0 in this bit and the bit is set by the hw atomically. Every subsequent read access to the field will return 1 until the agent that locked the gw writes a zero. */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct STD_QC_FSMS_st { /* Little Endian */\r
- pseudo_bit_t ts_ps[0x00001];\r
- pseudo_bit_t gw_ps_tag[0x00002];\r
- pseudo_bit_t exe_ps[0x00002];\r
- pseudo_bit_t miss_exe_ps[0x00002];\r
- pseudo_bit_t srw_ps[0x00001];\r
- pseudo_bit_t qpc_core_ps[0x00004]; /* IDELL = 4'b0000\r
- DECOD = 4'b0001\r
- ERROR = 4'b0010\r
- MISSS = 4'b0011\r
- W4SLT = 4'b0100\r
- RDMW0 = 4'b0101\r
- GNCON = 4'b0110\r
- RDMW1 = 4'b0111\r
- GNEVL = 4'b1000\r
- WDRAN = 4'b1001\r
- EVALT = 4'b1010\r
- PREVL = 4'b1011 */\r
- pseudo_bit_t misdrn_ps[0x00002];\r
- pseudo_bit_t hoq_ps[0x00002]; /* IDLE = 2'b00\r
- HEDR = 2'b01\r
- DATA = 2'b10 */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct timeoutfifoctrl_st { /* Little Endian */\r
- pseudo_bit_t full[0x00001];\r
- pseudo_bit_t almost_full[0x00001];\r
- pseudo_bit_t empty[0x00001];\r
- pseudo_bit_t almost_empty[0x00001];\r
- pseudo_bit_t reserved0[0x00014];\r
- pseudo_bit_t pop[0x00001];\r
- pseudo_bit_t poprd[0x00001];\r
- pseudo_bit_t reserved1[0x00005];\r
- pseudo_bit_t fifolocked[0x00001];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Context Cache Set Lock Control */\r
-\r
-struct QCGATEKEEPER_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x000c0];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GK63_32[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GK31_0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x000c0];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CGK1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CGK0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x000c0];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SGK1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SGK0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t stop[0x00001]; /* stops all sets (see bug 5168) */\r
- pseudo_bit_t reserved3[0x0001f];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t af_level[0x00005]; /* Miss FIFO almost full watermark.\r
- When Miss FIFO reaches almost full watermark, input to the cache is closed for all sets. After Miss FIFO has reached almost\r
- full watermark, 12 more lines can be pushed.\r
- If this field is configured to 1, then cache operates as a blocking cache (ie every miss locks all sets). */\r
- pseudo_bit_t reserved4[0x00003];\r
- pseudo_bit_t ae_level[0x00005]; /* Miss FIFO almost level watermark. */\r
- pseudo_bit_t reserved5[0x00013];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t clear_gk_all[0x00001]; /* writing a one to this bit clears the blocking gatekeeper function (relevant only if af_level is 1) */\r
- pseudo_bit_t reserved6[0x0001f];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t set_gk_all[0x00001]; /* writing a one to this bit sets the blocking gatekeeper function (relevant only if af_level is 1) */\r
- pseudo_bit_t reserved7[0x0001f];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x00080];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Miss Reexecute Control */\r
-\r
-struct REEXEFSMCTL_st { /* Little Endian */\r
- pseudo_bit_t pipe_clean[0x00001]; /* This bit is never set, see bug 5168 */\r
- pseudo_bit_t reserved0[0x00017];\r
- pseudo_bit_t cmd[0x00006];\r
- pseudo_bit_t busy[0x00001];\r
- pseudo_bit_t reserved1[0x00001];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* OpcodeMask of QPC */\r
-\r
-struct QC_OP_MASK_st { /* Little Endian */\r
- pseudo_bit_t fetch_and_xor[0x00001];\r
- pseudo_bit_t fetch_and_or[0x00001];\r
- pseudo_bit_t fetch_and_and[0x00001];\r
- pseudo_bit_t fetch_and_sub[0x00001];\r
- pseudo_bit_t fetch_and_add[0x00001];\r
- pseudo_bit_t xor[0x00001];\r
- pseudo_bit_t or[0x00001];\r
- pseudo_bit_t and[0x00001];\r
- pseudo_bit_t sub[0x00001];\r
- pseudo_bit_t add[0x00001];\r
- pseudo_bit_t write_timer[0x00001];\r
- pseudo_bit_t stop_timer[0x00001];\r
- pseudo_bit_t reset_timer[0x00001];\r
- pseudo_bit_t start_timer[0x00001];\r
- pseudo_bit_t write[0x00001];\r
- pseudo_bit_t read[0x00001];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Context Cache Tag Access Gateway */\r
-\r
-struct QCTAGGW_st { /* Little Endian */\r
- pseudo_bit_t Address[0x0000a];\r
- pseudo_bit_t reserved0[0x0000e];\r
- pseudo_bit_t gwcmd[0x00006];\r
- pseudo_bit_t gwbusy[0x00001];\r
- pseudo_bit_t gwlocked[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00006];\r
- pseudo_bit_t tag[0x00012];\r
- pseudo_bit_t reserved2[0x00005];\r
- pseudo_bit_t qe[0x00001];\r
- pseudo_bit_t v[0x00001];\r
- pseudo_bit_t eq[0x00001];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Context Miss Gateway */\r
-\r
-struct QCMISSGW_st { /* Little Endian */\r
- pseudo_bit_t full[0x00001];\r
- pseudo_bit_t af[0x00001]; /* Allmost Full */\r
- pseudo_bit_t e[0x00001]; /* empty */\r
- pseudo_bit_t ae[0x00001]; /* almost empty */\r
- pseudo_bit_t reserved0[0x00004];\r
- pseudo_bit_t num_of_lines[0x00006];\r
- pseudo_bit_t reserved1[0x0000a];\r
- pseudo_bit_t pop[0x00001];\r
- pseudo_bit_t poprd[0x00001];\r
- pseudo_bit_t reserved2[0x00005];\r
- pseudo_bit_t gwlocked[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t miss0[0x00020]; /* bit 31:19 reserved\r
- bit 18 - hit\r
- bit 17 - locked\r
- bit 16 - opcode2irisc\r
- */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t miss1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t miss2[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t miss3[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t miss4[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Context Cache Array Access Gateway */\r
-\r
-struct QCGW_st { /* Little Endian */\r
- pseudo_bit_t Address[0x0000d];\r
- pseudo_bit_t reserved0[0x0000b];\r
- pseudo_bit_t gwcmd[0x00006];\r
- pseudo_bit_t gwbusy[0x00001];\r
- pseudo_bit_t gwlocked[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gwdata0[0x00020]; /* Line[127:96] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gwdata1[0x00020]; /* Line[95:64] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gwdata2[0x00020]; /* Line[63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gwdata3[0x00020]; /* Line[31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ByteEnable[0x00010]; /* bit 15 - is for Line[127:120]\r
- bit 14 - is for Line[119:112]\r
- .\r
- .\r
- bit 0 - is for Line[7:0] */\r
- pseudo_bit_t reserved1[0x00010];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* CQ FIFO Control Register */\r
-\r
-struct CQFIFOGWCTL_st { /* Little Endian */\r
- pseudo_bit_t f[0x00001]; /* see tavor mas */\r
- pseudo_bit_t af[0x00001];\r
- pseudo_bit_t e[0x00001]; /* see tavor mas */\r
- pseudo_bit_t ae[0x00001]; /* see tavor mas */\r
- pseudo_bit_t reserved0[0x00004];\r
- pseudo_bit_t depth_0_7[0x00007]; /* depth in units of 32 bit. If 128, check f bit. */\r
- pseudo_bit_t last_pop[0x00001]; /* 1 if last POP, 0 if last PUSH */\r
- pseudo_bit_t reserved1[0x00008];\r
- pseudo_bit_t pop[0x00001];\r
- pseudo_bit_t poprd[0x00001];\r
- pseudo_bit_t reserved2[0x00005];\r
- pseudo_bit_t fifolocked[0x00001];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct EXUR_SCRPAD_st { /* Little Endian */\r
- pseudo_bit_t word[54][0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DB_DROP[0x00020]; /* Number of times DB was dropped */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CHECK_STACK[0x00020]; /* Write to memory at this address means stack overflow */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DEBUG[8][0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct EXUS_SCRPAD_st { /* Little Endian */\r
- pseudo_bit_t word[53][0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SUPER_DB[0x00020]; /* how many times Super DB succeeded */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DB_DROP[0x00020]; /* Number of times DB was dropped */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CHECK_STACK[0x00020]; /* Write to memory at this address means stack overflow */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DEBUG[8][0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct TCU_SCRPAD_st { /* Little Endian */\r
- pseudo_bit_t word[50][0x00020]; /* instead of RESERVED 248 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t MILI_SEC[0x00020]; /* value to set to timer to count milisecs */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t TCU_INT_CNT[0x00020]; /* Counter for debug */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DB_DROP[0x00020]; /* Number of times DB was dropped */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t UD_DROP[0x00020]; /* Number of times DB was dropped */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t UC_DROP[0x00020]; /* Number of times DB was dropped */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CHECK_STACK[0x00020]; /* Write to memory at this address means stack overflow */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DEBUG[8][0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct QPC_SCRPAD_st { /* Little Endian */\r
- pseudo_bit_t word[50][0x00020];\r
-/* --------------------------------------------------------- */\r
- struct QPC_Performance_Counters_st CNTR;/* QPC Performance counters */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ERR_SYN[0x00020]; /* Last error syndrome */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DB_DROP[0x00020]; /* Number of times DB was dropped */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CHECK_STACK[0x00020]; /* Write to memory at this address means stack overflow */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DEBUG[8][0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct NTU_SCRPAD_st { /* Little Endian */\r
- pseudo_bit_t word[54][0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SCRUBB_COUNTER[0x00020];/* Counts the number of times scrubbing was called. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t PERIODIC_COUNTER[0x00020];/* Counts the number of times FW read the whiole DDR. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CHECK_STACK[0x00020]; /* Write to memory at this address means stack overflow */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DEBUG[7][0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct TPT_SCRPAD_st { /* Little Endian */\r
- pseudo_bit_t apm_req_qpn[0x00020]; /* TPT pass QPN for APM request */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00260];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t NSIGW_UNLOCK[0x00020]; /* TPT shall unlock NSIGW when busy goes to 0 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t word[32][0x00020]; /* instead of RESERVED 248 */\r
-/* --------------------------------------------------------- */\r
- struct TPT_Performance_Counters_st CNTR;/* TPT Performance counters */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CHECK_STACK[0x00020]; /* Write to memory at this address means stack overflow */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DEBUG[8][0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* BOOT2 Scratch pad params */\r
-\r
-struct BOOT2_SCRPAD_st { /* Little Endian */\r
- pseudo_bit_t DIMM_SLV[4][0x00020]; /* DIMM slv addr info: 0x50 0x52 0x51 0x53 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t XSR_ICLK_WAIT[0x00020];/* How many iclocks we need to wait after exit self refresh. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t FAST_SR[0x00020]; /* fast self sefresh feature */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t NS_TO_CLOCKS[0x00020]; /* 0x82518 bits 0-4 ns/10 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t TACTUAL[0x00020]; /* DRAM clock, units: Bits 0-3: 0.1 ns; Bits 4-7: ns (round up) */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t NS_TO_8K_CLOCKS[0x00020];/* 10 * dram_frequency * 8K / 10000 */\r
-/* --------------------------------------------------------- */\r
- struct TAR_TABLE_st TAR_TABLE; /* Translates Refresh Period to DRAM clock */\r
-/* --------------------------------------------------------- */\r
- struct CAS_TABLE_st CAS_TABLE; /* Translates CAS latency to JEDEC encoding */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DIMM_TYPE[4][0x00020]; /* DIMM type supported by this slot: 1-unbuffered,2-registered, 3-both (3 2 3 2) */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t TACTUAL_DOWN[0x00020]; /* DRAM clock, units of 0.25 ns (round down) */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x002a0];\r
-/* --------------------------------------------------------- */\r
- struct LOADER_CMD_IF_st LOADER_CMD_IF;\r
-/* --------------------------------------------------------- */\r
- struct DIMM_SYND_st DIMM_SYND[4]; /* DIMM syndrome */\r
-/* --------------------------------------------------------- */\r
- struct DIMM_REQ_st DIMM_REQ[4]; /* DIMM Info from DMU discovery */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DOOR_BELL[0x00020]; /* Size of doorbell area (in units of 1M) */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DDR_SIZE_LIMIT[0x00020];/* Max supported total DDR size (units of 1M) */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t FW_SIZE[0x00020]; /* 0x82634 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DI_MODE[0x00020]; /* 0x82638 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t AP_MODE[0x00020]; /* 0x8263c */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x000a0];\r
-/* --------------------------------------------------------- */\r
- struct FW_IMAGE_st FW_IMAGE; /* Data on active FW image */\r
-/* --------------------------------------------------------- */\r
- struct Device_header_st SHRIMP_MASK_HEADER;/* 0x82838 .. 0x828bc */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x00080];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ACTUAL_DDR_SIZE_MSB[0x00020];/* 0x82700 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ACTUAL_DDR_SIZE_LSB[0x00020];/* 0x82704 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CALIB_STAT[0x00020]; /* 0x82708 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x00080];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SYSENA_SP[0x00020]; /* Used to store NTU stack pointer in SYSEN->SYSDIS */\r
-/* --------------------------------------------------------- */\r
- struct Bridge_header_st PCU_HEADER; /* 0x82720 .. 0x827a4 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved9[0x00040];\r
-/* --------------------------------------------------------- */\r
- struct Device_header_st HCA_HEADER; /* 0x827ac .. 0x82830 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved10[0x00040];\r
-/* --------------------------------------------------------- */\r
- struct Bridge_header_st B_MASK_HEADER;/* 0x82838 .. 0x828bc */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved11[0x00040];\r
-/* --------------------------------------------------------- */\r
- struct Device_header_st D_MASK_HEADER;/* 0x828c4 .. 0x82948 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved12[0x00040];\r
-/* --------------------------------------------------------- */\r
- struct Device_header_st SHRIMP_HEADER;/* 0x82950 .. 0x829d4 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved13[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DIMM_DISCOVERY_ERROR[0x00020];/* RO, for debugging */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DIMM_DISCOVERY_STAGE[0x00020];/* RO, for debugging */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t HIDE_DDR_EN[0x00020]; /* if eq 1 then we should hide the ddr */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Hidden_ddr_lsb[0x00020];/* 32 lsb bits of hidden ddr address */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Hidden_ddr_msb[0x00020];/* 32 msb bits of hidden ddr address */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DEBUG[5][0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct EQN_MAP_st { /* Little Endian */\r
- pseudo_bit_t eqn4type_3[0x00008];\r
- pseudo_bit_t eqn4type_2[0x00008];\r
- pseudo_bit_t eqn4type_1[0x00008];\r
- pseudo_bit_t eqn4type_0[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t eqn4type_7[0x00008];\r
- pseudo_bit_t eqn4type_6[0x00008];\r
- pseudo_bit_t eqn4type_5[0x00008];\r
- pseudo_bit_t eqn4type_4[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t eqn4type_B[0x00008];\r
- pseudo_bit_t eqn4type_A[0x00008];\r
- pseudo_bit_t eqn4type_9[0x00008];\r
- pseudo_bit_t eqn4type_8[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t eqn4type_F[0x00008];\r
- pseudo_bit_t eqn4type_E[0x00008];\r
- pseudo_bit_t eqn4type_D[0x00008];\r
- pseudo_bit_t eqn4type_C[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t eqn4type_13[0x00008];\r
- pseudo_bit_t eqn4type_12[0x00008];\r
- pseudo_bit_t eqn4type_11[0x00008];\r
- pseudo_bit_t eqn4type_10[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t eqn4type_17[0x00008];\r
- pseudo_bit_t eqn4type_16[0x00008];\r
- pseudo_bit_t eqn4type_15[0x00008];\r
- pseudo_bit_t eqn4type_14[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t eqn4type_1B[0x00008];\r
- pseudo_bit_t eqn4type_1A[0x00008];\r
- pseudo_bit_t eqn4type_19[0x00008];\r
- pseudo_bit_t eqn4type_18[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t eqn4type_1F[0x00008];\r
- pseudo_bit_t eqn4type_1E[0x00008];\r
- pseudo_bit_t eqn4type_1D[0x00008];\r
- pseudo_bit_t eqn4type_1C[0x00008];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct INIT_HCA_st { /* Little Endian */\r
- pseudo_bit_t eqpc_base_addr_h[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t eqpc_base_addr_l[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t eeec_base_addr_h[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t eeec_base_addr_l[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t eqc_base_addr_h[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t log_num_eq[0x00004];\r
- pseudo_bit_t reserved0[0x00002];\r
- pseudo_bit_t eqc_base_addr_l[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mc_base_addr_h[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mc_base_addr_l[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t log_mc_table_entry_sz[0x00010];\r
- pseudo_bit_t log_mc_table_sz[0x00005];\r
- pseudo_bit_t mc_hash_fn[0x00003];\r
- pseudo_bit_t reserved1[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mc_table_hash_sz[0x00011];\r
- pseudo_bit_t reserved2[0x0000f];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mtt_segment_sz[0x00003];/* Actual SegmentSize in bytes: 2^(6+mtt_segment_sz) */\r
- pseudo_bit_t pfto[0x00005]; /* PageFault TimeOut for RNR NAK */\r
- pseudo_bit_t reserved3[0x00012];\r
- pseudo_bit_t mtt_base_addr_l_31_26[0x00006];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t uar_scratch_base_addr_h[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t uar_scratch_base_addr_l[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t responder_exu[0x00010];/* how many exu engines are responder (0x0 => Auto(8)) */\r
- pseudo_bit_t wqe_quota[0x00010]; /* Max WQEs to execute per arbitration */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct FW_VERSION_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00010];\r
- pseudo_bit_t MAJOR[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SUBMINOR[0x00010];\r
- pseudo_bit_t MINOR[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00008];\r
- pseudo_bit_t Hour[0x00008];\r
- pseudo_bit_t Minutes[0x00008];\r
- pseudo_bit_t Seconds[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Day[0x00008];\r
- pseudo_bit_t Month[0x00008];\r
- pseudo_bit_t Year[0x00010];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct FW_TRACE_st { /* Little Endian */\r
- pseudo_bit_t FW_TRACE_MASK_H[0x00020];/* High mask. Unused. */\r
-/* --------------------------------------------------------- */\r
- struct FW_TRACE_MASK_L_st FW_TRACE_MASK_L;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t buf_trace_sz[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t EXU0_addr[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t EXU1_addr[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t TCU_addr[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t TPT_addr[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t QPC_addr[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t NTU_addr[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* SPD header (#Byte Function [Notes]) */\r
-\r
-struct SPDH_st { /* Little Endian */\r
- pseudo_bit_t NMANB[0x00008]; /* 0 Number of Serial PD Bytes written during module production[1] */\r
- pseudo_bit_t TSPDB[0x00008]; /* 1 Total number of Bytes in Serial PD device[2] */\r
- pseudo_bit_t TYPE[0x00008]; /* 2 Fundamental Memory Type (FPM, EDO, SDRAM &) */\r
- struct NALEN_st RALEN; /* 3 Number of Row Addresses on this assembly */\r
-/* --------------------------------------------------------- */\r
- struct NALEN_st CALEN; /* 4 Number of Column Addresses on this assembly */\r
- pseudo_bit_t NDIMMS[0x00008]; /* 5 Number of Physical Banks on DIMM */\r
- pseudo_bit_t DWIDTH[0x00010]; /* 6-7 Data Width of this assembly */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t VOLTL[0x00008]; /* 8 Voltage Interface Level of this assembly */\r
- pseudo_bit_t TCKCLX[0x00008]; /* 9 SDRAM Device Cycle time (t CK) at Maximum Supported CAS Latency (CL), CL=X[3] */\r
- pseudo_bit_t TACMAX[0x00008]; /* 10 SDRAM Device Access from Clock (t AC) at CLX */\r
- pseudo_bit_t CTYPE[0x00008]; /* 11 DIMM configuration type (Non-parity, Parity or ECC) */\r
-/* --------------------------------------------------------- */\r
- struct REFRESH_st REFRESH; /* 12 Refresh Rate/Type [3,4] */\r
- struct WIDTH_st DSDRAMW; /* 13 Data SDRAM Width */\r
- struct WIDTH_st ESDRAMW; /* 14 Error Checking SDRAM Width */\r
- pseudo_bit_t MINB2BC[0x00008]; /* 15 SDRAM Device Attributes: Minimum Clock Delay, Back-to-Back Random Column Access */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t BURSTLN[0x00008]; /* 16 SDRAM Device Attributes: Burst Lengths Supported */\r
- pseudo_bit_t NBANKS[0x00008]; /* 17 SDRAM Device Attributes: Number of Banks on SDRAM Device[3] */\r
- struct CASLAT_st CL; /* 18 SDRAM Device Attributes: CAS Latency[3] */\r
- pseudo_bit_t CSLAT[0x00008]; /* 19 SDRAM Device Attributes: Chip Select Latency[3] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t WRLAT[0x00008]; /* 20 SDRAM Device Attributes: Write Latency[3] */\r
- struct MODATTR_st MODATTR; /* 21 SDRAM Module Attributes */\r
- struct DEVATTR_st DEVATTR; /* 22 SDRAM Device Attributes: General[3] */\r
- pseudo_bit_t TCK0_5[0x00008]; /* 23 SDRAM Device Minimum Clock Cycle at CLX-0.5[3] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t TAC0_5[0x00008]; /* 24 SDRAM Device Maximum Data Access Time (t AC ) from Clock at CLX-0.5[3] */\r
- pseudo_bit_t TCK1_0[0x00008]; /* 25 SDRAM Device Minimum Clock Cycle at CLX-1[3] */\r
- pseudo_bit_t TAC1_0[0x00008]; /* 26 SDRAM Device Maximum Data Access Time (t AC ) from Clock at CLX-1[3] */\r
- pseudo_bit_t TRP[0x00008]; /* 27 SDRAM Device Minimum Row Precharge Time (t RP )[3] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t TRRD[0x00008]; /* 28 SDRAM Device Minimum Row Active to Row Active Delay (t RRD )[3] */\r
- pseudo_bit_t TRCD[0x00008]; /* 29 SDRAM Device Minimum RAS to CAS Delay (t RCD )[3] */\r
- pseudo_bit_t TRAS[0x00008]; /* 30 SDRAM Device Minimum Active to Precharge Time (t RAS )[3] */\r
- pseudo_bit_t DENSITY[0x00008]; /* 31 Module Bank Density */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t STPAC[0x00008]; /* 32 Address and Command Input Setup Time Before Clock[3] */\r
- pseudo_bit_t HLDAC[0x00008]; /* 33 Address and Command Input Hold Time After Clock[3] */\r
- pseudo_bit_t STPMSK[0x00008]; /* 34 SDRAM Device Data/Data Mask Input Setup Time Before Data Strobe[3] */\r
- pseudo_bit_t HLDMSK[0x00008]; /* 35 SDRAM Device Data/Data Mask Input Hold Time After Data Strobe[3] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00008];\r
- pseudo_bit_t TRC[0x00008]; /* 41 Minimum Active/Auto-Refresh Time (t RC )[3] */\r
- pseudo_bit_t TRFC[0x00008]; /* 42 SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh Command Period (t RFC ) [3] */\r
- pseudo_bit_t TCKMAX[0x00008]; /* 43 SDRAM Device Maximum Cycle Time (t CK max)[3] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t TDQSQ[0x00008]; /* 44 SDRAM Device Maximum DQS-DQ Skew Time (t DQSQ )[3] */\r
- pseudo_bit_t TQHS[0x00008]; /* 45 SDRAM Device Maximum Read Data Hold Skew Factor (t QHS )[3] */\r
- pseudo_bit_t reserved2[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00060];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00010];\r
- pseudo_bit_t REV[0x00008]; /* 62 SPD Revision */\r
- pseudo_bit_t CHKSUM[0x00008]; /* 63 Checksum for Bytes 0-62\r
- Process for Calculating the Checksum\r
- 1. Convert binary information, in byte locations 0 - 62, to decimal.\r
- 2. Add together (sum) all decimal values for addresses 0 - 6\r
- 2.\r
- 3. Divide sum by 25\r
- 6.\r
- 4. Convert remainder to binary (will be less than 256).\r
- 5. Store result (single byte) in address 63 as Checksum.\r
- Note: The same result can be obtained by adding the binary values in addresses 0 - 62 and eliminating all but the low order byte.\r
- The low order byte is the Checksum. */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct GUID_INFO_st { /* Little Endian */\r
- pseudo_bit_t NODE_GUID_INFO_H[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t NODE_GUID_INFO_L[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t PORT1_GUID_INFO_H[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t PORT1_GUID_INFO_L[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t PORT2_GUID_INFO_H[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t PORT2_GUID_INFO_L[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SYSTEM_GUID_INFO_H[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SYSTEM_GUID_INFO_L[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t parttion_cap[0x00010];\r
- pseudo_bit_t reserved0[0x00010];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Transport and CI Error Counters */\r
-\r
-struct Transport_and_CI_Error_Counters_st { /* Little Endian */\r
- pseudo_bit_t rq_num_lle[0x00020]; /* Responder - number of local length errors */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sq_num_lle[0x00020]; /* Requester - number of local length errors */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rq_num_lqpoe[0x00020]; /* Responder - number local QP operation error */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sq_num_lqpoe[0x00020]; /* Requester - number local QP operation error */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rq_num_leeoe[0x00020]; /* Responder - number local EE operation error */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sq_num_leeoe[0x00020]; /* Requester - number local EE operation error */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rq_num_lpe[0x00020]; /* Responder - number of local protection errors */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sq_num_lpe[0x00020]; /* Requester - number of local protection errors */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rq_num_wrfe[0x00020]; /* Responder - number of WR flushed errors */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sq_num_wrfe[0x00020]; /* Requester - number of WR flushed errors */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sq_num_mwbe[0x00020]; /* Requester - number of memory window bind errors */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sq_num_bre[0x00020]; /* Requester - number of bad response errors */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rq_num_lae[0x00020]; /* Responder - number of local access errors */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sq_num_rire[0x00020]; /* Responder - number of remote invalid request errors */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sq_num_rae[0x00020]; /* Requester - number of remote access errors */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sq_num_roe[0x00020]; /* Requester - number of remote operation errors */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sq_num_tree[0x00020]; /* Requester - number of transport retries exceeded errors */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sq_num_rree[0x00020]; /* Requester - number of RNR nak retries exceeded errors */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sq_num_lrdve[0x00020]; /* Requester - number of local RDD violation errors */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rq_num_rirdre[0x00020];/* Responder - number of remote invalid RD request errors */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sq_num_rabrte[0x00020];/* Requester - number of remote aborted errors */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sq_num_ieecne[0x00020];/* Requester - number of invalid EE context number errors */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sq_num_ieecse[0x00020];/* Requester - invalid EE context state errors */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rq_num_oos[0x00020]; /* Responder - number of out of sequence requests received */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sq_num_oos[0x00020]; /* Requester - number of out of sequence Naks received */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rq_num_mce[0x00020]; /* Responder - number of bad multicast packets received */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rq_num_rsync[0x00020]; /* Responder - number of RESYNC operations */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sq_num_rsync[0x00020]; /* Requester - number of RESYNC operations */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t num_cqovf[0x00020]; /* Number of CQ overflows */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t num_eqovf[0x00020]; /* Number of EQ overflows */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct MSIX_st { /* Little Endian */\r
- struct MSIX_TableEntry_st MSIX_TableEntry[32];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t MSIX_PendingBits[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct TPTGW_DATA_st { /* Little Endian */\r
- pseudo_bit_t miss_memkey[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t miss_opcode[0x00008];\r
- pseudo_bit_t miss_pd[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t miss_token[0x00010];\r
- pseudo_bit_t miss_flags[0x00008]; /* PXL,HXL,CPB,POK,AOK,LOK,PRW,HRW */\r
- pseudo_bit_t miss_page_size[0x00005];\r
- pseudo_bit_t reserved0[0x00003];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t miss_va_h[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t miss_va_l[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t miss_length[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t miss_lkey[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mpt_cache_lkey[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mpt_cache_va_h[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mpt_cache_va_l[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mpt_cache_len_h[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mpt_cache_len_l[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mpt_cache_pd[0x00018];\r
- pseudo_bit_t mpt_cache_page_size[0x00005];\r
- pseudo_bit_t reserved1[0x00003];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mpt_cache_acl[0x00005];\r
- pseudo_bit_t reserved2[0x00002];\r
- pseudo_bit_t mpt_cache_memkey_tag[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x0000c];\r
- pseudo_bit_t mpt_cache_mtt_20bit_ptr[0x00014];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mpt_cache_phy[0x00001];\r
- pseudo_bit_t mpt_cache_lock[0x00001];\r
- pseudo_bit_t mpt_cache_valid[0x00001];\r
- pseudo_bit_t mpt_cache_nsvl[0x00001];\r
- pseudo_bit_t mpt_cache_iomem_[0x00001];\r
- pseudo_bit_t reserved4[0x0000b];\r
- pseudo_bit_t mpt_cache_hit_vec[0x00004];\r
- pseudo_bit_t mpt_cache_valid_vec[0x00004];\r
- pseudo_bit_t mpt_cache_lock_vec[0x00004];\r
- pseudo_bit_t reserved5[0x00004];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t prot_mtt_offset_51_20[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t prot_len_ok[0x00001];\r
- pseudo_bit_t prot_acl_ok[0x00001];\r
- pseudo_bit_t prot_pd_ok[0x00001];\r
- pseudo_bit_t prot_page_crossed[0x00001];\r
- pseudo_bit_t reserved6[0x00008];\r
- pseudo_bit_t prot_mtt_offset_19_0[0x00014];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mtt_cache_lkey[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mtt_cache_va_h[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mtt_cache_va_l[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mtt_cache_pa_h[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mtt_cache_pa_l[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mtt_cache_hit_vec[0x00004];\r
- pseudo_bit_t mtt_cache_valid_vec[0x00004];\r
- pseudo_bit_t mtt_cache_lock_vec[0x00004];\r
- pseudo_bit_t reserved9[0x00004];\r
- pseudo_bit_t mtt_cache_ent_valid[0x00001];\r
- pseudo_bit_t mtt_cache_ent_locked[0x00001];\r
- pseudo_bit_t reserved10[0x0000e];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t xmit_pa_h[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t xmit_pa_l[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t xmit_token[0x00010];\r
- pseudo_bit_t reserved11[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t xmit_length[0x0000d];\r
- pseudo_bit_t reserved12[0x00003];\r
- pseudo_bit_t xmit_ns_destid[0x00003];\r
- pseudo_bit_t xmit_ns_lane[0x00002]; /* posted 1, nonposted 2 , response ???? */\r
- pseudo_bit_t xmit_nsvl[0x00001];\r
- pseudo_bit_t xmit_iomem_[0x00001];\r
- pseudo_bit_t reserved13[0x00001];\r
- pseudo_bit_t xmit_xstat[0x00003];\r
- pseudo_bit_t reserved14[0x00005];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved15[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct TPTGW_CTRL_st { /* Little Endian */\r
- pseudo_bit_t address[0x00008]; /* address (set) in caches. (in MTT , when accessing NOT thru Associativity MUX */\r
- pseudo_bit_t reserved0[0x00008];\r
- pseudo_bit_t way[0x00003]; /* 0x4 = random way, 0x7 = ALL ways (e.g. when doing InValidate) */\r
- pseudo_bit_t reserved1[0x00003];\r
- pseudo_bit_t thru_ass_mux[0x00001]; /* Read/Write MTT are done thru associativity MUX */\r
- pseudo_bit_t mtt_mpt_[0x00001]; /* '0': access MPT cache, '1': access MTT cache */\r
- pseudo_bit_t cmd[0x00006]; /* cache WRITE 0x01\r
- cache READ 0x02\r
- cache PROB 0x03\r
- miss fifo POP 0x04\r
- miss fifo READ 0x05\r
- miss fifo PUSH 0x06\r
- EXECUTE 0x07\r
- XMIT 0x08\r
- tmx CLOSE 0x09\r
- tmx OPEN 0x0a\r
- protection PROB 0x0b\r
- tmx OPEN debug 0x0c */\r
- pseudo_bit_t busy[0x00001];\r
- pseudo_bit_t lock[0x00001];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TCU Exception Buffer */\r
-\r
-struct TCUEB_st { /* Little Endian */\r
- pseudo_bit_t ebw0_0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_2[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_2[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_2[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_2[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_3[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_3[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_3[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_3[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_4[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_4[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_4[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_4[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_5[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_5[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_5[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_5[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_6[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_6[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_6[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_6[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_7[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_7[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_7[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_7[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_8[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_8[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_8[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_8[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_9[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_9[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_9[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_9[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_10[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_10[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_10[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_10[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_11[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_11[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_11[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_11[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_12[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_12[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_12[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_12[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_13[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_13[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_13[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_13[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_14[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_14[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_14[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_14[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_15[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_15[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_15[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_15[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_16[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_16[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_16[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_16[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_17[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_17[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_17[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_17[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_18[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_18[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_18[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_18[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_19[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_19[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_19[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_19[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_20[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_20[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_20[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_20[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_21[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_21[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_21[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_21[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_22[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_22[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_22[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_22[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_23[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_23[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_23[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_23[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_24[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_24[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_24[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_24[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_25[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_25[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_25[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_25[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_26[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_26[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_26[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_26[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_27[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_27[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_27[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_27[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_28[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_28[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_28[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_28[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_29[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_29[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_29[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_29[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_30[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_30[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_30[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_30[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_31[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_31[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_31[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_31[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_32[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_32[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_32[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_32[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_33[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_33[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_33[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_33[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_34[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_34[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_34[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_34[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_35[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_35[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_35[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_35[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_36[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_36[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_36[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_36[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_37[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_37[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_37[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_37[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_38[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_38[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_38[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_38[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_39[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_39[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_39[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_39[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_40[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_40[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_40[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_40[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_41[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_41[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_41[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_41[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_42[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_42[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_42[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_42[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_43[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_43[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_43[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_43[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_44[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_44[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_44[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_44[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_45[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_45[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_45[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_45[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_46[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_46[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_46[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_46[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_47[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_47[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_47[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_47[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_48[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_48[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_48[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_48[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_49[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_49[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_49[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_49[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_50[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_50[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_50[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_50[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_51[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_51[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_51[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_51[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_52[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_52[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_52[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_52[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_53[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_53[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_53[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_53[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_54[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_54[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_54[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_54[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_55[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_55[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_55[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_55[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_56[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_56[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_56[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_56[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_57[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_57[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_57[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_57[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_58[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_58[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_58[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_58[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_59[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_59[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_59[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_59[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_60[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_60[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_60[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_60[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_61[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_61[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_61[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_61[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_62[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_62[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_62[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_62[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_63[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_63[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_63[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_63[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_64[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_64[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_64[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_64[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_65[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_65[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_65[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_65[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_66[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_66[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_66[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_66[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_67[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_67[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_67[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_67[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_68[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_68[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_68[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_68[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_69[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_69[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_69[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_69[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_70[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_70[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_70[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_70[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_71[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_71[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_71[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_71[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_72[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_72[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_72[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_72[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_73[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_73[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_73[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_73[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_74[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_74[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_74[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_74[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_75[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_75[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_75[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_75[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_76[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_76[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_76[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_76[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_77[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_77[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_77[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_77[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_78[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_78[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_78[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_78[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_79[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_79[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_79[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_79[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_80[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_80[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_80[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_80[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_81[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_81[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_81[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_81[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_82[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_82[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_82[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_82[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_83[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_83[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_83[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_83[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_84[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_84[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_84[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_84[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_85[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_85[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_85[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_85[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_86[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_86[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_86[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_86[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_87[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_87[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_87[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_87[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_88[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_88[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_88[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_88[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_89[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_89[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_89[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_89[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_90[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_90[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_90[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_90[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_91[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_91[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_91[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_91[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_92[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_92[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_92[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_92[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_93[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_93[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_93[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_93[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_94[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_94[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_94[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_94[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_95[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_95[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_95[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_95[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_96[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_96[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_96[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_96[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_97[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_97[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_97[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_97[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_98[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_98[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_98[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_98[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_99[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_99[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_99[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_99[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_100[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_100[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_100[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_100[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_101[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_101[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_101[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_101[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_102[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_102[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_102[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_102[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_103[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_103[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_103[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_103[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_104[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_104[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_104[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_104[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_105[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_105[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_105[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_105[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_106[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_106[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_106[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_106[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_107[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_107[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_107[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_107[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_108[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_108[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_108[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_108[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_109[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_109[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_109[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_109[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_110[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_110[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_110[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_110[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_111[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_111[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_111[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_111[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_112[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_112[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_112[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_112[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_113[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_113[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_113[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_113[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_114[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_114[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_114[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_114[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_115[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_115[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_115[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_115[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_116[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_116[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_116[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_116[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_117[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_117[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_117[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_117[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_118[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_118[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_118[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_118[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_119[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_119[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_119[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_119[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_120[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_120[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_120[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_120[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_121[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_121[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_121[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_121[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_122[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_122[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_122[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_122[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_123[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_123[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_123[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_123[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_124[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_124[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_124[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_124[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_125[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_125[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_125[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_125[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_126[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_126[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_126[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_126[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_127[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_127[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_127[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_127[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_128[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_128[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_128[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_128[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_129[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_129[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_129[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_129[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_130[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_130[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_130[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_130[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_131[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_131[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_131[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_131[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_132[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_132[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_132[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_132[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_133[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_133[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_133[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_133[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_134[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_134[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_134[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_134[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_135[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_135[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_135[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_135[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_136[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_136[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_136[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_136[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_137[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_137[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_137[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_137[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_138[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_138[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_138[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_138[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_139[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_139[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_139[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_139[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_140[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_140[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_140[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_140[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_141[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_141[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_141[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_141[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_142[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_142[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_142[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_142[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw0_143[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw1_143[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw2_143[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ebw3_143[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x03800];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TCU Exception Buffer FIFO Controller */\r
-\r
-struct TCUEBCTL_st { /* Little Endian */\r
- pseudo_bit_t eb_write_ptr[0x00008]; /* eb write pointer */\r
- pseudo_bit_t reserved0[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t eb_read_ptr[0x00008]; /* eb write poiner */\r
- pseudo_bit_t reserved1[0x00018];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @TCU_BIST */\r
-\r
-struct TCU_BIST_st { /* Little Endian */\r
- pseudo_bit_t tcu_bist0_rdw_0[0x00007];/* 131 */\r
- pseudo_bit_t reserved0[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tcu_bist0_rdw_1[0x00007];/* 131 */\r
- pseudo_bit_t reserved1[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tcu_bist2_wdw_0[0x00006];/* 131 */\r
- pseudo_bit_t reserved2[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tcu_bist2_wdw_1[0x00006];/* 131 */\r
- pseudo_bit_t reserved3[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tcu_bist2_wdw_2[0x00006];/* 132 */\r
- pseudo_bit_t reserved4[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tcu_bist2_wdw_3[0x00006];/* 132 */\r
- pseudo_bit_t reserved5[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tcu_bist3_wdw_0[0x00007];/* 132 */\r
- pseudo_bit_t reserved6[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tcu_bist3_wdw_1[0x00007];/* 132 */\r
- pseudo_bit_t reserved7[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist2waydata_data_rdw_0[0x00006];/* 160 */\r
- pseudo_bit_t reserved8[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist2waydata_data_rdw_1[0x00006];/* 160 */\r
- pseudo_bit_t reserved9[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist2waydata_code_rdw_0[0x00006];/* 160 */\r
- pseudo_bit_t reserved10[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist2waydata_code_rdw_1[0x00006];/* 160 */\r
- pseudo_bit_t reserved11[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rep_arrays_stat[0x0000c];\r
- pseudo_bit_t reserved12[0x00014];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bists_stat[0x0000d];\r
- pseudo_bit_t reserved13[0x00013];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nonrep_arrays_stat[0x00017];\r
- pseudo_bit_t reserved14[0x00009];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved15[0x00220];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TCU Packet Checks Debug */\r
-\r
-struct TCUTCDEBUG_st { /* Little Endian */\r
- struct TCUCLIDEBUG_st tcuclidebug; /* tcucli debug */\r
-/* --------------------------------------------------------- */\r
- struct TCUTCQP2EEDEBUG_st tcutcqp2eedebug;/* tcutcqp2ee debug */\r
-/* --------------------------------------------------------- */\r
- struct TCUTCCHKER_st tcutcchker; /* tcutcchker debug */\r
-/* --------------------------------------------------------- */\r
- struct TCUTCCHKDI_st tcutcchkdi; /* tcutcchkdi debug */\r
-/* --------------------------------------------------------- */\r
- struct TCUTCHEADERDEBUG_st tcutcheaderdebug;/* tcutcheader debug */\r
-/* --------------------------------------------------------- */\r
- struct TCUTCQPCRDDEBUG_st tcutcqpcrddebug;/* tcutcqpc debug */\r
-/* --------------------------------------------------------- */\r
- struct TCUTCQPCWRDEBUG_st tcutcqpcwrdebug;/* tcutcqpcwr debug */\r
-/* --------------------------------------------------------- */\r
- struct TCUDICMDDEBUG_st tcudicmddebug;/* tcudipyld debug */\r
-/* --------------------------------------------------------- */\r
- struct TCUDIPYLDDEBUG_st tcudipylddebug;/* tcudipyld debug */\r
-/* --------------------------------------------------------- */\r
- struct TCUPBDEBUG_st tcupbdebug; /* tcu packet buffer debug */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Fence Mechanism */\r
-\r
-struct CEFENCE_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00018];\r
- pseudo_bit_t Command[0x00006]; /* Command\r
-\r
- 0x00 Reserved\r
- 0x01 Copy incount to limitcount\r
- 0x02 Do not copy incount to limitcount\r
- 0x03-0x3F Reserved */\r
- pseudo_bit_t b[0x00001]; /* Busy - When sw sets this bit the command in the command field is executed by hardware. */\r
- pseudo_bit_t s[0x00001]; /* Semaphore - When read if it was zero it is set to one and zero is returned. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t incount[0x00020]; /* Input Counter, incremented for every entry that enters the pipe */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t outcount[0x00020]; /* Output Counter - Incremented for every entry that exits the pipe. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t apm_req_qpn[0x00020]; /* TCU pass QPN for APM request */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Fence Mechanism */\r
-\r
-struct FENCE_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00018];\r
- pseudo_bit_t Command[0x00006]; /* Command\r
-\r
- 0x00 Reserved\r
- 0x01 Copy incount to limitcount\r
- 0x02 Do not copy incount to limitcount\r
- 0x03-0x3F Reserved */\r
- pseudo_bit_t b[0x00001]; /* Busy - When sw sets this bit the command in the command field is executed by hardware. */\r
- pseudo_bit_t s[0x00001]; /* Semaphore - When read if it was zero it is set to one and zero is returned. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t incount[0x00020]; /* Input Counter, incremented for every entry that enters the pipe */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t outcount[0x00020]; /* Output Counter - Incremented for every entry that exits the pipe. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t limitcount[0x00020]; /* Limit Count - If b bit is set, when outcount reaches the value in limitcount the b bit is cleared. */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Cause Registers */\r
-\r
-struct TCU_CAUSEREG_st { /* Little Endian */\r
- pseudo_bit_t pb_parity_err[0x00001];\r
- pseudo_bit_t eb_parity_err[0x00001];\r
- pseudo_bit_t ce_parity_err[0x00001];\r
- pseudo_bit_t tcu_crtimeout_occurred[0x00001];\r
- pseudo_bit_t irisc_nsw_error[0x00001];\r
- pseudo_bit_t reserved0[0x0001b];\r
-/* --------------------------------------------------------- */\r
- struct EXT_CAUSEREG_st extended_cause;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Partition Keys (P_Key) Table */\r
-\r
-struct PKEYTABLE_st { /* Little Endian */\r
- pseudo_bit_t pkey0[0x00010];\r
- pseudo_bit_t reserved0[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey1[0x00010];\r
- pseudo_bit_t reserved1[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey2[0x00010];\r
- pseudo_bit_t reserved2[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey3[0x00010];\r
- pseudo_bit_t reserved3[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey4[0x00010];\r
- pseudo_bit_t reserved4[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey5[0x00010];\r
- pseudo_bit_t reserved5[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey6[0x00010];\r
- pseudo_bit_t reserved6[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey7[0x00010];\r
- pseudo_bit_t reserved7[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey8[0x00010];\r
- pseudo_bit_t reserved8[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey9[0x00010];\r
- pseudo_bit_t reserved9[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey10[0x00010];\r
- pseudo_bit_t reserved10[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey11[0x00010];\r
- pseudo_bit_t reserved11[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey12[0x00010];\r
- pseudo_bit_t reserved12[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey13[0x00010];\r
- pseudo_bit_t reserved13[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey14[0x00010];\r
- pseudo_bit_t reserved14[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey15[0x00010];\r
- pseudo_bit_t reserved15[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey16[0x00010];\r
- pseudo_bit_t reserved16[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey17[0x00010];\r
- pseudo_bit_t reserved17[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey18[0x00010];\r
- pseudo_bit_t reserved18[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey19[0x00010];\r
- pseudo_bit_t reserved19[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey20[0x00010];\r
- pseudo_bit_t reserved20[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey21[0x00010];\r
- pseudo_bit_t reserved21[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey22[0x00010];\r
- pseudo_bit_t reserved22[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey23[0x00010];\r
- pseudo_bit_t reserved23[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey24[0x00010];\r
- pseudo_bit_t reserved24[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey25[0x00010];\r
- pseudo_bit_t reserved25[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey26[0x00010];\r
- pseudo_bit_t reserved26[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey27[0x00010];\r
- pseudo_bit_t reserved27[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey28[0x00010];\r
- pseudo_bit_t reserved28[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey29[0x00010];\r
- pseudo_bit_t reserved29[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey30[0x00010];\r
- pseudo_bit_t reserved30[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey31[0x00010];\r
- pseudo_bit_t reserved31[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey32[0x00010];\r
- pseudo_bit_t reserved32[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey33[0x00010];\r
- pseudo_bit_t reserved33[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey34[0x00010];\r
- pseudo_bit_t reserved34[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey35[0x00010];\r
- pseudo_bit_t reserved35[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey36[0x00010];\r
- pseudo_bit_t reserved36[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey37[0x00010];\r
- pseudo_bit_t reserved37[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey38[0x00010];\r
- pseudo_bit_t reserved38[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey39[0x00010];\r
- pseudo_bit_t reserved39[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey40[0x00010];\r
- pseudo_bit_t reserved40[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey41[0x00010];\r
- pseudo_bit_t reserved41[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey42[0x00010];\r
- pseudo_bit_t reserved42[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey43[0x00010];\r
- pseudo_bit_t reserved43[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey44[0x00010];\r
- pseudo_bit_t reserved44[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey45[0x00010];\r
- pseudo_bit_t reserved45[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey46[0x00010];\r
- pseudo_bit_t reserved46[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey47[0x00010];\r
- pseudo_bit_t reserved47[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey48[0x00010];\r
- pseudo_bit_t reserved48[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey49[0x00010];\r
- pseudo_bit_t reserved49[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey50[0x00010];\r
- pseudo_bit_t reserved50[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey51[0x00010];\r
- pseudo_bit_t reserved51[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey52[0x00010];\r
- pseudo_bit_t reserved52[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey53[0x00010];\r
- pseudo_bit_t reserved53[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey54[0x00010];\r
- pseudo_bit_t reserved54[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey55[0x00010];\r
- pseudo_bit_t reserved55[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey56[0x00010];\r
- pseudo_bit_t reserved56[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey57[0x00010];\r
- pseudo_bit_t reserved57[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey58[0x00010];\r
- pseudo_bit_t reserved58[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey59[0x00010];\r
- pseudo_bit_t reserved59[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey60[0x00010];\r
- pseudo_bit_t reserved60[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey61[0x00010];\r
- pseudo_bit_t reserved61[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey62[0x00010];\r
- pseudo_bit_t reserved62[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey63[0x00010];\r
- pseudo_bit_t reserved63[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey64[0x00010];\r
- pseudo_bit_t reserved64[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey65[0x00010];\r
- pseudo_bit_t reserved65[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey66[0x00010];\r
- pseudo_bit_t reserved66[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey67[0x00010];\r
- pseudo_bit_t reserved67[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey68[0x00010];\r
- pseudo_bit_t reserved68[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey69[0x00010];\r
- pseudo_bit_t reserved69[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey70[0x00010];\r
- pseudo_bit_t reserved70[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey71[0x00010];\r
- pseudo_bit_t reserved71[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey72[0x00010];\r
- pseudo_bit_t reserved72[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey73[0x00010];\r
- pseudo_bit_t reserved73[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey74[0x00010];\r
- pseudo_bit_t reserved74[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey75[0x00010];\r
- pseudo_bit_t reserved75[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey76[0x00010];\r
- pseudo_bit_t reserved76[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey77[0x00010];\r
- pseudo_bit_t reserved77[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey78[0x00010];\r
- pseudo_bit_t reserved78[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey79[0x00010];\r
- pseudo_bit_t reserved79[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey80[0x00010];\r
- pseudo_bit_t reserved80[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey81[0x00010];\r
- pseudo_bit_t reserved81[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey82[0x00010];\r
- pseudo_bit_t reserved82[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey83[0x00010];\r
- pseudo_bit_t reserved83[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey84[0x00010];\r
- pseudo_bit_t reserved84[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey85[0x00010];\r
- pseudo_bit_t reserved85[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey86[0x00010];\r
- pseudo_bit_t reserved86[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey87[0x00010];\r
- pseudo_bit_t reserved87[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey88[0x00010];\r
- pseudo_bit_t reserved88[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey89[0x00010];\r
- pseudo_bit_t reserved89[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey90[0x00010];\r
- pseudo_bit_t reserved90[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey91[0x00010];\r
- pseudo_bit_t reserved91[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey92[0x00010];\r
- pseudo_bit_t reserved92[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey93[0x00010];\r
- pseudo_bit_t reserved93[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey94[0x00010];\r
- pseudo_bit_t reserved94[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey95[0x00010];\r
- pseudo_bit_t reserved95[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey96[0x00010];\r
- pseudo_bit_t reserved96[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey97[0x00010];\r
- pseudo_bit_t reserved97[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey98[0x00010];\r
- pseudo_bit_t reserved98[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey99[0x00010];\r
- pseudo_bit_t reserved99[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey100[0x00010];\r
- pseudo_bit_t reserved100[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey101[0x00010];\r
- pseudo_bit_t reserved101[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey102[0x00010];\r
- pseudo_bit_t reserved102[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey103[0x00010];\r
- pseudo_bit_t reserved103[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey104[0x00010];\r
- pseudo_bit_t reserved104[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey105[0x00010];\r
- pseudo_bit_t reserved105[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey106[0x00010];\r
- pseudo_bit_t reserved106[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey107[0x00010];\r
- pseudo_bit_t reserved107[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey108[0x00010];\r
- pseudo_bit_t reserved108[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey109[0x00010];\r
- pseudo_bit_t reserved109[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey110[0x00010];\r
- pseudo_bit_t reserved110[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey111[0x00010];\r
- pseudo_bit_t reserved111[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey112[0x00010];\r
- pseudo_bit_t reserved112[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey113[0x00010];\r
- pseudo_bit_t reserved113[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey114[0x00010];\r
- pseudo_bit_t reserved114[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey115[0x00010];\r
- pseudo_bit_t reserved115[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey116[0x00010];\r
- pseudo_bit_t reserved116[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey117[0x00010];\r
- pseudo_bit_t reserved117[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey118[0x00010];\r
- pseudo_bit_t reserved118[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey119[0x00010];\r
- pseudo_bit_t reserved119[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey120[0x00010];\r
- pseudo_bit_t reserved120[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey121[0x00010];\r
- pseudo_bit_t reserved121[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey122[0x00010];\r
- pseudo_bit_t reserved122[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey123[0x00010];\r
- pseudo_bit_t reserved123[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey124[0x00010];\r
- pseudo_bit_t reserved124[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey125[0x00010];\r
- pseudo_bit_t reserved125[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey126[0x00010];\r
- pseudo_bit_t reserved126[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pkey127[0x00010];\r
- pseudo_bit_t reserved127[0x00010];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Completion Engine Configuration */\r
-\r
-struct CECFG_st { /* Little Endian */\r
- struct CEINFIFO_st ceinputfifo;\r
-/* --------------------------------------------------------- */\r
- struct CECQC_st cecqc;\r
-/* --------------------------------------------------------- */\r
- struct CELDB_st celdb;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ce_error[0x00009]; /* Completion Engine Exception Status\r
-\r
- */\r
- pseudo_bit_t reserved0[0x00003];\r
- pseudo_bit_t ce_current_unit_reg[0x00002];/* current nswr fifo which cecore works with (2'b01 or 2'b10)\r
- */\r
- pseudo_bit_t reserved1[0x00012];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t irisc_release_cmd[0x00005];/* Completion Engine Exception Command\r
- */\r
- pseudo_bit_t reserved2[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00040];\r
-/* --------------------------------------------------------- */\r
- struct CEGRLCFG_st cegrlcfg;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00100];\r
-/* --------------------------------------------------------- */\r
- struct TCUCEEXEGW_st ceexegw; /* Completion Engine Gateway to generate Exe entries in the CE */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00080];\r
-/* --------------------------------------------------------- */\r
- struct CEDEBUG_st cedebug;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TCU Multicast Cache */\r
-\r
-struct TCUMCCache_st { /* Little Endian */\r
- struct MCCACHEGID_st mcgid00; /* multicast cache gid 00 */\r
-/* --------------------------------------------------------- */\r
- struct MCCACHEGID_st mcgid01; /* multicast cache gid 01 */\r
-/* --------------------------------------------------------- */\r
- struct MCCACHEGID_st mcgid02; /* multicast cache gid 02 */\r
-/* --------------------------------------------------------- */\r
- struct MCCACHEGID_st mcgid03; /* multicast cache gid 03 */\r
-/* --------------------------------------------------------- */\r
- struct MCCACHEGID_st mcgid04; /* multicast cache gid 04 */\r
-/* --------------------------------------------------------- */\r
- struct MCCACHEGID_st mcgid05; /* multicast cache gid 05 */\r
-/* --------------------------------------------------------- */\r
- struct MCCACHEGID_st mcgid06; /* multicast cache gid 06 */\r
-/* --------------------------------------------------------- */\r
- struct MCCACHEGID_st mcgid07; /* multicast cache gid 07 */\r
-/* --------------------------------------------------------- */\r
- struct MCCACHEGID_st mcgid08; /* multicast cache gid 08 */\r
-/* --------------------------------------------------------- */\r
- struct MCCACHEGID_st mcgid09; /* multicast cache gid 09 */\r
-/* --------------------------------------------------------- */\r
- struct MCCACHEGID_st mcgid10; /* multicast cache gid 10 */\r
-/* --------------------------------------------------------- */\r
- struct MCCACHEGID_st mcgid11; /* multicast cache gid 11 */\r
-/* --------------------------------------------------------- */\r
- struct MCCACHEGID_st mcgid12; /* multicast cache gid 12 */\r
-/* --------------------------------------------------------- */\r
- struct MCCACHEGID_st mcgid13; /* multicast cache gid 13 */\r
-/* --------------------------------------------------------- */\r
- struct MCCACHEGID_st mcgid14; /* multicast cache gid 14 */\r
-/* --------------------------------------------------------- */\r
- struct MCCACHEGID_st mcgid15; /* multicast cache gid 15 */\r
-/* --------------------------------------------------------- */\r
- struct MCCACHEQPN_st mcqpn; /* multicast QP numbers */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_multi_dgid_111_96[0x00010];/* multicast Constant GID bits [111:32] - bits [111:96] */\r
- pseudo_bit_t reserved0[0x00008];\r
- pseudo_bit_t cfg_multi_dgid_127_120[0x00008];/* multicast constand GID bits[127:120] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_multi_dgid_95_64[0x00020];/* multicast Constant GID bits [111:32] - bits [95:64] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_multi_dgid_63_32[0x00020];/* multicast Constant GID bits [111:32] - bits [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x009a0];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* tcu gateway */\r
-\r
-struct TCUTCGW_st { /* Little Endian */\r
- struct TCUTCDIGW_st digw; /* tcu tc gateway controller\r
- Setting the GW for HW is by writting:\r
- 1. destination RDE and Command valid bit set\r
- 2. destination CLI.\r
- */\r
-/* --------------------------------------------------------- */\r
- struct TCUDIGWRAM_st tcudigwram; /* array of the tcu tc gateway */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TCU End of Packet Trap Command */\r
-\r
-struct TCUPKTMV_st { /* Little Endian */\r
- pseudo_bit_t erp_move[0x00004]; /* IRISC order the where to send packet with error:\r
- TCU_CONT 0x11\r
- TCU_DROP 0x12\r
- TCU_COPY 0x14\r
- */\r
- pseudo_bit_t pkt_toeb_last[0x00001];/* indication that packet has pushed into exception buffer. When this bit is reset thew packet is in the Exception buffer */\r
- pseudo_bit_t reserved0[0x0001b];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* QPC Access Gateway */\r
-\r
-struct QPCGW_st { /* Little Endian */\r
- pseudo_bit_t syndrome[0x00008]; /* output: valid during gwbusy=0 after "read" and "read&then" qpc commands */\r
- pseudo_bit_t qpstate[0x00004]; /* output: valid during gwbusy=0 after "read" and "read&then" qpc commands. */\r
- pseudo_bit_t illaddr[0x00001]; /* error indication of access to illegal address in QPCGW.\r
- output: asserted at the moment of the event. deasserted at rose(gwbusy).\r
- In the all error cases the operation is dropped. */\r
- pseudo_bit_t illread[0x00001]; /* error indication of reading from any QPCGW register, other than QPCGW header, during gwbusy=1\r
- output: asserted at the moment of the event. deasserted at rose(gwbusy).\r
- The read data during this operation is invalid. */\r
- pseudo_bit_t illwrite[0x00001];\r
- pseudo_bit_t reserved0[0x00002];\r
- pseudo_bit_t cqpc_eu[0x00005]; /* Execution unit number of EXE_CQPC.\r
- input: must be valid during EXE_CQPC commands at gwbusy=1 */\r
- pseudo_bit_t cache_selector[0x00002];/* input: must be valid during gwbusy=1\r
- 0 - SQPC\r
- 1 - RQPC\r
- 2 - CQC\r
- */\r
- pseudo_bit_t gwopcode[0x00006]; /* input: must be valid during gwbusy=1\r
- POSSIBLE OPCODES:\r
- 0 - read from EXE_CQPC to the GW\r
- 1 - write from the GW to EXE_CQPC\r
- 2 - execute QPC command\r
- */\r
- pseudo_bit_t gwbusy[0x00001]; /* input-output: asserted by FW, deasserted by HW\r
- This bit also known as GO bit. */\r
- pseudo_bit_t gwlocked[0x00001]; /* input-output: asserted by HW, deasserted by FW */\r
-/* --------------------------------------------------------- */\r
- struct QPC_command_header_st QPC_command_header;\r
-/* --------------------------------------------------------- */\r
- struct QPCLINE_st line0;\r
-/* --------------------------------------------------------- */\r
- struct QPCLINE_st line1;\r
-/* --------------------------------------------------------- */\r
- struct QPCLINE_st line2;\r
-/* --------------------------------------------------------- */\r
- struct QPCLINE_st line3;\r
-/* --------------------------------------------------------- */\r
- struct QPCLINE_st line4;\r
-/* --------------------------------------------------------- */\r
- struct QPCLINE_st line5;\r
-/* --------------------------------------------------------- */\r
- struct QPCLINE_st line6;\r
-/* --------------------------------------------------------- */\r
- struct QPCLINE_st line7;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t BE0[0x00010]; /* Byte Enables for QPC data line 0\r
-\r
- bit 15 - is for line[127:120]\r
- bit 14 - is for line[119:112]\r
- .\r
- .\r
- bit 0 - is for line[7:0]\r
-\r
- * This field is write only (see bug 4963) */\r
- pseudo_bit_t reserved1[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t BE1[0x00010]; /* Byte Enables for QPC data line 1\r
-\r
- * This field is write only (see bug 4963) */\r
- pseudo_bit_t reserved2[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t BE2[0x00010]; /* Byte Enables for QPC data line 2\r
-\r
- * This field is write only (see bug 4963) */\r
- pseudo_bit_t reserved3[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t BE3[0x00010]; /* Byte Enables for QPC data line 3\r
-\r
- * This field is write only (see bug 4963) */\r
- pseudo_bit_t reserved4[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t BE4[0x00010]; /* Byte Enables for QPC data line 4\r
-\r
- * This field is write only (see bug 4963) */\r
- pseudo_bit_t reserved5[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t BE5[0x00010]; /* Byte Enables for QPC data line 5\r
-\r
- * This field is write only (see bug 4963) */\r
- pseudo_bit_t reserved6[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t BE6[0x00010]; /* Byte Enables for QPC data line 6\r
-\r
- * This field is write only (see bug 4963) */\r
- pseudo_bit_t reserved7[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t BE7[0x00010]; /* Byte Enables for QPC data line 7\r
-\r
- * This field is write only (see bug 4963) */\r
- pseudo_bit_t reserved8[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved9[0x00240];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Local GIDs Table */\r
-\r
-struct MGIDTABLE_st { /* Little Endian */\r
- struct GID_st mgid0;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid1;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid2;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid3;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid4;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid5;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid6;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid7;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid8;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid9;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid10;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid11;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid12;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid13;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid14;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid15;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid16;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid17;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid18;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid19;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid20;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid21;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid22;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid23;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid24;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid25;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid26;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid27;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid28;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid29;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid30;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid31;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid32;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid33;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid34;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid35;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid36;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid37;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid38;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid39;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid40;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid41;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid42;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid43;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid44;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid45;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid46;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid47;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid48;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid49;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid50;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid51;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid52;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid53;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid54;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid55;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid56;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid57;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid58;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid59;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid60;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid61;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid62;\r
-/* --------------------------------------------------------- */\r
- struct GID_st mgid63;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Trapped Incoming Packet Context Data Read from QPC */\r
-\r
-struct TCUTCQPC_st { /* Little Endian */\r
- pseudo_bit_t migreq[0x00001]; /* migreq data from QPC */\r
- pseudo_bit_t ts[0x00003]; /* trasport service from QPC */\r
- pseudo_bit_t exqp[0x00001]; /* exception QP from QPC */\r
- pseudo_bit_t rd[0x00001]; /* read bit from QPC */\r
- pseudo_bit_t wr[0x00001]; /* write bit from QPC */\r
- pseudo_bit_t at[0x00001]; /* atomic bit from QPC */\r
- pseudo_bit_t grhen[0x00001]; /* GRH enable bit from QPC */\r
- pseudo_bit_t mylid[0x00007]; /* my LID from QPC */\r
- pseudo_bit_t rmtlid[0x00010]; /* remote LID from QPC */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rmtgid_127_96[0x00020];/* remote GID in QPC */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rmtgid_95_64[0x00020]; /* remote GID in QPC */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rmtgid_63_32[0x00020]; /* remote GID in QPC */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rmtgid_31_0[0x00020]; /* remote GID in QPC */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t errpsn[0x00018]; /* expected read response PSN from QPC */\r
- pseudo_bit_t errpsn_v[0x00001]; /* excpected read response PSN valid bit from QPC */\r
- pseudo_bit_t no_err_psn_lock[0x00001];/* no expected PSN lock bit from QPC */\r
- pseudo_bit_t rdatm[0x00001]; /* read_atomic_ bit from QPC. */\r
- pseudo_bit_t tculck[0x00001]; /* tcu lock bit from QPC (for Read Response/ Atomic lock) */\r
- pseudo_bit_t reserved0[0x00004];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t eesqpn[0x00018]; /* EE source QP number in QPC */\r
- pseudo_bit_t pkey_idx[0x00008]; /* P key index in QPC */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t eedqpn[0x00018]; /* EE destination QP number in QPC */\r
- pseudo_bit_t mygid[0x00008]; /* my GID in QPC */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t epsn[0x00018]; /* expected PSN */\r
- pseudo_bit_t opc_last[0x00002]; /* Opcoe last field in QPC */\r
- pseudo_bit_t rsvd_opc_last[0x00006];/* the reset of the bits in the byte where opcode last field is. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t highestpsn[0x00018]; /* highest psn fiels. */\r
- pseudo_bit_t portid[0x00004]; /* port number field in QPC */\r
- pseudo_bit_t mtu[0x00003]; /* MTU field in QPC */\r
- pseudo_bit_t reserved1[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t onapsn[0x00018]; /* Oldest non acked PSN */\r
- pseudo_bit_t reserved2[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t lstackreqpsn[0x00018]; /* last ackreq PSN */\r
- pseudo_bit_t reserved3[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qkey[0x00020]; /* Q key */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t e2ecredits[0x00010]; /* e2e credits field in QPC */\r
- pseudo_bit_t reserved4[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00140];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Trapped Incoming Packet Details */\r
-\r
-struct TCUTCHEADER_st { /* Little Endian */\r
- struct LRH_st LRH;\r
-/* --------------------------------------------------------- */\r
- struct GRH_st GRH;\r
-/* --------------------------------------------------------- */\r
- struct BTH_st BTH; /* BTH fileds */\r
-/* --------------------------------------------------------- */\r
- struct RDETH_st RDETH; /* RDETH fields */\r
-/* --------------------------------------------------------- */\r
- struct DETH_st DETH; /* DETH fields */\r
-/* --------------------------------------------------------- */\r
- struct RETH_st RETH; /* RETH firlds */\r
-/* --------------------------------------------------------- */\r
- struct AtomicETH_st AtomicETH; /* AtomicETH fields */\r
-/* --------------------------------------------------------- */\r
- struct AETH_st AETH; /* AETH fields */\r
-/* --------------------------------------------------------- */\r
- struct AtomicAckETH_st AtomicAckETH;/* AtomicAckETH fields */\r
-/* --------------------------------------------------------- */\r
- struct immDt_st immDT; /* immediate data field */\r
-/* --------------------------------------------------------- */\r
- struct IBTCUdata_st IBtcudata; /* data from IB: port number, LMC ,real packet length */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00040];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TCU General Configuration */\r
-\r
-struct TCUGRLCFG_st { /* Little Endian */\r
- struct TCUINITCREDITS_st tcuinitcredits;/* tcu credits */\r
-/* --------------------------------------------------------- */\r
- struct TCUTCCFG_st tcutccfg; /* tcu tc cfg */\r
-/* --------------------------------------------------------- */\r
- struct TCUCLI_st tcucli; /* tcucli cfg */\r
-/* --------------------------------------------------------- */\r
- struct TCUTCCLI_st tcutccli; /* tcutccli cfg */\r
-/* --------------------------------------------------------- */\r
- struct TCUTCQP2EE_st tcutcqp2ee; /* tcu tc qp2ee cfg */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00018];\r
- pseudo_bit_t gp_cfg[0x00008]; /* General Purpose Configuration Register\r
- bit 0 - used for disable (when set) non-starvation in ce input fifo\r
- */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* tcu checks cause data */\r
-\r
-struct TCUCHKCAUSE_st { /* Little Endian */\r
- struct TCUCHKCAUSE_REG0_st cause_reg_0;/* checker cause register 0:\r
- // 31. 1'b0,\r
- // 30. 1'b0,\r
- // 29. 1'b0,\r
- // 28. 1'b0,\r
- // 27. 1'b0,\r
- // 26. 1'b0,\r
- // 25. 1'b0,\r
- // 24. 1'b0,\r
- // 23. bad_qp2ee_eestate,\r
- // 22. bad_qp2ee_eenvalid,\r
- // 21. bad_eestate,\r
- // 20. bad_eevalid,\r
- // 19. bad_opcode_ts,\r
- // 18. bad_qpstate,\r
- // 17. bad_qpvalid,\r
- // 16. bad_opcode_int_drop,\r
- // 15. bad_portid,\r
- // 14. bad_malformed_packet,\r
- // 13. bad_bth_rsv,\r
- // 12. bad_bth_rsv_var,\r
- // 11. bad_tver,\r
- // 10. bad_no_bth,\r
- // 09. bad_ipver,\r
- // 08. bad_nxthdr,\r
- // 07. bad_cli_check,\r
- // 06. bad_icrc,\r
- // 05. bad_pktlen,\r
- // 04. bad_lrh_rsv,\r
- // 03. 1'b0,\r
- // 02. 1'b0,\r
- // 01. packet_is_raw_ethertype,\r
- // 00. packet_is_raw_ipv6\r
- */\r
-/* --------------------------------------------------------- */\r
- struct TCUCHKCAUSE_REG1_st cause_reg_1;/* checker cause register 1:\r
- 31. 1'b0,\r
- 30. 1'b0,\r
- 29. bad_multicast_match,\r
- 28. bad_multicast_pkt,\r
- 27. bad_qkey,\r
- 26. bad_pkey,\r
- 25. bad_rmtlid_rd,\r
- 24. bad_mylid_rd,\r
- 23. bad_rmtgid_rd,\r
- 22. bad_mygid_rd,\r
- 21. bad_eesource,\r
- 20. bad_eedestqp,\r
- 19. bad_qp_is_lock,\r
- 18. bad_qp2ee_rddmiss,\r
- 17. bad_qp2ee_qptsnrd,\r
- 16. bad_qp2ee_qpstate,\r
- 15. bad_qp2ee_qpnvalid,\r
- 14. bad_grhen,\r
- 13. bad_rmtlid_nrd,\r
- 12. bad_mylid_nrd,\r
- 11. bad_rmtgid_nrd,\r
- 10. bad_mygid_nrd,\r
- 09. bad_migreq,\r
- 08. bad_qp2ee_eeisbusy,\r
- 07. bad_no_qpcrd,\r
- 06. 1'b0,\r
- 05. 1'b0,\r
- 04. bad_router_packet,\r
- 03. bad_opcode_int_erp,\r
- 02. qp_is_qp0,\r
- 01. qp_is_qp1,\r
- 00.bad_exception_qp\r
-\r
- */\r
-/* --------------------------------------------------------- */\r
- struct TCUCHKCAUSE_REG2_st cause_reg_2;/* checker cause register 2\r
- 31.1'b0,\r
- 30.1'b0,\r
- 29.1'b0,\r
- 28.1'b0,\r
- 27.bad_ack_implnck,\r
- 26.bad_rdrsp_implnck,\r
- 25.bad_res_padcount,\r
- 24.bad_payload_res_pkt,\r
- 23.bad_rsp_supp,\r
- 22.bad_opc_res_seq,\r
- 21.bad_rdres_aack_mix,\r
- 20.bad_rdrsp_trash,\r
- 19.bad_eestate_bit_res,\r
- 18.bad_qpstate_bit_res,\r
- 17.unsolicited_ack,\r
- 16.bad_ghost_resp,\r
- 15.bad_e2ecredits_rel,\r
- 14.bad_e2ecredits_unrel,\r
- 13.bad_req_padcount,\r
- 12.bad_payload_req_pkt,\r
- 11.bad_opc_req_seq,\r
- 10.bad_req_supp_unrel,\r
- 09.bad_ud_epsn,\r
- 08.bad_uc_epsn,\r
- 07.bad_unrel_inv_psn,\r
- 06.bad_req_supp_rel,\r
- 05.bad_xxstate_psn_req,\r
- 04.bad_eestate_bit_req,\r
- 03.bad_qpstate_bit_req,\r
- 02.bad_qp2ee_eepsnerr,\r
- 01.bad_rel_inv_psn,\r
- 00.bad_rel_dupl_psn\r
-\r
- */\r
-/* --------------------------------------------------------- */\r
- struct TCUCHKCAUSE_REG3_st cause_reg_3;/* checker cause register 3:\r
- 31:8 - 0\r
- 07.bad_rdres_syn,\r
- 06.bad_malformed_synd,\r
- 05.bad_syn_inv_rd_req,\r
- 04.bad_syn_roe,\r
- 03.bad_syn_rae,\r
- 02.bad_syn_inv_req,\r
- 01.bad_syn_psn_seq_err,\r
- 00.bad_syn_rnrnack\r
- */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Incoming Packet Exception Masks - Ignore / Drop / Trap */\r
-\r
-struct EXCEPTIONMASKS_st { /* Little Endian */\r
- pseudo_bit_t cfg_exception_hmask_127_96[0x00020];/* high priority mask for exception vector in TCU [127:96] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_exception_hmask_95_64[0x00020];/* high priority mask for exception vector in TCU [95:64] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_exception_hmask_63_32[0x00020];/* high priority mask for exception vector in TCU [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_exception_hmask_31_0[0x00020];/* high priority mask for exception vector in TCU [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_exception_lmask_127_96[0x00020];/* low priority mask for exception vector in TCU [127:64] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_exception_lmask_95_64[0x00020];/* low priority mask for exception vector in TCU [95:64] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_exception_lmask_63_32[0x00020];/* low priority mask for exception vector in TCU [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_exception_lmask_31_0[0x00020];/* low priority mask for exception vector in TCU [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_exception_ignore_127_96[0x00020];/* ignore mask for exception vector in TCU [127:96] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_exception_ignore_95_64[0x00020];/* ignore mask for exception vector in TCU [95:64] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_exception_ignore_63_32[0x00020];/* ignore mask for exception vector in TCU [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_exception_ignore_31_0[0x00020];/* ignore mask for exception vector in TCU [31:0] */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Opcode Masks - Drop / Trap */\r
-\r
-struct OPCODEMASKS_st { /* Little Endian */\r
- pseudo_bit_t line0[0x00020]; /* drop/erp opcode mask [15:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line1[0x00020]; /* drop/erp opcode mask [31:16] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line2[0x00020]; /* drop/erp opcode mask [47:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line3[0x00020]; /* drop/erp opcode mask [63:48] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line4[0x00020]; /* drop/erp opcode mask [79:64] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line5[0x00020]; /* drop/erp opcode mask [95:60] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line6[0x00020]; /* drop/erp opcode mask [111:96] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line7[0x00020]; /* drop/erp opcode mask [127:112] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line8[0x00020]; /* drop/erp opcode mask [143:128] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line9[0x00020]; /* drop/erp opcode mask [159:144] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line10[0x00020]; /* drop/erp opcode mask [175:160] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line11[0x00020]; /* drop/erp opcode mask [191:176] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line12[0x00020]; /* drop/erp opcode mask [207:192] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line13[0x00020]; /* drop/erp opcode mask [223:208] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line14[0x00020]; /* drop/erp opcode mask [239:224] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t line15[0x00020]; /* drop/erp opcode mask [255:240] */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TCU Router Mode Configuration */\r
-\r
-struct ROUTERMODE_st { /* Little Endian */\r
- pseudo_bit_t cfg_hca_router[0x00001];/* router mode set */\r
- pseudo_bit_t reserved0[0x0001f];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_router_tclass[0x00008];/* Tclass data for router packets without GRH */\r
- pseudo_bit_t reserved1[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_router_bth_95_64[0x00020];/* BTH data for router mode [95:64] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_router_bth_63_32[0x00020];/* BTH data for router mode [63:32]\r
-\r
- * Dest QP should not be configured to zero when working in router mode, see bug 4984 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_router_bth_31_0[0x00020];/* BTH data for router mode [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_router_deth_63_32[0x00020];/* DETH data for router mode [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_router_deth_31_0[0x00020];/* DETH data for router mode [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Raw Packets Handling Registers */\r
-\r
-struct RAW_st { /* Little Endian */\r
- pseudo_bit_t cfg_raw_bth_95_64[0x00020];/* bth to use for this incomming packets [95:64] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_raw_bth_63_32[0x00020];/* bth to use for this incomming packets [63:32]\r
-\r
- * Dest QP should not be configured to zero, see bug 4984 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_raw_bth_31_0[0x00020];/* bth to use for this incomming packets [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_raw_deth_63_32[0x00020];/* deth to use for this incomming packets [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_raw_deth_31_0[0x00020];/* deth to use for this incomming packets [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00060];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* InfiniRISC */\r
-\r
-struct IRisc_st { /* Little Endian */\r
- pseudo_bit_t iriscboot[0x00020]; /* The boot ROM will keep the iRISC on an infinite loop polling for this register. When ready, the bootstrap software updates this register with the code entry point vector address and then the iRISC jumps to that address to continue executing. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t irisc_id[0x00020]; /* This read only register returns the base address in cr-space of the configuration registers for the irisc in question (can be used to identify the irisc via a loadcr instruction) */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t datacacheways[0x00004];/* Number of Ways in iRISC Data Cache */\r
- pseudo_bit_t reserved0[0x00004];\r
- pseudo_bit_t datacachelinesize[0x00004];\r
- pseudo_bit_t reserved1[0x00004];\r
- pseudo_bit_t data_cache_lines_per_way[0x00010];/* Size of Data Cache - in units of cache lines */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t codecacheways[0x00004];/* Number of Ways in iRISC Code Cache */\r
- pseudo_bit_t reserved2[0x00004];\r
- pseudo_bit_t codecachelinesize[0x00004];\r
- pseudo_bit_t reserved3[0x00004];\r
- pseudo_bit_t code_cache_lines_per_way[0x00010];/* Size of the implemented code cache - in units of cache lines */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t memaddrbase_63_32_[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00010];\r
- pseudo_bit_t memaddrbase_31_16_[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t readnsq[0x00006]; /* nsq bits to be used for read access to the nsi\r
-\r
- (update default with value used for read (NP) access to DMU) */\r
- pseudo_bit_t reserved5[0x00002];\r
- pseudo_bit_t writensq[0x00006]; /* nsq bits to be used for write access to the nsi\r
-\r
- (update default with value used for Posted access to DMU) */\r
- pseudo_bit_t reserved6[0x00001];\r
- pseudo_bit_t iomem_[0x00001]; /* io/mem bit to use in NSW\r
- 1 - I/O\r
- 0 - Mem */\r
- pseudo_bit_t reserved7[0x00006];\r
- pseudo_bit_t ldst4far_base[0x0000a];/* 10 msb of address when load/store 4 far is executed. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x00020];\r
-/* --------------------------------------------------------- */\r
- struct IRISCCACHEGW_st irisccachegw;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved9[0x00180];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t exinstptr[0x00020]; /* Address of last executed instruction */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nxtinstptr[0x00020]; /* Points to next to be executed Instruction */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gpreg[0x00020]; /* General Purpose LoadCR/StoreCR register */\r
-/* --------------------------------------------------------- */\r
- struct CCR_st CCR; /* Condition Code Register */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t intbase[0x00020]; /* Interrupt Address */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t intpins[0x00020]; /* This read only register shows the state of the 32 interrupt inputs to the iRISC (before the edge detector that sets corresponding bits in the cause register). */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rintbase[0x00020]; /* Remote Interrupt Base Address */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved10[0x000a0];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t intcause_r_w_[0x00020];/* Interrupt Cause\r
- Bits are set upon detection of a possitive edge (transition from 0 to 1) in corresponding signal of the iRISC interface.\r
- The resulting register is bitwise ANDed with the intenable register. A non-zero result triggers an interrupt to the iRISC core (unless intmask bit is set).\r
-\r
- Interrupt mapping for each of the 32 bits is specified for each iRISC in the FW flows document.\r
-\r
- The 32 bit input to the edge detector can be read in the intpins register.\r
-\r
- cause bit [0] - Code Breakpoint\r
- cause bit [1] - Data Breakpoint\r
- cause bit [2] - Performance Counters 0\r
- cause bit [3] - Performance Counters 1\r
- cause bit [4] - Code Cache miss\r
- cause bit [5] - Data Cache miss\r
- cause bit [16] - IPC\r
- cause bit [31] - timer\r
-\r
- */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t intcause_clear_[0x00020];/* Clear Interrupt Cause\r
- Writing to this register results in the bits set being cleared in the cause register. Bits not set in the write data are left unchanged.\r
- Reading from this register returns undefined results. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t intcause_set_[0x00020];/* Set Interrupt Cause\r
- Writing to this register results in the bits set being set in the cause register. Bits not set in the write data are left unchanged.\r
- Reading from this register returns undefined results. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t intenable[0x00020]; /* Interrupt Enable Mask - When set corresponding interrupt is enabled. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t intra[0x00020]; /* Interrupt Return Address */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t intm[0x00001]; /* Interrupt Mask */\r
- pseudo_bit_t intpm[0x00001]; /* Previous Interrupt Mask */\r
- pseudo_bit_t reserved11[0x00002];\r
- pseudo_bit_t rintm[0x00001]; /* remote Interrupt Mask */\r
- pseudo_bit_t reserved12[0x00019];\r
- pseudo_bit_t endl[0x00001]; /* Endianess for Loads\r
- 0 - Little Endian\r
- 1 - Big Endian */\r
- pseudo_bit_t ends[0x00001]; /* Endianess for Store\r
- 0 - Little Endian\r
- 1 - Big Endian */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rintra[0x00020]; /* Remote Interrupt Return Address */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t callra[0x00020]; /* Call Return Address */\r
-/* --------------------------------------------------------- */\r
- struct IRiscBP_st DataBP0;\r
-/* --------------------------------------------------------- */\r
- struct IRiscBP_st CodeBP0;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved13[0x00580];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t irisctimer[0x00020]; /* This is a free running counter that generates an interrupt every time it wraps around. It can be written to any a value through cr-space thus allowing programming the time between interrupts. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved14[0x001e0];\r
-/* --------------------------------------------------------- */\r
- struct IPCFIFO_st ipcfifo;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved15[0x00080];\r
-/* --------------------------------------------------------- */\r
- struct IRISCDEBUG_st iriscdebug;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved16[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Execution Unit */\r
-\r
-struct EXENGINE_st { /* Little Endian */\r
- struct EXEEVTCAUSE_st exeevtcause; /* Any bit set in the cause register will result in the bit corresponding to the execution engine being set in the exeevt register. */\r
-/* --------------------------------------------------------- */\r
- struct EXESTATUS_st exestatus;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t execmd[0x00008]; /* Execution Engine Command\r
-\r
- 0x00 Reserved\r
- 0x01 Go with clear (hw clears/programs descriptor fifo before starting)\r
- 0x02 Go Continue (used when EXU was preempted) - see bug 5183\r
- 0x03 Go with Blue Flame (hw clear/programs descriptor fifo before starting and copies cqpc ND* to descfifo fecthnd*. It is FW responsibility to update the cqpc NDS to the actual size of the writen BF data before giving the command in order to avoid access to non-written parts of the bf buffer)\r
- 0x04 Preemption\r
- 0x05 - Go without Clear (used when descriptor fifo is programmed by fw)\r
- 0x06-0xFF Reserved\r
- */\r
- pseudo_bit_t reserved0[0x00007];\r
- pseudo_bit_t preemptonly[0x00001]; /* when set the exeuction engine will stop only when preempted.\r
- See details in Tavor MAS. */\r
- pseudo_bit_t blueflameentry[0x00003];/* Blue flame entry number in responder flow blue flame FIFO. Relevant when command is GO with Blue Flame */\r
- pseudo_bit_t reserved1[0x00008];\r
- pseudo_bit_t syngen[0x00001]; /* set syndrome bit in LDB entries generated.\r
- this is used to control the generation of an internal event to the TCU ERP when the LDB entries are popped by the CE (in order to generate completion). To be used for example for retries when we want one single outstanding message. */\r
- pseudo_bit_t updateqpc[0x00001]; /* when set, qpc is updated after sending each packet accordingly\r
- when cleared, the qpc is not updated. (ldb entries are not also pushed at the end of msg)\r
- for example, this is useful for sending NAKs. the cqpc context values are used (as preprogrammed by scheduler) and the real qpc is not touched. */\r
- pseudo_bit_t ackenable[0x00001]; /* this bit is only relevant when the engine is configured for responder operation.\r
- if set, when the engine finishes sending all outstanding read responses, an ACK will be sent if donePSN is greater than ackedPSN. ackedPSN will be updated to donePSN. */\r
- pseudo_bit_t requester[0x00001]; /* This bit specifies whether the engine is processing a requester or a responder queue. When set the engine is configure to process a requester queue. When cleared the engine will process a responder queue. */\r
- pseudo_bit_t reserved2[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpn[0x00018]; /* Queue Pair Number */\r
- pseudo_bit_t ee[0x00001]; /* ee bit - if set then the engine is processing using an end to end context which number is stored in the qpn field */\r
- pseudo_bit_t reserved3[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ftcdlimit[0x0000f]; /* Fetch Descriptor Limit - See description in MAS */\r
- pseudo_bit_t ftcdlimitv[0x00001]; /* Fetch Descriptor Limit Valid Bit - See description in MAS */\r
- pseudo_bit_t ftcdcnt[0x0000f]; /* Number of descriptors fetched since last command\r
- Value is NOT reset when a command is received. */\r
- pseudo_bit_t ftcdcnto[0x00001]; /* ftcdcnt overflow\r
- Value is reset when a command is received. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t exedlimit[0x0000f]; /* Exer Descriptor Limit - See description in MAS */\r
- pseudo_bit_t exedlimitv[0x00001]; /* Exer Descriptor Limit Valid Bit - See description in MAS */\r
- pseudo_bit_t exedcnt[0x0000f]; /* Number of descriptors executed since last command\r
- Value is NOT reset when a command is received. */\r
- pseudo_bit_t exedcnto[0x00001]; /* exedcnt overflow */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t exeplimit[0x0000f]; /* Exer Packet Limit - See description in MAS\r
- */\r
- pseudo_bit_t exeplimitv[0x00001]; /* Exer Packet Limit Valid Bit - See description in MAS */\r
- pseudo_bit_t exepcnt[0x0000f]; /* Number of packets sent since last command\r
- Value is NOT reset when a command is received. */\r
- pseudo_bit_t exepcnto[0x00001]; /* exepcnt overflow */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t exeblimit[0x0000f]; /* Exer Bytes Limit - (in units of 64 bytes) - See description in MAS */\r
- pseudo_bit_t exeblimitv[0x00001]; /* Exer Bytes Limit Valid Bit - See description in MAS */\r
- pseudo_bit_t exebcnt[0x0000f]; /* Bytes sent since last command (in units of 64 bytes).\r
- Value is NOT reset when a command is received. */\r
- pseudo_bit_t exebcnto[0x00001]; /* exebcnt overflow\r
- Value is reset when a command is received. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gatherengine[0x00004]; /* Gather Engine Number that will be used by the execution engine\r
-\r
- 0x0-0x3 Gather Engine Number\r
- 0x4-0xF Reserved */\r
- pseudo_bit_t reserved5[0x00004];\r
- pseudo_bit_t fetchwatermark[0x00006];/* Descriptor Fecth Watermark - Fetcher will stop bringing new desctiptors when descriptors in FIFO exceed watermark level. Specified in units of 16 bytes. */\r
- pseudo_bit_t reserved6[0x00001];\r
- pseudo_bit_t prio[0x00001]; /* Priority - If set then engine is high priority. */\r
- pseudo_bit_t rrweight[0x00008]; /* Round Robin Weight for arbitration (in units of 256 bytes)\r
- Two level weighted round robin (see prio bit for priority) */\r
- pseudo_bit_t reserved7[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x00260];\r
-/* --------------------------------------------------------- */\r
- struct EXEFDESCCTL_st exefdescctl;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved9[0x00300];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Exe MGID Table */\r
-\r
-struct EXE_MGIDTABLE_st { /* Little Endian */\r
- struct EXE_GID_st mgid0;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid1;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid2;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid3;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid4;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid5;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid6;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid7;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid8;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid9;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid10;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid11;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid12;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid13;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid14;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid15;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid16;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid17;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid18;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid19;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid20;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid21;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid22;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid23;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid24;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid25;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid26;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid27;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid28;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid29;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid30;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid31;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid32;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid33;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid34;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid35;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid36;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid37;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid38;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid39;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid40;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid41;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid42;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid43;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid44;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid45;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid46;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid47;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid48;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid49;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid50;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid51;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid52;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid53;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid54;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid55;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid56;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid57;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid58;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid59;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid60;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid61;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid62;\r
-/* --------------------------------------------------------- */\r
- struct EXE_GID_st mgid63;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Execution Unit General Configuration */\r
-\r
-struct EXUGRLCFG_st { /* Little Endian */\r
- pseudo_bit_t grh_next_header[0x00008];/* This is the value placed in the GRH.NxtHdr field of outgoing packets. */\r
- pseudo_bit_t lver[0x00004]; /* value to put in the LRH.LVer field of generated packets */\r
- pseudo_bit_t tver[0x00004]; /* value to put in the BTH.TVer field of generated packets */\r
- pseudo_bit_t reserved0[0x00008];\r
- pseudo_bit_t gp_cfg[0x00008]; /* General Purpose Configuration Register */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t force_ackreq[0x00001]; /* Will force assertion of BTH.AckReq at the last packet of each request message sent */\r
- pseudo_bit_t udportcheck[0x00001]; /* When set, Port number in UD AV is checked to match Port field of QP in question. If thet are not equal, descriptor is not executed and corresponding error is reported (in engine cause register and syndrome). When cleared, AV Port field check is ignored. */\r
- pseudo_bit_t reserved1[0x00006];\r
- pseudo_bit_t system_log2pagesize[0x00006];/* log 2 of page size\r
- This page size should be not bigger than the nsb_page_size.\r
- By default it will be initialized by fw upon HCA initialization to the same page size as the nsb_page_size in TPT. The smaller values allow freedom in spliting the SDE gathers to smaller sizes.\r
- Note: for Tavor it MUST be greater than MTU */\r
- pseudo_bit_t reserved2[0x00002];\r
- pseudo_bit_t min_ge_credits2start[0x00008];/* Minimum GE credits needed to start a new packet */\r
- pseudo_bit_t reserved3[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00040];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ge0_credits[0x00008]; /* Number of gather entries available in gather engine 0 */\r
- pseudo_bit_t ge1_credits[0x00008]; /* see ge0_credits */\r
- pseudo_bit_t ge2_credits[0x00008]; /* see ge0_credits */\r
- pseudo_bit_t ge3_credits[0x00008]; /* see ge0_credits */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rrscentriescredits[0x00009];/* Number of available entries in the scatter lists buffer in the RDE */\r
- pseudo_bit_t reserved6[0x00017];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gff_credits[0x00009]; /* descriptor read filler available credits */\r
- pseudo_bit_t reserved7[0x00017];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x00100];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct EXEARB_st { /* Little Endian */\r
- pseudo_bit_t ex_penalty_map2[0x00020];/* Penalty map for arbitter */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ex_penalty_map3[0x00020];/* Penalty map for arbitter */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ex_penalty_map4[0x00020];/* Penalty map for arbitter */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ex_penalty_map5[0x00020];/* Penalty map for arbitter */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ex_penalty_map6[0x00020];/* Penalty map for arbitter */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ex_penalty_map7[0x00020];/* Penalty map for arbitter */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ex_penalty_map8[0x00020];/* Penalty map for arbitter */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ex_livelock_cnt[0x00010];/* Livelock counter, preventing starvation of low priority EUs. */\r
- pseudo_bit_t reserved0[0x00008];\r
- pseudo_bit_t ex_cfg_no_burstfee[0x00001];\r
- pseudo_bit_t ex_cfg_iter_noclps[0x00001];\r
- pseudo_bit_t ex_cfg_unlink_qufee[0x00001];\r
- pseudo_bit_t reserved1[0x00005];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Cause Registers */\r
-\r
-struct EXE_CAUSEREG_st { /* Little Endian */\r
- pseudo_bit_t irisc0_nsw_error[0x00001];\r
- pseudo_bit_t irisc1_nsw_error[0x00001];\r
- pseudo_bit_t crbus_timeout[0x00001];\r
- pseudo_bit_t reserved0[0x0001d];\r
-/* --------------------------------------------------------- */\r
- struct EXT_CAUSEREG_st extended_cause;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Descriptor Gateway */\r
-\r
-struct DESCFIFOGW_st { /* Little Endian */\r
- struct GWCONTROL_st descgwctrl; /* Command:\r
- 0x00 Reserved\r
- 0x01 Read Entry\r
- 0x02 Write Entry\r
- 0x03-0x3F Reserved\r
-\r
- Status\r
- 0x00 Success\r
- 0x01 Error\r
- 0x02-0x3F Reserved\r
- Address\r
- [23:21] Reserved\r
- [20:16] Execution Unit Number\r
- [15:06] Reserved\r
- [05:00] Descriptor Entry Number */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t descgwdata_127_96_[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t descgwdata_95_64_[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t descgwdata_63_32_[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t descgwdata_31_0_[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00060];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Reliable Datagram EE Disconnect FIFO */\r
-\r
-struct RDEEDISCFIFO_st { /* Little Endian */\r
- struct FIFOCONTROL_st rdeediscfifoctrl;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdeediscdata[0x00018]; /* bits 23:0 hold the ee context to be disconnected */\r
- pseudo_bit_t reserved0[0x00008];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Internal Doorbells */\r
-\r
-struct INTDB_st { /* Little Endian */\r
- struct INTDBFIFO_st intdbfifo; /* Internal Doorbell FIFO */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00040];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t int_bf_array_status[0x00008];/* the state of the entries in the internal blueflame array.\r
- 1 indicate that the entry is caputre, 0 - free. */\r
- pseudo_bit_t reserved1[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t int_bf_array_set[0x00008];/* set to the int_bf_array_status. each bit set the corrospoding bit in the status field. the filed return 0 when reading. */\r
- pseudo_bit_t reserved2[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t int_bf_array_clear[0x00008];/* clear to the int_bf_array_status. each bit clear the corrospoding bit in the status field. the filed return 0 when reading. */\r
- pseudo_bit_t reserved3[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x000a0];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* External Doorbells */\r
-\r
-struct EXTDB_st { /* Little Endian */\r
- pseudo_bit_t bf_lenght[0x00007]; /* this field contain the lenght of the current blueflame ( if exist ) by dword . if there is no blueflame thr field contsin 0. */\r
- pseudo_bit_t reserved0[0x00009];\r
- pseudo_bit_t uar_page_size[0x00006];/* hold the size of the uar page.\r
- the uar size in bits is 2^(12+uar_page_size) bytes. */\r
- pseudo_bit_t reserved1[0x00008];\r
- pseudo_bit_t disfilter[0x00001]; /* Disable DB Preprocessor Filter - When set Preprocessor will not filter writes to non-valid DB areas. */\r
- pseudo_bit_t disdbpp[0x00001]; /* Disable Doorbell Preprocessor. When set the doorbell preprocessor is disabled. Entries in the Pre DB FIFO are written directly to the QP DB FIFO. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bfstate[0x00002]; /* Blue Flame buffer State - Managed by DB Preprocessor (and Execution Units after reading from it). Can be written by FW (ie when freeing the buffer after deciding not to use it).\r
- 0x0 - Empty\r
- 0x1 - In Progress\r
- 0x2 - Full\r
- 0x3:0xF - Reserved */\r
- pseudo_bit_t reserved2[0x0001e];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t read_fsm_state[0x00003];/* the state of the fsm that handle the writing of the db to the qp fifo and the cq fifo */\r
- pseudo_bit_t reserved3[0x0001d];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t write_fsm[0x00003];\r
- pseudo_bit_t reserved4[0x0001d];\r
-/* --------------------------------------------------------- */\r
- struct QPDBFIFO_st qpdbfifo;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Execution Engine iRISC Assignement Mask */\r
-\r
-struct EXEENGIRISCMASK_st { /* Little Endian */\r
- pseudo_bit_t engiriscmask[0x00010]; /* bit set means irisc receives interrupt when corresponding execution engine is not busy */\r
- pseudo_bit_t reserved0[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00060];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Execution Engines Event Register */\r
-\r
-struct EXEEVENT_st { /* Little Endian */\r
- pseudo_bit_t exe00[0x00001]; /* Set when execution engine 00 is not busy */\r
- pseudo_bit_t exe01[0x00001]; /* Set when execution engine 01 is not busy */\r
- pseudo_bit_t exe02[0x00001]; /* Set when execution engine 02 is not busy */\r
- pseudo_bit_t exe03[0x00001]; /* Set when execution engine 03 is not busy */\r
- pseudo_bit_t exe04[0x00001]; /* Set when execution engine 04 is not busy */\r
- pseudo_bit_t exe05[0x00001]; /* Set when execution engine 05 is not busy */\r
- pseudo_bit_t exe06[0x00001]; /* Set when execution engine 06 is not busy */\r
- pseudo_bit_t exe07[0x00001]; /* Set when execution engine 07 is not busy */\r
- pseudo_bit_t exe08[0x00001]; /* Set when execution engine 08 is not busy */\r
- pseudo_bit_t exe09[0x00001]; /* Set when execution engine 09 is not busy */\r
- pseudo_bit_t exe10[0x00001]; /* Set when execution engine 10 is not busy */\r
- pseudo_bit_t exe11[0x00001]; /* Set when execution engine 11 is not busy */\r
- pseudo_bit_t exe12[0x00001]; /* Set when execution engine 12 is not busy */\r
- pseudo_bit_t exe13[0x00001]; /* Set when execution engine 13 is not busy */\r
- pseudo_bit_t exe14[0x00001]; /* Set when execution engine 14 is not busy */\r
- pseudo_bit_t exe15[0x00001]; /* Set when execution engine 15 is not busy */\r
- pseudo_bit_t reserved0[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00060];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @EXU_BIST */\r
-\r
-struct EXU_BIST_st { /* Little Endian */\r
- pseudo_bit_t exe_bistdbpp0_rdw_0[0x00006];/* 143 */\r
- pseudo_bit_t reserved0[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t exe_bistdbpp1_wdw_0[0x00006];/* 143 */\r
- pseudo_bit_t reserved1[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t exe_bistdescfifo_rdw_0[0x00007];/* 152 */\r
- pseudo_bit_t reserved2[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t exe_bistdescfifo_rdw_1[0x00007];/* 152 */\r
- pseudo_bit_t reserved3[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t exe_bistdescfifo_rdw_2[0x00007];/* 153 */\r
- pseudo_bit_t reserved4[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t exe_bistdescfifo_rdw_3[0x00007];/* 153 */\r
- pseudo_bit_t reserved5[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t exe_bistsdegff1_wdw_0[0x00007];/* 150 */\r
- pseudo_bit_t reserved6[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t exe_bistsdegff1_wdw_1[0x00007];/* 150 */\r
- pseudo_bit_t reserved7[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t exe_bistuppsncis_wdw_0[0x00008];/* 153 */\r
- pseudo_bit_t reserved8[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist2waydata_data0_rdw_0[0x00006];/* 162 */\r
- pseudo_bit_t reserved9[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist2waydata_data0_rdw_1[0x00006];/* 162 */\r
- pseudo_bit_t reserved10[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist4waydata_code0_rdw_0[0x00006];/* 162 */\r
- pseudo_bit_t reserved11[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist4waydata_code0_rdw_1[0x00006];/* 162 */\r
- pseudo_bit_t reserved12[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist4waydata_code0_rdw_2[0x00006];/* 162 */\r
- pseudo_bit_t reserved13[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist4waydata_code0_rdw_3[0x00006];/* 162 */\r
- pseudo_bit_t reserved14[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist2waydata_data1_rdw_0[0x00006];/* 162 */\r
- pseudo_bit_t reserved15[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist2waydata_data1_rdw_1[0x00006];/* 162 */\r
- pseudo_bit_t reserved16[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist4waydata_code1_rdw_0[0x00006];/* 162 */\r
- pseudo_bit_t reserved17[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist4waydata_code1_rdw_1[0x00006];/* 162 */\r
- pseudo_bit_t reserved18[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist4waydata_code1_rdw_2[0x00006];/* 162 */\r
- pseudo_bit_t reserved19[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist4waydata_code1_rdw_3[0x00006];/* 162 */\r
- pseudo_bit_t reserved20[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rep_arrays_stat[0x00015];\r
- pseudo_bit_t reserved21[0x0000b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bists_stat[0x0001f];\r
- pseudo_bit_t reserved22[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nonrep_arrays_stat_0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nonrep_arrays_stat_1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nonrep_arrays_stat_2[0x00006];\r
- pseudo_bit_t reserved23[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved24[0x000c0];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* EXE General Purpose Semaphores */\r
-\r
-struct EXE_SEMAPHORES_st { /* Little Endian */\r
- pseudo_bit_t semaphore0[0x00001]; /* Read returns 0 if lock succeeded\r
- 1 if lock failed\r
- Write of 0 releases semaphore\r
- 1 force lock (don't use it at home) */\r
- pseudo_bit_t reserved0[0x0001f];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t semaphore1[0x00001]; /* Read returns 0 if lock succeeded\r
- 1 if lock failed\r
- Write of 0 releases semaphore\r
- 1 force lock (don't use it at home) */\r
- pseudo_bit_t reserved1[0x0001f];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t semaphore2[0x00001]; /* Read returns 0 if lock succeeded\r
- 1 if lock failed\r
- Write of 0 releases semaphore\r
- 1 force lock (don't use it at home) */\r
- pseudo_bit_t reserved2[0x0001f];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t semaphore3[0x00001]; /* Read returns 0 if lock succeeded\r
- 1 if lock failed\r
- Write of 0 releases semaphore\r
- 1 force lock (don't use it at home) */\r
- pseudo_bit_t reserved3[0x0001f];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t semaphore4[0x00001]; /* Read returns 0 if lock succeeded\r
- 1 if lock failed\r
- Write of 0 releases semaphore\r
- 1 force lock (don't use it at home) */\r
- pseudo_bit_t reserved4[0x0001f];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t semaphore5[0x00001]; /* Read returns 0 if lock succeeded\r
- 1 if lock failed\r
- Write of 0 releases semaphore\r
- 1 force lock (don't use it at home) */\r
- pseudo_bit_t reserved5[0x0001f];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t semaphore6[0x00001]; /* Read returns 0 if lock succeeded\r
- 1 if lock failed\r
- Write of 0 releases semaphore\r
- 1 force lock (don't use it at home) */\r
- pseudo_bit_t reserved6[0x0001f];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t semaphore7[0x00001]; /* Read returns 0 if lock succeeded\r
- 1 if lock failed\r
- Write of 0 releases semaphore\r
- 1 force lock (don't use it at home) */\r
- pseudo_bit_t reserved7[0x0001f];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Descriptor Opcode Breakpoint */\r
-\r
-struct EXEOPCODEBP_st { /* Little Endian */\r
- pseudo_bit_t bp_rq_nop[0x00001];\r
- pseudo_bit_t bp_rq_r01[0x00001];\r
- pseudo_bit_t bp_rq_r02[0x00001];\r
- pseudo_bit_t bp_rq_r03[0x00001];\r
- pseudo_bit_t bp_rq_r04[0x00001];\r
- pseudo_bit_t bp_rq_r05[0x00001];\r
- pseudo_bit_t bp_rq_r06[0x00001];\r
- pseudo_bit_t bp_rq_r07[0x00001];\r
- pseudo_bit_t bp_rq_rdmaw[0x00001];\r
- pseudo_bit_t bp_rq_rdmaw_imm[0x00001];\r
- pseudo_bit_t bp_rq_send[0x00001];\r
- pseudo_bit_t bp_rq_send_imm[0x00001];\r
- pseudo_bit_t bp_rq_r12[0x00001];\r
- pseudo_bit_t bp_rq_r13[0x00001];\r
- pseudo_bit_t bp_rq_r14[0x00001];\r
- pseudo_bit_t bp_rq_r15[0x00001];\r
- pseudo_bit_t bp_rq_rdmar[0x00001];\r
- pseudo_bit_t bp_rq_cmpswp[0x00001];\r
- pseudo_bit_t bp_rq_fetchadd[0x00001];\r
- pseudo_bit_t bp_rq_r19[0x00001];\r
- pseudo_bit_t bp_rq_r20[0x00001];\r
- pseudo_bit_t bp_rq_r21[0x00001];\r
- pseudo_bit_t bp_rq_r22[0x00001];\r
- pseudo_bit_t bp_rq_r23[0x00001];\r
- pseudo_bit_t bp_rq_bind[0x00001];\r
- pseudo_bit_t bp_rq_r25[0x00001];\r
- pseudo_bit_t bp_rq_r26[0x00001];\r
- pseudo_bit_t bp_rq_r27[0x00001];\r
- pseudo_bit_t bp_rq_r28[0x00001];\r
- pseudo_bit_t bp_rq_r29[0x00001];\r
- pseudo_bit_t bp_rq_r30[0x00001];\r
- pseudo_bit_t bp_rq_r31[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x0000c];\r
- pseudo_bit_t bp_rp_rd[0x00001];\r
- pseudo_bit_t reserved1[0x00006];\r
- pseudo_bit_t bp_rp_cmpswp[0x00001];\r
- pseudo_bit_t bp_rp_fetchadd[0x00001];\r
- pseudo_bit_t reserved2[0x0000b];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* System Memory Access Parameters */\r
-\r
-struct MEMACCESSPARAMS_st { /* Little Endian */\r
- pseudo_bit_t key[0x00020]; /* Memory Key */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pd[0x00018]; /* Protection Domain */\r
- pseudo_bit_t reserved0[0x00005];\r
- pseudo_bit_t xlation_en[0x00001]; /* When cleared, baseaddress is physical address and no translation will be done. When set, address is virtual. TPT will be accessed in both cases for address decoding purposes. */\r
- pseudo_bit_t np[0x00001]; /* Non Posted Access */\r
- pseudo_bit_t nsvl[0x00001]; /* North Switch Virtual Lane */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t baseaddress_63_32_[0x00020];/* Base Address */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t baseaddress_31_0_[0x00020];/* Base Address */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* System Memory Access Parameters */\r
-\r
-struct RCVDB_RDBPARAMS_st { /* Little Endian */\r
- pseudo_bit_t rcvdb_qpn_credits[0x00020];/* use to be Memory Key in HW */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rcvdb_uar[0x00018]; /* use to be protection Doma in HW */\r
- pseudo_bit_t reserved0[0x00005];\r
- pseudo_bit_t rdb_xlation_en[0x00001];/* When cleared, baseaddress is physical address and no translation will be done. When set, address is virtual. TPT will be accessed in both cases for address decoding purposes. */\r
- pseudo_bit_t rdb_np[0x00001]; /* Non Posted Access */\r
- pseudo_bit_t rdb_nsvl[0x00001]; /* North Switch Virtual Lane */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdb_baseaddress_63_32_[0x00020];/* Base Address */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rcvdb_nda_nds[0x00020];/* use to be Base Address in HW */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @RDE_BIST */\r
-\r
-struct RDE_BIST_st { /* Little Endian */\r
- pseudo_bit_t rdebistsb_rdw_0[0x00007];/* 131 */\r
- pseudo_bit_t reserved0[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdebistsb_rdw_1[0x00007];/* 131 */\r
- pseudo_bit_t reserved1[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdebistsb_rdw_2[0x00007];/* 131 */\r
- pseudo_bit_t reserved2[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdebistsb_rdw_3[0x00007];/* 131 */\r
- pseudo_bit_t reserved3[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdebistsl6474_rdw_0[0x00007];/* 144 */\r
- pseudo_bit_t reserved4[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdebistsl6474_rdw_1[0x00007];/* 144 */\r
- pseudo_bit_t reserved5[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdebistsl6477_rdw_0[0x00007];/* 144 */\r
- pseudo_bit_t reserved6[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdebistsl6477_rdw_1[0x00007];/* 144 */\r
- pseudo_bit_t reserved7[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdebistpsfifo0_wdw_0[0x00007];/* 146 */\r
- pseudo_bit_t reserved8[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdebistpsfifo0_wdw_1[0x00007];/* 146 */\r
- pseudo_bit_t reserved9[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdebistpsfifo0_wdw_2[0x00007];/* 146 */\r
- pseudo_bit_t reserved10[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdebistpsfifo1_wdw_0[0x00007];/* 146 */\r
- pseudo_bit_t reserved11[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdebistpsfifo1_wdw_1[0x00007];/* 146 */\r
- pseudo_bit_t reserved12[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdebistpsfifo1_wdw_2[0x00007];/* 146 */\r
- pseudo_bit_t reserved13[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdebist256len_wdw_0[0x00007];/* 144 */\r
- pseudo_bit_t reserved14[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdebistdffd_wdw_0[0x00008];/* 138 */\r
- pseudo_bit_t reserved15[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdebistdffd_wdw_1[0x00008];/* 138 */\r
- pseudo_bit_t reserved16[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rep_arrays_stat[0x00011];\r
- pseudo_bit_t reserved17[0x0000f];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bists_stat[0x0000f];\r
- pseudo_bit_t reserved18[0x00011];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nonrep_arrays_stat[0x00016];\r
- pseudo_bit_t reserved19[0x0000a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved20[0x00080];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* RDE Debug */\r
-\r
-struct RDEDEBUG_st { /* Little Endian */\r
- pseudo_bit_t cqpc_falv_freed[0x00020];/* cqpc falv freed */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cqpc_falv_allocated[0x00020];/* cqpc falv allocated */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cqpc_falv_locked[0x00020];/* cqpc falv locked */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cqpc_falv_valid[0x00020];/* cqpc falv valid */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cqpc_falv_hold_relock[0x00020];/* cqpc falv hold relock */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00060];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cqpc_falv_allocate[0x00020];/* cqpc falv allocate */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cqpc_falv_lock[0x00020];/* cqpc falv lock */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cqpc_falv_unlock[0x00020];/* cqpc falv unlock */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cqpc_falv_relock[0x00020];/* cqpc falv relock */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cqpc_falv_free[0x00020];/* cqpc falv free */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00040];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_read_inflight[0x00020];/* for each cqpc entry, is it reading now QPC */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t desc_inflight[0x00020];/* for each cqpc entry is there a descriptor inflight from memory .\r
- */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t whole_dsl_inside[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ti_error[0x00020]; /* error occured in tptinit pipe stage or after it for each cqpc entry . */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t np_error[0x00020]; /* error propagated to Final pipe stage or after it for each cqpc entry . */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sb_write_ptr[0x00009]; /* scatter buffer writer pointer */\r
- pseudo_bit_t reserved2[0x00007];\r
- pseudo_bit_t sb_read_ptr[0x00009]; /* scatter buffer read pointer . */\r
- pseudo_bit_t reserved3[0x00006];\r
- pseudo_bit_t sb_empty[0x00001]; /* scatter buffer is empty . */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cmdfifo_empty[0x00001];/* tcu command fifo is empty . */\r
- pseudo_bit_t reserved4[0x00003];\r
- pseudo_bit_t fq2tififo_empty[0x00001];/* FQPC to TPTINIT fifo empty . */\r
- pseudo_bit_t fq2tififo_full[0x00001];/* FQPC to TPTINIT fifo empty . */\r
- pseudo_bit_t reserved5[0x00002];\r
- pseudo_bit_t ti2nsfifo_empy[0x00001];/* TPTINIT to NSINIT fifo empty . */\r
- pseudo_bit_t ti2nsfifo_full[0x00001];/* TPTINIT to NSINIT fifo full . */\r
- pseudo_bit_t reserved6[0x00002];\r
- pseudo_bit_t ns2tffifo_empty[0x00001];/* NSINIT to TPTFIN fifo empty . */\r
- pseudo_bit_t ns2tffifo_full[0x00001];/* NSINIT to TPTFIN fifo full . */\r
- pseudo_bit_t reserved7[0x00002];\r
- pseudo_bit_t tf2sefifo_empty[0x00001];/* TPTFIN to scatter engine fifo entry . */\r
- pseudo_bit_t tf2sefifo_full[0x00001];/* TPTFIN to scatter engine fifo full . */\r
- pseudo_bit_t reserved8[0x00002];\r
- pseudo_bit_t se2npfifo_empty[0x00001];/* scatter engine to NONPOST fifo empty . */\r
- pseudo_bit_t se2npfifo_full[0x00001];/* scatter engine to NONPOST fifo full */\r
- pseudo_bit_t reserved9[0x0000a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t stop_tpt[0x00001]; /* stop tpt accesses - requested by the stoptptaccess register */\r
- pseudo_bit_t reserved10[0x00019];\r
- pseudo_bit_t ti_phyfifo_empty[0x00001];/* TPTINIT PhysicalAdressTranlatedFIFO is empty */\r
- pseudo_bit_t tf_phyfifo_empty[0x00001];/* TPTFIN PhysicalAdressTranlatedFIFO is empty */\r
- pseudo_bit_t no_outstanding_np_write[0x00001];/* no outstanding non posted write. */\r
- pseudo_bit_t atreda_freed[0x00001]; /* atomic reply data entry is freed . */\r
- pseudo_bit_t no_outstanding_read[0x00001];/* no outstanding read */\r
- pseudo_bit_t nsw_stopped[0x00001]; /* no outstanding nswitch accesses . */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t fqpc_ps[0x00003]; /* FQPC FSM state\r
- fqpc_ps\r
- --------------------\r
- 3'b000 FQPCIDLE\r
- 3'b001 CACHEACC\r
- 3'b010 READXQPC\r
- 3'b011 USEOTHER\r
- 3'b100 ATAGADOL\r
- 3'b101 THROWQPC\r
- 3'b110 THROWDSC\r
- 3'b111 PTPTINIT\r
- */\r
- pseudo_bit_t reserved11[0x00001];\r
- pseudo_bit_t tptreq_ps[0x00003]; /* TPTINIT TPTreq FSM state\r
- tptreq_ps\r
- --------------------\r
- 3'b000 TPTIDLE\r
- 3'b001 GTREADY\r
- 3'b010 PNSINIT\r
- 3'b011 TPTRQST\r
- 3'b100 XSTROB1\r
-\r
- */\r
- pseudo_bit_t reserved12[0x00001];\r
- pseudo_bit_t cda_ps[0x00003]; /* CurrentDescriptorAddress FSM state in TPTINIT pipestage\r
- cda_ps\r
- --------------------\r
- 3'b000 CDAIDLE\r
- 3'b001 RDNDCDA\r
- 3'b010 ENOUGHS\r
- 3'b011 WRITCDA\r
- 3'b100 CHKSPCE\r
- 3'b101 THRWDSC\r
- */\r
- pseudo_bit_t reserved13[0x00001];\r
- pseudo_bit_t cqpc_ps[0x00003]; /* TPTINIT cqpc FSM state\r
- cqpc_ps\r
- --------------------\r
- 3'b000 CQPCIDLE\r
- 3'b001 QPCREADY\r
- 3'b010 CHECKRDB\r
- 3'b011 CQPCDONE\r
- 3'b100 CQPCREAD\r
- */\r
- pseudo_bit_t reserved14[0x00001];\r
- pseudo_bit_t dbctr_ps[0x00002]; /* TPTINIT DoorBell counter FSM state\r
- dbctr_ps\r
- --------------------\r
- 2'b00 DBCTRIDLE\r
- 2'b01 WAITPTFSM\r
- 2'b10 RQPCARBRQ\r
- 2'b11 PUSHXRQPC\r
- */\r
- pseudo_bit_t reserved15[0x00002];\r
- pseudo_bit_t nsinit_ps[0x00003]; /* NSINIT FSM state\r
- nsinit_ps\r
- --------------------\r
- 3'b000 NSWIDLE\r
- 3'b001 NSWRQST\r
- 3'b010 NSWCMND\r
- 3'b011 NSWATMC\r
- 3'b100 PTPTFIN\r
- */\r
- pseudo_bit_t reserved16[0x00009];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tptfin_ps[0x00003]; /* TPTFIN FSM state\r
- tptfin_ps\r
- --------------------\r
- 3'b000 TPTFINIDLE\r
- 3'b001 READXXCQPC\r
- 3'b010 CHECKERROR\r
- 3'b011 FLSHALLDSC\r
- 3'b100 QPC2UPDATE\r
- 3'b101 SPITOFDESC\r
- 3'b110 SCATERDATA\r
- */\r
- pseudo_bit_t reserved17[0x00001];\r
- pseudo_bit_t ce_ps[0x00002]; /* CompletionEvent (NDA/NDS setion in descriptor) FSM state in TPTFIN pipe stage\r
- ce_ps\r
- --------------------\r
- 2'b00 CEIDLE\r
- 2'b01 READCE\r
- 2'b10 POPXCE\r
- 2'b11 DONECE\r
- */\r
- pseudo_bit_t reserved18[0x00002];\r
- pseudo_bit_t dsl_ps[0x00003]; /* DescriptorScatterList FSM state in TPTFIN pipe stage\r
- dsl_ps\r
- --------------------\r
- 3'b000 DSLIDLE\r
- 3'b001 DONTXDO\r
- 3'b010 NEED2DO\r
- 3'b011 UNLOCK1\r
- 3'b100 DSLFREE\r
- */\r
- pseudo_bit_t reserved19[0x00001];\r
- pseudo_bit_t flush_ps[0x00002]; /* Flush Descriptor FSM state in TPTFIN pipe stage\r
- flush_ps\r
- --------------------\r
- 2'b00 FLSHIDLE\r
- 2'b01 ISDESCIN\r
- 2'b10 POP1DESC\r
- */\r
- pseudo_bit_t reserved20[0x00002];\r
- pseudo_bit_t updateqpc_ps[0x00003]; /* Update QPC FSM state in TPTFIN pipe stage\r
- updateqpc_ps\r
- --------------------\r
- 3'b000 UPDATEIDLE\r
- 3'b001 JUSTCOMITD\r
- 3'b010 SCTRLSTPTR\r
- 3'b011 ALSOCOMITD\r
- 3'b100 RDXQPXXNDA\r
- 3'b101 XQPLOCK4RD\r
- 3'b110 XXXQPXXNDA\r
- 3'b111 UPDATEDONE\r
- */\r
- pseudo_bit_t reserved21[0x00001];\r
- pseudo_bit_t tptreq2_ps[0x00002]; /* TPT request FSM state in TPTFIN pipe stage\r
- tptreq2_ps\r
- --------------------\r
- 2'b00 TPTIDLE\r
- 2'b01 TPTRQST\r
- 2'b10 XSTROB1\r
- */\r
- pseudo_bit_t reserved22[0x0000a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t dispatch_ps[0x00003]; /* dispatch FSM state in ScatterEngine pipe stage\r
- dispatch_ps\r
- --------------------\r
- 3'b000 SCTRIDLE\r
- 3'b001 WRITERDB\r
- 3'b010 WRITDATA\r
- 3'b011 ISNTDATA\r
- 3'b100 HDRXWAIT\r
- 3'b101 SE2NPUSH\r
- */\r
- pseudo_bit_t reserved23[0x00001];\r
- pseudo_bit_t nmxif_ps[0x00003]; /* Nmux Interface FSM state in ScatterEngine pipe stage\r
- nmxif_ps\r
- --------------------\r
- 3'b000 NMUXIDLE\r
- 3'b001 NMUXRQST\r
- 3'b010 NSWITCHC\r
- 3'b011 NSWITCHD\r
- 3'b100 IDLECYCL\r
- */\r
- pseudo_bit_t reserved24[0x00001];\r
- pseudo_bit_t nonpost_ps[0x00003]; /* NONPOST FSM state\r
- nonpost_ps\r
- --------------------\r
- 3'b000 IDLENONPOST\r
- 3'b001 GETCQPCATTR\r
- 3'b010 WAIT4DBCPLT\r
- 3'b011 IRISCXERROR\r
- 3'b100 QPCXXUPDATE\r
- */\r
- pseudo_bit_t reserved25[0x00001];\r
- pseudo_bit_t doorbell_ps[0x00002]; /* DoorBell FSM state - internal doorbell - in NONPOST pipe stage\r
- doorbell_ps\r
- --------------------\r
- 2'b00 DOORBELLIDLE\r
- 2'b01 BLUEFLAMPUSH\r
- 2'b10 DOORBELLRING\r
- 2'b11 WAIT4MAINFSM\r
- */\r
- pseudo_bit_t reserved26[0x00002];\r
- pseudo_bit_t completion_ps0[0x00002];/* Completion FSM state in NONPOST pipe stage\r
- completion_ps\r
- --------------------\r
- 2'b00 CPLTIDLE\r
- 2'b01 COMPLETE\r
- 2'b10 WAITMAIN\r
- */\r
- pseudo_bit_t reserved27[0x0000e];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved28[0x000c0];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Cause Registers */\r
-\r
-struct RDE_CAUSEREG_st { /* Little Endian */\r
- pseudo_bit_t cr_slave_timeout[0x00001];\r
- pseudo_bit_t parity_err[0x00001];\r
- pseudo_bit_t reserved0[0x0001e];\r
-/* --------------------------------------------------------- */\r
- struct EXT_CAUSEREG_st extended_cause;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* RDE Credits */\r
-\r
-struct RDECREDITS_st { /* Little Endian */\r
- pseudo_bit_t max_rqpc_credits[0x00005];/* credits twards rqpc */\r
- pseudo_bit_t reserved0[0x0000b];\r
- pseudo_bit_t used_rqpc_credits[0x00005];/* how many rqpc credits used . */\r
- pseudo_bit_t reserved1[0x0000b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t max_sqpc_credits[0x00005];/* credits twards sqpc */\r
- pseudo_bit_t reserved2[0x0000b];\r
- pseudo_bit_t used_sqpc_credits[0x00005];/* how many rqpc credits used . */\r
- pseudo_bit_t reserved3[0x0000b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t max_filler_credits[0x00008];/* how many descriptors read filler cfredits are allowed */\r
- pseudo_bit_t reserved4[0x00008];\r
- pseudo_bit_t used_filler_credits[0x00008];/* how many filler credits are used */\r
- pseudo_bit_t reserved5[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t max_scatterlist_credits[0x00009];/* how may descriptors scatterlist entrys are allowed . */\r
- pseudo_bit_t reserved6[0x00007];\r
- pseudo_bit_t used_scatterlist_credits[0x00009];/* how many scattrerlist entrys are used . */\r
- pseudo_bit_t reserved7[0x00007];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Receive Data Engine General Configuration */\r
-\r
-struct RDEGRLCFG_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00080];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t system_log2pagesize[0x00006];/* log 2 page size\r
- This page size should be not bigger than the nsb_page_size.\r
- By default it will be initialized by fw upon HCA initialization to the same page size as the nsb_page_size in TPT. The smaller values allow freedom in spliting the RDE scatters to smaller sizes. */\r
- pseudo_bit_t reserved1[0x00019];\r
- pseudo_bit_t host_is_little_endian[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pipe_limit[0x00008]; /* disable rde piping */\r
- pseudo_bit_t packets_in_pipe[0x00008];/* How many packets are inside the pipe (after command FIFO) */\r
- pseudo_bit_t cqpc_falv_limit[0x00004];/* how many packets are allowed for a QP in the CQPC cache. */\r
- pseudo_bit_t dsl_falv_limit[0x00004];/* how many Descriptors are allowed for a QP in the CQPC cache. */\r
- pseudo_bit_t reserved2[0x00001];\r
- pseudo_bit_t force_qpc_clken[0x00001];/* force the clock gate of the QPC boundary FF to be enabled */\r
- pseudo_bit_t force_tpt_clken[0x00001];/* force the clock gate of the TPT boundary FF to be enabled */\r
- pseudo_bit_t force_nsw_clken[0x00001];/* force the clock gate of the NSW boundary FF to be enabled */\r
- pseudo_bit_t interrupt_every_packet_after_error[0x00001];/* Generate event to iRISC for every packet that reaches the top of the pipe if this CQPC QP had error already */\r
- pseudo_bit_t interrupt_every_packet[0x00001];/* Generate event to iRISC for every packet that reaches the top of the pipe. */\r
- pseudo_bit_t implicit_ackreq[0x00001];/* for each packet, behave as if it AckReq bit is SET (relevant only for Responder Write/Send....)) */\r
- pseudo_bit_t ignore_headerx[0x00001];/* to ignore the header-x indication from NSI */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00018];\r
- pseudo_bit_t gp_cfg[0x00008]; /* General Purpose Configuration Register */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00120];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Completion Engine Entry Access Gateway */\r
-\r
-struct CEACCESSGW_st { /* Little Endian */\r
- struct GWCONTROL_st cegw_ctl;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cq[0x00018];\r
- pseudo_bit_t opcode[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mqpn[0x00018];\r
- pseudo_bit_t error_sdrm[0x00008]; /* If not 0 traps to TCU irisc */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t slid_15_8[0x00008];\r
- pseudo_bit_t ee[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t psn_or_source_qp[0x00018];\r
- pseudo_bit_t slid_7_0[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t descriptor_ptr[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t length_commited[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t immediate_data[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t solicited_event[0x00001];\r
- pseudo_bit_t event_request[0x00001];\r
- pseudo_bit_t reserved0[0x00012];\r
- pseudo_bit_t sl[0x00004];\r
- pseudo_bit_t dlid_path[0x00007];\r
- pseudo_bit_t grh_bit[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00060];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* RDE Gateway */\r
-\r
-struct RDEGW_st { /* Little Endian */\r
- struct GWCONTROL_st rdegwcntrl; /* RDE GateWay Command encoding\r
- ==================================================\r
- PUSH 0x10\r
- POP 0x11\r
- READ 0x12\r
- WRITE 0x13\r
- POPDESC 0x15\r
-\r
-\r
- RDE GateWay Addresses encoding\r
- ==================================================\r
- bits7:0 structure other bits Relevant\r
- value accessed meaning Commands\r
- ==================================================\r
- 0 RDE release 17:16 - "00": release All Same\r
- final PIPE - "01": clear the error\r
- stage interrupt in FinalPipeStage,\r
- of Error so another Non-Zero\r
- syndrome will\r
- interrupt iRISC.\r
- (however, subsequent\r
- packets will not\r
- be executed)\r
- - "10": Generate an EXTRA\r
- Entry to CE with all\r
- parameters from RDE's\r
- FinalPipeStage (the\r
- "release" command\r
- will generate another\r
- entry, depends upon the\r
- IB_OpCode and syndrome)\r
- - "11": Generate ACK to CE with\r
- PSN-1\r
- (all parameters are\r
- taken from RDE's\r
- FinalPipeStage)\r
- ==================================================\r
- bits7:0 structure other bits Relevant\r
- value accessed meaning Commands\r
- ==================================================\r
- 1 RDE final PIPE stage 10:8 - line number READ/WRITE\r
- parameters 23:11 - RESERVED\r
- ---------------------------------------------------------------------------\r
- 2 Requester Scatter List 23:8 - ScatterList Pointer All Commands\r
- ---------------------------------------------------------------------------\r
- 3 CQPC 12:8 - CQPC index READ/WRITE\r
- 15:13 - RESERVED\r
- 17:16 - "00": CQPC Constants\r
- - "01": CQPC r256length\r
- - "10": CQPC RDB_and_more\r
- - "11": RESERVED\r
- 23:18 - RESERVED\r
- ---------------------------------------------------------------------------\r
- 4 Responder Scatter List 12:8 - CQPC index All Commands\r
- ---------------------------------------------------------------------------\r
- 5 NDA/CDA list and FALVs 12:8 - CQPC index READ/WRITE\r
- 15:13 - RESERVED\r
- 18:16 - 0: NDA, CDA contents\r
- WRITE ERAD\r
- *********************************\r
- For NDA, CDA:POP DESC. - 1: allocate_nda allocated_nda\r
- in addition:READ/WRITE - 2: lock_nda locked_nda\r
- For the FALVs:WRITE to - 3: free_nda freed_nda\r
- move the FALVs - 4: lock_dsl locked_dsl\r
- READ to see who is in this . - 5: unlock_dsl valid_nda\r
- FALV state. - 6: relock_dsl valid_dsl\r
- - 7: free_dsl freed_dsl\r
- 23:19 - RESERVED\r
- ---------------------------------------------------------------------------\r
- 6-255 RESERVED\r
- */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gwdata0[0x00012];\r
- pseudo_bit_t reserved0[0x0000e];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gwdata1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gwdata2[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gwdata3[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gwdata4[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00040];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @SDE_BIST */\r
-\r
-struct SDE_BIST_st { /* Little Endian */\r
- pseudo_bit_t sdebistgffd_wdw_0[0x00007];/* 137 */\r
- pseudo_bit_t reserved0[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sdebistgffd_wdw_1[0x00007];/* 137 */\r
- pseudo_bit_t reserved1[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sdebistgdpf0_wdw_0[0x00007];/* 139 */\r
- pseudo_bit_t reserved2[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sdebistgdpf0_wdw_1[0x00007];/* 139 */\r
- pseudo_bit_t reserved3[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sdebistgdpf1_wdw_0[0x00007];/* 140 */\r
- pseudo_bit_t reserved4[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sdebistgdpf1_wdw_1[0x00007];/* 140 */\r
- pseudo_bit_t reserved5[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sdebistgdpf2_wdw_0[0x00007];/* 140 */\r
- pseudo_bit_t reserved6[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sdebistgdpf2_wdw_1[0x00007];/* 140 */\r
- pseudo_bit_t reserved7[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sdebistgdpf3_wdw_0[0x00007];/* 140 */\r
- pseudo_bit_t reserved8[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sdebistgdpf3_wdw_1[0x00007];/* 140 */\r
- pseudo_bit_t reserved9[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sdebistgbl_rdw_0[0x00007];/* 134 */\r
- pseudo_bit_t reserved10[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sdebistgbl_rdw_1[0x00007];/* 134 */\r
- pseudo_bit_t reserved11[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sdebistgbr_rdw_0[0x00007];/* 134 */\r
- pseudo_bit_t reserved12[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sdebistgbr_rdw_1[0x00007];/* 134 */\r
- pseudo_bit_t reserved13[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rep_arrays_stat[0x0000e];\r
- pseudo_bit_t reserved14[0x00012];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bists_stat[0x0000a];\r
- pseudo_bit_t reserved15[0x00016];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nonrep_arrays_stat[0x00009];\r
- pseudo_bit_t reserved16[0x00017];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved17[0x00060];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @Gather Engine Causes when Gathered Data fo an EU (1 of 32) */\r
-\r
-struct GeEuCause_st { /* Little Endian */\r
- pseudo_bit_t excause[32][0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Cause Registers */\r
-\r
-struct SDE_CAUSEREG_st { /* Little Endian */\r
- pseudo_bit_t cr_slave_timeout[0x00001];\r
- pseudo_bit_t parity_err[0x00001];\r
- pseudo_bit_t reserved0[0x0001e];\r
-/* --------------------------------------------------------- */\r
- struct EXT_CAUSEREG_st extended_cause;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Send Data Engine General Configuration */\r
-\r
-struct SDEGRLCFG_st { /* Little Endian */\r
- struct TPTNSIIF_st getptnsi;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t xcredits[0x00005]; /* How many outstanding Xlations Twds TPT are allwed. Do NOT put more than 0x10 */\r
- pseudo_bit_t reserved0[0x0000b];\r
- pseudo_bit_t xused[0x00005]; /* how many TPT xlations are infligh */\r
- pseudo_bit_t reserved1[0x0000b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gff_credits_cfg[0x0000c];/* How many credits (16bytes) are in GatherFiller. Do NOT put more than 0x100 */\r
- pseudo_bit_t gff_usedcred[0x0000c]; /* how many lines in GatherFiller are used */\r
- pseudo_bit_t performance_gf_livelock[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t stop_tpt[0x00001]; /* stop tpt accesses */\r
- pseudo_bit_t tpt_stopped[0x00001]; /* no OutStanding TPT accesses */\r
- pseudo_bit_t reserved2[0x0001c];\r
- pseudo_bit_t stop_nsw[0x00001]; /* Stop Nswitch Accesses\r
- There is a bug in this bit.\r
- when you write 1 to bit 0 OR to bit 1 - this bi will be SET.\r
- if you write '1' to this bit - it will have no impact. */\r
- pseudo_bit_t nsw_stopped[0x00001]; /* no OutStanding NSW reads */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00018];\r
- pseudo_bit_t gp_cfg[0x00008]; /* General Purpose Configuration Register */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00160];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Gather Engine */\r
-\r
-struct GATHERENG_st { /* Little Endian */\r
- pseudo_bit_t portnum[0x00004]; /* Port Number to which the Gather Engine is connected */\r
- pseudo_bit_t reserved0[0x0001c];\r
-/* --------------------------------------------------------- */\r
- struct GASTAT_st ga_status;\r
-/* --------------------------------------------------------- */\r
- struct GECTORSTAT_st gector_status;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t max_linklist_entries[0x00006];/* what is the maximum entries in the Gather Linklist allowed. it is the upper bound of the number of OutStanding reads */\r
- pseudo_bit_t reserved1[0x00002];\r
- pseudo_bit_t busy_entries[0x00006]; /* how many linklist entries are in use */\r
- pseudo_bit_t reserved2[0x00012];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* SerDes DFT Register */\r
-\r
-struct SERDESDFT_st { /* Little Endian */\r
- pseudo_bit_t stop_pd1[0x00001];\r
- pseudo_bit_t stop_pd2[0x00001];\r
- pseudo_bit_t override_pd2[0x00001];\r
- pseudo_bit_t inc_pd2[0x00001];\r
- pseudo_bit_t pdsel[0x00001];\r
- pseudo_bit_t pdstate_en[0x00001]; /* This is an enable signal to pdstate. */\r
- pseudo_bit_t inc_pd1[0x00001];\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t reserved1[0x0000c];\r
- pseudo_bit_t pdstate[0x0000c];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* IB port Event2 */\r
-\r
-struct IB_port_Event2_st { /* Little Endian */\r
- pseudo_bit_t FCupdateWDtimer[0x00001];\r
- pseudo_bit_t GRHVL15discarded[0x00001];\r
- pseudo_bit_t RAWVL15discarded[0x00001];\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t P_KEYInboundDiscarded[0x00001];\r
- pseudo_bit_t P_KEYOutboundDiscarded[0x00001];\r
- pseudo_bit_t PortRcvEBP[0x00001];\r
- pseudo_bit_t PortXmitDiscardRaw[0x00001];\r
- pseudo_bit_t PortRcvBadFCop[0x00001];\r
- pseudo_bit_t ExcessiveBufferOverrunError[0x00001];\r
- pseudo_bit_t PortRcvPktSymbolError2[0x00001];\r
- pseudo_bit_t PortRcvRemotePhyErrors[0x00001];\r
- pseudo_bit_t PortXmitConstraintError[0x00001];\r
- pseudo_bit_t PortRcvConstraintError[0x00001];\r
- pseudo_bit_t reserved1[0x00001];\r
- pseudo_bit_t MCASTVL15discarded[0x00001];\r
- pseudo_bit_t CauseSigDet[0x00001];\r
- pseudo_bit_t CauseComDet[0x00001];\r
- pseudo_bit_t ConfigSpaceTimeOut[0x00001];\r
- pseudo_bit_t reserved2[0x00008];\r
- pseudo_bit_t reserved3[0x00001];\r
- pseudo_bit_t RQDatafifo1ParityError[0x00001];\r
- pseudo_bit_t RQDatafifo2ParityError[0x00001];\r
- pseudo_bit_t RQDescFIFOParityError[0x00001];\r
- pseudo_bit_t LoopBsckFIFOparityError[0x00001];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* IB Port Event */\r
-\r
-struct IB_port_event_st { /* Little Endian */\r
- pseudo_bit_t ProgFuncCounterCause[0x00001];/* Programmable_Function_Counter */\r
- pseudo_bit_t PortData[0x00001]; /* PortData */\r
- pseudo_bit_t PortRcvErrorsCause[0x00001];/* PortRcvErrors */\r
- pseudo_bit_t PortXmitPktDiscards[0x00001];/* PortXmitPktDiscards */\r
- pseudo_bit_t VL15Dropped[0x00001]; /* VL15Dropped */\r
- pseudo_bit_t PortRcvPktLen[0x00001];/* PortRcvPktLen */\r
- pseudo_bit_t PortRcvPktCRC[0x00001];/* PortRcvPktCRC */\r
- pseudo_bit_t PortRcvPktSymbolError[0x00001];/* PortRcvPktSymbolError */\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t PortRcvPktVL[0x00001]; /* PortRcvPktVL */\r
- pseudo_bit_t PortRcvCreditsExceeded[0x00001];/* PortRcvCreditsExceeded */\r
- pseudo_bit_t PortRcvDiscardOther[0x00001];/* PortRcvDiscardOther */\r
- pseudo_bit_t PortXmitHOQTimeout[0x00001];/* PortXmitHOQTimeout */\r
- pseudo_bit_t PortXmitExcessFC[0x00001];/* PortXmitExcessFC */\r
- pseudo_bit_t PortXmitInactive[0x00001];/* PortXmitInactive */\r
- pseudo_bit_t PortXmitMTUExceeded[0x00001];/* PortXmitMTUExceeded */\r
- pseudo_bit_t PortXmitDiscardOther[0x00001];/* PortXmitDiscardOther */\r
- pseudo_bit_t PortRcvFull[0x00001]; /* PortRcvFull */\r
- pseudo_bit_t PortRcvDynamicFull[0x00001];/* PortRcvDynamicFull */\r
- pseudo_bit_t PortRcvEmpty[0x00001]; /* PortRcvEmpty */\r
- pseudo_bit_t PortXmitVLArbLivelock[0x00001];/* PortXmitVLArbLivelock */\r
- pseudo_bit_t reserved1[0x00001];\r
- pseudo_bit_t PhyLinkUp[0x00001]; /* Phy_Link_Up */\r
- pseudo_bit_t PhyLinkDown[0x00001]; /* Phy_Link_Down */\r
- pseudo_bit_t PhyError[0x00001]; /* Phy_Error */\r
- pseudo_bit_t PhyUnsuccessfulTraining[0x00001];/* Phy_Unsuccessful_Training */\r
- pseudo_bit_t LocalLinkIntegrity[0x00001];/* Local_Link_Integrity */\r
- pseudo_bit_t SWControlled27[0x00001];/* SW Controlled Event 27 */\r
- pseudo_bit_t SWControlled28[0x00001];/* SW Controlled Event 28 */\r
- pseudo_bit_t reserved2[0x00001];\r
- pseudo_bit_t SWControlled30[0x00001];/* SW Controlled Event 30 */\r
- pseudo_bit_t SWControlled31[0x00001];/* SW Controlled Event 31 */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* IB Port IO Configuration */\r
-\r
-struct IB_port_IO_config_st { /* Little Endian */\r
- pseudo_bit_t SD[0x00005]; /* Sync Delay */\r
- pseudo_bit_t reserved0[0x00011];\r
- pseudo_bit_t ParallelLoopBack[0x00001];/* Operating in loopback mode - bypassing the serdes */\r
- pseudo_bit_t reserved1[0x00006];\r
- pseudo_bit_t IODD[0x00002]; /* I/O Data Delay */\r
- pseudo_bit_t reserved2[0x00001];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* IB Link Transmit */\r
-\r
-struct ib_link_transmit_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00011];\r
- pseudo_bit_t HCBTBD[0x00001]; /* Half Clock BtoB Disable */\r
- pseudo_bit_t MXTBSS[0x0000e]; /* Max Time between Skip Sets */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* NTU debug fsm */\r
-\r
-struct NTU_debug_fsm_st { /* Little Endian */\r
- pseudo_bit_t PCUPWcmd[0x00001];\r
- pseudo_bit_t PCUPWdata[0x00001];\r
- pseudo_bit_t PCUPWovf[0x00001];\r
- pseudo_bit_t reserved0[0x00002];\r
- pseudo_bit_t PCUNPcmd[0x00001];\r
- pseudo_bit_t PCUNPdata[0x00001];\r
- pseudo_bit_t PCUNPovf[0x00001];\r
- pseudo_bit_t reserved1[0x00002];\r
- pseudo_bit_t HCAPWcmd[0x00001];\r
- pseudo_bit_t HCAPWdata[0x00001];\r
- pseudo_bit_t HCAPWovf[0x00001];\r
- pseudo_bit_t reserved2[0x00002];\r
- pseudo_bit_t HCANPcmd[0x00001];\r
- pseudo_bit_t HCANPdata[0x00001];\r
- pseudo_bit_t HCANPovf[0x00001];\r
- pseudo_bit_t reserved3[0x0000e];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntpsm_cmd_ps[0x00004];\r
- pseudo_bit_t ntpsm_rdplc_ps[0x00002];\r
- pseudo_bit_t ntpsm_attwr_ps[0x00002];\r
- pseudo_bit_t ntpsm_err_ps[0x00003];\r
- pseudo_bit_t reserved4[0x00001];\r
- pseudo_bit_t ntpsm_att_ps[0x00003];\r
- pseudo_bit_t ntpsm_att_empty[0x00001];\r
- pseudo_bit_t reserved5[0x00002];\r
- pseudo_bit_t ntpsm_main_ps[0x00002];\r
- pseudo_bit_t ntpsm_desc_ps[0x00003];\r
- pseudo_bit_t ntpsm_drbl_ps[0x00002];\r
- pseudo_bit_t reserved6[0x00003];\r
- pseudo_bit_t ntpsm_ge_copy_ps_0_[0x00001];\r
- pseudo_bit_t ntpsm_ge_copy_ps_1_[0x00001];\r
- pseudo_bit_t ntpsm_ge_copy_ps_2_[0x00001];\r
- pseudo_bit_t ntpsm_ge_copy_ps_3_[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntdl_arb_ps[0x00003];\r
- pseudo_bit_t ntdl_wr_ps[0x00003];\r
- pseudo_bit_t ntdl_rd_ps[0x00002];\r
- pseudo_bit_t ntdl_cmp_ps[0x00003];\r
- pseudo_bit_t ntdl_empty_ps[0x00002];\r
- pseudo_bit_t ntdl_pall_ps[0x00002];\r
- pseudo_bit_t ntdl_empty_cnt[0x00008];\r
- pseudo_bit_t reserved7[0x00003];\r
- pseudo_bit_t ntob_hit_ps[0x00002];\r
- pseudo_bit_t ntob_nout_ps[0x00004];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntcq_ca_ps[0x00002];\r
- pseudo_bit_t ntcq_entry_valid_0_[0x00001];\r
- pseudo_bit_t ntcq_entry_valid_1_[0x00001];\r
- pseudo_bit_t ntcq_entry_valid_2_[0x00001];\r
- pseudo_bit_t ntcq_entry_valid_3_[0x00001];\r
- pseudo_bit_t ntcq_wr_ps[0x00002];\r
- pseudo_bit_t ntcq_err_if_0_[0x00001];\r
- pseudo_bit_t ntcq_err_if_1_[0x00001];\r
- pseudo_bit_t reserved8[0x00004];\r
- pseudo_bit_t nthw_rdr_ps[0x00003];\r
- pseudo_bit_t nthw_buffer_valid_0_[0x00001];\r
- pseudo_bit_t nthw_buffer_valid_1_[0x00001];\r
- pseudo_bit_t nthw_buffer_valid_2_[0x00001];\r
- pseudo_bit_t nthw_buffer_valid_3_[0x00001];\r
- pseudo_bit_t reserved9[0x00009];\r
- pseudo_bit_t ntcfg_arb_ps[0x00002];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nttx_hca_tx_arb[0x00001];\r
- pseudo_bit_t nttx_hca_tx_ps[0x00003];\r
- pseudo_bit_t nttx_hca_pcrd[0x00003];\r
- pseudo_bit_t nttx_hca_rcrd[0x00003];\r
- pseudo_bit_t reserved10[0x00003];\r
- pseudo_bit_t nttx_pci_tx_arb[0x00002];\r
- pseudo_bit_t nttx_pci_tx_ps[0x00003];\r
- pseudo_bit_t nttx_pci_rcrd[0x00003];\r
- pseudo_bit_t reserved11[0x00008];\r
- pseudo_bit_t nthr_rd_ps[0x00003];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved12[0x00060];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* NTU PCU Error FIFO Gateway */\r
-\r
-struct NTUERRFIFO_st { /* Little Endian */\r
- struct GWCONTROL_NTU_st ntuerrfifoctrl;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t NSB_syndrome[0x00008];\r
- pseudo_bit_t reserved0[0x00016];\r
- pseudo_bit_t err_IO[0x00001];\r
- pseudo_bit_t err_RW[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t NSB_Address_63_32[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t NSB_Address_31_0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ERR_NSB_Size[0x00010];\r
- pseudo_bit_t NSB_Seq_Id[0x00008];\r
- pseudo_bit_t NSB_segm[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00060];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* NTU NSB Attribute FIFO */\r
-\r
-struct NTUATTRFIFO_st { /* Little Endian */\r
- struct GWCONTROL_NTU_st ntuattrfifoctrl;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ATTR_QPN[0x00018];\r
- pseudo_bit_t S[0x00001];\r
- pseudo_bit_t SR[0x00001];\r
- pseudo_bit_t DB[0x00002];\r
- pseudo_bit_t PW[0x00001];\r
- pseudo_bit_t att_RW[0x00001];\r
- pseudo_bit_t C[0x00001];\r
- pseudo_bit_t att_CMD[0x00001]; /* Differs between command and data */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Read_Prefetch_Length[0x0000c];/* or Data */\r
- pseudo_bit_t MTU[0x00003]; /* Maximum Transfer Unit\r
- or Data */\r
- pseudo_bit_t Data_Size[0x00009]; /* or Data */\r
- pseudo_bit_t Data[0x00008]; /* valid only for data\r
- Reserved in command */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t RADR_95_64[0x00020]; /* or Data */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t RADR_63_32[0x00020]; /* or Data */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t RADR_31_0[0x00020]; /* or Data */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00040];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* NTU NSW Cell Exception FIFO */\r
-\r
-struct NTUEXCPFIFO_st { /* Little Endian */\r
- struct GWCONTROL_NTU_st ntuexcgwctrl;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ExecFifo_QPN[0x00018]; /* Queue pair number */\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t exc_rdb[0x00001];\r
- pseudo_bit_t exc_int[0x00001];\r
- pseudo_bit_t WRM[0x00001];\r
- pseudo_bit_t exc_fence[0x00002];\r
- pseudo_bit_t exc_err[0x00001];\r
- pseudo_bit_t exc_CMD[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t NSB_Address_H[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t NSB_Address_L[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Exec_NSB_Size[0x00010];\r
- pseudo_bit_t exc_NSB_Seq_Id[0x00008];\r
- pseudo_bit_t exc_NSB_Segm[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t exc_data[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t exc_io[0x00001];\r
- pseudo_bit_t NP[0x00001];\r
- pseudo_bit_t exc_RW[0x00001];\r
- pseudo_bit_t reserved1[0x0001d];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* NTU Events */\r
-\r
-struct NTUEVENTS_st { /* Little Endian */\r
- struct QLTMISSINFO_st qltmissinfo;\r
-/* --------------------------------------------------------- */\r
- struct COMPERRINFO_st comperrinfo;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00080];\r
-/* --------------------------------------------------------- */\r
- struct NTU_PERF_st ntu_perf; /* NTU Performance Counter Interrupt Info Register (see Datasheet) */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00100];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* NTU Descriptors Gateway */\r
-\r
-struct NTUDESCGW_st { /* Little Endian */\r
- struct GWCONTROL_NTU_st ntudescgwctrl;/* NTU Descriptor Gateway Control Reister\r
-\r
- Command:\r
- 0x00 Reserved\r
- 0x01 Read Data and NextPtr - Address is entry number in FIFO (8bits)\r
- 0x02 Write Data and NextPtr - Address is entry number in FIFO (8bits)\r
- 0x03 Pop - Address is QP# (7 bit)\r
- 0x04 Push - Address is QP# (7bit)\r
- 0x05-0x3F Reserved\r
-\r
- Status\r
- 0x00 OK\r
- 0x01-0x3F Reserved */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t fatal_err_ext_synd[0x00018];/* desriptor entry0 [127:96] */\r
- pseudo_bit_t fatal_err_synd[0x00008];/* descriptor entry0 [95:64] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_ip[0x00020]; /* descriptor entry0 [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tcu_ip[0x00020]; /* descriptor entry0 [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t exer_ip[0x00020]; /* descriptor entry1 [127:96] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t exes_ip[0x00020]; /* descriptor entry1 [95:64] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_ip[0x00020]; /* descriptor entry1 [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntu_ip[0x00020]; /* descriptor entry1 [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t fatal_err_int[0x00008];\r
- pseudo_bit_t reserved9[0x00008];\r
- pseudo_bit_t last_size[0x00002];\r
- pseudo_bit_t reserved10[0x00006];\r
- pseudo_bit_t write_push_opcode[0x00002];/* Descriptor opcode */\r
- pseudo_bit_t reserved11[0x00006];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntuemptyptr[0x00008]; /* acces to empty pointer */\r
- pseudo_bit_t reserved12[0x00008];\r
- pseudo_bit_t empty_counter[0x00008];\r
- pseudo_bit_t reserved13[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntudescQPN[0x00018]; /* Queue Pair Number */\r
- pseudo_bit_t reserved14[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved15[0x00180];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* NTU QP Window Context Gateway */\r
-\r
-struct NTUQPWGW_st { /* Little Endian */\r
- struct GWCONTROL_NTU_st ntuqpwgwctrl;/* NTU QP Window Context Gateway Control\r
-\r
- Command\r
- 0x00 Reserved\r
- 0x01 Read\r
- 0x02 Write\r
- 0x03-0x3F Reserved\r
-\r
- Status\r
- 0x00 OK\r
- 0x01-0x3F Reserved\r
-\r
- Address\r
- QPN in bits 6:0 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t First[0x00008];\r
- pseudo_bit_t reserved0[0x00008];\r
- pseudo_bit_t Last[0x00008];\r
- pseudo_bit_t reserved1[0x00007];\r
- pseudo_bit_t V[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00007];\r
- pseudo_bit_t QPN_23_7[0x00011];\r
- pseudo_bit_t reserved3[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* NTU QLT Gateway */\r
-\r
-struct NTUQLTGW_st { /* Little Endian */\r
- struct GWCONTROL_NTU_st ntuqltgw; /* NTU Gateway Control Register\r
-\r
- Commands:\r
- 0x00 Reserved\r
- 0x01 Read\r
- 0x02 Write\r
- 0x03 Make Valid (validates more than required. bug 4986)\r
- 0x04 Make Invalid (invalidates more than required. bug 4986)\r
- 0x05-0x3F Reserved\r
-\r
- Status\r
- 0x00 OK\r
- 0x01 Error\r
- 0x01-0x3F Reserved\r
-\r
- QLT Address is in bits 6:0 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t WM[0x00002];\r
- pseudo_bit_t MTU[0x00003];\r
- pseudo_bit_t reserved0[0x00003];\r
- pseudo_bit_t Read_Length[0x00008];\r
- pseudo_bit_t reserved1[0x0000a];\r
- pseudo_bit_t Fence[0x00002]; /* 00 - Normal flow\r
- 01 - Reserved\r
- 10 - Breakpoint, no fence\r
- 11 - Breakpoint with fence - don't use it, see bug 5130 */\r
- pseudo_bit_t qlt_e[0x00001];\r
- pseudo_bit_t S[0x00001];\r
- pseudo_bit_t S_R_[0x00001];\r
- pseudo_bit_t Err[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t TAG_47_32[0x00010];\r
- pseudo_bit_t reserved3[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t TAG_31_0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Virtual_Address_63_32[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x0000c];\r
- pseudo_bit_t Virtual_Address_31_12[0x00014];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t RKey[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Target_QPN[0x00018];\r
- pseudo_bit_t reserved6[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x000c0];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @ntu bist */\r
-\r
-struct NTU_BIST_st { /* Little Endian */\r
- pseudo_bit_t ntbist_qlt_msb_rdw_0[0x00007];/* 144 */\r
- pseudo_bit_t reserved0[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntbist_desc_rdw_0[0x00007];/* 135 */\r
- pseudo_bit_t reserved1[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntbist_desc_rdw_1[0x00007];/* 135 */\r
- pseudo_bit_t reserved2[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntbist_rdb_rdw_0[0x00007];/* 132 */\r
- pseudo_bit_t reserved3[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntbist_rdb_rdw_1[0x00007];/* 133 */\r
- pseudo_bit_t reserved4[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntbist_rdb_rdw_2[0x00007];/* 133 */\r
- pseudo_bit_t reserved5[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntbist_rdb_rdw_3[0x00007];/* 133 */\r
- pseudo_bit_t reserved6[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntbist_hca_rx_pfifo_wdw_0[0x00007];/* 160 */\r
- pseudo_bit_t reserved7[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntbist_hca_rx_pfifo_wdw_1[0x00007];/* 160 */\r
- pseudo_bit_t reserved8[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntbist_hca_rx_pfifo_wdw_2[0x00007];/* 160 */\r
- pseudo_bit_t reserved9[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntbist_hca_rx_pfifo_wdw_3[0x00007];/* 160 */\r
- pseudo_bit_t reserved10[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntbist_pci_rx_pfifo_wdw_0[0x00007];/* 160 */\r
- pseudo_bit_t reserved11[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntbist_pci_rx_pfifo_wdw_1[0x00007];/* 160 */\r
- pseudo_bit_t reserved12[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntbist_pci_rx_pfifo_wdw_2[0x00007];/* 160 */\r
- pseudo_bit_t reserved13[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntbist_pci_rx_pfifo_wdw_3[0x00007];/* 160 */\r
- pseudo_bit_t reserved14[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist2waydata_data_rdw_0[0x00006];/* 158 */\r
- pseudo_bit_t reserved15[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist2waydata_data_rdw_1[0x00006];/* 158 */\r
- pseudo_bit_t reserved16[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist4waydata_code_rdw_0[0x00006];/* 158 */\r
- pseudo_bit_t reserved17[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist4waydata_code_rdw_1[0x00006];/* 158 */\r
- pseudo_bit_t reserved18[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist4waydata_code_rdw_2[0x00006];/* 158 */\r
- pseudo_bit_t reserved19[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist4waydata_code_rdw_3[0x00006];/* 158 */\r
- pseudo_bit_t reserved20[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rep_arrays_stat[0x00015];\r
- pseudo_bit_t reserved21[0x0000b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bists_stat[0x0000f];\r
- pseudo_bit_t reserved22[0x00011];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nonrep_arrays_stat[0x00011];\r
- pseudo_bit_t reserved23[0x0000f];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved24[0x00100];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @NTUWRB */\r
-\r
-struct NTUWRB_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x0001d];\r
- pseudo_bit_t clr[0x00001];\r
- pseudo_bit_t kill[0x00001];\r
- pseudo_bit_t err[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpn[0x00018];\r
- pseudo_bit_t nda[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00040];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00016];\r
- pseudo_bit_t wrb_fsm[0x00003];\r
- pseudo_bit_t reserved3[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t wrb_nsb_current_address_63_32[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t wrb_nsb_current_address_31_0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t wrb_nsb_current_size[0x0000c];\r
- pseudo_bit_t reserved5[0x00003];\r
- pseudo_bit_t io[0x00001];\r
- pseudo_bit_t wrb_nsb_current_sequence_id[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x000e0];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @NTURDB */\r
-\r
-struct NTURDB_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x0001d];\r
- pseudo_bit_t clr[0x00001];\r
- pseudo_bit_t kill[0x00001];\r
- pseudo_bit_t err[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t QPN[0x0001b];\r
- pseudo_bit_t NDA[0x00001];\r
- pseudo_bit_t reserved1[0x00004];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdb_start_address[0x0001b];\r
- pseudo_bit_t reserved2[0x00005];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdb_prefetch_address[0x0001b];\r
- pseudo_bit_t reserved3[0x00004];\r
- pseudo_bit_t wm[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdb_in_counter[0x00008];\r
- pseudo_bit_t rdb_sampled_size[0x0000c];\r
- pseudo_bit_t flush[0x00001];\r
- pseudo_bit_t error[0x00001];\r
- pseudo_bit_t rdb_fsm[0x00003];\r
- pseudo_bit_t rdb_out_fsm[0x00003];\r
- pseudo_bit_t reserved4[0x00004];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdb_read_valid_counter[0x00010];\r
- pseudo_bit_t reserved5[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdb_nsb_current_address_63_32[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdb_nsb_current_address_31_0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdb_nsb_current_size[0x0000c];\r
- pseudo_bit_t reserved6[0x00003];\r
- pseudo_bit_t io[0x00001];\r
- pseudo_bit_t rdb_nsb_current_sequence_id[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rdb_prefetch_size[0x0000c];\r
- pseudo_bit_t reserved7[0x00014];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x000c0];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct CAUSEREG_st { /* Little Endian */\r
- pseudo_bit_t cause[0x00020]; /* cause register data */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t clrcause[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t setcause[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t evtserviced[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t evtena0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t evtena1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00040];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Fencing causes every PCU transaction to be routed to error FIFO instead of normal flow. - This table controls that */\r
-\r
-struct NTUFENCE_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x0001e];\r
- pseudo_bit_t fence_trap_clr[0x00001];\r
- pseudo_bit_t fence_trap_set[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00060];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @NTUQLTVALID */\r
-\r
-struct NTUQLTVALID_st { /* Little Endian */\r
- pseudo_bit_t valid0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t valid1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t valid2[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t valid3[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* NTU General Configuration */\r
-\r
-struct NTUGENERAL_st { /* Little Endian */\r
- pseudo_bit_t NtuDdestid[0x00003]; /* N-Switch id of NTU\r
- gen_reg_0[2:0]\r
- ntcfg_dest_id_2_0 */\r
- pseudo_bit_t PciDestid[0x00003]; /* N-Switch id of PCU\r
- gen_reg_0[5:3]\r
- ntcfg_dest_id_5_3 */\r
- pseudo_bit_t HcaDestid[0x00003]; /* N-Switch id of HCA\r
- gen_reg_0[8:6]\r
- ntcfg_dest_id_8_6 */\r
- pseudo_bit_t DmuDestid[0x00003]; /* N-Switch id of DMU\r
- gen_reg_0[11:9]\r
- ntcfg_dest_id_11_9 */\r
- pseudo_bit_t LdtDestid[0x00003];\r
- pseudo_bit_t reserved0[0x0000f];\r
- pseudo_bit_t RDB_mode[0x00001];\r
- pseudo_bit_t WRM[0x00001]; /* ???\r
- gen_reg_0[12:12] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t NSWriteCutTimeOut[0x00008];/* counted time of woting for NS-trans from PCU , before cutting this trans , and sending a Blue-Flame to HCA\r
- gen_reg_1[7:0]\r
- ntcfg_ntu_wrto */\r
- pseudo_bit_t Desc_array_size[0x00002];\r
- pseudo_bit_t reserved1[0x00006];\r
- pseudo_bit_t HCA_syndrome[0x00008];\r
- pseudo_bit_t PCI_syndrome[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t p2p_page_size[0x00004];/* page size at qlt\r
- gen_reg_2[3:0]\r
-\r
- page_size encoding\r
- 0000 - 4KB\r
- 0001 - 8KB\r
- 0010 - 64KB\r
- 0011 - 1MB\r
- 0100 - 4MB\r
- 0101 - 16MB\r
- 0110 - 64MB\r
- 0111 - 128MB\r
- 1000 -1111 - Reseved\r
- */\r
- pseudo_bit_t reserved2[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00040];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t PCU_RX_rsp_cred[0x00003];\r
- pseudo_bit_t reserved4[0x00001];\r
- pseudo_bit_t PCU_RX_pw_cred[0x00004];\r
- pseudo_bit_t reserved5[0x00004];\r
- pseudo_bit_t PCU_RX_np_cred[0x00003];\r
- pseudo_bit_t reserved6[0x00001];\r
- pseudo_bit_t PCU_TX_rsp_cred[0x00003];\r
- pseudo_bit_t reserved7[0x00001];\r
- pseudo_bit_t PCU_TX_pw_cred[0x00003];\r
- pseudo_bit_t reserved8[0x00001];\r
- pseudo_bit_t PCU_TX_np_cred[0x00003];\r
- pseudo_bit_t reserved9[0x00005];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t HCA_RX_rsp_cred[0x00003];\r
- pseudo_bit_t reserved10[0x00001];\r
- pseudo_bit_t HCA_RX_pw_cred[0x00003];\r
- pseudo_bit_t reserved11[0x00005];\r
- pseudo_bit_t HCA_RX_np_cred[0x00003];\r
- pseudo_bit_t reserved12[0x00001];\r
- pseudo_bit_t HCA_TX_rsp_cred[0x00003];\r
- pseudo_bit_t reserved13[0x00001];\r
- pseudo_bit_t HCA_TX_pw_cred[0x00003];\r
- pseudo_bit_t reserved14[0x00001];\r
- pseudo_bit_t HCA_TX_np_cred[0x00003];\r
- pseudo_bit_t reserved15[0x00005];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t RdResponseValidTimeout[0x00010];/* ???\r
- gen_reg_6[15:0] */\r
- pseudo_bit_t reserved16[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t gp_cfg[0x00008]; /* general purpose configuration register */\r
- pseudo_bit_t reserved17[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved18[0x000e0];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* North Swith Bus Address Decoding */\r
-\r
-struct NSWADDRDEC_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00180];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntu_bar_0_msbs[0x00020];/* This bar is used for completions, scatters and descriptor reads from the HCA to the NTU */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntu_bar_size[0x00006]; /* in megabytes (minimum 2) */\r
- pseudo_bit_t reserved1[0x00002];\r
- pseudo_bit_t enable_ntu_0[0x00001];\r
- pseudo_bit_t reserved2[0x0000b];\r
- pseudo_bit_t ntu_bar_0_lsbs[0x0000c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00040];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t hca_bar_msbs[0x00020]; /* UAR in the HCA for D.B. and B.F. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t hca_bar_size[0x00006];\r
- pseudo_bit_t reserved4[0x00002];\r
- pseudo_bit_t enable_hca[0x00001];\r
- pseudo_bit_t reserved5[0x0000b];\r
- pseudo_bit_t hca_bar_lsbs[0x0000c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x005c0];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* SW Access to DIMMs Control Registers */\r
-\r
-struct dmu_chk_dimm_st { /* Little Endian */\r
- struct GWCONTROL_st chk_gwctl; /* commad= 0 - resereved.\r
- commad = 1 - init request\r
- commad = 2 - sr request\r
- commad = 3 - xsr request\r
- commad = 4 - chk wr request\r
- commad = 5 - chk rd request\r
- commad = 6 - chk wr then read then compare request\r
- commad = 7 - chk stop request\r
- commad = 8 - chk wr calibration request\r
- commad = 9 - reset dqs registers in the IO.\r
- commad = 10 - start calibration stage 0\r
- commad = 11 - start calibration stage 1 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t stretch_en[0x00001]; /* when high the strech circutis is enable */\r
- pseudo_bit_t calib_cfg_test[0x00001];/* the activate the calibration process by the IRISC */\r
- pseudo_bit_t short_calib0[0x00001];\r
- pseudo_bit_t calib_rd_dqsen_dly[0x00004];/* the dly of poping the data from the EB relative to\r
- the calibrated dqs_en !! */\r
- pseudo_bit_t reserved0[0x00009];\r
- pseudo_bit_t nondist_mode[0x00001]; /* when high the calibration is perfromed with no distractive to data */\r
- pseudo_bit_t nondist_cnt[0x00004]; /* for the dqs en calibration in non destructive mode */\r
- pseudo_bit_t rrelim_en[0x00001];\r
- pseudo_bit_t rrelim_lim[0x00006];\r
- pseudo_bit_t reserved1[0x00004];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t calib0_rst_cnt[0x00004];\r
- pseudo_bit_t calib0_dqsen_cnt[0x00004];\r
- pseudo_bit_t calib0_hold_cnt[0x00004];\r
- pseudo_bit_t calib1_rst_cnt[0x00004];\r
- pseudo_bit_t calib1_hold_cnt[0x00004];\r
- pseudo_bit_t reserved2[0x0000c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t dly_clka_0[0x00005];\r
- pseudo_bit_t dly_clka_2[0x00005];\r
- pseudo_bit_t dly_clka_1[0x00005];\r
- pseudo_bit_t dly_clkb_0[0x00005];\r
- pseudo_bit_t dly_clkb_1[0x00005];\r
- pseudo_bit_t dly_clkb_2[0x00005];\r
- pseudo_bit_t reserved3[0x00002];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00040];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t chk_end_da[0x00002];\r
- pseudo_bit_t chk_end_ba[0x00002];\r
- pseudo_bit_t chk_start_da[0x00002];\r
- pseudo_bit_t chk_start_ba[0x00002];\r
- pseudo_bit_t chk_ap_mode[0x00002];\r
- pseudo_bit_t reserved5[0x00016];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t chk_start_ra[0x00010];\r
- pseudo_bit_t chk_start_ca[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t chk_end_ra[0x00010];\r
- pseudo_bit_t chk_end_ca[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t chk_clib_pad[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ca_in_check[0x00010]; /* current column address in the check process */\r
- pseudo_bit_t ra_in_check[0x00010]; /* current row address in the check process */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t da_in_chk[0x00002];\r
- pseudo_bit_t ba_in_chk[0x00002];\r
- pseudo_bit_t reserved6[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x001e0];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pvt_en[0x00001]; /* when high the pvt circuit is enabled */\r
- pseudo_bit_t rddqs_drift_dly[0x00002];/* the dly boundry for the dqs to dected dqs drift */\r
- pseudo_bit_t dq_delay[0x00002]; /* Controls the delay of the dq[63:0] and ecc[7:0] pads in the read path. */\r
- pseudo_bit_t reserved8[0x00003];\r
- pseudo_bit_t mdat_powerup[0x00001]; /* when high the dimm input are enabled !! */\r
- pseudo_bit_t mecc_powerup[0x00001];\r
- pseudo_bit_t mdatx4_powerup[0x00001];\r
- pseudo_bit_t meccx4_powerup[0x00001];\r
- pseudo_bit_t reserved9[0x00004];\r
- pseudo_bit_t mclka_oe[0x00003]; /* clock group A OE */\r
- pseudo_bit_t mclkb_oe[0x00003]; /* clock group B OE */\r
- pseudo_bit_t mrst_oe[0x00001]; /* the dram reset OE */\r
- pseudo_bit_t mckea_en_oe[0x00001]; /* the cke 'A' OE */\r
- pseudo_bit_t mckeb_en_oe[0x00001]; /* the clock enable B OE */\r
- pseudo_bit_t mcmda_oe[0x00001]; /* oe for all the signals in command A */\r
- pseudo_bit_t mcmdb_oe[0x00001]; /* oe of all command B group */\r
- pseudo_bit_t mdat_oe[0x00001]; /* OE for all the dq/dqs/dqm of the data outputs */\r
- pseudo_bit_t mecc_oe[0x00001]; /* OE for all the dq/dqs/dqm of the data outputs */\r
- pseudo_bit_t reserved10[0x00003];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pvt_res0[0x00020]; /* the pvt map from the dmu io */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pvt_res1[0x00020]; /* the pvt map from the dmu io */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pvt_res2[0x00020]; /* the pvt map from the dmu io */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pvt_res3[0x00020]; /* the pvt map from the dmu io */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved11[0x00400];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t dimm0_chk_pad[16][0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t dimm1_chk_pad[16][0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t dimm2_chk_pad[16][0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t dimm3_chk_pad[16][0x00020];\r
-/* --------------------------------------------------------- */\r
- struct DMURDDQSCLB_st dmurddqsclb0;\r
-/* --------------------------------------------------------- */\r
- struct DMURDDQSCLB_st dmurddqsclb1;\r
-/* --------------------------------------------------------- */\r
- struct DMURDDQSCLB_st dmurddqsclb2;\r
-/* --------------------------------------------------------- */\r
- struct DMURDDQSCLB_st dmurddqsclb3;\r
-/* --------------------------------------------------------- */\r
- struct DMURDDQSCLB_st dmurddqsclb4;\r
-/* --------------------------------------------------------- */\r
- struct DMURDDQSCLB_st dmurddqsclb5;\r
-/* --------------------------------------------------------- */\r
- struct DMURDDQSCLB_st dmurddqsclb6;\r
-/* --------------------------------------------------------- */\r
- struct DMURDDQSCLB_st dmurddqsclb7;\r
-/* --------------------------------------------------------- */\r
- struct DMURDDQSCLB_st dmurddqsclb8;\r
-/* --------------------------------------------------------- */\r
- struct DMURDDQSCLB_st dmurddqsclb9;\r
-/* --------------------------------------------------------- */\r
- struct DMURDDQSCLB_st dmurddqsclb10;\r
-/* --------------------------------------------------------- */\r
- struct DMURDDQSCLB_st dmurddqsclb11;\r
-/* --------------------------------------------------------- */\r
- struct DMURDDQSCLB_st dmurddqsclb12;\r
-/* --------------------------------------------------------- */\r
- struct DMURDDQSCLB_st dmurddqsclb13;\r
-/* --------------------------------------------------------- */\r
- struct DMURDDQSCLB_st dmurddqsclb14;\r
-/* --------------------------------------------------------- */\r
- struct DMURDDQSCLB_st dmurddqsclb15;\r
-/* --------------------------------------------------------- */\r
- struct DMURDDQSCLB_st dmurddqsclb16;\r
-/* --------------------------------------------------------- */\r
- struct DMURDDQSCLB_st dmurddqsclb17;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved12[0x00080];\r
-/* --------------------------------------------------------- */\r
- struct DmuRdDqsenClb_st dmurddqsenclb0;\r
-/* --------------------------------------------------------- */\r
- struct DmuRdDqsenClb_st dmurddqsenclb1;\r
-/* --------------------------------------------------------- */\r
- struct DmuRdDqsenClb_st dmurddqsenclb2;\r
-/* --------------------------------------------------------- */\r
- struct DmuRdDqsenClb_st dmurddqsenclb3;\r
-/* --------------------------------------------------------- */\r
- struct DmuRdDqsenClb_st dmurddqsenclb4;\r
-/* --------------------------------------------------------- */\r
- struct DmuRdDqsenClb_st dmurddqsenclb5;\r
-/* --------------------------------------------------------- */\r
- struct DmuRdDqsenClb_st dmurddqsenclb6;\r
-/* --------------------------------------------------------- */\r
- struct DmuRdDqsenClb_st dmurddqsenclb7;\r
-/* --------------------------------------------------------- */\r
- struct DmuRdDqsenClb_st dmurddqsenclb8;\r
-/* --------------------------------------------------------- */\r
- struct DmuRdDqsenClb_st dmurddqsenclb9;\r
-/* --------------------------------------------------------- */\r
- struct DmuRdDqsenClb_st dmurddqsenclb10;\r
-/* --------------------------------------------------------- */\r
- struct DmuRdDqsenClb_st dmurddqsenclb11;\r
-/* --------------------------------------------------------- */\r
- struct DmuRdDqsenClb_st dmurddqsenclb12;\r
-/* --------------------------------------------------------- */\r
- struct DmuRdDqsenClb_st dmurddqsenclb13;\r
-/* --------------------------------------------------------- */\r
- struct DmuRdDqsenClb_st dmurddqsenclb14;\r
-/* --------------------------------------------------------- */\r
- struct DmuRdDqsenClb_st dmurddqsenclb15;\r
-/* --------------------------------------------------------- */\r
- struct DmuRdDqsenClb_st dmurddqsenclb16;\r
-/* --------------------------------------------------------- */\r
- struct DmuRdDqsenClb_st dmurddqsenclb17;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved13[0x00200];\r
-/* --------------------------------------------------------- */\r
- struct DMUWRCLB_st dmuwrclb0;\r
-/* --------------------------------------------------------- */\r
- struct DMUWRCLB_st dmuwrclb1;\r
-/* --------------------------------------------------------- */\r
- struct DMUWRCLB_st dmuwrclb2;\r
-/* --------------------------------------------------------- */\r
- struct DMUWRCLB_st dmuwrclb3;\r
-/* --------------------------------------------------------- */\r
- struct DMUWRCLB_st dmuwrclb4;\r
-/* --------------------------------------------------------- */\r
- struct DMUWRCLB_st dmuwrclb5;\r
-/* --------------------------------------------------------- */\r
- struct DMUWRCLB_st dmuwrclb6;\r
-/* --------------------------------------------------------- */\r
- struct DMUWRCLB_st dmuwrclb7;\r
-/* --------------------------------------------------------- */\r
- struct DMUWRCLB_st dmuwrclb8;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved14[0x005c0];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* DIMM Configuration */\r
-\r
-struct DIMMConfig_st { /* Little Endian */\r
- struct DIMMGeneralConfig_st DIMMGeneralConfig;\r
-/* --------------------------------------------------------- */\r
- struct DIMM_timimg_config_st DIMMTimingConfig;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* DMU Debug External Domain */\r
-\r
-struct DMUDEBUGEXT_st { /* Little Endian */\r
- pseudo_bit_t chk_err[0x00001]; /* check machine error reporting due to data mismatch in\r
- the WR/RD/COMPARE command. */\r
- pseudo_bit_t tx_rdinfly_perr[0x00001];\r
- pseudo_bit_t tx_rmwfifo_perr[0x00001];\r
- pseudo_bit_t rx_datafifo_perr0[0x00001];\r
- pseudo_bit_t rx_np_cmdfifo_perr0[0x00001];\r
- pseudo_bit_t rx_p_cmdfifo_perr0[0x00001];\r
- pseudo_bit_t rx_datafifo_perr1[0x00001];\r
- pseudo_bit_t rx_np_cmdfifo_perr1[0x00001];\r
- pseudo_bit_t rx_p_cmdfifo_perr1[0x00001];\r
- pseudo_bit_t tx_rmwfifo_underrun[0x00001];\r
- pseudo_bit_t tx_rdinfly_underrun[0x00001];\r
- pseudo_bit_t tx_rmwfifo_overflow[0x00001];\r
- pseudo_bit_t tx_rdinfly_overflow[0x00001];\r
- pseudo_bit_t tx_cmdfifo_overflow[0x00001];\r
- pseudo_bit_t tx_datafifo_overflow[0x00001];\r
- pseudo_bit_t tx_errfifo_overflow[0x00001];\r
- pseudo_bit_t rx_p_datafifo_underrun0[0x00001];\r
- pseudo_bit_t rx_p_cmdfifo_underrun0[0x00001];\r
- pseudo_bit_t rx_np_datafifo_underrun0[0x00001];\r
- pseudo_bit_t rx_np_cmdfifo_underrun0[0x00001];\r
- pseudo_bit_t rx_p_datafifo_underrun1[0x00001];\r
- pseudo_bit_t rx_p_cmdfifo_underrun1[0x00001];\r
- pseudo_bit_t rx_np_datafifo_underrun1[0x00001];\r
- pseudo_bit_t rx_np_cmdfifo_underrun1[0x00001];\r
- pseudo_bit_t reserved0[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00060];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* DMU status registers */\r
-\r
-struct dmustatus_st { /* Little Endian */\r
- pseudo_bit_t init_in_process[0x00001];/* the dimms init process is alive */\r
- pseudo_bit_t ar_in_process[0x00001];/* the auto refresh is in process */\r
- pseudo_bit_t sr_in_process[0x00001];/* self refresh in process */\r
- pseudo_bit_t sr_done[0x00001]; /* the self refresh process is over ( exit self refresh can be asserted) */\r
- pseudo_bit_t xsr_in_process[0x00001];/* exiting from self refresh is in process */\r
- pseudo_bit_t chk_in_process[0x00001];/* the check dimm machine is working */\r
- pseudo_bit_t calib0_in_process[0x00001];/* the DIMMs calibration stage 0 is in process */\r
- pseudo_bit_t calib1_in_process[0x00001];/* the DIMMs calibration stage 1 is in process */\r
- pseudo_bit_t reserved0[0x00008];\r
- pseudo_bit_t dimms_stop[0x00004]; /* the stopped dimms map, for NSB read/write transaction.\r
- check dimm /calibration/SR/AR may be performed.\r
- */\r
- pseudo_bit_t reserved1[0x0000c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t dimms_idle[0x00004]; /* the idimms parser machine are idle */\r
- pseudo_bit_t sch_idle[0x00001]; /* scheduler is idle */\r
- pseudo_bit_t rx_cmd_empty0[0x00001];/* dmu rx commad fifo in port 0 is empty */\r
- pseudo_bit_t rx_data_empty0[0x00001];/* dmu rx data fifo in port 0 is empty */\r
- pseudo_bit_t rx_cmd_empty1[0x00001];/* dmu rx commad fifo in port 1 is empty */\r
- pseudo_bit_t rx_data_empty1[0x00001];/* dmu rx data fifo in port 1 is empty */\r
- pseudo_bit_t rmwfifo_empty[0x00001];/* dmu rmw fifo is empty */\r
- pseudo_bit_t reqinfly_empty[0x00001];/* dmu requests in fly fifo is empty */\r
- pseudo_bit_t reserved2[0x00015];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00040];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Rx External Domain Configuration Register */\r
-\r
-struct DMURXCONFIGEXT_st { /* Little Endian */\r
- pseudo_bit_t resp_cred[0x00004]; /* Credits for responses to requests arriving to this port */\r
- pseudo_bit_t port_quota[0x00008]; /* wieght of this port (for the wighted round robin scheduling) */\r
- pseudo_bit_t pwr_mng_rate[0x00008]; /* Gap between commands sent for execution in the DIMM. For power reduction. */\r
- pseudo_bit_t Ap_mode[0x00002]; /* Auto precharge mode:\r
- 00 - No auto precharge\r
- 01 - Auto precharge per transaction\r
- 10 - Auto precharge per cell\r
- 11 - reserved */\r
- pseudo_bit_t trgid[0x00003]; /* the NSB id connected to this port\r
- */\r
- pseudo_bit_t reserved0[0x00007];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* DMUstatistical counters */\r
-\r
-struct DMUSTATISTIC_st { /* Little Endian */\r
- struct statistics_openpages_st open_pages_statistics;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00060];\r
-/* --------------------------------------------------------- */\r
- struct DIMMStatistics_st dimm0statistics;\r
-/* --------------------------------------------------------- */\r
- struct DIMMStatistics_st dimm1statistics;\r
-/* --------------------------------------------------------- */\r
- struct DIMMStatistics_st dimm2statistics;\r
-/* --------------------------------------------------------- */\r
- struct DIMMStatistics_st dimm3statistics;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00580];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* DMU External Interface General Configuration Registers */\r
-\r
-struct DMUGENERALEXT_st { /* Little Endian */\r
- pseudo_bit_t Burst_mode[0x00001]; /* in this mode, full write cache line transaction, toward the dimm, are performed. */\r
- pseudo_bit_t AR_disable[0x00001]; /* Auto refresh:\r
- 1 - disable\r
- 0 - enable */\r
- pseudo_bit_t errors_injection[0x00002];/* 00 - disable\r
- 01 - flip one bit\r
- 11 - flip two bits\r
- 10 - reserved */\r
- pseudo_bit_t nop_default[0x00001]; /* when this field is high , the command that the DMU drives\r
- toward the DIMMs is NOP , otherwise it is DESELECT */\r
- pseudo_bit_t sr_shutclk_en[0x00001];/* in Self refrsh process, shut off the DIMMs clocks */\r
- pseudo_bit_t shut_clk_high[0x00001];/* When shuting the clock it high - default shut clock to zero */\r
- pseudo_bit_t dynamic_pd_en[0x00001];/* Enable the dynamic power down mode. */\r
- pseudo_bit_t Command_gap[0x00008]; /* idle gap, in dram clock, between any command toward the DIMMs */\r
- pseudo_bit_t reserved0[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t dimm_cl[0x00003]; /* Dimms Cas Latency - it the same paramters dor all the imms\r
- 0 - 1.5 clock\r
- 1 - 2 clocks\r
- 2 - 2.5 clocks\r
- 3 - 3 clocks\r
- 4 - 3.5 clocks */\r
- pseudo_bit_t dimm_reg[0x00001]; /* the dimms are registers or unbuffered */\r
- pseudo_bit_t di_mode[0x00002]; /* 0 - no di\r
- 1 - parity\r
- 2 - ecc without correction\r
- 3 - ecc with correction */\r
- pseudo_bit_t di_report[0x00002]; /* 00 - dont report\r
- 01 - report only muti+ parity error\r
- 10 -report all errors */\r
- pseudo_bit_t rdi_report[0x00002]; /* the same as di_report but to rmw transactions\r
- */\r
- pseudo_bit_t di_ignore[0x00001]; /* ignore di errors */\r
- pseudo_bit_t rdi_ignore[0x00001]; /* ignore di errors on rmw transactions */\r
- pseudo_bit_t reserved1[0x00014];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Tar[0x00010]; /* Auto Refresh Period in dram clock */\r
- pseudo_bit_t Tcke[0x00010]; /* Power Up interval before activating the CKE in the initiation phase, in dram clocks. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Tdll[0x0000c]; /* idle period until the DIMM DLL is synchronized after the initiation phase, in dram clocks. */\r
- pseudo_bit_t pll_bypass_xor_mode[0x00001];/* In dmu pll bypass mode:\r
- When this register is 1, the clock is a xor of two pins\r
- When this register is 0, the pll bypass works in the regular manner */\r
- pseudo_bit_t gp_iocfg[0x00003]; /* reserved\r
- was: idle period for self refresh exit unit non read command, in dram clocks */\r
- pseudo_bit_t Txsrd[0x00008]; /* idle period for self refresh exit unit read command, in dram clocks */\r
- pseudo_bit_t Tpre_ar[0x00004]; /* hold period before performing Auto Refresh command, in dram clocks */\r
- pseudo_bit_t Tpre_sr[0x00004]; /* hold period before performing Self Refresh command, in dram clocks */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sr_pre_shut_clk[0x00008];/* The period between self refresh and clocks shut down */\r
- pseudo_bit_t sr_post_shut_clk[0x00008];/* period between clocks reactivation and CLK reactivation */\r
- pseudo_bit_t sr_interval[0x00008]; /* The time interval between assertion of self refresh command on port A and port B */\r
- pseudo_bit_t sr_duration[0x00008]; /* The minimum duration in self refresh state */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sr_pre_shut_rst[0x00008];/* the period in clocks between asserting the SR command and activate the DIMM MRST_ in case of registered DIMM + shut the clocks, after activated the MRST the DMU wait for "sr_pre_shut_clk" then shuting of the clocks */\r
- pseudo_bit_t sr_post_shut_rst[0x00008];/* this period in existing from self refresh , after activating the clocks the DMU still activating the MRST for "sr_post_shut_rst" then it deactivating the MRST and asserting XSR command.\r
- (this issue is related to registered DIMM with shuting the clocks is enabled). */\r
- pseudo_bit_t reserved2[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t prs_starv_lim[0x00008];\r
- pseudo_bit_t reserved3[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x003a0];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* DIMM Bar and Mask registers */\r
-\r
-struct DIMMBarMask_st { /* Little Endian */\r
- pseudo_bit_t dimm_en[0x00001]; /* 1=Enabled\r
- 0=Disabled (DIMM not present) */\r
- pseudo_bit_t reserved0[0x00013];\r
- pseudo_bit_t bar_lsb[0x0000c]; /* lsb bits of the bar */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bar_msb[0x00020]; /* msb bits of the bar */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00014];\r
- pseudo_bit_t mask_lsb[0x0000c]; /* lsb bits of the mask */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t mask_msb[0x00020]; /* msb bits of the mask */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* DMU Debug Internal Domain */\r
-\r
-struct DMUDEBUGINT_st { /* Little Endian */\r
- pseudo_bit_t crslavet_err[0x00001]; /* crslcave macro timeout error */\r
- pseudo_bit_t tx_cmdfifo_perr[0x00001];/* the data parity happened on the tx command fifo */\r
- pseudo_bit_t tx_datafifo_perr[0x00001];/* the data parity happened on the tx command fifo */\r
- pseudo_bit_t errorfifo_perr[0x00001];/* the data parity happened on the error fifo */\r
- pseudo_bit_t tx_cmdfifo_underrun[0x00001];/* the underrun indecation in tx command fifo */\r
- pseudo_bit_t tx_datafifo_underrun[0x00001];/* the underrun indecation in tx data fifo */\r
- pseudo_bit_t error_fifo_underrun[0x00001];/* the underrun indecation in error fifo */\r
- pseudo_bit_t rx_pdatafifo_overflow0[0x00001];/* overflow indecation of posted data fifo in NSB RX port 0 */\r
- pseudo_bit_t rx_pcmdfifo_overflow0[0x00001];/* overflow indecation of posted command fifo in NSB RX port 0 */\r
- pseudo_bit_t tx_npdatafifo_overflow0[0x00001];/* overflow indecation of non- posted datafifo in NSB RX port 0 */\r
- pseudo_bit_t tx_npcmdfifo_overflow0[0x00001];/* overflow indecation of non - posted command fifo in NSB RX port 0 */\r
- pseudo_bit_t tx_pdatafifo_overflow1[0x00001];/* overflow indecation of posted data fifo in NSB RX port 1 */\r
- pseudo_bit_t tx_pcmdfifo_overflow1[0x00001];/* overflow indecation of posted command fifo in NSB RX port 1 */\r
- pseudo_bit_t tx_npdatafifo_overflow1[0x00001];/* overflow indecation of non posted data fifo in NSB RX port 1 */\r
- pseudo_bit_t tx_npcmdfifo_overflow1[0x00001];/* overflow indecation of non - posted command fifo in NSB RX port 1 */\r
- pseudo_bit_t str_add_nohit0[0x00001];/* NSB error port 0 : transaction started address had no hit in any defined dimm address segments */\r
- pseudo_bit_t str_add_multhit0[0x00001];/* NSB error port 0 : transaction started address had multi hit in the defined dimm address segments */\r
- pseudo_bit_t end_add_nohit0[0x00001];/* NSB error port 0 : transaction ending address had no hit in any defined dimm address segments */\r
- pseudo_bit_t end_add_multhit0[0x00001];/* NSB error port 0 : transaction ending address had multi hit in the defined dimm address segments */\r
- pseudo_bit_t out_of_range0[0x00001];/* NSB error port 0 : transaction starting & ending address has hit to differnat segments */\r
- pseudo_bit_t str_add_nohit1[0x00001];/* NSB error port 0 : transaction started address had no hit in any defined dimm address segments */\r
- pseudo_bit_t str_add_multhit1[0x00001];/* NSB error port 1 : transaction started address had multi hit in the defined dimm address segments */\r
- pseudo_bit_t end_add_nohit1[0x00001];/* NSB error port 1 : transaction ending address had no hit in any defined dimm address segments */\r
- pseudo_bit_t end_add_multhit1[0x00001];/* NSB error port 1 : transaction ending address had multi hit in the defined dimm address segments */\r
- pseudo_bit_t out_of_range1[0x00001];/* NSB error port 1 : transaction starting & ending address has hit to differnat segments */\r
- pseudo_bit_t nsb_page_violation0[0x00001];\r
- pseudo_bit_t nsb_page_violation1[0x00001];\r
- pseudo_bit_t reserved0[0x00005];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00060];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* DMU Errors FIFO */\r
-\r
-struct DMUERRORFIFO_st { /* Little Endian */\r
- struct FIFOCONTROL_st dmuerrorfifoctl;/* This fifo control gateway is responsible of the DRAMS data integrity errors reporting fifo. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cause_lsb[0x00003]; /* data integrty error in cause:\r
- (error in the 64bit lsb data, on the rise edge of the clock)\r
- cause[0] - single ECC error\r
- cause[1] - multiple ECC error\r
- cause[2] - parity error */\r
- pseudo_bit_t MSBcause[0x00003]; /* data integrty error cause:\r
- (error in the 64bit msb data, on the fall edge of the clock)\r
- cause[0] - single ECC error\r
- cause[1] - multiple ECC error\r
- cause[2] - parity error\r
- */\r
- pseudo_bit_t err_RMW[0x00001]; /* Data integrity error on Read data, and this Read command is performed due to RMW transaction */\r
- pseudo_bit_t err_src_id[0x00003]; /* NSB Unit source of the transaction */\r
- pseudo_bit_t err_da[0x00002]; /* Error DIMM address.\r
- */\r
- pseudo_bit_t err_ba[0x00002]; /* Error bank address */\r
- pseudo_bit_t reserved0[0x00012];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t err_ra[0x00010]; /* Error row address */\r
- pseudo_bit_t err_ca[0x00010]; /* Error column address */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Rx Internal Domain Configuration Register */\r
-\r
-struct DMURXCONFIGINT_st { /* Little Endian */\r
- pseudo_bit_t cred_rel_mode[0x00002];/* Credit release mode:\r
- 00 - Release credit when cell service begin\r
- (for better performance)\r
- 01 - Release credit when cell service end\r
- 1x - Reserved */\r
- pseudo_bit_t rx_stop[0x00001]; /* When asserted, posted/non poseted credit release by the port is disabled\r
- */\r
- pseudo_bit_t reserved0[0x0001d];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Cause Registers */\r
-\r
-struct DMU_CAUSEREG_st { /* Little Endian */\r
- pseudo_bit_t error_fifo_not_empty[0x00001];/* Data Integrity Fifo is not empty. */\r
- pseudo_bit_t error_fifo_overflow[0x00001];/* Data Integrity Fifo had overflow. */\r
- pseudo_bit_t calibration_drift[0x00001];/* Calibration drift indecation. */\r
- pseudo_bit_t NSB_Rx_port0[0x00001]; /* NSB Rx port 0 error. */\r
- pseudo_bit_t NSB_Rx_port1[0x00001]; /* NSB Rx port 1 error. */\r
- pseudo_bit_t cr_slave_macro_error[0x00001];/* Crslave macro error. */\r
- pseudo_bit_t reserved0[0x0001a];\r
-/* --------------------------------------------------------- */\r
- struct EXT_CAUSEREG_st extended_cause;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @DMU_BIST */\r
-\r
-struct DMU_BIST_st { /* Little Endian */\r
- pseudo_bit_t bists_stat[0x00009];\r
- pseudo_bit_t reserved0[0x00017];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nonrep_arrays_stat[0x00012];\r
- pseudo_bit_t reserved1[0x0000e];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00040];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* DMU Internal Interface General Configuration Registers */\r
-\r
-struct DMUGENERALINT_st { /* Little Endian */\r
- pseudo_bit_t nsb_id[0x00003]; /* This field describes the DMU NSB ID - 1 */\r
- pseudo_bit_t rx_order_mode[0x00002];/* NSB RX Ports ordering policy (per transactions):\r
- 00 - Address hit order\r
- 01 - Global order\r
- 10 - no order\r
- 11 reserved */\r
- pseudo_bit_t reserved0[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bar_num[0x00001]; /* Number of bars used to map the DIMMs memory */\r
- pseudo_bit_t bars_type[0x00002]; /* type of teh bars used to map the DIMMs memory. The lsb bit is related to the first bar. If single bar exist (bar_num=0), the msb bit of this register is not valid.\r
- 0 - prefetchable\r
- 1 - non-prefetchable */\r
- pseudo_bit_t reserved1[0x00005];\r
- pseudo_bit_t nsb_page_size[0x00004];/* page_size encoding\r
- 0000 - reserved\r
- 0001 - reserved\r
- 0010 - 4K (default)\r
- 0011 - 8K\r
- 0100 - 16K\r
- 0101 - 32K\r
- 0110 - 64K\r
- Others - reserved\r
- */\r
- pseudo_bit_t reserved2[0x00014];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t dqsm_single_buf[0x00001];/* 0 - use double buffer for the I/O\r
- 1- use single buffer for the I/O\r
- Note that in test mode, double buffer is used */\r
- pseudo_bit_t addra_single_buf[0x00001];/* 0 - use double buffer for the I/O\r
- 1- use single buffer for the I/O\r
- Note that in test mode, double buffer is used */\r
- pseudo_bit_t addrb_single_buf[0x00001];/* 0 - use double buffer for the I/O\r
- 1- use single buffer for the I/O\r
- Note that in test mode, double buffer is used */\r
- pseudo_bit_t cmda_single_buf[0x00001];/* 0 - use double buffer for the I/O\r
- 1- use single buffer for the I/O\r
- Note that in test mode, double buffer is used */\r
- pseudo_bit_t cmdb_single_buf[0x00001];/* 0 - use double buffer for the I/O\r
- 1- use single buffer for the I/O\r
- Note that in test mode, double buffer is used */\r
- pseudo_bit_t clkouta_single_buf[0x00001];/* 0 - use double buffer for the I/O\r
- 1- use single buffer for the I/O\r
- Note that in test mode, double buffer is used */\r
- pseudo_bit_t clkoutb_single_buf[0x00001];/* 0 - use double buffer for the I/O\r
- 1- use single buffer for the I/O\r
- Note that in test mode, double buffer is used */\r
- pseudo_bit_t cs_single_buf[0x00001];/* 0 - use double buffer for the I/O\r
- 1- use single buffer for the I/O\r
- Note that in test mode, double buffer is used */\r
- pseudo_bit_t reserved3[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x000a0];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rxdb_idle[0x00001]; /* the dmu rx data base is idle (no transaction in the dmu rx ports) */\r
- pseudo_bit_t tx_cmd_empty[0x00001]; /* dmu tx commad fifo is empty. */\r
- pseudo_bit_t tx_data_empty[0x00001];/* tx data fifo is empty */\r
- pseudo_bit_t reserved5[0x0001d];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t dmu_dqs_drift[0x00012];/* DQS calibration machine early 'out of sync' alarm per nibble. */\r
- pseudo_bit_t reserved6[0x0000e];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x00340];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @PCU_BIST */\r
-\r
-struct PCU_BIST_st { /* Little Endian */\r
- pseudo_bit_t bists_stat[0x0000e];\r
- pseudo_bit_t reserved0[0x00012];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nonrep_arrays_stat[0x0001d];\r
- pseudo_bit_t reserved1[0x00003];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x000c0];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* PCU General Configuration - Internal Domain */\r
-\r
-struct PCUGENERALINT_st { /* Little Endian */\r
- pseudo_bit_t i1_ntu_id[0x00003];\r
- pseudo_bit_t i1_pcu_id[0x00003];\r
- pseudo_bit_t i1_hca_id[0x00003];\r
- pseudo_bit_t i1_dmu_id[0x00003];\r
- pseudo_bit_t reserved0[0x00014];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t i1pcf_gp_cfg[0x00020]; /* general purpose cfg i1 registers */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00040];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* monitoring internal state for debug */\r
-\r
-struct pcu_monitor_st { /* Little Endian */\r
- pseudo_bit_t pcu_monitor0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pcu_monitor1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pcu_monitor2[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pcu_monitor3[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pcu_monitor4[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pcu_monitor5[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pcu_monitor6[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* PCU init register */\r
-\r
-struct pcu_init_st { /* Little Endian */\r
- pseudo_bit_t sw_req64[0x00001]; /* When sw_req64_en set, the value in sw_req64 register overrides the sampled value. */\r
- pseudo_bit_t sw_req64_en[0x00001]; /* When set, the value in sw_req64 register overrides the sampled value. */\r
- pseudo_bit_t reserved0[0x00006];\r
- pseudo_bit_t sampled_req64[0x00001];/* The sampled value for req64 */\r
- pseudo_bit_t bit64_supported[0x00001];/* When set, 64 bit mode is supported. This is the result of sw_req64, sw_req64_en and sampled_req64 */\r
- pseudo_bit_t reserved1[0x00016];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sw_pcix_mode[0x00001]; /* When sw_pcix_mode_en set, the value in sw_pcix_mode register overrides the sampled value. */\r
- pseudo_bit_t sw_pcix_mode_en[0x00001];/* When sw_pcix_mode_en set, the value in sw_pcix_mode register overrides the sampled value. */\r
- pseudo_bit_t reserved2[0x00006];\r
- pseudo_bit_t sampled_pcix_mode[0x00001];/* sampled value of pcix mode */\r
- pseudo_bit_t pcix_en[0x00001]; /* When set, pcix mode is enabled. This is the result of sw_pcix_mode, sw_pcix_mode_en and sampled_pcix_mode */\r
- pseudo_bit_t reserved3[0x00016];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t init_pattern_drive_en[0x00001];/* When this bit is set, init pattern is being drived by the Tavor when RST# is asserted (by Tavor) */\r
- pseudo_bit_t init_pattern[0x00003]; /* init pattern to drive when init_pattern_drive_en is set.\r
- 1 - devsel_\r
- 2 - stop_\r
- 3 - trdy_ */\r
- pseudo_bit_t reserved4[0x00004];\r
- pseudo_bit_t gpio15_ctrl[0x00003]; /* 0 - gpio15 ctrl en\r
- 1 - gpio15 value to drive\r
- 2 - gpio15 oe to drive\r
- This register is used to drive the pci bus reset when in */\r
- pseudo_bit_t reserved5[0x00005];\r
- pseudo_bit_t init_req64_drive_en[0x00001];/* enable to drive req64 at reset */\r
- pseudo_bit_t init_req64[0x00001]; /* req64 to drive at reset if req64_drive_en is set */\r
- pseudo_bit_t reserved6[0x0000e];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t sw_ignore_idsel[0x00001];/* When sw_ignore_idsel_en set, the value in sw_ignore_idsel register overrides the sampled value. */\r
- pseudo_bit_t sw_ignore_idsel_en[0x00001];/* When sw_ignore_idsel_en set, the value in sw_ignore_idsel register overrides the sampled value. */\r
- pseudo_bit_t reserved7[0x00006];\r
- pseudo_bit_t sampled_ignore_idsel[0x00001];/* ignore_idsel calculated from the strapping options */\r
- pseudo_bit_t ignore_idsel[0x00001]; /* the resulting ignore_idsel */\r
- pseudo_bit_t reserved8[0x00016];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* error logging */\r
-\r
-struct pcu_err_log_st { /* Little Endian */\r
- pseudo_bit_t ptu_err_log0[0x00020]; /* Address caused the error [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ptu_err_log1[0x00020]; /* Address caused the error [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ptu_err_log2[0x00020]; /* [24] PTU write pointer\r
- [23:16] Error counter\r
- [15:0] Cause vector for the error */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ptu_err_log3[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pmu_err_log0[0x00020]; /* Address of the error transaction [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pmu_err_log1[0x00020]; /* Address of the transaction caused error [63:32]\r
- see bug 5205 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pmu_err_log2[0x00020]; /* [24] PMU write pointer\r
- [23:16] Error counter\r
- [4:0] Cause vector for the error */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pmu_err_log3[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* PCU Configuration Cycles Register */\r
-\r
-struct PCUCONFIGCYCLES_st { /* Little Endian */\r
- pseudo_bit_t cmd[0x00001]; /* cfg command - read (0) or write (1) */\r
- pseudo_bit_t reserved0[0x00007];\r
- pseudo_bit_t byte_enables[0x00004]; /* Byte enables of configuration command */\r
- pseudo_bit_t fw_done[0x00001]; /* Indication that the FW execute the configuration cycle. In case of PCI read - the read data is in the cfg_data register. In case of PCI write, the data have been written to the appropriate configuration register. In the case of PCIX, the required information for the generation of split completion have been captured by the FW.\r
- */\r
- pseudo_bit_t trans_nack[0x00001]; /* trans_nack shows the result of configuration transaction.\r
- 0 - ACK\r
- 1 - NACK (implies that the FW failed to execute the cycle and target abort will be executed by HW)\r
- This bit is set by FW and cleared by HW after it finishes to process the current transaction. This bit should be valid during fw_done. */\r
- pseudo_bit_t reserved1[0x00001];\r
- pseudo_bit_t pcix[0x00001]; /* PCIX mode. In this mode the requested data at read commands and the write acknoledgement on write commands should be returned to PCI bus as split completion via PCUSWCYCLES port. */\r
- pseudo_bit_t reserved2[0x0000a];\r
- pseudo_bit_t discard[0x00001]; /* Discard pending delayed transaction (write only)\r
-\r
- This bit is used to implement firmware Discard Timer, firmware should set this bit, in order to discard pending delayed transaction (PCI). When setting this bit, fw_done and trans_nak should be zero.\r
- This bit is also used to discard incoming transation with parity error (PCI). In this case firmware should write discard=1 with fw_done=1 and trans_nak=0\r
- */\r
- pseudo_bit_t reserved3[0x00001];\r
- pseudo_bit_t pe[0x00001]; /* Recieved Parity Error. This bit is set by HW during the capture of the cfg cycle. If asserted, In PCIX mode FW should send Split Completion Message with SCE, class 2, index 01h.\r
- */\r
- pseudo_bit_t service_required[0x00001];/* Indication that config cycle have been captured and require service.\r
- In PCIX this bit is cleard when fw_done is set.\r
- In PCI, this bit is cleared when pending delayed transaction has been completed OR firmware requested discard (Discard Timer) */\r
- pseudo_bit_t reserved4[0x00001];\r
- pseudo_bit_t lock[0x00001]; /* HW sets this bit to 1 after every reading of PCUCONFIGCYCLES register 00h. At writes it just stores the input. FW usually uses this bit as test&set semaphore in the case of multiagent work.\r
- HW does not use this bit internally. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_address[0x00020]; /* Address of cfg command. Contains configuration type (1:0),\r
- register number (7:2), function number (10:8). For configuration type 1 it also contains device number (15:11) and bus number (23:16). Bits 31:24 are reserved. */\r
-/* --------------------------------------------------------- */\r
- struct cfg_attributes_st cfg_attributes;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cfg_data[0x00020]; /* At configuration write command, this is the data latched from AD bus during the data phase. It is valid starting assertion of\r
- a cause bit "Configuration Cycle command has arrived" (CAUSEREG) until fw_done (bit 12).\r
- At the configuration read command of PCI (NOT PCIX), the requested data should be written here. It will be transferred to PCI bus.\r
- In the case of PCIX (bit 8 of PCUCONFIGCYCLES register 00h): The data should be returned as split completion via PCUSWCYCLES port. Register 04h contains requestor's attributes for the split completion.\r
- */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Software Generation of PCI Cycles */\r
-\r
-struct PCUSWCYCLES_st { /* Little Endian */\r
- pseudo_bit_t r_w[0x00001]; /* 0=read\r
- 1=write, split completion\r
- */\r
- pseudo_bit_t io[0x00001]; /* 0=memory / 1=io\r
- This bit should be asserted (io) in mutual exclusion with cfg sc and special bits. Bit rw defines, if Memory/IO Read or Memory/IO Write command will be issued to PCI bus. Will a memory command be burst or DWORD transaction depends from bytecount. */\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t sc[0x00001]; /* Split Completion transaction command.\r
- This bit should be asserted in mutual exclusion with cfg, mem_io, special. r_w must be 1\r
- */\r
- pseudo_bit_t reserved1[0x00001];\r
- pseudo_bit_t special[0x00001]; /* Special Cycle or Interrupt Acknowledge transaction command.\r
- This bit should be asserted in mutual exclusion with cfg, sc and mem_io bits.\r
- rw=0: Interrupt Acknowledge\r
- rw=1: Special Cycle */\r
- pseudo_bit_t cfg[0x00001]; /* Configuration transaction command.\r
- This bit should be asserted in mutual exclusion with sc, mem_io and special bits. Bit rw defines, if Configuration Read or Configuration Write command will be issued to PCI bus. */\r
- pseudo_bit_t persist[0x00001]; /* When this bit is asserted, the PCU master is dedicated for this transaction and no other transactions will interleave its execution until its completion (deassertion of the GO bit). */\r
- pseudo_bit_t be[0x00004]; /* Byte Enables (BE) - active low.\r
- BE can be used for I/O, configuration and INTA cycles.\r
- For memory cycles with BE!=0, it is possible only to use BE for single data phase transactions.\r
- * Non 4 bytes aligned I/O READ cycles can not be generated in PCIX. see bug 5138 */\r
- pseudo_bit_t reserved2[0x00003];\r
- pseudo_bit_t pcix[0x00001]; /* pcix mode */\r
- pseudo_bit_t MaxRetry[0x00008]; /* The maximum number of retry responses to this transaction before the cycle is considered as completed by this mechanism. */\r
- pseudo_bit_t status[0x00006]; /* Transaction completion status\r
- 000000 - Normal completion\r
- 000001 - Retry Timeout\r
- 000010 - Split Completion Timeout\r
- 000011 - Unexpected Split Completion received (Correct Sequence ID, but bytecount or address[6:0] mismatch)\r
- 000100 - Split Completion Error received (SCM with SCE)\r
- 001000 - Target Abort\r
- 010000 - Master Abort\r
- 100000 - Parity Error\r
- others - reserved */\r
- pseudo_bit_t GO[0x00001]; /* This bit is used to trigger the transaction and to report its completion */\r
- pseudo_bit_t lock[0x00001];\r
-/* --------------------------------------------------------- */\r
- struct swcycle_internal_st sw_int_status;/* Reserved for Monitoring and debug use */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pci_address_lsb5_0[0x00006];/* This field contains 6 lowest bits of the address to be driven to the PCI bus during the address phase\r
- * Non 4 bytes aligned I/O READ cycles can not be generated in PCIX. see bug 5138 */\r
- pseudo_bit_t pci_address_lsb31_6[0x0001a];/* This field contains bits [31:7] of the address to be driven to the PCI bus during the address phase */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pci_address_msb[0x00020];/* This field contains the 32 msb bits of the address to be driven to the PCI bus during the address phase */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t attributes6_0[0x00007];/* This field contains lowest 7 bits of the attribute to be driven to the PCIX bus during the attribute phase. Ignored in PCI mode */\r
- pseudo_bit_t attributes31_7[0x00019];/* This field contains bits[31:7] of the attribute to be driven to the PCIX bus during the attribute phase. Ignored in PCI mode. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00160];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pci_data0[0x00020]; /* In write transactions - the data to be driven to the pci bus during the write phase.\r
- In read transaction, this is the location to store the read data. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pci_data1[0x00020]; /* In write transactions - the data to be driven to the pci bus during the write phase.\r
- In read transaction, this is the location to store the read data. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pci_data2[0x00020]; /* In write transactions - the data to be driven to the pci bus during the write phase.\r
- In read transaction, this is the location to store the read data. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pci_data3[0x00020]; /* In write transactions - the data to be driven to the pci bus during the write phase.\r
- In read transaction, this is the location to store the read data. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pci_data4[0x00020]; /* In write transactions - the data to be driven to the pci bus during the write phase.\r
- In read transaction, this is the location to store the read data. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pci_data5[0x00020]; /* In write transactions - the data to be driven to the pci bus during the write phase.\r
- In read transaction, this is the location to store the read data. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pci_data6[0x00020]; /* In write transactions - the data to be driven to the pci bus during the write phase.\r
- In read transaction, this is the location to store the read data. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pci_data7[0x00020]; /* In write transactions - the data to be driven to the pci bus during the write phase.\r
- In read transaction, this is the location to store the read data. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pci_data8[0x00020]; /* In write transactions - the data to be driven to the pci bus during the write phase.\r
- In read transaction, this is the location to store the read data. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pci_data9[0x00020]; /* In write transactions - the data to be driven to the pci bus during the write phase.\r
- In read transaction, this is the location to store the read data. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pci_data10[0x00020]; /* In write transactions - the data to be driven to the pci bus during the write phase.\r
- In read transaction, this is the location to store the read data. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pci_data11[0x00020]; /* In write transactions - the data to be driven to the pci bus during the write phase.\r
- In read transaction, this is the location to store the read data. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pci_data12[0x00020]; /* In write transactions - the data to be driven to the pci bus during the write phase.\r
- In read transaction, this is the location to store the read data. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pci_data13[0x00020]; /* In write transactions - the data to be driven to the pci bus during the write phase.\r
- In read transaction, this is the location to store the read data. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pci_data14[0x00020]; /* In write transactions - the data to be driven to the pci bus during the write phase.\r
- In read transaction, this is the location to store the read data. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pci_data15[0x00020]; /* In write transactions - the data to be driven to the pci bus during the write phase.\r
- In read transaction, this is the location to store the read data. */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Fence Command Directed to iRISC */\r
-\r
-struct cmd_out_st { /* Little Endian */\r
- pseudo_bit_t r_w[0x00001];\r
- pseudo_bit_t mem_io[0x00001];\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t split[0x00001];\r
- pseudo_bit_t reserved1[0x00001];\r
- pseudo_bit_t inta[0x00001];\r
- pseudo_bit_t cfg[0x00001];\r
- pseudo_bit_t reserved2[0x00017];\r
- pseudo_bit_t go[0x00001];\r
- pseudo_bit_t lock[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pci_address_lsb[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pci_address_msb[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t byte_cnt[0x00007];\r
- pseudo_bit_t reserved3[0x00011];\r
- pseudo_bit_t tag[0x00005];\r
- pseudo_bit_t relexed_order[0x00001];\r
- pseudo_bit_t no_snoop[0x00001];\r
- pseudo_bit_t reserved4[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t online_stat[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00160];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Data0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Data1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Data2[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Data3[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Data4[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Data5[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Data6[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Data7[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Data8[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Data9[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Data10[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Data11[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Data12[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Data13[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Data14[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Data15[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* NSwitch Address Decoder Registers */\r
-\r
-struct Nswitch_address_deocder_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x0000c];\r
- pseudo_bit_t io_base_pcu[0x00014];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x0000c];\r
- pseudo_bit_t io_limt_pcu[0x00014];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00014];\r
- pseudo_bit_t mem_base_pcu[0x0000c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00014];\r
- pseudo_bit_t mem_limt_pcu[0x0000c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t preftch_mem_base_pcu_msbs[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00014];\r
- pseudo_bit_t preftch_mem_base_pcu_lsbs[0x0000c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t preftch_mem_limt_pcu_msbs[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00014];\r
- pseudo_bit_t preftch_mem_limt_pcu_lsbs[0x0000c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ns_is_primary4pcu[0x00001];/* nswitch_is_primary4pcu */\r
- pseudo_bit_t subtractive_dec_pcu_on_pci[0x00001];\r
- pseudo_bit_t subtractive_dec_pcu_on_nsb[0x00001];\r
- pseudo_bit_t isa_mode4pcu[0x00001];\r
- pseudo_bit_t reserved6[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x000e0];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x0000c];\r
- pseudo_bit_t io_base_ntu[0x00014];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved9[0x0000c];\r
- pseudo_bit_t io_limt_ntu[0x00014];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved10[0x00014];\r
- pseudo_bit_t mem_base_ntu[0x0000c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved11[0x00014];\r
- pseudo_bit_t mem_limt_ntu[0x0000c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t preftch_mem_base_ntu_msbs[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved12[0x00014];\r
- pseudo_bit_t preftch_mem_base_ntu_lsbs[0x0000c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t preftch_mem_limt_ntu_msbs[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved13[0x00014];\r
- pseudo_bit_t preftch_mem_limt_ntu_lsbs[0x0000c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ns_is_primary4ntu[0x00001];\r
- pseudo_bit_t reserved14[0x00001];\r
- pseudo_bit_t substractive_dec_ntu[0x00001];\r
- pseudo_bit_t isa_mode4ntu[0x00001];\r
- pseudo_bit_t reserved15[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved16[0x000e0];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntu_bar_0_msbs[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ntu_bar_size_0[0x00006];\r
- pseudo_bit_t reserved17[0x00002];\r
- pseudo_bit_t enable_ntu_0[0x00001];\r
- pseudo_bit_t reserved18[0x0000b];\r
- pseudo_bit_t ntu_bar_0_lsbs[0x0000c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved19[0x001c0];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t hca_bar_0_msbs[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t hca_bar_size_0[0x00006];\r
- pseudo_bit_t reserved20[0x00002];\r
- pseudo_bit_t enable_hca_0[0x00001];\r
- pseudo_bit_t reserved21[0x0000b];\r
- pseudo_bit_t hca_bar_0_lsbs[0x0000c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved22[0x00040];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t hca_bar_1_msbs[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t hca_bar_size_1[0x00006];\r
- pseudo_bit_t reserved23[0x00002];\r
- pseudo_bit_t enable_hca_1[0x00001];\r
- pseudo_bit_t reserved24[0x0000b];\r
- pseudo_bit_t hca_bar_1_lsbs[0x0000c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved25[0x00140];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t dmu_bar_0_msbs[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t dmu_bar_size_0[0x00006];\r
- pseudo_bit_t reserved26[0x00002];\r
- pseudo_bit_t enable_dmu_0[0x00001];\r
- pseudo_bit_t reserved27[0x0000b];\r
- pseudo_bit_t dmu_bar_0_lsbs[0x0000c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved28[0x00040];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t dmu_bar_1_msbs[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t dmu_bar_size_1[0x00006];\r
- pseudo_bit_t reserved29[0x00002];\r
- pseudo_bit_t enable_dmu_1[0x00001];\r
- pseudo_bit_t reserved30[0x0000b];\r
- pseudo_bit_t dmu_bar_1_lsbs[0x0000c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved31[0x00740];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @pci registers */\r
-\r
-struct conf_header_registers_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t io_space[0x00001]; /* Enable for IO decoders. When 0, the device do not respond to IO transactions. From the Command Register (p2p page 27, pcix spec page 131) */\r
- pseudo_bit_t mem_space[0x00001]; /* Enable for memory decoders. When 0, the device do not respond to memory transactions.From the Command Register */\r
- pseudo_bit_t reserved1[0x00002];\r
- pseudo_bit_t mri_en[0x00001]; /* memory write and invalidate enable. Relevant for PCI mode.\r
- Ignored in PCIX mode.From the Command Register */\r
- pseudo_bit_t P_perr_en[0x00001]; /* When set to one, the device can report parity errors through PERR#. From the Command Register */\r
- pseudo_bit_t reserved2[0x00001];\r
- pseudo_bit_t P_serr_en[0x00001]; /* SERR# enable for the primary bus. From the Command Register */\r
- pseudo_bit_t reserved3[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t S_perr_en[0x00001];\r
- pseudo_bit_t S_serr_en[0x00001];\r
- pseudo_bit_t reserved4[0x00003];\r
- pseudo_bit_t master_abort_mode[0x00001];/* Master abort mode\r
- 0 - Master abort on read return all '1. On write, ignored.\r
- 1 - Master abort on one bus cause target abort on the other bus. Master abort on posted write cause SERR\r
- (from the bridge control register) */\r
- pseudo_bit_t reserved5[0x00002];\r
- pseudo_bit_t primary_discard_timeout[0x00004];/* number of PCI clocks that the PCU waits for a master on the primary bus (When in Primary mode) to repeate a delayed transaction. Relevant in PCI only. Ignored in PCIX mode.\r
- (relevant for inbound non-posted)\r
- The number of PCI cycles that we wait for split completion. If expired, appropriate cause bit is set. Encoding:\r
- 0 - 2^6 cycles\r
- 1 - 2^8\r
- 2 - 2^10\r
- 3 - 2^12\r
- 4 - 2^14\r
- 5 - 2^16\r
- 6 - 2^18\r
- 7 - 2^20\r
- 8 - 2^22\r
- 9 - 2^24\r
- 10- 2^26\r
- 11- 2^28\r
- 12- 2^30\r
- else - disable\r
- Reset value is 7 */\r
- pseudo_bit_t reserved6[0x00014];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cls[0x00008]; /* Cache line size. Defined in PCI mode. No meaning in PCIX mode.\r
- In dword increment.\r
- When zero, the master can not use mri command\r
- Tavor supports cls that are larger than ???\r
- */\r
- pseudo_bit_t latency_timer[0x00008];/* latency timer as defined in the pci/x spec.\r
- In Primary mode it is acts as the "primary latency timer" and in Secondary mode as the "secondary latency timer"\r
- If PCIX mode, the default value should be 64. This should be set by FW. */\r
- pseudo_bit_t reserved7[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t p_bus_num[0x00008];\r
- pseudo_bit_t s_bus_number[0x00008];\r
- pseudo_bit_t subord_bus_num[0x00008];\r
- pseudo_bit_t reserved8[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t function_number[0x00003];/* Indicates the number of this function; i.e., the number in the Function Number field (AD[10::08]) of\r
- the address of a Type 0 configuration transaction to which this bridge responds.\r
- This register is from the PCI-X Bridge Status Register.\r
- This register is read only in respect to config ycle and is automatically updated from the type 0 cfg cycles. So is the device number */\r
- pseudo_bit_t device_number[0x00005];/* It indicates the number of this device; i.e., the number in the Device Number field (AD[15::11]) of the address of a Type 0 configuration transaction that is assigned to this bridge\r
- by the connection of the system hardware.\r
- This register is from the PCI-X Bridge Status Register */\r
- pseudo_bit_t reserved9[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t up_splt_commitment_limit[0x00010];\r
- pseudo_bit_t reserved10[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved11[0x00120];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* PCI/X Arbiter Configuration */\r
-\r
-struct pci_arbiter_st { /* Little Endian */\r
- pseudo_bit_t parb_pair_used[0x00007];/* used to select the number of active external agents connected to the arbiter. This bit mask controls the pin usage and overrides any GPIO configuration. See \93PCI Arbiter Pin Usage\94 on page 105. In order to support external PCI agents through the GPIO pins, this register has to be programmed. The default GPIO configuration results in the GPIO pins being inputs right after reset. Therefore, weak pull ups are required on the corresponding pin so that connected PCI agents do not receive a floating GNT after reset is deasserted while the PCI Arb Pair Used has not yet been programmed to its desired value. To ensure a glitch free transition on the GNT pins at the moment the PCI Arb Pair Used is programmed, the GPIO Data register should keep its reset value until the it has been configured.\r
- 1 - corresponding GPIO pair is used for an external agent\92s REQ# and GNT# signals\r
- 0 - GPIO controls the pins and corresponding REQ input to the internal arbiter is masked. See \93PCI Arbiter Pin Usage\94 on page 105.\r
- The reset value is 0 (meaning no GPIO pair is used by the arbiter by default */\r
- pseudo_bit_t reserved0[0x00005];\r
- pseudo_bit_t parb_TimeOut[0x00004]; /* Number of PCI cycles which arbiter will continue to provide Grant to an agent that does not initiate a cycle on an IDLE PCI bus. After TimeOut +2 cycles the arbiter removes grant and continues normal operation. The timed out agent will not be granted the bus until it removes the request for at least one PCI cycle. Reset value is 0xE. */\r
- pseudo_bit_t parb_P[0x00001]; /* Priority for internal agent.\r
- 1 - internal agent is high priority\r
- 0 - internal agent is low priority\r
- Reset value is 1. */\r
- pseudo_bit_t parb_H[0x00004]; /* Number of external high priority agents. Valid values are 0 to 8. Greater than 8 is reserved. Agents 1 to H are high priority agents. Agents H+1 to 8 are low priority agents. Reset value is 0. */\r
- pseudo_bit_t reserved1[0x00006];\r
- pseudo_bit_t parb_park_agt[0x00004];/* Agent to receive the Grant when no requests are active. Note, this field should be configured so an existing connected agent is the parked one. Reset value is 0 (internal agent parked)\r
- park_agt encoding is as follows:\r
- 0000-1001 - agent number\r
- 1010-1110 - reserved\r
- 1111 - park on last\r
- */\r
- pseudo_bit_t parb_en[0x00001]; /* Arbiter Enabled.\r
- 1 - internal PCI Arbiter is enabled. PCI REQ# and GNT# pins are used for connecting external agent 1 to the internal arbiter.\r
- 0 - internal PCI Arbiter is disabled. Internal agent uses PCI REQ# and GNT# pins for connecting to an external arbiter. Reset value for the A bit is controlled using strapping pin. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00060];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* PCU Debug */\r
-\r
-struct pcu_debug_st { /* Little Endian */\r
- pseudo_bit_t out_p_en[0x00001]; /* enable outbound-posted transactions. Default value is 0 as after reset. the PCI defined configuration - bus_master is 0. */\r
- pseudo_bit_t out_np_en[0x00001]; /* enable outbound non-posted transactions. Default value is 0 as after reset. the PCI defined configuration - bus_master is 0. */\r
- pseudo_bit_t in_p_en[0x00001]; /* enable inbound-posted transactions */\r
- pseudo_bit_t out_np_burst_en[0x00001];/* When 0, np write burst is disabled. The np write would be dispersed into dword transactions */\r
- pseudo_bit_t in_read_np_engine_en[0x00004];/* enable working of the inbound non-posted engine (for read). a bit for each engine\r
- 0 - engine disabled\r
- 1 - engine enabled */\r
- pseudo_bit_t in_write_np_engine_en[0x00004];/* enable working of the inbound non-posted engine (for write). a bit for each engine\r
- 0 - engine disabled\r
- 1 - engine enabled */\r
- pseudo_bit_t reserved0[0x00014];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t out_np_persist[0x00001];/* If this bit is set, outbound non-posted request would not be preempted from the engine in the case of retry */\r
- pseudo_bit_t packbuff_bypass_en[0x00001];\r
- pseudo_bit_t reserved1[0x0001e];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t min_inter_frame_gap[0x00004];/* minimum interval between the falling edge of 2 consequtive frame.\r
- 2 - 4 cycles f2f (frame to frame)\r
- 3 - 5 cycles\r
- etc\r
- */\r
- pseudo_bit_t reserved2[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* PCU Prefetch Configuration */\r
-\r
-struct pcu_prefetch_st { /* Little Endian */\r
- pseudo_bit_t max_prefetch[0x00004]; /* The maximum amount of prefetched data for inbound read.\r
- 0000 - 128 bytes\r
- 0001 - 256 bytes\r
- 0010 - 512 bytes\r
- 0011 - 1k bytes\r
- 0100 - 2K bytes\r
- 0101 - 4K bytes\r
- 0110 - 8Kbytes\r
- 0111 - 16KBytes */\r
- pseudo_bit_t reserved0[0x00004];\r
- pseudo_bit_t discard_timeout[0x00004];/* Maximum time to hold prefetched data. When this timer expire, the prefetched data is discarded.\r
- 0 - 2^6 cycles\r
- 1 - 2^7\r
- 2 - 2^8\r
- 3 - 2^9\r
- 4 - 2^10\r
- 5 - 2^11\r
- 6 - 2^13\r
- 7 - 2^15\r
- 8-15 - disable\r
- Reset value is 7\r
- */\r
- pseudo_bit_t reserved1[0x00004];\r
- pseudo_bit_t prefetch_discard_mode[0x00004];/* mode for discarding prefetched data:\r
- 0000 - discard only due to timeout\r
- 0001 - write hit to the memory bar of the prefetched data\r
- 0010 - write hit to the page of the prefetched data\r
- 0100 - immediate discard (when the read transaction is disconneted)\r
-\r
- others - reserved */\r
- pseudo_bit_t reserved2[0x00004];\r
- pseudo_bit_t prefetch_watermark[0x00005];/* Buffer empty level for starting prefetch. The value of this register is the line number in the fifo. default velue is f, implies half buffer.\r
- */\r
- pseudo_bit_t reserved3[0x00003];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t decoder_prefetch_ctrl[0x00008];/* bit 0 - prefetch low - prefetch en for the first 4G (in upstream read transactions in secondary mode and in subtractive) Value of 0 is enable\r
- bit 1 - prefetch high\r
- bit 2 - prefetch en (0 - enable) - for enable disable for the whole prefetch feature.\r
- bit 3 - ISA en\r
-\r
- **** all those bits exist in the pci configuration header. They would by accessed by cfg cycles and updated by FW */\r
- pseudo_bit_t reserved4[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00040];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* PCU NSWITCH TX Configuration */\r
-\r
-struct pcu_tx_st { /* Little Endian */\r
- pseudo_bit_t dmu_p_cred[0x00004]; /* Credits to send posted requests to the DMU */\r
- pseudo_bit_t dmu_np_cred[0x00004]; /* Credits to send non-posted requests to the DMU */\r
- pseudo_bit_t ntu_p_cred[0x00004]; /* Credits to send posted requests to the NTU */\r
- pseudo_bit_t ntu_np_cred[0x00004]; /* Credits to send non-posted requests to the NTU */\r
- pseudo_bit_t hca_p_cred[0x00004]; /* Credits to send posted requests to the HCA */\r
- pseudo_bit_t hca_np_cred[0x00004]; /* Credits to send non-posted requests to the HCA */\r
- pseudo_bit_t hca_resp_cred[0x00004];/* Credits to send responses to the HCA */\r
- pseudo_bit_t reserved0[0x00004];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* PCU General Configuration - External Domain */\r
-\r
-struct PCUGENERALEXT_st { /* Little Endian */\r
- pseudo_bit_t p1_ntu_id[0x00003];\r
- pseudo_bit_t p1_pcu_id[0x00003];\r
- pseudo_bit_t p1_hca_id[0x00003];\r
- pseudo_bit_t p1_dmu_id[0x00003];\r
- pseudo_bit_t reserved0[0x00004];\r
- pseudo_bit_t Primary_mode[0x00001]; /* This bit is used to inform Tavor if it is in Primary or secondary mode.\r
- 0 - Secondary mode\r
- 1 - Primary mode */\r
- pseudo_bit_t reserved1[0x0000f];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pci_retry_timer[0x00008];/* defines the number of PCI Clocks that the Master will wait between retries of a delayed transaction from the moment bus returned to IDLE. This field is specified in units of 2 PCI cycles. When set to zero, the transaction will be retried as fast as possible. Reset value is 4 (8 PCI cycles) */\r
- pseudo_bit_t max_pci_retry_times[0x00018];/* used by the PCI Master to set the maximum times a delayed request will be retried on the bus. If no success is achieved after the specified amount of retries, the PCIM will report a Master Abort condition. Reset value is 0x000FFF. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t split_timeout[0x00004];/* The number of PCI cycles that we wait for split completion. If expired, appropriate cause bit is set. Encoding:\r
- 0 - 2^6 cycles\r
- 1 - 2^7\r
- 2 - 2^8\r
- 3 - 2^9\r
- 4 - 2^10\r
- 5 - 2^11\r
- 6 - 2^13\r
- 7 - 2^15\r
- 8-15 - disable\r
- Reset value is 7 */\r
- pseudo_bit_t reserved2[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t slowdec[0x00001]; /* When this bit is asserted, address decoding is slow (rather than medium) */\r
- pseudo_bit_t mwdcl[0x00001]; /* When set, even when latency timer expire, memory write cotinue until the next cache line boundry. Default value is 0. */\r
- pseudo_bit_t reserved3[0x00006];\r
- pseudo_bit_t nsb_page_size[0x00004];/* page_size encoding\r
- 0000 - 1K (reserved)\r
- 0001 - 2K (reserved)\r
- 0010 - 4K (default)\r
- 0011 - 8K\r
- 0100 - 16K\r
- 0101 - 32K\r
- 0110 - 64K\r
- Others - reserved\r
- */\r
- pseudo_bit_t reserved4[0x00004];\r
- pseudo_bit_t pci_page_size[0x00004];/* page_size encoding\r
- 000 - 0.5K (default value)\r
- 001 - 1K\r
- 010 - 2K\r
- 011 - 4K\r
- 100 - 128 byte\r
- 101 - 256 byte */\r
- pseudo_bit_t reserved5[0x00004];\r
- pseudo_bit_t data_to_pci_req_waterlevel[0x00004];/* The amount of bytes that should be accumulated in the posted write buffer before initiating outbound transaction\r
-\r
- Do we have such waterlevel for inbound ??? TBD */\r
- pseudo_bit_t data_to_pci_disc_waterlevel[0x00004];/* The amount of bytes that should be left in the posted write buffer before disconnecting outbound transaction */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x00008];\r
- pseudo_bit_t functions[0x00003]; /* The number of functions implemented.\r
- This value is being checked when accepting type 0 config cycle */\r
- pseudo_bit_t reserved7[0x00015];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x00003];\r
- pseudo_bit_t max_outstanding_split_trans[0x00004];/* Maximum Outstanding Split Transactions in the PCIX Command register. This register sets the maximum number of Split Transactions the device is permitted to have outstanding at one time.\r
-\r
- Register Maximum Outstanding\r
- 0000 - 1\r
- 0001 - 2\r
- 0010 - 3\r
- ...\r
- 1111 - 16\r
- */\r
- pseudo_bit_t reserved9[0x00019];\r
-/* --------------------------------------------------------- */\r
- struct pcu_gp_cfg_st gp_cfg; /* general purpose configuration register\r
-\r
- 3 1 - Enable cfg_cycle engine. When cleared, cfg cycles respond with retry */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t array_redundency1[0x00020];/* general purpose configuration register */\r
-/* --------------------------------------------------------- */\r
- struct pcu_gp_cfg_h1_st gp_cfg_h1;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* BIST Debug */\r
-\r
-struct BIST_DEBUG_st { /* Little Endian */\r
- pseudo_bit_t fail_number[0x0000a];\r
- pseudo_bit_t reserved0[0x00006];\r
- pseudo_bit_t unit_number[0x00005];\r
- pseudo_bit_t reserved1[0x00003];\r
- pseudo_bit_t bist_number[0x00003];\r
- pseudo_bit_t reserved2[0x00004];\r
- pseudo_bit_t data_valid[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bist_debug_data0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bist_debug_data1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bist_debug_data2[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bist_debug_data3[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bist_debug_data4[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bist_debug_data5[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bist_debug_data6[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bist_debug_data7[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00160];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* General Purpose Semaphores */\r
-\r
-struct cs_semaphores_st { /* Little Endian */\r
- pseudo_bit_t PERFCNT[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t LED[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CRBUS[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP3[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP4[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP5[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP6[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP7[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP8[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP9[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP10[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP11[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP12[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP13[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP14[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP15[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP16[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP17[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP18[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP19[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP20[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP21[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP22[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP23[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP24[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP25[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP26[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP27[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP28[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP29[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP30[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP31[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP32[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP33[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP34[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP35[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP36[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP37[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP38[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP39[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP40[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP41[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP42[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP43[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP44[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP45[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP46[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP47[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP48[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP49[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP50[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP51[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP52[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP53[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP54[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP55[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP56[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP57[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP58[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP59[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP60[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP61[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SemaP62[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Misc Cause Register */\r
-\r
-struct miscellaneous_cause_register_st { /* Little Endian */\r
- pseudo_bit_t crbus_brkpnt_cause[0x00001];\r
- pseudo_bit_t crbus_to_cause[0x00001];\r
- pseudo_bit_t ibml_not_idle_cause[0x00001];\r
- pseudo_bit_t i2c_master_idle_cause[0x00001];\r
- pseudo_bit_t reserved0[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t crbus_brkpnt_clear[0x00001];\r
- pseudo_bit_t crbus_to_clear[0x00001];\r
- pseudo_bit_t ibml_not_idle_clr[0x00001];\r
- pseudo_bit_t i2c_master_idle_clr[0x00001];\r
- pseudo_bit_t reserved1[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t crbus_brkpnt_set[0x00001];\r
- pseudo_bit_t crbus_to_set[0x00001];\r
- pseudo_bit_t ibml_not_idle_set[0x00001];\r
- pseudo_bit_t i2c_master_idle_set[0x00001];\r
- pseudo_bit_t reserved2[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t crbus_brkpnt_ena[0x00001];\r
- pseudo_bit_t crbus_to_ena[0x00001];\r
- pseudo_bit_t ibml_not_idle_ena[0x00001];\r
- pseudo_bit_t i2c_master_idle_ena[0x00001];\r
- pseudo_bit_t reserved3[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t crbus_brkpnt_serviced[0x00001];\r
- pseudo_bit_t crbus_to_serviced[0x00001];\r
- pseudo_bit_t ibml_not_idle_serviced[0x00001];\r
- pseudo_bit_t i2c_master_idle_serviced[0x00001];\r
- pseudo_bit_t reserved4[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t vir_addr1[0x00014];\r
- pseudo_bit_t reserved5[0x0000a];\r
- pseudo_bit_t vir_cmd1[0x00001];\r
- pseudo_bit_t vir_active1[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t vir_data0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t vir_addr2[0x00014];\r
- pseudo_bit_t reserved6[0x0000a];\r
- pseudo_bit_t vir_cmd2[0x00001];\r
- pseudo_bit_t vir_active2[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t vir_data2[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x00080];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* CR Address Breakpoints */\r
-\r
-struct cs_brk_point_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00002];\r
- pseudo_bit_t Brkpoint0addr[0x00012];\r
- pseudo_bit_t reserved1[0x00002];\r
- pseudo_bit_t Brkpoint0mask[0x00008];\r
- pseudo_bit_t ER0[0x00001];\r
- pseudo_bit_t EW0[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00002];\r
- pseudo_bit_t Brkpoint1addr[0x00012];\r
- pseudo_bit_t reserved3[0x00002];\r
- pseudo_bit_t Brkpoint1mask[0x00008];\r
- pseudo_bit_t ER1[0x00001];\r
- pseudo_bit_t EW1[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00002];\r
- pseudo_bit_t Brkpoint2addr[0x00012];\r
- pseudo_bit_t reserved5[0x00002];\r
- pseudo_bit_t Brkpoint2mask[0x00008];\r
- pseudo_bit_t ER2[0x00001];\r
- pseudo_bit_t EW2[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x00002];\r
- pseudo_bit_t Brkpoint3addr[0x00012];\r
- pseudo_bit_t reserved7[0x00002];\r
- pseudo_bit_t Brkpoint3mask[0x00008];\r
- pseudo_bit_t ER3[0x00001];\r
- pseudo_bit_t EW3[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x00002];\r
- pseudo_bit_t Brkpoint4addr[0x00012];\r
- pseudo_bit_t reserved9[0x00002];\r
- pseudo_bit_t Brkpoint4mask[0x00008];\r
- pseudo_bit_t ER4[0x00001];\r
- pseudo_bit_t EW4[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved10[0x00002];\r
- pseudo_bit_t Brkpoint5addr[0x00012];\r
- pseudo_bit_t reserved11[0x00002];\r
- pseudo_bit_t Brkpoint5mask[0x00008];\r
- pseudo_bit_t ER5[0x00001];\r
- pseudo_bit_t EW5[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved12[0x00002];\r
- pseudo_bit_t Brkpoint6addr[0x00012];\r
- pseudo_bit_t reserved13[0x00002];\r
- pseudo_bit_t Brkpoint6mask[0x00008];\r
- pseudo_bit_t ER6[0x00001];\r
- pseudo_bit_t EW6[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved14[0x00002];\r
- pseudo_bit_t BrkpointLatch[0x00012];\r
- pseudo_bit_t reserved15[0x0000a];\r
- pseudo_bit_t R_latch[0x00001];\r
- pseudo_bit_t W_latch[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved16[0x00100];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Consolidated Cause Registers */\r
-\r
-struct CONSCAUSE_st { /* Little Endian */\r
- pseudo_bit_t misc_cause[0x00001]; /* Consolidated Cause Register */\r
- pseudo_bit_t reserved0[0x00005];\r
- pseudo_bit_t dmu0_cause[0x00001];\r
- pseudo_bit_t dmu1_cause[0x00001];\r
- pseudo_bit_t ntu0_cause[0x00001];\r
- pseudo_bit_t ntu1_cause[0x00001];\r
- pseudo_bit_t pcu0_cause[0x00001];\r
- pseudo_bit_t pcu1_cause[0x00001];\r
- pseudo_bit_t nsi0_cause[0x00001];\r
- pseudo_bit_t nsi1_cause[0x00001];\r
- pseudo_bit_t tpt0_cause[0x00001];\r
- pseudo_bit_t tpt1_cause[0x00001];\r
- pseudo_bit_t qpc0_cause[0x00001];\r
- pseudo_bit_t qpc1_cause[0x00001];\r
- pseudo_bit_t ldb0_cause[0x00001];\r
- pseudo_bit_t ldb1_cause[0x00001];\r
- pseudo_bit_t sde0_cause[0x00001];\r
- pseudo_bit_t sde1_cause[0x00001];\r
- pseudo_bit_t exe0_cause[0x00001];\r
- pseudo_bit_t exe1_cause[0x00001];\r
- pseudo_bit_t rde0_cause[0x00001];\r
- pseudo_bit_t rde1_cause[0x00001];\r
- pseudo_bit_t tcu0_cause[0x00001];\r
- pseudo_bit_t tcu1_cause[0x00001];\r
- pseudo_bit_t timer_cause[0x00001];\r
- pseudo_bit_t gpio_cause[0x00001];\r
- pseudo_bit_t encoded_cause[0x00001];\r
- pseudo_bit_t reserved1[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ib1_cause0[0x00001];\r
- pseudo_bit_t ib1_cause1[0x00001];\r
- pseudo_bit_t ib2_cause0[0x00001];\r
- pseudo_bit_t ib2_cause1[0x00001];\r
- pseudo_bit_t reserved2[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t erpena_virbus[0x00001];\r
- pseudo_bit_t reserved3[0x00005];\r
- pseudo_bit_t erpena[0x00019];\r
- pseudo_bit_t reserved4[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t erpena2[0x00004];\r
- pseudo_bit_t reserved5[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t intb_virbus[0x00001];\r
- pseudo_bit_t reserved6[0x00005];\r
- pseudo_bit_t intb[0x00019];\r
- pseudo_bit_t reserved7[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t intb2[0x00004];\r
- pseudo_bit_t reserved8[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved9[0x00040];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t into_virbus[0x00001];\r
- pseudo_bit_t reserved10[0x00005];\r
- pseudo_bit_t into[0x00019];\r
- pseudo_bit_t reserved11[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t into2[0x00004];\r
- pseudo_bit_t reserved12[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t serr_virbus[0x00001];\r
- pseudo_bit_t reserved13[0x00005];\r
- pseudo_bit_t serr[0x00019];\r
- pseudo_bit_t reserved14[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t serr2[0x00004];\r
- pseudo_bit_t reserved15[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved16[0x00080];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Flash Memory Interface Control */\r
-\r
-struct flash_memory_st { /* Little Endian */\r
- pseudo_bit_t data_read_wait_cycle[0x00008];\r
- pseudo_bit_t reserved0[0x00008];\r
- pseudo_bit_t data_write_wait_cycle[0x00008];\r
- pseudo_bit_t reserved1[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t address[0x00013];\r
- pseudo_bit_t reserved2[0x0000a];\r
- pseudo_bit_t flash_CMD[0x00003];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t flash_data3[0x00008];\r
- pseudo_bit_t flash_data2[0x00008];\r
- pseudo_bit_t flash_data1[0x00008];\r
- pseudo_bit_t flash_data0[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x000a0];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Serial Port Master */\r
-\r
-struct serial_port_master_st { /* Little Endian */\r
- pseudo_bit_t ADR7[0x00007]; /* Addr[6:0] */\r
- pseudo_bit_t ADR10[0x00003]; /* Addr[9:7] */\r
- pseudo_bit_t reserved0[0x00005];\r
- pseudo_bit_t A[0x00001];\r
- pseudo_bit_t STS[0x00003]; /* Status */\r
- pseudo_bit_t reserved1[0x00003];\r
- pseudo_bit_t VBT[0x00002]; /* Valid Bytes */\r
- pseudo_bit_t reserved2[0x00005];\r
- pseudo_bit_t CMD[0x00003];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DAT_3[0x00008]; /* Serial Master Data 3 */\r
- pseudo_bit_t DAT_2[0x00008]; /* Serial Master Data 2 */\r
- pseudo_bit_t DAT_1[0x00008]; /* Serial Master Data 1 */\r
- pseudo_bit_t DAT_0[0x00008]; /* Serial Master Data 0 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SMTO[0x00010]; /* Serial Master Timeout */\r
- pseudo_bit_t GFRC[0x00008]; /* Glitch Free Rise Counter */\r
- pseudo_bit_t GFFC[0x00008]; /* Glitch Free Fall Counter */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CLKG[0x00010]; /* Serial Master Clock Generator */\r
- pseudo_bit_t reserved3[0x00008];\r
- pseudo_bit_t CLKSC[0x00008]; /* Clock Stretching Counter */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* IBML Slave */\r
-\r
-struct IBML_slave_st { /* Little Endian */\r
- pseudo_bit_t ADR0[0x00007]; /* IBMLSlaveAddress */\r
- pseudo_bit_t E0[0x00001]; /* IBML Slave address 0 decoding enable */\r
- pseudo_bit_t reserved0[0x00008];\r
- pseudo_bit_t CAP_ADDR[0x00007]; /* The actual captured IB-ML address by the slave */\r
- pseudo_bit_t reserved1[0x00005];\r
- pseudo_bit_t W4BSTP[0x00001]; /* IBML detected stop condition after 4 byte write (should be cleaned by software) */\r
- pseudo_bit_t STS[0x00003]; /* Status */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DAT[0x00020]; /* IBML Data */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ADR1[0x00007];\r
- pseudo_bit_t E1[0x00001];\r
- pseudo_bit_t ADR2[0x00007];\r
- pseudo_bit_t E2[0x00001];\r
- pseudo_bit_t ADR3[0x00007];\r
- pseudo_bit_t E3[0x00001];\r
- pseudo_bit_t ADR4[0x00007];\r
- pseudo_bit_t E4[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ADR5[0x00007];\r
- pseudo_bit_t E5[0x00001];\r
- pseudo_bit_t ADR6[0x00007];\r
- pseudo_bit_t E6[0x00001];\r
- pseudo_bit_t ADR7[0x00007];\r
- pseudo_bit_t E7[0x00001];\r
- pseudo_bit_t ADR8[0x00007];\r
- pseudo_bit_t E8[0x00001];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Serial Port Slave */\r
-\r
-struct serial_port_slave_st { /* Little Endian */\r
- pseudo_bit_t slave_ADR[0x00007]; /* Serial Slave Address */\r
- pseudo_bit_t E[0x00001]; /* Enable slave address decoding\r
- (default value: if serial eprom not present - enabled, otherwise disabled) */\r
- pseudo_bit_t reserved0[0x00017];\r
- pseudo_bit_t F[0x00001];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Parallel CPU Port */\r
-\r
-struct parallel_CPU_port_st { /* Little Endian */\r
- pseudo_bit_t CPUT[0x00004]; /* CPU Type */\r
- pseudo_bit_t reserved0[0x0001a];\r
- pseudo_bit_t CpuMode[0x00002];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Parallel Port Debug (global) */\r
-\r
-struct par_debug_p_st { /* Little Endian */\r
- pseudo_bit_t PowerUp[0x00001];\r
- pseudo_bit_t extend[0x00001];\r
- pseudo_bit_t exthigh[0x00001];\r
- pseudo_bit_t extmore[0x00001];\r
- pseudo_bit_t RBCdelay[0x00005];\r
- pseudo_bit_t datadelay[0x00002];\r
- pseudo_bit_t TBCgenpolar[0x00001];\r
- pseudo_bit_t rx_reversed_bit_order[0x00001];\r
- pseudo_bit_t tx_reversed_bit_order[0x00001];\r
- pseudo_bit_t reserved0[0x00012];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* System Monitoring Control */\r
-\r
-struct system_monitoring_ctrl_st { /* Little Endian */\r
- pseudo_bit_t CLKDIV[0x00008]; /* System Monitoring Clock Divider */\r
- pseudo_bit_t reserved0[0x00008];\r
- pseudo_bit_t CHBLEN[0x0000b]; /* System Monitoring Chain Bit Length\r
- Default Value is 0x33C loaded 1 cycle after reset . */\r
- pseudo_bit_t reserved1[0x00005];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @serdes_rsu */\r
-\r
-struct serdes_rsu_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00018];\r
- pseudo_bit_t RSR[0x00005]; /* reserved bits */\r
- pseudo_bit_t CMD[0x00003];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t RSU_value[0x00014];\r
- pseudo_bit_t reserved1[0x0000c];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* SerDes General Control */\r
-\r
-struct serdes_general_cont_st { /* Little Endian */\r
- pseudo_bit_t SDDC0[0x00001];\r
- pseudo_bit_t SDTHLD0[0x00001];\r
- pseudo_bit_t reserved0[0x0001e];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Encoded Interrupt Control Registers */\r
-\r
-struct encoded_intr_ctlr_regs_st { /* Little Endian */\r
- pseudo_bit_t GPIO_EnCauseHigh[0x00020];/* Encoded Interrupt Cause [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_EnCauseLow[0x00020];/* Encoded Interrupt Cause [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_EnClearHigh[0x00020];/* Clear Encoded Interrupt [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_EnClearLow[0x00020];/* Clear Encoded Interrupt [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_EnSetHigh[0x00020];/* Set Encoded Interrupt [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_EnSetLow[0x00020];/* Set Encoded Interrupt [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_EnEnableHigh[0x00020];/* Encoded Interrupt Enable [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_EnEnableLow[0x00020];/* Encoded Interrupt Enable [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_EnServicedHigh[0x00020];/* Encoded Interrupt Serviced # [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_EnServicedLow[0x00020];/* Encoded Interrupt Serviced # [31:0] */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* GPIO */\r
-\r
-struct GPIO_st { /* Little Endian */\r
- pseudo_bit_t GPIO_DataHigh[0x00008];/* GPIO Data [39:32] */\r
- pseudo_bit_t reserved0[0x00015];\r
- pseudo_bit_t serr_bit[0x00001]; /* sw controlled access to serr pin */\r
- pseudo_bit_t intb_bit[0x00001]; /* sw controlled access to intb pin */\r
- pseudo_bit_t into_bit[0x00001]; /* sw controlled access to into pin */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_DataLow[0x00020]; /* GPIO Data [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_DirHigh[0x00008]; /* GPIO Direction [39:32] */\r
- pseudo_bit_t reserved1[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_DirLow[0x00020]; /* GPIO Direction [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_PolHigh[0x00008]; /* GPIO Polarity [39:32] */\r
- pseudo_bit_t reserved2[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_PolLow[0x00020]; /* GPIO Polarity [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_ModeHigh[0x00008];/* GPIO Output Mode [39:32] */\r
- pseudo_bit_t reserved3[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_ModeLow[0x00020]; /* GPIO Output Mode [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_DeCauseHigh[0x00008];/* GPIO Interrupt Cause [39:32] */\r
- pseudo_bit_t reserved4[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_DeCauseLow[0x00020];/* GPIO Interrupt Cause [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_DeClearHigh[0x00008];/* Clear GPIO Interrupt Cause [39:32] */\r
- pseudo_bit_t reserved5[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_DeClearLow[0x00020];/* Clear GPIO Interrupt Cause [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_DeSetHigh[0x00008];/* Set GPIO Interrupt Cause [39:32] */\r
- pseudo_bit_t reserved6[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_DeSetLow[0x00020];/* Set GPIO Interrupt Cause [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_DeEnableHigh[0x00008];/* GPIO Interrupt Enabled [39:32] */\r
- pseudo_bit_t reserved7[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_DeEnableLow[0x00020];/* GPIO Interrupt Enabled [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_DeServicedHigh[0x00008];/* GPIO Interrupt Serviced # [39:32] */\r
- pseudo_bit_t reserved8[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_DeServicedLow[0x00020];/* GPIO Interrupt Serviced # [31:0] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved9[0x00040];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_DataClearHigh[0x00008];\r
- pseudo_bit_t reserved10[0x00015];\r
- pseudo_bit_t serrclear[0x00001];\r
- pseudo_bit_t intbclear[0x00001];\r
- pseudo_bit_t intoclear[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_DataClearLow[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIIO_DataSetHigh[0x00008];\r
- pseudo_bit_t reserved11[0x00015];\r
- pseudo_bit_t serrset[0x00001];\r
- pseudo_bit_t intbset[0x00001];\r
- pseudo_bit_t intoset[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GPIO_DataSetLow[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Programmable Timers */\r
-\r
-struct prog_timers_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00080];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Timer_Limit0[0x0001e]; /* Use value bigger than 1 */\r
- pseudo_bit_t M0[0x00001];\r
- pseudo_bit_t S0[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Timer_Limit1[0x0001e]; /* Use value bigger than 1 */\r
- pseudo_bit_t M1[0x00001];\r
- pseudo_bit_t S1[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Timer_Limit2[0x0001e]; /* Use value bigger than 1 */\r
- pseudo_bit_t M2[0x00001];\r
- pseudo_bit_t S2[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Timer_Limit3[0x0001e]; /* Use value bigger than 1 */\r
- pseudo_bit_t M3[0x00001];\r
- pseudo_bit_t S3[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Timer0cause[0x00001];\r
- pseudo_bit_t Timer1cause[0x00001];\r
- pseudo_bit_t Timer2cause[0x00001];\r
- pseudo_bit_t Timer3cause[0x00001];\r
- pseudo_bit_t reserved1[0x0001a];\r
- pseudo_bit_t SMPT[0x00001]; /* Sample Start */\r
- pseudo_bit_t SMPP[0x00001]; /* Sample Stop */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Timer0CLR[0x00001]; /* Clear Timer-Cause */\r
- pseudo_bit_t Timer1CLR[0x00001];\r
- pseudo_bit_t Timer2CLR[0x00001];\r
- pseudo_bit_t Timer3CLR[0x00001];\r
- pseudo_bit_t reserved2[0x0001a];\r
- pseudo_bit_t CSMPT[0x00001]; /* Clear Sample Start */\r
- pseudo_bit_t CSMPP[0x00001]; /* Clear Sample Stop */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Timer0SET[0x00001]; /* Set Timer Cause */\r
- pseudo_bit_t Timer1SET[0x00001];\r
- pseudo_bit_t Timer2SET[0x00001];\r
- pseudo_bit_t Timer3SET[0x00001];\r
- pseudo_bit_t reserved3[0x0001a];\r
- pseudo_bit_t SSMPT[0x00001]; /* Set Sample Start */\r
- pseudo_bit_t SSMPP[0x00001]; /* Set Sample Stop */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ENB[0x00004]; /* Timer Events Enabled */\r
- pseudo_bit_t reserved4[0x0001a];\r
- pseudo_bit_t SMPTE[0x00001]; /* Sample Start Enabled */\r
- pseudo_bit_t SMPPE[0x00001]; /* Sample Stop Enabled */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Timer0srv[0x00001];\r
- pseudo_bit_t Timer1srv[0x00001];\r
- pseudo_bit_t Timer2srv[0x00001];\r
- pseudo_bit_t Timer3srv[0x00001];\r
- pseudo_bit_t reserved5[0x0001a];\r
- pseudo_bit_t SMPTSRV_N[0x00001]; /* Sample Start Serviced # */\r
- pseudo_bit_t SMPPSRV_N[0x00001]; /* Sample Stop Serviced # */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* IB Bist Result */\r
-\r
-struct IB_BIST_result_st { /* Little Endian */\r
- pseudo_bit_t IBP1BC[0x00001]; /* IB Port 1 Bist complited */\r
- pseudo_bit_t IBP1BF[0x00001]; /* IB Port 1 bist failed */\r
- pseudo_bit_t IBP2BC[0x00001]; /* IB Port 2 Bist complited */\r
- pseudo_bit_t IBP2BF[0x00001]; /* IB Port 2 Bist failed */\r
- pseudo_bit_t reserved0[0x0001c];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* IB Port Clock Timer */\r
-\r
-struct IB_port_clock_timer_st { /* Little Endian */\r
- pseudo_bit_t PSMPT[0x00010]; /* Stop Samples Timer */\r
- pseudo_bit_t TSMPT[0x00010]; /* Start Samples Timer */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ib_phy_timeout[0x00010];/* IB Phy Timeout Generator */\r
- pseudo_bit_t SMPTK[0x00010]; /* Samples Tick Timer */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* BIST Result */\r
-\r
-struct BIST_result_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00008];\r
- pseudo_bit_t DMU0[0x00001];\r
- pseudo_bit_t DMU1[0x00001];\r
- pseudo_bit_t NTU0[0x00001];\r
- pseudo_bit_t NTU1[0x00001];\r
- pseudo_bit_t PCU0[0x00001];\r
- pseudo_bit_t PCU1[0x00001];\r
- pseudo_bit_t NSI0[0x00001];\r
- pseudo_bit_t NSI1[0x00001];\r
- pseudo_bit_t TPT0[0x00001];\r
- pseudo_bit_t TPT1[0x00001];\r
- pseudo_bit_t QPC0[0x00001];\r
- pseudo_bit_t QPC1[0x00001];\r
- pseudo_bit_t LDB0[0x00001];\r
- pseudo_bit_t LDB1[0x00001];\r
- pseudo_bit_t SDE0[0x00001];\r
- pseudo_bit_t SDE1[0x00001];\r
- pseudo_bit_t EXE0[0x00001];\r
- pseudo_bit_t EXE1[0x00001];\r
- pseudo_bit_t RDE0[0x00001];\r
- pseudo_bit_t RDE1[0x00001];\r
- pseudo_bit_t TCU0[0x00001];\r
- pseudo_bit_t TCU1[0x00001];\r
- pseudo_bit_t SERC[0x00001]; /* Serial EEPROM Read Completed */\r
- pseudo_bit_t SERF[0x00001]; /* Serial EEPROM Read Failed */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* INIT and CTRL */\r
-\r
-struct init_and_ctrl_st { /* Little Endian */\r
- pseudo_bit_t RST[0x00001]; /* Reset */\r
- pseudo_bit_t PcuPll_od[0x00001];\r
- pseudo_bit_t last_reset_swhw[0x00001];/* 1 means that the last reset was a SW reset.\r
- 0 means that the last reset was a HW reset */\r
- pseudo_bit_t reserved0[0x00005];\r
- pseudo_bit_t Serial_EEPROM_HW_Address[0x00007];\r
- pseudo_bit_t EEPROM[0x00001];\r
- pseudo_bit_t PCIXCLKDLY[0x00002]; /* PCI IO Timing Strapping */\r
- pseudo_bit_t PCIXCLKFEEDBACK[0x00002];\r
- pseudo_bit_t BISTS[0x00001]; /* BIST Strapping 0 */\r
- pseudo_bit_t FTS[0x00001]; /* Funct TEst Strapping */\r
- pseudo_bit_t SerDes_BISTS[0x00001];\r
- pseudo_bit_t BISTS1[0x00001]; /* BIST Strapping 1 */\r
- pseudo_bit_t EEPROM_type[0x00001];\r
- pseudo_bit_t PcuPll_idin[0x00001];\r
- pseudo_bit_t PcuPll_idinbk[0x00001];\r
- pseudo_bit_t PcuPllctrl[0x00001];\r
- pseudo_bit_t ERP_hold[0x00001];\r
- pseudo_bit_t bist_debug_mode[0x00001];\r
- pseudo_bit_t init_pci[0x00001];\r
- pseudo_bit_t init_ib[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DEVID[0x00010];\r
- pseudo_bit_t REVID[0x00008];\r
- pseudo_bit_t reserved1[0x00008];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* HCA General Configuration Registers */\r
-\r
-struct HCA_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00010];\r
- pseudo_bit_t fcupdatetimedivider[0x00005];\r
- pseudo_bit_t reserved1[0x00003];\r
- pseudo_bit_t fcperiodtimedivider[0x00004];\r
- pseudo_bit_t reserved2[0x00004];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t LVer[0x00004];\r
- pseudo_bit_t TVer[0x00004];\r
- pseudo_bit_t dreqwm_4x_4x[0x00006];\r
- pseudo_bit_t dreqwm_4x_1x[0x00006];\r
- pseudo_bit_t dreqwm_1x_4x[0x00006];\r
- pseudo_bit_t dreqwm_1x_1x[0x00006];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00040];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Cause Registers */\r
-\r
-struct LDB_CAUSEREG_st { /* Little Endian */\r
- pseudo_bit_t parity_err[0x00001];\r
- pseudo_bit_t dequeue_wrong_number[0x00001];\r
- pseudo_bit_t dequeue_when_linklist_empty[0x00001];\r
- pseudo_bit_t enqueue_when_linklist_full[0x00001];\r
- pseudo_bit_t cr_slave_err[0x00001];\r
- pseudo_bit_t reserved0[0x0001b];\r
-/* --------------------------------------------------------- */\r
- struct EXT_CAUSEREG_st extended_cause;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* LDB Access Gateway */\r
-\r
-struct LDBGW_st { /* Little Endian */\r
- struct GWCONTROL_st ldbgwctrl; /* Command\r
- 0x00 Reserved\r
- 0x01 Execute LDB operation as written in the data\r
- 0x02 request for LDB credit\r
- 0x03-0x3F Reserved\r
-\r
- Status\r
- 0x00 Success\r
- 0x01 Error\r
-\r
- Address\r
- For the LDB command, Address is not applicable. Specific command and Data are specified in the GW data according to LDB interface format (see LDB MAS).\r
-\r
- Data\r
- For the LDB Commands, Data contents is described in LDB MAS */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ldbgwdata_127_96_[0x00020];/* LDB Gateway Data */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ldbgwdata_95_64_[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ldbgwdata_63_32_[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ldbgwdata_31_0_[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00060];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @LDB_BIST */\r
-\r
-struct LDB_BIST_st { /* Little Endian */\r
- pseudo_bit_t ldb_bist_rdw_0[0x00007];/* 126 */\r
- pseudo_bit_t reserved0[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rep_arrays_stat[0x00001];\r
- pseudo_bit_t reserved1[0x0001f];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bists_stat[0x00001];\r
- pseudo_bit_t reserved2[0x0001f];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* LDB Debug */\r
-\r
-struct ldb_debug_st { /* Little Endian */\r
- pseudo_bit_t ldbarb_agent[0x00003]; /* arbiter agent */\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t ldbarb_agentlast[0x00003];/* arbiter last agent */\r
- pseudo_bit_t reserved1[0x00001];\r
- pseudo_bit_t arbiter_stage_ps[0x00001];/* ldb arbiter_stage FSM */\r
- pseudo_bit_t reserved2[0x00003];\r
- pseudo_bit_t send_data_to[0x00005]; /* unit to send response to */\r
- pseudo_bit_t reserved3[0x0000f];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qp_num[0x00019]; /* qp/ee number LDB is dealing with */\r
- pseudo_bit_t reserved4[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_state_ps[0x00005]; /* ldb_qpc2ldb FSM */\r
- pseudo_bit_t reserved5[0x00003];\r
- pseudo_bit_t qp_ready[0x00001]; /* ldb_qpc2ldb ready signal */\r
- pseudo_bit_t ldb_doorbell_ps[0x00001];/* ldb_qpc2ldb doorbell FSM */\r
- pseudo_bit_t reserved6[0x00016];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rwe_state_ps[0x00003]; /* rwe FSM */\r
- pseudo_bit_t reserved7[0x00001];\r
- pseudo_bit_t rwe_ready[0x00001]; /* rwe ready signal */\r
- pseudo_bit_t reserved8[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tail[0x00010]; /* tail to LinkList */\r
- pseudo_bit_t head[0x00010]; /* head to LinkList */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ldbcred_agent[0x00002];/* ldb_credmng agent */\r
- pseudo_bit_t reserved9[0x00002];\r
- pseudo_bit_t ldbcred_agentlast[0x00002];/* agent last in ldb_credmng */\r
- pseudo_bit_t reserved10[0x0001a];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* This bit when set indicates that ERP will treat each request coming from the corresponding agent as miss. */\r
-\r
-struct QPCDIRTY_st { /* Little Endian */\r
- pseudo_bit_t ex_sqpc_dirty[0x00001];\r
- pseudo_bit_t reserved0[0x00007];\r
- pseudo_bit_t ld_sqpc_dirty[0x00001];\r
- pseudo_bit_t reserved1[0x00007];\r
- pseudo_bit_t tc_sqpc_dirty[0x00001];\r
- pseudo_bit_t reserved2[0x00007];\r
- pseudo_bit_t rd_sqpc_dirty[0x00001];\r
- pseudo_bit_t reserved3[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ex_rqpc_dirty[0x00001];\r
- pseudo_bit_t reserved4[0x00007];\r
- pseudo_bit_t tc_rqpc_dirty[0x00001];\r
- pseudo_bit_t reserved5[0x00007];\r
- pseudo_bit_t rd_rqpc_dirty[0x00001];\r
- pseudo_bit_t reserved6[0x00007];\r
- pseudo_bit_t tc_cqc_dirty[0x00001];\r
- pseudo_bit_t reserved7[0x00007];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @QPC_BIST */\r
-\r
-struct QPC_BIST_st { /* Little Endian */\r
- pseudo_bit_t qpc_bist1_rdw_0[0x00004];/* 129 */\r
- pseudo_bit_t reserved0[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist1_rdw_1[0x00004];/* 129 */\r
- pseudo_bit_t reserved1[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist1_rdw_2[0x00004];/* 129 */\r
- pseudo_bit_t reserved2[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist1_rdw_3[0x00004];/* 129 */\r
- pseudo_bit_t reserved3[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist1_rdw_4[0x00004];/* 130 */\r
- pseudo_bit_t reserved4[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist1_rdw_5[0x00004];/* 130 */\r
- pseudo_bit_t reserved5[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist1_rdw_6[0x00004];/* 130 */\r
- pseudo_bit_t reserved6[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist1_rdw_7[0x00004];/* 130 */\r
- pseudo_bit_t reserved7[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist2_rdw_0[0x00004];/* 130 */\r
- pseudo_bit_t reserved8[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist2_rdw_1[0x00004];/* 130 */\r
- pseudo_bit_t reserved9[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist2_rdw_2[0x00004];/* 130 */\r
- pseudo_bit_t reserved10[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist2_rdw_3[0x00004];/* 130 */\r
- pseudo_bit_t reserved11[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist2_rdw_4[0x00004];/* 130 */\r
- pseudo_bit_t reserved12[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist2_rdw_5[0x00004];/* 130 */\r
- pseudo_bit_t reserved13[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist2_rdw_6[0x00004];/* 130 */\r
- pseudo_bit_t reserved14[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist2_rdw_7[0x00004];/* 130 */\r
- pseudo_bit_t reserved15[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist3_rdw_0[0x00004];/* 130 */\r
- pseudo_bit_t reserved16[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist3_rdw_1[0x00004];/* 130 */\r
- pseudo_bit_t reserved17[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist3_rdw_2[0x00004];/* 130 */\r
- pseudo_bit_t reserved18[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist3_rdw_3[0x00004];/* 130 */\r
- pseudo_bit_t reserved19[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist3_rdw_4[0x00004];/* 130 */\r
- pseudo_bit_t reserved20[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist3_rdw_5[0x00004];/* 130 */\r
- pseudo_bit_t reserved21[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist3_rdw_6[0x00004];/* 130 */\r
- pseudo_bit_t reserved22[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist3_rdw_7[0x00004];/* 130 */\r
- pseudo_bit_t reserved23[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist4_rdw_0[0x00004];/* 130 */\r
- pseudo_bit_t reserved24[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist4_rdw_1[0x00004];/* 130 */\r
- pseudo_bit_t reserved25[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist4_rdw_2[0x00004];/* 130 */\r
- pseudo_bit_t reserved26[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist4_rdw_3[0x00004];/* 130 */\r
- pseudo_bit_t reserved27[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist4_rdw_4[0x00004];/* 130 */\r
- pseudo_bit_t reserved28[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist4_rdw_5[0x00004];/* 130 */\r
- pseudo_bit_t reserved29[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist4_rdw_6[0x00004];/* 130 */\r
- pseudo_bit_t reserved30[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist4_rdw_7[0x00004];/* 130 */\r
- pseudo_bit_t reserved31[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist5_rdw_0[0x00004];/* 130 */\r
- pseudo_bit_t reserved32[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist5_rdw_1[0x00004];/* 130 */\r
- pseudo_bit_t reserved33[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist5_rdw_2[0x00004];/* 130 */\r
- pseudo_bit_t reserved34[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist5_rdw_3[0x00004];/* 130 */\r
- pseudo_bit_t reserved35[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist5_rdw_4[0x00004];/* 130 */\r
- pseudo_bit_t reserved36[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist5_rdw_5[0x00004];/* 130 */\r
- pseudo_bit_t reserved37[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist6_rdw_0[0x00004];/* 130 */\r
- pseudo_bit_t reserved38[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist6_rdw_1[0x00004];/* 130 */\r
- pseudo_bit_t reserved39[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist6_rdw_2[0x00004];/* 130 */\r
- pseudo_bit_t reserved40[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist6_rdw_3[0x00004];/* 130 */\r
- pseudo_bit_t reserved41[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist6_rdw_4[0x00004];/* 130 */\r
- pseudo_bit_t reserved42[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist6_rdw_5[0x00004];/* 130 */\r
- pseudo_bit_t reserved43[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist7_rdw_0[0x00004];/* 130 */\r
- pseudo_bit_t reserved44[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist7_rdw_1[0x00004];/* 130 */\r
- pseudo_bit_t reserved45[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist7_rdw_2[0x00004];/* 130 */\r
- pseudo_bit_t reserved46[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist7_rdw_3[0x00004];/* 130 */\r
- pseudo_bit_t reserved47[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist8_rdw_0[0x00004];/* 130 */\r
- pseudo_bit_t reserved48[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist8_rdw_1[0x00004];/* 130 */\r
- pseudo_bit_t reserved49[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist8_rdw_2[0x00004];/* 130 */\r
- pseudo_bit_t reserved50[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist8_rdw_3[0x00004];/* 130 */\r
- pseudo_bit_t reserved51[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist8_rdw_4[0x00004];/* 130 */\r
- pseudo_bit_t reserved52[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist8_rdw_5[0x00004];/* 130 */\r
- pseudo_bit_t reserved53[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist8_rdw_6[0x00004];/* 130 */\r
- pseudo_bit_t reserved54[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist8_rdw_7[0x00004];/* 130 */\r
- pseudo_bit_t reserved55[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist9_rdw_0[0x00004];/* 130 */\r
- pseudo_bit_t reserved56[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist9_rdw_1[0x00004];/* 130 */\r
- pseudo_bit_t reserved57[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist9_rdw_2[0x00004];/* 130 */\r
- pseudo_bit_t reserved58[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist9_rdw_3[0x00004];/* 130 */\r
- pseudo_bit_t reserved59[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist9_rdw_4[0x00004];/* 130 */\r
- pseudo_bit_t reserved60[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist9_rdw_5[0x00004];/* 130 */\r
- pseudo_bit_t reserved61[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist9_rdw_6[0x00004];/* 130 */\r
- pseudo_bit_t reserved62[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist9_rdw_7[0x00004];/* 130 */\r
- pseudo_bit_t reserved63[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist13_wdw_0[0x00005];/* 134 */\r
- pseudo_bit_t reserved64[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist13_wdw_1[0x00005];/* 134 */\r
- pseudo_bit_t reserved65[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist13_wdw_2[0x00005];/* 134 */\r
- pseudo_bit_t reserved66[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist13_wdw_3[0x00005];/* 134 */\r
- pseudo_bit_t reserved67[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist13_wdw_4[0x00005];/* 134 */\r
- pseudo_bit_t reserved68[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist13_wdw_5[0x00005];/* 134 */\r
- pseudo_bit_t reserved69[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist13_wdw_6[0x00005];/* 134 */\r
- pseudo_bit_t reserved70[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist13_wdw_7[0x00005];/* 134 */\r
- pseudo_bit_t reserved71[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist14_wdw_0[0x00005];/* 134 */\r
- pseudo_bit_t reserved72[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist14_wdw_1[0x00005];/* 134 */\r
- pseudo_bit_t reserved73[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist14_wdw_2[0x00005];/* 134 */\r
- pseudo_bit_t reserved74[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist14_wdw_3[0x00005];/* 134 */\r
- pseudo_bit_t reserved75[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist14_wdw_4[0x00005];/* 134 */\r
- pseudo_bit_t reserved76[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist14_wdw_5[0x00005];/* 134 */\r
- pseudo_bit_t reserved77[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist14_wdw_6[0x00005];/* 134 */\r
- pseudo_bit_t reserved78[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist14_wdw_7[0x00005];/* 134 */\r
- pseudo_bit_t reserved79[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist24_wdw_0[0x00008];/* 134 */\r
- pseudo_bit_t reserved80[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist25_wdw_0[0x00008];/* 134 */\r
- pseudo_bit_t reserved81[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist26_wdw_0[0x00008];/* 134 */\r
- pseudo_bit_t reserved82[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist27_wdw_0[0x00008];/* 134 */\r
- pseudo_bit_t reserved83[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist28_wdw_0[0x00008];/* 134 */\r
- pseudo_bit_t reserved84[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist29_wdw_0[0x00008];/* 134 */\r
- pseudo_bit_t reserved85[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist30_wdw_0[0x00008];/* 134 */\r
- pseudo_bit_t reserved86[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist31_wdw_0[0x00008];/* 134 */\r
- pseudo_bit_t reserved87[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist32_wdw_0[0x00008];/* 134 */\r
- pseudo_bit_t reserved88[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist32_wdw_1[0x00008];/* 134 */\r
- pseudo_bit_t reserved89[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist33_wdw_0[0x00008];/* 134 */\r
- pseudo_bit_t reserved90[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist35_wdw_0[0x00005];/* 134 */\r
- pseudo_bit_t reserved91[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist35_wdw_1[0x00005];/* 134 */\r
- pseudo_bit_t reserved92[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist35_wdw_2[0x00005];/* 134 */\r
- pseudo_bit_t reserved93[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist35_wdw_3[0x00005];/* 134 */\r
- pseudo_bit_t reserved94[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist35_wdw_4[0x00005];/* 134 */\r
- pseudo_bit_t reserved95[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist35_wdw_5[0x00005];/* 134 */\r
- pseudo_bit_t reserved96[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist35_wdw_6[0x00005];/* 134 */\r
- pseudo_bit_t reserved97[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_bist35_wdw_7[0x00005];/* 134 */\r
- pseudo_bit_t reserved98[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist2waydata_data_rdw_0[0x00006];/* 159 */\r
- pseudo_bit_t reserved99[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist2waydata_data_rdw_1[0x00006];/* 159 */\r
- pseudo_bit_t reserved100[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist2waydata_code_rdw_0[0x00006];/* 159 */\r
- pseudo_bit_t reserved101[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist2waydata_code_rdw_1[0x00006];/* 159 */\r
- pseudo_bit_t reserved102[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rep_arrays_stat_0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rep_arrays_stat_1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rep_arrays_stat_2[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rep_arrays_stat_3[0x00007];\r
- pseudo_bit_t reserved103[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bists_stat_0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bists_stat_1[0x00008];\r
- pseudo_bit_t reserved104[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nonrep_arrays_stat_0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nonrep_arrays_stat_1[0x00002];\r
- pseudo_bit_t reserved105[0x0001e];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved106[0x00220];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* QPC General Configuration */\r
-\r
-struct QPCGRLCFG_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00018];\r
- pseudo_bit_t gp_cfg[0x00008]; /* General Purpose Configuration Register */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00060];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* QPC/EEC/CQC Memory Access Parameters */\r
-\r
-struct QPCBASEADDR_st { /* Little Endian */\r
- pseudo_bit_t key[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t pd[0x00018];\r
- pseudo_bit_t te[0x00001];\r
- pseudo_bit_t reserved0[0x00004];\r
- pseudo_bit_t va_pa[0x00001]; /* When cleared, baseaddress is physical address and no translation will be done. When set, address is virtual. This bit does not control wether TPT is accessed or not (this is done by the te field). If te is set, TPT will be accessed (regardless of va_pa value) for address decoding purposes. */\r
- pseudo_bit_t np[0x00001];\r
- pseudo_bit_t nsvl[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsq_for_reads[0x00006];\r
- pseudo_bit_t reserved1[0x00002];\r
- pseudo_bit_t nsq_for_writes[0x00006];\r
- pseudo_bit_t reserved2[0x00001];\r
- pseudo_bit_t mem_io[0x00001]; /* mem/io bit to be used in the NSI transaction if the te bit is cleared (no tpt access)\r
- 1 - memory\r
- 0 - I/O */\r
- pseudo_bit_t reserved3[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t base_addr_srqp_high[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t base_addr_srqp_low[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t log_num_of_qp[0x00005];\r
- pseudo_bit_t reserved5[0x0000b];\r
- pseudo_bit_t log_qpc_entry_size[0x00004];\r
- pseudo_bit_t reserved6[0x00004];\r
- pseudo_bit_t log_qpc_entry_stride[0x00005];\r
- pseudo_bit_t reserved7[0x00003];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t base_addr_ee_high[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t timeout_qpn[0x00020]; /* in HW this field was calledbase_addr_ee_low now\r
- it use to pass qpn with T.O from QPC to EXES */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t log_num_of_ee[0x00005];\r
- pseudo_bit_t reserved9[0x0000b];\r
- pseudo_bit_t log_eec_entry_size[0x00004];\r
- pseudo_bit_t reserved10[0x00004];\r
- pseudo_bit_t log_eec_entry_stride[0x00005];\r
- pseudo_bit_t reserved11[0x00003];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved12[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t base_addr_cqp_high[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t base_addr_cqp_low[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t log_num_of_cq[0x00005];\r
- pseudo_bit_t reserved13[0x00013];\r
- pseudo_bit_t log_cqc_entry_stride[0x00005];\r
- pseudo_bit_t reserved14[0x00003];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved15[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* QPC NSI Gateway */\r
-\r
-struct QPCNSIGW_st { /* Little Endian */\r
- struct NSIGWCTRL_st nsigw_ctrl;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00060];\r
-/* --------------------------------------------------------- */\r
- struct NSIGWEXTCTRL_st nsi_gateway_ext_control;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00080];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t crl_fsm[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x005e0];\r
-/* --------------------------------------------------------- */\r
- struct NSIGWRAM_st nsi_gateway_ram;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct COMP_FSM_st { /* Little Endian */\r
- pseudo_bit_t fifo_ps[0x00001];\r
- pseudo_bit_t gw_ps_sram[0x00002];\r
- pseudo_bit_t tag_ps[0x00002];\r
- pseudo_bit_t qpstate_ps[0x00002];\r
- struct STD_QC_FSMS_st qc_fsms;\r
- pseudo_bit_t reserved0[0x00009];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct RECEIVE_FSM_st { /* Little Endian */\r
- pseudo_bit_t in_use_ps[0x00002];\r
- pseudo_bit_t gw_ps_sram[0x00002];\r
- pseudo_bit_t tag_ps[0x00002];\r
- pseudo_bit_t qpstate_ps[0x00002];\r
- struct STD_QC_FSMS_st qc_fsms;\r
- pseudo_bit_t reserved0[0x00008];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct SEND_FSM_st { /* Little Endian */\r
- pseudo_bit_t in_use_ps[0x00002];\r
- pseudo_bit_t gw_ps_sram[0x00002];\r
- pseudo_bit_t tag_ps[0x00002];\r
- pseudo_bit_t qpstate_ps[0x00002];\r
- struct STD_QC_FSMS_st qc_fsms;\r
- pseudo_bit_t c2t_ps[0x00001];\r
- pseudo_bit_t time_access_ps[0x00002];\r
- pseudo_bit_t gw_ps_timers[0x00002];\r
- pseudo_bit_t reserved0[0x00003];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Transport Timeout Mechanism Access */\r
-\r
-struct QPCTIMERS_st { /* Little Endian */\r
- pseudo_bit_t limit[0x00009];\r
- pseudo_bit_t reserved0[0x00017];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t Address[0x00009];\r
- pseudo_bit_t reserved1[0x0000f];\r
- pseudo_bit_t gwcmd[0x00006];\r
- pseudo_bit_t gwbusy[0x00001];\r
- pseudo_bit_t gwlocked[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t timers_gw_data[0x00010];\r
- pseudo_bit_t reserved2[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t to_status[0x00020];\r
-/* --------------------------------------------------------- */\r
- struct timeoutfifoctrl_st timeoutfifoctrl;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t timeoutfifodata[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00040];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Context Gateways */\r
-\r
-struct QCGWS_st { /* Little Endian */\r
- struct QCGW_st qcgw;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00040];\r
-/* --------------------------------------------------------- */\r
- struct QCMISSGW_st qcmissgw;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x001c0];\r
-/* --------------------------------------------------------- */\r
- struct QCTAGGW_st qctaggw;\r
-/* --------------------------------------------------------- */\r
- struct QC_OP_MASK_st opcode_mask;\r
- pseudo_bit_t reserved2[0x00008];\r
- pseudo_bit_t condtion_mask[0x00006];\r
- pseudo_bit_t reserved3[0x00002];\r
-/* --------------------------------------------------------- */\r
- struct REEXEFSMCTL_st ReexeFsmCtl;\r
-/* --------------------------------------------------------- */\r
- struct QCGATEKEEPER_st qcgatekeeper;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Cache Performance Counters */\r
-\r
-struct CACHEPERF_st { /* Little Endian */\r
- pseudo_bit_t accesscounter[0x00020];/* Access Counter: Incremented for every access to the cache.\r
- Generates an event to the unit iRISC every time it wraps around. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00060];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Cause Registers */\r
-\r
-struct QPC_CAUSEREG_st { /* Little Endian */\r
- pseudo_bit_t irisc_nsw_error[0x00001];\r
- pseudo_bit_t SQPC_parity_err[0x00001];\r
- pseudo_bit_t Hit_more_one_way_SQPC[0x00001];\r
- pseudo_bit_t RQPC_parity_err[0x00001];\r
- pseudo_bit_t Hit_more_one_way_RQPC[0x00001];\r
- pseudo_bit_t CQC_parity_err[0x00001];\r
- pseudo_bit_t Hit_more_one_way_CQC[0x00001];\r
- pseudo_bit_t CR_slave_timeout[0x00001];\r
- pseudo_bit_t reserved0[0x00018];\r
-/* --------------------------------------------------------- */\r
- struct EXT_CAUSEREG_st extended_cause;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* CQ Doorbell FIFO */\r
-\r
-struct CQDBFIFO_st { /* Little Endian */\r
- struct CQFIFOGWCTL_st cqfifo_gwctl;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t fifodata0[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Virtual CR Space Access Register */\r
-\r
-struct CRGW_st { /* Little Endian */\r
- pseudo_bit_t address[0x00014]; /* Address in CR-Space */\r
- pseudo_bit_t reserved0[0x0000a];\r
- pseudo_bit_t cmd[0x00001]; /* 1 - Read\r
- 0 - Write */\r
- pseudo_bit_t active[0x00001]; /* if cleared, CR-Space acceses through this slave are done by hardware. If set, the cr-space gateway is used by the slave to access the CR-Space. Transaction details are stored in the cmd, address and data register and busy bit is set to trigger FW handling of the transaction. FW clears the busy field to notify hardware transaction completion. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t data[0x00020]; /* For write - the data to be writen.\r
- For read - return data to here.\r
- Wrting to this register signals the end of the ERP processing - so it need to be done to read & writes !! */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* NSI BIST */\r
-\r
-struct nsi_bist_st { /* Little Endian */\r
- pseudo_bit_t nsi_bist_dmunturx_wdw_0[0x00008];/* 153 */\r
- pseudo_bit_t reserved0[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_bist_dmunturx_wdw_1[0x00008];/* 153 */\r
- pseudo_bit_t reserved1[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_bist_dmunturx_wdw_2[0x00008];/* 153 */\r
- pseudo_bit_t reserved2[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_bist_pcurx_wdw_0[0x00008];/* 144 */\r
- pseudo_bit_t reserved3[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_bist_pcurx_wdw_1[0x00008];/* 145 */\r
- pseudo_bit_t reserved4[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_bist_pcurx_wdw_2[0x00008];/* 145 */\r
- pseudo_bit_t reserved5[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nsi_bist_pcurx_wdw_3[0x00008];/* 145 */\r
- pseudo_bit_t reserved6[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rep_arrays_stat[0x00007];\r
- pseudo_bit_t reserved7[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bists_stat[0x00004];\r
- pseudo_bit_t reserved8[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nonrep_arrays_stat[0x00006];\r
- pseudo_bit_t reserved9[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved10[0x00040];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Those register hold the credits ( one credit - 128 bit ) to the NSI fifos in the send side.\r
- Defalt value are OK.\r
- HardWare change those register all the time.\r
- If because of a bug those registers need to be changed it should be done before some one accessed NSI !!! */\r
-\r
-struct ns_vl_hexcreds_st { /* Little Endian */\r
- pseudo_bit_t hexcred_p[0x00005];\r
- pseudo_bit_t reserved0[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t hexcred_nonp[0x00005];\r
- pseudo_bit_t reserved1[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t hexcred_res[0x00005];\r
- pseudo_bit_t reserved2[0x0001b];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* NSwitch Agent Credits */\r
-\r
-struct ns_creds_ntu_st { /* Little Endian */\r
- pseudo_bit_t cred_p[0x00004];\r
- pseudo_bit_t reserved0[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cred_nonp[0x00004];\r
- pseudo_bit_t reserved1[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cred_res[0x00004];\r
- pseudo_bit_t reserved2[0x0001c];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* NSwitch Agent Credits */\r
-\r
-struct ns_creds_pcu_st { /* Little Endian */\r
- pseudo_bit_t cred_p[0x00004];\r
- pseudo_bit_t reserved0[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cred_nonp[0x00004];\r
- pseudo_bit_t reserved1[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cred_res[0x00004];\r
- pseudo_bit_t reserved2[0x0001c];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* NSwitch Agent Credits */\r
-\r
-struct ns_creds_dmu_st { /* Little Endian */\r
- pseudo_bit_t cred_p[0x00004];\r
- pseudo_bit_t reserved0[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cred_nonp[0x00004];\r
- pseudo_bit_t reserved1[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t cred_res[0x00004];\r
- pseudo_bit_t reserved2[0x0001c];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* CR Space Base Address Register */\r
-\r
-struct mem_bar_st { /* Little Endian */\r
- pseudo_bit_t bar_msms[0x00020]; /* CR space address lsbs */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t size[0x00006]; /* CR space address space BASE = BAR.\r
- CR space address sapce LIMIT = BAR + ( 2 ^ size )\r
- Any address the is BASE <= address <= LIMIT will go to CR space */\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t enable[0x00001]; /* Enable bit for all this address decoder */\r
- pseudo_bit_t reserved1[0x0000c];\r
- pseudo_bit_t bar_lsbs[0x0000c]; /* CR space address msbs */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @nsi_nonp_cfg */\r
-\r
-struct nsi_nonp_cfg_st { /* Little Endian */\r
- pseudo_bit_t vl[0x00001];\r
- pseudo_bit_t io_mem[0x00001]; /* This bit controls the io_mem bit in the Nswitch read response header. */\r
- pseudo_bit_t return_deadbeef[0x00001];/* When set read responses will return with data phases of ffffffff.....\r
- When clear returns read responses header only - In this configuration the Syndrom must be set to error - other wise the chip will get stuck !!! */\r
- pseudo_bit_t reserved0[0x00005];\r
- pseudo_bit_t syndorm[0x00008]; /* This syndrom will be returned in the read response packet - check Nswitch spec for those values. */\r
- pseudo_bit_t reserved1[0x00010];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* FW Scratch Pad */\r
-\r
-struct SCRPAD_st { /* Little Endian */\r
- struct MSIX_st msix;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t word[42][0x00020]; /* instead of RESERVED */\r
-/* --------------------------------------------------------- */\r
- struct Transport_and_CI_Error_Counters_st error_counters;/* Transport and CI error counters */\r
-/* --------------------------------------------------------- */\r
- struct GUID_INFO_st guid_info; /* GUID_INFO holding node,port1 and port2 GUIDs */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00060];\r
-/* --------------------------------------------------------- */\r
- struct SPDH_st spd[4]; /* SPD info from DDR DIMMS (part of boot2?) */\r
-/* --------------------------------------------------------- */\r
- struct FW_TRACE_st fw_trace; /* FW_TRACE params */\r
-/* --------------------------------------------------------- */\r
- struct FW_VERSION_st fw_version; /* FW Version */\r
-/* --------------------------------------------------------- */\r
- struct INIT_HCA_st init_hca; /* INIT_HCA params */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00100];\r
-/* --------------------------------------------------------- */\r
- struct EQN_MAP_st eqn_map;\r
-/* --------------------------------------------------------- */\r
- struct BOOT2_SCRPAD_st boot2;\r
-/* --------------------------------------------------------- */\r
- struct TPT_SCRPAD_st tpt;\r
-/* --------------------------------------------------------- */\r
- struct NTU_SCRPAD_st ntu;\r
-/* --------------------------------------------------------- */\r
- struct QPC_SCRPAD_st qpc;\r
-/* --------------------------------------------------------- */\r
- struct TCU_SCRPAD_st tcu;\r
-/* --------------------------------------------------------- */\r
- struct EXUS_SCRPAD_st exus;\r
-/* --------------------------------------------------------- */\r
- struct EXUR_SCRPAD_st exur;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TPT BIST */\r
-\r
-struct tpt_bist_st { /* Little Endian */\r
- pseudo_bit_t tpt_rw26bist_wdw_0[0x00005];/* 138 */\r
- pseudo_bit_t reserved0[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_rw26bist_wdw_1[0x00005];/* 138 */\r
- pseudo_bit_t reserved1[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_rw26bist_wdw_2[0x00005];/* 138 */\r
- pseudo_bit_t reserved2[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_rw26bist_wdw_3[0x00005];/* 138 */\r
- pseudo_bit_t reserved3[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_rw112_bist_way0l_rdw_0[0x00007];/* 157 */\r
- pseudo_bit_t reserved4[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_rw112_bist_way0m_rdw_0[0x00007];/* 157 */\r
- pseudo_bit_t reserved5[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_rw112_bist_way1l_rdw_0[0x00007];/* 157 */\r
- pseudo_bit_t reserved6[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_rw112_bist_way1m_rdw_0[0x00007];/* 157 */\r
- pseudo_bit_t reserved7[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_rw112_bist_way2l_rdw_0[0x00007];/* 157 */\r
- pseudo_bit_t reserved8[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_rw112_bist_way2m_rdw_0[0x00007];/* 157 */\r
- pseudo_bit_t reserved9[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_rw112_bist_way3l_rdw_0[0x00007];/* 157 */\r
- pseudo_bit_t reserved10[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_rw112_bist_way3m_rdw_0[0x00007];/* 157 */\r
- pseudo_bit_t reserved11[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_xl68_bist_way_0_rdw_0[0x00007];/* 157 */\r
- pseudo_bit_t reserved12[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_xl68_bist_way_0_rdw_1[0x00007];/* 157 */\r
- pseudo_bit_t reserved13[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_xl68_bist_way_1_rdw_0[0x00007];/* 158 */\r
- pseudo_bit_t reserved14[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_xl68_bist_way_1_rdw_1[0x00007];/* 158 */\r
- pseudo_bit_t reserved15[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_xl68_bist_way_2_rdw_0[0x00007];/* 158 */\r
- pseudo_bit_t reserved16[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_xl68_bist_way_2_rdw_1[0x00007];/* 158 */\r
- pseudo_bit_t reserved17[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_xl68_bist_way_3_rdw_0[0x00007];/* 158 */\r
- pseudo_bit_t reserved18[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_xl68_bist_way_3_rdw_1[0x00007];/* 158 */\r
- pseudo_bit_t reserved19[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_array_bist_rdw_0[0x00006];/* 145 */\r
- pseudo_bit_t reserved20[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist2waydata_data_rdw_0[0x00006];/* 158 */\r
- pseudo_bit_t reserved21[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist2waydata_data_rdw_1[0x00006];/* 158 */\r
- pseudo_bit_t reserved22[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist2waydata_code_rdw_0[0x00006];/* 158 */\r
- pseudo_bit_t reserved23[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ir_bist2waydata_code_rdw_1[0x00006];/* 158 */\r
- pseudo_bit_t reserved24[0x0001a];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rep_arrays_stat[0x00019];\r
- pseudo_bit_t reserved25[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bists_stat[0x00017];\r
- pseudo_bit_t reserved26[0x00009];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nonrep_arrays_stat[0x00011];\r
- pseudo_bit_t reserved27[0x0000f];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved28[0x00c80];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TPT NSI Gateway */\r
-\r
-struct TPTNSIGW_st { /* Little Endian */\r
- struct NSIGWCTRL_st nsigw_ctrl;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00060];\r
-/* --------------------------------------------------------- */\r
- struct NSIGWEXTCTRL_st nsi_gateway_ext_control;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00080];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t crl_fsm[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x005e0];\r
-/* --------------------------------------------------------- */\r
- struct NSIGWRAM_st nsi_gateway_ram;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Event Queues Cause Register */\r
-\r
-struct ECR_st { /* Little Endian */\r
- pseudo_bit_t ecr_63_32_[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ecr_31_0_[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ecr_clear_63_32_[0x00020];/* bits set when writing to this register results in corresponding bits in ecr[63:32] being cleared. bits not set are not changed in ecr[63:32]. reading this register returns undefined value. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ecr_clear_31_0_[0x00020];/* bits set when writing to this register results in corresponding bits in ecr[31:0] being cleared. bits not set are not changed in ecr[31:0]. reading this register returns undefined value. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ecr_set_63_32_[0x00020];/* bits set when writing to this register results in corresponding bits in ecr[63:32] being set. bits not set are not changed in ecr[63:32]. reading this register returns undefined value. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ecr_set_31_0_[0x00020];/* bits set when writing to this register results in corresponding bits in ecr[31:0] being set. bits not set are not changed in ecr[31:0]. reading this register returns undefined value. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00040];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* HCA Command Interface */\r
-\r
-struct HCACMDIFACE_st { /* Little Endian */\r
- pseudo_bit_t in_param_h[0x00020]; /* Input parameter[63:32] / pointer to mailbox. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t in_param_l[0x00020]; /* Input parameter[31:0] / pointer to mailbox. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t input_modifier[0x00020];/* Command interface input modifier */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t out_param_h[0x00020]; /* Output parameter [63:32] / output mailbox pointer */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t out_param_l[0x00020]; /* Output parameter [31:0] / output mailbox pointer */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00010];\r
- pseudo_bit_t token[0x00010]; /* Software assigned token to the command */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t opcode[0x0000c]; /* Command opcode */\r
- pseudo_bit_t opcode_modifier[0x00004];/* Command opcode modifier */\r
- pseudo_bit_t reserved1[0x00006];\r
- pseudo_bit_t e[0x00001]; /* Event required */\r
- pseudo_bit_t go[0x00001]; /* Go - set this bit to execute the command\r
- 1 - HW ownership of the HCR\r
- 0 - SW ownership of the HCR\r
- */\r
- pseudo_bit_t status[0x00008]; /* Command execution status\r
- 0 = success */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Cause Registers */\r
-\r
-struct TPT_CAUSEREG_st { /* Little Endian */\r
- pseudo_bit_t tp_crtimeout_occured[0x00001];\r
- pseudo_bit_t tpt_pipe0[0x00001];\r
- pseudo_bit_t tpt_pipe1[0x00001];\r
- pseudo_bit_t tpt_pipe2[0x00001];\r
- pseudo_bit_t tpt_pipe3[0x00001];\r
- pseudo_bit_t tpt_pipe4[0x00001];\r
- pseudo_bit_t xl_perr[0x00001];\r
- pseudo_bit_t rw_perr[0x00001];\r
- pseudo_bit_t irisc_nsw_error[0x00001];\r
- pseudo_bit_t reserved0[0x00017];\r
-/* --------------------------------------------------------- */\r
- struct EXT_CAUSEREG_st extended_cause;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* TPT Cache Gateway */\r
-\r
-struct TPTGW_st { /* Little Endian */\r
- struct TPTGW_CTRL_st tptgwctrl;\r
-/* --------------------------------------------------------- */\r
- struct TPTGW_DATA_st tptgwdata;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Transport and Completion Unit (TCU) */\r
-\r
-struct TCU_st { /* Little Endian */\r
- struct IRisc_st irisc; /* Interrupt Routing:\r
- ----------------------------\r
- 0 missaligned access\r
- 1 code bp\r
- 2 data bp\r
- 3 trap\r
-\r
- 4 ipc\r
- 5 ccm\r
- 6 dcm\r
- 7 pcnt0\r
- 8 pcnt1\r
-\r
- 9 tpterr - Request from translation from TPT failed.\r
- 10 nswnak - non posted write to NSW failed.\r
- 11 entint, e.g. NAK\r
- 12 cqerror - cq does not exist\r
- 13 cqlock - CQC entry is locked for reading. Retry counter exceeded.\r
- 14 cqbp - CQ BreakPoint\r
- 15 cqoverfl - CQ overflow\r
- 16 ldberr - syndrome read from LDB != ok\r
- 17 wrppb - warparound / page boundary\r
- 18 i1rde_gpint0 - top of RDE fifo detected error\r
- 19 i1rde_gpint1 - RDE finished TPT flush mechanism.\r
- 20 i1rde_gpint2 - general purpose register from RDE\r
- 21 i1rde_gpint3 - general purpose register from RDE\r
- 23 excp - packet received with bp (error, trap, qp0 etc.)\r
- 24 digw - busy bit released of dispatcher\r
- 25 qpcgw - qpc gw busy bit released\r
- 26 drppkt - counter of dropped packets reached 0xffffffff (and wrapped around)\r
-\r
- 31 timer\r
- */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00800];\r
-/* --------------------------------------------------------- */\r
- struct RAW_st raweth; /* RAW BTH and DETH for Ethertype */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00100];\r
-/* --------------------------------------------------------- */\r
- struct RAW_st rawipv6; /* RAW BTH and DETH for IPV6 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00100];\r
-/* --------------------------------------------------------- */\r
- struct ROUTERMODE_st routermode; /* router mode cfg data. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00b00];\r
-/* --------------------------------------------------------- */\r
- struct OPCODEMASKS_st opcodemasks; /* Opcode Masks - Drop and Trap */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00100];\r
-/* --------------------------------------------------------- */\r
- struct EXCEPTIONMASKS_st exceptionmasks;/* TCU Exception Masks - Ignore, Drop and Trap */\r
-/* --------------------------------------------------------- */\r
- struct TCUCHKCAUSE_st tcuchkcause; /* checker cause registers */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00080];\r
-/* --------------------------------------------------------- */\r
- struct TCUGRLCFG_st tcugrlcfg; /* tcu general cfg */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x00800];\r
-/* --------------------------------------------------------- */\r
- struct TCUTCHEADER_st tcutcheader;\r
-/* --------------------------------------------------------- */\r
- struct TCUTCQPC_st tcutcqpcrd; /* tcu data that was sampled from QPC */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x00080];\r
-/* --------------------------------------------------------- */\r
- struct MGIDTABLE_st mgidtable;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x02000];\r
-/* --------------------------------------------------------- */\r
- struct QPCGW_st tcuqpcgw;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved9[0x00180];\r
-/* --------------------------------------------------------- */\r
- struct TCUPKTMV_st tcupktmv; /* irisc order for what to do with packet with excetion vector not null */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved10[0x00040];\r
-/* --------------------------------------------------------- */\r
- struct TCUTCGW_st tcutcgw; /* tcu tc gate way for sending packets from exception buffer to CLI or to RDE */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved11[0x00400];\r
-/* --------------------------------------------------------- */\r
- struct TCUMCCache_st mccache;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved12[0x00800];\r
-/* --------------------------------------------------------- */\r
- struct CECFG_st completionenginecfg;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved13[0x00800];\r
-/* --------------------------------------------------------- */\r
- struct PKEYTABLE_st pkeytable;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved14[0x01000];\r
-/* --------------------------------------------------------- */\r
- struct TCU_CAUSEREG_st tcucause; /* Cause Bits:\r
- 31:5 - reserved\r
- 4 - ir_nsw_error\r
- 3 - tcu_crtimeout_occurred\r
- 2 - ce_parity_error\r
- 1 - eb_parity_error\r
- 0 - pb_parity_error */\r
-/* --------------------------------------------------------- */\r
- struct FENCE_st tcufence; /* Fence for the transport checks. incount is incremented for every packet received from cli. outcount is incremented for every packet dropped or handed over to the rde.\r
-\r
- * This feature does not work, see bug 4982 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tcufence_outincred[0x00020];/* Increment Output Counter from CrSpace\r
-\r
- * This feature does not work, see bug 4982 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved15[0x00060];\r
-/* --------------------------------------------------------- */\r
- struct CEFENCE_st cefence; /* Fence for the completion engine. incount is incremented for every entry pushed in the input fifo. outcount is incremented for every entry that has finished processing at the completion engine.\r
-\r
- * This feature does not work see bug 4961 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved16[0x00580];\r
-/* --------------------------------------------------------- */\r
- struct TCUTCDEBUG_st tcutcdebug; /* TCU TC debug */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved17[0x00600];\r
-/* --------------------------------------------------------- */\r
- struct TCU_BIST_st tcu_bist;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved18[0x00bc0];\r
-/* --------------------------------------------------------- */\r
- struct TCUEBCTL_st tcuebctl; /* tcu exception buffer read/write pointers */\r
-/* --------------------------------------------------------- */\r
- struct TCUEB_st tcueb;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved19[0x08000];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Execution Engines Unit (EXU) */\r
-\r
-struct EXU_st { /* Little Endian */\r
- struct IRisc_st irisc0; /* Interrupt Routing:\r
- ----------------------------\r
- 0 missaligned access\r
- 1 code bp\r
- 2 data bp\r
- 3 trap\r
-\r
- 4 ipc\r
- 5 ccm\r
- 6 dcm\r
- 7 pcnt0\r
- 8 pcnt1\r
-\r
- 9 sdb - send qp doorbell (FIFO not empty)\r
- 10 exus - Execution unit halted\r
- 11 rdb - receive qp doorbell (FIFO not empty)\r
- 12 qpcgw0 - qpc gw 0 busy bit released\r
- 13 qpcgw1 - qpc gw 1 busy bit released\r
- 14 eeddb - ee disconnect DB (FIFO not empty)\r
-\r
- 18 i1sde_gpint0 - general purpose int pin from SDE\r
- 19 i1sde_gpint1 - general purpose int pin from SDE\r
- 20 i1sde_gpint2 - general purpose int pin from SDE\r
- 21 i1sde_gpint3 - general purpose int pin from SDE\r
-\r
- 31 timer\r
- */\r
-/* --------------------------------------------------------- */\r
- struct IRisc_st irisc1; /* Interrupt Routing:\r
- ----------------------------\r
- 0 missaligned access\r
- 1 code bp\r
- 2 data bp\r
- 3 trap\r
-\r
- 4 ipc\r
- 5 ccm\r
- 6 dcm\r
- 7 pcnt0\r
- 8 pcnt1\r
-\r
- 9 sdb - send qp doorbell (FIFO not empty)\r
- 10 exus - Execution unit halted\r
- 11 rdb - receive qp doorbell (FIFO not empty)\r
- 12 qpcgw0 - qpc gw 0 busy bit released\r
- 13 qpcgw1 - qpc gw 1 busy bit released\r
- 14 eeddb - ee disconnect DB (FIFO not empty)\r
-\r
- 18 i1sde_gpint0 - general purpose int pin from SDE\r
- 19 i1sde_gpint1 - general purpose int pin from SDE\r
- 20 i1sde_gpint2 - general purpose int pin from SDE\r
- 21 i1sde_gpint3 - general purpose int pin from SDE\r
-\r
- 31 timer\r
- */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00800];\r
-/* --------------------------------------------------------- */\r
- struct RCVDB_RDBPARAMS_st rcvdb_rdbparams;/* Base Address is only 63:32 -\r
- baseaddress[31:0] is reserved\r
-\r
- A copy of this table is held in the RDE. It is up to config sw to keep them equal. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00080];\r
-/* --------------------------------------------------------- */\r
- struct MEMACCESSPARAMS_st avtableparams;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00080];\r
-/* --------------------------------------------------------- */\r
- struct EXEOPCODEBP_st opcodebp; /* when corresponding bit is set, execution engine stops upon detection of opcode */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x005c0];\r
-/* --------------------------------------------------------- */\r
- struct QPCGW_st exuqpcgw0;\r
-/* --------------------------------------------------------- */\r
- struct QPCGW_st exuqpcgw1;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x01000];\r
-/* --------------------------------------------------------- */\r
- struct EXE_SEMAPHORES_st semaphores;/* Exe general purpose semaphores */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00700];\r
-/* --------------------------------------------------------- */\r
- struct EXU_BIST_st exu_bist;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x01c00];\r
-/* --------------------------------------------------------- */\r
- struct EXEEVENT_st exeevent; /* Any bit set will cause interrupt in the corresponding exuirisc if mask bit is set (see engiriscXena) */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x00080];\r
-/* --------------------------------------------------------- */\r
- struct EXEENGIRISCMASK_st engirisc0ena;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x00080];\r
-/* --------------------------------------------------------- */\r
- struct EXEENGIRISCMASK_st engirisc1ena;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved9[0x00d80];\r
-/* --------------------------------------------------------- */\r
- struct EXTDB_st extdb; /* External Doorbells Control */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved10[0x00740];\r
-/* --------------------------------------------------------- */\r
- struct INTDB_st intdb; /* Internal Doorbells Control */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved11[0x00080];\r
-/* --------------------------------------------------------- */\r
- struct RDEEDISCFIFO_st rdeediscfifo;/* fifo with end to end contexts whose last message has been completed. iRisc pops this fifo and disconnects qp from the ee in question. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved12[0x000c0];\r
-/* --------------------------------------------------------- */\r
- struct TPTNSIIF_st fetchertptnsiif;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved13[0x000e0];\r
-/* --------------------------------------------------------- */\r
- struct DESCFIFOGW_st exudesc;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved14[0x00300];\r
-/* --------------------------------------------------------- */\r
- struct EXE_CAUSEREG_st exucause; /* Cause bits:\r
- 31:3 - reserved\r
- 2 - CRBus Timeout\r
- 1 - IRISC 1 Error\r
- 0 - IRISC 0 Error */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved15[0x00100];\r
-/* --------------------------------------------------------- */\r
- struct EXEARB_st exearb; /* Arbiter properties */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved16[0x00100];\r
-/* --------------------------------------------------------- */\r
- struct EXUGRLCFG_st exugrlcfg;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved17[0x00200];\r
-/* --------------------------------------------------------- */\r
- struct PKEYTABLE_st pkeytable;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved18[0x01000];\r
-/* --------------------------------------------------------- */\r
- struct EXE_MGIDTABLE_st mgidtable;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved19[0x02000];\r
-/* --------------------------------------------------------- */\r
- struct EXENGINE_st exu[16];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved20[0x08000];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Receive Data Engine (RDE) */\r
-\r
-struct RDE_st { /* Little Endian */\r
- struct RDEGW_st rdegw; /* LINE 0\r
- ------------------------------------\r
- 63:56 IB OpCode\r
- 55:32 PSN\r
- 31 AckReq\r
- 28:24 CQPC index\r
- 23 SE\r
- 19:12 RDB wptr\r
- 11 RDB wptr wrap\r
- 10 GRH bit\r
- 9 Signalled Completion\r
- 8 Event Request\r
- 7:0 Error Syndrome\r
- ------------------------------------\r
- LINE 1\r
- ------------------------------------\r
- 63:32 ReadReq:dmalen\r
- Req/w/immdt:ImmediateData\r
- 31:0 Responder:Rkey/DescriptorPTR\r
- 23:0 Requester:DQP for Requester EE\r
- ------------------------------------\r
- LINE 2\r
- ------------------------------------\r
- 63:0 ReadReq/Atomicreq:VA\r
- 31:0 Send/Write/ReadResp:Length Committed\r
- ------------------------------------\r
- LINE 3\r
- ------------------------------------\r
- 63:0 Atomic:Atomic Reply Data of AtomicREQ\r
- 63 DoorBell counter was decremented\r
- 62:56 DLID path bits\r
- 55:32 Source QP\r
- 31:28 SL\r
- 15:0 SLID\r
- ------------------------------------\r
- LINE 4\r
- ------------------------------------\r
- 23:0 CQ number\r
- ------------------------------------\r
- LINE 5\r
- ------------------------------------\r
- 63:56 RDB Base LSB + MTU\r
- 55:32 DQP for Responder EE\r
- 24 `1' when opcode[7:5]=="010" (RD service)\r
- 23:0 QP/EE number\r
- ==================================================\r
- CQPC Constants\r
- ------------------------------------\r
- 124 NSVL\r
- 123 NonPosted\r
- 122 EventEn\r
- 121 SignalledCompletion\r
- 120 XlationEN\r
- 119:117 MaxReadAtom\r
- 116:112 MaxMsgSize\r
- 111:88 PD\r
- 87:64 CQ\r
- 63:32 Descriptor L_key\r
- 31:0 Descriptor BAR\r
- ==================================================\r
- CQPC r256length\r
- ------------------------------------\r
- 127:104 256bytes Length Committed\r
- 95:64 Write R_key\r
- 63:0 Write VA\r
- ==================================================\r
- CQPC RDB_and_more\r
- ------------------------------------\r
- 121:120 Tag MSB (Requester_Responder#,QP/EE) (READ ONLY)\r
- 119:96 QP/EE number (READ ONLY)\r
- 95:88 RDB read Pointer\r
- 87:80 RDB write Pointer\r
- 79:64 ScatterList Pointer\r
- 63 Freed Entry\r
- 62 Allocated Entry\r
- 61 Locked Entry\r
- 60 Valid Entry\r
- 59 Hold Relock Entry\r
- 57 Descriptor is Inflight (from Memory)\r
- 56 Descriptor is Inside\r
- 55:32 DQP for Responder EE\r
- 31:5 RDB base\r
- 3 LastPushPOP#\r
- 2:0 MTU\r
- ==================================================\r
- Requester ScatterList\r
- ------------------------------------\r
- 145 RESERVED\r
- 144 Entry is Last\r
- 143:128 Next ScatterList Pointer (linklist) (READ ONLY)\r
- 127:96 Entry Length\r
- 95:64 Entry L_key\r
- 63:0 Entry VA\r
- ==================================================\r
- Responder ScatterList\r
- ------------------------------------\r
- 145 Entry Read with Error\r
- 144 Entry is Last\r
- 143:130 RESERVED\r
- 129:128 C/E bits of descriptor\r
- 127:96 Entry Length\r
- 95:64 Entry L_key\r
- 63:0 Entry VA\r
- ==================================================\r
- NDA / CDA list\r
- ------------------------------------\r
- 127:97 RESERVED\r
- 96 CDDBD\r
- 95:70 CDA\r
- 69:64 CDS\r
- 63:33 RESERVED\r
- 32 NDDBD\r
- 31:6 NDA\r
- 5:0 NDS\r
- ==================================================\r
- Syndromes\r
- syndrome[7:0] description PIPE stage\r
- ---------------------------------------------------------------------------\r
- 00000001 atomic alignment is not on 8bytes TPTINIT\r
- 00000010 RDB exceeded TPTINIT\r
- 00000100 null reached but need a descriptor TPTINIT\r
- 00001ttt TPT INIT access violation. NSINIT\r
- ttt=Xstat from TPT\r
- 001abcde a: max_msg_exceeded TPTFIN\r
- b: requester_sl_but_nodata\r
- c: requester_data_but_nosl\r
- d: responder_data_but_nosl\r
- e: NDA BusErr\r
- 01000ttt TPT FINAL access violation. ScatterEngine\r
- ttt=Xstat from TPT\r
- 01001abc a: error_buserr on descriptor ScatterEngine\r
- b: error_longlist\r
- c: error_longdata\r
- 01010000 Atomic Read/Write error ScatterEngine\r
- (nonposted Queue....)\r
- 01010001 NonPosted Write Failed ScatterEngine\r
- */\r
-/* --------------------------------------------------------- */\r
- struct CEACCESSGW_st ceaccessgw;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00e00];\r
-/* --------------------------------------------------------- */\r
- struct TPTNSIIF_st rdetptnsiif;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00760];\r
-/* --------------------------------------------------------- */\r
- struct RDEGRLCFG_st rdegrlcfg;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00080];\r
-/* --------------------------------------------------------- */\r
- struct RDECREDITS_st rdecredits;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00100];\r
-/* --------------------------------------------------------- */\r
- struct RDE_CAUSEREG_st rdecause; /* Cause Bits:\r
- 31:2 - reserved\r
- 1 - Parity Error\r
- 0 - CRBus Timeout Error */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00100];\r
-/* --------------------------------------------------------- */\r
- struct MEMACCESSPARAMS_st rdbparams;/* Base Address is only 63:32 -\r
- baseaddress[31:0] is reserved\r
-\r
- A copy of this table is held in the EXE. It is up to config sw to keep them equal. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00180];\r
-/* --------------------------------------------------------- */\r
- struct RDEDEBUG_st rde_debug_hooks; /* rde_debug_hooks */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x00400];\r
-/* --------------------------------------------------------- */\r
- struct RDE_BIST_st rde_bist; /* rde bist */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x05500];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Send Data Engine (SDE) */\r
-\r
-struct SDE_st { /* Little Endian */\r
- struct GATHERENG_st ge0;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00080];\r
-/* --------------------------------------------------------- */\r
- struct GATHERENG_st ge1;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00080];\r
-/* --------------------------------------------------------- */\r
- struct GATHERENG_st ge2;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00080];\r
-/* --------------------------------------------------------- */\r
- struct GATHERENG_st ge3;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00480];\r
-/* --------------------------------------------------------- */\r
- struct SDEGRLCFG_st sdegrlcfg;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00200];\r
-/* --------------------------------------------------------- */\r
- struct SDE_CAUSEREG_st sdecause; /* Cause Bits:\r
- 31:2 - reserved\r
- 1 - Parity Error\r
- 0 - CRBus Timeout Error */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00300];\r
-/* --------------------------------------------------------- */\r
- struct GeEuCause_st geeucause;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t exerror[0x00020]; /* errror bit per EU while gathering */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t exerror_set[0x00020]; /* set to the bits of EU error */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t exerror_rst[0x00020]; /* set to exerror */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x00ba0];\r
-/* --------------------------------------------------------- */\r
- struct SDE_BIST_st sde_bist; /* sde bist */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x05d80];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* IB Port Debug */\r
-\r
-struct port_debug_config_st { /* Little Endian */\r
- pseudo_bit_t TS1DetectDisabled[0x00001];\r
- pseudo_bit_t ZeroCredits[0x00001]; /* Zero Credits */\r
- pseudo_bit_t TransmitHold[0x00001]; /* Transmit Hold */\r
- pseudo_bit_t TransmitHoldVL15[0x00001];/* Transmit Hold VL15 */\r
- pseudo_bit_t TransmitHoldCredits[0x00001];/* Transmit Hold Credits */\r
- pseudo_bit_t IgnoreCredits[0x00001];/* Ignore Credits */\r
- pseudo_bit_t IgnoreVCRC[0x00001]; /* Ignore VCRC */\r
- pseudo_bit_t ignore_disparity[0x00001];\r
- pseudo_bit_t RBCActivityWDParam[0x00004];\r
- pseudo_bit_t rq_watchdog_disable[0x00001];\r
- pseudo_bit_t enable_skip_delay[0x00001];/* EnableSkipDelay */\r
- pseudo_bit_t debounce_debug_mode[0x00001];\r
- pseudo_bit_t ignore_training_error[0x00001];\r
- pseudo_bit_t rbc_wd_disable[0x00001];\r
- pseudo_bit_t active_wd_disable[0x00001];\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t DVCRC[0x00001];\r
- pseudo_bit_t SignalDetectDisabled[0x00001];\r
- pseudo_bit_t CommSkipWdDisable[0x00001];\r
- pseudo_bit_t reserved1[0x0000a];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Loopback Buffer Status and Drop Control */\r
-\r
-struct LBCTRL_st { /* Little Endian */\r
- pseudo_bit_t lb_full[0x00001]; /* Loopback buffer has a complete packet in it (pending delivery to TCU) */\r
- pseudo_bit_t ib_packet_in_rdy[0x00001];/* There is at least one complete IB packet in the input FIFO */\r
- pseudo_bit_t reserved0[0x0001d];\r
- pseudo_bit_t drop_loopback[0x00001];/* When a 1 is written to this field the loopback buffer is released. TCU input needs to be closed before this command is executed. */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Packet Discard Configuration Mask */\r
-\r
-struct PktDiscConfigMask_st { /* Little Endian */\r
- pseudo_bit_t LinkError[0x00001]; /* Link error mask bit */\r
- pseudo_bit_t VL15Error[0x00001]; /* VL15 error */\r
- pseudo_bit_t VLError[0x00001]; /* VL error */\r
- pseudo_bit_t DLIDError[0x00001]; /* Dlid error */\r
- pseudo_bit_t MTULenError[0x00001]; /* length is greater then the MTU or less then min length */\r
- pseudo_bit_t LenError[0x00001]; /* LRH length is different then the packet length */\r
- pseudo_bit_t LverError[0x00001]; /* lver is greater then the configured lver */\r
- pseudo_bit_t VCRCError[0x00001]; /* vcrc error */\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t reserved1[0x00001];\r
- pseudo_bit_t ICRCError[0x00001]; /* icrc error */\r
- pseudo_bit_t reserved2[0x00015];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* IB Port General Configuration */\r
-\r
-struct IB_port_general_config_st { /* Little Endian */\r
- pseudo_bit_t tq_watermark[0x00005]; /* TQ WaterMark (Max value for TQWM should be 20 see bug 5943) */\r
- pseudo_bit_t reserved0[0x00003];\r
- pseudo_bit_t tqcredits[0x00008]; /* Number of free lines in the TQ FIFO\r
- Can be programmed to a value lower than the default in order to overcome possible edge problems. Usually configured (if needed) before the port is activated. It is strongly suggested that this value is not changed during normal operation. */\r
- pseudo_bit_t reserved1[0x00008];\r
- pseudo_bit_t HOQdisable[0x00001]; /* disabling hoq timier in TQ */\r
- pseudo_bit_t LoopbackDisable[0x00001];/* a bit disabling a mechanism of loopback in clo */\r
- pseudo_bit_t reserved2[0x00002];\r
- pseudo_bit_t hoq_timer_divider[0x00004];/* HOQTimerDivider */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t brr[0x00001]; /* Bit Reorder RQ */\r
- pseudo_bit_t brt[0x00001]; /* Bit Reorder TQ */\r
- pseudo_bit_t spare_reg[0x00001]; /* cfg_ib_lb_fair_disable:\r
-\r
- Disables waited roud robin in accsessing tcu from crcore ( giving abselute priority to loopback packets)\r
-\r
- to */\r
- pseudo_bit_t sl2vl_lb_disable[0x00001];/* bit for disabling mechanism of not translating sl2vl for loopback\r
-\r
- */\r
- pseudo_bit_t reserved4[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Parallel Port Debug (per Port) */\r
-\r
-struct Parallel_Debug_Port_Configuration_st { /* Little Endian */\r
- pseudo_bit_t SerDesRX_Parallel_Port_Select[0x00004];\r
- pseudo_bit_t reserved0[0x0000c];\r
- pseudo_bit_t SerDesTX_Parallel_Port_Select[0x00004];\r
- pseudo_bit_t reserved1[0x0000c];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Flow Control update watchdog register */\r
-\r
-struct Flow_Control_update_watchdog_register_st { /* Little Endian */\r
- pseudo_bit_t VL0_FC_update_WD[0x00001];\r
- pseudo_bit_t VL1_FC_update_WD[0x00001];\r
- pseudo_bit_t VL2_FC_update_WD[0x00001];\r
- pseudo_bit_t VL3_FC_update_WD[0x00001];\r
- pseudo_bit_t VL4_FC_update_WD[0x00001];\r
- pseudo_bit_t VL5_FC_update_WD[0x00001];\r
- pseudo_bit_t VL6_FC_update_WD[0x00001];\r
- pseudo_bit_t VL7_FC_update_WD[0x00001];\r
- pseudo_bit_t reserved0[0x00018];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* @IB1_BIST */\r
-\r
-struct IB1_BIST_st { /* Little Endian */\r
- pseudo_bit_t bists_stat[0x00009]; /* Automaticly add for bist */\r
- pseudo_bit_t reserved0[0x00017];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rqtq4x_bists_stat[0x00008];/* rq descriptor fifo repair control register */\r
- pseudo_bit_t reserved1[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rep_arrays_stat[0x00009];/* Automaticly add for bist */\r
- pseudo_bit_t reserved2[0x00017];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t nonrep_arrays_stat[0x0000a];/* Automaticly add for bist */\r
- pseudo_bit_t reserved3[0x00016];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ibhbistrqdscf_rdw_0[0x00005];/* Automaticly add for bist */\r
- pseudo_bit_t reserved4[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ibhbistclolbf_rdw_0[0x00007];/* Automaticly add for bist */\r
- pseudo_bit_t reserved5[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ibhbistclolbf_rdw_1[0x00007];/* Automaticly add for bist */\r
- pseudo_bit_t reserved6[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ibhbistdtf1_l_rdw_0[0x00007];/* Automaticly add for bist */\r
- pseudo_bit_t reserved7[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ibhbistdtf1_m_rdw_0[0x00007];/* Automaticly add for bist */\r
- pseudo_bit_t reserved8[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ibhbistdtf2_l_rdw_0[0x00007];/* Automaticly add for bist */\r
- pseudo_bit_t reserved9[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ibhbistdtf2_m_rdw_0[0x00007];/* Automaticly add for bist */\r
- pseudo_bit_t reserved10[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ibhbisttqdtf_wdw_0[0x00007];/* Automaticly add for bist */\r
- pseudo_bit_t reserved11[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ibhbisttqdtf_wdw_1[0x00007];/* Automaticly add for bist */\r
- pseudo_bit_t reserved12[0x00019];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved13[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* VL Mapping */\r
-\r
-struct VL_mapping_st { /* Little Endian */\r
- pseudo_bit_t vl_for_sl0[0x00004]; /* mapping of sl0 */\r
- pseudo_bit_t reserved0[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t vl_for_sl1[0x00004]; /* mapping of sl1 */\r
- pseudo_bit_t reserved2[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t vl_for_sl2[0x00004]; /* mapping sl2 */\r
- pseudo_bit_t reserved4[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t vl_for_sl3[0x00004]; /* mapping sl3 */\r
- pseudo_bit_t reserved6[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t vl_for_sl4[0x00004]; /* mapping sl4 */\r
- pseudo_bit_t reserved8[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved9[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t vl_for_sl5[0x00004]; /* mapping sl5 */\r
- pseudo_bit_t reserved10[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved11[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t vl_for_sl6[0x00004]; /* mapping sl6 */\r
- pseudo_bit_t reserved12[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved13[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t vl_for_sl7[0x00004]; /* mapping sl7 */\r
- pseudo_bit_t reserved14[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved15[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t vl_for_sl8[0x00004]; /* mapping sl8 */\r
- pseudo_bit_t reserved16[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved17[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t vl_for_sl9[0x00004]; /* mapping sl9 */\r
- pseudo_bit_t reserved18[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved19[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t vl_for_sl10[0x00004]; /* mapping sl10 */\r
- pseudo_bit_t reserved20[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved21[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t vl_for_sl11[0x00004]; /* mapping sl11 */\r
- pseudo_bit_t reserved22[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved23[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t vl_for_sl12[0x00004]; /* mapping sl12 */\r
- pseudo_bit_t reserved24[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved25[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t vl_for_sl13[0x00004]; /* mapping sl13 */\r
- pseudo_bit_t reserved26[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved27[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t vl_for_sl14[0x00004]; /* mapping sl14 */\r
- pseudo_bit_t reserved28[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved29[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t vl_for_sl15[0x00004]; /* mapping sl15 */\r
- pseudo_bit_t reserved30[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved31[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Extended Buffer Allocation Register */\r
-\r
-struct Extended_Buffer_Allocation_Register_st { /* Little Endian */\r
- pseudo_bit_t MaxDynCred_0[0x00008];\r
- pseudo_bit_t ExtMaxDynCred0[0x00001];\r
- pseudo_bit_t reserved0[0x00007];\r
- pseudo_bit_t StatCred0[0x00007];\r
- pseudo_bit_t ExtStatCred0[0x00002];\r
- pseudo_bit_t reserved1[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t UsedDyn_0[0x00008];\r
- pseudo_bit_t ExtUsedDyn0[0x00001];\r
- pseudo_bit_t reserved2[0x00007];\r
- pseudo_bit_t Used_StatCred0[0x00007];\r
- pseudo_bit_t ExtUsedStat0[0x00002];\r
- pseudo_bit_t reserved3[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t MaxDynCred_1[0x00008];\r
- pseudo_bit_t ExtMaxDynCred1[0x00001];\r
- pseudo_bit_t reserved4[0x00007];\r
- pseudo_bit_t StatCred1[0x00007];\r
- pseudo_bit_t ExtStatCred1[0x00002];\r
- pseudo_bit_t reserved5[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t UsedDyn_1[0x00008];\r
- pseudo_bit_t ExtUsedDyn1[0x00001];\r
- pseudo_bit_t reserved6[0x00007];\r
- pseudo_bit_t Used_StatCred1[0x00007];\r
- pseudo_bit_t ExtUsedStat1[0x00002];\r
- pseudo_bit_t reserved7[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t MaxDynCred_2[0x00008];\r
- pseudo_bit_t ExtMaxDynCred2[0x00001];\r
- pseudo_bit_t reserved8[0x00007];\r
- pseudo_bit_t StatCred2[0x00007];\r
- pseudo_bit_t ExtStatCred2[0x00002];\r
- pseudo_bit_t reserved9[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t UsedDyn_2[0x00008];\r
- pseudo_bit_t ExtUsedDyn2[0x00001];\r
- pseudo_bit_t reserved10[0x00007];\r
- pseudo_bit_t Used_StatCred2[0x00007];\r
- pseudo_bit_t ExtUsedStat2[0x00002];\r
- pseudo_bit_t reserved11[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t MaxDynCred_3[0x00008];\r
- pseudo_bit_t ExtMaxDynCred3[0x00001];\r
- pseudo_bit_t reserved12[0x00007];\r
- pseudo_bit_t StatCred3[0x00007];\r
- pseudo_bit_t ExtStatCred3[0x00002];\r
- pseudo_bit_t reserved13[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t UsedDyn_3[0x00008];\r
- pseudo_bit_t ExtUsedDyn3[0x00001];\r
- pseudo_bit_t reserved14[0x00007];\r
- pseudo_bit_t Used_StatCred3[0x00007];\r
- pseudo_bit_t ExtUsedStat3[0x00002];\r
- pseudo_bit_t reserved15[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t MaxDynCred_4[0x00008];\r
- pseudo_bit_t ExtMaxDynCred4[0x00001];\r
- pseudo_bit_t reserved16[0x00007];\r
- pseudo_bit_t StatCred4[0x00007];\r
- pseudo_bit_t ExtStatCred4[0x00002];\r
- pseudo_bit_t reserved17[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t UsedDyn_4[0x00008];\r
- pseudo_bit_t ExtUsedDyn4[0x00001];\r
- pseudo_bit_t reserved18[0x00007];\r
- pseudo_bit_t UsedStatCred4[0x00007];\r
- pseudo_bit_t ExtUsedStat4[0x00002];\r
- pseudo_bit_t reserved19[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t MaxDynCred_5[0x00008];\r
- pseudo_bit_t ExtMaxDynCred5[0x00001];\r
- pseudo_bit_t reserved20[0x00007];\r
- pseudo_bit_t StatCred5[0x00007];\r
- pseudo_bit_t ExtStatCred5[0x00002];\r
- pseudo_bit_t reserved21[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t UsedDyn_5[0x00008];\r
- pseudo_bit_t ExtUsedDyn5[0x00001];\r
- pseudo_bit_t reserved22[0x00007];\r
- pseudo_bit_t Used_StatCred5[0x00007];\r
- pseudo_bit_t ExtUsedStat5[0x00002];\r
- pseudo_bit_t reserved23[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t MaxDynCred_6[0x00008];\r
- pseudo_bit_t ExtMaxDynCred6[0x00001];\r
- pseudo_bit_t reserved24[0x00007];\r
- pseudo_bit_t StatCred6[0x00007];\r
- pseudo_bit_t ExtStatCred6[0x00002];\r
- pseudo_bit_t reserved25[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t UsedDyn_6[0x00008];\r
- pseudo_bit_t ExtUsedDyn6[0x00001];\r
- pseudo_bit_t reserved26[0x00007];\r
- pseudo_bit_t Used_StatCred6[0x00007];\r
- pseudo_bit_t ExtUsedStat6[0x00002];\r
- pseudo_bit_t reserved27[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t MaxDynCred_7[0x00008];\r
- pseudo_bit_t ExtMaxDynCred7[0x00001];\r
- pseudo_bit_t reserved28[0x00007];\r
- pseudo_bit_t StatCred7[0x00007];\r
- pseudo_bit_t ExtStatCred7[0x00002];\r
- pseudo_bit_t reserved29[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t UsedDyn_7[0x00008];\r
- pseudo_bit_t ExtUsedDyn7[0x00001];\r
- pseudo_bit_t reserved30[0x00007];\r
- pseudo_bit_t Used_StatCred7[0x00007];\r
- pseudo_bit_t ExtUsedStat7[0x00002];\r
- pseudo_bit_t reserved31[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved32[0x001c0];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t MaxDynCred_15[0x00008];\r
- pseudo_bit_t ExtMaxDynCred15[0x00001];\r
- pseudo_bit_t reserved33[0x00007];\r
- pseudo_bit_t StatCred15[0x00007];\r
- pseudo_bit_t ExtStatCred15[0x00002];\r
- pseudo_bit_t reserved34[0x00007];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t UsedDyn_15[0x00008];\r
- pseudo_bit_t ExtUsedDyn15[0x00001];\r
- pseudo_bit_t reserved35[0x00007];\r
- pseudo_bit_t Used_StatCred15[0x00007];\r
- pseudo_bit_t ExtUsedStat15[0x00002];\r
- pseudo_bit_t reserved36[0x00007];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* IB Port Link Phy Configuration Register */\r
-\r
-struct IB_Port_Link_Phy_Configuration_Register_st { /* Little Endian */\r
- pseudo_bit_t RxLanePolarity[0x00004];\r
- pseudo_bit_t reserved0[0x00008];\r
- pseudo_bit_t TxLanePolarity[0x00004];\r
- pseudo_bit_t reserved1[0x00008];\r
- pseudo_bit_t RxRevLanes[0x00001];\r
- pseudo_bit_t TxRevLanes[0x00001];\r
- pseudo_bit_t reserved2[0x00003];\r
- pseudo_bit_t LinkPolarity_AutoConfig[0x00001];\r
- pseudo_bit_t RxLaneRev_AutoConfig[0x00001];\r
- pseudo_bit_t TxLaneRev_AutoConfig[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t RxPolarityResult[0x00004];\r
- pseudo_bit_t reserved3[0x00014];\r
- pseudo_bit_t RxRevLanesResult[0x00001];\r
- pseudo_bit_t TxRevLanesResult[0x00001];\r
- pseudo_bit_t reserved4[0x00006];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00040];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* SerDes Configuration and Debug */\r
-\r
-struct SerDes_Configuration_and_Debug_st { /* Little Endian */\r
- pseudo_bit_t TBCMode[0x00004];\r
- pseudo_bit_t reserved0[0x00008];\r
- pseudo_bit_t FullSw[0x00004]; /* 0xF - Half Swing\r
- 0x0 - Full Swing\r
- Note: this is exactly the opposite than Anafa. */\r
- pseudo_bit_t reserved1[0x0000b];\r
- pseudo_bit_t ComDetMode[0x00001];\r
- pseudo_bit_t ComDetSel[0x00001];\r
- pseudo_bit_t EnComDet[0x00001];\r
- pseudo_bit_t TRate[0x00001];\r
- pseudo_bit_t RRate[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t TxEmp[0x00004];\r
- pseudo_bit_t reserved2[0x00008];\r
- pseudo_bit_t EnEql[0x00004];\r
- pseudo_bit_t reserved3[0x00008];\r
- pseudo_bit_t TestSel0[0x00002];\r
- pseudo_bit_t TestSel1[0x00002];\r
- pseudo_bit_t TestSel2[0x00002];\r
- pseudo_bit_t TestSel3[0x00002];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SLoop[0x00004];\r
- pseudo_bit_t reserved4[0x00008];\r
- pseudo_bit_t PLoop[0x00004];\r
- pseudo_bit_t reserved5[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t RxPwrDwn[0x00004];\r
- pseudo_bit_t reserved6[0x00008];\r
- pseudo_bit_t TxPwrDwn[0x00004];\r
- pseudo_bit_t reserved7[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SigDet[0x00004];\r
- pseudo_bit_t reserved8[0x00008];\r
- pseudo_bit_t ComDet[0x00004];\r
- pseudo_bit_t reserved9[0x00010];\r
-/* --------------------------------------------------------- */\r
- struct SERDESDFT_st sd0;\r
-/* --------------------------------------------------------- */\r
- struct SERDESDFT_st sd1;\r
-/* --------------------------------------------------------- */\r
- struct SERDESDFT_st sd2;\r
-/* --------------------------------------------------------- */\r
- struct SERDESDFT_st sd3;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Congestion Control */\r
-\r
-struct Congestion_Control_Register_st { /* Little Endian */\r
- pseudo_bit_t CongCtlTimerDivider[0x00004];/* a prescaler for congestion control counter */\r
- pseudo_bit_t reserved0[0x0000c];\r
- pseudo_bit_t VL0Enable[0x00001];\r
- pseudo_bit_t VL1Enable[0x00001]; /* enabling for cheating mode in vl1 */\r
- pseudo_bit_t VL2Enable[0x00001]; /* enabling for cheating mode in vl2 */\r
- pseudo_bit_t VL3Enable[0x00001]; /* enabling for cheating mode in vl3 */\r
- pseudo_bit_t VL4Enable[0x00001]; /* enabling for cheating mode in vl4 */\r
- pseudo_bit_t VL5Enable[0x00001]; /* enabling for cheating mode in vl5 */\r
- pseudo_bit_t VL6Enable[0x00001]; /* enabling for cheating mode in vl6 */\r
- pseudo_bit_t VL7Enable[0x00001]; /* enabling for cheating mode in vl7 */\r
- pseudo_bit_t reserved1[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CongestionTimerLimit[0x00008];/* max value for counting the time when the number of credits is less then MTU */\r
- pseudo_bit_t reserved2[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00040];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* IB Port Performance Management and Event Generation */\r
-\r
-struct IB_port_PMEG_hdr_st { /* Little Endian */\r
- struct IB_port_event_st KOZ; /* IB Port Event Cause Register */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ClearCauseReg1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SetCauseReg1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t EventServicedReg1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t EventEnable0Reg1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t EventEnable1Reg1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t PortSamplesCount[0x00020];/* PortSamples Counting Register */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SamplingCounterSelector[0x00004];/* Sampling Counter Selector */\r
- pseudo_bit_t reserved0[0x00004];\r
- pseudo_bit_t ProgFuncCounterSelector[0x00008];/* Programmable Function Counter Selector */\r
- pseudo_bit_t VLCounterMask_7_0[0x00008];/* per VL Counter Mask */\r
- pseudo_bit_t VLCounterMask_14_8[0x00007];\r
- pseudo_bit_t VLCounterMask_15[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t PortXmitData[0x00020]; /* PortXmitData Counter */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t PortRcvData[0x00020]; /* PortRcvData Counter */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t PortXmitPkts[0x00020]; /* PortXmitPkts Counter */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t PortRcvPkts[0x00020]; /* PortRcvPkts Counter */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t PortRcvErrors[0x00010];/* PortRcvErrors Counter */\r
- pseudo_bit_t reserved1[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t PortXmitDiscards[0x00010];/* PortXmitPktDiscards Counter */\r
- pseudo_bit_t reserved2[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t VL15DroppedCounter[0x00010];/* VL15Dropped */\r
- pseudo_bit_t reserved3[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t PortXmitWait[0x00020]; /* PortXMitWait Counter */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t LocalIntegrityErrors[0x00008];/* Local Integrity Errors */\r
- pseudo_bit_t reserved4[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t PortRcvRemotePhysicalErrors[0x00010];\r
- pseudo_bit_t reserved5[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t PortXmitConstraintErrors[0x00008];\r
- pseudo_bit_t reserved6[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t PortRcvConstraintErrors[0x00008];\r
- pseudo_bit_t reserved7[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SymbolErrorCounter[0x00010];/* Phy Layer Errors Counter */\r
- pseudo_bit_t reserved8[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t LinkErrorRecoveryCounter[0x00010];/* Phy Successful Recovery Counter */\r
- pseudo_bit_t LinkDownedCounter[0x00010];/* Phy Unsuccessful Recovery Counter */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ProgFuncCounter[0x00010];/* Programmable Function Counter */\r
- pseudo_bit_t reserved9[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved10[0x00040];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ExcessiveBufferOverrunErrors[0x00004];\r
- pseudo_bit_t reserved11[0x00004];\r
- pseudo_bit_t LocalLinkIntegrityErrors[0x00004];\r
- pseudo_bit_t reserved12[0x00014];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved13[0x000a0];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t PortRcvErrorsMask[0x0000a];\r
- pseudo_bit_t reserved14[0x00004];\r
- pseudo_bit_t PortRcvDataMask[0x00001];\r
- pseudo_bit_t reserved15[0x00001];\r
- pseudo_bit_t PortRcvRemotePhysicalErrorsMask[0x00002];\r
- pseudo_bit_t reserved16[0x00005];\r
- pseudo_bit_t PortXmitDiscardMask[0x00005];\r
- pseudo_bit_t PortConstraintErrorMask[0x00004];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved17[0x00040];\r
-/* --------------------------------------------------------- */\r
- struct IB_port_Event2_st IB_port_Event_Cause_Register2;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ClearCauseReg2[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t SetCauseReg2[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t EventServicedReg2[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t EventEnable0Reg2[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t EventEnable1Reg2[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* IB Link */\r
-\r
-struct ib_link_st { /* Little Endian */\r
- struct ib_link_transmit_st TXL; /* IB Port Transmit Link Configuration Register */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00020];\r
-/* --------------------------------------------------------- */\r
- struct IB_port_IO_config_st IOC; /* IB Port I/O Configuration Register */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t LinkPhyState[0x00008];\r
- pseudo_bit_t reserved1[0x00018];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Buffer Allocation */\r
-\r
-struct buffer_allocation_st { /* Little Endian */\r
- pseudo_bit_t MaxDynCred1[0x00008]; /* Max Dyn Cred 1 */\r
- pseudo_bit_t StatCred1[0x00007]; /* Stat Cred 1 */\r
- pseudo_bit_t U_1[0x00001];\r
- pseudo_bit_t MaxDynCred0[0x00008]; /* Max Dyn Cred 0 */\r
- pseudo_bit_t StatCred0[0x00007]; /* Stat Cred 0 */\r
- pseudo_bit_t U_0[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t UsedDyn1[0x00008]; /* Used Dyn Cred 1 */\r
- pseudo_bit_t UsedStat1[0x00007]; /* Used Stat Cred 1 */\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t UsedDyn0[0x00008]; /* Used Dyn Cred 0 */\r
- pseudo_bit_t UsedStat0[0x00007]; /* Used Stat Cred 0 */\r
- pseudo_bit_t reserved1[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t MaxDynCred3[0x00008]; /* Max Dyn Cred 3 */\r
- pseudo_bit_t StatCred3[0x00007]; /* Stat Cred 3 */\r
- pseudo_bit_t U_3[0x00001];\r
- pseudo_bit_t MaxDynCred2[0x00008]; /* Max Dyn Cred 2 */\r
- pseudo_bit_t StatCred2[0x00007]; /* Stat Cred 2 */\r
- pseudo_bit_t U_2[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t UsedDyn3[0x00008]; /* Used Dyn Cred 3 */\r
- pseudo_bit_t UsedStat3[0x00007]; /* Used Stat Cred 3 */\r
- pseudo_bit_t reserved2[0x00001];\r
- pseudo_bit_t UsedDyn2[0x00008]; /* Used Dyn Cred 2 */\r
- pseudo_bit_t UsedStat2[0x00007]; /* Used Stat Cred 2 */\r
- pseudo_bit_t reserved3[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t MaxDynCred5[0x00008]; /* Max Dyn Cred 5 */\r
- pseudo_bit_t StatCred5[0x00007]; /* Stat Cred 5 */\r
- pseudo_bit_t U_5[0x00001];\r
- pseudo_bit_t MaxDynCred4[0x00008]; /* Max Dyn Cred 4 */\r
- pseudo_bit_t StatCred4[0x00007]; /* Stat Cred 4 */\r
- pseudo_bit_t U_4[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t UsedDyn5[0x00008]; /* Used Dyn Cred 5 */\r
- pseudo_bit_t UsedStat5[0x00007]; /* Used Stat Cred 5 */\r
- pseudo_bit_t reserved4[0x00001];\r
- pseudo_bit_t UsedDyn4[0x00008]; /* Used Dyn Cred 4 */\r
- pseudo_bit_t UsedStat4[0x00007]; /* Used Stat Cred 4 */\r
- pseudo_bit_t reserved5[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t MaxDynCred7[0x00008]; /* Max Dyn Cred 7 */\r
- pseudo_bit_t StatCred7[0x00007]; /* Stat Cred 7 */\r
- pseudo_bit_t U_7[0x00001];\r
- pseudo_bit_t MaxDynCred6[0x00008]; /* Max Dyn Cred 6 */\r
- pseudo_bit_t StatCred6[0x00007]; /* Stat Cred 6 */\r
- pseudo_bit_t U_6[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t UsedDyn7[0x00008]; /* Used Dyn Cred 7 */\r
- pseudo_bit_t UsedStat7[0x00007]; /* Used Stat Cred 7 */\r
- pseudo_bit_t reserved6[0x00001];\r
- pseudo_bit_t UsedDyn6[0x00008]; /* Used Dyn Cred 6 */\r
- pseudo_bit_t UsedStat6[0x00007]; /* Used Stat Cred 6 */\r
- pseudo_bit_t reserved7[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x000c0];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t MaxDynCred15[0x00008]; /* Max Dyn Cred 15 */\r
- pseudo_bit_t StatCred15[0x00007]; /* Stat Cred 15 */\r
- pseudo_bit_t U_15[0x00001];\r
- pseudo_bit_t reserved9[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t UsedDyn15[0x00008]; /* Used Dyn Cred 15 */\r
- pseudo_bit_t UsedStat15[0x00007]; /* Used Stat Cred 15 */\r
- pseudo_bit_t reserved10[0x00011];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t UnallocatedDyn[0x00010];/* Unallocated Dynamic (this is how many credits are in the dynamic pool) */\r
- pseudo_bit_t BufferSize[0x00010]; /* Buffer Size */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved11[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CreditMinTime[0x0000a];/* Min Time Between Credit Packets */\r
- pseudo_bit_t CreditMaxTime[0x00008];/* Max time between credit packets */\r
- pseudo_bit_t reserved12[0x0000d];\r
- pseudo_bit_t FCU[0x00001];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved13[0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Port Status */\r
-\r
-struct Port_status_st { /* Little Endian */\r
- pseudo_bit_t RQFIFOF[0x00001]; /* RQ FIFO Full */\r
- pseudo_bit_t reserved0[0x00007];\r
- pseudo_bit_t VL0Stalled[0x00001]; /* VL0 Stalled */\r
- pseudo_bit_t VL1Stalled[0x00001]; /* VL1 Stalled */\r
- pseudo_bit_t VL2Stalled[0x00001]; /* VL2 Stalled */\r
- pseudo_bit_t VL3Stalled[0x00001]; /* VL3 Stalled */\r
- pseudo_bit_t VL4Stalled[0x00001]; /* VL4 Stalled */\r
- pseudo_bit_t VL5Stalled[0x00001]; /* VL5 Stalled */\r
- pseudo_bit_t VL6Stalled[0x00001]; /* VL6 Stalled */\r
- pseudo_bit_t VL7Stalled[0x00001]; /* VL7 Stalled */\r
- pseudo_bit_t RBCACT[0x00001]; /* RBC Active */\r
- pseudo_bit_t TS2DTCT[0x00001]; /* TS2 Detected */\r
- pseudo_bit_t SERACT[0x00001]; /* Serial Activity */\r
- pseudo_bit_t TRERR[0x00001]; /* Training Error */\r
- pseudo_bit_t IDLRCV[0x00001]; /* Idle Received */\r
- pseudo_bit_t TS1Detected[0x00001];\r
- pseudo_bit_t CommaDetectEnable[0x00001];\r
- pseudo_bit_t reserved1[0x00009];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* VL Arbitration Table */\r
-\r
-struct VL_arbitration_table_st { /* Little Endian */\r
- pseudo_bit_t WTR0C1[0x00008]; /* WeightRow0Col1 */\r
- pseudo_bit_t VLR0C1[0x00004]; /* VL */\r
- pseudo_bit_t WTR0C0[0x00008]; /* WeightRow0Col0 */\r
- pseudo_bit_t VLR0C0[0x00004]; /* VL */\r
- pseudo_bit_t reserved0[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t WTR0C3[0x00008]; /* WeightRow0Col3 */\r
- pseudo_bit_t VLR0C3[0x00004]; /* VL */\r
- pseudo_bit_t WTR0C2[0x00008]; /* WeightRow0Col2 */\r
- pseudo_bit_t VLR0C2[0x00004]; /* VL */\r
- pseudo_bit_t reserved1[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t WTR0C5[0x00008]; /* WeightRow0Col5 */\r
- pseudo_bit_t VLR0C5[0x00004]; /* VL */\r
- pseudo_bit_t WTR0C4[0x00008]; /* WeightRow0Col4 */\r
- pseudo_bit_t VLR0C4[0x00004]; /* VL */\r
- pseudo_bit_t reserved2[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t WTR0C7[0x00008]; /* WeightRow0Col7 */\r
- pseudo_bit_t VLR0C7[0x00004]; /* VL */\r
- pseudo_bit_t WTR0C6[0x00008]; /* WeightRow0Col6 */\r
- pseudo_bit_t VLR0C6[0x00004]; /* VL */\r
- pseudo_bit_t reserved3[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00080];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t WTR1C1[0x00008]; /* WeightRow1Col1 */\r
- pseudo_bit_t VLR1C1[0x00004]; /* VL */\r
- pseudo_bit_t WTR1C0[0x00008]; /* WeightRow1Col0 */\r
- pseudo_bit_t VLR1C0[0x00004]; /* VL */\r
- pseudo_bit_t reserved5[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t WTR1C3[0x00008]; /* WeightRow1Col3 */\r
- pseudo_bit_t VLR1C3[0x00004]; /* VL */\r
- pseudo_bit_t WTR1C2[0x00008]; /* WeightRow1Col2 */\r
- pseudo_bit_t VLR1C2[0x00004]; /* VL */\r
- pseudo_bit_t reserved6[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t WTR1C5[0x00008]; /* WeightRow1Col5 */\r
- pseudo_bit_t VLR1C5[0x00004]; /* VL */\r
- pseudo_bit_t WTR1C4[0x00008]; /* WeightRow1Col4 */\r
- pseudo_bit_t VLR1C4[0x00004]; /* VL */\r
- pseudo_bit_t reserved7[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t WTR1C7[0x00008]; /* WeightRow1Col7 */\r
- pseudo_bit_t VLR1C7[0x00004]; /* VL */\r
- pseudo_bit_t WTR1C6[0x00008]; /* WeightRow1Col6 */\r
- pseudo_bit_t VLR1C6[0x00004]; /* VL */\r
- pseudo_bit_t reserved8[0x00008];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved9[0x00080];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* IB PortInfo and GUIDInfo */\r
-\r
-struct IB_port_info_GUID_info_st { /* Little Endian */\r
- pseudo_bit_t MK0[0x00020]; /* M_Key */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t MK1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GIDPR0[0x00020]; /* GIDPrefix */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GIDPR1[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t MSMLID[0x00010]; /* MasterSMLID */\r
- pseudo_bit_t LID[0x00010];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CAPMSK[0x00020]; /* CapabilityMask */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t MKLP[0x00010]; /* M_KeyLeasePeriod */\r
- pseudo_bit_t DIAG[0x00010]; /* DiagCode */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t link_width_active[0x00008];/* LinkWidthActive */\r
- pseudo_bit_t link_width_supported[0x00008];/* LinkWidthSupported */\r
- pseudo_bit_t link_width_enable[0x00008];/* LinkWidthEnabled */\r
- pseudo_bit_t LPNUM[0x00008]; /* LocalPortNum */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t LSPENB[0x00004]; /* LinkSpeedEnabled */\r
- pseudo_bit_t LSPACT[0x00004]; /* LinkSpeedActive */\r
- pseudo_bit_t LMC[0x00003];\r
- pseudo_bit_t reserved0[0x00003];\r
- pseudo_bit_t MKPROT[0x00002]; /* M_KeyProtectBits */\r
- pseudo_bit_t link_down_default_state[0x00004];/* LinkDownDefaultState */\r
- pseudo_bit_t link_phy_state[0x00004];\r
- pseudo_bit_t port_state[0x00004]; /* PortState */\r
- pseudo_bit_t LSPSUP[0x00004]; /* LinkSpeedSupported */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t VLARHCAP[0x00008]; /* VLArbitrationHighCap */\r
- pseudo_bit_t VLHLIM[0x00008]; /* VLHighLimit */\r
- pseudo_bit_t reserved1[0x00004];\r
- pseudo_bit_t VLCAP[0x00004]; /* VLCap */\r
- pseudo_bit_t MSMSL[0x00004]; /* MasterSMSL */\r
- pseudo_bit_t NeighborMTU[0x00004]; /* NeighborMTU */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t FilterRawOutbound[0x00001];/* FilterRawOutbound */\r
- pseudo_bit_t FilterRawInbound[0x00001];/* FilterRawInbound */\r
- pseudo_bit_t PartEnfOutbound[0x00001];/* PartEnfOutbound */\r
- pseudo_bit_t PartEnfInbound[0x00001];/* PartEnfInbound */\r
- pseudo_bit_t OperationalVLs[0x00004];/* Operational VL */\r
- pseudo_bit_t HOQLife[0x00005]; /* HOQ Life */\r
- pseudo_bit_t VLStallCount[0x00003]; /* VLStallCount */\r
- pseudo_bit_t MTUCAP[0x00004]; /* MTUCap */\r
- pseudo_bit_t reserved2[0x00004];\r
- pseudo_bit_t VLARLCAP[0x00008]; /* VLArbitrationLowCap */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t PKVIO[0x00010]; /* P_KeyViolations */\r
- pseudo_bit_t MKVIO[0x00010]; /* M_Key_Violations */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00003];\r
- pseudo_bit_t SUBNTOUT[0x00005]; /* SubnetTimeout */\r
- pseudo_bit_t GUIDCAP[0x00008];\r
- pseudo_bit_t QKVIO[0x00010]; /* Q_KeyViolations */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t local_phy_errors_threshold[0x00008];/* local_phy_errors_threshold */\r
- pseudo_bit_t Overrun_Errors[0x00004];\r
- pseudo_bit_t reserved4[0x0000f];\r
- pseudo_bit_t RTVAL[0x00005]; /* RespTimeValue */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x00080];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* (NTU) */\r
-\r
-struct NTU_st { /* Little Endian */\r
- struct IRisc_st irisc; /* Interrupt Routing:\r
- ----------------------------\r
- 0 missaligned access\r
- 1 code bp\r
- 2 data bp\r
- 3 trap\r
-\r
- 4 ipc\r
- 5 ccm\r
- 6 dcm\r
- 7 pcnt0\r
- 8 pcnt1\r
-\r
- 9 qltm - QLT miss\r
- 10 cmpe - NTU completion with error\r
- 11 cellef - Cell exception FIFO not empty\r
- 12 halt - qlt trap and NTU halted\r
- 13 i1pc_gpint0 - general purpose register from PCU\r
- 14 i1pc_gpint1 - general purpose register from PCU\r
- 15 i1pc_gpint2 - general purpose register from PCU\r
- 16 i1pc_gpint3 - system error from PCU\r
- 17 i1cp_cfgint - got a configuration cycle in PCU\r
- 18 pcuerp - PCU has received a transaction from N-switch with ERP bit and need to be serviced\r
- 19 swgcle - from PCU - SW cycle generator busy bit released (trasn. To PCI)\r
- 21 cmdif - command interface from TPT\r
- 22 cons - YU consolidated cause register\r
- 23 vc_pci - Virtual CrSpace. Comes from the NSI\r
- 24 vc_i2c - Virtual CrSpace. Comes from YU\r
- 25 vc_cpu - Virtual CrSpace. Comes from YU\r
- 26 perf0 - performance counter for QLT\r
- 27 i1dm_clbdrft_int - calibration\r
- 28 i1dm_gpint1 - general purpose register from DMU\r
- 29 i1dm_gpint2 - general purpose register from DMU\r
- 30 i1dm_gpint3 - general purpose register from DMU\r
-\r
- 31 timer */\r
-/* --------------------------------------------------------- */\r
- struct NSWADDRDEC_st ntunswdec;\r
-/* --------------------------------------------------------- */\r
- struct NTUGENERAL_st ntugeneral;\r
-/* --------------------------------------------------------- */\r
- struct NTUQLTVALID_st ntuqltvalid;\r
-/* --------------------------------------------------------- */\r
- struct NTUFENCE_st ntu_fence; /* ntu fence */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00100];\r
-/* --------------------------------------------------------- */\r
- struct CAUSEREG_st ntucause;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00300];\r
-/* --------------------------------------------------------- */\r
- struct NTURDB_st ntuoutsbufattr0;\r
-/* --------------------------------------------------------- */\r
- struct NTURDB_st ntuoutsbufattr1;\r
-/* --------------------------------------------------------- */\r
- struct NTURDB_st ntuoutsbufattr2;\r
-/* --------------------------------------------------------- */\r
- struct NTURDB_st ntuoutsbufattr3;\r
-/* --------------------------------------------------------- */\r
- struct NTUWRB_st ntuoutsbufattr4;\r
-/* --------------------------------------------------------- */\r
- struct NTUWRB_st ntuoutsbufattr5;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00400];\r
-/* --------------------------------------------------------- */\r
- struct NTU_BIST_st ntu_bist;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00c00];\r
-/* --------------------------------------------------------- */\r
- struct NTUQLTGW_st ntuqltgw;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00600];\r
-/* --------------------------------------------------------- */\r
- struct NTUQPWGW_st ntuqpwgw;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00780];\r
-/* --------------------------------------------------------- */\r
- struct NTUDESCGW_st ntudescgw;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x00400];\r
-/* --------------------------------------------------------- */\r
- struct NTUEVENTS_st ntuevents;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x00400];\r
-/* --------------------------------------------------------- */\r
- struct NTUEXCPFIFO_st ntuexcfifo;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x00700];\r
-/* --------------------------------------------------------- */\r
- struct NTUATTRFIFO_st ntuattrfifo;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved9[0x00700];\r
-/* --------------------------------------------------------- */\r
- struct NTUERRFIFO_st ntupcuerrgw;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved10[0x00300];\r
-/* --------------------------------------------------------- */\r
- struct NTU_debug_fsm_st ntu_debug_fsm;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved11[0x08b00];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* DDR Memory Interface Unit (DMU) */\r
-\r
-struct DMU_st { /* Little Endian */\r
- struct DMUGENERALINT_st dmuigeneral;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00080];\r
-/* --------------------------------------------------------- */\r
- struct DMU_BIST_st dmu_bist;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00280];\r
-/* --------------------------------------------------------- */\r
- struct DMU_CAUSEREG_st dmucause0; /* bit 0 - Data Integrity Fifo is not empty.\r
- bit 1 - Data Integrity Fifo had overflow.\r
- bit 2 - Calibration drift indecation.\r
- bit 3 - NSB Rx port 0 error.\r
- bit 4 - NSB Rx port 1 error.\r
- bit 5 - Crslave macro error.\r
- */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00700];\r
-/* --------------------------------------------------------- */\r
- struct DMURXCONFIGINT_st dmurx0i;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x001e0];\r
-/* --------------------------------------------------------- */\r
- struct DMURXCONFIGINT_st dmurx1i;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x001e0];\r
-/* --------------------------------------------------------- */\r
- struct DMUERRORFIFO_st dmuerrfifo;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x001a0];\r
-/* --------------------------------------------------------- */\r
- struct DMUDEBUGINT_st dmudebugint;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x00180];\r
-/* --------------------------------------------------------- */\r
- struct DIMMBarMask_st dmudimm0i;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x00180];\r
-/* --------------------------------------------------------- */\r
- struct DIMMBarMask_st dmudimm1i;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x00180];\r
-/* --------------------------------------------------------- */\r
- struct DIMMBarMask_st dmudimm2i;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved9[0x00180];\r
-/* --------------------------------------------------------- */\r
- struct DIMMBarMask_st dmudimm3i;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved10[0x02180];\r
-/* --------------------------------------------------------- */\r
- struct DMUGENERALEXT_st dmudgeneral;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved11[0x00380];\r
-/* --------------------------------------------------------- */\r
- struct DMUSTATISTIC_st dmustatistics;\r
-/* --------------------------------------------------------- */\r
- struct DMURXCONFIGEXT_st dmurx0d; /* rx port configuration 1 register */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved12[0x001e0];\r
-/* --------------------------------------------------------- */\r
- struct DMURXCONFIGEXT_st dmurx1d;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved13[0x00060];\r
-/* --------------------------------------------------------- */\r
- struct dmustatus_st dmustatus; /* the status registers of the dmu */\r
-/* --------------------------------------------------------- */\r
- struct DMUDEBUGEXT_st dmudebugext;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved14[0x00080];\r
-/* --------------------------------------------------------- */\r
- struct DIMMConfig_st dmudimm0d;\r
-/* --------------------------------------------------------- */\r
- struct DIMMConfig_st dmudimm1d;\r
-/* --------------------------------------------------------- */\r
- struct DIMMConfig_st dmudimm2d;\r
-/* --------------------------------------------------------- */\r
- struct DIMMConfig_st dmudimm3d;\r
-/* --------------------------------------------------------- */\r
- struct dmu_chk_dimm_st dmu_chk_dimm;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* PCI/PCIX Interface Unit (PCU) */\r
-\r
-struct PCU_st { /* Little Endian */\r
- struct PCUGENERALEXT_st pcu_general;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x000e0];\r
-/* --------------------------------------------------------- */\r
- struct pcu_tx_st pcutx;\r
-/* --------------------------------------------------------- */\r
- struct pcu_prefetch_st pcu_prefetch;\r
-/* --------------------------------------------------------- */\r
- struct pcu_debug_st pcu_debug; /* includes internal state too. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00060];\r
-/* --------------------------------------------------------- */\r
- struct pci_arbiter_st pci_arbiter;\r
-/* --------------------------------------------------------- */\r
- struct conf_header_registers_st cfg_header_regs;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00a00];\r
-/* --------------------------------------------------------- */\r
- struct Nswitch_address_deocder_st pcu_address_decoder;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00400];\r
-/* --------------------------------------------------------- */\r
- struct cmd_out_st cmd_out;\r
-/* --------------------------------------------------------- */\r
- struct PCUSWCYCLES_st pcuswcycles;\r
-/* --------------------------------------------------------- */\r
- struct PCUCONFIGCYCLES_st pcuconfigcycles;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00380];\r
-/* --------------------------------------------------------- */\r
- struct pcu_err_log_st pcu_err_log;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00100];\r
-/* --------------------------------------------------------- */\r
- struct pcu_init_st pcu_init; /* PCU init control register */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x00180];\r
-/* --------------------------------------------------------- */\r
- struct pcu_monitor_st pcu_monitor;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x00b00];\r
-/* --------------------------------------------------------- */\r
- struct CAUSEREG_st pcucause; /* Cause bits:\r
- 31 - reserved\r
- 30 - pcix_enable - Don't use this cause bit. PCIX mode bit can be found at: /pcu0/pcu_init/pcix_en. It should not be a cause bit.\r
- 29 - Overflow in command fifo to NSW\r
- 28 - Overflow in data fifo to NSW\r
- 27 - Overflow in posted lane credits to HCA\r
- 26 - Overflow in non-posted lane credits to HCA\r
- 25 - Overflow in credits of responses HCA\r
- 24 - Changed in A-1. Now it is inb_pw_perr_hca_dmu (bug 6424) - data parity error has occurred during posted write transaction targeted to HCA or DMU.\r
- 23 - Changed in A-1. Now it is bug6010_posted_flush_cause (bug 6010) - outbound posted write was flushed due to target abort or master abort.\r
- 22 - Changed in A-1. Now it is bug5128_commit_discard_cause - discard timer expiration (relevant in PCI mode only).\r
- 21 - Changed in A-1. Now it is tran_buff_discard_entry (bug 5276 in A-1) - in\r
- dicates that split completion timeout expired and caused an entry in tranbuff to be discarded.\r
- 20 - Unexpected split completion arrived at the swcycles gate-way.\r
- 19 - Don't use this cause bit. 64-bit supported bit can be found elsewhere in crspace. It should not be a cause bit.\r
- 18 - Received-Master-Abort status bit from PCI/X master.\r
- 17 - Received-Target-Abort status bit from PCI/X master.\r
- 16 - Master-Detected-Parity-Error status bit from PCI/X master\r
- 15 - Parity-Error-Detected status bit from PCI/X master\r
- 14 - Parity-Error-Detected status bit from PCI/X target\r
- 13 - Signalled-SERR# status bit\r
- 12 - Signalled-Target-Abort from PCI/X target\r
- 11 - Received-SERR# status bit\r
- 10 - Received-Target-Abort status bit from PCI/X target\r
- 9 - Received-Master-Abort status bit from PCI/X target\r
- 8 - Master-Detected-Parity-Error status bit from PCI/X target\r
- 7 - Attribute parity error detected by PCI/X target\r
- 6 - Master-abort occurred on secondary bus (NSW) during inbound posted write\r
- 5 - Master-abort occurred on secondary bus (NSW) during inbound non-posted transaction\r
- 4 - Target-abort occurred on secondary bus (NSW) during inbound non-posted transaction, i.e. a NACK was received from HCA/DMU/NTU.\r
- 3 - Split completion was discarded by non-posted inbound engines, due to target abort or master abort on PCIX bus\r
- 2 - pcr_rd_sc_discard - Don't use this bit.\r
- 1 - Unexpected split completion arrived\r
- 0 - Split completion message error arrived\r
-\r
-\r
-\r
- */\r
-/* --------------------------------------------------------- */\r
- struct CAUSEREG_st pcu_pcix_cause; /* Cause Bits:\r
- 31:10 - reserved\r
- 9 - Overflow in posted lane sync-fifo from HCA\r
- 8 - Overflow in non-posted lane sync-fifo from HCA\r
- 7 - Overflow in response sync-fifo from HCA\r
- 6 - Overflow in response sync-fifo from DMU\r
- 5 - Overflow in response sync-fifo from NTU\r
- 4 - Not used. Always '0.\r
- 3 - cfgerr: err output of crslavet // Stuck on cr-space access\r
- 2:0 - reserved\r
- ---------\r
- PCI/X oriented cause bits:\r
- PCI (Primary) status register:\r
- 0 - master_data_perr (24)\r
- 1 - signaled_target_abort (27)\r
- 2 - recieved_target_abort (28)\r
- 3 - recieved_master_abort (29)\r
- 4 - signaled_serr (30)\r
- 5 - detected_perr (31)\r
- Bridge Secondary status register\r
- 9 - split_comp_discarded\r
- 10 - unexpected_split_comp\r
- 11 - split completion overrun\r
- 12 - split completion delayed\r
- Bridge Status Register\r
- - Primary Split completion discarded\r
- - Primary Unexpected split completion\r
- - Primary split completion overrun\r
- - Primary split completion delayed\r
- - discard timer expired (inbound, np, pci only)\r
- */\r
-/* --------------------------------------------------------- */\r
- struct PCUGENERALINT_st pcu_general_i1;\r
-/* --------------------------------------------------------- */\r
- struct PCU_BIST_st pcu_bist;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x03c80];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Miscellaneous Control Registers */\r
-\r
-struct misc_st { /* Little Endian */\r
- struct HCA_st HCA;\r
-/* --------------------------------------------------------- */\r
- struct init_and_ctrl_st INTCTL; /* Initialization and Control Register */\r
-/* --------------------------------------------------------- */\r
- struct BIST_result_st BISTR; /* BIST Result Register */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t TCLK[0x00020]; /* Time Clock Register */\r
-/* --------------------------------------------------------- */\r
- struct IB_port_clock_timer_st IBPCLKT;/* IB Port Clock Timer Register */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t TCLK2[0x00020]; /* Time Clock Register */\r
-/* --------------------------------------------------------- */\r
- struct IB_BIST_result_st BISTR2; /* IB Bist result register */\r
-/* --------------------------------------------------------- */\r
- struct prog_timers_st PRGT; /* Programmable Timers Registers */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x000e0];\r
-/* --------------------------------------------------------- */\r
- struct GPIO_st GPIO; /* GPIO Registers */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00100];\r
-/* --------------------------------------------------------- */\r
- struct encoded_intr_ctlr_regs_st EICTLR;/* Encoded Interrupt Controller Registers */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00060];\r
-/* --------------------------------------------------------- */\r
- struct serdes_general_cont_st SERGCNTRL;\r
-/* --------------------------------------------------------- */\r
- struct serdes_rsu_st RSU;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t GMON[0x00020]; /* General Monitor Register */\r
-/* --------------------------------------------------------- */\r
- struct system_monitoring_ctrl_st SMONCTL;/* System Monitoring Control Registers */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CFGVER[0x00020];\r
-/* --------------------------------------------------------- */\r
- struct par_debug_p_st ParallelDebugPort;/* Parallel Debug port */\r
-/* --------------------------------------------------------- */\r
- struct parallel_CPU_port_st PCPUP; /* Parallel CPU Port Register */\r
-/* --------------------------------------------------------- */\r
- struct serial_port_slave_st SPS; /* Serial Port Slave Registers */\r
-/* --------------------------------------------------------- */\r
- struct IBML_slave_st IBMLS; /* IB-ML Slave Registers */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x000c0];\r
-/* --------------------------------------------------------- */\r
- struct serial_port_master_st SPM; /* Serial Port Master Registers */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00080];\r
-/* --------------------------------------------------------- */\r
- struct flash_memory_st FLASH;\r
-/* --------------------------------------------------------- */\r
- struct CONSCAUSE_st consolidatedcause;\r
-/* --------------------------------------------------------- */\r
- struct cs_brk_point_st CSBRKP;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CONFBUSTO[0x00020]; /* Configuration bus timeou register */\r
-/* --------------------------------------------------------- */\r
- struct miscellaneous_cause_register_st miscellaneous_cause;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00440];\r
-/* --------------------------------------------------------- */\r
- struct cs_semaphores_st SEMAPHOR;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x00800];\r
-/* --------------------------------------------------------- */\r
- struct BIST_DEBUG_st bist_debug;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x0d580];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Local Outstanding Requests Data Base (LDB) */\r
-\r
-struct LDB_st { /* Little Endian */\r
- pseudo_bit_t ldb_qpc_token[0x00008];/* token to qpc - 8 msb bits: (slice number, ldb, 0) */\r
- pseudo_bit_t reserved0[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00018];\r
- pseudo_bit_t gp_cfg[0x00008]; /* General Purpose Configuration Register */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00040];\r
-/* --------------------------------------------------------- */\r
- struct ldb_debug_st ldb_debug; /* debug registers */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t qpc_credits[0x00005]; /* credits between LDB and SQPC */\r
- pseudo_bit_t reserved3[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t erp_stop[0x00002]; /* Stop LDB - LDB will work only with gateway. See LDB mas for details. */\r
- pseudo_bit_t reserved4[0x0001e];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ldb_credits[0x0000c]; /* credits of LDB. from 0 to the size of LinkList. */\r
- pseudo_bit_t reserved5[0x00014];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x00060];\r
-/* --------------------------------------------------------- */\r
- struct LDB_BIST_st ldb_bist;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x00180];\r
-/* --------------------------------------------------------- */\r
- struct LDBGW_st ldbgw; /* LDB Gateway */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x00300];\r
-/* --------------------------------------------------------- */\r
- struct LDB_CAUSEREG_st ldbcausereg; /* Cause Bits:\r
- 31:5 - reserved\r
- 4 - crslave_err\r
- 3 - enqueue when linklist full\r
- 2 - dequeue when linklist empty\r
- 1 - dequeue wrong number\r
- 0 - parity error */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved9[0x07700];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Queue Pairs and Completion Queues Context (QPC) */\r
-\r
-struct QPC_st { /* Little Endian */\r
- struct IRisc_st irisc; /* Interrupt Routing:\r
- ----------------------------\r
- 0 missaligned access\r
- 1 code bp\r
- 2 data bp\r
- 3 trap\r
-\r
- 4 ipc\r
- 5 ccm\r
- 6 dcm\r
- 7 pcnt0\r
- 8 pcnt1\r
-\r
- 9 sqpm - Send QPC cache miss\r
- 10 rqpm - Receive QPC cache miss\r
- 11 cqm - Completion Context cache miss\r
- 12 cqdb - CQ doorbell (FIFO not empty)\r
- 13 nsigw - nsi gw busy bit released\r
- 14 tmot - QPC timeout on a QP\r
- 17 perf0 - performance counter on SQPC\r
- 18 perf1 - performance counter on RQPC\r
- 19 perf2 - performance counter on RQPC\r
- 22 cons - consolidated cause register from YU\r
- 27 i1ldb_gpint0 - general purpose int pin from LDB\r
- 28 i1ldb_gpint1 - general purpose int pin from LDB\r
- 29 i1ldb_gpint2 - general purpose int pin from LDB\r
- 30 i1ldb_gpint3 - general purpose int pin from LDB\r
-\r
- 31 timer */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00180];\r
-/* --------------------------------------------------------- */\r
- struct CQDBFIFO_st cqdbfifo;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00240];\r
-/* --------------------------------------------------------- */\r
- struct QPC_CAUSEREG_st qpccause; /* Cause Bits:\r
- 31:8 - reserved\r
- 7 - CRSlave timeout\r
- 6 - Hit in more than one way in CQC\r
- 5 - CQC Parity Error\r
- 4 - Hit in more than one way in RQPC\r
- 3 - RQPC Parity Error\r
- 2 - Hit in more than one way in SQPC\r
- 1 - SQPC Parity Error\r
- 0 - IRISC Error */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00300];\r
-/* --------------------------------------------------------- */\r
- struct CACHEPERF_st sqpcperf;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00180];\r
-/* --------------------------------------------------------- */\r
- struct CACHEPERF_st rqpcperf;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00180];\r
-/* --------------------------------------------------------- */\r
- struct CACHEPERF_st cqcperf;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00380];\r
-/* --------------------------------------------------------- */\r
- struct QCGWS_st recieve_gws; /* Receive (Responder Flow) Context Gateways */\r
-/* --------------------------------------------------------- */\r
- struct QCGWS_st comp_gws; /* Completion Queues Context Gateways */\r
-/* --------------------------------------------------------- */\r
- struct QCGWS_st send_gws;\r
-/* --------------------------------------------------------- */\r
- struct QPCTIMERS_st send_timers;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x00300];\r
-/* --------------------------------------------------------- */\r
- struct SEND_FSM_st send_fsm;\r
-/* --------------------------------------------------------- */\r
- struct RECEIVE_FSM_st receive_fsm;\r
-/* --------------------------------------------------------- */\r
- struct COMP_FSM_st comp_fsm;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x003a0];\r
-/* --------------------------------------------------------- */\r
- struct QPCNSIGW_st qpc_nsigw;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x00800];\r
-/* --------------------------------------------------------- */\r
- struct QPCBASEADDR_st qpcbaseaddr;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved9[0x00200];\r
-/* --------------------------------------------------------- */\r
- struct QPCGRLCFG_st qpcgrlcfg;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved10[0x00380];\r
-/* --------------------------------------------------------- */\r
- struct QPC_BIST_st qpc_bist;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved11[0x00480];\r
-/* --------------------------------------------------------- */\r
- struct QPCDIRTY_st qpc_dirty;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved12[0x00b40];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* HCA North Switch Interface */\r
-\r
-struct NSI_st { /* Little Endian */\r
- pseudo_bit_t vl_arb_ap[0x00001]; /* This bit conifigures the Virtual Lanes arbiter to give absolute prairety to to some VL. If not set round roubin is done between the VLs.If set the next bit select which VL will have the Absoulte praiurety.\r
- */\r
- pseudo_bit_t which_vl_has_ap[0x00001];/* This bit configured the NSI Virtual Lane arbitrtion Mechnizime to give Absoult praiorety to one of the VLs.\r
- Default Value gives prauierty to VL 1 , the control VL.\r
- If for some reasen this will change - VL 1 will be the data VL - only then this default value need to be changed\r
- This feture ( Absolute praierty ) has an eanble bit ( vl_arb_ap ) */\r
- pseudo_bit_t disable_saf4c[0x00001];/* When set this bit diables the NSI store & forward for Nswitch cell in the send side - I have reasons to belive it does not work !! */\r
- pseudo_bit_t host_is_littel_endian[0x00001];/* When set the Atomic oparation FSMs in the NSI think that the host is little endian.\r
- This bit has an other instance in the RDE - they must be configured to same value !!!! */\r
- pseudo_bit_t one_tx[0x00001]; /* In the NSI upstream configuration this bit conigures the number of TXs that the NSI will use.\r
- When set to one life is easy but preormance suckes.\r
- When set to zero - 2 TXs are used - other registers in the NSI need to be conigured in a specil way.\r
- Those registers are cfg4nmxvl_0 & cfg4nmxl_1, theri description explanies how they should be configured.\r
- */\r
- pseudo_bit_t cr_vl[0x00001]; /* CR space read response will go one this VL */\r
- pseudo_bit_t reserved0[0x0000a];\r
- pseudo_bit_t dbarb_ap[0x00003]; /* Doorbell arbiter abosulte praierty configuration register.\r
- This arbiter arbitrates between the NTU , PCU.\r
- Values :\r
- 3'b001 : Round robin.\r
- 3'b010 : NTU has absulte prairty.\r
- 3'b100 : PCU has absulte pariorety.\r
- Dont try any hting else */\r
- pseudo_bit_t reserved1[0x00003];\r
- pseudo_bit_t rx_ap_cfg[0x00003]; /* This register configures the arbiter of the responses from the NTU,PCU & DMU.\r
- One agent will always get Absolet prairety.\r
- Values :\r
- 3'b001 : PCU has absolute pairety.\r
- 3'b010 : DMU has absolute pairety.\r
- 3'b100 : NTU has absolute pairety. */\r
- pseudo_bit_t reserved2[0x00007];\r
-/* --------------------------------------------------------- */\r
- struct nsi_nonp_cfg_st nsi_nonp_cfg;/* This register configurates all kind of values that are needed in order to return read responses to read requests to DoorBell pages. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t status_0[0x00020]; /* Debug feature */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t status_1[0x00020]; /* Debug feature */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t status_2[0x00020]; /* Debug feature */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t status_3[0x00020]; /* Debug feature */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t status_4[0x00020]; /* Debug feature */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t status_5[0x00020]; /* Debug feature */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t status_6[0x00020]; /* Debug feature */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t status_7[0x00020]; /* Debug feature */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00020];\r
-/* --------------------------------------------------------- */\r
- struct mem_bar_st crsapce; /* CR space base address & size - Those registers need to be configured with the CR address in the Tavor address space. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00040];\r
-/* --------------------------------------------------------- */\r
- struct CAUSEREG_st nsicause; /* only the fist two registers are valid :\r
- Bit 0 = CR space timeout accured.\r
- Bit 1 = Virtual CR space access. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x00200];\r
-/* --------------------------------------------------------- */\r
- struct ns_creds_dmu_st dmu_creds; /* DMU creds for posted , nonposted & responses. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x00020];\r
-/* --------------------------------------------------------- */\r
- struct ns_creds_pcu_st pcu_creds; /* PCU creds for posted , nonposted & responses. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x00160];\r
-/* --------------------------------------------------------- */\r
- struct ns_creds_ntu_st ntu_creds; /* NTU creds for posted , nonposted & responses. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved9[0x00060];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ex1dbcred[0x00008]; /* This register hold the number of credits ( credit if for one line of 16 bytes ) form the NSI to EXE Unit 1.\r
- HardWare changes this register all the time.\r
- If because of bugs this register value will need to be changed it should be in a state before HW had consumed any credits ( Before the first DoorBell )\r
- CR space access has praiorety one HW accesss. */\r
- pseudo_bit_t reserved10[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t ex2dbcred[0x00008]; /* This register hold the number of credits ( credit if for one line of 16 bytes ) form the NSI to EXE Unit 2.\r
- HardWare changes this register all the time.\r
- If because of bugs this register value will need to be changed it should be in a state before HW had consumed any credits ( Before the first DoorBell )\r
- CR space access has praiorety one HW accesss. */\r
- pseudo_bit_t reserved11[0x00018];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved12[0x00140];\r
-/* --------------------------------------------------------- */\r
- struct ns_vl_hexcreds_st ns_vl_hexcreds_0;/* Those register hold the credits ( one credit - 128 bit ) to the NSI fifos in the send side.\r
- Defalt value are OK.\r
- HardWare change those register all the time.\r
- If because of a bug those registers need to be changed it should be done before some one accessed NSI !!! */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved13[0x00120];\r
-/* --------------------------------------------------------- */\r
- struct ns_vl_hexcreds_st ns_vl_hexcreds_1;/* Those register hold the credits ( one credit - 128 bit ) to the NSI fifos in the send side.\r
- Defalt value are OK.\r
- HardWare change those register all the time.\r
- If because of a bug those registers need to be changed it should be done before some one accessed NSI !!! */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved14[0x000a0];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved15[0x00018];\r
- pseudo_bit_t gp_cfg[0x00008]; /* General Purpose Configuration Register */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved16[0x000e0];\r
-/* --------------------------------------------------------- */\r
- struct nsi_bist_st nsi_bist;\r
-/* --------------------------------------------------------- */\r
- struct CRGW_st crgw; /* Virtual CR space access mechanizem.\r
- */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved17[0x00140];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Translation and Protection Table (TPT) */\r
-\r
-struct TPT_st { /* Little Endian */\r
- struct IRisc_st irisc; /* Interrupt Routing:\r
- ----------------------------\r
- 0 missaligned access\r
- 1 code bp\r
- 2 data bp\r
- 3 trap\r
-\r
- 4 ipc\r
- 5 ccm\r
- 6 dcm\r
- 7 pcnt0\r
- 8 pcnt1\r
-\r
- 9 tptm - Region / Translation cache miss\r
- 10 tptfl - RDE, SDE, EXE, CE "finished tpt translation requests and all nsi requests from these translations" - and logic of these 4 units inputs\r
- 11 bind - Bind request (Bind FIFO not empty)\r
- 12 nsigw - nsi gw busy bit released\r
- 13 i1pc_gpint0 - general purpose register from PCU\r
- 14 i1pc_gpint1 - general purpose register from PCU\r
- 15 i1pc_gpint2 - general purpose register from PCU\r
- 16 i1pc_gpint3 - system error from PCU\r
- 17 i1cp_cfgint - configuration cycle (See also NTU cause register)\r
- 18 pcuerp - PCU has received a transaction from N-switch with ERP bit and need to be serviced\r
- 19 swgcle - from PCU - SW cycle generator busy bit released (trasn. To PCI)\r
- 21 cmdif - Command interface\r
- 22 cons - YU Consolidated cause register, e.g. gpio, virtual crspace.\r
- 23 vc_pci - Virtual CrSpace. Comes from the NSI\r
- 24 vc_i2c - Virtual CrSpace. Comes from YU\r
- 25 vc_cpu - Virtual CrSpace. Comes from YU\r
- 26 perf0 - performance counter for TPT cache\r
- 27 i1dm_clbdrft_int- calibration\r
- 28 i1dm_gpint1 - general purpose register from DMU\r
- 29 i1dm_gpint2 - general purpose register from DMU\r
- 30 i1dm_gpint3 - general purpose register from DMU\r
-\r
- 31 timer */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_cfg_tptenabled[0x00001];/* TPT modes :\r
- 1 - TPT Defualt mode - all TPT functnalty is done.\r
- 0 - TPT Disabled mode - TPT does only :\r
- Nswitch address decoding ( Calcolating nsq bits )\r
- Page size crossing logic\r
- It does not do Virtual to Phsical address transaltion & does not check all the access rightes. */\r
- pseudo_bit_t tpt_cfg_len_msb_ptr[0x00001];/* MAS 3.3.2\r
- When set the high 32 bits of the region lenght ignored by hardware. In that case those bits can be used for other perpuse ( e.g write your name - if you can write it in hex , or write the pointer to the page table of this region ) */\r
- pseudo_bit_t reserved0[0x00006];\r
- pseudo_bit_t tpt_cfg_xlcache_conf[0x00004];/* When accessing the transaltion cache one need to select the index & tag bits from this vector\r
- {Virtual address[63:12] , Lkey[31:0] } This register selects which values go into the tag & which go into the index.\r
- always @ ( tpt_cfg_xlcache_conf or req_va_page_align or srw_entry_lkey)\r
- case(tpt_cfg_xlcache_conf)\r
- 4'h0 : begin\r
- xl_cache_index_pre = { srw_entry_lkey[ 7:0]};\r
- xl_cache_tag_pre = {req_va_page_align[51: 0],srw_entry_lkey[31:8]};\r
- end\r
- 4'h1 : begin\r
- xl_cache_index_pre = {req_va_page_align[ 0],srw_entry_lkey[ 6:0]};\r
- xl_cache_tag_pre = {req_va_page_align[51: 1],srw_entry_lkey[31:7]};\r
- end\r
- 4'h2 : begin\r
- xl_cache_index_pre = {req_va_page_align[ 1: 0],srw_entry_lkey[ 5:0]};\r
- xl_cache_tag_pre = {req_va_page_align[51: 2],srw_entry_lkey[31:6]};\r
- end\r
- 4'h3 : begin\r
- xl_cache_index_pre = {req_va_page_align[ 2: 0],srw_entry_lkey[ 4:0]};\r
- xl_cache_tag_pre = {req_va_page_align[51: 3],srw_entry_lkey[31:5]};\r
- end\r
- 4'h4 : begin\r
- xl_cache_index_pre = {req_va_page_align[ 3: 0],srw_entry_lkey[ 3:0]};\r
- xl_cache_tag_pre = {req_va_page_align[51: 4],srw_entry_lkey[31:4]};\r
- end\r
- 4'h5 : begin\r
- xl_cache_index_pre = {req_va_page_align[ 4: 0],srw_entry_lkey[ 2:0]};\r
- xl_cache_tag_pre = {req_va_page_align[51: 5],srw_entry_lkey[31:3]};\r
- end\r
- 4'h6 : begin\r
- xl_cache_index_pre = {req_va_page_align[ 5: 0],srw_entry_lkey[ 1:0]};\r
- xl_cache_tag_pre = {req_va_page_align[51: 6],srw_entry_lkey[31:2]};\r
- end\r
- 4'h7 : begin\r
- xl_cache_index_pre = {req_va_page_align[ 6: 0],srw_entry_lkey[ 0]};\r
- xl_cache_tag_pre = {req_va_page_align[51: 7],srw_entry_lkey[31:1]};\r
- end\r
- 4'h8 : begin\r
- xl_cache_index_pre = {req_va_page_align[ 7: 0] };\r
- xl_cache_tag_pre = {req_va_page_align[51: 8],srw_entry_lkey[31:0]};\r
- end\r
- // For pages bigger then 4k:\r
- 4'h9 : begin\r
- xl_cache_index_pre = {req_va_page_align[ 4] ,srw_entry_lkey[ 6:0]};\r
- xl_cache_tag_pre = {req_va_page_align[51: 5],req_va_page_align[3:0],srw_entry_lkey[31:7]};\r
- end\r
- 4'ha : begin\r
- xl_cache_index_pre = {req_va_page_align[ 5: 4] ,srw_entry_lkey[ 5:0]};\r
- xl_cache_tag_pre = {req_va_page_align[51: 6],req_va_page_align[3:0],srw_entry_lkey[31:6]};\r
- end\r
- 4'hb : begin\r
- xl_cache_index_pre = {req_va_page_align[ 6: 4] ,srw_entry_lkey[ 4:0]};\r
- xl_cache_tag_pre = {req_va_page_align[51: 7],req_va_page_align[3:0],srw_entry_lkey[31:5]};\r
- end\r
- 4'hc : begin\r
- xl_cache_index_pre = {req_va_page_align[ 7: 4] ,srw_entry_lkey[ 3:0]};\r
- xl_cache_tag_pre = {req_va_page_align[51: 8],req_va_page_align[3:0],srw_entry_lkey[31:4]};\r
- end\r
- 4'hd : begin\r
- xl_cache_index_pre = {req_va_page_align[ 8: 4] ,srw_entry_lkey[ 2:0]};\r
- xl_cache_tag_pre = {req_va_page_align[51: 9],req_va_page_align[3:0],srw_entry_lkey[31:3]};\r
- end\r
- 4'he : begin\r
- xl_cache_index_pre = {req_va_page_align[ 9: 4] ,srw_entry_lkey[ 1:0]};\r
- xl_cache_tag_pre = {req_va_page_align[51:10],req_va_page_align[3:0],srw_entry_lkey[31:2]};\r
- end\r
- 4'hf : begin\r
- xl_cache_index_pre = {req_va_page_align[10: 4] ,srw_entry_lkey[ 0]};\r
- xl_cache_tag_pre = {req_va_page_align[51:11],req_va_page_align[3:0],srw_entry_lkey[31:1]};\r
- end */\r
- pseudo_bit_t reserved1[0x00004];\r
- pseudo_bit_t nsb_page_size[0x00004];/* page_size encoding\r
- 0000 - reserved\r
- 0001 - reserved\r
- 0010 - 4K (default)\r
- 0011 - 8K\r
- 0100 - 16K\r
- 0101 - 32K\r
- 0110 - 64K\r
- Others - reserved\r
- */\r
- pseudo_bit_t reserved2[0x0000c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t tpt_cfg_disable_cross_page_bndry[0x00001];/* When set TPTdoes not check page boundery cross. */\r
- pseudo_bit_t tpt_cfg_disable_pd_check[0x00001];/* When set TPT does not check protection domain */\r
- pseudo_bit_t tpt_cfg_disable_ar_check[0x00001];/* When set TPT does not check Access righets */\r
- pseudo_bit_t tpt_cfg_disable_len_check[0x00001];/* When set TPT does not check lenght of access */\r
- pseudo_bit_t reserved3[0x00004];\r
- pseudo_bit_t tpt_cfg_int_cross_page_bndry[0x00001];/* When set TPT interrupts on Page cross vaiolation. */\r
- pseudo_bit_t tpt_cfg_int_pd[0x00001];/* When set TPT interrupts on Protection domain vaiolation. */\r
- pseudo_bit_t tpt_cfg_int_ar[0x00001];/* When set TPT interrupts on Access rightes vaiolation. */\r
- pseudo_bit_t tpt_cfg_int_len[0x00001];/* When set TPT interrupts on Access lenght vaiolation. */\r
- pseudo_bit_t reserved4[0x0000c];\r
- pseudo_bit_t gp_cfg[0x00008]; /* General Purpose Configuration Register */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x001c0];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rwt_base_add_63_32[0x00020];/* Base Address of Region & WIndow table */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rwt_base_add_31_0[0x00020];/* TPT MAS 3.3.1 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rw_cache_enable[0x00001];/* Region & WIndow cache enable */\r
- pseudo_bit_t reserved6[0x00007];\r
- pseudo_bit_t rw_entry_size[0x00004];/* Log of Region & Window entry size. */\r
- pseudo_bit_t reserved7[0x00004];\r
- pseudo_bit_t rw_entry_stride[0x00005];/* Log of Region & Window entry stride. */\r
- pseudo_bit_t reserved8[0x00003];\r
- pseudo_bit_t rwt_lenght[0x00005]; /* Log of Region & Window table entries. */\r
- pseudo_bit_t reserved9[0x00003];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved10[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t translation_table_msbs[0x00020];/* Translation table base address is a concatnation of those bit & the bits in the Region enrty. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t xl_cache_enable[0x00001];/* Translation cache enable. */\r
- pseudo_bit_t reserved11[0x00007];\r
- pseudo_bit_t xl_entry_size[0x00004];/* This register has a BUG !!!!!!!\r
- The Log of Transltion entry size need to be writen to bits[3:1]\r
- Bit[0] is ignored by HW !!!!!!\r
- HW looks on bits[3:1] & thinks this is the Log og the entry size. */\r
- pseudo_bit_t reserved12[0x00004];\r
- pseudo_bit_t xl_entry_stride[0x00005];/* Log of Transltion entry stride */\r
- pseudo_bit_t reserved13[0x0000b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved14[0x00140];\r
-/* --------------------------------------------------------- */\r
- struct TPTGW_st tptgw;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t status_0[0x00020]; /* TPT Status and internal states - See TPT MAS section 6.5 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t status_1[0x00020]; /* TPT Status and internal states - See TPT MAS section 6.5 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t status_2[0x00020]; /* TPT Status and internal states - See TPT MAS section 6.5 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t status_3[0x00020]; /* TPT Status and internal states - See TPT MAS section 6.5 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t status_4[0x00020]; /* TPT Status and internal states - See TPT MAS section 6.5 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t status_5[0x00020]; /* TPT Status and internal states - See TPT MAS section 6.5 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t status_6[0x00020]; /* TPT Status and internal states - See TPT MAS section 6.5 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t status_7[0x00020]; /* TPT Status and internal states - See TPT MAS section 6.5 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved15[0x00300];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t miss_bp_wm[0x00005]; /* When the number of misses in the miss fifo reaches this number - Back Pressure is asserted to the TMX & no more transactions can enter the TPT.\r
- Default value is OK. */\r
- pseudo_bit_t reserved16[0x0001b];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved17[0x003e0];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved18[0x00001];\r
- pseudo_bit_t bind_full0[0x00001]; /* Bind fifo is full */\r
- pseudo_bit_t bind_full1[0x00001]; /* Bind fifo full */\r
- pseudo_bit_t bind_empty0[0x00001]; /* Bind Fifo Empty */\r
- pseudo_bit_t bind_empty1[0x00001]; /* Bind Fifo Empty */\r
- pseudo_bit_t reserved19[0x00004];\r
- pseudo_bit_t rd_addr[0x00003]; /* Bind fifo read pointer */\r
- pseudo_bit_t reserved20[0x00001];\r
- pseudo_bit_t wr_addr[0x00003]; /* Bind fifo write pointer */\r
- pseudo_bit_t reserved21[0x00007];\r
- pseudo_bit_t bind_poponrd_ro[0x00001];/* Bind GW Pop On Read bit\r
- * This bit is read only see bug 5210 */\r
- pseudo_bit_t bind_pop[0x00001]; /* Pop bit og Bind GW */\r
- pseudo_bit_t bind_poponrd[0x00001]; /* Bind GW Pop On Read bit\r
- * This bit is write only see bug 5210 */\r
- pseudo_bit_t reserved22[0x00005];\r
- pseudo_bit_t bind_gw_locked[0x00001];/* locked bit of bind GW */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bind_data[0x00020]; /* Bind fifo is read from here */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved23[0x007c0];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t bind_result[0x00004]; /* Wrting to this register tranmit the bind sttus to the EXE.\r
- After the write the data is erased. */\r
- pseudo_bit_t reserved24[0x0001c];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved25[0x007e0];\r
-/* --------------------------------------------------------- */\r
- struct TPT_CAUSEREG_st tptcause; /* Cause Bits:\r
- 31:9 - reserved\r
- 8 - nsw_error\r
- 7 - rw_perr\r
- 6 - xl_perr\r
- 5 - tpt_pipe4 (debug)\r
- 4 - tpt_pipe3 (debug)\r
- 3 - tpt_pipe2 (debug)\r
- 2 - tpt_pipe1 (debug)\r
- 1 - tpt_pipe0 (debug)\r
- 0 - tp_crtimeout_occured */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved26[0x00100];\r
-/* --------------------------------------------------------- */\r
- struct CACHEPERF_st tptperf;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved27[0x00180];\r
-/* --------------------------------------------------------- */\r
- struct HCACMDIFACE_st hca_command_interface;/* Writing to the last word of this filed cause an interupt */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved28[0x00300];\r
-/* --------------------------------------------------------- */\r
- struct ECR_st eventcauseregister;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved29[0x04700];\r
-/* --------------------------------------------------------- */\r
- struct Nswitch_address_deocder_st TPT_address_decoder;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved30[0x01000];\r
-/* --------------------------------------------------------- */\r
- struct TPTNSIGW_st tpt_nsigw;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved31[0x01000];\r
-/* --------------------------------------------------------- */\r
- struct tpt_bist_st tpt_bist;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved32[0x03000];\r
-/* --------------------------------------------------------- */\r
- struct SCRPAD_st scratchpad; /* FW General usage */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved33[0x08000];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Transport Slice */\r
-\r
-struct TSlice_st { /* Little Endian */\r
- struct SDE_st sde;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x08000];\r
-/* --------------------------------------------------------- */\r
- struct RDE_st rde;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x08000];\r
-/* --------------------------------------------------------- */\r
- struct EXU_st exu;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x20000];\r
-/* --------------------------------------------------------- */\r
- struct TCU_st tcu;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* InfiniBand Port */\r
-\r
-struct ib_st { /* Little Endian */\r
- struct IB_port_info_GUID_info_st IBCPC;/* Port IB Compliant Configuration Register */\r
-/* --------------------------------------------------------- */\r
- struct VL_arbitration_table_st VLARBT;/* VL Arbitration Table */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00060];\r
-/* --------------------------------------------------------- */\r
- struct Port_status_st PORTSR; /* Post Status Register */\r
-/* --------------------------------------------------------- */\r
- struct buffer_allocation_st BUFALO; /* Buffer Allocation Registers */\r
-/* --------------------------------------------------------- */\r
- struct ib_link_st link; /* IB Port Link Configuration Register */\r
-/* --------------------------------------------------------- */\r
- struct IB_port_PMEG_hdr_st PMEG; /* IB Port Performance Management and Event Generation Header */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x00480];\r
-/* --------------------------------------------------------- */\r
- struct Congestion_Control_Register_st Congestion_Control_Register;\r
-/* --------------------------------------------------------- */\r
- struct SerDes_Configuration_and_Debug_st SerDes_configuration_and_Debug;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x00060];\r
-/* --------------------------------------------------------- */\r
- struct IB_Port_Link_Phy_Configuration_Register_st IBPPHYCON;\r
-/* --------------------------------------------------------- */\r
- struct Extended_Buffer_Allocation_Register_st ExBUFA;\r
-/* --------------------------------------------------------- */\r
- struct VL_mapping_st VLM; /* VL Mapping Registers */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x00080];\r
-/* --------------------------------------------------------- */\r
- struct IB1_BIST_st ib_bist;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x00020];\r
-/* --------------------------------------------------------- */\r
- struct Flow_Control_update_watchdog_register_st Flow_Ctrl_Up_WD;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x00060];\r
-/* --------------------------------------------------------- */\r
- struct Parallel_Debug_Port_Configuration_st Parallel_Debug_Port_Config;\r
-/* --------------------------------------------------------- */\r
- struct IB_port_general_config_st PGC;/* IB Port General Configuration Register */\r
-/* --------------------------------------------------------- */\r
- struct PktDiscConfigMask_st PktDiscConfigMask;\r
-/* --------------------------------------------------------- */\r
- struct LBCTRL_st loopbackctrl;\r
-/* --------------------------------------------------------- */\r
- struct port_debug_config_st PBUGC; /* Port Debug Configuration Register */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x02000];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Area reserved for backwards compatibility */\r
-\r
-struct bw_compat_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x80000];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Copy from PRM */\r
-\r
-struct PRM_QPCBASEADDR_st { /* Little Endian */\r
- pseudo_bit_t QPC_Base_Addr_H[0x00020];/* QPC Base Address [63:32]\r
- Table must be aligned on its size */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t log_num_of_qp[0x00005];/* Log base 2 of number of supported QPs */\r
- pseudo_bit_t reserved0[0x00002];\r
- pseudo_bit_t QPC_Base_Addr_L[0x00019];/* QPC Base Address [31:7]\r
- Table must be aligned on its size */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t EEC_Base_Addr_H[0x00020];/* EEC Base Address [63:32]\r
- Table must be aligned on its size.\r
- Address may be set to zero if RD is not supported. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t log_num_of_ee[0x00005];/* Log base 2 of number of supported EEs. */\r
- pseudo_bit_t reserved1[0x00002];\r
- pseudo_bit_t EEC_Base_Addr_L[0x00019];/* EEC Base Address [31:7]\r
- Table must be aligned on its size\r
- Address may be set to zero if RD is not supported. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CQC_Base_Addr_H[0x00020];/* CQC Base Address [63:32]\r
- Table must be aligned on its size */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t log_num_of_cq[0x00005];/* Log base 2 of number of supported CQs. */\r
- pseudo_bit_t reserved2[0x00001];\r
- pseudo_bit_t CQC_Base_Addr_L[0x0001a];/* CQC Base Address [31:6]\r
- Table must be aligned on its size */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t EQPC_Base_Addr_H[0x00020];/* Extended QPC Base Address [63:32]\r
- Table has same number of entries as QPC table.\r
- Table must be aligned to entry size. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t EQPC_Base_Addr_L[0x00020];/* Extended QPC Base Address [31:0]\r
- Table has same number of entries as QPC table.\r
- Table must be aligned to entry size. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t EEEC_Base_Addr_H[0x00020];/* Extended EEC Base Address [63:32]\r
- Table has same number of entries as EEC table.\r
- Table must be aligned to entry size.\r
- Address may be set to zero if RD is not supported. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t EEEC_Base_Addr_L[0x00020];/* Extended EEC Base Address [31:0]\r
- Table has same number of entries as EEC table.\r
- Table must be aligned to entry size.\r
- Address may be set to zero if RD is not supported. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t EQC_Base_Addr_H[0x00020];/* EQC Base Address [63:32]\r
- Address may be set to zero if EQs are not supported.\r
- Table must be aligned to entry size. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t log_num_eq[0x00004]; /* Log base 2 of number of supported EQs.\r
- Must be 6 or less in InfiniHost. */\r
- pseudo_bit_t reserved3[0x00002];\r
- pseudo_bit_t EQC_Base_Addr_L[0x0001a];/* EQC Base Address [31:6]\r
- Address may be set to zero if EQs are not supported.\r
- Table must be aligned to entry size. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t RDB_Base_Addr_H[0x00020];/* Base address of table that holds remote read and remote atomic requests [63:32].\r
- Table must be aligned to RDB entry size (32 bytes).\r
- Address may be set to zero if remote RDMA reads are not supported.\r
- Please refer to QP and EE chapter for further explanation on RDB allocation. */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t RDB_Base_Addr_L[0x00020];/* Base address of table that holds remote read and remote atomic requests [31:0].\r
- Table must be aligned to RDB entry size (32 bytes).\r
- This field must always be zero.\r
- Please refer to QP and EE chapter for further explanation on RDB allocation. */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* */\r
-\r
-struct IR_SCRPAD_st { /* Little Endian */\r
- pseudo_bit_t word[55][0x00020]; /* instead of RESERVED 248 */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t CHECK_STACK[0x00020]; /* Write to memory at this address means stack overflow */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t DEBUG[8][0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Victor: buffer of 16 words */\r
-\r
-struct BUFF16_st { /* Little Endian */\r
- pseudo_bit_t word[16][0x00020];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* NSwitch Agent Credits */\r
-\r
-struct ns_creds_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00060];\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Cause Registers */\r
-\r
-struct PCU_CAUSEREG_st { /* Little Endian */\r
- pseudo_bit_t split_comp_err[0x00001];/* Split completion message error arrived */\r
- pseudo_bit_t unexpected_split_comp[0x00001];/* Unexpected split completion arrived */\r
- pseudo_bit_t pcr_rd_sc_discard[0x00001];/* pcr_rd_sc_discard - Don't use this bit. */\r
- pseudo_bit_t split_comp_discarded[0x00001];/* Split completion was discarded by non-posted inbound engines, due to target abort or master abort on PCIX bus */\r
- pseudo_bit_t TA_secondary_bus[0x00001];/* Target-abort occurred on secondary bus (NSW) during inbound non-posted transaction, i.e. a NACK was received from HCA/DMU/NTU. */\r
- pseudo_bit_t MA_secondary_bus[0x00001];/* Master-abort occurred on secondary bus (NSW) during inbound non-posted transaction */\r
- pseudo_bit_t MA_secondary_bus_posted[0x00001];/* Master-abort occurred on secondary bus (NSW) during inbound posted write */\r
- pseudo_bit_t target_parity_err[0x00001];/* Attribute parity error detected by PCI/X target */\r
- pseudo_bit_t parity_err0[0x00001]; /* Master-Detected-Parity-Error status bit from PCI/X target */\r
- pseudo_bit_t rcv_MA_from_target[0x00001];/* Received-Master-Abort status bit from PCI/X target */\r
- pseudo_bit_t rcv_TA_from_target[0x00001];/* Received-Target-Abort status bit from PCI/X target */\r
- pseudo_bit_t rcv_SERR[0x00001]; /* Received-SERR# status bit */\r
- pseudo_bit_t signal_TAfrom_target[0x00001];/* Signalled-Target-Abort from PCI/X target */\r
- pseudo_bit_t parity_err1[0x00001]; /* Parity-Error-Detected status bit from PCI/X target */\r
- pseudo_bit_t parity_err2[0x00001]; /* Master-Detected-Parity-Error status bit from PCI/X master */\r
- pseudo_bit_t cause[0x00011];\r
-/* --------------------------------------------------------- */\r
- struct EXT_CAUSEREG_st extended_cause;\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* RDB Entry */\r
-\r
-struct RDBENTRY_st { /* Little Endian */\r
- pseudo_bit_t psn[0x00018]; /* PSN of Request */\r
- pseudo_bit_t opcode[0x00008]; /* OpCode */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x00020];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t replydata_63_32_[0x00020];/* Reply Data[63:32] (for Atomics) */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t replydata_31_0_[0x00020];/* ReplyData[31:0] for Atomics */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t len[0x00020]; /* Length - For RDMA Read */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t rkey[0x00020]; /* R_Key */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t va_63_32_[0x00020]; /* Virtual Address [63:32] */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t va_31_0_[0x00020]; /* Virtual Address [31:0] */\r
-/* --------------------------------------------------------- */\r
-};\r
-\r
-/* Tavor */\r
-\r
-struct Tavor_st { /* Little Endian */\r
- struct bw_compat_st bw_compat; /* CR region saved for backwards compatibility */\r
-/* --------------------------------------------------------- */\r
- struct ib_st IB[2];\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved0[0x178000];\r
-/* --------------------------------------------------------- */\r
- struct TSlice_st ts0; /* Transport Slice 0 Configuration Space */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved1[0x180000];\r
-/* --------------------------------------------------------- */\r
- struct TPT_st tpt;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved2[0x10000];\r
-/* --------------------------------------------------------- */\r
- struct NSI_st nsi;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved3[0x0f000];\r
-/* --------------------------------------------------------- */\r
- struct QPC_st qpc;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved4[0x18000];\r
-/* --------------------------------------------------------- */\r
- struct LDB_st ldb;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved5[0x318000];\r
-/* --------------------------------------------------------- */\r
- struct misc_st MISC; /* Miscellaneous Configuration Registers Summary */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved6[0x08000];\r
-/* --------------------------------------------------------- */\r
- struct PCU_st pcu0; /* PCI/PCIX Unit Configuration Space */\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved7[0x08000];\r
-/* --------------------------------------------------------- */\r
- struct DMU_st dmu0;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved8[0x10000];\r
-/* --------------------------------------------------------- */\r
- struct NTU_st ntu0;\r
-/* --------------------------------------------------------- */\r
- pseudo_bit_t reserved9[0x30000];\r
-/* --------------------------------------------------------- */\r
-};\r
-#endif /* H_bits_tav_csp_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef _VERSION_H\r
-#define _VERSION_H\r
-\r
-#define FILE_VERSION "2.0.0.0\0"\r
-#define FV1 2\r
-#define FV2 0\r
-#define FV3 0\r
-#define FV4 0\r
-#define PV1 FV1\r
-#define PV2 FV2\r
-#define PV3 FV3\r
-#define PV4 FV4\r
-#define PRODUCT_VERSION FILE_VERSION\r
-#define PRIVATE_BUILD "\0"\r
-#define SPECIAL_BUILD PRIVATE_BUILD\r
-#define FILE_DESCRIPTION "MT23108 Card Driver\0"\r
-#define INTERNAL_NAME "Mdt.sys\0"\r
-#define ORIGINAL_NAME INTERNAL_NAME\r
-#define PRODUCT_NAME "Mellanox Driver Development Kit\0"\r
-#endif\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MTPERF_H\r
-#define H_MTPERF_H\r
-\r
-#ifdef MTPERF\r
-\r
-\r
-#include <mtl_common.h>\r
-#include <mosal.h>\r
-\r
-\r
-typedef struct {\r
- u_int64_t time_accum; /* Total time of segment accumulated so far */\r
- u_int32_t samples_cntr; /* Counter for number of time the segment was sampled */\r
- u_int64_t start; /* Start time of current sample */\r
- u_int64_t sample_time; /* temporary var. to compute sample time */\r
- u_int64_t sample_accum; /* for supporting pause/cont */\r
- u_int64_t latency_limit; /* Limit of sample - to exclude context switches */\r
- u_int32_t exceed_cntr; /* counter for measures which exceed latency_limit */\r
-} MTPERF_segment_t;\r
-\r
-/* Define a new performance measurement segment */\r
-#define MTPERF_NEW_SEGMENT(segment_name,estimated_tick_latency) \\r
- MTPERF_segment_t MTPERF_##segment_name = {0,0,0,0,0,estimated_tick_latency*100,0}\r
-\r
-/* Declare a segment which was defined in another source file */\r
-#define MTPERF_EXTERN_SEGMENT(segment_name) extern MTPERF_segment_t MTPERF_##segment_name\r
-\r
-/* Start a sample of the given segment (sample current time) */\r
-#define MTPERF_TIME_START(segment_name) MTPERF_##segment_name.start = MOSAL_get_time_counter()\r
-\r
-/* Pause sample of current segment (time accumulator updated , but counter does not) */\r
-#define MTPERF_TIME_PAUSE(segment_name) /* not supported yet */\r
-\r
-/* Continue segment time measure */\r
-#define MTPERF_TIME_CONT(segment_name) /* not supported yet */\r
-\r
-/* End time accumulation of the segment (counter++) */\r
-#define MTPERF_TIME_END(segment_name) \\r
- MTPERF_##segment_name.sample_time = \\r
- (MOSAL_get_time_counter()- MTPERF_##segment_name.start) ; \\r
- if (MTPERF_##segment_name.sample_time > MTPERF_##segment_name.latency_limit) { \\r
- MTPERF_##segment_name.exceed_cntr++ ; \\r
- } else { /* normal sample */ \\r
- MTPERF_##segment_name.time_accum += MTPERF_##segment_name.sample_time; \\r
- MTPERF_##segment_name.samples_cntr++ ; \\r
- }\r
-\r
-/* MTPERF_TIME_END only if the given condition is met */\r
-#define MTPERF_TIME_END_IF(segment_name,condition) \\r
- if (condition) {MTPERF_TIME_END(segment_name)}\r
-\r
-/* Return current status */\r
-#define MTPERF_REPORT(segment_name,samples_cnt_p,total_ticks_p,exceed_cntr_p) \\r
- *samples_cnt_p= MTPERF_##segment_name.samples_cntr; \\r
- *total_ticks_p= MTPERF_##segment_name.time_accum; \\r
- *exceed_cntr_p= MTPERF_##segment_name.exceed_cntr; \r
-\r
-/* Output current status using printf */\r
-\r
-#ifndef MT_KERNEL\r
-#define MTPERF_REPORT_PRINTF(segment_name) \\r
- printf("%s segment stats: %d times in " U64_FMT_SPEC "u ticks - average= " U64_FMT_SPEC "u ticks (%d exc.).\n", \\r
- #segment_name,MTPERF_##segment_name.samples_cntr, \\r
- (u_int64_t) MTPERF_##segment_name.time_accum, \\r
- (u_int64_t) ((MTPERF_##segment_name.samples_cntr > 0) ? \\r
- MTPERF_##segment_name.time_accum/MTPERF_##segment_name.samples_cntr : 0), \\r
- MTPERF_##segment_name.exceed_cntr)\r
-#else\r
-#define MTPERF_REPORT_PRINTF(segment_name) \\r
- printk("%s segment stats: %d times in " U64_FMT_SPEC "u ticks - average= %d ticks (%d exc.).\n", \\r
- #segment_name,MTPERF_##segment_name.samples_cntr, \\r
- (u_int64_t) MTPERF_##segment_name.time_accum, \\r
- (MTPERF_##segment_name.samples_cntr > 0) ? \\r
- (u_int32_t)(MTPERF_##segment_name.time_accum)/MTPERF_##segment_name.samples_cntr : 0, \\r
- MTPERF_##segment_name.exceed_cntr)\r
-#endif\r
-\r
-/* Reset counter and samples accumulator of given segment */\r
-#define MTPERF_RESET(segment_name) \\r
- MTPERF_##segment_name.samples_cntr= 0; \\r
- MTPERF_##segment_name.time_accum= 0; \\r
- MTPERF_##segment_name.exceed_cntr= 0\r
-\r
-#else /* MTPERF not defined */\r
-/* Define empty macros */\r
-\r
-#define MTPERF_NEW_SEGMENT(segment_name,estimated_tick_latency) \r
-\r
-#define MTPERF_EXTERN_SEGMENT(segment_name) \r
-\r
-#define MTPERF_TIME_START(segment_name) \r
-\r
-#define MTPERF_TIME_PAUSE(segment_name) \r
-\r
-#define MTPERF_TIME_CONT(segment_name) \r
-\r
-#define MTPERF_TIME_END(segment_name) \r
- \r
-#define MTPERF_TIME_END_IF(segment_name,condition)\r
-\r
-#define MTPERF_REPORT(segment_name,samples_cnt_p,total_ticks_p,exceed_cntr_p) \r
-\r
-#define MTPERF_REPORT_PRINTF(segment_name) \r
-\r
-#define MTPERF_RESET(segment_name) \r
-\r
-\r
-#endif /* MTPERF */\r
-#endif /* #ifndef H_MTPERF_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_MT23108_H\r
-#define H_MT23108_H\r
-\r
-#include <mtl_common.h>\r
-#include <tavor_dev_defs.h>\r
-#include <tavor_if_defs.h>\r
-#include <cr_types.h>\r
-#include <MT23108_PRM.h>\r
-#include <MT23108_PRM_append.h>\r
-\r
-#endif\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-/***\r
- *** This file was generated at "Thu Apr 29 10:25:56 2004"\r
- *** by:\r
- *** % csp_bf -copyright=/mswg/misc/license-header.txt -prefix tavorprm_ -bits -fixnames MT23108_PRM.csp\r
- ***/\r
-\r
-#ifndef H_prefix_tavorprm_bits_fixnames_MT23108_PRM_csp_H\r
-#define H_prefix_tavorprm_bits_fixnames_MT23108_PRM_csp_H\r
-\r
-\r
-/* Send doorbell */\r
-\r
-struct tavorprm_send_doorbell_st { /* Little Endian */\r
- pseudo_bit_t nopcode[0x00005]; /* Opcode of descriptor to be executed */\r
- pseudo_bit_t f[0x00001]; /* Fence bit. If set, descriptor is fenced */\r
- pseudo_bit_t nda[0x0001a]; /* Bits 31:6 of descriptors virtual address */\r
-/* -------------- */\r
- pseudo_bit_t nds[0x00006]; /* Next descriptor size (in 16-byte chunks) */\r
- pseudo_bit_t reserved0[0x00002];\r
- pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */\r
-/* -------------- */\r
-}; \r
-\r
-/* Address Path */\r
-\r
-struct tavorprm_address_path_st { /* Little Endian */\r
- pseudo_bit_t pkey_index[0x00007]; /* PKey table index */\r
- pseudo_bit_t reserved0[0x00011];\r
- pseudo_bit_t port_number[0x00002]; /* Specific port associated with this QP/EE.\r
- 1 - Port 1\r
- 2 - Port 2\r
- other - reserved */\r
- pseudo_bit_t reserved1[0x00006];\r
-/* -------------- */\r
- pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */\r
- pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */\r
- pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */\r
- pseudo_bit_t reserved2[0x00005];\r
- pseudo_bit_t rnr_retry[0x00003]; /* RNR retry count (see C9-132 in IB spec Vol 1)\r
- 0-6 - number of retries\r
- 7 - infinite */\r
-/* -------------- */\r
- pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */\r
- pseudo_bit_t max_stat_rate[0x00003];/* Maximum static rate control. \r
- 0 - 4X injection rate\r
- 1 - 1X injection rate\r
- other - reserved\r
- */\r
- pseudo_bit_t reserved3[0x00005];\r
- pseudo_bit_t mgid_index[0x00006]; /* Index to port GID table */\r
- pseudo_bit_t reserved4[0x00005];\r
- pseudo_bit_t ack_timeout[0x00005]; /* Local ACK timeout - Transport timer for activation of retransmission mechanism. Refer to IB spec Vol1 9.7.6.1.3 for further details.\r
- The transport timer is set to 4.096us*2^ack_timeout, if ack_timeout is 0 then transport timer is disabled. */\r
-/* -------------- */\r
- pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */\r
- pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */\r
- pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */\r
-/* -------------- */\r
- pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */\r
-/* -------------- */\r
- pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */\r
-/* -------------- */\r
- pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */\r
-/* -------------- */\r
- pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] */\r
-/* -------------- */\r
-}; \r
-\r
-/* HCA Command Register (HCR) */\r
-\r
-struct tavorprm_hca_command_register_st { /* Little Endian */\r
- pseudo_bit_t in_param_h[0x00020]; /* Input Parameter: parameter[63:32] or pointer[63:32] to input mailbox (see command description) */\r
-/* -------------- */\r
- pseudo_bit_t in_param_l[0x00020]; /* Input Parameter: parameter[31:0] or pointer[31:0] to input mailbox (see command description) */\r
-/* -------------- */\r
- pseudo_bit_t input_modifier[0x00020];/* Input Parameter Modifier */\r
-/* -------------- */\r
- pseudo_bit_t out_param_h[0x00020]; /* Output Parameter: parameter[63:32] or pointer[63:32] to output mailbox (see command description) */\r
-/* -------------- */\r
- pseudo_bit_t out_param_l[0x00020]; /* Output Parameter: parameter[31:0] or pointer[31:0] to output mailbox (see command description) */\r
-/* -------------- */\r
- pseudo_bit_t reserved0[0x00010];\r
- pseudo_bit_t token[0x00010]; /* Software assigned token to the command, to uniquely identify it. The token is returned to the software in the EQE reported. */\r
-/* -------------- */\r
- pseudo_bit_t opcode[0x0000c]; /* Command opcode */\r
- pseudo_bit_t opcode_modifier[0x00004];/* Opcode Modifier, see specific description for each command. */\r
- pseudo_bit_t reserved1[0x00006];\r
- pseudo_bit_t e[0x00001]; /* Event Request\r
- 0 - Don't report event (software will poll the GO bit)\r
- 1 - Report event to EQ when the command completes */\r
- pseudo_bit_t go[0x00001]; /* Go (0=Software ownership for the HCR, 1=Hardware ownership for the HCR)\r
- Software can write to the HCR only if Go bit is cleared.\r
- Software must set the Go bit to trigger the HW to execute the command. Software must not write to this register value other than 1 for the Go bit. */\r
- pseudo_bit_t status[0x00008]; /* Command execution status report. Valid only if command interface in under SW ownership (Go bit is cleared)\r
- 0 - command completed without error. If different than zero, command execution completed with error. Syndrom encoding is depended on command executed and is defined for each command */\r
-/* -------------- */\r
-}; \r
-\r
-/* EQ Doorbell */\r
-\r
-struct tavorprm_eq_cmd_doorbell_st { /* Little Endian */\r
- pseudo_bit_t eqn[0x00006]; /* EQ accessed */\r
- pseudo_bit_t reserved0[0x00012];\r
- pseudo_bit_t eq_cmd[0x00008]; /* Command to be executed on EQ\r
- 01 - increment Consumer_indx by one\r
- 02 - Request notification for next event (Arm EQ)\r
- 03 - Disarm CQ (CQ number is specified in EQ_param)\r
- 04 - set Consumer_indx to value of EQ_param\r
- 05 - move EQ to Always Armed state\r
- other - reserved */\r
-/* -------------- */\r
- pseudo_bit_t eq_param[0x00020]; /* parameter to be used by EQ command */\r
-/* -------------- */\r
-}; \r
-\r
-/* CQ Doorbell */\r
-\r
-struct tavorprm_cq_cmd_doorbell_st { /* Little Endian */\r
- pseudo_bit_t cqn[0x00018]; /* CQ number accessed */\r
- pseudo_bit_t cq_cmd[0x00008]; /* Command to be executed on CQ\r
- 01 - increment Consumer_indx by cq_param plus 1\r
- 02 - Request notification for next Solicited or Unsolicited completion event. CQ_param must contain last succesfully polled consumer index. For newly generated CQs the CQ_param should contain (-1) modulu CQ size. When working with CQs with overrun detection, CQ_param can be set to 0xFFFFFFFF (HW will use the last polled index). \r
- 03 - Request notification for next Solicited completion event CQ_param must contain last succesfully polled consumer index. For newly generated CQs the CQ_param should contain (-1) modulu CQ size. When working with CQs with overrun detection, CQ_param can be set to 0xFFFFFFFF (HW will use the last polled index).\r
- 04 - set Consumer_indx to value of CQ_param\r
- other - reserved */\r
-/* -------------- */\r
- pseudo_bit_t cq_param[0x00020]; /* parameter to be used by CQ command */\r
-/* -------------- */\r
-}; \r
-\r
-/* Receive doorbell */\r
-\r
-struct tavorprm_receive_doorbell_st { /* Little Endian */\r
- pseudo_bit_t nds[0x00006]; /* Next descriptor size (in 16-byte chunks)\r
- Must be zero for SRQ doorbells */\r
- pseudo_bit_t nda[0x0001a]; /* Bits 31:6 of descriptors virtual address */\r
-/* -------------- */\r
- pseudo_bit_t credits[0x00008]; /* Amount of credits ((length of the chain) posted with the doorbell on receive queue. Chain of up to 256 descriptors can be linked with single doorbell. Zero value in this field means 256. */\r
- pseudo_bit_t qpn[0x00018]; /* QP number or SRQ number this doorbell is rung on */\r
-/* -------------- */\r
-}; \r
-\r
-/* RD-send doorbell */\r
-\r
-struct tavorprm_rd_send_doorbell_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00008];\r
- pseudo_bit_t een[0x00018]; /* End-to-end context number (reliable datagram)\r
- Must be zero for Nop and Bind operations */\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x00008];\r
- pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */\r
-/* -------------- */\r
- struct tavorprm_send_doorbell_st snd_params;/* Send parameters */\r
-/* -------------- */\r
-}; \r
-\r
-/* Multicast Group Member QP */\r
-\r
-struct tavorprm_mgmqp_st { /* Little Endian */\r
- pseudo_bit_t qpn_i[0x00018]; /* QPN_i: QP number which is a member in this multicast group. Valid only if Qi bit is set. Length of the QPN_i list is set in INIT_HCA */\r
- pseudo_bit_t reserved0[0x00007];\r
- pseudo_bit_t qi[0x00001]; /* Qi: QPN_i is valid */\r
-/* -------------- */\r
-}; \r
-\r
-/* Logical DIMM Information */\r
-\r
-struct tavorprm_dimminfo_st { /* Little Endian */\r
- pseudo_bit_t dimmsize[0x00010]; /* Size of DIMM in units of 2^20 Bytes. This value is valid only when DIMMStatus is 0. */\r
- pseudo_bit_t reserved0[0x00008];\r
- pseudo_bit_t dimmstatus[0x00001]; /* DIMM Status\r
- 0 - Enabled\r
- 1 - Disabled\r
- */\r
- pseudo_bit_t dh[0x00001]; /* When set, the DIMM is Hidden and can not be accessed from the PCI bus. */\r
- pseudo_bit_t wo[0x00001]; /* When set, the DIMM is write only.\r
- If data integrity is configured (other than none), the DIMM must be\r
- only targeted by write transactions where the address and size are multiples of 16 bytes. */\r
- pseudo_bit_t reserved1[0x00005];\r
-/* -------------- */\r
- pseudo_bit_t spd[0x00001]; /* 0 - DIMM SPD was read from DIMM\r
- 1 - DIMM SPD was read from InfiniHost NVMEM */\r
- pseudo_bit_t sladr[0x00003]; /* SPD Slave Address 3 LSBits. \r
- Valid only if spd bit is 0. */\r
- pseudo_bit_t sock_num[0x00002]; /* DIMM socket number (for double sided DIMM one of the two numbers will be reported) */\r
- pseudo_bit_t syn[0x00004]; /* Error syndrome (valid regardless of status value)\r
- 0 - DIMM has no error\r
- 1 - SPD error (e.g. checksum error, no response, error while reading)\r
- 2 - DIMM out of bounds (e.g. DIMM rows number is not between 7 and 14, DIMM type is not 2)\r
- 3 - DIMM conflict (e.g. mix of registered and unbuffered DIMMs, CAS latency conflict)\r
- 5 - DIMM size trimmed due to configuration (size exceeds)\r
- other - Error, reserved\r
- */\r
- pseudo_bit_t reserved2[0x00016];\r
-/* -------------- */\r
- pseudo_bit_t vendor_id_h[0x00020]; /* JDEC Manufacturer ID[63:32] */\r
-/* -------------- */\r
- pseudo_bit_t vendor_id_l[0x00020]; /* JDEC Manufacturer ID[31:0] */\r
-/* -------------- */\r
- pseudo_bit_t dimm_start_adr_h[0x00020];/* DDR memory start address [63:32]. This value is valid only when DIMMStatus is 0. */\r
-/* -------------- */\r
- pseudo_bit_t dimm_start_adr_l[0x00020];/* DDR memory start address [31:0]. This value is valid only when DIMMStatus is 0. */\r
-/* -------------- */\r
- pseudo_bit_t reserved3[0x00040];\r
-/* -------------- */\r
-}; \r
-\r
-/* UAR Parameters */\r
-\r
-struct tavorprm_uar_params_st { /* Little Endian */\r
- pseudo_bit_t uar_base_addr_h[0x00020];/* UAR Base Address [63:32] (QUERY_HCA only) */\r
-/* -------------- */\r
- pseudo_bit_t reserved0[0x00014];\r
- pseudo_bit_t uar_base_addr_l[0x0000c];/* UAR Base Address [31:20] (QUERY_HCA only) */\r
-/* -------------- */\r
- pseudo_bit_t uar_page_sz[0x00008]; /* This field defines the size of each UAR page.\r
- Size of UAR Page is 4KB*2^UAR_Page_Size */\r
- pseudo_bit_t reserved1[0x00018];\r
-/* -------------- */\r
- pseudo_bit_t reserved2[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t uar_scratch_base_addr_h[0x00020];/* Base address of UAR scratchpad [63:32].\r
- Number of entries in table is UAR BAR size divided by UAR Page Size. \r
- Table must be aligned to entry size. */\r
-/* -------------- */\r
- pseudo_bit_t uar_scratch_base_addr_l[0x00020];/* Base address of UAR scratchpad [31:0].\r
- Number of entries in table is UAR BAR size divided by UAR Page Size. \r
- Table must be aligned to entry size. */\r
-/* -------------- */\r
- pseudo_bit_t reserved3[0x00040];\r
-/* -------------- */\r
-}; \r
-\r
-/* Translation and Protection Tables Parameters */\r
-\r
-struct tavorprm_tptparams_st { /* Little Endian */\r
- pseudo_bit_t mpt_base_adr_h[0x00020];/* MPT - Memory Protection Table base physical address [63:32].\r
- Entry size is 64 bytes.\r
- Table must be aligned to its size.\r
- Address may be set to zero if address translation and protection is not supported. */\r
-/* -------------- */\r
- pseudo_bit_t mpt_base_adr_l[0x00020];/* MPT - Memory Protection Table base physical address [31:0].\r
- Entry size is 64 bytes.\r
- Table must be aligned to its size.\r
- Address may be set to zero if address translation and protection is not supported. */\r
-/* -------------- */\r
- pseudo_bit_t log_mpt_sz[0x00006]; /* Log (base 2) of the number of region/windows entries in the MPT table. */\r
- pseudo_bit_t reserved0[0x00002];\r
- pseudo_bit_t pfto[0x00005]; /* Page Fault RNR Timeout - \r
- The field returned in RNR Naks generated when a page fault is detected.\r
- It has no effect when on-demand-paging is not used. */\r
- pseudo_bit_t reserved1[0x00003];\r
- pseudo_bit_t mtt_segment_size[0x00003];/* The size of MTT segment is 64*2^MTT_Segment_Size bytes */\r
- pseudo_bit_t reserved2[0x0000d];\r
-/* -------------- */\r
- pseudo_bit_t mtt_version[0x00008]; /* Version of MTT page walk. Must be zero */\r
- pseudo_bit_t reserved3[0x00018];\r
-/* -------------- */\r
- pseudo_bit_t mtt_base_addr_h[0x00020];/* MTT - Memory Translation table base physical address [63:32].\r
- Table must be aligned to its size.\r
- Address may be set to zero if address translation and protection is not supported. */\r
-/* -------------- */\r
- pseudo_bit_t mtt_base_addr_l[0x00020];/* MTT - Memory Translation table base physical address [31:0].\r
- Table must be aligned to its size.\r
- Address may be set to zero if address translation and protection is not supported. */\r
-/* -------------- */\r
- pseudo_bit_t reserved4[0x00040];\r
-/* -------------- */\r
-}; \r
-\r
-/* Multicast Support Parameters */\r
-\r
-struct tavorprm_multicastparam_st { /* Little Endian */\r
- pseudo_bit_t mc_base_addr_h[0x00020];/* Base Address of the Multicast Table [63:32].\r
- The base address must be aligned to the entry size.\r
- Address may be set to zero if multicast is not supported. */\r
-/* -------------- */\r
- pseudo_bit_t mc_base_addr_l[0x00020];/* Base Address of the Multicast Table [31:0]. \r
- The base address must be aligned to the entry size.\r
- Address may be set to zero if multicast is not supported. */\r
-/* -------------- */\r
- pseudo_bit_t reserved0[0x00040];\r
-/* -------------- */\r
- pseudo_bit_t log_mc_table_entry_sz[0x00010];/* Log2 of the Size of multicast group member (MGM) entry.\r
- Must be greater than 5 (to allow CTRL and GID sections). \r
- That implies the number of QPs per MC table entry. */\r
- pseudo_bit_t reserved1[0x00010];\r
-/* -------------- */\r
- pseudo_bit_t mc_table_hash_sz[0x00011];/* Number of entries in multicast DGID hash table (must be power of 2)\r
- INIT_HCA - the required number of entries\r
- QUERY_HCA - the actual number of entries assigned by firmware (will be less than or equal to the amount required in INIT_HCA) */\r
- pseudo_bit_t reserved2[0x0000f];\r
-/* -------------- */\r
- pseudo_bit_t log_mc_table_sz[0x00005];/* Log2 of the overall number of MC entries in the MCG table (includes both hash and auxiliary tables) */\r
- pseudo_bit_t reserved3[0x00013];\r
- pseudo_bit_t mc_hash_fn[0x00003]; /* Multicast hash function\r
- 0 - Default hash function\r
- other - reserved */\r
- pseudo_bit_t reserved4[0x00005];\r
-/* -------------- */\r
- pseudo_bit_t reserved5[0x00020];\r
-/* -------------- */\r
-}; \r
-\r
-/* Memory Access Parameters for UD Address Vector Table */\r
-\r
-struct tavorprm_udavtable_memory_parameters_st { /* Little Endian */\r
- pseudo_bit_t l_key[0x00020]; /* L_Key used to access TPT */\r
-/* -------------- */\r
- pseudo_bit_t pd[0x00018]; /* PD used by TPT for matching against PD of region entry being accessed. */\r
- pseudo_bit_t reserved0[0x00005];\r
- pseudo_bit_t xlation_en[0x00001]; /* When cleared, address is physical address and no translation will be done. When set, address is virtual. TPT will be accessed in both cases for address decoding purposes. */\r
- pseudo_bit_t reserved1[0x00002];\r
-/* -------------- */\r
-}; \r
-\r
-/* QPC/EEC/CQC/EQC/RDB Parameters */\r
-\r
-struct tavorprm_qpcbaseaddr_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00080];\r
-/* -------------- */\r
- pseudo_bit_t qpc_base_addr_h[0x00020];/* QPC Base Address [63:32]\r
- Table must be aligned on its size */\r
-/* -------------- */\r
- pseudo_bit_t log_num_of_qp[0x00005];/* Log base 2 of number of supported QPs */\r
- pseudo_bit_t reserved1[0x00002];\r
- pseudo_bit_t qpc_base_addr_l[0x00019];/* QPC Base Address [31:7]\r
- Table must be aligned on its size */\r
-/* -------------- */\r
- pseudo_bit_t reserved2[0x00040];\r
-/* -------------- */\r
- pseudo_bit_t eec_base_addr_h[0x00020];/* EEC Base Address [63:32]\r
- Table must be aligned on its size.\r
- Address may be set to zero if RD is not supported. */\r
-/* -------------- */\r
- pseudo_bit_t log_num_of_ee[0x00005];/* Log base 2 of number of supported EEs. */\r
- pseudo_bit_t reserved3[0x00002];\r
- pseudo_bit_t eec_base_addr_l[0x00019];/* EEC Base Address [31:7]\r
- Table must be aligned on its size\r
- Address may be set to zero if RD is not supported. */\r
-/* -------------- */\r
- pseudo_bit_t srqc_base_addr_h[0x00020];/* SRQ Context Base Address [63:32]\r
- Table must be aligned on its size\r
- Address may be set to zero if SRQ is not supported. */\r
-/* -------------- */\r
- pseudo_bit_t log_num_of_srq[0x00005];/* Log base 2 of number of supported SRQs. */\r
- pseudo_bit_t srqc_base_addr_l[0x0001b];/* SRQ Context Base Address [31:5]\r
- Table must be aligned on its size\r
- Address may be set to zero if SRQ is not supported. */\r
-/* -------------- */\r
- pseudo_bit_t cqc_base_addr_h[0x00020];/* CQC Base Address [63:32]\r
- Table must be aligned on its size */\r
-/* -------------- */\r
- pseudo_bit_t log_num_of_cq[0x00005];/* Log base 2 of number of supported CQs. */\r
- pseudo_bit_t reserved4[0x00001];\r
- pseudo_bit_t cqc_base_addr_l[0x0001a];/* CQC Base Address [31:6]\r
- Table must be aligned on its size */\r
-/* -------------- */\r
- pseudo_bit_t reserved5[0x00040];\r
-/* -------------- */\r
- pseudo_bit_t eqpc_base_addr_h[0x00020];/* Extended QPC Base Address [63:32]\r
- Table has same number of entries as QPC table.\r
- Table must be aligned to entry size. */\r
-/* -------------- */\r
- pseudo_bit_t eqpc_base_addr_l[0x00020];/* Extended QPC Base Address [31:0]\r
- Table has same number of entries as QPC table.\r
- Table must be aligned to entry size. */\r
-/* -------------- */\r
- pseudo_bit_t reserved6[0x00040];\r
-/* -------------- */\r
- pseudo_bit_t eeec_base_addr_h[0x00020];/* Extended EEC Base Address [63:32]\r
- Table has same number of entries as EEC table.\r
- Table must be aligned to entry size.\r
- Address may be set to zero if RD is not supported. */\r
-/* -------------- */\r
- pseudo_bit_t eeec_base_addr_l[0x00020];/* Extended EEC Base Address [31:0]\r
- Table has same number of entries as EEC table.\r
- Table must be aligned to entry size.\r
- Address may be set to zero if RD is not supported. */\r
-/* -------------- */\r
- pseudo_bit_t reserved7[0x00040];\r
-/* -------------- */\r
- pseudo_bit_t eqc_base_addr_h[0x00020];/* EQC Base Address [63:32]\r
- Address may be set to zero if EQs are not supported.\r
- Table must be aligned to entry size. */\r
-/* -------------- */\r
- pseudo_bit_t log_num_eq[0x00004]; /* Log base 2 of number of supported EQs.\r
- Must be 6 or less in InfiniHost. */\r
- pseudo_bit_t reserved8[0x00002];\r
- pseudo_bit_t eqc_base_addr_l[0x0001a];/* EQC Base Address [31:6]\r
- Address may be set to zero if EQs are not supported.\r
- Table must be aligned to entry size. */\r
-/* -------------- */\r
- pseudo_bit_t reserved9[0x00040];\r
-/* -------------- */\r
- pseudo_bit_t rdb_base_addr_h[0x00020];/* Base address of table that holds remote read and remote atomic requests [63:32]. \r
- Table must be aligned to RDB entry size (32 bytes).\r
- Address may be set to zero if remote RDMA reads are not supported.\r
- Please refer to QP and EE chapter for further explanation on RDB allocation. */\r
-/* -------------- */\r
- pseudo_bit_t rdb_base_addr_l[0x00020];/* Base address of table that holds remote read and remote atomic requests [31:0]. \r
- Table must be aligned to RDB entry size (32 bytes).\r
- This field must always be zero. \r
- Please refer to QP and EE chapter for further explanation on RDB allocation. */\r
-/* -------------- */\r
- pseudo_bit_t reserved10[0x00040];\r
-/* -------------- */\r
-}; \r
-\r
-/* Performance Monitors */\r
-\r
-struct tavorprm_performance_monitors_st { /* Little Endian */\r
- pseudo_bit_t e0[0x00001]; /* Enables counting of respective performance counter */\r
- pseudo_bit_t e1[0x00001]; /* Enables counting of respective performance counter */\r
- pseudo_bit_t e2[0x00001]; /* Enables counting of respective performance counter */\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t r0[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */\r
- pseudo_bit_t r1[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */\r
- pseudo_bit_t r2[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */\r
- pseudo_bit_t reserved1[0x00001];\r
- pseudo_bit_t i0[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */\r
- pseudo_bit_t i1[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */\r
- pseudo_bit_t i2[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */\r
- pseudo_bit_t reserved2[0x00001];\r
- pseudo_bit_t f0[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */\r
- pseudo_bit_t f1[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */\r
- pseudo_bit_t f2[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */\r
- pseudo_bit_t reserved3[0x00001];\r
- pseudo_bit_t ev_cnt1[0x00005]; /* Specifies event to be counted by Event_counter1 See XXX for events' definition. */\r
- pseudo_bit_t reserved4[0x00003];\r
- pseudo_bit_t ev_cnt2[0x00005]; /* Specifies event to be counted by Event_counter2 See XXX for events' definition. */\r
- pseudo_bit_t reserved5[0x00003];\r
-/* -------------- */\r
- pseudo_bit_t clock_counter[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t event_counter1[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t event_counter2[0x00020];/* Read/write event counter, counting events specified by EvCntl and EvCnt2 fields repsectively. When the event counter reaches is maximum value of 0xFFFFFF, the next event will cause it to roll over to zero, set F1 or F2 bit respectively and generate interrupt by I1 I2 bit respectively. */\r
-/* -------------- */\r
-}; \r
-\r
-/* QP and EE Context Entry */\r
-\r
-struct tavorprm_queue_pair_ee_context_entry_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00008];\r
- pseudo_bit_t de[0x00001]; /* Send/Receive Descriptor Event enable - if set, events can be generated upon descriptors' completion on send/receive queue (controlled by E bit in WQE). Invalid in EE context */\r
- pseudo_bit_t reserved1[0x00002];\r
- pseudo_bit_t pm_state[0x00002]; /* Path migration state (Migrated, Armed or Rearm)\r
- 11-Migrated\r
- 00-Armed\r
- 01-Rearm\r
- 10-Reserved\r
- Should be set to 11 for UD QPs and for QPs which do not support APM */\r
- pseudo_bit_t reserved2[0x00003];\r
- pseudo_bit_t st[0x00003]; /* Service type (invalid in EE context):\r
- 000-Reliable Connection\r
- 001-Unreliable Connection\r
- 010-Reliable Datagram (Not supported for InfiniHost MT23108)\r
- 011-Unreliable Datagram\r
- 111-MLX transport (raw bits injection). Used for management QPs and RAW */\r
- pseudo_bit_t reserved3[0x00009];\r
- pseudo_bit_t state[0x00004]; /* QP/EE state:\r
- 0 - RST\r
- 1 - INIT\r
- 2 - RTR\r
- 3 - RTS\r
- 4 - SQEr\r
- 5 - SQD (Send Queue Drained)\r
- 6 - ERR\r
- 7 - Send Queue Draining\r
- 8 - F - RESERVED\r
- (Valid for QUERY_QPEE and ERR2RST_QPEE commands only) */\r
-/* -------------- */\r
- pseudo_bit_t sched_queue[0x00004]; /* Schedule queue to be used for WQE scheduling to execution. Determines QOS for this QP. */\r
- pseudo_bit_t reserved4[0x0001c];\r
-/* -------------- */\r
- pseudo_bit_t reserved5[0x00018];\r
- pseudo_bit_t msg_max[0x00005]; /* Max message size allowed on the QP. Maximum message size is 2^msg_Max.\r
- Must be equal to MTU for UD and MLX QPs. */\r
- pseudo_bit_t mtu[0x00003]; /* MTU of the QP (Must be the same for both paths: primary and alternative):\r
- 0x1 - 256 bytes\r
- 0x2 - 512\r
- 0x3 - 1024\r
- 0x4 - 2048\r
- other - reserved\r
- \r
- Should be configured to 0x4 for UD and MLX QPs. */\r
-/* -------------- */\r
- pseudo_bit_t usr_page[0x00018]; /* Index (offset) of user page allocated for this QP (see "non_privileged Access to the HCA Hardware"). Not valid (reserved) in EE context. */\r
- pseudo_bit_t reserved6[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t local_qpn_een[0x00018];/* Local QP/EE number Lower bits determine position of this record in QPC table, and - thus - constrained\r
- This field is valid for QUERY and ERR2RST commands only. */\r
- pseudo_bit_t reserved7[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t remote_qpn_een[0x00018];/* Remote QP/EE number */\r
- pseudo_bit_t reserved8[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t reserved9[0x00040];\r
-/* -------------- */\r
- struct tavorprm_address_path_st primary_address_path;/* Primary address path for the QP/EE */\r
-/* -------------- */\r
- struct tavorprm_address_path_st alternative_address_path;/* Alternate address path for the QP/EE */\r
-/* -------------- */\r
- pseudo_bit_t rdd[0x00018]; /* Reliable Datagram Domain */\r
- pseudo_bit_t reserved10[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t pd[0x00018]; /* QP protection domain. Not valid (reserved) in EE context. */\r
- pseudo_bit_t reserved11[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t wqe_base_adr[0x00020]; /* Bits 63:32 of WQE address for both SQ and RQ. \r
- Reserved for EE context. */\r
-/* -------------- */\r
- pseudo_bit_t wqe_lkey[0x00020]; /* memory key (L-Key) to be used to access WQEs. Not valid (reserved) in EE context. */\r
-/* -------------- */\r
- pseudo_bit_t reserved12[0x00003];\r
- pseudo_bit_t ssc[0x00001]; /* Send Signaled Completion\r
- 1 - all send WQEs generate CQEs. \r
- 0 - only send WQEs with C bit set generate completion. \r
- Not valid (reserved) in EE context. */\r
- pseudo_bit_t sic[0x00001]; /* If set - Ignore end to end credits on send queue. Not valid (reserved) in EE context. */\r
- pseudo_bit_t cur_retry_cnt[0x00003];/* Current transport retry counter (QUERY_QPEE only).\r
- The current transport retry counter can vary from retry_count down to 1, where 1 means that the last retry attempt is currently executing. */\r
- pseudo_bit_t cur_rnr_retry[0x00003];/* Current RNR retry counter (QUERY_QPEE only).\r
- The current RNR retry counter can vary from rnr_retry to 1, where 1 means that the last retry attempt is currently executing. */\r
- pseudo_bit_t reserved13[0x00002];\r
- pseudo_bit_t sae[0x00001]; /* If set - Atomic operations enabled on send queue. Not valid (reserved) in EE context. */\r
- pseudo_bit_t swe[0x00001]; /* If set - RDMA - write enabled on send queue. Not valid (reserved) in EE context. */\r
- pseudo_bit_t sre[0x00001]; /* If set - RDMA - read enabled on send queue. Not valid (reserved) in EE context. */\r
- pseudo_bit_t retry_count[0x00003]; /* Transport timeout Retry count */\r
- pseudo_bit_t reserved14[0x00002];\r
- pseudo_bit_t sra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed in the send queue. Maximum number is 2^SRA_Max. Must be zero in EE context. */\r
- pseudo_bit_t flight_lim[0x00004]; /* Number of outstanding (in-flight) messages on the wire allowed for this send queue. \r
- Number of outstanding messages is 2^Flight_Lim. \r
- Use 0xF for unlimited number of outstanding messages. */\r
- pseudo_bit_t ack_req_freq[0x00004]; /* ACK required frequency. ACK required bit will be set in every 2^AckReqFreq packets at least. Not valid for RD QP. */\r
-/* -------------- */\r
- pseudo_bit_t reserved15[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t next_send_psn[0x00018];/* Next PSN to be sent */\r
- pseudo_bit_t reserved16[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t cqn_snd[0x00018]; /* CQ number completions from the send queue to be reported to. Not valid (reserved) in EE context. */\r
- pseudo_bit_t reserved17[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t next_snd_wqe_0[0x00020];/* Pointer and properties of next WQE on send queue. The format is same as next segment (first 8 bytes) in the WQE. This field is read-only and provided for debug purposes. Not valid (reserved) in EE context. */\r
-/* -------------- */\r
- pseudo_bit_t next_snd_wqe_1[0x00020];/* Pointer and properties of next WQE on send queue. The format is same as next segment (first 8 bytes) in the WQE. This field is read-only and provided for debug purposes. Not valid (reserved) in EE context. */\r
-/* -------------- */\r
- pseudo_bit_t last_acked_psn[0x00018];/* The last acknowledged PSN for the requester (QUERY_QPEE only) */\r
- pseudo_bit_t reserved18[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t ssn[0x00018]; /* Requester Send Sequence Number (QUERY_QPEE only) */\r
- pseudo_bit_t reserved19[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t reserved20[0x00003];\r
- pseudo_bit_t rsc[0x00001]; /* 1 - all receive WQEs generate CQEs. \r
- 0 - only receive WQEs with C bit set generate completion. \r
- Not valid (reserved) in EE context.\r
- */\r
- pseudo_bit_t ric[0x00001]; /* Invalid Credits. \r
- 1 - place "Invalid Credits" to ACKs sent from this queue.\r
- 0 - ACKs report the actual number of end to end credits on the connection. \r
- Not valid (reserved) in EE context.\r
- Must be set to 1 on QPs which are attached to SRQ. */\r
- pseudo_bit_t reserved21[0x00008];\r
- pseudo_bit_t rae[0x00001]; /* If set - Atomic operations enabled. on receive queue. Not valid (reserved) in EE context. */\r
- pseudo_bit_t rwe[0x00001]; /* If set - RDMA - write enabled on receive queue. Not valid (reserved) in EE context. */\r
- pseudo_bit_t rre[0x00001]; /* If set - RDMA - read enabled on receive queue. Not valid (reserved) in EE context. */\r
- pseudo_bit_t reserved22[0x00005];\r
- pseudo_bit_t rra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed on receive queue is 2^RRA_Max. \r
- Must be 0 for EE context. */\r
- pseudo_bit_t reserved23[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t next_rcv_psn[0x00018]; /* Next (expected) PSN on receive */\r
- pseudo_bit_t min_rnr_nak[0x00005]; /* Minimum RNR NAK timer value (TTTTT field encoding according to the IB spec Vol1 9.7.5.2.8). \r
- Not valid (reserved) in EE context. */\r
- pseudo_bit_t reserved24[0x00003];\r
-/* -------------- */\r
- pseudo_bit_t reserved25[0x00005];\r
- pseudo_bit_t ra_buff_indx[0x0001b]; /* Index to outstanding read/atomic buffer. \r
- This field constructs the address to the RDB for maintaining the incoming RDMA read and atomic requests. */\r
-/* -------------- */\r
- pseudo_bit_t cqn_rcv[0x00018]; /* CQ number completions from receive queue to be reported to. Not valid (reserved) in EE context. */\r
- pseudo_bit_t reserved26[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t next_rcv_wqe_0[0x00020];/* Pointer and properties of next WQE on the receive queue. This format is same as next segment (first 8 bytes) in the WQE.This field is read-only and provided for debug purposes. Not valid (reserved) in EE context. */\r
-/* -------------- */\r
- pseudo_bit_t next_rcv_wqe_1[0x00020];/* Pointer and properties of next WQE on the receive queue. This format is same as next segment (first 8 bytes) in the WQE.This field is read-only and provided for debug purposes. Not valid (reserved) in EE context. */\r
-/* -------------- */\r
- pseudo_bit_t q_key[0x00020]; /* Q_Key to be validated against received datagrams.\r
- On send datagrams, if Q_Key[31] specified in the WQE is set, then this Q_Key will be transmitted in the outgoing message.\r
- Not valid (reserved) in EE context. */\r
-/* -------------- */\r
- pseudo_bit_t srqn[0x00018]; /* SRQN - Shared Receive Queue Number - specifies the SRQ number from which the QP dequeues receive descriptors. \r
- SRQN is valid only if SRQ bit is set. Not valid (reserved) in EE context. */\r
- pseudo_bit_t srq[0x00001]; /* SRQ - Shared Receive Queue. If this bit is set, then the QP is associated with a SRQ. Not valid (reserved) in EE context. */\r
- pseudo_bit_t reserved27[0x00007];\r
-/* -------------- */\r
- pseudo_bit_t rmsn[0x00018]; /* Responder current message sequence number (QUERY_QPEE only) */\r
- pseudo_bit_t reserved28[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t reserved29[0x00260];\r
-/* -------------- */\r
-}; \r
-\r
-/* MOD_STAT_CFG */\r
-\r
-struct tavorprm_mod_stat_cfg_st { /* Little Endian */\r
- pseudo_bit_t log_max_srqs[0x00005]; /* Log (base 2) of the number of SRQs to allocate (0 if no SRQs are required), valid only if srq bit is set. */\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t srq[0x00001]; /* When set SRQs are supported */\r
- pseudo_bit_t srq_m[0x00001]; /* Modify SRQ parameters */\r
- pseudo_bit_t reserved1[0x00018];\r
-/* -------------- */\r
- pseudo_bit_t tpt_map[0x00004];\r
- pseudo_bit_t reserved2[0x00003];\r
- pseudo_bit_t tpt_map_m[0x00001];\r
- pseudo_bit_t reserved3[0x00018];\r
-/* -------------- */\r
- pseudo_bit_t reserved4[0x007c0];\r
-/* -------------- */\r
-}; \r
-\r
-/* SRQ Context */\r
-\r
-struct tavorprm_srq_context_st { /* Little Endian */\r
- pseudo_bit_t wqe_addr_h[0x00020]; /* WQE base address for the SRQ [63:32]\r
- Must be set at SW2HW_SRQ */\r
-/* -------------- */\r
- pseudo_bit_t ds[0x00006]; /* Descriptor Size on the SRQ in units of 16 bytes */\r
- pseudo_bit_t next_wqe_addr_l[0x0001a];/* Next WQE address for the SRQ [31:6] \r
- Valid only on QUERY_SRQ and HW2SW_SRQ commands. */\r
-/* -------------- */\r
- pseudo_bit_t pd[0x00018]; /* SRQ PD - used for descriptor fetching on the SRQ and for data scatter on send operations on QPs attached to SRQ.\r
- In InfiniHost MT23108 SRQ.PD must be equal to the PD of all QPs which are attached to the SRQ */\r
- pseudo_bit_t reserved0[0x00004];\r
- pseudo_bit_t state[0x00004]; /* SRQ State:\r
- 1111 - SW Ownership\r
- 0000 - HW Ownership\r
- 0001 - Error\r
- Valid only on QUERY_SRQ and HW2SW_SRQ commands. */\r
-/* -------------- */\r
- pseudo_bit_t l_key[0x00020]; /* L_Key for descriptor fetching on the SRQ */\r
-/* -------------- */\r
- pseudo_bit_t uar[0x00018]; /* SRQ User Access Region - Index (offset) of user page allocated for the SRQ (see "Non Privileged Access to the HCA HW"). */\r
- pseudo_bit_t reserved1[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t wqe_cnt[0x00010]; /* WQE count on the SRQ. \r
- Valid only on QUERY_SRQ and HW2SW_SRQ commands. */\r
- pseudo_bit_t reserved2[0x00010];\r
-/* -------------- */\r
- pseudo_bit_t reserved3[0x00010];\r
- pseudo_bit_t reserved4[0x00010];\r
-/* -------------- */\r
- pseudo_bit_t reserved5[0x00020];\r
-/* -------------- */\r
-}; \r
-\r
-/* InfiniHost Configuration Registers */\r
-\r
-struct tavorprm_mt23108_configuration_registers_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x403400];\r
-/* -------------- */\r
- struct tavorprm_hca_command_register_st hca_command_interface_register;/* HCA Command Register */\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x00320];\r
-/* -------------- */\r
- pseudo_bit_t ecr_h[0x00020]; /* Event Cause Register[63:32]. Each bit in the ECR corresponds to one of the 64 Event Queues in InfiniHost. If bit is set, interrupt was asserted due to event reported on corresponding event queue. This register is read-only; writing to this register will cause undefined results\r
- */\r
-/* -------------- */\r
- pseudo_bit_t ecr_l[0x00020]; /* Event Cause Register[31:0]. Each bit in the ECR corresponds to one of the 64 Event Queues in InfiniHost. If bit is set, interrupt was asserted due to event reported on corresponding event queue. This register is read-only; writing to this register will cause undefined results\r
- */\r
-/* -------------- */\r
- pseudo_bit_t clr_ecr_h[0x00020]; /* Clear Event Cause Register[63:32]. \r
- This register is used to clear bits in ECR register. Each set bit in data written to this register clears corresponding bit in the ECR register, Each bit written with zero has no effect. This register is write-only. Reading from this register will cause undefined result\r
- */\r
-/* -------------- */\r
- pseudo_bit_t clr_ecr_l[0x00020]; /* Clear Event Cause Register[31:0]. \r
- This register is used to clear bits in ECR register. Each set bit in data written to this register clears corresponding bit in the ECR register, Each bit written with zero has no effect. This register is write-only. Reading from this register will cause undefined result\r
- */\r
-/* -------------- */\r
- pseudo_bit_t reserved2[0x4c780];\r
-/* -------------- */\r
- pseudo_bit_t reserved3[0x01000];\r
-/* -------------- */\r
- pseudo_bit_t reserved4[0x32f6c0];\r
-/* -------------- */\r
- pseudo_bit_t clr_int_h[0x00020]; /* Clear Interrupt [63:32]\r
- This register is used to clear (de-assert) interrupt output pins of InfiniHost. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. This register is write-only. Reading from this register will cause undefined result */\r
-/* -------------- */\r
- pseudo_bit_t clr_int_l[0x00020]; /* Clear Interrupt [31:0]\r
- This register is used to clear (de-assert) interrupt output pins of InfiniHost. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. This register is write-only. Reading from this register will cause undefined result */\r
-/* -------------- */\r
- pseudo_bit_t reserved5[0x7f900];\r
-/* -------------- */\r
-}; \r
-\r
-/* Schedule queues configuration */\r
-\r
-struct tavorprm_cfg_schq_st { /* Little Endian */\r
- pseudo_bit_t quota[0x00008]; /* Number of WQEs that are executed until preemption of the scheduling queue and switching to the next schedule queue */\r
- pseudo_bit_t reserved0[0x00018];\r
-/* -------------- */\r
- pseudo_bit_t rqsq0[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq0[0x00008]; /* Weight for responder schedule queue */\r
- pseudo_bit_t rqsq1[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq1[0x00008]; /* Weight for responder schedule queue */\r
-/* -------------- */\r
- pseudo_bit_t rqsq2[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq2[0x00008]; /* Weight for responder schedule queue */\r
- pseudo_bit_t rqsq3[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq3[0x00008]; /* Weight for responder schedule queue */\r
-/* -------------- */\r
- pseudo_bit_t rqsq4[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq4[0x00008]; /* Weight for responder schedule queue */\r
- pseudo_bit_t rqsq5[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq5[0x00008]; /* Weight for responder schedule queue */\r
-/* -------------- */\r
- pseudo_bit_t rqsq6[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq6[0x00008]; /* Weight for responder schedule queue */\r
- pseudo_bit_t rqsq7[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq7[0x00008]; /* Weight for responder schedule queue */\r
-/* -------------- */\r
- pseudo_bit_t rqsq8[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq8[0x00008]; /* Weight for responder schedule queue */\r
- pseudo_bit_t rqsq9[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq9[0x00008]; /* Weight for responder schedule queue */\r
-/* -------------- */\r
- pseudo_bit_t rqsq10[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq10[0x00008]; /* Weight for responder schedule queue */\r
- pseudo_bit_t rqsq11[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq11[0x00008]; /* Weight for responder schedule queue */\r
-/* -------------- */\r
- pseudo_bit_t rqsq12[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq12[0x00008]; /* Weight for responder schedule queue */\r
- pseudo_bit_t rqsq13[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq13[0x00008]; /* Weight for responder schedule queue */\r
-/* -------------- */\r
- pseudo_bit_t rqsq14[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq14[0x00008]; /* Weight for responder schedule queue */\r
- pseudo_bit_t rqsq15[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq15[0x00008]; /* Weight for responder schedule queue */\r
-/* -------------- */\r
- pseudo_bit_t rqsq16[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq16[0x00008]; /* Weight for responder schedule queue */\r
- pseudo_bit_t rqsq17[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq17[0x00008]; /* Weight for responder schedule queue */\r
-/* -------------- */\r
- pseudo_bit_t rqsq18[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq18[0x00008]; /* Weight for responder schedule queue */\r
- pseudo_bit_t rqsq19[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq19[0x00008]; /* Weight for responder schedule queue */\r
-/* -------------- */\r
- pseudo_bit_t rqsq20[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq20[0x00008]; /* Weight for responder schedule queue */\r
- pseudo_bit_t rqsq21[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq21[0x00008]; /* Weight for responder schedule queue */\r
-/* -------------- */\r
- pseudo_bit_t rqsq22[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq22[0x00008]; /* Weight for responder schedule queue */\r
- pseudo_bit_t rqsq23[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq23[0x00008]; /* Weight for responder schedule queue */\r
-/* -------------- */\r
- pseudo_bit_t rqsq24[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq24[0x00008]; /* Weight for responder schedule queue */\r
- pseudo_bit_t rqsq25[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq25[0x00008]; /* Weight for responder schedule queue */\r
-/* -------------- */\r
- pseudo_bit_t rqsq26[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq26[0x00008]; /* Weight for responder schedule queue */\r
- pseudo_bit_t rqsq27[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq27[0x00008]; /* Weight for responder schedule queue */\r
-/* -------------- */\r
- pseudo_bit_t rqsq28[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq28[0x00008]; /* Weight for responder schedule queue */\r
- pseudo_bit_t rqsq29[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq29[0x00008]; /* Weight for responder schedule queue */\r
-/* -------------- */\r
- pseudo_bit_t rqsq30[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq30[0x00008]; /* Weight for responder schedule queue */\r
- pseudo_bit_t rqsq31[0x00008]; /* Weight for requestor schedule queue */\r
- pseudo_bit_t rssq31[0x00008]; /* Weight for responder schedule queue */\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x005e0];\r
-/* -------------- */\r
-}; \r
-\r
-/* Query BAR */\r
-\r
-struct tavorprm_query_bar_st { /* Little Endian */\r
- pseudo_bit_t bar_base_h[0x00020]; /* BAR base [63:32] */\r
-/* -------------- */\r
- pseudo_bit_t reserved0[0x00014];\r
- pseudo_bit_t bar_base_l[0x0000c]; /* BAR base [31:20] */\r
-/* -------------- */\r
-}; \r
-\r
-/* Performance Counters */\r
-\r
-struct tavorprm_performance_counters_st { /* Little Endian */\r
- pseudo_bit_t sqpc_access_cnt[0x00020];/* SQPC cache access count */\r
-/* -------------- */\r
- pseudo_bit_t sqpc_miss_cnt[0x00020];/* SQPC cache miss count */\r
-/* -------------- */\r
- pseudo_bit_t reserved0[0x00040];\r
-/* -------------- */\r
- pseudo_bit_t rqpc_access_cnt[0x00020];/* RQPC cache access count */\r
-/* -------------- */\r
- pseudo_bit_t rqpc_miss_cnt[0x00020];/* RQPC cache miss count */\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x00040];\r
-/* -------------- */\r
- pseudo_bit_t cqc_access_cnt[0x00020];/* CQC cache access count */\r
-/* -------------- */\r
- pseudo_bit_t cqc_miss_cnt[0x00020]; /* CQC cache miss count */\r
-/* -------------- */\r
- pseudo_bit_t reserved2[0x00040];\r
-/* -------------- */\r
- pseudo_bit_t tpt_access_cnt[0x00020];/* TPT cache access count */\r
-/* -------------- */\r
- pseudo_bit_t mpt_miss_cnt[0x00020]; /* MPT cache miss count */\r
-/* -------------- */\r
- pseudo_bit_t mtt_miss_cnt[0x00020]; /* MTT cache miss count */\r
-/* -------------- */\r
- pseudo_bit_t reserved3[0x00620];\r
-/* -------------- */\r
-}; \r
-\r
-/* Transport and CI Error Counters */\r
-\r
-struct tavorprm_transport_and_ci_error_counters_st { /* Little Endian */\r
- pseudo_bit_t rq_num_lle[0x00020]; /* Responder - number of local length errors.\r
- Local Length Errors: Inbound "Send" request message exceeded the responders available buffer space. */\r
-/* -------------- */\r
- pseudo_bit_t sq_num_lle[0x00020]; /* Requester - number of local length errors.\r
- Length Errors: RDMA READ response message contained too much or too little payload data. */\r
-/* -------------- */\r
- pseudo_bit_t rq_num_lqpoe[0x00020]; /* Responder - number local QP operation error.\r
- 1. Malformed WQE: Responder detected a malformed Receive Queue WQE while processing the packet.\r
- 2. Local QP Error: Responder detected a local QP related error while executing the request message. The local error prevented the responder from completing the request. */\r
-/* -------------- */\r
- pseudo_bit_t sq_num_lqpoe[0x00020]; /* Requester - number local QP operation error\r
- 1. Local Operation Error: (WQE gather, affiliated or unaffiliated): An error occurred in the requesters local channel interface that either cannot be associated with a certain WQE, or occurred when reading a WQE.\r
- */\r
-/* -------------- */\r
- pseudo_bit_t rq_num_leeoe[0x00020]; /* Responder - number local EE operation error.\r
- RD */\r
-/* -------------- */\r
- pseudo_bit_t sq_num_leeoe[0x00020]; /* Requester - number local EE operation error.\r
- RD */\r
-/* -------------- */\r
- pseudo_bit_t rq_num_lpe[0x00020]; /* Responder - number of local protection errors.\r
- Local QP (Protection) Error: Responder detected a local access violation error while executing a send request message. The error prevented the responder from completing the request. */\r
-/* -------------- */\r
- pseudo_bit_t sq_num_lpe[0x00020]; /* Requester - number of local protection errors.\r
- Local Memory Protection Error: Requester detected a memory translation/protection (TPT) error.\r
- */\r
-/* -------------- */\r
- pseudo_bit_t rq_num_wrfe[0x00020]; /* Responder - number of WR flushed errors.\r
- Incremented each time a CQE with error is generated. */\r
-/* -------------- */\r
- pseudo_bit_t sq_num_wrfe[0x00020]; /* Requester - number of WR flushed errors.\r
- Incremented each time a CQE with error is generated. */\r
-/* -------------- */\r
- pseudo_bit_t reserved0[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t sq_num_mwbe[0x00020]; /* Requester - number of memory window bind errors. */\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t sq_num_bre[0x00020]; /* Requester - number of bad response errors.\r
- Bad response: Unexpected opcode for the response packet received at the expected response PSN. */\r
-/* -------------- */\r
- pseudo_bit_t rq_num_lae[0x00020]; /* Responder - number of local access errors.\r
- Unused. */\r
-/* -------------- */\r
- pseudo_bit_t reserved2[0x00040];\r
-/* -------------- */\r
- pseudo_bit_t sq_num_rire[0x00020]; /* Requester - number of remote invalid request errors.\r
- NAK-Invalid Request on:\r
- 1. Unsupported OpCode: Responder detected an unsupported OpCode.\r
- 2. Unexpected OpCode: Responder detected an error in the sequence of OpCodes, such as a missing "Last" packet.\r
- Note: there is no PSN error, thus this does not indicate a dropped packet. */\r
-/* -------------- */\r
- pseudo_bit_t rq_num_rire[0x00020]; /* Responder - number of remote invalid request errors.\r
- NAK may or may not be sent.\r
- 1. Unsupported or Reserved OpCode: Inbound request OpCode was either reserved, or was for a function not supported by this QP. (E.G. RDMA or ATOMIC on QP not set up for this). For RC this is "QP Async affiliated".\r
- 2. Misaligned ATOMIC: VA does not point to an aligned address on an atomic operation.\r
- 3. Too many RDMA READ or ATOMIC Requests: There were more requests received and not ACKed than allowed for the connection.\r
- 4. Out of Sequence OpCode, current packet is "first" or "Only": The Responder detected an error in the sequence of OpCodes; a missing "Last" packet\r
- 5. Out of Sequence OpCode, current packet is not "first" or "Only": The Responder detected an error in the sequence of OpCodes; a missing "First" packet\r
- 6. Local Length Error: Inbound "Send" request message exceeded the responder.s available buffer space.\r
- 7. Length error: RDMA WRITE request message contained too much or too little payload data compared to the DMA length advertised in the first or only packet.\r
- 8. Length error: Payload length was not consistent with the opcode: \r
- a: 0 byte <= "only" <= PMTU bytes\r
- b: ("first" or "middle") == PMTU bytes\r
- c: 1byte <= "last" <= PMTU bytes \r
- 9. Length error: Inbound message exceeded the size supported by the CA port. */\r
-/* -------------- */\r
- pseudo_bit_t sq_num_rae[0x00020]; /* Requester - number of remote access errors.\r
- NAK-Remote Access Error on:\r
- R_Key Violation: Responder detected an invalid R_Key while executing an RDMA Request. */\r
-/* -------------- */\r
- pseudo_bit_t rq_num_rae[0x00020]; /* Responder - number of remote access errors.\r
- R_Key Violation Responder detected an R_Key violation while executing an RDMA request.\r
- NAK may or may not be sent. */\r
-/* -------------- */\r
- pseudo_bit_t sq_num_roe[0x00020]; /* Requester - number of remote operation errors.\r
- NAK-Remote Operation Error on:\r
- Remote Operation Error: Responder encountered an error, (local to the responder), which prevented it from completing the request. */\r
-/* -------------- */\r
- pseudo_bit_t rq_num_roe[0x00020]; /* Responder - number of remote operation errors.\r
- NAK-Remote Operation Error on:\r
- 1. Malformed WQE: Responder detected a malformed Receive Queue WQE while processing the packet.\r
- 2. Remote Operation Error: Responder encountered an error, (local to the responder), which prevented it from completing the request. */\r
-/* -------------- */\r
- pseudo_bit_t sq_num_tree[0x00020]; /* Requester - number of transport retries exceeded errors.\r
- 1. Packet sequence error: Retry limit exceeded. Responder detected a PSN larger than it expected. The requestor performed retries, and automatic path migration and additional retries, if applicable, but all attempts failed.\r
- 2. Implied NAK sequence error: Retry limit exceeded. Requestor detected an ACK with a PSN larger than the expected PSN for an RDMA READ or atomic response. The requestor performed retries, and automatic path migration and additional retries, if applicable, but all attempts failed.\r
- 3. Local Ack Timeout error: Retry limit exceeded. No ACK response within timer interval. The requestor performed retries, and automatic path migration and additional retries, but all attempts failed. */\r
-/* -------------- */\r
- pseudo_bit_t reserved3[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t sq_num_rree[0x00020]; /* Requester - number of RNR nak retries exceeded errors.\r
- RNR NAK Retry error. Retry limit exceeded. Excessive RNR NAKs returned by the responder: Requestor retried the request "n" times, but received RNR NAK each time. */\r
-/* -------------- */\r
- pseudo_bit_t reserved4[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t sq_num_lrdve[0x00020]; /* Requester - number of local RDD violation errors.\r
- RD only. */\r
-/* -------------- */\r
- pseudo_bit_t rq_num_rirdre[0x00020];/* Responder - number of remote invalid RD request errors.\r
- RD only. */\r
-/* -------------- */\r
- pseudo_bit_t reserved5[0x00040];\r
-/* -------------- */\r
- pseudo_bit_t sq_num_rabrte[0x00020];/* Requester - number of remote aborted errors.\r
- RD only. */\r
-/* -------------- */\r
- pseudo_bit_t reserved6[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t sq_num_ieecne[0x00020];/* Requester - number of invalid EE context number errors.\r
- RD only. */\r
-/* -------------- */\r
- pseudo_bit_t reserved7[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t sq_num_ieecse[0x00020];/* Requester - invalid EE context state errors.\r
- RD only. */\r
-/* -------------- */\r
- pseudo_bit_t reserved8[0x00380];\r
-/* -------------- */\r
- pseudo_bit_t rq_num_oos[0x00020]; /* Responder - number of out of sequence requests received.\r
- Out of Sequence Request Packet: Packet PSN of the inbound request is outside the responders valid PSN window.\r
- NAK may or may not be sent. */\r
-/* -------------- */\r
- pseudo_bit_t sq_num_oos[0x00020]; /* Requester - number of out of sequence Naks received.\r
- NAK-Sequence Error on:\r
- 1. Packet sequence error. Retry limit not exceeded: Responder detected a PSN larger than it expected. Requester may retry the request.\r
- 2. Packet sequence error. Retry limit exceeded: Responder detected a PSN larger than it expected. The requestor performed retries, and automatic path migration and additional retries, if applicable, but all attempts failed. */\r
-/* -------------- */\r
- pseudo_bit_t rq_num_mce[0x00020]; /* Responder - number of bad multicast packets received.\r
- Missing GID or bad GID. */\r
-/* -------------- */\r
- pseudo_bit_t reserved9[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t rq_num_rsync[0x00020]; /* Responder - number of RESYNC operations.\r
- RD only. */\r
-/* -------------- */\r
- pseudo_bit_t sq_num_rsync[0x00020]; /* Requester - number of RESYNC operations.\r
- RD only. */\r
-/* -------------- */\r
- pseudo_bit_t rq_num_udsdprd[0x00020];/* The number of UD packets silently discarded on the receive queue due to lack of receive descriptor.\r
- Resources Not Ready Error: A UD WQE is not currently available. */\r
-/* -------------- */\r
- pseudo_bit_t reserved10[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t rq_num_ucsdprd[0x00020];/* The number of UC packets silently discarded on the receive queue due to lack of receive descriptor.\r
- Resources Not Ready Error: A UC WQE is not currently available. */\r
-/* -------------- */\r
- pseudo_bit_t reserved11[0x003e0];\r
-/* -------------- */\r
- pseudo_bit_t num_cqovf[0x00020]; /* Number of CQ overflows.\r
- Incremented each time a completion is discarded due CQ overflow. */\r
-/* -------------- */\r
- pseudo_bit_t num_eqovf[0x00020]; /* Number of EQ overflows.\r
- Incremented each time EQ enters the overflow state. */\r
-/* -------------- */\r
- pseudo_bit_t num_baddb[0x00020]; /* Number of bad doorbells.\r
- Doorbell dropped due to UAR violation or bad resource state. */\r
-/* -------------- */\r
- pseudo_bit_t reserved12[0x002a0];\r
-/* -------------- */\r
-}; \r
-\r
-/* Event_data Field - HCR Completion Event */\r
-\r
-struct tavorprm_hcr_completion_event_st { /* Little Endian */\r
- pseudo_bit_t token[0x00010]; /* HCR Token */\r
- pseudo_bit_t reserved0[0x00010];\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t status[0x00008]; /* HCR Status */\r
- pseudo_bit_t reserved2[0x00018];\r
-/* -------------- */\r
- pseudo_bit_t out_param_h[0x00020]; /* HCR Output Parameter [63:32] */\r
-/* -------------- */\r
- pseudo_bit_t out_param_l[0x00020]; /* HCR Output Parameter [31:0] */\r
-/* -------------- */\r
- pseudo_bit_t reserved3[0x00020];\r
-/* -------------- */\r
-}; \r
-\r
-/* Completion with Error CQE */\r
-\r
-struct tavorprm_completion_with_error_st { /* Little Endian */\r
- pseudo_bit_t myqpn[0x00018]; /* Indicates the QP for which completion is being reported */\r
- pseudo_bit_t reserved0[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x00060];\r
-/* -------------- */\r
- pseudo_bit_t db_cnt[0x00010]; /* Doorbell count */\r
- pseudo_bit_t reserved2[0x00008];\r
- pseudo_bit_t syndrome[0x00008]; /* Completion with error syndrome:\r
- 0x01 - Local Length Error\r
- 0x02 - Local QP Operation Error\r
- 0x03 - Local EE Context Operation Error\r
- 0x04 - Local Protection Error\r
- 0x05 - Work Request Flushed Error \r
- 0x06 - Memory Window Bind Error\r
- 0x10 - Bad Response Error\r
- 0x11 - Local Access Error\r
- 0x12 - Remote Invalid Request Error\r
- 0x13 - Remote Access Error\r
- 0x14 - Remote Operation Error\r
- 0x15 - Transport Retry Counter Exceeded\r
- 0x16 - RNR Retry Counter Exceeded\r
- 0x20 - Local RDD Violation Error\r
- 0x21 - Remote Invalid RD Request\r
- 0x22 - Remote Aborted Error\r
- 0x23 - Invalid EE Context Number\r
- 0x24 - Invalid EE Context State\r
- other - Reserved\r
- Syndrome is defined according to the IB specification volume 1. For detailed explanation of the syndromes, refer to chapters 10-11 of the IB specification rev 1.1. */\r
-/* -------------- */\r
- pseudo_bit_t reserved3[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t wqe_size[0x00006]; /* Size (in 16-byte chunks) of WQE completion is reported for */\r
- pseudo_bit_t wqe_addr[0x0001a]; /* Bits 31:6 of WQE virtual address completion is reported for. The 6 least significant bits are zero. */\r
-/* -------------- */\r
- pseudo_bit_t reserved4[0x00007];\r
- pseudo_bit_t owner[0x00001]; /* Owner field. Zero value of this field means SW ownership of CQE. */\r
- pseudo_bit_t reserved5[0x00010];\r
- pseudo_bit_t opcode[0x00008]; /* The opcode of WQE completion is reported for.\r
- \r
- The following values are reported in case of completion with error:\r
- 0xFE - For completion with error on Receive Queues\r
- 0xFF - For completion with error on Send Queues */\r
-/* -------------- */\r
-}; \r
-\r
-/* Resize CQ Input Mailbox */\r
-\r
-struct tavorprm_resize_cq_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t start_addr_h[0x00020]; /* Start address of CQ[63:32]. \r
- Must be aligned on CQE size (32 bytes) */\r
-/* -------------- */\r
- pseudo_bit_t start_addr_l[0x00020]; /* Start address of CQ[31:0]. \r
- Must be aligned on CQE size (32 bytes) */\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x00018];\r
- pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries) */\r
- pseudo_bit_t reserved2[0x00003];\r
-/* -------------- */\r
- pseudo_bit_t reserved3[0x00060];\r
-/* -------------- */\r
- pseudo_bit_t l_key[0x00020]; /* Memory key (L_Key) to be used to access CQ */\r
-/* -------------- */\r
- pseudo_bit_t reserved4[0x00100];\r
-/* -------------- */\r
-}; \r
-\r
-/* SYS_EN Output Parameter */\r
-\r
-struct tavorprm_sys_en_out_param_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t spd[0x00001]; /* 0 - DIMM SPD was read from DIMM\r
- 1 - DIMM SPD was read from InfiniHost NVMEM */\r
- pseudo_bit_t sladr[0x00003]; /* SPD Slave Address 3 LSBits. \r
- Valid only if spd bit is 0. */\r
- pseudo_bit_t sock_num[0x00002]; /* DIMM socket number (for double sided DIMM one of the two numbers will be reported) */\r
- pseudo_bit_t syn[0x00004]; /* Error Syndrome\r
- 0 - reserved\r
- 1 - SPD error (e.g. checksum error, no response, error while reading)\r
- 2 - DIMM out of bounds (e.g. DIMM rows number is not between 7 and 14, DIMM type is not 2)\r
- 3 - DIMM conflict (e.g. mix of registered and unbuffered DIMMs, CAS latency conflict)\r
- 4 - Calibration error\r
- other - Error, reserved */\r
- pseudo_bit_t reserved1[0x00016];\r
-/* -------------- */\r
-}; \r
-\r
-/* Query Debug Message */\r
-\r
-struct tavorprm_query_debug_msg_st { /* Little Endian */\r
- pseudo_bit_t base_addr_h[0x00020]; /* Debug Buffers Base Address [63:32] */\r
-/* -------------- */\r
- pseudo_bit_t base_addr_l[0x00020]; /* Debug Buffers Base Address [31:0] */\r
-/* -------------- */\r
- pseudo_bit_t buf_sz[0x00020]; /* Debug Buffer Size (in bytes) */\r
-/* -------------- */\r
- pseudo_bit_t reserved0[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t trc_hdr_sz[0x00020]; /* Trace message header size in dwords. */\r
-/* -------------- */\r
- pseudo_bit_t trc_arg_num[0x00020]; /* The number of arguments per trace message. */\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x000c0];\r
-/* -------------- */\r
- pseudo_bit_t dbg_msk_h[0x00020]; /* Debug messages mask [63:32] */\r
-/* -------------- */\r
- pseudo_bit_t dbg_msk_l[0x00020]; /* Debug messages mask [31:0] */\r
-/* -------------- */\r
- pseudo_bit_t reserved2[0x00040];\r
-/* -------------- */\r
- pseudo_bit_t fs_base_addr0_h[0x00020];/* Base address for format string for irisc 0 bits[63:32] */\r
-/* -------------- */\r
- pseudo_bit_t fs_base_addr0_l[0x00020];/* Base address for format string for irisc 0 bits[31:0] */\r
-/* -------------- */\r
- pseudo_bit_t fs_base_addr1_h[0x00020];/* Base address for format string for irisc 1 bits[63:32] */\r
-/* -------------- */\r
- pseudo_bit_t fs_base_addr1_l[0x00020];/* Base address for format string for irisc 1 bits[31:0] */\r
-/* -------------- */\r
- pseudo_bit_t fs_base_addr2_h[0x00020];/* Base address for format string for irisc 2 bits[63:32] */\r
-/* -------------- */\r
- pseudo_bit_t fs_base_addr2_l[0x00020];/* Base address for format string for irisc 2 bits[31:0] */\r
-/* -------------- */\r
- pseudo_bit_t fs_base_addr3_h[0x00020];/* Base address for format string for irisc 3 bits[63:32] */\r
-/* -------------- */\r
- pseudo_bit_t fs_base_addr3_l[0x00020];/* Base address for format string for irisc 3 bits[31:0] */\r
-/* -------------- */\r
- pseudo_bit_t fs_base_addr4_h[0x00020];/* Base address for format string for irisc 4 bits[63:32] */\r
-/* -------------- */\r
- pseudo_bit_t fs_base_addr4_l[0x00020];/* Base address for format string for irisc 4 bits[31:0] */\r
-/* -------------- */\r
- pseudo_bit_t fs_base_addr5_h[0x00020];/* Base address for format string for irisc 5 bits[63:32] */\r
-/* -------------- */\r
- pseudo_bit_t fs_base_addr5_l[0x00020];/* Base address for format string for irisc 5 bits[31:0] */\r
-/* -------------- */\r
- pseudo_bit_t reserved3[0x00480];\r
-/* -------------- */\r
-}; \r
-\r
-/* User Access Region */\r
-\r
-struct tavorprm_uar_st { /* Little Endian */\r
- struct tavorprm_rd_send_doorbell_st rd_send_doorbell;/* Reliable Datagram SQ Doorbell */\r
-/* -------------- */\r
- struct tavorprm_send_doorbell_st send_doorbell;/* SQ Doorbell */\r
-/* -------------- */\r
- struct tavorprm_receive_doorbell_st receive_doorbell;/* RQ Doorbell */\r
-/* -------------- */\r
- struct tavorprm_cq_cmd_doorbell_st cq_command_doorbell;/* CQ Doorbell */\r
-/* -------------- */\r
- struct tavorprm_eq_cmd_doorbell_st eq_command_doorbell;/* EQ Doorbell */\r
-/* -------------- */\r
- pseudo_bit_t reserved0[0x01e80];\r
-/* -------------- */\r
- pseudo_bit_t infini_blast[256][0x00020];/* InfiniBlast buffer (same format as WQE format)\r
- Infiniblast is not supported by InfiniHost MT23108 */\r
-/* -------------- */\r
-}; \r
-\r
-/* SET_IB Parameters */\r
-\r
-struct tavorprm_set_ib_st { /* Little Endian */\r
- pseudo_bit_t rqk[0x00001]; /* Reset QKey Violation Counter */\r
- pseudo_bit_t reserved0[0x00011];\r
- pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified.\r
- system_image_guid and sig must be the same for all ports. */\r
- pseudo_bit_t reserved1[0x0000d];\r
-/* -------------- */\r
- pseudo_bit_t capability_mask[0x00020];/* PortInfo Capability Mask */\r
-/* -------------- */\r
- pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set\r
- Must be the same for both ports. */\r
-/* -------------- */\r
- pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set\r
- Must be the same for both ports. */\r
-/* -------------- */\r
- pseudo_bit_t reserved2[0x00180];\r
-/* -------------- */\r
-}; \r
-\r
-/* Multicast Group Member */\r
-\r
-struct tavorprm_mgm_entry_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00006];\r
- pseudo_bit_t next_gid_index[0x0001a];/* Index of next Multicast Group Member whose GID maps to same MGID_HASH number.\r
- The index is into the Multicast Group Table, which is the comprised the MGHT and AMGM tables.\r
- next_gid_index=0 means end of the chain. */\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x00060];\r
-/* -------------- */\r
- pseudo_bit_t mgid_128_96[0x00020]; /* Multicast group GID[128:96] in big endian format.\r
- Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */\r
-/* -------------- */\r
- pseudo_bit_t mgid_95_64[0x00020]; /* Multicast group GID[95:64] in big endian format.\r
- Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */\r
-/* -------------- */\r
- pseudo_bit_t mgid_63_32[0x00020]; /* Multicast group GID[63:32] in big endian format.\r
- Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */\r
-/* -------------- */\r
- pseudo_bit_t mgid_31_0[0x00020]; /* Multicast group GID[31:0] in big endian format.\r
- Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */\r
-/* -------------- */\r
- struct tavorprm_mgmqp_st mgmqp_0; /* Multicast Group Member QP */\r
-/* -------------- */\r
- struct tavorprm_mgmqp_st mgmqp_1; /* Multicast Group Member QP */\r
-/* -------------- */\r
- struct tavorprm_mgmqp_st mgmqp_2; /* Multicast Group Member QP */\r
-/* -------------- */\r
- struct tavorprm_mgmqp_st mgmqp_3; /* Multicast Group Member QP */\r
-/* -------------- */\r
- struct tavorprm_mgmqp_st mgmqp_4; /* Multicast Group Member QP */\r
-/* -------------- */\r
- struct tavorprm_mgmqp_st mgmqp_5; /* Multicast Group Member QP */\r
-/* -------------- */\r
- struct tavorprm_mgmqp_st mgmqp_6; /* Multicast Group Member QP */\r
-/* -------------- */\r
- struct tavorprm_mgmqp_st mgmqp_7; /* Multicast Group Member QP */\r
-/* -------------- */\r
-}; \r
-\r
-/* INIT_IB Parameters */\r
-\r
-struct tavorprm_init_ib_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00004];\r
- pseudo_bit_t vl_cap[0x00004]; /* Maximum VLs supported on the port, excluding VL15 */\r
- pseudo_bit_t port_width_cap[0x00004];/* IB Port Width\r
- 1 - 1x\r
- 3 - 1x, 4x\r
- 11 - 1x, 4x or 12x (must not be used in InfiniHost MT23108)\r
- else - Reserved */\r
- pseudo_bit_t mtu_cap[0x00004]; /* Maximum MTU Supported\r
- 0x0 - Reserved\r
- 0x1 - 256\r
- 0x2 - 512\r
- 0x3 - 1024\r
- 0x4 - 2048\r
- 0x5 - 0xF Reserved */\r
- pseudo_bit_t g0[0x00001]; /* Set port GUID0 to GUID0 specified */\r
- pseudo_bit_t ng[0x00001]; /* Set node GUID to node_guid specified.\r
- node_guid and ng must be the same for all ports. */\r
- pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified.\r
- system_image_guid and sig must be the same for all ports. */\r
- pseudo_bit_t reserved1[0x0000d];\r
-/* -------------- */\r
- pseudo_bit_t max_gid[0x00010]; /* Maximum number of GIDs for the port */\r
- pseudo_bit_t reserved2[0x00010];\r
-/* -------------- */\r
- pseudo_bit_t max_pkey[0x00010]; /* Maximum pkeys for the port.\r
- Must be the same for both ports. */\r
- pseudo_bit_t reserved3[0x00010];\r
-/* -------------- */\r
- pseudo_bit_t reserved4[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t guid0_h[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 63:32) */\r
-/* -------------- */\r
- pseudo_bit_t guid0_l[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 31:0) */\r
-/* -------------- */\r
- pseudo_bit_t node_guid_h[0x00020]; /* Node GUID[63:32], takes effect only if the NG bit is set\r
- Must be the same for both ports. */\r
-/* -------------- */\r
- pseudo_bit_t node_guid_l[0x00020]; /* Node GUID[31:0], takes effect only if the NG bit is set\r
- Must be the same for both ports. */\r
-/* -------------- */\r
- pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set\r
- Must be the same for both ports. */\r
-/* -------------- */\r
- pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set\r
- Must be the same for both ports. */\r
-/* -------------- */\r
- pseudo_bit_t reserved5[0x006c0];\r
-/* -------------- */\r
-}; \r
-\r
-/* Query Device Limitations */\r
-\r
-struct tavorprm_query_dev_lim_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00080];\r
-/* -------------- */\r
- pseudo_bit_t log_max_qp[0x00005]; /* Log2 of the Maximum number of QPs supported */\r
- pseudo_bit_t reserved1[0x00003];\r
- pseudo_bit_t log2_rsvd_qps[0x00004];/* Log (base 2) of the number of QPs reserved for firmware use\r
- The reserved resources are numbered from 0 to 2^log2_rsvd_qps-1 */\r
- pseudo_bit_t reserved2[0x00004];\r
- pseudo_bit_t log_max_qp_sz[0x00008];/* Log2 of the maximum WQEs allowed on the RQ or the SQ */\r
- pseudo_bit_t log_max_srq_sz[0x00008];/* Log2 of the maximum WQEs allowed on the SRQ */\r
-/* -------------- */\r
- pseudo_bit_t log_max_ee[0x00005]; /* Log2 of the Maximum number of EE contexts supported */\r
- pseudo_bit_t reserved3[0x00003];\r
- pseudo_bit_t log2_rsvd_ees[0x00004];/* Log (base 2) of the number of EECs reserved for firmware use\r
- The reserved resources are numbered from 0 to 2^log2_rsvd_ees-1 */\r
- pseudo_bit_t reserved4[0x00004];\r
- pseudo_bit_t log_max_srqs[0x00005]; /* Log base 2 of the maximum number of SRQs supported, valid only if SRQ bit is set.\r
- */\r
- pseudo_bit_t reserved5[0x00007];\r
- pseudo_bit_t log2_rsvd_srqs[0x00004];/* Log (base 2) of the number of reserved SRQs for firmware use\r
- The reserved resources are numbered from 0 to 2^log2_rsvd_srqs-1\r
- This parameter is valid only if the SRQ bit is set. */\r
-/* -------------- */\r
- pseudo_bit_t log_max_cq[0x00005]; /* Log2 of the Maximum number of CQs supported */\r
- pseudo_bit_t reserved6[0x00003];\r
- pseudo_bit_t log2_rsvd_cqs[0x00004];/* Log (base 2) of the number of CQs reserved for firmware use\r
- The reserved resources are numbered from 0 to 2^log2_rsrvd_cqs-1 */\r
- pseudo_bit_t reserved7[0x00004];\r
- pseudo_bit_t log_max_cq_sz[0x00008];/* Log2 of the Maximum CQEs allowed in a CQ */\r
- pseudo_bit_t reserved8[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t log_max_eq[0x00003]; /* Log2 of the Maximum number of EQs */\r
- pseudo_bit_t reserved9[0x00005];\r
- pseudo_bit_t num_rsvd_eqs[0x00004]; /* The number of EQs reserved for firmware use\r
- The reserved resources are numbered from 0 to num_rsvd_eqs-1\r
- If 0 - no resources are reserved. */\r
- pseudo_bit_t reserved10[0x00004];\r
- pseudo_bit_t log_max_mpts[0x00006]; /* Log (base 2) of the maximum number of MPT entries (the number of Regions/Windows) */\r
- pseudo_bit_t reserved11[0x0000a];\r
-/* -------------- */\r
- pseudo_bit_t log_max_mtt_seg[0x00006];/* Log2 of the Maximum number of MTT segments */\r
- pseudo_bit_t reserved12[0x00002];\r
- pseudo_bit_t log2_rsvd_mrws[0x00004];/* Log (base 2) of the number of MPTs reserved for firmware use\r
- The reserved resources are numbered from 0 to 2^log2_rsvd_mrws-1 */\r
- pseudo_bit_t reserved13[0x00004];\r
- pseudo_bit_t log_max_mrw_sz[0x00008];/* Log2 of the Maximum Size of Memory Region/Window */\r
- pseudo_bit_t reserved14[0x00004];\r
- pseudo_bit_t log2_rsvd_mtts[0x00004];/* Log (base 2) of the number of MTT segments reserved for firmware use\r
- The reserved resources are numbered from 0 to 2^log2_rsvd_mtts-1\r
- */\r
-/* -------------- */\r
- pseudo_bit_t log_max_av[0x00006]; /* Log2 of the Maximum number of Address Vectors */\r
- pseudo_bit_t reserved15[0x0001a];\r
-/* -------------- */\r
- pseudo_bit_t log_max_ra_res_qp[0x00006];/* Log2 of the Maximum number of outstanding RDMA read/Atomic per QP as a responder */\r
- pseudo_bit_t reserved16[0x0000a];\r
- pseudo_bit_t log_max_ra_req_qp[0x00006];/* Log2 of the maximum number of outstanding RDMA read/Atomic per QP as a requester */\r
- pseudo_bit_t reserved17[0x0000a];\r
-/* -------------- */\r
- pseudo_bit_t log_max_ra_res_global[0x00006];/* Log2 of the maximum number of RDMA read/atomic operations the HCA responder can support globally. That implies the RDB table size. */\r
- pseudo_bit_t reserved18[0x0001a];\r
-/* -------------- */\r
- pseudo_bit_t reserved19[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t num_ports[0x00004]; /* Number of IB ports. */\r
- pseudo_bit_t max_vl[0x00004]; /* Maximum VLs supported on each port, excluding VL15 */\r
- pseudo_bit_t max_port_width[0x00004];/* IB Port Width\r
- 1 - 1x\r
- 3 - 1x, 4x\r
- 11 - 1x, 4x or 12x\r
- else - Reserved */\r
- pseudo_bit_t max_mtu[0x00004]; /* Maximum MTU Supported\r
- 0x0 - Reserved\r
- 0x1 - 256\r
- 0x2 - 512\r
- 0x3 - 1024\r
- 0x4 - 2048\r
- 0x5 - 0xF Reserved */\r
- pseudo_bit_t local_ca_ack_delay[0x00005];/* The Local CA ACK Delay. This is the value recommended to be returned in Query HCA verb.\r
- The delay value in microseconds is computed using 4.096us * 2^(Local_CA_ACK_Delay). */\r
- pseudo_bit_t reserved20[0x0000b];\r
-/* -------------- */\r
- pseudo_bit_t log_max_gid[0x00004]; /* Log2 of the maximum number of GIDs per port */\r
- pseudo_bit_t reserved21[0x0001c];\r
-/* -------------- */\r
- pseudo_bit_t log_max_pkey[0x00004]; /* Log2 of the max PKey Table Size (per IB port) */\r
- pseudo_bit_t reserved22[0x0001c];\r
-/* -------------- */\r
- pseudo_bit_t reserved23[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t rc[0x00001]; /* RC Transport supported */\r
- pseudo_bit_t uc[0x00001]; /* UC Transport Supported */\r
- pseudo_bit_t ud[0x00001]; /* UD Transport Supported */\r
- pseudo_bit_t rd[0x00001]; /* RD Transport Supported\r
- RD is not supported in InfiniHost MT23108 */\r
- pseudo_bit_t raw_ipv6[0x00001]; /* Raw IPv6 Transport Supported */\r
- pseudo_bit_t raw_ether[0x00001]; /* Raw Ethertype Transport Supported */\r
- pseudo_bit_t srq[0x00001]; /* SRQ is supported\r
- */\r
- pseudo_bit_t reserved24[0x00001];\r
- pseudo_bit_t pkv[0x00001]; /* PKey Violation Counter Supported */\r
- pseudo_bit_t qkv[0x00001]; /* QKey Violation Coutner Supported */\r
- pseudo_bit_t reserved25[0x00006];\r
- pseudo_bit_t mw[0x00001]; /* Memory windows supported */\r
- pseudo_bit_t apm[0x00001]; /* Automatic Path Migration Supported */\r
- pseudo_bit_t atm[0x00001]; /* Atomic operations supported (atomicity is guaranteed between QPs on this HCA) */\r
- pseudo_bit_t rm[0x00001]; /* Raw Multicast Supported */\r
- pseudo_bit_t avp[0x00001]; /* Address Vector Port checking supported */\r
- pseudo_bit_t udm[0x00001]; /* UD Multicast Supported */\r
- pseudo_bit_t reserved26[0x00002];\r
- pseudo_bit_t pg[0x00001]; /* Paging on demand supported */\r
- pseudo_bit_t r[0x00001]; /* Router mode supported */\r
- pseudo_bit_t reserved27[0x00006];\r
-/* -------------- */\r
- pseudo_bit_t log_pg_sz[0x00008]; /* Minimum system page size supported (log2) . \r
- For proper operation it must be less than or equal the hosting platform (CPU) minimum page size. */\r
- pseudo_bit_t reserved28[0x00008];\r
- pseudo_bit_t uar_sz[0x00006]; /* UAR Area Size = 1MB * 2^uar_sz */\r
- pseudo_bit_t reserved29[0x00006];\r
- pseudo_bit_t num_rsvd_uars[0x00004];/* The number of UARs reserved for firmware use\r
- The reserved resources are numbered from 0 to num_reserved_uars-1\r
- Note that UAR 1 is always for the kernel\r
- If 0 - no resources are reserved. */\r
-/* -------------- */\r
- pseudo_bit_t reserved30[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t max_desc_sz[0x00010]; /* Max descriptor size in bytes */\r
- pseudo_bit_t max_sg[0x00008]; /* The maximum S/G list elements in a WQE (max_desc_sz/16 - 3) */\r
- pseudo_bit_t reserved31[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t reserved32[0x00060];\r
-/* -------------- */\r
- pseudo_bit_t log_max_mcg[0x00008]; /* Log2 of the maximum number of multicast groups */\r
- pseudo_bit_t num_rsvd_mcgs[0x00004];/* The number of MGMs reserved for firmware use in the MGHT.\r
- The reserved resources are numbered from 0 to num_reserved_mcgs-1\r
- If 0 - no resources are reserved. */\r
- pseudo_bit_t reserved33[0x00004];\r
- pseudo_bit_t log_max_qp_mcg[0x00008];/* Log2 of the maximum number of QPs per multicast group */\r
- pseudo_bit_t reserved34[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t log_max_rdds[0x00006]; /* Log2 of the maximum number of RDDs */\r
- pseudo_bit_t reserved35[0x00006];\r
- pseudo_bit_t num_rsvd_rdds[0x00004];/* The number of RDDs reserved for firmware use\r
- The reserved resources are numbered from 0 to num_reserved_rdds-1.\r
- If 0 - no resources are reserved. */\r
- pseudo_bit_t log_max_pd[0x00006]; /* Log2 of the maximum number of PDs */\r
- pseudo_bit_t reserved36[0x00006];\r
- pseudo_bit_t num_rsvd_pds[0x00004]; /* The number of PDs reserved for firmware use\r
- The reserved resources are numbered from 0 to num_reserved_pds-1\r
- If 0 - no resources are reserved. */\r
-/* -------------- */\r
- pseudo_bit_t reserved37[0x000c0];\r
-/* -------------- */\r
- pseudo_bit_t qpc_entry_sz[0x00010]; /* QPC Entry Size for the device\r
- For the InfiniHost MT23108 entry size is 256 bytes */\r
- pseudo_bit_t eec_entry_sz[0x00010]; /* EEC Entry Size for the device\r
- For the InfiniHost MT23108 entry size is 256 bytes */\r
-/* -------------- */\r
- pseudo_bit_t eqpc_entry_sz[0x00010];/* Extended QPC entry size for the device\r
- For the InfiniHost MT23108 entry size is 32 bytes */\r
- pseudo_bit_t eeec_entry_sz[0x00010];/* Extended EEC entry size for the device\r
- For the InfiniHost MT23108 entry size is 32 bytes */\r
-/* -------------- */\r
- pseudo_bit_t cqc_entry_sz[0x00010]; /* CQC entry size for the device\r
- For the InfiniHost MT23108 entry size is 64 bytes */\r
- pseudo_bit_t eqc_entry_sz[0x00010]; /* EQ context entry size for the device\r
- For the InfiniHost MT23108 entry size is 64 bytes */\r
-/* -------------- */\r
- pseudo_bit_t uar_scratch_entry_sz[0x00010];/* UAR Scratchpad Entry Size\r
- For the InfiniHost MT23108 entry size is 32 bytes */\r
- pseudo_bit_t srq_entry_sz[0x00010]; /* SRQ context entry size for the device\r
- For the InfiniHost MT23108 entry size is 32 bytes */\r
-/* -------------- */\r
- pseudo_bit_t reserved38[0x00380];\r
-/* -------------- */\r
-}; \r
-\r
-/* QUERY_ADAPTER Parameters Block */\r
-\r
-struct tavorprm_query_adapter_st { /* Little Endian */\r
- pseudo_bit_t vendor_id[0x00020]; /* Adapter vendor ID */\r
-/* -------------- */\r
- pseudo_bit_t device_id[0x00020]; /* Adapter Device ID */\r
-/* -------------- */\r
- pseudo_bit_t revision_id[0x00020]; /* Adapter Revision ID */\r
-/* -------------- */\r
- pseudo_bit_t reserved0[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x00018];\r
- pseudo_bit_t intapin[0x00008]; /* Interrupt Signal ID of HCA device pin that is connected to the INTA trace in the HCA board.\r
- 0..39 and 63 are valid values\r
- 255 means INTA trace in board is not connected to the HCA device.\r
- All other values are reserved */\r
-/* -------------- */\r
- pseudo_bit_t reserved2[0x00760];\r
-/* -------------- */\r
-}; \r
-\r
-/* QUERY_FW Parameters Block */\r
-\r
-struct tavorprm_query_fw_st { /* Little Endian */\r
- pseudo_bit_t fw_rev_major[0x00010]; /* Firmware Revision - Major */\r
- pseudo_bit_t reserved0[0x00010];\r
-/* -------------- */\r
- pseudo_bit_t fw_rev_minor[0x00010]; /* Firmware Revision - Minor */\r
- pseudo_bit_t fw_rev_subminor[0x00010];/* Firmware Sub-minor version (Patch level). */\r
-/* -------------- */\r
- pseudo_bit_t cmd_interface_rev[0x00010];/* Command Interface Interpreter Revision ID */\r
- pseudo_bit_t reserved1[0x00010];\r
-/* -------------- */\r
- pseudo_bit_t log_max_outstanding_cmd[0x00008];/* Log2 of the maximum number of commands the HCR can support simultaneously */\r
- pseudo_bit_t reserved2[0x00017];\r
- pseudo_bit_t dt[0x00001]; /* Debug Trace Support\r
- 0 - Debug trace is not supported \r
- 1 - Debug trace is supported */\r
-/* -------------- */\r
- pseudo_bit_t reserved3[0x00080];\r
-/* -------------- */\r
- pseudo_bit_t fw_base_addr_h[0x00020];/* Physical Address of Firmware Area in DDR Memory [63:32] */\r
-/* -------------- */\r
- pseudo_bit_t fw_base_addr_l[0x00020];/* Physical Address of Firmware Area in DDR Memory [31:0] */\r
-/* -------------- */\r
- pseudo_bit_t fw_end_addr_h[0x00020];/* End of firmware address in DDR memory [63:32] */\r
-/* -------------- */\r
- pseudo_bit_t fw_end_addr_l[0x00020];/* End of firmware address in DDR memory [31:0] */\r
-/* -------------- */\r
- pseudo_bit_t error_buf_start_h[0x00020];/* Read Only buffer for catastrofic error reports. */\r
-/* -------------- */\r
- pseudo_bit_t error_buf_start_l[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t error_buf_size[0x00020];/* Size in words */\r
-/* -------------- */\r
- pseudo_bit_t reserved4[0x00620];\r
-/* -------------- */\r
-}; \r
-\r
-/* QUERY_DDR Parameters Block */\r
-\r
-struct tavorprm_query_ddr_st { /* Little Endian */\r
- pseudo_bit_t ddr_start_adr_h[0x00020];/* DDR memory start address [63:32] */\r
-/* -------------- */\r
- pseudo_bit_t ddr_start_adr_l[0x00020];/* DDR memory start address [31:0] */\r
-/* -------------- */\r
- pseudo_bit_t ddr_end_adr_h[0x00020];/* DDR memory end address [63:32] */\r
-/* -------------- */\r
- pseudo_bit_t ddr_end_adr_l[0x00020];/* DDR memory end address [31:0] */\r
-/* -------------- */\r
- pseudo_bit_t di[0x00002]; /* Data Integrity Configuration:\r
- 00 - none\r
- 01 - Parity\r
- 10 - ECC Detection Only\r
- 11 - ECC With Correction */\r
- pseudo_bit_t ap[0x00002]; /* Auto Precharge Mode\r
- 00 - No auto precharge\r
- 01 - Auto precharge per transaction\r
- 10 - Auto precharge per 64 bytes\r
- 11 - reserved */\r
- pseudo_bit_t dh[0x00001]; /* When Set DDR is Hidden and can not be accessed from PCI bus */\r
- pseudo_bit_t reserved0[0x0001b];\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x00160];\r
-/* -------------- */\r
- struct tavorprm_dimminfo_st dimm0; /* Logical DIMM 0 Parameters */\r
-/* -------------- */\r
- struct tavorprm_dimminfo_st dimm1; /* Logical DIMM 1 Parameters */\r
-/* -------------- */\r
- struct tavorprm_dimminfo_st dimm2; /* Logical DIMM 2 Parameters */\r
-/* -------------- */\r
- struct tavorprm_dimminfo_st dimm3; /* Logical DIMM 3 Parameters */\r
-/* -------------- */\r
- pseudo_bit_t reserved2[0x00200];\r
-/* -------------- */\r
-}; \r
-\r
-/* INIT_HCA & QUERY_HCA Parameters Block */\r
-\r
-struct tavorprm_init_hca_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00060];\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x00018];\r
- pseudo_bit_t hca_core_clock[0x00008];/* Internal Clock Period (in units of 1/16 ns) (QUERY_HCA only) */\r
-/* -------------- */\r
- pseudo_bit_t reserved2[0x00008];\r
- pseudo_bit_t router_qp[0x00010]; /* Upper 16 bit to be used as a QP number for router mode. Low order 8 bits are taken from the TClass field of the incoming packet.\r
- Valid only if RE bit is set */\r
- pseudo_bit_t reserved3[0x00007];\r
- pseudo_bit_t re[0x00001]; /* Router Mode Enable\r
- If this bit is set, entire packet (including all headers and ICRC) will be considered as a data payload and will be scattered to memory as specified in the descriptor that is posted on the QP matching the TClass field of packet. */\r
-/* -------------- */\r
- pseudo_bit_t udp[0x00001]; /* UD Port Check Enable\r
- 0 - Port field in Address Vector is ignored\r
- 1 - HCA will check the port field in AV entry (fetched for UD descriptor) against the Port of the UD QP executing the descriptor. */\r
- pseudo_bit_t he[0x00001]; /* Host Endianess - Used for Atomic Operations\r
- 0 - Host is Little Endian\r
- 1 - Host is Big endian\r
- */\r
- pseudo_bit_t ud[0x00001]; /* Force UD address vector protection check. If this bit is set, Passing address vector as immediate data in WQE is suppressed and privileged memory key will be used by hardware to access UD address vector table. */\r
- pseudo_bit_t reserved4[0x00005];\r
- pseudo_bit_t responder_exu[0x00004];/* How many execution engines are dedicated to the responder. Legal values are 0x0-0xF. 0 is "auto" */\r
- pseudo_bit_t reserved5[0x00004];\r
- pseudo_bit_t wqe_quota[0x0000f]; /* Maximum number of WQEs that are executed prior to preemption of execution unit. 0 - reserved. */\r
- pseudo_bit_t wqe_quota_en[0x00001]; /* If set - wqe_quota field is used. If cleared - WQE quota is set to "auto" value */\r
-/* -------------- */\r
- pseudo_bit_t reserved6[0x00040];\r
-/* -------------- */\r
- struct tavorprm_qpcbaseaddr_st qpc_eec_cqc_eqc_rdb_parameters;\r
-/* -------------- */\r
- pseudo_bit_t reserved7[0x00080];\r
-/* -------------- */\r
- struct tavorprm_udavtable_memory_parameters_st udavtable_memory_parameters;/* Memory Access Parameters for UD Address Vector Table. Used for QPs/EEc that are configured to use protected Address Vectors. */\r
-/* -------------- */\r
- pseudo_bit_t reserved8[0x00040];\r
-/* -------------- */\r
- struct tavorprm_multicastparam_st multicast_parameters;\r
-/* -------------- */\r
- pseudo_bit_t reserved9[0x00080];\r
-/* -------------- */\r
- struct tavorprm_tptparams_st tpt_parameters;\r
-/* -------------- */\r
- pseudo_bit_t reserved10[0x00080];\r
-/* -------------- */\r
- struct tavorprm_uar_params_st uar_parameters;/* UAR Parameters */\r
-/* -------------- */\r
- pseudo_bit_t reserved11[0x00600];\r
-/* -------------- */\r
-}; \r
-\r
-/* Event Queue Context Table Entry */\r
-\r
-struct tavorprm_eqc_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00008];\r
- pseudo_bit_t st[0x00002]; /* Event delivery state machine\r
- 01 - Armed\r
- 10 - Fired\r
- 11 - Always_Armed (auto-rearm)\r
- 00 - Reserved */\r
- pseudo_bit_t reserved1[0x00007];\r
- pseudo_bit_t oi[0x00001]; /* Ignore overrun on this EQ if this bit is set */\r
- pseudo_bit_t tr[0x00001]; /* Translation Required. If set - EQ access undergo address translation. */\r
- pseudo_bit_t reserved2[0x00005];\r
- pseudo_bit_t owner[0x00004]; /* 0 - SW ownership\r
- 1 - HW ownership\r
- Valid for the QUERY_EQ and HW2SW_EQ commands only */\r
- pseudo_bit_t status[0x00004]; /* EQ status:\r
- 0000 - OK\r
- 1001 - EQ overflow\r
- 1010 - EQ write failure\r
- Valid for the QUERY_EQ and HW2SW_EQ commands only */\r
-/* -------------- */\r
- pseudo_bit_t start_address_h[0x00020];/* Start Address of Event Queue[63:32]. \r
- Must be aligned on 32-byte boundary */\r
-/* -------------- */\r
- pseudo_bit_t start_address_l[0x00020];/* Start Address of Event Queue[31:0]. \r
- Must be aligned on 32-byte boundary */\r
-/* -------------- */\r
- pseudo_bit_t usr_page[0x00018];\r
- pseudo_bit_t log_eq_size[0x00005]; /* Amount of entries in this EQ is 2^log_eq_size.\r
- Log_eq_size must be bigger than 1 */\r
- pseudo_bit_t reserved3[0x00003];\r
-/* -------------- */\r
- pseudo_bit_t pd[0x00018]; /* PD to be used to access EQ */\r
- pseudo_bit_t reserved4[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t intr[0x00008]; /* Interrupt (message) to be generated to report event to INT layer.\r
- 00iiiiii - specifies GPIO pin to be asserted (according to INTA given in QUERY_ADAPTER)\r
- 10jjjjjj - specificies type of interrupt message to be generated (total 64 different messages supported).\r
- \r
- If interrupt generation is not required one of the two following options should be set:\r
- 1. ST must be set on creation to Fired state and not EQ arming doorbell should be performed. In this case hardware will not generate any interrupt.\r
- 2. intr should be set to 60 decimal\r
- */\r
- pseudo_bit_t reserved5[0x00018];\r
-/* -------------- */\r
- pseudo_bit_t lost_count[0x00020]; /* Number of events lost due to EQ overrun */\r
-/* -------------- */\r
- pseudo_bit_t lkey[0x00020]; /* Memory key (L-Key) to be used to access EQ */\r
-/* -------------- */\r
- pseudo_bit_t reserved6[0x00040];\r
-/* -------------- */\r
- pseudo_bit_t consumer_indx[0x00020];/* Contains next entry to be read upon polling the event queue.\r
- Must be initalized to '0 while opening EQ */\r
-/* -------------- */\r
- pseudo_bit_t producer_indx[0x00020];/* Contains next entry in EQ to be written by the HCA.\r
- Must be initalized to '0 while opening EQ. */\r
-/* -------------- */\r
- pseudo_bit_t reserved7[0x00080];\r
-/* -------------- */\r
-}; \r
-\r
-/* Memory Translation Table (MTT) Entry */\r
-\r
-struct tavorprm_mtt_st { /* Little Endian */\r
- pseudo_bit_t ptag_h[0x00020]; /* High-order bits of physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */\r
-/* -------------- */\r
- pseudo_bit_t p[0x00001]; /* Present bit. If set, page entry is valid. If cleared, access to this page will generate 'non-present page access fault'. */\r
- pseudo_bit_t reserved0[0x0000b];\r
- pseudo_bit_t ptag_l[0x00014]; /* Low-order bits of Physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */\r
-/* -------------- */\r
-}; \r
-\r
-/* Memory Protection Table (MPT) Entry */\r
-\r
-struct tavorprm_mpt_st { /* Little Endian */\r
- pseudo_bit_t ver[0x00004]; /* Version. Must be zero for InfiniHost */\r
- pseudo_bit_t reserved0[0x00004];\r
- pseudo_bit_t r_w[0x00001]; /* Defines whether this entry is Region (1) or Window (0) */\r
- pseudo_bit_t pa[0x00001]; /* Physical address. If set, no virtual-to-physical address translation will be performed for this region */\r
- pseudo_bit_t lr[0x00001]; /* If set - local read access enabled */\r
- pseudo_bit_t lw[0x00001]; /* If set - local write access enabled */\r
- pseudo_bit_t rr[0x00001]; /* If set - Remote read access enabled. */\r
- pseudo_bit_t rw[0x00001]; /* If set - remote write access enabled */\r
- pseudo_bit_t a[0x00001]; /* If set - Remote Atomic access is enabled */\r
- pseudo_bit_t eb[0x00001]; /* If set - Bind is enabled. Valid for region entry only. */\r
- pseudo_bit_t reserved1[0x00001];\r
- pseudo_bit_t m_io[0x00001]; /* Memory / I/O\r
- 1 - Memory commands used on the uplink bus\r
- 0 - I/O commands used on the uplink bus\r
- Must be 1 for the InfiniHost MT23108. */\r
- pseudo_bit_t reserved2[0x0000a];\r
- pseudo_bit_t status[0x00004]; /* Regios/Window Status\r
- 0xF - not valid (SW ownership)\r
- else - HW ownership\r
- Note that an unbound Window is denoted by the reg_wnd_len field equals zero. */\r
-/* -------------- */\r
- pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes.\r
- page_size should be less than 20. */\r
- pseudo_bit_t reserved3[0x00002];\r
- pseudo_bit_t reserved4[0x00001];\r
- pseudo_bit_t reserved5[0x00018];\r
-/* -------------- */\r
- pseudo_bit_t mem_key[0x00020]; /* The memory Key. This field is compared to key used to access the region/window. Lower-order bits are restricted (index to the table). */\r
-/* -------------- */\r
- pseudo_bit_t pd[0x00018]; /* Protection Domain */\r
- pseudo_bit_t reserved6[0x00001];\r
- pseudo_bit_t reserved7[0x00001];\r
- pseudo_bit_t reserved8[0x00001];\r
- pseudo_bit_t reserved9[0x00001];\r
- pseudo_bit_t reserved10[0x00001];\r
- pseudo_bit_t reserved11[0x00003];\r
-/* -------------- */\r
- pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region/window starts */\r
-/* -------------- */\r
- pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region/window starts */\r
-/* -------------- */\r
- pseudo_bit_t reg_wnd_len_h[0x00020];/* Region/Window Length[63:32] */\r
-/* -------------- */\r
- pseudo_bit_t reg_wnd_len_l[0x00020];/* Region/Window Length[31:0] */\r
-/* -------------- */\r
- pseudo_bit_t lkey[0x00020]; /* Must be 0 for SW2HW_MPT.\r
- On QUERY_MPTand HW2SW_MPT commands for Memory Window it reflects the LKey of the Region that the Window is bound to. */\r
-/* -------------- */\r
- pseudo_bit_t win_cnt[0x00020]; /* Number of windows bound to this region. Valid for regions only.\r
- The field is valid only for the QUERY_MPT and HW2SW_MPT commands. */\r
-/* -------------- */\r
- pseudo_bit_t win_cnt_limit[0x00020];/* The number of windows (limit) that can be bound to this region. If a bind operation is attempted when WIN_CNT == WIN_CNT_LIMIT, the operation will be aborted, a CQE with error will be generated, and the QP will be moved into the error state.\r
- Zero means no limit.\r
- Note that for best hardware performance, win_cnt_limit should be set to zero. */\r
-/* -------------- */\r
- pseudo_bit_t mtt_seg_adr_h[0x00020];/* Base (first) address of the MTT segment, aligned on segment_size boundary (bits 63:31). */\r
-/* -------------- */\r
- pseudo_bit_t reserved12[0x00006];\r
- pseudo_bit_t mtt_seg_adr_l[0x0001a];/* Base (first) address of the MTT segment, aligned on segment_size boundary (bits 31:6). */\r
-/* -------------- */\r
- pseudo_bit_t reserved13[0x00060];\r
-/* -------------- */\r
-}; \r
-\r
-/* Completion Queue Context Table Entry */\r
-\r
-struct tavorprm_completion_queue_context_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00008];\r
- pseudo_bit_t st[0x00004]; /* Event delivery state machine\r
- 0x0 - DISARMED\r
- 0x1 - ARMED (Request for Notification)\r
- 0x4 - ARMED SOLICITED (Request Solicited Notification)\r
- 0xA - FIRED\r
- other - reserved */\r
- pseudo_bit_t reserved1[0x00005];\r
- pseudo_bit_t oi[0x00001]; /* Ignore overrun of this CQ if this bit is set */\r
- pseudo_bit_t tr[0x00001]; /* Translation Required\r
- 1 - accesses to CQ will undergo address translation\r
- 0 - accesses to CQ will not undergo address translation */\r
- pseudo_bit_t reserved2[0x00009];\r
- pseudo_bit_t status[0x00004]; /* CQ status\r
- 0000 - OK\r
- 1001 - CQ overflow\r
- 1010 - CQ write failure\r
- Valid for the QUERY_CQ and HW2SW_CQ commands only */\r
-/* -------------- */\r
- pseudo_bit_t start_address_h[0x00020];/* Start address of CQ[63:32]. \r
- Must be aligned on CQE size (32 bytes) */\r
-/* -------------- */\r
- pseudo_bit_t start_address_l[0x00020];/* Start address of CQ[31:0]. \r
- Must be aligned on CQE size (32 bytes) */\r
-/* -------------- */\r
- pseudo_bit_t usr_page[0x00018]; /* UAR page this CQ can be accessed through (ringinig CQ doorbells) */\r
- pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries).\r
- Maximum CQ size is 128K CQEs (max log_cq_size is 17) */\r
- pseudo_bit_t reserved3[0x00003];\r
-/* -------------- */\r
- pseudo_bit_t e_eqn[0x00008]; /* Event Queue this CQ reports errors to (e.g. CQ overflow)\r
- Valid values are 0 to 63\r
- If configured to value other than 0-63, error events will not be reported on the CQ. */\r
- pseudo_bit_t reserved4[0x00018];\r
-/* -------------- */\r
- pseudo_bit_t c_eqn[0x00008]; /* Event Queue this CQ reports completion events to.\r
- Valid values are 0 to 63\r
- If configured to value other than 0-63, completion events will not be reported on the CQ. */\r
- pseudo_bit_t reserved5[0x00018];\r
-/* -------------- */\r
- pseudo_bit_t pd[0x00018]; /* Protection Domain to be used to access CQ.\r
- Must be the same PD of the CQ L_Key. */\r
- pseudo_bit_t reserved6[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t l_key[0x00020]; /* Memory key (L_Key) to be used to access CQ */\r
-/* -------------- */\r
- pseudo_bit_t last_notified_indx[0x00020];/* Maintained by HW.\r
- Valid for QUERY_CQ and HW2SW_CQ commands only. */\r
-/* -------------- */\r
- pseudo_bit_t solicit_producer_indx[0x00020];/* Maintained by HW.\r
- Valid for QUERY_CQ and HW2SW_CQ commands only. \r
- */\r
-/* -------------- */\r
- pseudo_bit_t consumer_indx[0x00020];/* Contains index to the next entry to be read upon poll for completion. The first completion after passing ownership of CQ from software to hardware will be reported to value passed in this field. Only the low log_cq_size bits may be non-zero. */\r
-/* -------------- */\r
- pseudo_bit_t producer_indx[0x00020];/* Points to the next entry to be written to by Hardware. CQ overrun is reported if Producer_indx + 1 equals to Consumer_indx. \r
- Maintained by HW (valid for the QUERY_CQ and HW2SW_CQ commands only) */\r
-/* -------------- */\r
- pseudo_bit_t cqn[0x00018]; /* CQ number. Least significant bits are constrained by the position of this CQ in CQC table\r
- Valid for the QUERY_CQ and HW2SW_CQ commands only */\r
- pseudo_bit_t reserved7[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t reserved8[0x00060];\r
-/* -------------- */\r
-}; \r
-\r
-/* UD Address Vector */\r
-\r
-struct tavorprm_ud_address_vector_st { /* Little Endian */\r
- pseudo_bit_t pd[0x00018]; /* Protection Domain */\r
- pseudo_bit_t port_number[0x00002]; /* Port number\r
- 1 - Port 1\r
- 2 - Port 2\r
- other - reserved */\r
- pseudo_bit_t reserved0[0x00006];\r
-/* -------------- */\r
- pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */\r
- pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */\r
- pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */\r
- pseudo_bit_t reserved1[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */\r
- pseudo_bit_t max_stat_rate[0x00003];/* Maximum static rate control. \r
- 0 - 4X injection rate\r
- 1 - 1X injection rate\r
- other - reserved\r
- */\r
- pseudo_bit_t reserved2[0x00001];\r
- pseudo_bit_t msg[0x00002]; /* Max Message size, size is 256*2^MSG bytes */\r
- pseudo_bit_t reserved3[0x00002];\r
- pseudo_bit_t mgid_index[0x00006]; /* Index to port GID table\r
- mgid_index = (port_number-1) * 2^log_max_gid + gid_index\r
- Where:\r
- 1. log_max_gid is taken from QUERY_DEV_LIM command\r
- 2. gid_index is the index to the GID table */\r
- pseudo_bit_t reserved4[0x0000a];\r
-/* -------------- */\r
- pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */\r
- pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */\r
- pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */\r
-/* -------------- */\r
- pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */\r
-/* -------------- */\r
- pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */\r
-/* -------------- */\r
- pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */\r
-/* -------------- */\r
- pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] */\r
-/* -------------- */\r
-}; \r
-\r
-/* Event_data Field - QP/EE Events */\r
-\r
-struct tavorprm_qp_ee_event_st { /* Little Endian */\r
- pseudo_bit_t qpn_een[0x00018]; /* QP/EE/SRQ number event is reported for */\r
- pseudo_bit_t reserved0[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t reserved2[0x0001c];\r
- pseudo_bit_t e_q[0x00001]; /* If set - EEN if cleared - QP in the QPN/EEN field\r
- Not valid on SRQ events */\r
- pseudo_bit_t reserved3[0x00003];\r
-/* -------------- */\r
- pseudo_bit_t reserved4[0x00060];\r
-/* -------------- */\r
-}; \r
-\r
-/* InfiniHost Type0 Configuration Header */\r
-\r
-struct tavorprm_mt23108_type0_st { /* Little Endian */\r
- pseudo_bit_t vendor_id[0x00010]; /* Hardwired to 0x15B3 */\r
- pseudo_bit_t device_id[0x00010]; /* hardwired to 23108 */\r
-/* -------------- */\r
- pseudo_bit_t command[0x00010]; /* PCI Command Register */\r
- pseudo_bit_t status[0x00010]; /* PCI Status Register */\r
-/* -------------- */\r
- pseudo_bit_t revision_id[0x00008];\r
- pseudo_bit_t class_code_hca_class_code[0x00018];\r
-/* -------------- */\r
- pseudo_bit_t cache_line_size[0x00008];/* Cache Line Size */\r
- pseudo_bit_t latency_timer[0x00008];\r
- pseudo_bit_t header_type[0x00008]; /* hardwired to zero */\r
- pseudo_bit_t bist[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t bar0_ctrl[0x00004]; /* hard-wired to '0100 */\r
- pseudo_bit_t reserved0[0x00010];\r
- pseudo_bit_t bar0_l[0x0000c]; /* Lower bits of BAR0 (configuration space) */\r
-/* -------------- */\r
- pseudo_bit_t bar0_h[0x00020]; /* Upper 32 bits of BAR0 (configuration space) */\r
-/* -------------- */\r
- pseudo_bit_t bar1_ctrl[0x00004]; /* Hardwired to '1100 */\r
- pseudo_bit_t reserved1[0x00010];\r
- pseudo_bit_t bar1_l[0x0000c]; /* Lower bits of BAR1 */\r
-/* -------------- */\r
- pseudo_bit_t bar1_h[0x00020]; /* upper 32 bits of BAR1 (User Access Revion - UAR - space) */\r
-/* -------------- */\r
- pseudo_bit_t bar2_ctrl[0x00004]; /* Hardwired to '1100 */\r
- pseudo_bit_t reserved2[0x00010];\r
- pseudo_bit_t bar2_l[0x0000c]; /* Lower bits of BAR2 */\r
-/* -------------- */\r
- pseudo_bit_t bar2_h[0x00020]; /* Upper 32 bits of BAR2 - DDR (attached memory) BAR */\r
-/* -------------- */\r
- pseudo_bit_t cardbus_cis_pointer[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t subsystem_vendor_id[0x00010];/* Programmed via InfiniBurn */\r
- pseudo_bit_t subsystem_id[0x00010]; /* programmed via InfiniBurn */\r
-/* -------------- */\r
- pseudo_bit_t expansion_rom_base_address[0x00020];/* Programmed via InfiniBurn if expansion ROM enabled */\r
-/* -------------- */\r
- pseudo_bit_t capabilities_pointer[0x00008];/* Programmed via InfiniBurn */\r
- pseudo_bit_t reserved3[0x00018];\r
-/* -------------- */\r
- pseudo_bit_t reserved4[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t interrupt_line[0x00008];\r
- pseudo_bit_t interrupt_pin[0x00008];\r
- pseudo_bit_t min_gnt[0x00008];\r
- pseudo_bit_t max_latency[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t reserved5[0x00100];\r
-/* -------------- */\r
- pseudo_bit_t msi_cap_id[0x00008];\r
- pseudo_bit_t msi_next_cap_ptr[0x00008];\r
- pseudo_bit_t msi_en[0x00001];\r
- pseudo_bit_t multiple_msg_cap[0x00003];\r
- pseudo_bit_t multiple_msg_en[0x00003];\r
- pseudo_bit_t cap_64_bit_addr[0x00001];\r
- pseudo_bit_t reserved6[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t msg_addr_l[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t msg_addr_h[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t msg_data[0x00010];\r
- pseudo_bit_t reserved7[0x00010];\r
-/* -------------- */\r
- pseudo_bit_t pcix_cap_id[0x00008];\r
- pseudo_bit_t pcix_next_cap_ptr[0x00008];\r
- pseudo_bit_t pcix_command_reg[0x00010];/* PCIX command register */\r
-/* -------------- */\r
- pseudo_bit_t pcix_status_reg[0x00020];/* PCIX Status Register */\r
-/* -------------- */\r
- pseudo_bit_t reserved8[0x00440];\r
-/* -------------- */\r
-}; \r
-\r
-/* NTU QP Map Table Entry */\r
-\r
-struct tavorprm_ntu_qpm_st { /* Little Endian */\r
- pseudo_bit_t va_h[0x00020]; /* Bits 63:32 of the virtual address to be used in IB request, Number of bits to be actually used depends on the page size (eg. will use all 52 for 4K page, 51 for 8K page etc). */\r
-/* -------------- */\r
- pseudo_bit_t wm[0x00002]; /* Amount of data to fill in to the read response buffer prior to delivering read response to uplink\r
- 00 - forward\r
- 01 - MTU\r
- 10 - full message\r
- 11 - Reserved */\r
- pseudo_bit_t mtu[0x00002]; /* MTUI of the channel to be used by this page, value is 256*2MU bytes */\r
- pseudo_bit_t rd_len[0x00003]; /* Length of speculative prefetch for read, value is 16*2RD_Len bytes */\r
- pseudo_bit_t fence[0x00002];\r
- pseudo_bit_t reserved0[0x00002];\r
- pseudo_bit_t err_fence[0x00001]; /* 0,00 - No action in NTU - normal flow\r
- 0,01 - Reserved (fence bits value of "01" is not defined)\r
- 0,10 - Enter PCU transaction to Error fifo, NO fence trap to consequent transaction\r
- 0,11 - Enter PCU transaction to Error fifo, fence trap to consequent transactions\r
- 1,xx - Enter PCU transaction to Error fifo, mark QRM indication in error fifo. */\r
- pseudo_bit_t va_l[0x00014]; /* Bits 31:12 of the virtual address to be used in IB request, Number of bits to be actually used depends on the page size (eg. will use all 52 for 4K page, 51 for 8K page etc). */\r
-/* -------------- */\r
- pseudo_bit_t rkey[0x00020]; /* RKey to be places for RDMA IB requests message */\r
-/* -------------- */\r
- pseudo_bit_t my_qpn[0x00018]; /* Local QO this page is mapped to */\r
- pseudo_bit_t s[0x00001]; /* Force solicit event bit in the descriptor */\r
- pseudo_bit_t e[0x00001]; /* Force E-bit in the descriptor */\r
- pseudo_bit_t s_r[0x00001]; /* S/R# - generate Send as a result of write hit to this page */\r
- pseudo_bit_t b[0x00001]; /* Breakpoint - ptransfer control to firmware for every cycle that hits this page */\r
- pseudo_bit_t reserved1[0x00002];\r
- pseudo_bit_t ce[0x00001]; /* Cache Enable - entry can be cached if this bit is set. */\r
- pseudo_bit_t v[0x00001]; /* Valid bit - the entry is valid only if this bit is set */\r
-/* -------------- */\r
-}; \r
-\r
-/* Event Data Field - Performance Monitor */\r
-\r
-struct tavorprm_performance_monitor_event_st { /* Little Endian */\r
- struct tavorprm_performance_monitors_st performance_monitor_snapshot;/* Performance monitor snapshot */\r
-/* -------------- */\r
- pseudo_bit_t monitor_number[0x00008];/* 0x01 - SQPC\r
- 0x02 - RQPC\r
- 0x03 - CQC\r
- 0x04 - Rkey\r
- 0x05 - TLB\r
- 0x06 - port0\r
- 0x07 - port1 */\r
- pseudo_bit_t reserved0[0x00018];\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x00040];\r
-/* -------------- */\r
-}; \r
-\r
-/* Event_data Field - Page Faults */\r
-\r
-struct tavorprm_page_fault_event_data_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00040];\r
-/* -------------- */\r
- pseudo_bit_t s_r[0x00001]; /* Send (1) or Receive (0) queue caused page fault */\r
- pseudo_bit_t r_l[0x00001]; /* Remote (1) or local (0) access caused fault */\r
- pseudo_bit_t w_d[0x00001]; /* WQE (1) or data (0) access caused fault */\r
- pseudo_bit_t wqv[0x00001]; /* Indicates whether message caused fault consumes descriptor (valid for receive queue only). */\r
- pseudo_bit_t fault_type[0x00004]; /* 0000-0111 - RESERVED\r
- 1000 - Translation page not present\r
- 1001 - RESERVED\r
- 1010 - Page write access violation\r
- 1011 - 1101 - RESERVED\r
- 1110 - Unsupported non-present page fault\r
- 1111 - unsupported write access fault */\r
- pseudo_bit_t reserved1[0x00018];\r
-/* -------------- */\r
- pseudo_bit_t va_h[0x00020]; /* Virtual address that caused access fault[63:32] */\r
-/* -------------- */\r
- pseudo_bit_t va_l[0x00020]; /* Virtual address that caused access fault[31:0] */\r
-/* -------------- */\r
- pseudo_bit_t mem_key[0x00020]; /* Memory Key used for address translation */\r
-/* -------------- */\r
-}; \r
-\r
-/* Event_data Field - Port State Change */\r
-\r
-struct tavorprm_port_state_change_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00040];\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x0001c];\r
- pseudo_bit_t p[0x00002]; /* Port number (1 or 2) */\r
- pseudo_bit_t reserved2[0x00002];\r
-/* -------------- */\r
- pseudo_bit_t reserved3[0x00060];\r
-/* -------------- */\r
-}; \r
-\r
-/* Event_data Field - Completion Queue Error */\r
-\r
-struct tavorprm_completion_queue_error_st { /* Little Endian */\r
- pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */\r
- pseudo_bit_t reserved0[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t syndrome[0x00008]; /* Error syndrome\r
- 0x01 - CQ overrun\r
- 0x02 - CQ access violation error */\r
- pseudo_bit_t reserved2[0x00018];\r
-/* -------------- */\r
- pseudo_bit_t reserved3[0x00060];\r
-/* -------------- */\r
-}; \r
-\r
-/* Event_data Field - Completion Event */\r
-\r
-struct tavorprm_completion_event_st { /* Little Endian */\r
- pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */\r
- pseudo_bit_t reserved0[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x000a0];\r
-/* -------------- */\r
-}; \r
-\r
-/* Event Queue Entry */\r
-\r
-struct tavorprm_event_queue_entry_st { /* Little Endian */\r
- pseudo_bit_t event_sub_type[0x00008];/* Event Sub Type. \r
- Defined for events which have sub types, zero elsewhere. */\r
- pseudo_bit_t reserved0[0x00008];\r
- pseudo_bit_t event_type[0x00008]; /* Event Type */\r
- pseudo_bit_t reserved1[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t event_data[6][0x00020];/* Delivers auxilary data to handle event. */\r
-/* -------------- */\r
- pseudo_bit_t reserved2[0x00007];\r
- pseudo_bit_t owner[0x00001]; /* Owner of the entry \r
- 0 SW \r
- 1 HW */\r
- pseudo_bit_t reserved3[0x00018];\r
-/* -------------- */\r
-}; \r
-\r
-/* QP/EE State Transitions Command Parameters */\r
-\r
-struct tavorprm_qp_ee_state_transitions_st { /* Little Endian */\r
- pseudo_bit_t opt_param_mask[0x00020];/* This field defines which optional parameters are passed. Each bit specifies whether optional parameter is passed (set) or not (cleared). The optparammask is defined for each QP/EE command. */\r
-/* -------------- */\r
- pseudo_bit_t reserved0[0x00020];\r
-/* -------------- */\r
- struct tavorprm_queue_pair_ee_context_entry_st qpc_eec_data;/* QPC/EEC data */\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x007c0];\r
-/* -------------- */\r
-}; \r
-\r
-/* Completion Queue Entry Format */\r
-\r
-struct tavorprm_completion_queue_entry_st { /* Little Endian */\r
- pseudo_bit_t my_qpn[0x00018]; /* Indicates the QP for which completion is being reported */\r
- pseudo_bit_t reserved0[0x00004];\r
- pseudo_bit_t ver[0x00004]; /* CQE version. \r
- 0 for InfiniHost */\r
-/* -------------- */\r
- pseudo_bit_t my_ee[0x00018]; /* EE context (for RD only).\r
- Invalid for Bind and Nop operation on RD. */\r
- pseudo_bit_t reserved1[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t rqpn[0x00018]; /* Remote (source) QP number. Valid in Responder CQE only for Datagram QP. */\r
- pseudo_bit_t reserved2[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t rlid[0x00010]; /* Remote (source) LID of the message. Valid in Responder of UD QP CQE only. */\r
- pseudo_bit_t ml_path[0x00007]; /* My (destination) LID path bits - these are the lowemost LMC bits of the DLID in an incoming UD packet, higher bits of this field, that are not part of the LMC bits are zeroed by HW.\r
- Valid in responder of UD QP CQE only.\r
- Invalid if incoming message DLID is the permissive LID or incoming message is multicast. */\r
- pseudo_bit_t g[0x00001]; /* GRH present indicator. Valid in Responder of UD QP CQE only. */\r
- pseudo_bit_t reserved3[0x00001];\r
- pseudo_bit_t reserved4[0x00003];\r
- pseudo_bit_t sl[0x00004]; /* Service Level of the message. Valid in Responder of UD QP CQE only. */\r
-/* -------------- */\r
- pseudo_bit_t immediate_ethertype_pkey_indx_eecredits[0x00020];/* Valid for receive queue completion only. \r
- If Opcode field indicates that this was send/write with immediate, this field contains immediate field of the packet. \r
- If completion corresponds to RAW receive queue, bits 15:0 contain Ethertype field of the packet. \r
- If completion corresponds to GSI receive queue, bits 31:16 contain index in PKey table that matches PKey of the message arrived. \r
- For CQE of send queue of the reliable connection service, bits [4:0] of this field contain the encoded EEcredits received in last ACK of the message.\r
- */\r
-/* -------------- */\r
- pseudo_bit_t byte_cnt[0x00020]; /* Byte count of data actually transferred (valid for receive queue completions only) */\r
-/* -------------- */\r
- pseudo_bit_t wqe_size[0x00006]; /* Size (in 16-byte chunks) of WQE completion is reported for */\r
- pseudo_bit_t wqe_adr[0x0001a]; /* Bits 31:6 of WQE virtual address completion is reported for. The 6 least significant bits are zero. */\r
-/* -------------- */\r
- pseudo_bit_t reserved5[0x00007];\r
- pseudo_bit_t owner[0x00001]; /* Owner field. Zero value of this field means SW ownership of CQE. */\r
- pseudo_bit_t reserved6[0x0000d];\r
- pseudo_bit_t reserved7[0x00001];\r
- pseudo_bit_t reserved8[0x00001];\r
- pseudo_bit_t s[0x00001]; /* If set, completion is reported for Send queue, if cleared - receive queue. */\r
- pseudo_bit_t opcode[0x00008]; /* The opcode of WQE completion is reported for.\r
- For CQEs corresponding to send completion, NOPCODE field of the WQE is copied to this field.\r
- For CQEs corresponding to receive completions, opcode field of last packet in the message copied to this field.\r
- For CQEs corresponding to the receive queue of QPs mapped to QP1, the opcode will be SEND with Immediate (messages are guaranteed to be SEND only)\r
- \r
- The following values are reported in case of completion with error:\r
- 0xFE - For completion with error on Receive Queues\r
- 0xFF - For completion with error on Send Queues */\r
-/* -------------- */\r
-}; \r
-\r
-/* 0 */\r
-\r
-struct tavorprm_tavor_prm_st { /* Little Endian */\r
- struct tavorprm_completion_queue_entry_st completion_queue_entry;/* Completion Queue Entry Format */\r
-/* -------------- */\r
- pseudo_bit_t reserved0[0x7ff00];\r
-/* -------------- */\r
- struct tavorprm_qp_ee_state_transitions_st qp_ee_state_transitions;/* QP/EE State Transitions Command Parameters */\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x7f000];\r
-/* -------------- */\r
- struct tavorprm_event_queue_entry_st event_queue_entry;/* Event Queue Entry */\r
-/* -------------- */\r
- pseudo_bit_t reserved2[0x7ff00];\r
-/* -------------- */\r
- struct tavorprm_completion_event_st completion_event;/* Event_data Field - Completion Event */\r
-/* -------------- */\r
- pseudo_bit_t reserved3[0x7ff40];\r
-/* -------------- */\r
- struct tavorprm_completion_queue_error_st completion_queue_error;/* Event_data Field - Completion Queue Error */\r
-/* -------------- */\r
- pseudo_bit_t reserved4[0x7ff40];\r
-/* -------------- */\r
- struct tavorprm_port_state_change_st port_state_change;/* Event_data Field - Port State Change */\r
-/* -------------- */\r
- pseudo_bit_t reserved5[0xfff40];\r
-/* -------------- */\r
- struct tavorprm_page_fault_event_data_st page_fault_event_data;/* Event_data Field - Page Faults */\r
-/* -------------- */\r
- pseudo_bit_t reserved6[0x7ff40];\r
-/* -------------- */\r
- struct tavorprm_performance_monitor_event_st performance_monitor_event;/* Event Data Field - Performance Monitor */\r
-/* -------------- */\r
- pseudo_bit_t reserved7[0x7ff20];\r
-/* -------------- */\r
- struct tavorprm_ntu_qpm_st ntu_qpm; /* NTU QP Map Table Entry */\r
-/* -------------- */\r
- pseudo_bit_t reserved8[0x7ff80];\r
-/* -------------- */\r
- struct tavorprm_mt23108_type0_st mt23108_type0;/* InfiniHost Type0 Configuration Header */\r
-/* -------------- */\r
- pseudo_bit_t reserved9[0x7f800];\r
-/* -------------- */\r
- struct tavorprm_qp_ee_event_st qp_ee_event;/* Event_data Field - QP/EE Events */\r
-/* -------------- */\r
- pseudo_bit_t reserved10[0x7ff40];\r
-/* -------------- */\r
- struct tavorprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */\r
-/* -------------- */\r
- pseudo_bit_t reserved11[0x7ff00];\r
-/* -------------- */\r
- struct tavorprm_queue_pair_ee_context_entry_st queue_pair_ee_context_entry;/* QP and EE Context Entry */\r
-/* -------------- */\r
- pseudo_bit_t reserved12[0x7f800];\r
-/* -------------- */\r
- struct tavorprm_address_path_st address_path;/* Address Path */\r
-/* -------------- */\r
- pseudo_bit_t reserved13[0x7ff00];\r
-/* -------------- */\r
- struct tavorprm_completion_queue_context_st completion_queue_context;/* Completion Queue Context Table Entry */\r
-/* -------------- */\r
- pseudo_bit_t reserved14[0x7fe00];\r
-/* -------------- */\r
- struct tavorprm_mpt_st mpt; /* Memory Protection Table (MPT) Entry */\r
-/* -------------- */\r
- pseudo_bit_t reserved15[0x7fe00];\r
-/* -------------- */\r
- struct tavorprm_mtt_st mtt; /* Memory Translation Table (MTT) Entry */\r
-/* -------------- */\r
- pseudo_bit_t reserved16[0x7ffc0];\r
-/* -------------- */\r
- struct tavorprm_eqc_st eqc; /* Event Queue Context Table Entry */\r
-/* -------------- */\r
- pseudo_bit_t reserved17[0x7fe00];\r
-/* -------------- */\r
- struct tavorprm_performance_monitors_st performance_monitors;/* Performance Monitors */\r
-/* -------------- */\r
- pseudo_bit_t reserved18[0x7ff80];\r
-/* -------------- */\r
- struct tavorprm_hca_command_register_st hca_command_register;/* HCA Command Register (HCR) */\r
-/* -------------- */\r
- pseudo_bit_t reserved19[0xfff20];\r
-/* -------------- */\r
- struct tavorprm_init_hca_st init_hca;/* INIT_HCA & QUERY_HCA Parameters Block */\r
-/* -------------- */\r
- pseudo_bit_t reserved20[0x7f000];\r
-/* -------------- */\r
- struct tavorprm_qpcbaseaddr_st qpcbaseaddr;/* QPC/EEC/CQC/EQC/RDB Parameters */\r
-/* -------------- */\r
- pseudo_bit_t reserved21[0x7fc00];\r
-/* -------------- */\r
- struct tavorprm_udavtable_memory_parameters_st udavtable_memory_parameters;/* Memory Access Parameters for UD Address Vector Table */\r
-/* -------------- */\r
- pseudo_bit_t reserved22[0x7ffc0];\r
-/* -------------- */\r
- struct tavorprm_multicastparam_st multicastparam;/* Multicast Support Parameters */\r
-/* -------------- */\r
- pseudo_bit_t reserved23[0x7ff00];\r
-/* -------------- */\r
- struct tavorprm_tptparams_st tptparams;/* Translation and Protection Tables Parameters */\r
-/* -------------- */\r
- pseudo_bit_t reserved24[0x7ff00];\r
-/* -------------- */\r
- struct tavorprm_query_ddr_st query_ddr;/* QUERY_DDR Parameters Block */\r
-/* -------------- */\r
- pseudo_bit_t reserved25[0x7f800];\r
-/* -------------- */\r
- struct tavorprm_dimminfo_st dimminfo;/* Logical DIMM Information */\r
-/* -------------- */\r
- pseudo_bit_t reserved26[0x7ff00];\r
-/* -------------- */\r
- struct tavorprm_query_fw_st query_fw;/* QUERY_FW Parameters Block */\r
-/* -------------- */\r
- pseudo_bit_t reserved27[0x7f800];\r
-/* -------------- */\r
- struct tavorprm_query_adapter_st query_adapter;/* QUERY_ADAPTER Parameters Block */\r
-/* -------------- */\r
- pseudo_bit_t reserved28[0x7f800];\r
-/* -------------- */\r
- struct tavorprm_query_dev_lim_st query_dev_lim;/* Query Device Limitations */\r
-/* -------------- */\r
- pseudo_bit_t reserved29[0x7f800];\r
-/* -------------- */\r
- struct tavorprm_uar_params_st uar_params;/* UAR Parameters */\r
-/* -------------- */\r
- pseudo_bit_t reserved30[0x7ff00];\r
-/* -------------- */\r
- struct tavorprm_init_ib_st init_ib; /* INIT_IB Parameters */\r
-/* -------------- */\r
- pseudo_bit_t reserved31[0x7f800];\r
-/* -------------- */\r
- struct tavorprm_mgm_entry_st mgm_entry;/* Multicast Group Member */\r
-/* -------------- */\r
- pseudo_bit_t reserved32[0x7fe00];\r
-/* -------------- */\r
- struct tavorprm_set_ib_st set_ib; /* SET_IB Parameters */\r
-/* -------------- */\r
- pseudo_bit_t reserved33[0x7fe00];\r
-/* -------------- */\r
- struct tavorprm_rd_send_doorbell_st rd_send_doorbell;/* RD-send doorbell */\r
-/* -------------- */\r
- pseudo_bit_t reserved34[0x7ff80];\r
-/* -------------- */\r
- struct tavorprm_send_doorbell_st send_doorbell;/* Send doorbell */\r
-/* -------------- */\r
- pseudo_bit_t reserved35[0x7ffc0];\r
-/* -------------- */\r
- struct tavorprm_receive_doorbell_st receive_doorbell;/* Receive doorbell */\r
-/* -------------- */\r
- pseudo_bit_t reserved36[0x7ffc0];\r
-/* -------------- */\r
- struct tavorprm_cq_cmd_doorbell_st cq_cmd_doorbell;/* CQ Doorbell */\r
-/* -------------- */\r
- pseudo_bit_t reserved37[0x7ffc0];\r
-/* -------------- */\r
- struct tavorprm_eq_cmd_doorbell_st eq_cmd_doorbell;/* EQ Doorbell */\r
-/* -------------- */\r
- pseudo_bit_t reserved38[0x7ffc0];\r
-/* -------------- */\r
- struct tavorprm_uar_st uar; /* User Access Region */\r
-/* -------------- */\r
- pseudo_bit_t reserved39[0x7c000];\r
-/* -------------- */\r
- struct tavorprm_mgmqp_st mgmqp; /* Multicast Group Member QP */\r
-/* -------------- */\r
- pseudo_bit_t reserved40[0x7ffe0];\r
-/* -------------- */\r
- struct tavorprm_query_debug_msg_st query_debug_msg;/* Query Debug Message */\r
-/* -------------- */\r
- pseudo_bit_t reserved41[0x7f800];\r
-/* -------------- */\r
- struct tavorprm_sys_en_out_param_st sys_en_out_param;/* SYS_EN Output Parameter */\r
-/* -------------- */\r
- pseudo_bit_t reserved42[0x7ffc0];\r
-/* -------------- */\r
- struct tavorprm_resize_cq_st resize_cq;/* Resize CQ Input Mailbox */\r
-/* -------------- */\r
- pseudo_bit_t reserved43[0x7fe00];\r
-/* -------------- */\r
- struct tavorprm_completion_with_error_st completion_with_error;/* Completion with Error CQE */\r
-/* -------------- */\r
- pseudo_bit_t reserved44[0x7ff00];\r
-/* -------------- */\r
- struct tavorprm_hcr_completion_event_st hcr_completion_event;/* Event_data Field - HCR Completion Event */\r
-/* -------------- */\r
- pseudo_bit_t reserved45[0x7ff40];\r
-/* -------------- */\r
- struct tavorprm_transport_and_ci_error_counters_st transport_and_ci_error_counters;/* Transport and CI Error Counters */\r
-/* -------------- */\r
- pseudo_bit_t reserved46[0x7f000];\r
-/* -------------- */\r
- struct tavorprm_performance_counters_st performance_counters;/* Performance Counters */\r
-/* -------------- */\r
- pseudo_bit_t reserved47[0x7f800];\r
-/* -------------- */\r
- struct tavorprm_query_bar_st query_bar;/* Query BAR */\r
-/* -------------- */\r
- pseudo_bit_t reserved48[0x7ffc0];\r
-/* -------------- */\r
- struct tavorprm_cfg_schq_st cfg_schq;/* Schedule queues configuration */\r
-/* -------------- */\r
- pseudo_bit_t reserved49[0x7f800];\r
-/* -------------- */\r
- struct tavorprm_mt23108_configuration_registers_st mt23108_configuration_registers;/* InfiniHost Configuration Registers - Used in Mem-Free mode only */\r
-/* -------------- */\r
- pseudo_bit_t reserved50[0x80000];\r
-/* -------------- */\r
- pseudo_bit_t reserved51[0x00100];\r
-/* -------------- */\r
- pseudo_bit_t reserved52[0x7ff00];\r
-/* -------------- */\r
- pseudo_bit_t reserved53[0x00100];\r
-/* -------------- */\r
- pseudo_bit_t reserved54[0x7ff00];\r
-/* -------------- */\r
- struct tavorprm_srq_context_st srq_context;/* SRQ Context */\r
-/* -------------- */\r
- pseudo_bit_t reserved55[0x7ff00];\r
-/* -------------- */\r
- struct tavorprm_mod_stat_cfg_st mod_stat_cfg;/* MOD_STAT_CFG */\r
-/* -------------- */\r
- pseudo_bit_t reserved56[0x00080];\r
-/* -------------- */\r
- pseudo_bit_t reserved57[0x00040];\r
-/* -------------- */\r
- pseudo_bit_t reserved58[0x1bff740];\r
-/* -------------- */\r
-}; \r
-\r
-/* Event_data Field - ECC Detection Event */\r
-\r
-struct tavorprm_scrubbing_event_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00080];\r
-/* -------------- */\r
- pseudo_bit_t ecc_err_fifo_word1[0x00010];/* For debug: ECC error was discovered and corrected by InfiniHost */\r
- pseudo_bit_t reserved1[0x0000f];\r
- pseudo_bit_t overflow[0x00001]; /* Fatal: ECC error FIFO overflow - ECC errors were detected, which may or may not have been corrected by InfiiHost */\r
-/* -------------- */\r
- pseudo_bit_t ecc_err_fifo_word2[0x00020];/* For debug: ECC error was discovered and corrected by InfiniHost */\r
-/* -------------- */\r
-}; \r
-\r
-/* PBL */\r
-\r
-struct tavorprm_pbl_st { /* Little Endian */\r
- pseudo_bit_t mtt_0_h[0x00020]; /* First MTT[63:32] */\r
-/* -------------- */\r
- pseudo_bit_t mtt_0_l[0x00020]; /* First MTT[31:0] */\r
-/* -------------- */\r
- pseudo_bit_t mtt_1_h[0x00020]; /* Second MTT[63:32] */\r
-/* -------------- */\r
- pseudo_bit_t mtt_1_l[0x00020]; /* Second MTT[31:0] */\r
-/* -------------- */\r
- pseudo_bit_t mtt_2_h[0x00020]; /* Third MTT[63:32] */\r
-/* -------------- */\r
- pseudo_bit_t mtt_2_l[0x00020]; /* Third MTT[31:0] */\r
-/* -------------- */\r
- pseudo_bit_t mtt_3_h[0x00020]; /* Fourth MTT[63:32] */\r
-/* -------------- */\r
- pseudo_bit_t mtt_3_l[0x00020]; /* Fourth MTT[31:0] */\r
-/* -------------- */\r
-}; \r
-\r
-/* Miscellaneous Counters */\r
-\r
-struct tavorprm_misc_counters_st { /* Little Endian */\r
- pseudo_bit_t ddr_scan_cnt[0x00020]; /* Number of times whole of DDR was scanned */\r
-/* -------------- */\r
- pseudo_bit_t reserved0[0x007e0];\r
-/* -------------- */\r
-}; \r
-\r
-/* Fast_Registration_Segment */\r
-\r
-struct tavorprm_fast_registration_segment_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x0001b];\r
- pseudo_bit_t lr[0x00001]; /* If set - Local Read access will be enabled */\r
- pseudo_bit_t lw[0x00001]; /* If set - Local Write access will be enabled */\r
- pseudo_bit_t rr[0x00001]; /* If set - Remote Read access will be enabled */\r
- pseudo_bit_t rw[0x00001]; /* If set - Remote Write access will be enabled */\r
- pseudo_bit_t a[0x00001]; /* If set - Remote Atomic access will be enabled */\r
-/* -------------- */\r
- pseudo_bit_t pbl_ptr_63_32[0x00020];/* Physical address pointer [63:32] to the physical block list */\r
-/* -------------- */\r
- pseudo_bit_t mem_key[0x00020]; /* Memory Key on which the fast registration is executed on. */\r
-/* -------------- */\r
- pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes.\r
- page_size should be less than 20. */\r
- pseudo_bit_t reserved1[0x00002];\r
- pseudo_bit_t zb[0x00001]; /* Zero Based Region */\r
- pseudo_bit_t pbl_ptr_31_8[0x00018]; /* Physical address pointer [31:8] to the physical block list */\r
-/* -------------- */\r
- pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region starts */\r
-/* -------------- */\r
- pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region starts */\r
-/* -------------- */\r
- pseudo_bit_t reg_len_h[0x00020]; /* Region Length[63:32] */\r
-/* -------------- */\r
- pseudo_bit_t reg_len_l[0x00020]; /* Region Length[31:0] */\r
-/* -------------- */\r
-}; \r
-#endif /* H_prefix_tavorprm_bits_fixnames_MT23108_PRM_csp_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-/***\r
- *** This file was generated at "Thu Apr 29 10:25:56 2004"\r
- *** by:\r
- *** % csp_bf -copyright=/mswg/misc/license-header.txt -bits MT23108_PRM_append.csp\r
- ***/\r
-\r
-#ifndef H_bits_MT23108_PRM_append_csp_H\r
-#define H_bits_MT23108_PRM_append_csp_H\r
-\r
-\r
-/* Gather entry with inline data */\r
-\r
-struct wqe_segment_data_inline_st { /* Little Endian */\r
- pseudo_bit_t byte_count[0x0000a]; /* Not including padding for 16Byte chunks */\r
- pseudo_bit_t reserved0[0x00015];\r
- pseudo_bit_t always1[0x00001];\r
-/* -------------- */\r
- pseudo_bit_t data[0x00018]; /* Data may be more this segment size - in 16Byte chunks */\r
-/* -------------- */\r
-}; \r
-\r
-/* Scatter/Gather entry with a pointer */\r
-\r
-struct wqe_segment_data_ptr_st { /* Little Endian */\r
- pseudo_bit_t byte_count[0x0001f];\r
- pseudo_bit_t always0[0x00001];\r
-/* -------------- */\r
- pseudo_bit_t l_key[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t local_address_h[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t local_address_l[0x00020];\r
-/* -------------- */\r
-}; \r
-\r
-/* */\r
-\r
-struct wqe_segment_atomic_st { /* Little Endian */\r
- pseudo_bit_t swap_add_h[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t swap_add_l[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t compare_h[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t compare_l[0x00020];\r
-/* -------------- */\r
-}; \r
-\r
-/* */\r
-\r
-struct wqe_segment_remote_address_st { /* Little Endian */\r
- pseudo_bit_t remote_virt_addr_h[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t remote_virt_addr_l[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t rkey[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t reserved0[0x00020];\r
-/* -------------- */\r
-}; \r
-\r
-/* Bind memory window segment */\r
-\r
-struct wqe_segment_bind_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x0001d];\r
- pseudo_bit_t rr[0x00001]; /* Remote read */\r
- pseudo_bit_t rw[0x00001]; /* Remote write */\r
- pseudo_bit_t a[0x00001]; /* atomic */\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t new_rkey[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t region_lkey[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t start_address_h[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t start_address_l[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t length_h[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t length_l[0x00020];\r
-/* -------------- */\r
-}; \r
-\r
-/* */\r
-\r
-struct wqe_segment_ud_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t l_key[0x00020]; /* memory key for UD AV */\r
-/* -------------- */\r
- pseudo_bit_t av_address_63_32[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x00005];\r
- pseudo_bit_t av_address_31_5[0x0001b];\r
-/* -------------- */\r
- pseudo_bit_t reserved2[0x00080];\r
-/* -------------- */\r
- pseudo_bit_t destination_qp[0x00018];\r
- pseudo_bit_t reserved3[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t q_key[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t reserved4[0x00040];\r
-/* -------------- */\r
-}; \r
-\r
-/* */\r
-\r
-struct wqe_segment_rd_st { /* Little Endian */\r
- pseudo_bit_t destination_qp[0x00018];\r
- pseudo_bit_t reserved0[0x00008];\r
-/* -------------- */\r
- pseudo_bit_t q_key[0x00020];\r
-/* -------------- */\r
- pseudo_bit_t reserved1[0x00040];\r
-/* -------------- */\r
-}; \r
-\r
-/* */\r
-\r
-struct wqe_segment_ctrl_recv_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00002];\r
- pseudo_bit_t e[0x00001]; /* WQE event */\r
- pseudo_bit_t c[0x00001]; /* Create CQE (for "requested signalling" QP) */\r
- pseudo_bit_t reserved1[0x0001c];\r
-/* -------------- */\r
- pseudo_bit_t reserved2[0x00020];\r
-/* -------------- */\r
-}; \r
-\r
-/* */\r
-\r
-struct wqe_segment_ctrl_mlx_st { /* Little Endian */\r
- pseudo_bit_t reserved0[0x00002];\r
- pseudo_bit_t e[0x00001]; /* WQE event */\r
- pseudo_bit_t c[0x00001]; /* Create CQE (for "requested signalling" QP) */\r
- pseudo_bit_t reserved1[0x00004];\r
- pseudo_bit_t sl[0x00004];\r
- pseudo_bit_t max_statrate[0x00003];\r
- pseudo_bit_t reserved2[0x00001];\r
- pseudo_bit_t slr[0x00001]; /* 0= take slid from port. 1= take slid from given headers */\r
- pseudo_bit_t v15[0x00001]; /* Send packet over VL15 */\r
- pseudo_bit_t reserved3[0x0000e];\r
-/* -------------- */\r
- pseudo_bit_t vcrc[0x00010]; /* Packet's VCRC (if not 0 - otherwise computed by HW) */\r
- pseudo_bit_t rlid[0x00010]; /* Destination LID (must match given headers) */\r
-/* -------------- */\r
-}; \r
-\r
-/* */\r
-\r
-struct wqe_segment_ctrl_send_st { /* Little Endian */\r
- pseudo_bit_t always1[0x00001];\r
- pseudo_bit_t s[0x00001]; /* Solicited event */\r
- pseudo_bit_t e[0x00001]; /* WQE event */\r
- pseudo_bit_t c[0x00001]; /* Create CQE (for "requested signalling" QP) */\r
- pseudo_bit_t reserved0[0x0001c];\r
-/* -------------- */\r
- pseudo_bit_t immediate[0x00020];\r
-/* -------------- */\r
-}; \r
-\r
-/* */\r
-\r
-struct wqe_segment_next_st { /* Little Endian */\r
- pseudo_bit_t nopcode[0x00005]; /* next opcode */\r
- pseudo_bit_t reserved0[0x00001];\r
- pseudo_bit_t nda_31_6[0x0001a]; /* NDA[31:6] */\r
-/* -------------- */\r
- pseudo_bit_t nds[0x00006];\r
- pseudo_bit_t f[0x00001]; /* fence bit */\r
- pseudo_bit_t dbd[0x00001]; /* doorbell rung */\r
- pseudo_bit_t nee[0x00018]; /* next EE */\r
-/* -------------- */\r
-}; \r
-#endif /* H_bits_MT23108_PRM_append_csp_H */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_CR_TYPES_H\r
-#define H_CR_TYPES_H\r
-\r
-\r
-/* Macros to use with device's header file */\r
-\r
-#define MT_BIT_OFFSET(object_struct,reg_path) \\r
- ((MT_offset_t) &( ((struct object_struct *)(0))-> reg_path ))\r
-\r
-#define MT_BIT_SIZE(object_struct,reg_path) \\r
- ((MT_size_t) sizeof( ((struct object_struct *)(0))-> reg_path ))\r
- \r
-#define MT_BIT_OFFSET_SIZE(object_struct,reg_path) \\r
- MT_BIT_OFFSET(object_struct,reg_path),MT_BIT_SIZE(object_struct,reg_path)\r
-\r
-#undef MT_BYTE_OFFSET\r
-#define MT_BYTE_OFFSET(object_struct,reg_path) \\r
- ((MT_offset_t) (MT_BIT_OFFSET(object_struct,reg_path)/8))\r
-\r
-#define MT_BYTE_SIZE(object_struct,reg_path) \\r
- ((MT_size_t) MT_BIT_SIZE(object_struct,reg_path)/8)\r
-\r
-#define MT_BYTE_OFFSET_SIZE(object_struct,reg_path) \\r
- MT_BYTE_OFFSET(object_struct,reg_path),MT_BYTE_SIZE(object_struct,reg_path)\r
-\r
-typedef u_int8_t pseudo_bit_t;\r
-\r
-#endif\r
\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-#ifndef H_TAVOR_DEV_DEFS_H_\r
-#define H_TAVOR_DEV_DEFS_H_\r
-\r
-#define MT23108_DEV_ID 23108\r
-#define MT25208_DEV_ID 25208\r
-/* cr-space ofsetts */\r
-#define TAVOR_HCR_OFFSET_FROM_CR_BASE \\r
- MT_BYTE_OFFSET(tavorprm_mt23108_configuration_registers_st,hca_command_interface_register)\r
-/* offset of HCR from cr-space base */\r
-#define TAVOR_ECR_H_OFFSET_FROM_CR_BASE \\r
- MT_BYTE_OFFSET(tavorprm_mt23108_configuration_registers_st,ecr_h)\r
-#define TAVOR_ECR_L_OFFSET_FROM_CR_BASE \\r
- MT_BYTE_OFFSET(tavorprm_mt23108_configuration_registers_st,ecr_l)\r
-#define TAVOR_CLR_ECR_H_OFFSET_FROM_CR_BASE \\r
- MT_BYTE_OFFSET(tavorprm_mt23108_configuration_registers_st,clr_ecr_h)\r
-#define TAVOR_CLR_ECR_L_OFFSET_FROM_CR_BASE \\r
- MT_BYTE_OFFSET(tavorprm_mt23108_configuration_registers_st,clr_ecr_l)\r
-#define TAVOR_CLR_INT_H_OFFSET_FROM_CR_BASE \\r
- MT_BYTE_OFFSET(tavorprm_mt23108_configuration_registers_st,clr_int_h)\r
-#define TAVOR_CLR_INT_L_OFFSET_FROM_CR_BASE \\r
- MT_BYTE_OFFSET(tavorprm_mt23108_configuration_registers_st,clr_int_l)\r
-\r
-\r
-\r
-#endif /* H_TAVOR_DEV_DEFS_H_ */\r
-/*\r
- * Copyright (c) 2004-2005 Mellanox Technologies Ltd. All rights reserved.\r
- *\r
- * This software is available to you under the OpenIB.org BSD license\r
- * below:\r
- *\r
- * Redistribution and use in source and binary forms, with or\r
- * without modification, are permitted provided that the following\r
- * conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer.\r
- *\r
- * - Redistributions in binary form must reproduce the above\r
- * copyright notice, this list of conditions and the following\r
- * disclaimer in the documentation and/or other materials\r
- * provided with the distribution.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
- * SOFTWARE.\r
- *\r
- * $Id$\r
- */\r
-\r
-#ifndef H_TAVOR_IF_DEFS_H\r
-#define H_TAVOR_IF_DEFS_H\r
-\r
-// FW TEAM: timeouts are divided into 3 classes - values are in usec:\r
-//#define TAVOR_IF_CMD_ETIME_CLASS_A 5000000\r
-//#define TAVOR_IF_CMD_ETIME_CLASS_B 10000000\r
-//#define TAVOR_IF_CMD_ETIME_CLASS_C 20000000\r
-//#define TAVOR_IF_CMD_ETIME_UNKNOWN_LAT 50000000\r
-\r
-/* TK: FW cannot guarantee commands completion timeout due to starvation with door-bells\r
- So we put the 15 minutes hoping that the DBs will stop and the\r
- command will have time to complete */\r
-#define TAVOR_IF_CMD_ETIME_CLASS_A 300000000\r
-#define TAVOR_IF_CMD_ETIME_CLASS_B 300000000\r
-#define TAVOR_IF_CMD_ETIME_CLASS_C 300000000\r
-\r
-/* macros to define the estimated time in microseconds to execute a command */\r
-#define TAVOR_IF_CMD_ETIME_SYS_EN TAVOR_IF_CMD_ETIME_CLASS_C\r
-#define TAVOR_IF_CMD_ETIME_SYS_DIS TAVOR_IF_CMD_ETIME_CLASS_C\r
-#define TAVOR_IF_CMD_ETIME_QUERY_DEV_LIM TAVOR_IF_CMD_ETIME_CLASS_A\r
-#define TAVOR_IF_CMD_ETIME_QUERY_FW TAVOR_IF_CMD_ETIME_CLASS_A\r
-#define TAVOR_IF_CMD_ETIME_ACCESS_DDR TAVOR_IF_CMD_ETIME_UNKNOWN_LAT\r
-#define TAVOR_IF_CMD_ETIME_QUERY_DDR TAVOR_IF_CMD_ETIME_CLASS_A\r
-#define TAVOR_IF_CMD_ETIME_QUERY_ADAPTER TAVOR_IF_CMD_ETIME_CLASS_A\r
-#define TAVOR_IF_CMD_ETIME_INIT_HCA TAVOR_IF_CMD_ETIME_CLASS_C\r
-#define TAVOR_IF_CMD_ETIME_CLOSE_HCA TAVOR_IF_CMD_ETIME_CLASS_C\r
-#define TAVOR_IF_CMD_ETIME_INIT_IB TAVOR_IF_CMD_ETIME_CLASS_A\r
-#define TAVOR_IF_CMD_ETIME_CLOSE_IB TAVOR_IF_CMD_ETIME_CLASS_A\r
-#define TAVOR_IF_CMD_ETIME_QUERY_HCA TAVOR_IF_CMD_ETIME_CLASS_C\r
-#define TAVOR_IF_CMD_ETIME_SET_IB TAVOR_IF_CMD_ETIME_CLASS_B\r
-\r
-#define TAVOR_IF_CMD_ETIME_SW2HW_MPT TAVOR_IF_CMD_ETIME_CLASS_B\r
-#define TAVOR_IF_CMD_ETIME_QUERY_MPT TAVOR_IF_CMD_ETIME_CLASS_A\r
-#define TAVOR_IF_CMD_ETIME_HW2SW_MPT TAVOR_IF_CMD_ETIME_CLASS_B\r
-#define TAVOR_IF_CMD_ETIME_READ_MTT TAVOR_IF_CMD_ETIME_CLASS_A\r
-#define TAVOR_IF_CMD_ETIME_WRITE_MTT TAVOR_IF_CMD_ETIME_CLASS_B\r
-#define TAVOR_IF_CMD_ETIME_SYNC_TPT TAVOR_IF_CMD_ETIME_CLASS_B\r
-\r
-#define TAVOR_IF_CMD_ETIME_MAP_EQ TAVOR_IF_CMD_ETIME_CLASS_B\r
-#define TAVOR_IF_CMD_ETIME_SW2HW_EQ TAVOR_IF_CMD_ETIME_CLASS_A\r
-#define TAVOR_IF_CMD_ETIME_HW2SW_EQ TAVOR_IF_CMD_ETIME_CLASS_A\r
-#define TAVOR_IF_CMD_ETIME_QUERY_EQ TAVOR_IF_CMD_ETIME_CLASS_A\r
-\r
-#define TAVOR_IF_CMD_ETIME_SW2HW_CQ TAVOR_IF_CMD_ETIME_CLASS_A\r
-#define TAVOR_IF_CMD_ETIME_HW2SW_CQ TAVOR_IF_CMD_ETIME_CLASS_A\r
-#define TAVOR_IF_CMD_ETIME_QUERY_CQ TAVOR_IF_CMD_ETIME_CLASS_A\r
-#define TAVOR_IF_CMD_ETIME_RESIZE_CQ TAVOR_IF_CMD_ETIME_CLASS_A\r
-\r
-#define TAVOR_IF_CMD_ETIME_RST2INIT_QPEE TAVOR_IF_CMD_ETIME_CLASS_C\r
-#define TAVOR_IF_CMD_ETIME_INIT2INIT_QPEE TAVOR_IF_CMD_ETIME_CLASS_C\r
-#define TAVOR_IF_CMD_ETIME_INIT2RTR_QPEE TAVOR_IF_CMD_ETIME_CLASS_C\r
-#define TAVOR_IF_CMD_ETIME_RTR2RTS_QPEE TAVOR_IF_CMD_ETIME_CLASS_C\r
-#define TAVOR_IF_CMD_ETIME_RTS2RTS_QPEE TAVOR_IF_CMD_ETIME_CLASS_C\r
-#define TAVOR_IF_CMD_ETIME_SQERR2RTS_QPEE TAVOR_IF_CMD_ETIME_CLASS_C\r
-#define TAVOR_IF_CMD_ETIME_2ERR_QPEE TAVOR_IF_CMD_ETIME_CLASS_C\r
-#define TAVOR_IF_CMD_ETIME_RTS2SQD TAVOR_IF_CMD_ETIME_CLASS_C\r
-#define TAVOR_IF_CMD_ETIME_SQD2RTS_QPEE TAVOR_IF_CMD_ETIME_CLASS_C\r
-#define TAVOR_IF_CMD_ETIME_ERR2RST_QPEE TAVOR_IF_CMD_ETIME_CLASS_C\r
-#define TAVOR_IF_CMD_ETIME_QUERY_QPEE TAVOR_IF_CMD_ETIME_CLASS_C\r
-\r
-#define TAVOR_IF_CMD_ETIME_CONF_SPECIAL_QP TAVOR_IF_CMD_ETIME_CLASS_B\r
-#define TAVOR_IF_CMD_ETIME_MAD_IFC TAVOR_IF_CMD_ETIME_CLASS_C\r
-\r
-#define TAVOR_IF_CMD_ETIME_READ_MGM TAVOR_IF_CMD_ETIME_CLASS_A\r
-#define TAVOR_IF_CMD_ETIME_WRITE_MGM TAVOR_IF_CMD_ETIME_CLASS_A\r
-#define TAVOR_IF_CMD_ETIME_MGID_HASH TAVOR_IF_CMD_ETIME_CLASS_A\r
-\r
-#define TAVOR_IF_CMD_ETIME_CONF_PM TAVOR_IF_CMD_ETIME_CLASS_C\r
-\r
-#define TAVOR_IF_CMD_ETIME_CONF_NTU TAVOR_IF_CMD_ETIME_CLASS_C\r
-#define TAVOR_IF_CMD_ETIME_QUERY_NTU TAVOR_IF_CMD_ETIME_CLASS_C\r
-\r
-#define TAVOR_IF_CMD_ETIME_DIAG_RPRT TAVOR_IF_CMD_ETIME_UNKNOWN_LAT\r
-#define TAVOR_IF_CMD_ETIME_QUERY_DEBUG_MSG TAVOR_IF_CMD_ETIME_UNKNOWN_LAT\r
-#define TAVOR_IF_CMD_ETIME_SET_DEBUG_MSG TAVOR_IF_CMD_ETIME_UNKNOWN_LAT\r
-\r
-\r
-//////////////////////// ADDED BY FW TEAM /////////////////////////\r
-#define TAVOR_IF_STRIDE_QPC_BIT 8\r
-#define TAVOR_IF_STRIDE_EEC_BIT 8\r
-#define TAVOR_IF_STRIDE_SRQC_BIT 5\r
-#define TAVOR_IF_STRIDE_CQC_BIT 6\r
-#define TAVOR_IF_STRIDE_EQC_BIT 6\r
-#define TAVOR_IF_STRIDE_MPT_BIT 6\r
-#define TAVOR_IF_STRIDE_MTT_BIT 3\r
-#define TAVOR_IF_STRIDE_EQPC_BIT 5\r
-#define TAVOR_IF_STRIDE_EEEC_BIT 5\r
-#define TAVOR_IF_STRIDE_APM_BIT 5\r
-#define TAVOR_IF_STRIDE_MCST_BIT 5\r
-#define TAVOR_IF_STRIDE_UARSCR_BIT 5\r
-\r
-#define TAVOR_IF_STRIDE_QPC (1<<TAVOR_IF_STRIDE_QPC_BIT)\r
-#define TAVOR_IF_STRIDE_EEC (1<<TAVOR_IF_STRIDE_EEC_BIT)\r
-#define TAVOR_IF_STRIDE_SRQC (1<<TAVOR_IF_STRIDE_SRQC_BIT)\r
-#define TAVOR_IF_STRIDE_CQC (1<<TAVOR_IF_STRIDE_CQC_BIT)\r
-#define TAVOR_IF_STRIDE_EQC (1<<TAVOR_IF_STRIDE_EQC_BIT)\r
-#define TAVOR_IF_STRIDE_MPT (1<<TAVOR_IF_STRIDE_MPT_BIT)\r
-#define TAVOR_IF_STRIDE_MTT (1<<TAVOR_IF_STRIDE_MTT_BIT)\r
-#define TAVOR_IF_STRIDE_EQPC (1<<TAVOR_IF_STRIDE_EQPC_BIT)\r
-#define TAVOR_IF_STRIDE_EEEC (1<<TAVOR_IF_STRIDE_EEEC_BIT)\r
-#define TAVOR_IF_STRIDE_APM (1<<TAVOR_IF_STRIDE_APM_BIT)\r
-#define TAVOR_IF_STRIDE_MCST (1<<TAVOR_IF_STRIDE_MCST_BIT)\r
-#define TAVOR_IF_STRIDE_UARSCR (1<<TAVOR_IF_STRIDE_UARSCR_BIT)\r
-\r
-#define TAVOR_IF_MPT_HW_STATUS_OFFSET 0\r
-#define TAVOR_IF_MPT_HW_START_ADDR_OFFSET 16\r
-#define TAVOR_IF_MPT_HW_LEN_OFFSET 24\r
-#define TAVOR_IF_MPT_HW_MEMKEY_OFFSET 8\r
-#define TAVOR_IF_MPT_HW_LKEY_OFFSET 32\r
-\r
-/* this constant is the flag masked on to the opcode modifier in TAVOR_IF_CMD_RTS2SQD_QPEE\r
- in order to request SQD notification */\r
-#define TAVOR_IF_SQD_EVENT_FLAG 0x80000000\r
-\r
-//////////////////////// FW TEAM /////////////////////////\r
-\r
-typedef enum tavor_if_cmd {\r
- /* initialization and general commands */\r
- TAVOR_IF_CMD_SYS_EN = 0x1,\r
- TAVOR_IF_CMD_SYS_DIS = 0x2,\r
- TAVOR_IF_CMD_MOD_STAT_CFG = 0x34,\r
- TAVOR_IF_CMD_QUERY_DEV_LIM = 0x3,\r
- TAVOR_IF_CMD_QUERY_FW = 0x4,\r
- TAVOR_IF_CMD_QUERY_DDR = 0x5,\r
- TAVOR_IF_CMD_QUERY_ADAPTER = 0x6,\r
- TAVOR_IF_CMD_INIT_HCA = 0x7,\r
- TAVOR_IF_CMD_CLOSE_HCA = 0x8,\r
- TAVOR_IF_CMD_INIT_IB = 0x9,\r
- TAVOR_IF_CMD_CLOSE_IB = 0xa,\r
- TAVOR_IF_CMD_QUERY_HCA = 0xb,\r
- TAVOR_IF_CMD_SET_IB = 0xc,\r
- TAVOR_IF_CMD_ACCESS_DDR = 0x2e,\r
-\r
- /* TPT commands */\r
- TAVOR_IF_CMD_SW2HW_MPT = 0xd,\r
- TAVOR_IF_CMD_QUERY_MPT = 0xe,\r
- TAVOR_IF_CMD_HW2SW_MPT = 0xf,\r
- TAVOR_IF_CMD_MODIFY_MPT = 0x39,\r
- TAVOR_IF_CMD_READ_MTT = 0x10,\r
- TAVOR_IF_CMD_WRITE_MTT = 0x11,\r
- TAVOR_IF_CMD_SYNC_TPT = 0x2f,\r
-\r
- /* EQ commands */\r
- TAVOR_IF_CMD_MAP_EQ = 0x12,\r
- TAVOR_IF_CMD_SW2HW_EQ = 0x13,\r
- TAVOR_IF_CMD_HW2SW_EQ = 0x14,\r
- TAVOR_IF_CMD_QUERY_EQ = 0x15,\r
-\r
- /* CQ commands */\r
- TAVOR_IF_CMD_SW2HW_CQ = 0x16,\r
- TAVOR_IF_CMD_HW2SW_CQ = 0x17,\r
- TAVOR_IF_CMD_QUERY_CQ = 0x18,\r
- TAVOR_IF_CMD_RESIZE_CQ= 0x2c,\r
-\r
- /* SRQ commands */\r
- TAVOR_IF_CMD_SW2HW_SRQ = 0x35,\r
- TAVOR_IF_CMD_HW2SW_SRQ = 0x36,\r
- TAVOR_IF_CMD_QUERY_SRQ = 0x37,\r
-\r
- /* QP/EE commands */\r
- TAVOR_IF_CMD_RST2INIT_QPEE = 0x19,\r
- TAVOR_IF_CMD_INIT2RTR_QPEE = 0x1a,\r
- TAVOR_IF_CMD_RTR2RTS_QPEE = 0x1b,\r
- TAVOR_IF_CMD_RTS2RTS_QPEE = 0x1c,\r
- TAVOR_IF_CMD_SQERR2RTS_QPEE = 0x1d,\r
- TAVOR_IF_CMD_2ERR_QPEE = 0x1e,\r
- TAVOR_IF_CMD_RTS2SQD_QPEE = 0x1f,\r
- TAVOR_IF_CMD_SQD2SQD_QPEE = 0x38,\r
- TAVOR_IF_CMD_SQD2RTS_QPEE = 0x20,\r
- TAVOR_IF_CMD_ERR2RST_QPEE = 0x21,\r
- TAVOR_IF_CMD_QUERY_QPEE = 0x22,\r
- TAVOR_IF_CMD_INIT2INIT_QPEE = 0x2d,\r
- TAVOR_IF_CMD_SUSPEND_QPEE = 0x32,\r
- TAVOR_IF_CMD_UNSUSPEND_QPEE = 0x33,\r
- /* special QPs and management commands */\r
- TAVOR_IF_CMD_CONF_SPECIAL_QP = 0x23,\r
- TAVOR_IF_CMD_MAD_IFC = 0x24,\r
-\r
- /* multicast commands */\r
- TAVOR_IF_CMD_READ_MGM = 0x25,\r
- TAVOR_IF_CMD_WRITE_MGM = 0x26,\r
- TAVOR_IF_CMD_MGID_HASH = 0x27,\r
-\r
- /* miscellaneous commands */\r
- // TAVOR_IF_CMD_CONF_PM = 0,\r
- TAVOR_IF_CMD_DIAG_RPRT = 0x30,\r
- TAVOR_IF_CMD_NOP = 0x31,\r
-\r
- /* debug commands */\r
- TAVOR_IF_CMD_QUERY_DEBUG_MSG = 0x2a,\r
- TAVOR_IF_CMD_SET_DEBUG_MSG = 0x2b,\r
- /* NTU commands */\r
- TAVOR_IF_CMD_CONF_NTU = 0x28,\r
- TAVOR_IF_CMD_QUERY_NTU = 0x29\r
-\r
-}\r
-tavor_if_cmd_t;\r
-\r
-\r
-typedef enum tavor_if_cmd_status {\r
- TAVOR_IF_CMD_STAT_OK = 0x00, /* command completed successfully */\r
- TAVOR_IF_CMD_STAT_INTERNAL_ERR = 0x01, /* Internal error (such as a bus error) occurred while processing command */\r
- TAVOR_IF_CMD_STAT_BAD_OP = 0x02, /* Operation/command not supported or opcode modifier not supported */\r
- TAVOR_IF_CMD_STAT_BAD_PARAM = 0x03, /* Parameter not supported or parameter out of range */\r
- TAVOR_IF_CMD_STAT_BAD_SYS_STATE = 0x04, /* System not enabled or bad system state */\r
- TAVOR_IF_CMD_STAT_BAD_RESOURCE = 0x05, /* Attempt to access reserved or unallocaterd resource */\r
- TAVOR_IF_CMD_STAT_RESOURCE_BUSY = 0x06, /* Requested resource is currently executing a command, or is otherwise busy */\r
- TAVOR_IF_CMD_STAT_DDR_MEM_ERR = 0x07, /* memory error */\r
- TAVOR_IF_CMD_STAT_EXCEED_LIM = 0x08, /* Required capability exceeds device limits */\r
- TAVOR_IF_CMD_STAT_BAD_RES_STATE = 0x09, /* Resource is not in the appropriate state or ownership */\r
- TAVOR_IF_CMD_STAT_BAD_INDEX = 0x0a, /* Index out of range */\r
- TAVOR_IF_CMD_STAT_BAD_NVMEM = 0x0b, /* FW image corrupted */\r
- TAVOR_IF_CMD_STAT_BAD_QPEE_STATE = 0x10, /* Attempt to modify a QP/EE which is not in the presumed state */\r
- TAVOR_IF_CMD_STAT_BAD_SEG_PARAM = 0x20, /* Bad segment parameters (Address/Size) */\r
- TAVOR_IF_CMD_STAT_REG_BOUND = 0x21, /* Memory Region has Memory Windows bound to */\r
- TAVOR_IF_CMD_STAT_BAD_PKT = 0x30, /* Bad management packet (silently discarded) */\r
- TAVOR_IF_CMD_STAT_BAD_SIZE = 0x40 /* More outstanding CQEs in CQ than new CQ size */\r
-}\r
-tavor_if_cmd_status_t;\r
-\r
-/* special QP types */\r
-typedef enum tavor_if_spqp {\r
- TAVOR_IF_SPQP_SMI = 0,\r
- TAVOR_IF_SPQP_GSI = 1,\r
- TAVOR_IF_SPQP_RAW_IPV6 = 2,\r
- TAVOR_IF_SPQP_RAW_ETHERTYPE = 3\r
-}\r
-tavor_if_spqp_t;\r
-\r
-/* optparammask of QP/EE transition commands. (Tavor-PRM 13.6.x) */\r
-enum tavor_if_qpee_optpar {\r
- TAVOR_IF_QPEE_OPTPAR_ALT_ADDR_PATH = 1 << 0,\r
- TAVOR_IF_QPEE_OPTPAR_RRE = 1 << 1,\r
- TAVOR_IF_QPEE_OPTPAR_RAE = 1 << 2,\r
- TAVOR_IF_QPEE_OPTPAR_REW = 1 << 3,\r
- TAVOR_IF_QPEE_OPTPAR_PKEY_INDEX = 1 << 4,\r
- TAVOR_IF_QPEE_OPTPAR_Q_KEY = 1 << 5,\r
- TAVOR_IF_QPEE_OPTPAR_RNR_TIMEOUT = 1 << 6,\r
- TAVOR_IF_QPEE_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,\r
- TAVOR_IF_QPEE_OPTPAR_SRA_MAX = 1 << 8,\r
- TAVOR_IF_QPEE_OPTPAR_RRA_MAX = 1 << 9,\r
- TAVOR_IF_QPEE_OPTPAR_PM_STATE = 1 << 10,\r
- TAVOR_IF_QPEE_OPTPAR_PORT_NUM = 1 << 11,\r
- TAVOR_IF_QPEE_OPTPAR_RETRY_COUNT = 1 << 12,\r
- TAVOR_IF_QPEE_OPTPAR_ALT_RNR_RETRY = 1 << 13,\r
- TAVOR_IF_QPEE_OPTPAR_ACK_TIMEOUT = 1 << 14,\r
- TAVOR_IF_QPEE_OPTPAR_RNR_RETRY = 1 << 15,\r
- TAVOR_IF_QPEE_OPTPAR_SCHED_QUEUE = 1 << 16,\r
- TAVOR_IF_QPEE_OPTPAR_ALL = (1 << 17) -1\r
-};\r
-\r
-/* NOPCODE field enumeration for doorbells and send-WQEs */\r
-typedef enum tavor_if_nopcode {\r
- TAVOR_IF_NOPCODE_NOP = 0, /* NOP */\r
- TAVOR_IF_NOPCODE_RDMAW = 8, /* RDMA-write */\r
- TAVOR_IF_NOPCODE_RDMAW_IMM = 9, /* RDMA-write w/immediate */\r
- TAVOR_IF_NOPCODE_SEND = 10, /* Send */\r
- TAVOR_IF_NOPCODE_SEND_IMM = 11, /* Send w/immediate */\r
- TAVOR_IF_NOPCODE_RDMAR = 16, /* RDMA-read */\r
- TAVOR_IF_NOPCODE_ATOM_CMPSWP = 17, /* Atomic Compare & Swap */\r
- TAVOR_IF_NOPCODE_ATOM_FTCHADD = 18, /* Atomic Fetch & Add */\r
- TAVOR_IF_NOPCODE_BIND_MEMWIN = 24 /* Bind memory window */\r
-}\r
-tavor_if_nopcode_t;\r
-\r
-\r
-/* event types */\r
-/*=============*/\r
-typedef enum tavor_if_eventt_num {\r
-/* Completion Events */\r
- TAVOR_IF_EV_TYPE_CQ_COMP = 0,\r
-/* IB - affiliated events */\r
- TAVOR_IF_EV_TYPE_PATH_MIG = 0x01,\r
- TAVOR_IF_EV_TYPE_COMM_EST = 0x02,\r
- TAVOR_IF_EV_TYPE_SEND_Q_DRAINED = 0x03,\r
- /* IB - affiliated errors CQ */\r
- TAVOR_IF_EV_TYPE_CQ_ERR = 0x04,\r
- TAVOR_IF_EV_TYPE_LOCAL_WQ_CATAS_ERR = 0x05,\r
- TAVOR_IF_EV_TYPE_LOCAL_EE_CATAS_ERR = 0x06,\r
- TAVOR_IF_EV_TYPE_PATH_MIG_FAIL = 0x07,\r
- TAVOR_IF_EV_TYPE_LOCAL_SRQ_CATAS_ERR = 0x12,\r
- TAVOR_IF_EV_TYPE_SRQ_QP_LAST_WQE_REACHED = 0x13,\r
- /* Unaffiliated errors */\r
- TAVOR_IF_EV_TYPE_LOCAL_CATAS_ERR = 0x08,\r
- TAVOR_IF_EV_TYPE_PORT_ERR = 0x09,\r
- TAVOR_IF_EV_TYPE_LOCAL_WQ_INVALID_REQ_ERR = 0x10,\r
- TAVOR_IF_EV_TYPE_LOCAL_WQ_ACCESS_VIOL_ERR = 0x11,\r
- /* Command Interface */\r
- TAVOR_IF_EV_TYPE_CMD_IF_COMP = 0x0A,\r
- /* Address translation */\r
- TAVOR_IF_EV_TYPE_WQE_DATA_BUFF_PAGE_FAULT = 0x0B,\r
- TAVOR_IF_EV_TYPE_UNSUPP_PAGE_FAULT = 0x0C,\r
- /* Performance Tuning Events */\r
- TAVOR_IF_EV_TYPE_PERF_MONITOR_EVENTS = 0x0D,\r
- /*Debug Events */\r
- TAVOR_IF_EV_TYPE_DEBUG = 0x0E,\r
- TAVOR_IF_EV_TYPE_OVERRUN = 0x0F\r
-} tavor_if_eventt_num_t;\r
-\r
-/* events sub-types */\r
-typedef enum tavor_if_debug_eventt_subtype {\r
- TAVOR_IF_RAW_DBG_INFO1 = 0xF0,\r
- TAVOR_IF_RAW_DBG_INFO2 = 0xF1,\r
- TAVOR_IF_RAW_DBG_INFO3 = 0xF2,\r
- TAVOR_IF_RAW_DBG_ERROR1 = 0xF4,\r
- TAVOR_IF_RAW_DBG_ERROR2 = 0xF5,\r
- TAVOR_IF_RAW_DBG_ERROR3 = 0xF6\r
-}tavor_if_debug_eventt_subtype_t;\r
-\r
-\r
-typedef enum tavor_if_port_event_subtype {\r
- TAVOR_IF_SUB_EV_PORT_DOWN = 0x1,\r
- TAVOR_IF_SUB_EV_PORT_UP = 0x4\r
-}tavor_if_port_event_subtype_t;\r
-\r
-/* event type mask */\r
-typedef enum tavor_if_eventt_mask_enum {\r
- TAVOR_IF_EV_MASK_CQ_COMP = 1<<TAVOR_IF_EV_TYPE_CQ_COMP,\r
- TAVOR_IF_EV_MASK_PATH_MIG = 1<<TAVOR_IF_EV_TYPE_PATH_MIG,\r
- TAVOR_IF_EV_MASK_COMM_EST = 1<<TAVOR_IF_EV_TYPE_COMM_EST,\r
- TAVOR_IF_EV_MASK_SEND_Q_DRAINED = 1<<TAVOR_IF_EV_TYPE_SEND_Q_DRAINED,\r
- TAVOR_IF_EV_MASK_CQ_ERR = 1<<TAVOR_IF_EV_TYPE_CQ_ERR,\r
- TAVOR_IF_EV_MASK_LOCAL_WQ_CATAS_ERR = 1<<TAVOR_IF_EV_TYPE_LOCAL_WQ_CATAS_ERR,\r
- TAVOR_IF_EV_MASK_LOCAL_EE_CATAS_ERR = 1<<TAVOR_IF_EV_TYPE_LOCAL_EE_CATAS_ERR,\r
- TAVOR_IF_EV_MASK_PATH_MIG_FAIL = 1<<TAVOR_IF_EV_TYPE_PATH_MIG_FAIL,\r
- TAVOR_IF_EV_MASK_LOCAL_CATAS_ERR = 1<<TAVOR_IF_EV_TYPE_LOCAL_CATAS_ERR,\r
- TAVOR_IF_EV_MASK_PORT_ERR = 1<<TAVOR_IF_EV_TYPE_PORT_ERR,\r
- TAVOR_IF_EV_MASK_CMD_IF_COMP = 1<<TAVOR_IF_EV_TYPE_CMD_IF_COMP,\r
- TAVOR_IF_EV_MASK_WQE_DATA_BUFF_PAGE_FAULT = 1<<TAVOR_IF_EV_TYPE_WQE_DATA_BUFF_PAGE_FAULT,\r
- TAVOR_IF_EV_MASK_UNSUPP_PAGE_FAULT = 1<<TAVOR_IF_EV_TYPE_UNSUPP_PAGE_FAULT,\r
- TAVOR_IF_EV_MASK_PERF_MONITOR_EVENTS = 1<<TAVOR_IF_EV_TYPE_PERF_MONITOR_EVENTS,\r
- TAVOR_IF_EV_MASK_DEBUG = 1<<TAVOR_IF_EV_TYPE_DEBUG,\r
- TAVOR_IF_EV_MASK_LOCAL_WQ_INVALID_REQ_ERR = 1<<TAVOR_IF_EV_TYPE_LOCAL_WQ_INVALID_REQ_ERR,\r
- TAVOR_IF_EV_MASK_LOCAL_WQ_ACCESS_VIOL_ERR = 1<<TAVOR_IF_EV_TYPE_LOCAL_WQ_ACCESS_VIOL_ERR,\r
- TAVOR_IF_EV_MASK_LOCAL_SRQ_CATAS_ERR = 1<<TAVOR_IF_EV_TYPE_LOCAL_SRQ_CATAS_ERR,\r
- TAVOR_IF_EV_MASK_SRQ_QP_LAST_WQE_REACHED = 1<<TAVOR_IF_EV_TYPE_SRQ_QP_LAST_WQE_REACHED\r
-} tavor_if_eventt_mask_enum_t;\r
-\r
-typedef u_int64_t tavor_if_eventt_mask_t; /* To be used with tavor_if_eventt_mask_enum_t */\r
-\r
-\r
-typedef enum tavor_if_ev_catas_error_type {\r
- TAVOR_IF_EV_CATAS_ERR_FW_INTERNAL_ERR = 0x00,\r
- TAVOR_IF_EV_CATAS_ERR_MISBEHAVED_UAR_PAGE = 0x02,\r
- TAVOR_IF_EV_CATAS_ERR_UPLINK_BUS_ERR = 0x03,\r
- TAVOR_IF_EV_CATAS_ERR_HCA_DDR_DATA_ERR = 0x04,\r
- TAVOR_IF_EV_CATAS_ERR_INTERNAL_PARITY_ERR = 0x05,\r
- TAVOR_IF_EV_CATAS_ERR_EQ_ERR = 0x06\r
-}tavor_if_ev_catas_error_type_t;\r
-\r
-#define TAVOR_IF_UNMAP_QP_BIT 0x80000000\r
-\r
-/* Completion status encoding (as given in CQE.immediate[31:24]) */\r
-typedef enum tavor_if_comp_status {\r
- TAVOR_IF_COMP_STATUS_SUCCESS = 0x0,\r
- TAVOR_IF_COMP_STATUS_ERR_LCL_LEN = 0x1,\r
- TAVOR_IF_COMP_STATUS_ERR_LCL_QP_OP = 0x2,\r
- TAVOR_IF_COMP_STATUS_ERR_LCL_EE_OP = 0x3,\r
- TAVOR_IF_COMP_STATUS_ERR_LCL_PROT = 0x4,\r
- TAVOR_IF_COMP_STATUS_ERR_FLUSH = 0x5,\r
- TAVOR_IF_COMP_STATUS_ERR_MWIN_BIND = 0x6,\r
- TAVOR_IF_COMP_STATUS_ERR_BAD_RESP = 0x10,\r
- TAVOR_IF_COMP_STATUS_ERR_LCL_ACCS = 0x11,\r
- TAVOR_IF_COMP_STATUS_ERR_RMT_INVAL_REQ = 0x12,\r
- TAVOR_IF_COMP_STATUS_ERR_RMT_ACCSS = 0x13,\r
- TAVOR_IF_COMP_STATUS_ERR_RMT_OP = 0x14,\r
- TAVOR_IF_COMP_STATUS_ERR_TRANS_RETRY_EX = 0x15,\r
- TAVOR_IF_COMP_STATUS_ERR_RNR_RETRY_EX = 0x16,\r
- TAVOR_IF_COMP_STATUS_ERR_LCL_RDD_VIOL = 0x20,\r
- TAVOR_IF_COMP_STATUS_ERR_RMT_INVAL_REQ_RD = 0x21,\r
- TAVOR_IF_COMP_STATUS_ERR_RMT_ABORT = 0x22,\r
- TAVOR_IF_COMP_STATUS_ERR_INVAL_EEC_NUM = 0x23,\r
- TAVOR_IF_COMP_STATUS_ERR_INVAL_EEC_STT = 0x24\r
-} tavor_if_comp_status_t;\r
-\r
-\r
-/* different enums for error events */\r
-typedef enum tavor_if_cq_err_synd {\r
- TAVOR_IF_CQ_OVERRUN = 1,\r
- TAVOR_IF_CQ_ACCSS_VIOL_ERR = 2\r
-}tavor_if_cq_err_synd_t;\r
-\r
-\r
-typedef enum tavor_if_port_change_synd {\r
- TAVOR_IF_PORT_LOG_DN_PHY_DN = 0,\r
- TAVOR_IF_PORT_LOG_DN_PHY_UP = 1,\r
- TAVOR_IF_PORT_LOG_UP_PHY_UP = 2\r
-}tavor_if_port_change_synd_t;\r
-\r
-typedef enum tavor_if_addr_trans_fault_type{\r
- TAVOR_IF_FALT_REGION_INVALID =0,\r
- TAVOR_IF_FALT_REGION_PD_MIS =1,\r
- TAVOR_IF_FALT_REGION_WRT_ACC_VIOL =2,\r
- TAVOR_IF_FALT_REGION_ATOMIC_ACC_VIOL =3,\r
- /*4-7 - reserved */\r
- TAVOR_IF_FALT_PAGE_NOT_PRESENT =8,\r
- /* RESERVED 9 */\r
- TAVOR_IF_FALT_PAGE_WRT_ACC_VIOL =10,\r
- /* RESERVED 11-13 */\r
- TAVOR_IF_FALT_UNSUPP_NON_PRESENT_PAGE_FLT =14,\r
- TAVOR_IF_FALT_UNSUPP_WRT_ACC_VIOL =15\r
-}tavor_if_addr_trans_fault_type_t;\r
-\r
-typedef enum tavor_if_perf_mntr_num {\r
- TAVOR_IF_MNTR_NUM_SQPC = 1,\r
- TAVOR_IF_MNTR_NUM_RQPC = 2,\r
- TAVOR_IF_MNTR_NUM_CQC = 3,\r
- TAVOR_IF_MNTR_NUM_RKEY = 4,\r
- TAVOR_IF_MNTR_NUM_TLB = 5,\r
- TAVOR_IF_MNTR_NUM_PORT_0 = 6,\r
- TAVOR_IF_MNTR_NUM_PORT_1 = 7\r
-} tavor_if_perf_mntr_num_t;\r
-\r
-/* CQ-command doorbell command encoding */\r
-typedef enum tavor_if_uar_cq_cmd {\r
- TAVOR_IF_UAR_CQ_INC_CI =1,/* Increment CQ's consumer index */\r
- TAVOR_IF_UAR_CQ_NOTIF_NEXT_COMP =2,/* Request notif. for next comp. event (param=consumer index)*/\r
- TAVOR_IF_UAR_CQ_NOTIF_SOLIC_COMP=3,/* Req. notif. for next solicited comp.(param=consumer index)*/\r
- TAVOR_IF_UAR_CQ_SET_CI =4,/* Set CQ's consumer index to value given in param. */\r
- TAVOR_IF_UAR_CQ_NOTIF_NCOMP=5 /* Request notif. when N CQEs are outstanding (PI-CI>=N=cq_param)*/\r
-} tavor_if_uar_cq_cmd_t;\r
-\r
-/* EQ-command doorbell command encoding */\r
-typedef enum tavor_if_uar_eq_cmd {\r
- TAVOR_IF_UAR_EQ_INC_CI =1,/* Increment EQ's consumer index */\r
- TAVOR_IF_UAR_EQ_INT_ARM =2,/* Request interrupt for next event (next EQE posted)*/\r
- TAVOR_IF_UAR_EQ_DISARM_CQ =3,/* Disarm CQ request notification state machine (param= CQ num)*/\r
- TAVOR_IF_UAR_EQ_SET_CI =4,/* Set EQ's consumer index to value given in param. */\r
- TAVOR_IF_UAR_EQ_INT_ALWAYS_ARM =5 /* interrupts are generated for every EQE generated */\r
-} tavor_if_uar_eq_cmd_t;\r
-\r
-/* QP-state encoding */\r
-typedef enum tavor_if_qp_state {\r
- TAVOR_IF_QP_STATE_RESET = 0,\r
- TAVOR_IF_QP_STATE_INIT = 1,\r
- TAVOR_IF_QP_STATE_RTR = 2,\r
- TAVOR_IF_QP_STATE_RTS = 3,\r
- TAVOR_IF_QP_STATE_SQER = 4,\r
- TAVOR_IF_QP_STATE_SQD = 5,\r
- TAVOR_IF_QP_STATE_ERR = 6,\r
- TAVOR_IF_QP_STATE_DRAINING = 7,\r
- TAVOR_IF_QP_STATE_BUSY = 8,\r
- TAVOR_IF_QP_STATE_SUSPENDED = 9\r
-} tavor_if_qp_state_t;\r
-\r
-/* Old CQ state encoding (for STS,STC).\r
- * Kept here for informational purposes.\r
- *\r
- TAVOR_IF_CQ_STATE_DISARMED = 0,\r
- TAVOR_IF_CQ_STATE_ARMED = 1,\r
- TAVOR_IF_CQ_STATE_FIRED = 2\r
- *\r
- */\r
-\r
-/* CQ state encoding */\r
-typedef enum tavor_if_cq_state {\r
- TAVOR_IF_CQ_STATE_DISARMED = 0x0,\r
- TAVOR_IF_CQ_STATE_ARMED = 0x1,\r
- TAVOR_IF_CQ_STATE_ARMED_SOL = 0x4,\r
- TAVOR_IF_CQ_STATE_FIRED = 0xA\r
-} tavor_if_cq_state_t;\r
-\r
-/* EQ state encoding */\r
-\r
-typedef enum tavor_if_eq_state {\r
- TAVOR_IF_EQ_STATE_ARMED = 0x1,\r
- TAVOR_IF_EQ_STATE_FIRED = 0x2,\r
- TAVOR_IF_EQ_STATE_ALWAYS_ARMED = 0x3\r
-} tavor_if_eq_state_t;\r
-\r
-/* Miscellaneous Values: limits, tunable paramaters, etc. */\r
-enum\r
-{\r
- TAVOR_IF_HOST_BIGENDIAN = 1, /* host is big endian*/\r
- TAVOR_NUM_RESERVED_PDS = 0, /* Obselete: will be moved to internal FW define once QUERY_DEV_LIM is implemented in full in driver */\r
- TAVOR_NUM_RESERVED_EQS = 0, /* Obselete: will be moved to internal FW define once QUERY_DEV_LIM is implemented in full in driver */\r
- TAVOR_NUM_RESERVED_RDDS = 0, /* Obselete: will be moved to internal FW define once QUERY_DEV_LIM is implemented in full in driver */\r
- TAVOR_IF_HOST_LTLENDIAN = 0, /* host is little endian*/\r
-\r
- /* Limits on QP in UD mode: max message and MTU */\r
- TAVOR_LOG2_MAX_MTU = 11,\r
-\r
- TAVOR_IF_MAX_MPT_PAGE_SIZE = 31 /* (log2) Maximum page size for an MPT */\r
- /*sharon: 23.3.2003: changed from 32 at the req of tziporet */\r
-};\r
-\r
-typedef enum tavor_sys_en_syn\r
-{\r
- TAVOR_SYS_EN_SYN_OK = 0x0, /* No syndrome: When command succeeds */\r
- TAVOR_SYS_EN_SYN_SPD = 0x1, /* SPD error (e. g. checksum error,\r
- no response, error while reading) */\r
- TAVOR_SYS_EN_SYN_DIMM = 0x2, /* DIMM out of bounds (e. g. DIMM rows\r
- number is not between 7 and 14,\r
- DIMM type is not 2) */\r
- TAVOR_SYS_EN_SYN_CONF = 0x3, /* DIMM conflict (e.g. mix of registered and\r
- unbuffered DIMMs, CAS latency conflict) */\r
- TAVOR_SYS_EN_SYN_CALB = 0x4, /* Calibration error */\r
- TAVOR_SYS_EN_SYN_TSIZ = 0x5, /* Total size out of bounds:\r
- E.g. total memory size exceeds the\r
- maximum supported value. */\r
- TAVOR_SYS_EN_SYN_DCHK = 0x6 /*dimm check error occured*/\r
-} tavor_sys_en_syn_t;\r
-\r
-typedef enum tavor_diag_rprt\r
-{\r
- TAVOR_DIAG_RPRT_QUERY_ERR = 0x2, /* Query transport and CI error counters */\r
- TAVOR_DIAG_RPRT_RESET_ERR = 0x3, /* Query and reset error counters */\r
- TAVOR_DIAG_RPRT_QUERY_PERF = 0x4, /* Query performance counters */\r
- TAVOR_DIAG_RPRT_RESET_PERF = 0x5, /* Query and reset performance counters */\r
- TAVOR_DIAG_RPRT_QUERY_MISC = 0x6, /* Query MISC counters */\r
- TAVOR_DIAG_RPRT_RESET_MISC = 0x7, /* Query and reset MISC counters */\r
-} tavor_diag_rprt_t;\r
-\r
-#define CMDIF_OUTPRM_ALIGN 16 /* alignment requirement for out params */\r
-\r
-#endif /* H_TAVOR_IF_DEFS_H */\r
\r
-#\r
-# DO NOT EDIT THIS FILE!!! Edit .\sources. if you want to add a new source\r
-# file to this component. This file merely indirects to the real make file\r
-# that is shared by all the driver components of the Windows NT DDK\r
-#\r
-\r
-!INCLUDE $(NTMAKEENV)\makefile.def\r
-TARGETNAME=vapi\r
-TARGETPATH=..\..\..\..\bin\user\obj$(BUILD_ALT_DIR)\r
-TARGETTYPE=LIBRARY\r
-\r
-SOURCES= \\r
- mtl_common_ul_sources.c \\r
- mosal_ul_sources.c \\r
- mpga_ul_sources.c \\r
- hh_ul_sources.c \\r
- thhul_ul_sources.c \\r
- vapi_common_ul_sources.c\r
-\r
-MT_HOME=..\r
-OS_DEP_HOME=$(MT_HOME)\mlxsys\os_dep\win\\r
-MOSAL_HOME=$(MT_HOME)\mlxsys\mosal\os_dep\win\r
-THH_HOME=$(MT_HOME)\hca\hcahal\tavor\r
-\r
-INCLUDES= \\r
- ..\..\user; \\r
- $(MT_HOME)\mlxsys\tools; \\r
- $(MT_HOME)\tavor_arch_db; \\r
- $(MT_HOME)\Hca\verbs; \\r
- $(MT_HOME)\Hca\verbs\common; \\r
- $(MT_HOME)\mlxsys\mpga\os_dep\win; \\r
- $(MT_HOME)\mlxsys\mpga; \\r
- $(MT_HOME)\mlxsys\mtl_types; \\r
- $(MT_HOME)\mlxsys\mtl_types\win; \\r
- $(MT_HOME)\mlxsys\mtl_types\win\win; \\r
- $(MT_HOME)\mlxsys\mtl_common\os_dep\win; \\r
- $(MT_HOME)\mlxsys\mtl_common; \\r
- $(MT_HOME)\mlxsys\mosal; \\r
- $(MT_HOME)\mlxsys\mosal\os_dep\win; \\r
- $(MT_HOME)\Hca\hcahal; \\r
- $(THH_HOME); \\r
- $(THH_HOME)\os_dep\win; \\r
- $(THH_HOME)\thhul_hob; \\r
- $(THH_HOME)\thhul_pdm; \\r
- $(THH_HOME)\thhul_cqm; \\r
- $(THH_HOME)\thhul_qpm; \\r
- $(THH_HOME)\thhul_srqm; \\r
- $(THH_HOME)\thhul_mwm; \\r
- $(THH_HOME)\thh_hob; \\r
- $(THH_HOME)\thh_srqm; \\r
- $(THH_HOME)\thh_qpm; \\r
- $(THH_HOME)\thh_cqm; \\r
- $(THH_HOME)\util; \\r
- $(THH_HOME)\uar; \\r
- $(THH_HOME)\uldm; \\r
- $(THH_HOME)\udavm; \\r
- $(THH_HOME)\eventp; \\r
- $(THH_HOME)\mrwm; \\r
- $(THH_HOME)\mcgm; \\r
- $(THH_HOME)\ddrmm; \\r
- $(THH_HOME)\cmdif; \\r
- $(MT_HOME)\mlxsys\os_dep\win\tdriver; \\r
- ..\..\..\..\inc; \\r
- ..\..\..\..\inc\user; \\r
- ..\..\..\..\core\al; \\r
- .; \r
-\r
-C_DEFINES=$(C_DEFINES) -DUMT23108_EXPORTS -DIVAPI_THH -DMT_LITTLE_ENDIAN -D__WIN__ -D__MSC__ -D__LITTLE_ENDIAN -D__DLL_EXPORTS__ -Di386 -DCL_NO_TRACK_MEM\r
-\r
-MSC_WARNING_LEVEL= /W3 # /Wp64 /ZI /Gz /TP /Gm /EHsc /RTC1 /MTd\r
-#include "..\Hca\hcahal\hh.c"\r
-#include "..\Hca\hcahal\hh.h"\r
-#include "..\Hca\hcahal\hh_common.c"\r
-#include "..\Hca\hcahal\hh_common.h"\r
-#include "..\Hca\hcahal\hh_init.h"\r
\r
-#include "..\mlxsys\mosal\os_dep\win\mosalu_driver.c"\r
-#include "..\mlxsys\mosal\os_dep\win\mosalu_mem.c"\r
-#include "..\mlxsys\mosal\os_dep\win\mosalu_sync.c"\r
-#include "..\mlxsys\mosal\os_dep\win\mosalu_thread.c"\r
-#include "..\mlxsys\mpga\mpga.c"\r
-#include "..\mlxsys\mpga\packet_append.c"\r
-#include "..\mlxsys\mpga\internal_functions.c"\r
-#include "..\mlxsys\mpga\packet_utilities.c"\r
-#include "..\mlxsys\mpga\nMPGA_packet_append.c"\r
-#include "..\mlxsys\mpga\nMPGA.c"\r
-\r
\r
-\r
-#include "..\mlxsys\mtl_common\mtl_common.c"\r
-#include "..\Hca\hcahal\tavor\thhul_cqm\thhul_cqm.c"\r
-#include "..\Hca\hcahal\tavor\thhul_srqm\thhul_srqm.c"\r
-#include "..\Hca\hcahal\tavor\thhul_hob\thhul_hob.c"\r
-#include "..\Hca\hcahal\tavor\thhul_qpm\thhul_qpm.c"\r
-#include "..\Hca\hcahal\tavor\thhul_pdm\thhul_pdm.c"\r
-#include "..\Hca\hcahal\tavor\thhul_mwm\thhul_mwm.c"\r
-#include "..\Hca\hcahal\tavor\uar\uar.c"\r
-#include "..\Hca\hcahal\tavor\udavm\udavm.c"\r
-#include "..\Hca\hcahal\tavor\util\epool.c"\r
-#include "..\Hca\hcahal\tavor\util\tlog2.c"\r
\r
-#include "..\Hca\verbs\common\vapi_common.c"\r
-#include "..\Hca\verbs\common\vip_array.c"\r
-#include "..\Hca\verbs\common\vip_cirq.c"\r
-#include "..\Hca\verbs\common\vip_hash.c"\r
projects / ~shefty / rdma-win.git / commitdiff