]> git.openfabrics.org - ~emulex/infiniband.git/commitdiff
drm/nv40/fb: enable z compression
authorBen Skeggs <bskeggs@redhat.com>
Thu, 11 Oct 2012 05:13:10 +0000 (15:13 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Wed, 28 Nov 2012 23:56:33 +0000 (09:56 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/core/include/subdev/fb.h
drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c
drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c
drivers/gpu/drm/nouveau/core/subdev/fb/nv47.c
drivers/gpu/drm/nouveau/core/subdev/fb/nv49.c

index aa13f6b2d8ebfabfc06d0cb091b7a6b12954a586..eb5cbbf7d4441a47c4e4b73b91b4839529732cd5 100644 (file)
@@ -151,6 +151,9 @@ int  nv30_fb_init(struct nouveau_object *);
 void nv30_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
                       u32 pitch, u32 flags, struct nouveau_fb_tile *);
 
+void nv40_fb_tile_comp(struct nouveau_fb *, int i, u32 size, u32 flags,
+                      struct nouveau_fb_tile *);
+
 int  nv41_fb_vram_init(struct nouveau_fb *);
 int  nv41_fb_init(struct nouveau_object *);
 void nv41_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
index 37c5e4c2c3f7854cbb469a2ba96a23f638493e75..fe7e29841aa5e101f1f5208204cf95cf3f7d2698 100644 (file)
@@ -41,15 +41,26 @@ nv40_fb_vram_init(struct nouveau_fb *pfb)
        case 0x00000300: pfb->ram.type = NV_MEM_TYPE_DDR2; break;
        }
 
-       pfb->ram.size = nv_rd32(pfb, 0x10020c) & 0xff000000;
+       pfb->ram.size  =  nv_rd32(pfb, 0x10020c) & 0xff000000;
+       pfb->ram.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
        return nv_rd32(pfb, 0x100320);
 }
 
-static void
+void
 nv40_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
                  struct nouveau_fb_tile *tile)
 {
-       tile->zcomp = 0x00000000;
+       u32 tiles = DIV_ROUND_UP(size, 0x80);
+       u32 tags  = round_up(tiles / pfb->ram.parts, 0x100);
+       if ( (flags & 2) &&
+           !nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) {
+               tile->zcomp  = 0x24000000; /* Z24S8_SPLIT */
+               tile->zcomp |= ((tile->tag->offset           ) >> 8);
+               tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13;
+#ifdef __BIG_ENDIAN
+               tile->zcomp |= 0x40000000;
+#endif
+       }
 }
 
 static int
index cc2cff65fcc9afb31e84f82087e4e30142932ee9..e9e5a08c41a14617d0b8c8e3c810e8639c3a088d 100644 (file)
@@ -41,7 +41,8 @@ nv41_fb_vram_init(struct nouveau_fb *pfb)
        if (pfb474 & 0x00000001)
                pfb->ram.type = NV_MEM_TYPE_DDR1;
 
-       pfb->ram.size = nv_rd32(pfb, 0x10020c) & 0xff000000;
+       pfb->ram.size =   nv_rd32(pfb, 0x10020c) & 0xff000000;
+       pfb->ram.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
        return nv_rd32(pfb, 0x100320);
 }
 
@@ -86,6 +87,7 @@ nv41_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
        priv->base.ram.init = nv41_fb_vram_init;
        priv->base.tile.regions = 12;
        priv->base.tile.init = nv30_fb_tile_init;
+       priv->base.tile.comp = nv40_fb_tile_comp;
        priv->base.tile.fini = nv20_fb_tile_fini;
        priv->base.tile.prog = nv41_fb_tile_prog;
        return nouveau_fb_preinit(&priv->base);
index a2ca3c8e4007d054d33c3ecf85ef44b1fc1c2f88..818bba35b3684d48f2c1825320ab19eb77324836 100644 (file)
@@ -47,6 +47,7 @@ nv47_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
        priv->base.ram.init = nv41_fb_vram_init;
        priv->base.tile.regions = 15;
        priv->base.tile.init = nv30_fb_tile_init;
+       priv->base.tile.comp = nv40_fb_tile_comp;
        priv->base.tile.fini = nv20_fb_tile_fini;
        priv->base.tile.prog = nv41_fb_tile_prog;
        return nouveau_fb_preinit(&priv->base);
index aaec1e3e1d98a701d39ae6d543bf253eef8ebecd..84a31af16ab48e67fea78966c9c61b9ab3c05419 100644 (file)
@@ -42,7 +42,8 @@ nv49_fb_vram_init(struct nouveau_fb *pfb)
        case 0x00000003: break;
        }
 
-       pfb->ram.size = nv_rd32(pfb, 0x10020c) & 0xff000000;
+       pfb->ram.size =   nv_rd32(pfb, 0x10020c) & 0xff000000;
+       pfb->ram.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
        return nv_rd32(pfb, 0x100320);
 }
 
@@ -63,6 +64,7 @@ nv49_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
        priv->base.ram.init = nv49_fb_vram_init;
        priv->base.tile.regions = 15;
        priv->base.tile.init = nv30_fb_tile_init;
+       priv->base.tile.comp = nv40_fb_tile_comp;
        priv->base.tile.fini = nv20_fb_tile_fini;
        priv->base.tile.prog = nv41_fb_tile_prog;