MIPS: Probe for and report hardware virtualization support.

The presence of the MIPS Virtualization Application-Specific Extension
is indicated by CP0_Config3[23].  Probe for this and report it in
/proc/cpuinfo.

Signed-off-by: David Daney <david.daney@cavium.com>
Patchwork: http://patchwork.linux-mips.org/patch/4904/
Signed-off-by: John Crispin <blogic@openwrt.org>

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 00171cddb6d5a77fcf0a6e2ca1b7f01db63a70a4..c6f64ef0681eeff318e191ac725f662f27148efc 100644 (file)
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -263,4 +263,8 @@
 #define cpu_has_perf_cntr_intr_bit     (cpu_data[0].options & MIPS_CPU_PCI)
 #endif
 
+#ifndef cpu_has_vz
+#define cpu_has_vz             (cpu_data[0].ases & MIPS_ASE_VZ)
+#endif
+
 #endif /* __ASM_CPU_FEATURES_H */

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 2de2fee16cc434fadde7c51d60b9dc1f92f4f748..4dff3378d96ff77d93b3b0499c9ae5deaff201eb 100644 (file)
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -336,6 +336,6 @@ enum cpu_type_enum {
 #define MIPS_ASE_DSP           0x00000010 /* Signal Processing ASE */
 #define MIPS_ASE_MIPSMT                0x00000020 /* CPU supports MIPS MT */
 #define MIPS_ASE_DSP2P         0x00000040 /* Signal Processing ASE Rev 2 */
-
+#define MIPS_ASE_VZ            0x00000080 /* Virtualization ASE */
 
 #endif /* _ASM_CPU_H */

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 9f47cda632abe594a5f49a38ed497caa5622dd03..5df4cda4991af8df1ba60dd08544d4b9d332f7ef 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -596,6 +596,7 @@
 #define MIPS_CONF3_RXI         (_ULCAST_(1) << 12)
 #define MIPS_CONF3_ULRI                (_ULCAST_(1) << 13)
 #define MIPS_CONF3_ISA         (_ULCAST_(3) << 14)
+#define MIPS_CONF3_VZ          (_ULCAST_(1) << 23)
 
 #define MIPS_CONF4_MMUSIZEEXT  (_ULCAST_(255) << 0)
 #define MIPS_CONF4_MMUEXTDEF   (_ULCAST_(3) << 14)

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index ba169022fe1dc920b4c82e209fa51aa2915b06a3..0c69d1d14080b8408a80381528f3b67c44eb55d1 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -442,6 +442,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
                c->options |= MIPS_CPU_ULRI;
        if (config3 & MIPS_CONF3_ISA)
                c->options |= MIPS_CPU_MICROMIPS;
+       if (config3 & MIPS_CONF3_VZ)
+               c->ases |= MIPS_ASE_VZ;
 
        return config3 & MIPS_CONF_M;
 }

diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 239ae03f33302e3fe364de3be14fa8567cfd4889..453d55699fefea323ddc4a3a0ef886c21aca2b4c 100644 (file)
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -74,6 +74,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
        if (cpu_has_dsp2)       seq_printf(m, "%s", " dsp2");
        if (cpu_has_mipsmt)     seq_printf(m, "%s", " mt");
        if (cpu_has_mmips)      seq_printf(m, "%s", " micromips");
+       if (cpu_has_vz)         seq_printf(m, "%s", " vz");
        seq_printf(m, "\n");
 
        seq_printf(m, "shadow register sets\t: %d\n",