if(fullPrint){\r
printf("\t\tmax_msg_sz=0x%x (Max message size)\n", portPtr->max_msg_size);\r
printf("\t\tcapability_mask=TBD\n");\r
- printf("\t\tmax_vl_num=0x%x (Maximum number of VL supported by this port)\n", portPtr->max_vls);\r
+ printf("\t\tmax_vl_num=0x%x (Maximum number of VL supported by this port)\n", portPtr->max_vls);\r
printf("\t\tbad_pkey_counter=0x%x (Bad PKey counter)\n", portPtr->pkey_ctr);\r
printf("\t\tqkey_viol_counter=0x%x (QKey violation counter)\n", portPtr->qkey_ctr);\r
- printf("\t\tsm_sl=0x%x (IB_SL to be used in communication with subnet manager)\n", portPtr->sm_sl);\r
+ printf("\t\tsm_sl=0x%x (IB_SL to be used in communication with subnet manager)\n", portPtr->sm_sl);\r
printf("\t\tpkey_tbl_len=0x%x (Current size of pkey table)\n", portPtr->num_pkeys);\r
printf("\t\tgid_tbl_len=0x%x (Current size of GID table)\n", portPtr->num_gids);\r
printf("\t\tsubnet_timeout=0x%x (Subnet Timeout for this port (see PortInfo))\n", portPtr->subnet_timeout);\r
\r
\r
\r
-void vstat_print_ca_attr(ib_ca_attr_t* ca_attr, BOOLEAN fullPrint){\r
+void vstat_print_ca_attr(int idx, ib_ca_attr_t* ca_attr, BOOLEAN fullPrint){\r
int i;\r
\r
- printf("\thca_id=%s\n", ca_attr->dev_id==0x5a44?"InfiniHost0":"TBD"); //TODO: all HCAs and hadle multi HCAs \r
- printf("\tpci_location={BUS=TBD,DEV/FUNC=TBD}\n");\r
+ printf("\thca_idx=%d\n",idx);\r
+ printf("\tpci_location={BUS=NA,DEV/FUNC=NA}\n");\r
printf("\tvendor_id=0x%04x\n", ca_attr->vend_id);\r
printf("\tvendor_part_id=0x%04x\n", ca_attr->dev_id);\r
printf("\thw_ver=0x%x\n", ca_attr->revision); //TODO: ???\r
- printf("\tfw_ver=TBD\n");\r
- printf("\tPSID=TBD\n");\r
+ printf("\tfw_ver=NA\n");\r
+ printf("\tPSID=NA\n");\r
if(fullPrint){\r
- printf("\tnum_phys_ports = TBD\n");\r
+ printf("\tnum_phys_ports = %d\n",ca_attr->num_ports);\r
printf("\tmax_num_qp = 0x%x (Maximum Number of QPs supported)\n", ca_attr->max_qps);\r
- printf("\tmax_qp_ous_wr = 0x%x (Maximum Number of oustanding WR on any WQ)\n", ca_attr->max_wrs);\r
- printf("\tflags== TBD\n");\r
+ printf("\tmax_qp_ous_wr = 0x%x (Maximum Number of oustanding WR on any WQ)\n", ca_attr->max_wrs);\r
printf("\tmax_num_sg_ent = 0x%x (Max num of scatter/gather entries for WQE other than RD)\n", ca_attr->max_sges);\r
- printf("\tmax_num_sg_ent_rd = 0x%x (Max num of scatter/gather entries for RD WQE)\n", ca_attr->max_rd_sges);\r
- printf("\tmax_num_srq = TBD (Maximum Number of SRQs supported)\n");\r
- printf("\tmax_wqe_per_srq = TBD (Maximum Number of oustanding WR on any SRQ)\n");\r
- printf("\tmax_srq_sentries = TBD (Maximum Number of scatter entries for SRQ WQE)\n");\r
- printf("\tsrq_resize_supported = TBD (SRQ resize supported)\n");\r
- printf("\tmax_num_cq = 0x%x (Max num of supported CQs)\n", ca_attr->max_cqs);\r
+ printf("\tmax_num_sg_ent_rd = 0x%x (Max num of scatter/gather entries for RD WQE)\n", ca_attr->max_rd_sges);\r
+ printf("\tmax_num_srq = 0 (Maximum Number of SRQs supported)\n");\r
+ printf("\tmax_wqe_per_srq = 0 (Maximum Number of oustanding WR on any SRQ)\n");\r
+ printf("\tmax_srq_sentries = 0 (Maximum Number of scatter entries for SRQ WQE)\n");\r
+ printf("\tsrq_resize_supported = 0 (SRQ resize supported)\n");\r
+ printf("\tmax_num_cq = 0x%x (Max num of supported CQs)\n", ca_attr->max_cqs);\r
printf("\tmax_num_ent_cq = 0x%x (Max num of supported entries per CQ)\n", ca_attr->max_cqes);\r
- printf("\tmax_num_mr = 0x%x (Maximum number of memory region supported)\n", ca_attr->init_regions);\r
+ printf("\tmax_num_mr = 0x%x (Maximum number of memory region supported)\n", ca_attr->init_regions);\r
printf("\tmax_mr_size = 0x%x (Largest contigous block of memory region in bytes)\n", ca_attr->init_region_size);\r
- printf("\tmax_pd_num = 0x%x (Maximum number of protection domains supported)\n", ca_attr->max_pds);\r
- printf("\tpage_size_cap = TBD (Largest page size supported by this HCA)\n");\r
- printf("\tmax_pkeys = TBD (Maximum number of partitions supported)\n");\r
+ printf("\tmax_pd_num = 0x%x (Maximum number of protection domains supported)\n", ca_attr->max_pds);\r
+ printf("\tpage_size_cap = 0x%x (Largest page size supported by this HCA)\n",ca_attr->p_page_size[ca_attr->num_page_sizes-1]);\r
printGUID(ca_attr->ca_guid);\r
- printf("\tlocal_ca_ack_delay = 0x%x (Log2 4.096usec Max. RX to ACK or NAK delay)\n", ca_attr->local_ack_delay);\r
- printf("\tmax_qp_ous_rd_atom = TBD (Maximum number of oust. RDMA read/atomic as target)\n");\r
- printf("\tmax_ee_ous_rd_atom = TBD (EE Maximum number of outs. RDMA read/atomic as target)\n");\r
- printf("\tmax_res_rd_atom = TBD (Max. Num. of resources used for RDMA read/atomic as target)\n");\r
- printf("\tmax_qp_init_rd_atom = TBD (Max. Num. of outs. RDMA read/atomic as initiator)\n");\r
- printf("\tmax_ee_init_rd_atom = TBD (EE Max. Num. of outs. RDMA read/atomic as initiator)\n");\r
- printf("\tatomic_cap = TBD (Level of Atomicity supported)\n");\r
+ printf("\tlocal_ca_ack_delay = 0x%x (Log2 4.096usec Max. RX to ACK or NAK delay)\n", ca_attr->local_ack_delay);\r
+ printf("\tmax_qp_ous_rd_atom = 0x%x (Maximum number of oust. RDMA read/atomic as target)\n",ca_attr->max_qp_resp_res);\r
+ printf("\tmax_ee_ous_rd_atom = 0 (EE Maximum number of outs. RDMA read/atomic as target)\n");\r
+ printf("\tmax_res_rd_atom = 0x%x (Max. Num. of resources used for RDMA read/atomic as target)\n",ca_attr->max_resp_res);\r
+ printf("\tmax_qp_init_rd_atom = 0x%x (Max. Num. of outs. RDMA read/atomic as initiator)\n",ca_attr->max_qp_init_depth);\r
+ printf("\tmax_ee_init_rd_atom = 0 (EE Max. Num. of outs. RDMA read/atomic as initiator)\n");\r
+ printf("\tatomic_cap = %s (Level of Atomicity supported)\n",ca_attr->atomicity == IB_ATOMIC_GLOBAL?"GLOBAL":\r
+ ca_attr->atomicity == IB_ATOMIC_LOCAL?"LOCAL":"NORMAL");\r
printf("\tmax_ee_num = 0x0 (Maximum number of EEC supported)\n");\r
printf("\tmax_rdd_num = 0x0 (Maximum number of IB_RDD supported)\n");\r
- printf("\tmax_mw_num = 0x%x (Maximum Number of memory windows supported)\n", ca_attr->init_windows);\r
- printf("\tmax_raw_ipv6_qp = 0x%x (Maximum number of Raw IPV6 QPs supported)\n", ca_attr->max_ipv6_qps);\r
- printf("\tmax_raw_ethy_qp = 0x%x (Maximum number of Raw Ethertypes QPs supported)\n", ca_attr->max_ether_qps);\r
+ printf("\tmax_mw_num = 0x%x (Maximum Number of memory windows supported)\n", ca_attr->init_windows);\r
+ printf("\tmax_raw_ipv6_qp = 0x%x (Maximum number of Raw IPV6 QPs supported)\n", ca_attr->max_ipv6_qps);\r
+ printf("\tmax_raw_ethy_qp = 0x%x (Maximum number of Raw Ethertypes QPs supported)\n", ca_attr->max_ether_qps);\r
printf("\tmax_mcast_grp_num = 0x%x (Maximum Number of multicast groups)\n", ca_attr->max_mcast_grps);\r
- printf("\tmax_mcast_qp_attach_num = 0x%x(Maximum number of QP per multicast group)\n", ca_attr->max_qps_per_mcast_grp);\r
- printf("\tmax_total_mcast_qp_attach_num = 0x%x(Maximum number of QPs which can be attached to a mcast grp)\n", ca_attr->max_mcast_qps);\r
- printf("\tmax_ah_num = 0x%x (Maximum number of address handles)\n", ca_attr->max_addr_handles);\r
- printf("\tmax_num_fmr = TBD (maximum number FMRs)\n");\r
- printf("\tmax_num_map_per_fmr = TBD (Maximum number of (re)maps per FMR before an unmap operation in required)\n");\r
+ printf("\tmax_mcast_qp_attach_num = 0x%x (Maximum number of QP per multicast group)\n", ca_attr->max_qps_per_mcast_grp);\r
+ printf("\tmax_ah_num = 0x%x (Maximum number of address handles)\n", ca_attr->max_addr_handles);\r
+ printf("\tmax_num_fmr = 0 (Maximum number FMRs)\n");\r
+ printf("\tmax_num_map_per_fmr = 0 (Maximum number of (re)maps per FMR before an unmap operation in required)\n");\r
}else{\r
printf("\tnum_phys_ports=%d\n", ca_attr->num_ports);\r
}\r
size_t guid_count;\r
ib_net64_t *ca_guid_array;\r
ib_ca_attr_t *vstat_ca_attr;\r
- uintn_t i;\r
+ size_t i;\r
ib_ca_handle_t h_ca = NULL;\r
uint32_t bsize;\r
ib_port_attr_mod_t port_attr_mod;\r
\r
/* Print_ca_attributes */\r
\r
- vstat_print_ca_attr(vstat_ca_attr, fullPrint);\r
+ vstat_print_ca_attr((int)i,vstat_ca_attr, fullPrint);\r
\r
\r
/* Free the memory */\r