ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority

ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority

This is needed so that the IPU framebuffer scanout cannot be
starved by VPU or GPU activity.
Some boards like the SabreLite and SabreSD seem to set this in
the DCD already, but the documented register reset values do not
contain the necessary settings.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>